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Merge git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-nvram
[linux-2.6-block.git] / drivers / net / ucc_geth.c
CommitLineData
ce973b14 1/*
4e19b5c1 2 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
ce973b14
LY		 3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
18a8e864 5 * Li Yang <leoli@freescale.com>
ce973b14
LY		 6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
ce973b14
LY		 10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/slab.h>
19#include <linux/stddef.h>
20#include <linux/interrupt.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/spinlock.h>
25#include <linux/mm.h>
ce973b14
LY		 26#include <linux/dma-mapping.h>
27#include <linux/fsl_devices.h>
ce973b14 28#include <linux/mii.h>
728de4c9 29#include <linux/phy.h>
df19b6b0 30#include <linux/workqueue.h>
55b6c8e9 31#include <linux/of_platform.h>
ce973b14
LY		 32
33#include <asm/uaccess.h>
34#include <asm/irq.h>
35#include <asm/io.h>
36#include <asm/immap_qe.h>
37#include <asm/qe.h>
38#include <asm/ucc.h>
39#include <asm/ucc_fast.h>
40
41#include "ucc_geth.h"
728de4c9 42#include "ucc_geth_mii.h"
ce973b14
LY		 43
44#undef DEBUG
45
ce973b14
LY		 46#define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
48
49#define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51#define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53#define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55#define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
57
58#ifdef UGETH_VERBOSE_DEBUG
59#define ugeth_vdbg ugeth_dbg
60#else
61#define ugeth_vdbg(fmt, args...) do { } while (0)
62#endif /* UGETH_VERBOSE_DEBUG */
890de95e 63#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
ce973b14 64
88a15f2e 65
ce973b14
LY		 66static DEFINE_SPINLOCK(ugeth_lock);
67
890de95e
LY		 68static struct {
69 u32 msg_enable;
70} debug = { -1 };
71
72module_param_named(debug, debug.msg_enable, int, 0);
73MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
74
18a8e864 75static struct ucc_geth_info ugeth_primary_info = {
ce973b14
LY		 76 .uf_info = {
77 .bd_mem_part = MEM_PART_SYSTEM,
78 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
79 .max_rx_buf_length = 1536,
728de4c9 80 /* adjusted at startup if max-speed 1000 */
ce973b14
LY		 81 .urfs = UCC_GETH_URFS_INIT,
82 .urfet = UCC_GETH_URFET_INIT,
83 .urfset = UCC_GETH_URFSET_INIT,
84 .utfs = UCC_GETH_UTFS_INIT,
85 .utfet = UCC_GETH_UTFET_INIT,
86 .utftt = UCC_GETH_UTFTT_INIT,
ce973b14
LY		 87 .ufpt = 256,
88 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
89 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
90 .tenc = UCC_FAST_TX_ENCODING_NRZ,
91 .renc = UCC_FAST_RX_ENCODING_NRZ,
92 .tcrc = UCC_FAST_16_BIT_CRC,
93 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
94 },
95 .numQueuesTx = 1,
96 .numQueuesRx = 1,
97 .extendedFilteringChainPointer = ((uint32_t) NULL),
98 .typeorlen = 3072 /*1536 */ ,
99 .nonBackToBackIfgPart1 = 0x40,
100 .nonBackToBackIfgPart2 = 0x60,
101 .miminumInterFrameGapEnforcement = 0x50,
102 .backToBackInterFrameGap = 0x60,
103 .mblinterval = 128,
104 .nortsrbytetime = 5,
105 .fracsiz = 1,
106 .strictpriorityq = 0xff,
107 .altBebTruncation = 0xa,
108 .excessDefer = 1,
109 .maxRetransmission = 0xf,
110 .collisionWindow = 0x37,
111 .receiveFlowControl = 1,
ac421852 112 .transmitFlowControl = 1,
ce973b14
LY		 113 .maxGroupAddrInHash = 4,
114 .maxIndAddrInHash = 4,
115 .prel = 7,
116 .maxFrameLength = 1518,
117 .minFrameLength = 64,
118 .maxD1Length = 1520,
119 .maxD2Length = 1520,
120 .vlantype = 0x8100,
121 .ecamptr = ((uint32_t) NULL),
122 .eventRegMask = UCCE_OTHER,
123 .pausePeriod = 0xf000,
124 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
125 .bdRingLenTx = {
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN},
134
135 .bdRingLenRx = {
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN},
144
145 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
146 .largestexternallookupkeysize =
147 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
ac421852
LY		 148 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
ce973b14
LY		 151 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
152 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
153 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
154 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
155 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
ffea31ed
JT		 156 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
157 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
ce973b14
LY		 158 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
159 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160};
161
18a8e864 162static struct ucc_geth_info ugeth_info[8];
ce973b14
LY		 163
164#ifdef DEBUG
165static void mem_disp(u8 *addr, int size)
166{
167 u8 *i;
168 int size16Aling = (size >> 4) << 4;
169 int size4Aling = (size >> 2) << 2;
170 int notAlign = 0;
171 if (size % 16)
172 notAlign = 1;
173
174 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
175 printk("0x%08x: %08x %08x %08x %08x\r\n",
176 (u32) i,
177 *((u32 *) (i)),
178 *((u32 *) (i + 4)),
179 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
180 if (notAlign == 1)
181 printk("0x%08x: ", (u32) i);
182 for (; (u32) i < (u32) addr + size4Aling; i += 4)
183 printk("%08x ", *((u32 *) (i)));
184 for (; (u32) i < (u32) addr + size; i++)
185 printk("%02x", *((u8 *) (i)));
186 if (notAlign == 1)
187 printk("\r\n");
188}
189#endif /* DEBUG */
190
ce973b14
LY		 191static struct list_head *dequeue(struct list_head *lh)
192{
193 unsigned long flags;
194
1083cfe1 195 spin_lock_irqsave(&ugeth_lock, flags);
ce973b14
LY		 196 if (!list_empty(lh)) {
197 struct list_head *node = lh->next;
198 list_del(node);
1083cfe1 199 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 200 return node;
201 } else {
1083cfe1 202 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 203 return NULL;
204 }
205}
206
6fee40e9
AF		 207static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
208 u8 __iomem *bd)
ce973b14
LY		 209{
210 struct sk_buff *skb = NULL;
211
212 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
213 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
214
215 if (skb == NULL)
216 return NULL;
217
218 /* We need the data buffer to be aligned properly. We will reserve
219 * as many bytes as needed to align the data properly
220 */
221 skb_reserve(skb,
222 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
223 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
224 1)));
225
226 skb->dev = ugeth->dev;
227
6fee40e9 228 out_be32(&((struct qe_bd __iomem *)bd)->buf,
7f80202b 229 dma_map_single(&ugeth->dev->dev,
ce973b14
LY		 230 skb->data,
231 ugeth->ug_info->uf_info.max_rx_buf_length +
232 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
233 DMA_FROM_DEVICE));
234
6fee40e9
AF		 235 out_be32((u32 __iomem *)bd,
236 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
ce973b14
LY		 237
238 return skb;
239}
240
18a8e864 241static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
ce973b14 242{
6fee40e9 243 u8 __iomem *bd;
ce973b14
LY		 244 u32 bd_status;
245 struct sk_buff *skb;
246 int i;
247
248 bd = ugeth->p_rx_bd_ring[rxQ];
249 i = 0;
250
251 do {
6fee40e9 252 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 253 skb = get_new_skb(ugeth, bd);
254
255 if (!skb) /* If can not allocate data buffer,
256 abort. Cleanup will be elsewhere */
257 return -ENOMEM;
258
259 ugeth->rx_skbuff[rxQ][i] = skb;
260
261 /* advance the BD pointer */
18a8e864 262 bd += sizeof(struct qe_bd);
ce973b14
LY		 263 i++;
264 } while (!(bd_status & R_W));
265
266 return 0;
267}
268
18a8e864 269static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 270 u32 *p_start,
ce973b14
LY		 271 u8 num_entries,
272 u32 thread_size,
273 u32 thread_alignment,
18a8e864 274 enum qe_risc_allocation risc,
ce973b14
LY		 275 int skip_page_for_first_entry)
276{
277 u32 init_enet_offset;
278 u8 i;
279 int snum;
280
281 for (i = 0; i < num_entries; i++) {
282 if ((snum = qe_get_snum()) < 0) {
890de95e
LY		 283 if (netif_msg_ifup(ugeth))
284 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
ce973b14
LY		 285 return snum;
286 }
287 if ((i == 0) && skip_page_for_first_entry)
288 /* First entry of Rx does not have page */
289 init_enet_offset = 0;
290 else {
291 init_enet_offset =
292 qe_muram_alloc(thread_size, thread_alignment);
4c35630c 293 if (IS_ERR_VALUE(init_enet_offset)) {
890de95e
LY		 294 if (netif_msg_ifup(ugeth))
295 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
ce973b14
LY		 296 qe_put_snum((u8) snum);
297 return -ENOMEM;
298 }
299 }
300 *(p_start++) =
301 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
302 | risc;
303 }
304
305 return 0;
306}
307
18a8e864 308static int return_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 309 u32 *p_start,
ce973b14 310 u8 num_entries,
18a8e864 311 enum qe_risc_allocation risc,
ce973b14
LY		 312 int skip_page_for_first_entry)
313{
314 u32 init_enet_offset;
315 u8 i;
316 int snum;
317
318 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 319 u32 val = *p_start;
320
ce973b14
LY		 321 /* Check that this entry was actually valid --
322 needed in case failed in allocations */
6fee40e9 323 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 324 snum =
6fee40e9 325 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 326 ENET_INIT_PARAM_SNUM_SHIFT;
327 qe_put_snum((u8) snum);
328 if (!((i == 0) && skip_page_for_first_entry)) {
329 /* First entry of Rx does not have page */
330 init_enet_offset =
6fee40e9 331 (val & ENET_INIT_PARAM_PTR_MASK);
ce973b14
LY		 332 qe_muram_free(init_enet_offset);
333 }
6fee40e9 334 *p_start++ = 0;
ce973b14
LY		 335 }
336 }
337
338 return 0;
339}
340
341#ifdef DEBUG
18a8e864 342static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 343 u32 __iomem *p_start,
ce973b14
LY		 344 u8 num_entries,
345 u32 thread_size,
18a8e864 346 enum qe_risc_allocation risc,
ce973b14
LY		 347 int skip_page_for_first_entry)
348{
349 u32 init_enet_offset;
350 u8 i;
351 int snum;
352
353 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 354 u32 val = in_be32(p_start);
355
ce973b14
LY		 356 /* Check that this entry was actually valid --
357 needed in case failed in allocations */
6fee40e9 358 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 359 snum =
6fee40e9 360 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 361 ENET_INIT_PARAM_SNUM_SHIFT;
362 qe_put_snum((u8) snum);
363 if (!((i == 0) && skip_page_for_first_entry)) {
364 /* First entry of Rx does not have page */
365 init_enet_offset =
366 (in_be32(p_start) &
367 ENET_INIT_PARAM_PTR_MASK);
368 ugeth_info("Init enet entry %d:", i);
369 ugeth_info("Base address: 0x%08x",
370 (u32)
371 qe_muram_addr(init_enet_offset));
372 mem_disp(qe_muram_addr(init_enet_offset),
373 thread_size);
374 }
375 p_start++;
376 }
377 }
378
379 return 0;
380}
381#endif
382
18a8e864 383static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
ce973b14
LY		 384{
385 kfree(enet_addr_cont);
386}
387
df19b6b0 388static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
18a8e864
LY		 389{
390 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
391 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
392 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
393}
394
18a8e864 395static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
ce973b14 396{
6fee40e9 397 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 398
399 if (!(paddr_num < NUM_OF_PADDRS)) {
b39d66a8 400 ugeth_warn("%s: Illagel paddr_num.", __func__);
ce973b14
LY		 401 return -EINVAL;
402 }
403
404 p_82xx_addr_filt =
6fee40e9 405 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 406 addressfiltering;
407
408 /* Writing address ff.ff.ff.ff.ff.ff disables address
409 recognition for this register */
410 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
411 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
412 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
413
414 return 0;
415}
416
18a8e864
LY		 417static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
418 u8 *p_enet_addr)
ce973b14 419{
6fee40e9 420 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 421 u32 cecr_subblock;
422
423 p_82xx_addr_filt =
6fee40e9 424 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 425 addressfiltering;
426
427 cecr_subblock =
428 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
429
430 /* Ethernet frames are defined in Little Endian mode,
431 therefor to insert */
432 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
18a8e864
LY		 433
434 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
ce973b14
LY		 435
436 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
18a8e864 437 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 438}
439
440#ifdef CONFIG_UGETH_MAGIC_PACKET
18a8e864 441static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
ce973b14 442{
18a8e864 443 struct ucc_fast_private *uccf;
6fee40e9 444 struct ucc_geth __iomem *ug_regs;
ce973b14
LY		 445 u32 maccfg2, uccm;
446
447 uccf = ugeth->uccf;
448 ug_regs = ugeth->ug_regs;
449
450 /* Enable interrupts for magic packet detection */
451 uccm = in_be32(uccf->p_uccm);
452 uccm |= UCCE_MPD;
453 out_be32(uccf->p_uccm, uccm);
454
455 /* Enable magic packet detection */
456 maccfg2 = in_be32(&ug_regs->maccfg2);
457 maccfg2 |= MACCFG2_MPE;
458 out_be32(&ug_regs->maccfg2, maccfg2);
459}
460
18a8e864 461static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
ce973b14 462{
18a8e864 463 struct ucc_fast_private *uccf;
6fee40e9 464 struct ucc_geth __iomem *ug_regs;
ce973b14
LY		 465 u32 maccfg2, uccm;
466
467 uccf = ugeth->uccf;
468 ug_regs = ugeth->ug_regs;
469
470 /* Disable interrupts for magic packet detection */
471 uccm = in_be32(uccf->p_uccm);
472 uccm &= ~UCCE_MPD;
473 out_be32(uccf->p_uccm, uccm);
474
475 /* Disable magic packet detection */
476 maccfg2 = in_be32(&ug_regs->maccfg2);
477 maccfg2 &= ~MACCFG2_MPE;
478 out_be32(&ug_regs->maccfg2, maccfg2);
479}
480#endif /* MAGIC_PACKET */
481
18a8e864 482static inline int compare_addr(u8 **addr1, u8 **addr2)
ce973b14
LY		 483{
484 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
485}
486
487#ifdef DEBUG
18a8e864
LY		 488static void get_statistics(struct ucc_geth_private *ugeth,
489 struct ucc_geth_tx_firmware_statistics *
ce973b14 490 tx_firmware_statistics,
18a8e864 491 struct ucc_geth_rx_firmware_statistics *
ce973b14 492 rx_firmware_statistics,
18a8e864 493 struct ucc_geth_hardware_statistics *hardware_statistics)
ce973b14 494{
6fee40e9
AF		 495 struct ucc_fast __iomem *uf_regs;
496 struct ucc_geth __iomem *ug_regs;
18a8e864
LY		 497 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
498 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
ce973b14
LY		 499
500 ug_regs = ugeth->ug_regs;
6fee40e9 501 uf_regs = (struct ucc_fast __iomem *) ug_regs;
ce973b14
LY		 502 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
503 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
504
505 /* Tx firmware only if user handed pointer and driver actually
506 gathers Tx firmware statistics */
507 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
508 tx_firmware_statistics->sicoltx =
509 in_be32(&p_tx_fw_statistics_pram->sicoltx);
510 tx_firmware_statistics->mulcoltx =
511 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
512 tx_firmware_statistics->latecoltxfr =
513 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
514 tx_firmware_statistics->frabortduecol =
515 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
516 tx_firmware_statistics->frlostinmactxer =
517 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
518 tx_firmware_statistics->carriersenseertx =
519 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
520 tx_firmware_statistics->frtxok =
521 in_be32(&p_tx_fw_statistics_pram->frtxok);
522 tx_firmware_statistics->txfrexcessivedefer =
523 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
524 tx_firmware_statistics->txpkts256 =
525 in_be32(&p_tx_fw_statistics_pram->txpkts256);
526 tx_firmware_statistics->txpkts512 =
527 in_be32(&p_tx_fw_statistics_pram->txpkts512);
528 tx_firmware_statistics->txpkts1024 =
529 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
530 tx_firmware_statistics->txpktsjumbo =
531 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
532 }
533
534 /* Rx firmware only if user handed pointer and driver actually
535 * gathers Rx firmware statistics */
536 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
537 int i;
538 rx_firmware_statistics->frrxfcser =
539 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
540 rx_firmware_statistics->fraligner =
541 in_be32(&p_rx_fw_statistics_pram->fraligner);
542 rx_firmware_statistics->inrangelenrxer =
543 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
544 rx_firmware_statistics->outrangelenrxer =
545 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
546 rx_firmware_statistics->frtoolong =
547 in_be32(&p_rx_fw_statistics_pram->frtoolong);
548 rx_firmware_statistics->runt =
549 in_be32(&p_rx_fw_statistics_pram->runt);
550 rx_firmware_statistics->verylongevent =
551 in_be32(&p_rx_fw_statistics_pram->verylongevent);
552 rx_firmware_statistics->symbolerror =
553 in_be32(&p_rx_fw_statistics_pram->symbolerror);
554 rx_firmware_statistics->dropbsy =
555 in_be32(&p_rx_fw_statistics_pram->dropbsy);
556 for (i = 0; i < 0x8; i++)
557 rx_firmware_statistics->res0[i] =
558 p_rx_fw_statistics_pram->res0[i];
559 rx_firmware_statistics->mismatchdrop =
560 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
561 rx_firmware_statistics->underpkts =
562 in_be32(&p_rx_fw_statistics_pram->underpkts);
563 rx_firmware_statistics->pkts256 =
564 in_be32(&p_rx_fw_statistics_pram->pkts256);
565 rx_firmware_statistics->pkts512 =
566 in_be32(&p_rx_fw_statistics_pram->pkts512);
567 rx_firmware_statistics->pkts1024 =
568 in_be32(&p_rx_fw_statistics_pram->pkts1024);
569 rx_firmware_statistics->pktsjumbo =
570 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
571 rx_firmware_statistics->frlossinmacer =
572 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
573 rx_firmware_statistics->pausefr =
574 in_be32(&p_rx_fw_statistics_pram->pausefr);
575 for (i = 0; i < 0x4; i++)
576 rx_firmware_statistics->res1[i] =
577 p_rx_fw_statistics_pram->res1[i];
578 rx_firmware_statistics->removevlan =
579 in_be32(&p_rx_fw_statistics_pram->removevlan);
580 rx_firmware_statistics->replacevlan =
581 in_be32(&p_rx_fw_statistics_pram->replacevlan);
582 rx_firmware_statistics->insertvlan =
583 in_be32(&p_rx_fw_statistics_pram->insertvlan);
584 }
585
586 /* Hardware only if user handed pointer and driver actually
587 gathers hardware statistics */
588 if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
589 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
590 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
591 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
592 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
593 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
594 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
595 hardware_statistics->txok = in_be32(&ug_regs->txok);
596 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
597 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
598 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
599 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
600 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
601 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
602 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
603 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
604 }
605}
606
18a8e864 607static void dump_bds(struct ucc_geth_private *ugeth)
ce973b14
LY		 608{
609 int i;
610 int length;
611
612 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
613 if (ugeth->p_tx_bd_ring[i]) {
614 length =
615 (ugeth->ug_info->bdRingLenTx[i] *
18a8e864 616 sizeof(struct qe_bd));
ce973b14
LY		 617 ugeth_info("TX BDs[%d]", i);
618 mem_disp(ugeth->p_tx_bd_ring[i], length);
619 }
620 }
621 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
622 if (ugeth->p_rx_bd_ring[i]) {
623 length =
624 (ugeth->ug_info->bdRingLenRx[i] *
18a8e864 625 sizeof(struct qe_bd));
ce973b14
LY		 626 ugeth_info("RX BDs[%d]", i);
627 mem_disp(ugeth->p_rx_bd_ring[i], length);
628 }
629 }
630}
631
18a8e864 632static void dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 633{
634 int i;
635
636 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
637 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
638
639 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
640 (u32) & ugeth->ug_regs->maccfg1,
641 in_be32(&ugeth->ug_regs->maccfg1));
642 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
643 (u32) & ugeth->ug_regs->maccfg2,
644 in_be32(&ugeth->ug_regs->maccfg2));
645 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
646 (u32) & ugeth->ug_regs->ipgifg,
647 in_be32(&ugeth->ug_regs->ipgifg));
648 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
649 (u32) & ugeth->ug_regs->hafdup,
650 in_be32(&ugeth->ug_regs->hafdup));
ce973b14
LY		 651 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
652 (u32) & ugeth->ug_regs->ifctl,
653 in_be32(&ugeth->ug_regs->ifctl));
654 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
655 (u32) & ugeth->ug_regs->ifstat,
656 in_be32(&ugeth->ug_regs->ifstat));
657 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
658 (u32) & ugeth->ug_regs->macstnaddr1,
659 in_be32(&ugeth->ug_regs->macstnaddr1));
660 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
661 (u32) & ugeth->ug_regs->macstnaddr2,
662 in_be32(&ugeth->ug_regs->macstnaddr2));
663 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
664 (u32) & ugeth->ug_regs->uempr,
665 in_be32(&ugeth->ug_regs->uempr));
666 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
667 (u32) & ugeth->ug_regs->utbipar,
668 in_be32(&ugeth->ug_regs->utbipar));
669 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
670 (u32) & ugeth->ug_regs->uescr,
671 in_be16(&ugeth->ug_regs->uescr));
672 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
673 (u32) & ugeth->ug_regs->tx64,
674 in_be32(&ugeth->ug_regs->tx64));
675 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
676 (u32) & ugeth->ug_regs->tx127,
677 in_be32(&ugeth->ug_regs->tx127));
678 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
679 (u32) & ugeth->ug_regs->tx255,
680 in_be32(&ugeth->ug_regs->tx255));
681 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
682 (u32) & ugeth->ug_regs->rx64,
683 in_be32(&ugeth->ug_regs->rx64));
684 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
685 (u32) & ugeth->ug_regs->rx127,
686 in_be32(&ugeth->ug_regs->rx127));
687 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
688 (u32) & ugeth->ug_regs->rx255,
689 in_be32(&ugeth->ug_regs->rx255));
690 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
691 (u32) & ugeth->ug_regs->txok,
692 in_be32(&ugeth->ug_regs->txok));
693 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
694 (u32) & ugeth->ug_regs->txcf,
695 in_be16(&ugeth->ug_regs->txcf));
696 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
697 (u32) & ugeth->ug_regs->tmca,
698 in_be32(&ugeth->ug_regs->tmca));
699 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
700 (u32) & ugeth->ug_regs->tbca,
701 in_be32(&ugeth->ug_regs->tbca));
702 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
703 (u32) & ugeth->ug_regs->rxfok,
704 in_be32(&ugeth->ug_regs->rxfok));
705 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
706 (u32) & ugeth->ug_regs->rxbok,
707 in_be32(&ugeth->ug_regs->rxbok));
708 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
709 (u32) & ugeth->ug_regs->rbyt,
710 in_be32(&ugeth->ug_regs->rbyt));
711 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
712 (u32) & ugeth->ug_regs->rmca,
713 in_be32(&ugeth->ug_regs->rmca));
714 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
715 (u32) & ugeth->ug_regs->rbca,
716 in_be32(&ugeth->ug_regs->rbca));
717 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
718 (u32) & ugeth->ug_regs->scar,
719 in_be32(&ugeth->ug_regs->scar));
720 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
721 (u32) & ugeth->ug_regs->scam,
722 in_be32(&ugeth->ug_regs->scam));
723
724 if (ugeth->p_thread_data_tx) {
725 int numThreadsTxNumerical;
726 switch (ugeth->ug_info->numThreadsTx) {
727 case UCC_GETH_NUM_OF_THREADS_1:
728 numThreadsTxNumerical = 1;
729 break;
730 case UCC_GETH_NUM_OF_THREADS_2:
731 numThreadsTxNumerical = 2;
732 break;
733 case UCC_GETH_NUM_OF_THREADS_4:
734 numThreadsTxNumerical = 4;
735 break;
736 case UCC_GETH_NUM_OF_THREADS_6:
737 numThreadsTxNumerical = 6;
738 break;
739 case UCC_GETH_NUM_OF_THREADS_8:
740 numThreadsTxNumerical = 8;
741 break;
742 default:
743 numThreadsTxNumerical = 0;
744 break;
745 }
746
747 ugeth_info("Thread data TXs:");
748 ugeth_info("Base address: 0x%08x",
749 (u32) ugeth->p_thread_data_tx);
750 for (i = 0; i < numThreadsTxNumerical; i++) {
751 ugeth_info("Thread data TX[%d]:", i);
752 ugeth_info("Base address: 0x%08x",
753 (u32) & ugeth->p_thread_data_tx[i]);
754 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
18a8e864 755 sizeof(struct ucc_geth_thread_data_tx));
ce973b14
LY		 756 }
757 }
758 if (ugeth->p_thread_data_rx) {
759 int numThreadsRxNumerical;
760 switch (ugeth->ug_info->numThreadsRx) {
761 case UCC_GETH_NUM_OF_THREADS_1:
762 numThreadsRxNumerical = 1;
763 break;
764 case UCC_GETH_NUM_OF_THREADS_2:
765 numThreadsRxNumerical = 2;
766 break;
767 case UCC_GETH_NUM_OF_THREADS_4:
768 numThreadsRxNumerical = 4;
769 break;
770 case UCC_GETH_NUM_OF_THREADS_6:
771 numThreadsRxNumerical = 6;
772 break;
773 case UCC_GETH_NUM_OF_THREADS_8:
774 numThreadsRxNumerical = 8;
775 break;
776 default:
777 numThreadsRxNumerical = 0;
778 break;
779 }
780
781 ugeth_info("Thread data RX:");
782 ugeth_info("Base address: 0x%08x",
783 (u32) ugeth->p_thread_data_rx);
784 for (i = 0; i < numThreadsRxNumerical; i++) {
785 ugeth_info("Thread data RX[%d]:", i);
786 ugeth_info("Base address: 0x%08x",
787 (u32) & ugeth->p_thread_data_rx[i]);
788 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
18a8e864 789 sizeof(struct ucc_geth_thread_data_rx));
ce973b14
LY		 790 }
791 }
792 if (ugeth->p_exf_glbl_param) {
793 ugeth_info("EXF global param:");
794 ugeth_info("Base address: 0x%08x",
795 (u32) ugeth->p_exf_glbl_param);
796 mem_disp((u8 *) ugeth->p_exf_glbl_param,
797 sizeof(*ugeth->p_exf_glbl_param));
798 }
799 if (ugeth->p_tx_glbl_pram) {
800 ugeth_info("TX global param:");
801 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
802 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
803 (u32) & ugeth->p_tx_glbl_pram->temoder,
804 in_be16(&ugeth->p_tx_glbl_pram->temoder));
805 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
806 (u32) & ugeth->p_tx_glbl_pram->sqptr,
807 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
808 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
809 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
810 in_be32(&ugeth->p_tx_glbl_pram->
811 schedulerbasepointer));
812 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
813 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
814 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
815 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
816 (u32) & ugeth->p_tx_glbl_pram->tstate,
817 in_be32(&ugeth->p_tx_glbl_pram->tstate));
818 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
819 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
820 ugeth->p_tx_glbl_pram->iphoffset[0]);
821 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
822 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
823 ugeth->p_tx_glbl_pram->iphoffset[1]);
824 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
825 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
826 ugeth->p_tx_glbl_pram->iphoffset[2]);
827 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
828 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
829 ugeth->p_tx_glbl_pram->iphoffset[3]);
830 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
831 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
832 ugeth->p_tx_glbl_pram->iphoffset[4]);
833 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
834 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
835 ugeth->p_tx_glbl_pram->iphoffset[5]);
836 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
837 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
838 ugeth->p_tx_glbl_pram->iphoffset[6]);
839 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
840 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
841 ugeth->p_tx_glbl_pram->iphoffset[7]);
842 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
843 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
844 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
845 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
846 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
847 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
848 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
849 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
850 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
851 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
852 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
853 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
854 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
855 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
856 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
857 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
858 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
859 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
860 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
861 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
862 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
863 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
864 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
865 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
866 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
867 (u32) & ugeth->p_tx_glbl_pram->tqptr,
868 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
869 }
870 if (ugeth->p_rx_glbl_pram) {
871 ugeth_info("RX global param:");
872 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
873 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
874 (u32) & ugeth->p_rx_glbl_pram->remoder,
875 in_be32(&ugeth->p_rx_glbl_pram->remoder));
876 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
877 (u32) & ugeth->p_rx_glbl_pram->rqptr,
878 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
879 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
880 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
881 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
882 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
883 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
884 ugeth->p_rx_glbl_pram->rxgstpack);
885 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
886 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
887 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
888 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
889 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
890 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
891 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
892 (u32) & ugeth->p_rx_glbl_pram->rstate,
893 ugeth->p_rx_glbl_pram->rstate);
894 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
895 (u32) & ugeth->p_rx_glbl_pram->mrblr,
896 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
897 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
898 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
899 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
900 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
901 (u32) & ugeth->p_rx_glbl_pram->mflr,
902 in_be16(&ugeth->p_rx_glbl_pram->mflr));
903 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
904 (u32) & ugeth->p_rx_glbl_pram->minflr,
905 in_be16(&ugeth->p_rx_glbl_pram->minflr));
906 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
907 (u32) & ugeth->p_rx_glbl_pram->maxd1,
908 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
909 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
910 (u32) & ugeth->p_rx_glbl_pram->maxd2,
911 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
912 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
913 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
914 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
915 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
916 (u32) & ugeth->p_rx_glbl_pram->l2qt,
917 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
918 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
919 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
920 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
921 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
922 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
923 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
924 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
925 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
926 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
927 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
928 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
929 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
930 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
931 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
932 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
933 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
934 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
935 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
936 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
937 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
938 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
939 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
940 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
941 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
942 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
943 (u32) & ugeth->p_rx_glbl_pram->vlantype,
944 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
945 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
946 (u32) & ugeth->p_rx_glbl_pram->vlantci,
947 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
948 for (i = 0; i < 64; i++)
949 ugeth_info
950 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
951 i,
952 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
953 ugeth->p_rx_glbl_pram->addressfiltering[i]);
954 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
955 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
956 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
957 }
958 if (ugeth->p_send_q_mem_reg) {
959 ugeth_info("Send Q memory registers:");
960 ugeth_info("Base address: 0x%08x",
961 (u32) ugeth->p_send_q_mem_reg);
962 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
963 ugeth_info("SQQD[%d]:", i);
964 ugeth_info("Base address: 0x%08x",
965 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
966 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
18a8e864 967 sizeof(struct ucc_geth_send_queue_qd));
ce973b14
LY		 968 }
969 }
970 if (ugeth->p_scheduler) {
971 ugeth_info("Scheduler:");
972 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
973 mem_disp((u8 *) ugeth->p_scheduler,
974 sizeof(*ugeth->p_scheduler));
975 }
976 if (ugeth->p_tx_fw_statistics_pram) {
977 ugeth_info("TX FW statistics pram:");
978 ugeth_info("Base address: 0x%08x",
979 (u32) ugeth->p_tx_fw_statistics_pram);
980 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
981 sizeof(*ugeth->p_tx_fw_statistics_pram));
982 }
983 if (ugeth->p_rx_fw_statistics_pram) {
984 ugeth_info("RX FW statistics pram:");
985 ugeth_info("Base address: 0x%08x",
986 (u32) ugeth->p_rx_fw_statistics_pram);
987 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
988 sizeof(*ugeth->p_rx_fw_statistics_pram));
989 }
990 if (ugeth->p_rx_irq_coalescing_tbl) {
991 ugeth_info("RX IRQ coalescing tables:");
992 ugeth_info("Base address: 0x%08x",
993 (u32) ugeth->p_rx_irq_coalescing_tbl);
994 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
995 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
996 ugeth_info("Base address: 0x%08x",
997 (u32) & ugeth->p_rx_irq_coalescing_tbl->
998 coalescingentry[i]);
999 ugeth_info
1000 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
1001 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1002 coalescingentry[i].interruptcoalescingmaxvalue,
1003 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1004 coalescingentry[i].
1005 interruptcoalescingmaxvalue));
1006 ugeth_info
1007 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1008 (u32) & ugeth->p_rx_irq_coalescing_tbl->
1009 coalescingentry[i].interruptcoalescingcounter,
1010 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1011 coalescingentry[i].
1012 interruptcoalescingcounter));
1013 }
1014 }
1015 if (ugeth->p_rx_bd_qs_tbl) {
1016 ugeth_info("RX BD QS tables:");
1017 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1018 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1019 ugeth_info("RX BD QS table[%d]:", i);
1020 ugeth_info("Base address: 0x%08x",
1021 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1022 ugeth_info
1023 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1024 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1025 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1026 ugeth_info
1027 ("bdptr : addr - 0x%08x, val - 0x%08x",
1028 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1029 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1030 ugeth_info
1031 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1032 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1033 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1034 externalbdbaseptr));
1035 ugeth_info
1036 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1037 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1038 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1039 ugeth_info("ucode RX Prefetched BDs:");
1040 ugeth_info("Base address: 0x%08x",
1041 (u32)
1042 qe_muram_addr(in_be32
1043 (&ugeth->p_rx_bd_qs_tbl[i].
1044 bdbaseptr)));
1045 mem_disp((u8 *)
1046 qe_muram_addr(in_be32
1047 (&ugeth->p_rx_bd_qs_tbl[i].
1048 bdbaseptr)),
18a8e864 1049 sizeof(struct ucc_geth_rx_prefetched_bds));
ce973b14
LY		 1050 }
1051 }
1052 if (ugeth->p_init_enet_param_shadow) {
1053 int size;
1054 ugeth_info("Init enet param shadow:");
1055 ugeth_info("Base address: 0x%08x",
1056 (u32) ugeth->p_init_enet_param_shadow);
1057 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1058 sizeof(*ugeth->p_init_enet_param_shadow));
1059
18a8e864 1060 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 1061 if (ugeth->ug_info->rxExtendedFiltering) {
1062 size +=
1063 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1064 if (ugeth->ug_info->largestexternallookupkeysize ==
1065 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1066 size +=
1067 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1068 if (ugeth->ug_info->largestexternallookupkeysize ==
1069 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1070 size +=
1071 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1072 }
1073
1074 dump_init_enet_entries(ugeth,
1075 &(ugeth->p_init_enet_param_shadow->
1076 txthread[0]),
1077 ENET_INIT_PARAM_MAX_ENTRIES_TX,
18a8e864 1078 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 1079 ugeth->ug_info->riscTx, 0);
1080 dump_init_enet_entries(ugeth,
1081 &(ugeth->p_init_enet_param_shadow->
1082 rxthread[0]),
1083 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1084 ugeth->ug_info->riscRx, 1);
1085 }
1086}
1087#endif /* DEBUG */
1088
6fee40e9
AF		 1089static void init_default_reg_vals(u32 __iomem *upsmr_register,
1090 u32 __iomem *maccfg1_register,
1091 u32 __iomem *maccfg2_register)
ce973b14
LY		 1092{
1093 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1094 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1095 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1096}
1097
1098static int init_half_duplex_params(int alt_beb,
1099 int back_pressure_no_backoff,
1100 int no_backoff,
1101 int excess_defer,
1102 u8 alt_beb_truncation,
1103 u8 max_retransmissions,
1104 u8 collision_window,
6fee40e9 1105 u32 __iomem *hafdup_register)
ce973b14
LY		 1106{
1107 u32 value = 0;
1108
1109 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1110 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1111 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1112 return -EINVAL;
1113
1114 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1115
1116 if (alt_beb)
1117 value |= HALFDUP_ALT_BEB;
1118 if (back_pressure_no_backoff)
1119 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1120 if (no_backoff)
1121 value |= HALFDUP_NO_BACKOFF;
1122 if (excess_defer)
1123 value |= HALFDUP_EXCESSIVE_DEFER;
1124
1125 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1126
1127 value |= collision_window;
1128
1129 out_be32(hafdup_register, value);
1130 return 0;
1131}
1132
1133static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1134 u8 non_btb_ipg,
1135 u8 min_ifg,
1136 u8 btb_ipg,
6fee40e9 1137 u32 __iomem *ipgifg_register)
ce973b14
LY		 1138{
1139 u32 value = 0;
1140
1141 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1142 IPG part 2 */
1143 if (non_btb_cs_ipg > non_btb_ipg)
1144 return -EINVAL;
1145
1146 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1147 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1148 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1149 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1150 return -EINVAL;
1151
1152 value |=
1153 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1154 IPGIFG_NBTB_CS_IPG_MASK);
1155 value |=
1156 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1157 IPGIFG_NBTB_IPG_MASK);
1158 value |=
1159 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1160 IPGIFG_MIN_IFG_MASK);
1161 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1162
1163 out_be32(ipgifg_register, value);
1164 return 0;
1165}
1166
ac421852 1167int init_flow_control_params(u32 automatic_flow_control_mode,
ce973b14
LY		 1168 int rx_flow_control_enable,
1169 int tx_flow_control_enable,
1170 u16 pause_period,
1171 u16 extension_field,
6fee40e9
AF		 1172 u32 __iomem *upsmr_register,
1173 u32 __iomem *uempr_register,
1174 u32 __iomem *maccfg1_register)
ce973b14
LY		 1175{
1176 u32 value = 0;
1177
1178 /* Set UEMPR register */
1179 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1180 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1181 out_be32(uempr_register, value);
1182
1183 /* Set UPSMR register */
1184 value = in_be32(upsmr_register);
1185 value |= automatic_flow_control_mode;
1186 out_be32(upsmr_register, value);
1187
1188 value = in_be32(maccfg1_register);
1189 if (rx_flow_control_enable)
1190 value |= MACCFG1_FLOW_RX;
1191 if (tx_flow_control_enable)
1192 value |= MACCFG1_FLOW_TX;
1193 out_be32(maccfg1_register, value);
1194
1195 return 0;
1196}
1197
1198static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1199 int auto_zero_hardware_statistics,
6fee40e9
AF		 1200 u32 __iomem *upsmr_register,
1201 u16 __iomem *uescr_register)
ce973b14
LY		 1202{
1203 u32 upsmr_value = 0;
1204 u16 uescr_value = 0;
1205 /* Enable hardware statistics gathering if requested */
1206 if (enable_hardware_statistics) {
1207 upsmr_value = in_be32(upsmr_register);
1208 upsmr_value |= UPSMR_HSE;
1209 out_be32(upsmr_register, upsmr_value);
1210 }
1211
1212 /* Clear hardware statistics counters */
1213 uescr_value = in_be16(uescr_register);
1214 uescr_value |= UESCR_CLRCNT;
1215 /* Automatically zero hardware statistics counters on read,
1216 if requested */
1217 if (auto_zero_hardware_statistics)
1218 uescr_value |= UESCR_AUTOZ;
1219 out_be16(uescr_register, uescr_value);
1220
1221 return 0;
1222}
1223
1224static int init_firmware_statistics_gathering_mode(int
1225 enable_tx_firmware_statistics,
1226 int enable_rx_firmware_statistics,
6fee40e9 1227 u32 __iomem *tx_rmon_base_ptr,
ce973b14 1228 u32 tx_firmware_statistics_structure_address,
6fee40e9 1229 u32 __iomem *rx_rmon_base_ptr,
ce973b14 1230 u32 rx_firmware_statistics_structure_address,
6fee40e9
AF		 1231 u16 __iomem *temoder_register,
1232 u32 __iomem *remoder_register)
ce973b14
LY		 1233{
1234 /* Note: this function does not check if */
1235 /* the parameters it receives are NULL */
1236 u16 temoder_value;
1237 u32 remoder_value;
1238
1239 if (enable_tx_firmware_statistics) {
1240 out_be32(tx_rmon_base_ptr,
1241 tx_firmware_statistics_structure_address);
1242 temoder_value = in_be16(temoder_register);
1243 temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
1244 out_be16(temoder_register, temoder_value);
1245 }
1246
1247 if (enable_rx_firmware_statistics) {
1248 out_be32(rx_rmon_base_ptr,
1249 rx_firmware_statistics_structure_address);
1250 remoder_value = in_be32(remoder_register);
1251 remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
1252 out_be32(remoder_register, remoder_value);
1253 }
1254
1255 return 0;
1256}
1257
1258static int init_mac_station_addr_regs(u8 address_byte_0,
1259 u8 address_byte_1,
1260 u8 address_byte_2,
1261 u8 address_byte_3,
1262 u8 address_byte_4,
1263 u8 address_byte_5,
6fee40e9
AF		 1264 u32 __iomem *macstnaddr1_register,
1265 u32 __iomem *macstnaddr2_register)
ce973b14
LY		 1266{
1267 u32 value = 0;
1268
1269 /* Example: for a station address of 0x12345678ABCD, */
1270 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1271
1272 /* MACSTNADDR1 Register: */
1273
1274 /* 0 7 8 15 */
1275 /* station address byte 5 station address byte 4 */
1276 /* 16 23 24 31 */
1277 /* station address byte 3 station address byte 2 */
1278 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1279 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1280 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1281 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1282
1283 out_be32(macstnaddr1_register, value);
1284
1285 /* MACSTNADDR2 Register: */
1286
1287 /* 0 7 8 15 */
1288 /* station address byte 1 station address byte 0 */
1289 /* 16 23 24 31 */
1290 /* reserved reserved */
1291 value = 0;
1292 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1293 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1294
1295 out_be32(macstnaddr2_register, value);
1296
1297 return 0;
1298}
1299
ce973b14 1300static int init_check_frame_length_mode(int length_check,
6fee40e9 1301 u32 __iomem *maccfg2_register)
ce973b14
LY		 1302{
1303 u32 value = 0;
1304
1305 value = in_be32(maccfg2_register);
1306
1307 if (length_check)
1308 value |= MACCFG2_LC;
1309 else
1310 value &= ~MACCFG2_LC;
1311
1312 out_be32(maccfg2_register, value);
1313 return 0;
1314}
1315
1316static int init_preamble_length(u8 preamble_length,
6fee40e9 1317 u32 __iomem *maccfg2_register)
ce973b14
LY		 1318{
1319 u32 value = 0;
1320
1321 if ((preamble_length < 3) || (preamble_length > 7))
1322 return -EINVAL;
1323
1324 value = in_be32(maccfg2_register);
1325 value &= ~MACCFG2_PREL_MASK;
1326 value |= (preamble_length << MACCFG2_PREL_SHIFT);
1327 out_be32(maccfg2_register, value);
1328 return 0;
1329}
1330
ce973b14
LY		 1331static int init_rx_parameters(int reject_broadcast,
1332 int receive_short_frames,
6fee40e9 1333 int promiscuous, u32 __iomem *upsmr_register)
ce973b14
LY		 1334{
1335 u32 value = 0;
1336
1337 value = in_be32(upsmr_register);
1338
1339 if (reject_broadcast)
1340 value |= UPSMR_BRO;
1341 else
1342 value &= ~UPSMR_BRO;
1343
1344 if (receive_short_frames)
1345 value |= UPSMR_RSH;
1346 else
1347 value &= ~UPSMR_RSH;
1348
1349 if (promiscuous)
1350 value |= UPSMR_PRO;
1351 else
1352 value &= ~UPSMR_PRO;
1353
1354 out_be32(upsmr_register, value);
1355
1356 return 0;
1357}
1358
1359static int init_max_rx_buff_len(u16 max_rx_buf_len,
6fee40e9 1360 u16 __iomem *mrblr_register)
ce973b14
LY		 1361{
1362 /* max_rx_buf_len value must be a multiple of 128 */
1363 if ((max_rx_buf_len == 0)
1364 || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1365 return -EINVAL;
1366
1367 out_be16(mrblr_register, max_rx_buf_len);
1368 return 0;
1369}
1370
1371static int init_min_frame_len(u16 min_frame_length,
6fee40e9
AF		 1372 u16 __iomem *minflr_register,
1373 u16 __iomem *mrblr_register)
ce973b14
LY		 1374{
1375 u16 mrblr_value = 0;
1376
1377 mrblr_value = in_be16(mrblr_register);
1378 if (min_frame_length >= (mrblr_value - 4))
1379 return -EINVAL;
1380
1381 out_be16(minflr_register, min_frame_length);
1382 return 0;
1383}
1384
18a8e864 1385static int adjust_enet_interface(struct ucc_geth_private *ugeth)
ce973b14 1386{
18a8e864 1387 struct ucc_geth_info *ug_info;
6fee40e9
AF		 1388 struct ucc_geth __iomem *ug_regs;
1389 struct ucc_fast __iomem *uf_regs;
728de4c9
KP		 1390 int ret_val;
1391 u32 upsmr, maccfg2, tbiBaseAddress;
ce973b14
LY		 1392 u16 value;
1393
b39d66a8 1394 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 1395
1396 ug_info = ugeth->ug_info;
1397 ug_regs = ugeth->ug_regs;
1398 uf_regs = ugeth->uccf->uf_regs;
1399
ce973b14
LY		 1400 /* Set MACCFG2 */
1401 maccfg2 = in_be32(&ug_regs->maccfg2);
1402 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
728de4c9
KP		 1403 if ((ugeth->max_speed == SPEED_10) ||
1404 (ugeth->max_speed == SPEED_100))
ce973b14 1405 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
728de4c9 1406 else if (ugeth->max_speed == SPEED_1000)
ce973b14
LY		 1407 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1408 maccfg2 |= ug_info->padAndCrc;
1409 out_be32(&ug_regs->maccfg2, maccfg2);
1410
1411 /* Set UPSMR */
1412 upsmr = in_be32(&uf_regs->upsmr);
1413 upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
728de4c9
KP		 1414 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1415 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1416 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1417 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1418 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9 1419 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
ce973b14 1420 upsmr |= UPSMR_RPM;
728de4c9
KP		 1421 switch (ugeth->max_speed) {
1422 case SPEED_10:
1423 upsmr |= UPSMR_R10M;
1424 /* FALLTHROUGH */
1425 case SPEED_100:
1426 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1427 upsmr |= UPSMR_RMM;
1428 }
1429 }
1430 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1431 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
ce973b14 1432 upsmr |= UPSMR_TBIM;
728de4c9 1433 }
ce973b14
LY		 1434 out_be32(&uf_regs->upsmr, upsmr);
1435
ce973b14
LY		 1436 /* Disable autonegotiation in tbi mode, because by default it
1437 comes up in autonegotiation mode. */
1438 /* Note that this depends on proper setting in utbipar register. */
728de4c9
KP		 1439 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1440 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
ce973b14
LY		 1441 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1442 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1443 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
728de4c9
KP		 1444 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1445 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
ce973b14 1446 value &= ~0x1000; /* Turn off autonegotiation */
728de4c9
KP		 1447 ugeth->phydev->bus->write(ugeth->phydev->bus,
1448 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
ce973b14
LY		 1449 }
1450
1451 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1452
1453 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1454 if (ret_val != 0) {
890de95e
LY		 1455 if (netif_msg_probe(ugeth))
1456 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
b39d66a8 1457 __func__);
ce973b14
LY		 1458 return ret_val;
1459 }
1460
1461 return 0;
1462}
1463
1464/* Called every time the controller might need to be made
1465 * aware of new link state. The PHY code conveys this
1466 * information through variables in the ugeth structure, and this
1467 * function converts those variables into the appropriate
1468 * register values, and can bring down the device if needed.
1469 */
728de4c9 1470
ce973b14
LY		 1471static void adjust_link(struct net_device *dev)
1472{
18a8e864 1473 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9
AF		 1474 struct ucc_geth __iomem *ug_regs;
1475 struct ucc_fast __iomem *uf_regs;
728de4c9
KP		 1476 struct phy_device *phydev = ugeth->phydev;
1477 unsigned long flags;
1478 int new_state = 0;
ce973b14
LY		 1479
1480 ug_regs = ugeth->ug_regs;
728de4c9 1481 uf_regs = ugeth->uccf->uf_regs;
ce973b14 1482
728de4c9
KP		 1483 spin_lock_irqsave(&ugeth->lock, flags);
1484
1485 if (phydev->link) {
1486 u32 tempval = in_be32(&ug_regs->maccfg2);
1487 u32 upsmr = in_be32(&uf_regs->upsmr);
ce973b14
LY		 1488 /* Now we make sure that we can be in full duplex mode.
1489 * If not, we operate in half-duplex mode. */
728de4c9
KP		 1490 if (phydev->duplex != ugeth->oldduplex) {
1491 new_state = 1;
1492 if (!(phydev->duplex))
ce973b14 1493 tempval &= ~(MACCFG2_FDX);
728de4c9 1494 else
ce973b14 1495 tempval |= MACCFG2_FDX;
728de4c9 1496 ugeth->oldduplex = phydev->duplex;
ce973b14
LY		 1497 }
1498
728de4c9
KP		 1499 if (phydev->speed != ugeth->oldspeed) {
1500 new_state = 1;
1501 switch (phydev->speed) {
1502 case SPEED_1000:
1503 tempval = ((tempval &
1504 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1505 MACCFG2_INTERFACE_MODE_BYTE);
a1862a53 1506 break;
728de4c9
KP		 1507 case SPEED_100:
1508 case SPEED_10:
1509 tempval = ((tempval &
1510 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1511 MACCFG2_INTERFACE_MODE_NIBBLE);
1512 /* if reduced mode, re-set UPSMR.R10M */
1513 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1514 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1515 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1516 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1517 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9
KP		 1518 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1519 if (phydev->speed == SPEED_10)
1520 upsmr |= UPSMR_R10M;
1521 else
1522 upsmr &= ~(UPSMR_R10M);
1523 }
ce973b14
LY		 1524 break;
1525 default:
728de4c9
KP		 1526 if (netif_msg_link(ugeth))
1527 ugeth_warn(
1528 "%s: Ack! Speed (%d) is not 10/100/1000!",
1529 dev->name, phydev->speed);
ce973b14
LY		 1530 break;
1531 }
728de4c9 1532 ugeth->oldspeed = phydev->speed;
ce973b14
LY		 1533 }
1534
728de4c9
KP		 1535 out_be32(&ug_regs->maccfg2, tempval);
1536 out_be32(&uf_regs->upsmr, upsmr);
1537
ce973b14 1538 if (!ugeth->oldlink) {
728de4c9 1539 new_state = 1;
ce973b14 1540 ugeth->oldlink = 1;
ce973b14 1541 }
728de4c9
KP		 1542 } else if (ugeth->oldlink) {
1543 new_state = 1;
ce973b14
LY		 1544 ugeth->oldlink = 0;
1545 ugeth->oldspeed = 0;
1546 ugeth->oldduplex = -1;
ce973b14 1547 }
728de4c9
KP		 1548
1549 if (new_state && netif_msg_link(ugeth))
1550 phy_print_status(phydev);
1551
1552 spin_unlock_irqrestore(&ugeth->lock, flags);
ce973b14
LY		 1553}
1554
1555/* Configure the PHY for dev.
1556 * returns 0 if success. -1 if failure
1557 */
1558static int init_phy(struct net_device *dev)
1559{
728de4c9
KP		 1560 struct ucc_geth_private *priv = netdev_priv(dev);
1561 struct phy_device *phydev;
1562 char phy_id[BUS_ID_SIZE];
ce973b14 1563
728de4c9
KP		 1564 priv->oldlink = 0;
1565 priv->oldspeed = 0;
1566 priv->oldduplex = -1;
ce973b14 1567
fb28ad35
KS		 1568 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, priv->ug_info->mdio_bus,
1569 priv->ug_info->phy_address);
ce973b14 1570
728de4c9 1571 phydev = phy_connect(dev, phy_id, &adjust_link, 0, priv->phy_interface);
ce973b14 1572
728de4c9
KP		 1573 if (IS_ERR(phydev)) {
1574 printk("%s: Could not attach to PHY\n", dev->name);
1575 return PTR_ERR(phydev);
ce973b14
LY		 1576 }
1577
728de4c9 1578 phydev->supported &= (ADVERTISED_10baseT_Half |
ce973b14
LY		 1579 ADVERTISED_10baseT_Full |
1580 ADVERTISED_100baseT_Half |
728de4c9 1581 ADVERTISED_100baseT_Full);
ce973b14 1582
728de4c9
KP		 1583 if (priv->max_speed == SPEED_1000)
1584 phydev->supported |= ADVERTISED_1000baseT_Full;
ce973b14 1585
728de4c9 1586 phydev->advertising = phydev->supported;
68dc44af 1587
728de4c9 1588 priv->phydev = phydev;
ce973b14
LY		 1589
1590 return 0;
ce973b14
LY		 1591}
1592
728de4c9 1593
ce973b14 1594
18a8e864 1595static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
ce973b14 1596{
18a8e864 1597 struct ucc_fast_private *uccf;
ce973b14
LY		 1598 u32 cecr_subblock;
1599 u32 temp;
b3431c64 1600 int i = 10;
ce973b14
LY		 1601
1602 uccf = ugeth->uccf;
1603
1604 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1605 temp = in_be32(uccf->p_uccm);
1606 temp &= ~UCCE_GRA;
1607 out_be32(uccf->p_uccm, temp);
1608 out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */
1609
1610 /* Issue host command */
1611 cecr_subblock =
1612 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1613 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
18a8e864 1614 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 1615
1616 /* Wait for command to complete */
1617 do {
b3431c64 1618 msleep(10);
ce973b14 1619 temp = in_be32(uccf->p_ucce);
b3431c64 1620 } while (!(temp & UCCE_GRA) && --i);
ce973b14
LY		 1621
1622 uccf->stopped_tx = 1;
1623
1624 return 0;
1625}
1626
18a8e864 1627static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
ce973b14 1628{
18a8e864 1629 struct ucc_fast_private *uccf;
ce973b14
LY		 1630 u32 cecr_subblock;
1631 u8 temp;
b3431c64 1632 int i = 10;
ce973b14
LY		 1633
1634 uccf = ugeth->uccf;
1635
1636 /* Clear acknowledge bit */
6fee40e9 1637 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
ce973b14 1638 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
6fee40e9 1639 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
ce973b14
LY		 1640
1641 /* Keep issuing command and checking acknowledge bit until
1642 it is asserted, according to spec */
1643 do {
1644 /* Issue host command */
1645 cecr_subblock =
1646 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1647 ucc_num);
1648 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
18a8e864 1649 QE_CR_PROTOCOL_ETHERNET, 0);
b3431c64 1650 msleep(10);
6fee40e9 1651 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
b3431c64 1652 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
ce973b14
LY		 1653
1654 uccf->stopped_rx = 1;
1655
1656 return 0;
1657}
1658
18a8e864 1659static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
ce973b14 1660{
18a8e864 1661 struct ucc_fast_private *uccf;
ce973b14
LY		 1662 u32 cecr_subblock;
1663
1664 uccf = ugeth->uccf;
1665
1666 cecr_subblock =
1667 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 1668 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 1669 uccf->stopped_tx = 0;
1670
1671 return 0;
1672}
1673
18a8e864 1674static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
ce973b14 1675{
18a8e864 1676 struct ucc_fast_private *uccf;
ce973b14
LY		 1677 u32 cecr_subblock;
1678
1679 uccf = ugeth->uccf;
1680
1681 cecr_subblock =
1682 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 1683 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 1684 0);
1685 uccf->stopped_rx = 0;
1686
1687 return 0;
1688}
1689
18a8e864 1690static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
ce973b14 1691{
18a8e864 1692 struct ucc_fast_private *uccf;
ce973b14
LY		 1693 int enabled_tx, enabled_rx;
1694
1695 uccf = ugeth->uccf;
1696
1697 /* check if the UCC number is in range. */
1698 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
890de95e 1699 if (netif_msg_probe(ugeth))
b39d66a8 1700 ugeth_err("%s: ucc_num out of range.", __func__);
ce973b14
LY		 1701 return -EINVAL;
1702 }
1703
1704 enabled_tx = uccf->enabled_tx;
1705 enabled_rx = uccf->enabled_rx;
1706
1707 /* Get Tx and Rx going again, in case this channel was actively
1708 disabled. */
1709 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1710 ugeth_restart_tx(ugeth);
1711 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1712 ugeth_restart_rx(ugeth);
1713
1714 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1715
1716 return 0;
1717
1718}
1719
18a8e864 1720static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
ce973b14 1721{
18a8e864 1722 struct ucc_fast_private *uccf;
ce973b14
LY		 1723
1724 uccf = ugeth->uccf;
1725
1726 /* check if the UCC number is in range. */
1727 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
890de95e 1728 if (netif_msg_probe(ugeth))
b39d66a8 1729 ugeth_err("%s: ucc_num out of range.", __func__);
ce973b14
LY		 1730 return -EINVAL;
1731 }
1732
1733 /* Stop any transmissions */
1734 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1735 ugeth_graceful_stop_tx(ugeth);
1736
1737 /* Stop any receptions */
1738 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1739 ugeth_graceful_stop_rx(ugeth);
1740
1741 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1742
1743 return 0;
1744}
1745
18a8e864 1746static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 1747{
1748#ifdef DEBUG
1749 ucc_fast_dump_regs(ugeth->uccf);
1750 dump_regs(ugeth);
1751 dump_bds(ugeth);
1752#endif
1753}
1754
18a8e864 1755static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
ce973b14 1756 ugeth,
18a8e864 1757 enum enet_addr_type
ce973b14
LY		 1758 enet_addr_type)
1759{
6fee40e9 1760 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
18a8e864
LY		 1761 struct ucc_fast_private *uccf;
1762 enum comm_dir comm_dir;
ce973b14
LY		 1763 struct list_head *p_lh;
1764 u16 i, num;
6fee40e9
AF		 1765 u32 __iomem *addr_h;
1766 u32 __iomem *addr_l;
ce973b14
LY		 1767 u8 *p_counter;
1768
1769 uccf = ugeth->uccf;
1770
1771 p_82xx_addr_filt =
6fee40e9
AF		 1772 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1773 ugeth->p_rx_glbl_pram->addressfiltering;
ce973b14
LY		 1774
1775 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1776 addr_h = &(p_82xx_addr_filt->gaddr_h);
1777 addr_l = &(p_82xx_addr_filt->gaddr_l);
1778 p_lh = &ugeth->group_hash_q;
1779 p_counter = &(ugeth->numGroupAddrInHash);
1780 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1781 addr_h = &(p_82xx_addr_filt->iaddr_h);
1782 addr_l = &(p_82xx_addr_filt->iaddr_l);
1783 p_lh = &ugeth->ind_hash_q;
1784 p_counter = &(ugeth->numIndAddrInHash);
1785 } else
1786 return -EINVAL;
1787
1788 comm_dir = 0;
1789 if (uccf->enabled_tx)
1790 comm_dir |= COMM_DIR_TX;
1791 if (uccf->enabled_rx)
1792 comm_dir |= COMM_DIR_RX;
1793 if (comm_dir)
1794 ugeth_disable(ugeth, comm_dir);
1795
1796 /* Clear the hash table. */
1797 out_be32(addr_h, 0x00000000);
1798 out_be32(addr_l, 0x00000000);
1799
1800 if (!p_lh)
1801 return 0;
1802
1803 num = *p_counter;
1804
1805 /* Delete all remaining CQ elements */
1806 for (i = 0; i < num; i++)
1807 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1808
1809 *p_counter = 0;
1810
1811 if (comm_dir)
1812 ugeth_enable(ugeth, comm_dir);
1813
1814 return 0;
1815}
1816
18a8e864 1817static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
ce973b14
LY		 1818 u8 paddr_num)
1819{
1820 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1821 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1822}
1823
18a8e864 1824static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
ce973b14
LY		 1825{
1826 u16 i, j;
6fee40e9 1827 u8 __iomem *bd;
ce973b14
LY		 1828
1829 if (!ugeth)
1830 return;
1831
80a9fad8 1832 if (ugeth->uccf) {
ce973b14 1833 ucc_fast_free(ugeth->uccf);
80a9fad8
AV		 1834 ugeth->uccf = NULL;
1835 }
ce973b14
LY		 1836
1837 if (ugeth->p_thread_data_tx) {
1838 qe_muram_free(ugeth->thread_dat_tx_offset);
1839 ugeth->p_thread_data_tx = NULL;
1840 }
1841 if (ugeth->p_thread_data_rx) {
1842 qe_muram_free(ugeth->thread_dat_rx_offset);
1843 ugeth->p_thread_data_rx = NULL;
1844 }
1845 if (ugeth->p_exf_glbl_param) {
1846 qe_muram_free(ugeth->exf_glbl_param_offset);
1847 ugeth->p_exf_glbl_param = NULL;
1848 }
1849 if (ugeth->p_rx_glbl_pram) {
1850 qe_muram_free(ugeth->rx_glbl_pram_offset);
1851 ugeth->p_rx_glbl_pram = NULL;
1852 }
1853 if (ugeth->p_tx_glbl_pram) {
1854 qe_muram_free(ugeth->tx_glbl_pram_offset);
1855 ugeth->p_tx_glbl_pram = NULL;
1856 }
1857 if (ugeth->p_send_q_mem_reg) {
1858 qe_muram_free(ugeth->send_q_mem_reg_offset);
1859 ugeth->p_send_q_mem_reg = NULL;
1860 }
1861 if (ugeth->p_scheduler) {
1862 qe_muram_free(ugeth->scheduler_offset);
1863 ugeth->p_scheduler = NULL;
1864 }
1865 if (ugeth->p_tx_fw_statistics_pram) {
1866 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1867 ugeth->p_tx_fw_statistics_pram = NULL;
1868 }
1869 if (ugeth->p_rx_fw_statistics_pram) {
1870 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1871 ugeth->p_rx_fw_statistics_pram = NULL;
1872 }
1873 if (ugeth->p_rx_irq_coalescing_tbl) {
1874 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1875 ugeth->p_rx_irq_coalescing_tbl = NULL;
1876 }
1877 if (ugeth->p_rx_bd_qs_tbl) {
1878 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1879 ugeth->p_rx_bd_qs_tbl = NULL;
1880 }
1881 if (ugeth->p_init_enet_param_shadow) {
1882 return_init_enet_entries(ugeth,
1883 &(ugeth->p_init_enet_param_shadow->
1884 rxthread[0]),
1885 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1886 ugeth->ug_info->riscRx, 1);
1887 return_init_enet_entries(ugeth,
1888 &(ugeth->p_init_enet_param_shadow->
1889 txthread[0]),
1890 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1891 ugeth->ug_info->riscTx, 0);
1892 kfree(ugeth->p_init_enet_param_shadow);
1893 ugeth->p_init_enet_param_shadow = NULL;
1894 }
1895 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1896 bd = ugeth->p_tx_bd_ring[i];
3a8205ea
NIP		 1897 if (!bd)
1898 continue;
ce973b14
LY		 1899 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1900 if (ugeth->tx_skbuff[i][j]) {
7f80202b 1901 dma_unmap_single(&ugeth->dev->dev,
6fee40e9
AF		 1902 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1903 (in_be32((u32 __iomem *)bd) &
ce973b14
LY		 1904 BD_LENGTH_MASK),
1905 DMA_TO_DEVICE);
1906 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1907 ugeth->tx_skbuff[i][j] = NULL;
1908 }
1909 }
1910
1911 kfree(ugeth->tx_skbuff[i]);
1912
1913 if (ugeth->p_tx_bd_ring[i]) {
1914 if (ugeth->ug_info->uf_info.bd_mem_part ==
1915 MEM_PART_SYSTEM)
1916 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1917 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1918 MEM_PART_MURAM)
1919 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1920 ugeth->p_tx_bd_ring[i] = NULL;
1921 }
1922 }
1923 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1924 if (ugeth->p_rx_bd_ring[i]) {
1925 /* Return existing data buffers in ring */
1926 bd = ugeth->p_rx_bd_ring[i];
1927 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1928 if (ugeth->rx_skbuff[i][j]) {
7f80202b 1929 dma_unmap_single(&ugeth->dev->dev,
6fee40e9 1930 in_be32(&((struct qe_bd __iomem *)bd)->buf),
18a8e864
LY		 1931 ugeth->ug_info->
1932 uf_info.max_rx_buf_length +
1933 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1934 DMA_FROM_DEVICE);
1935 dev_kfree_skb_any(
1936 ugeth->rx_skbuff[i][j]);
ce973b14
LY		 1937 ugeth->rx_skbuff[i][j] = NULL;
1938 }
18a8e864 1939 bd += sizeof(struct qe_bd);
ce973b14
LY		 1940 }
1941
1942 kfree(ugeth->rx_skbuff[i]);
1943
1944 if (ugeth->ug_info->uf_info.bd_mem_part ==
1945 MEM_PART_SYSTEM)
1946 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1947 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1948 MEM_PART_MURAM)
1949 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1950 ugeth->p_rx_bd_ring[i] = NULL;
1951 }
1952 }
1953 while (!list_empty(&ugeth->group_hash_q))
1954 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1955 (dequeue(&ugeth->group_hash_q)));
1956 while (!list_empty(&ugeth->ind_hash_q))
1957 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1958 (dequeue(&ugeth->ind_hash_q)));
3e73fc9a
AV		 1959 if (ugeth->ug_regs) {
1960 iounmap(ugeth->ug_regs);
1961 ugeth->ug_regs = NULL;
1962 }
ce973b14
LY		 1963}
1964
1965static void ucc_geth_set_multi(struct net_device *dev)
1966{
18a8e864 1967 struct ucc_geth_private *ugeth;
ce973b14 1968 struct dev_mc_list *dmi;
6fee40e9
AF		 1969 struct ucc_fast __iomem *uf_regs;
1970 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
9030b3dd 1971 int i;
ce973b14
LY		 1972
1973 ugeth = netdev_priv(dev);
1974
1975 uf_regs = ugeth->uccf->uf_regs;
1976
1977 if (dev->flags & IFF_PROMISC) {
1978
6fee40e9 1979 out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr) | UPSMR_PRO);
ce973b14
LY		 1980
1981 } else {
1982
6fee40e9 1983 out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr)&~UPSMR_PRO);
ce973b14
LY		 1984
1985 p_82xx_addr_filt =
6fee40e9 1986 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 1987 p_rx_glbl_pram->addressfiltering;
1988
1989 if (dev->flags & IFF_ALLMULTI) {
1990 /* Catch all multicast addresses, so set the
1991 * filter to all 1's.
1992 */
1993 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
1994 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
1995 } else {
1996 /* Clear filter and add the addresses in the list.
1997 */
1998 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
1999 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2000
2001 dmi = dev->mc_list;
2002
2003 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2004
2005 /* Only support group multicast for now.
2006 */
2007 if (!(dmi->dmi_addr[0] & 1))
2008 continue;
2009
ce973b14
LY		 2010 /* Ask CPM to run CRC and set bit in
2011 * filter mask.
2012 */
9030b3dd 2013 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
ce973b14
LY		 2014 }
2015 }
2016 }
2017}
2018
18a8e864 2019static void ucc_geth_stop(struct ucc_geth_private *ugeth)
ce973b14 2020{
6fee40e9 2021 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
728de4c9 2022 struct phy_device *phydev = ugeth->phydev;
ce973b14
LY		 2023 u32 tempval;
2024
b39d66a8 2025 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 2026
2027 /* Disable the controller */
2028 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2029
2030 /* Tell the kernel the link is down */
728de4c9 2031 phy_stop(phydev);
ce973b14
LY		 2032
2033 /* Mask all interrupts */
c6f5047b 2034 out_be32(ugeth->uccf->p_uccm, 0x00000000);
ce973b14
LY		 2035
2036 /* Clear all interrupts */
2037 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2038
2039 /* Disable Rx and Tx */
2040 tempval = in_be32(&ug_regs->maccfg1);
2041 tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2042 out_be32(&ug_regs->maccfg1, tempval);
2043
ce973b14
LY		 2044 ucc_geth_memclean(ugeth);
2045}
2046
728de4c9 2047static int ucc_struct_init(struct ucc_geth_private *ugeth)
ce973b14 2048{
18a8e864
LY		 2049 struct ucc_geth_info *ug_info;
2050 struct ucc_fast_info *uf_info;
728de4c9 2051 int i;
ce973b14
LY		 2052
2053 ug_info = ugeth->ug_info;
2054 uf_info = &ug_info->uf_info;
2055
2056 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2057 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
890de95e
LY		 2058 if (netif_msg_probe(ugeth))
2059 ugeth_err("%s: Bad memory partition value.",
b39d66a8 2060 __func__);
ce973b14
LY		 2061 return -EINVAL;
2062 }
2063
2064 /* Rx BD lengths */
2065 for (i = 0; i < ug_info->numQueuesRx; i++) {
2066 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2067 (ug_info->bdRingLenRx[i] %
2068 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
890de95e
LY		 2069 if (netif_msg_probe(ugeth))
2070 ugeth_err
2071 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
b39d66a8 2072 __func__);
ce973b14
LY		 2073 return -EINVAL;
2074 }
2075 }
2076
2077 /* Tx BD lengths */
2078 for (i = 0; i < ug_info->numQueuesTx; i++) {
2079 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
890de95e
LY		 2080 if (netif_msg_probe(ugeth))
2081 ugeth_err
2082 ("%s: Tx BD ring length must be no smaller than 2.",
b39d66a8 2083 __func__);
ce973b14
LY		 2084 return -EINVAL;
2085 }
2086 }
2087
2088 /* mrblr */
2089 if ((uf_info->max_rx_buf_length == 0) ||
2090 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
890de95e
LY		 2091 if (netif_msg_probe(ugeth))
2092 ugeth_err
2093 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
b39d66a8 2094 __func__);
ce973b14
LY		 2095 return -EINVAL;
2096 }
2097
2098 /* num Tx queues */
2099 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
890de95e 2100 if (netif_msg_probe(ugeth))
b39d66a8 2101 ugeth_err("%s: number of tx queues too large.", __func__);
ce973b14
LY		 2102 return -EINVAL;
2103 }
2104
2105 /* num Rx queues */
2106 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
890de95e 2107 if (netif_msg_probe(ugeth))
b39d66a8 2108 ugeth_err("%s: number of rx queues too large.", __func__);
ce973b14
LY		 2109 return -EINVAL;
2110 }
2111
2112 /* l2qt */
2113 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2114 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2115 if (netif_msg_probe(ugeth))
2116 ugeth_err
2117 ("%s: VLAN priority table entry must not be"
2118 " larger than number of Rx queues.",
b39d66a8 2119 __func__);
ce973b14
LY		 2120 return -EINVAL;
2121 }
2122 }
2123
2124 /* l3qt */
2125 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2126 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2127 if (netif_msg_probe(ugeth))
2128 ugeth_err
2129 ("%s: IP priority table entry must not be"
2130 " larger than number of Rx queues.",
b39d66a8 2131 __func__);
ce973b14
LY		 2132 return -EINVAL;
2133 }
2134 }
2135
2136 if (ug_info->cam && !ug_info->ecamptr) {
890de95e
LY		 2137 if (netif_msg_probe(ugeth))
2138 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
b39d66a8 2139 __func__);
ce973b14
LY		 2140 return -EINVAL;
2141 }
2142
2143 if ((ug_info->numStationAddresses !=
2144 UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2145 && ug_info->rxExtendedFiltering) {
890de95e
LY		 2146 if (netif_msg_probe(ugeth))
2147 ugeth_err("%s: Number of station addresses greater than 1 "
2148 "not allowed in extended parsing mode.",
b39d66a8 2149 __func__);
ce973b14
LY		 2150 return -EINVAL;
2151 }
2152
2153 /* Generate uccm_mask for receive */
2154 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2155 for (i = 0; i < ug_info->numQueuesRx; i++)
2156 uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i);
2157
2158 for (i = 0; i < ug_info->numQueuesTx; i++)
2159 uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i);
2160 /* Initialize the general fast UCC block. */
728de4c9 2161 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
890de95e 2162 if (netif_msg_probe(ugeth))
b39d66a8 2163 ugeth_err("%s: Failed to init uccf.", __func__);
ce973b14
LY		 2164 return -ENOMEM;
2165 }
728de4c9 2166
3e73fc9a
AV		 2167 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2168 if (!ugeth->ug_regs) {
2169 if (netif_msg_probe(ugeth))
2170 ugeth_err("%s: Failed to ioremap regs.", __func__);
2171 return -ENOMEM;
2172 }
728de4c9
KP		 2173
2174 return 0;
2175}
2176
2177static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2178{
6fee40e9
AF		 2179 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2180 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
728de4c9
KP		 2181 struct ucc_fast_private *uccf;
2182 struct ucc_geth_info *ug_info;
2183 struct ucc_fast_info *uf_info;
6fee40e9
AF		 2184 struct ucc_fast __iomem *uf_regs;
2185 struct ucc_geth __iomem *ug_regs;
728de4c9
KP		 2186 int ret_val = -EINVAL;
2187 u32 remoder = UCC_GETH_REMODER_INIT;
2188 u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
2189 u32 ifstat, i, j, size, l2qt, l3qt, length;
2190 u16 temoder = UCC_GETH_TEMODER_INIT;
2191 u16 test;
2192 u8 function_code = 0;
6fee40e9
AF		 2193 u8 __iomem *bd;
2194 u8 __iomem *endOfRing;
728de4c9
KP		 2195 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2196
b39d66a8 2197 ugeth_vdbg("%s: IN", __func__);
728de4c9
KP		 2198 uccf = ugeth->uccf;
2199 ug_info = ugeth->ug_info;
2200 uf_info = &ug_info->uf_info;
2201 uf_regs = uccf->uf_regs;
2202 ug_regs = ugeth->ug_regs;
ce973b14
LY		 2203
2204 switch (ug_info->numThreadsRx) {
2205 case UCC_GETH_NUM_OF_THREADS_1:
2206 numThreadsRxNumerical = 1;
2207 break;
2208 case UCC_GETH_NUM_OF_THREADS_2:
2209 numThreadsRxNumerical = 2;
2210 break;
2211 case UCC_GETH_NUM_OF_THREADS_4:
2212 numThreadsRxNumerical = 4;
2213 break;
2214 case UCC_GETH_NUM_OF_THREADS_6:
2215 numThreadsRxNumerical = 6;
2216 break;
2217 case UCC_GETH_NUM_OF_THREADS_8:
2218 numThreadsRxNumerical = 8;
2219 break;
2220 default:
890de95e
LY		 2221 if (netif_msg_ifup(ugeth))
2222 ugeth_err("%s: Bad number of Rx threads value.",
b39d66a8 2223 __func__);
ce973b14
LY		 2224 return -EINVAL;
2225 break;
2226 }
2227
2228 switch (ug_info->numThreadsTx) {
2229 case UCC_GETH_NUM_OF_THREADS_1:
2230 numThreadsTxNumerical = 1;
2231 break;
2232 case UCC_GETH_NUM_OF_THREADS_2:
2233 numThreadsTxNumerical = 2;
2234 break;
2235 case UCC_GETH_NUM_OF_THREADS_4:
2236 numThreadsTxNumerical = 4;
2237 break;
2238 case UCC_GETH_NUM_OF_THREADS_6:
2239 numThreadsTxNumerical = 6;
2240 break;
2241 case UCC_GETH_NUM_OF_THREADS_8:
2242 numThreadsTxNumerical = 8;
2243 break;
2244 default:
890de95e
LY		 2245 if (netif_msg_ifup(ugeth))
2246 ugeth_err("%s: Bad number of Tx threads value.",
b39d66a8 2247 __func__);
ce973b14
LY		 2248 return -EINVAL;
2249 break;
2250 }
2251
2252 /* Calculate rx_extended_features */
2253 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2254 ug_info->ipAddressAlignment ||
2255 (ug_info->numStationAddresses !=
2256 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2257
2258 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2259 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2260 || (ug_info->vlanOperationNonTagged !=
2261 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2262
ce973b14
LY		 2263 init_default_reg_vals(&uf_regs->upsmr,
2264 &ug_regs->maccfg1, &ug_regs->maccfg2);
2265
2266 /* Set UPSMR */
2267 /* For more details see the hardware spec. */
2268 init_rx_parameters(ug_info->bro,
2269 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2270
2271 /* We're going to ignore other registers for now, */
2272 /* except as needed to get up and running */
2273
2274 /* Set MACCFG1 */
2275 /* For more details see the hardware spec. */
2276 init_flow_control_params(ug_info->aufc,
2277 ug_info->receiveFlowControl,
ac421852 2278 ug_info->transmitFlowControl,
ce973b14
LY		 2279 ug_info->pausePeriod,
2280 ug_info->extensionField,
2281 &uf_regs->upsmr,
2282 &ug_regs->uempr, &ug_regs->maccfg1);
2283
2284 maccfg1 = in_be32(&ug_regs->maccfg1);
2285 maccfg1 |= MACCFG1_ENABLE_RX;
2286 maccfg1 |= MACCFG1_ENABLE_TX;
2287 out_be32(&ug_regs->maccfg1, maccfg1);
2288
2289 /* Set IPGIFG */
2290 /* For more details see the hardware spec. */
2291 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2292 ug_info->nonBackToBackIfgPart2,
2293 ug_info->
2294 miminumInterFrameGapEnforcement,
2295 ug_info->backToBackInterFrameGap,
2296 &ug_regs->ipgifg);
2297 if (ret_val != 0) {
890de95e
LY		 2298 if (netif_msg_ifup(ugeth))
2299 ugeth_err("%s: IPGIFG initialization parameter too large.",
b39d66a8 2300 __func__);
ce973b14
LY		 2301 return ret_val;
2302 }
2303
2304 /* Set HAFDUP */
2305 /* For more details see the hardware spec. */
2306 ret_val = init_half_duplex_params(ug_info->altBeb,
2307 ug_info->backPressureNoBackoff,
2308 ug_info->noBackoff,
2309 ug_info->excessDefer,
2310 ug_info->altBebTruncation,
2311 ug_info->maxRetransmission,
2312 ug_info->collisionWindow,
2313 &ug_regs->hafdup);
2314 if (ret_val != 0) {
890de95e
LY		 2315 if (netif_msg_ifup(ugeth))
2316 ugeth_err("%s: Half Duplex initialization parameter too large.",
b39d66a8 2317 __func__);
ce973b14
LY		 2318 return ret_val;
2319 }
2320
2321 /* Set IFSTAT */
2322 /* For more details see the hardware spec. */
2323 /* Read only - resets upon read */
2324 ifstat = in_be32(&ug_regs->ifstat);
2325
2326 /* Clear UEMPR */
2327 /* For more details see the hardware spec. */
2328 out_be32(&ug_regs->uempr, 0);
2329
2330 /* Set UESCR */
2331 /* For more details see the hardware spec. */
2332 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2333 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2334 0, &uf_regs->upsmr, &ug_regs->uescr);
2335
2336 /* Allocate Tx bds */
2337 for (j = 0; j < ug_info->numQueuesTx; j++) {
2338 /* Allocate in multiple of
2339 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2340 according to spec */
18a8e864 2341 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
ce973b14
LY		 2342 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2343 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
18a8e864 2344 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
ce973b14
LY		 2345 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2346 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2347 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2348 u32 align = 4;
2349 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2350 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2351 ugeth->tx_bd_ring_offset[j] =
6fee40e9 2352 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
04b588d7 2353
ce973b14
LY		 2354 if (ugeth->tx_bd_ring_offset[j] != 0)
2355 ugeth->p_tx_bd_ring[j] =
6fee40e9 2356 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
ce973b14
LY		 2357 align) & ~(align - 1));
2358 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2359 ugeth->tx_bd_ring_offset[j] =
2360 qe_muram_alloc(length,
2361 UCC_GETH_TX_BD_RING_ALIGNMENT);
4c35630c 2362 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
ce973b14 2363 ugeth->p_tx_bd_ring[j] =
6fee40e9 2364 (u8 __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2365 tx_bd_ring_offset[j]);
2366 }
2367 if (!ugeth->p_tx_bd_ring[j]) {
890de95e
LY		 2368 if (netif_msg_ifup(ugeth))
2369 ugeth_err
2370 ("%s: Can not allocate memory for Tx bd rings.",
b39d66a8 2371 __func__);
ce973b14
LY		 2372 return -ENOMEM;
2373 }
2374 /* Zero unused end of bd ring, according to spec */
6fee40e9
AF		 2375 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2376 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
18a8e864 2377 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
ce973b14
LY		 2378 }
2379
2380 /* Allocate Rx bds */
2381 for (j = 0; j < ug_info->numQueuesRx; j++) {
18a8e864 2382 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
ce973b14
LY		 2383 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2384 u32 align = 4;
2385 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2386 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2387 ugeth->rx_bd_ring_offset[j] =
6fee40e9 2388 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
ce973b14
LY		 2389 if (ugeth->rx_bd_ring_offset[j] != 0)
2390 ugeth->p_rx_bd_ring[j] =
6fee40e9 2391 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
ce973b14
LY		 2392 align) & ~(align - 1));
2393 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2394 ugeth->rx_bd_ring_offset[j] =
2395 qe_muram_alloc(length,
2396 UCC_GETH_RX_BD_RING_ALIGNMENT);
4c35630c 2397 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
ce973b14 2398 ugeth->p_rx_bd_ring[j] =
6fee40e9 2399 (u8 __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2400 rx_bd_ring_offset[j]);
2401 }
2402 if (!ugeth->p_rx_bd_ring[j]) {
890de95e
LY		 2403 if (netif_msg_ifup(ugeth))
2404 ugeth_err
2405 ("%s: Can not allocate memory for Rx bd rings.",
b39d66a8 2406 __func__);
ce973b14
LY		 2407 return -ENOMEM;
2408 }
2409 }
2410
2411 /* Init Tx bds */
2412 for (j = 0; j < ug_info->numQueuesTx; j++) {
2413 /* Setup the skbuff rings */
04b588d7
AD		 2414 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2415 ugeth->ug_info->bdRingLenTx[j],
2416 GFP_KERNEL);
ce973b14
LY		 2417
2418 if (ugeth->tx_skbuff[j] == NULL) {
890de95e
LY		 2419 if (netif_msg_ifup(ugeth))
2420 ugeth_err("%s: Could not allocate tx_skbuff",
b39d66a8 2421 __func__);
ce973b14
LY		 2422 return -ENOMEM;
2423 }
2424
2425 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2426 ugeth->tx_skbuff[j][i] = NULL;
2427
2428 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2429 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2430 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
18a8e864 2431 /* clear bd buffer */
6fee40e9 2432 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
18a8e864 2433 /* set bd status and length */
6fee40e9 2434 out_be32((u32 __iomem *)bd, 0);
18a8e864 2435 bd += sizeof(struct qe_bd);
ce973b14 2436 }
18a8e864
LY		 2437 bd -= sizeof(struct qe_bd);
2438 /* set bd status and length */
6fee40e9 2439 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
ce973b14
LY		 2440 }
2441
2442 /* Init Rx bds */
2443 for (j = 0; j < ug_info->numQueuesRx; j++) {
2444 /* Setup the skbuff rings */
04b588d7
AD		 2445 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2446 ugeth->ug_info->bdRingLenRx[j],
2447 GFP_KERNEL);
ce973b14
LY		 2448
2449 if (ugeth->rx_skbuff[j] == NULL) {
890de95e
LY		 2450 if (netif_msg_ifup(ugeth))
2451 ugeth_err("%s: Could not allocate rx_skbuff",
b39d66a8 2452 __func__);
ce973b14
LY		 2453 return -ENOMEM;
2454 }
2455
2456 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2457 ugeth->rx_skbuff[j][i] = NULL;
2458
2459 ugeth->skb_currx[j] = 0;
2460 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2461 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
18a8e864 2462 /* set bd status and length */
6fee40e9 2463 out_be32((u32 __iomem *)bd, R_I);
18a8e864 2464 /* clear bd buffer */
6fee40e9 2465 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
18a8e864 2466 bd += sizeof(struct qe_bd);
ce973b14 2467 }
18a8e864
LY		 2468 bd -= sizeof(struct qe_bd);
2469 /* set bd status and length */
6fee40e9 2470 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
ce973b14
LY		 2471 }
2472
2473 /*
2474 * Global PRAM
2475 */
2476 /* Tx global PRAM */
2477 /* Allocate global tx parameter RAM page */
2478 ugeth->tx_glbl_pram_offset =
18a8e864 2479 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
ce973b14 2480 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2481 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
890de95e
LY		 2482 if (netif_msg_ifup(ugeth))
2483 ugeth_err
2484 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
b39d66a8 2485 __func__);
ce973b14
LY		 2486 return -ENOMEM;
2487 }
2488 ugeth->p_tx_glbl_pram =
6fee40e9 2489 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2490 tx_glbl_pram_offset);
2491 /* Zero out p_tx_glbl_pram */
6fee40e9 2492 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
ce973b14
LY		 2493
2494 /* Fill global PRAM */
2495
2496 /* TQPTR */
2497 /* Size varies with number of Tx threads */
2498 ugeth->thread_dat_tx_offset =
2499 qe_muram_alloc(numThreadsTxNumerical *
18a8e864 2500 sizeof(struct ucc_geth_thread_data_tx) +
ce973b14
LY		 2501 32 * (numThreadsTxNumerical == 1),
2502 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2503 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
890de95e
LY		 2504 if (netif_msg_ifup(ugeth))
2505 ugeth_err
2506 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
b39d66a8 2507 __func__);
ce973b14
LY		 2508 return -ENOMEM;
2509 }
2510
2511 ugeth->p_thread_data_tx =
6fee40e9 2512 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2513 thread_dat_tx_offset);
2514 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2515
2516 /* vtagtable */
2517 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2518 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2519 ug_info->vtagtable[i]);
2520
2521 /* iphoffset */
2522 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
6fee40e9
AF		 2523 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2524 ug_info->iphoffset[i]);
ce973b14
LY		 2525
2526 /* SQPTR */
2527 /* Size varies with number of Tx queues */
2528 ugeth->send_q_mem_reg_offset =
2529 qe_muram_alloc(ug_info->numQueuesTx *
18a8e864 2530 sizeof(struct ucc_geth_send_queue_qd),
ce973b14 2531 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
4c35630c 2532 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
890de95e
LY		 2533 if (netif_msg_ifup(ugeth))
2534 ugeth_err
2535 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
b39d66a8 2536 __func__);
ce973b14
LY		 2537 return -ENOMEM;
2538 }
2539
2540 ugeth->p_send_q_mem_reg =
6fee40e9 2541 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2542 send_q_mem_reg_offset);
2543 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2544
2545 /* Setup the table */
2546 /* Assume BD rings are already established */
2547 for (i = 0; i < ug_info->numQueuesTx; i++) {
2548 endOfRing =
2549 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
18a8e864 2550 1) * sizeof(struct qe_bd);
ce973b14
LY		 2551 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2552 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2553 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2554 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2555 last_bd_completed_address,
2556 (u32) virt_to_phys(endOfRing));
2557 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2558 MEM_PART_MURAM) {
2559 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2560 (u32) immrbar_virt_to_phys(ugeth->
2561 p_tx_bd_ring[i]));
2562 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2563 last_bd_completed_address,
2564 (u32) immrbar_virt_to_phys(endOfRing));
2565 }
2566 }
2567
2568 /* schedulerbasepointer */
2569
2570 if (ug_info->numQueuesTx > 1) {
2571 /* scheduler exists only if more than 1 tx queue */
2572 ugeth->scheduler_offset =
18a8e864 2573 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
ce973b14 2574 UCC_GETH_SCHEDULER_ALIGNMENT);
4c35630c 2575 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
890de95e
LY		 2576 if (netif_msg_ifup(ugeth))
2577 ugeth_err
2578 ("%s: Can not allocate DPRAM memory for p_scheduler.",
b39d66a8 2579 __func__);
ce973b14
LY		 2580 return -ENOMEM;
2581 }
2582
2583 ugeth->p_scheduler =
6fee40e9 2584 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2585 scheduler_offset);
2586 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2587 ugeth->scheduler_offset);
2588 /* Zero out p_scheduler */
6fee40e9 2589 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
ce973b14
LY		 2590
2591 /* Set values in scheduler */
2592 out_be32(&ugeth->p_scheduler->mblinterval,
2593 ug_info->mblinterval);
2594 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2595 ug_info->nortsrbytetime);
6fee40e9
AF		 2596 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2597 out_8(&ugeth->p_scheduler->strictpriorityq,
2598 ug_info->strictpriorityq);
2599 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2600 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
ce973b14 2601 for (i = 0; i < NUM_TX_QUEUES; i++)
6fee40e9
AF		 2602 out_8(&ugeth->p_scheduler->weightfactor[i],
2603 ug_info->weightfactor[i]);
ce973b14
LY		 2604
2605 /* Set pointers to cpucount registers in scheduler */
2606 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2607 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2608 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2609 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2610 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2611 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2612 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2613 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2614 }
2615
2616 /* schedulerbasepointer */
2617 /* TxRMON_PTR (statistics) */
2618 if (ug_info->
2619 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2620 ugeth->tx_fw_statistics_pram_offset =
2621 qe_muram_alloc(sizeof
18a8e864 2622 (struct ucc_geth_tx_firmware_statistics_pram),
ce973b14 2623 UCC_GETH_TX_STATISTICS_ALIGNMENT);
4c35630c 2624 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
890de95e
LY		 2625 if (netif_msg_ifup(ugeth))
2626 ugeth_err
2627 ("%s: Can not allocate DPRAM memory for"
2628 " p_tx_fw_statistics_pram.",
b39d66a8 2629 __func__);
ce973b14
LY		 2630 return -ENOMEM;
2631 }
2632 ugeth->p_tx_fw_statistics_pram =
6fee40e9 2633 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2634 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2635 /* Zero out p_tx_fw_statistics_pram */
6fee40e9 2636 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
18a8e864 2637 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
ce973b14
LY		 2638 }
2639
2640 /* temoder */
2641 /* Already has speed set */
2642
2643 if (ug_info->numQueuesTx > 1)
2644 temoder |= TEMODER_SCHEDULER_ENABLE;
2645 if (ug_info->ipCheckSumGenerate)
2646 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2647 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2648 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2649
2650 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2651
2652 /* Function code register value to be used later */
6b0b594b 2653 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
ce973b14
LY		 2654 /* Required for QE */
2655
2656 /* function code register */
2657 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2658
2659 /* Rx global PRAM */
2660 /* Allocate global rx parameter RAM page */
2661 ugeth->rx_glbl_pram_offset =
18a8e864 2662 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
ce973b14 2663 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2664 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
890de95e
LY		 2665 if (netif_msg_ifup(ugeth))
2666 ugeth_err
2667 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
b39d66a8 2668 __func__);
ce973b14
LY		 2669 return -ENOMEM;
2670 }
2671 ugeth->p_rx_glbl_pram =
6fee40e9 2672 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2673 rx_glbl_pram_offset);
2674 /* Zero out p_rx_glbl_pram */
6fee40e9 2675 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
ce973b14
LY		 2676
2677 /* Fill global PRAM */
2678
2679 /* RQPTR */
2680 /* Size varies with number of Rx threads */
2681 ugeth->thread_dat_rx_offset =
2682 qe_muram_alloc(numThreadsRxNumerical *
18a8e864 2683 sizeof(struct ucc_geth_thread_data_rx),
ce973b14 2684 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2685 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
890de95e
LY		 2686 if (netif_msg_ifup(ugeth))
2687 ugeth_err
2688 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
b39d66a8 2689 __func__);
ce973b14
LY		 2690 return -ENOMEM;
2691 }
2692
2693 ugeth->p_thread_data_rx =
6fee40e9 2694 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2695 thread_dat_rx_offset);
2696 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2697
2698 /* typeorlen */
2699 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2700
2701 /* rxrmonbaseptr (statistics) */
2702 if (ug_info->
2703 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2704 ugeth->rx_fw_statistics_pram_offset =
2705 qe_muram_alloc(sizeof
18a8e864 2706 (struct ucc_geth_rx_firmware_statistics_pram),
ce973b14 2707 UCC_GETH_RX_STATISTICS_ALIGNMENT);
4c35630c 2708 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
890de95e
LY		 2709 if (netif_msg_ifup(ugeth))
2710 ugeth_err
2711 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2712 " p_rx_fw_statistics_pram.", __func__);
ce973b14
LY		 2713 return -ENOMEM;
2714 }
2715 ugeth->p_rx_fw_statistics_pram =
6fee40e9 2716 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2717 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2718 /* Zero out p_rx_fw_statistics_pram */
6fee40e9 2719 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
18a8e864 2720 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
ce973b14
LY		 2721 }
2722
2723 /* intCoalescingPtr */
2724
2725 /* Size varies with number of Rx queues */
2726 ugeth->rx_irq_coalescing_tbl_offset =
2727 qe_muram_alloc(ug_info->numQueuesRx *
7563907e
MB		 2728 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2729 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
4c35630c 2730 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
890de95e
LY		 2731 if (netif_msg_ifup(ugeth))
2732 ugeth_err
2733 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2734 " p_rx_irq_coalescing_tbl.", __func__);
ce973b14
LY		 2735 return -ENOMEM;
2736 }
2737
2738 ugeth->p_rx_irq_coalescing_tbl =
6fee40e9 2739 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
ce973b14
LY		 2740 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2741 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2742 ugeth->rx_irq_coalescing_tbl_offset);
2743
2744 /* Fill interrupt coalescing table */
2745 for (i = 0; i < ug_info->numQueuesRx; i++) {
2746 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2747 interruptcoalescingmaxvalue,
2748 ug_info->interruptcoalescingmaxvalue[i]);
2749 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2750 interruptcoalescingcounter,
2751 ug_info->interruptcoalescingmaxvalue[i]);
2752 }
2753
2754 /* MRBLR */
2755 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2756 &ugeth->p_rx_glbl_pram->mrblr);
2757 /* MFLR */
2758 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2759 /* MINFLR */
2760 init_min_frame_len(ug_info->minFrameLength,
2761 &ugeth->p_rx_glbl_pram->minflr,
2762 &ugeth->p_rx_glbl_pram->mrblr);
2763 /* MAXD1 */
2764 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2765 /* MAXD2 */
2766 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2767
2768 /* l2qt */
2769 l2qt = 0;
2770 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2771 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2772 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2773
2774 /* l3qt */
2775 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2776 l3qt = 0;
2777 for (i = 0; i < 8; i++)
2778 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
18a8e864 2779 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
ce973b14
LY		 2780 }
2781
2782 /* vlantype */
2783 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2784
2785 /* vlantci */
2786 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2787
2788 /* ecamptr */
2789 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2790
2791 /* RBDQPTR */
2792 /* Size varies with number of Rx queues */
2793 ugeth->rx_bd_qs_tbl_offset =
2794 qe_muram_alloc(ug_info->numQueuesRx *
18a8e864
LY		 2795 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2796 sizeof(struct ucc_geth_rx_prefetched_bds)),
ce973b14 2797 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
4c35630c 2798 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
890de95e
LY		 2799 if (netif_msg_ifup(ugeth))
2800 ugeth_err
2801 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
b39d66a8 2802 __func__);
ce973b14
LY		 2803 return -ENOMEM;
2804 }
2805
2806 ugeth->p_rx_bd_qs_tbl =
6fee40e9 2807 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2808 rx_bd_qs_tbl_offset);
2809 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2810 /* Zero out p_rx_bd_qs_tbl */
6fee40e9 2811 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
ce973b14 2812 0,
18a8e864
LY		 2813 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2814 sizeof(struct ucc_geth_rx_prefetched_bds)));
ce973b14
LY		 2815
2816 /* Setup the table */
2817 /* Assume BD rings are already established */
2818 for (i = 0; i < ug_info->numQueuesRx; i++) {
2819 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2820 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2821 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2822 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2823 MEM_PART_MURAM) {
2824 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2825 (u32) immrbar_virt_to_phys(ugeth->
2826 p_rx_bd_ring[i]));
2827 }
2828 /* rest of fields handled by QE */
2829 }
2830
2831 /* remoder */
2832 /* Already has speed set */
2833
2834 if (ugeth->rx_extended_features)
2835 remoder |= REMODER_RX_EXTENDED_FEATURES;
2836 if (ug_info->rxExtendedFiltering)
2837 remoder |= REMODER_RX_EXTENDED_FILTERING;
2838 if (ug_info->dynamicMaxFrameLength)
2839 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2840 if (ug_info->dynamicMinFrameLength)
2841 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2842 remoder |=
2843 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2844 remoder |=
2845 ug_info->
2846 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2847 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2848 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2849 if (ug_info->ipCheckSumCheck)
2850 remoder |= REMODER_IP_CHECKSUM_CHECK;
2851 if (ug_info->ipAddressAlignment)
2852 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2853 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2854
2855 /* Note that this function must be called */
2856 /* ONLY AFTER p_tx_fw_statistics_pram */
2857 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2858 init_firmware_statistics_gathering_mode((ug_info->
2859 statisticsMode &
2860 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2861 (ug_info->statisticsMode &
2862 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2863 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2864 ugeth->tx_fw_statistics_pram_offset,
2865 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2866 ugeth->rx_fw_statistics_pram_offset,
2867 &ugeth->p_tx_glbl_pram->temoder,
2868 &ugeth->p_rx_glbl_pram->remoder);
2869
2870 /* function code register */
6fee40e9 2871 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
ce973b14
LY		 2872
2873 /* initialize extended filtering */
2874 if (ug_info->rxExtendedFiltering) {
2875 if (!ug_info->extendedFilteringChainPointer) {
890de95e
LY		 2876 if (netif_msg_ifup(ugeth))
2877 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
b39d66a8 2878 __func__);
ce973b14
LY		 2879 return -EINVAL;
2880 }
2881
2882 /* Allocate memory for extended filtering Mode Global
2883 Parameters */
2884 ugeth->exf_glbl_param_offset =
18a8e864 2885 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
ce973b14 2886 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
4c35630c 2887 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
890de95e
LY		 2888 if (netif_msg_ifup(ugeth))
2889 ugeth_err
2890 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2891 " p_exf_glbl_param.", __func__);
ce973b14
LY		 2892 return -ENOMEM;
2893 }
2894
2895 ugeth->p_exf_glbl_param =
6fee40e9 2896 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2897 exf_glbl_param_offset);
2898 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2899 ugeth->exf_glbl_param_offset);
2900 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2901 (u32) ug_info->extendedFilteringChainPointer);
2902
2903 } else { /* initialize 82xx style address filtering */
2904
2905 /* Init individual address recognition registers to disabled */
2906
2907 for (j = 0; j < NUM_OF_PADDRS; j++)
2908 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2909
ce973b14 2910 p_82xx_addr_filt =
6fee40e9 2911 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2912 p_rx_glbl_pram->addressfiltering;
2913
2914 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2915 ENET_ADDR_TYPE_GROUP);
2916 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2917 ENET_ADDR_TYPE_INDIVIDUAL);
2918 }
2919
2920 /*
2921 * Initialize UCC at QE level
2922 */
2923
2924 command = QE_INIT_TX_RX;
2925
2926 /* Allocate shadow InitEnet command parameter structure.
2927 * This is needed because after the InitEnet command is executed,
2928 * the structure in DPRAM is released, because DPRAM is a premium
2929 * resource.
2930 * This shadow structure keeps a copy of what was done so that the
2931 * allocated resources can be released when the channel is freed.
2932 */
2933 if (!(ugeth->p_init_enet_param_shadow =
04b588d7 2934 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
890de95e
LY		 2935 if (netif_msg_ifup(ugeth))
2936 ugeth_err
2937 ("%s: Can not allocate memory for"
b39d66a8 2938 " p_UccInitEnetParamShadows.", __func__);
ce973b14
LY		 2939 return -ENOMEM;
2940 }
2941 /* Zero out *p_init_enet_param_shadow */
2942 memset((char *)ugeth->p_init_enet_param_shadow,
18a8e864 2943 0, sizeof(struct ucc_geth_init_pram));
ce973b14
LY		 2944
2945 /* Fill shadow InitEnet command parameter structure */
2946
2947 ugeth->p_init_enet_param_shadow->resinit1 =
2948 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2949 ugeth->p_init_enet_param_shadow->resinit2 =
2950 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2951 ugeth->p_init_enet_param_shadow->resinit3 =
2952 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2953 ugeth->p_init_enet_param_shadow->resinit4 =
2954 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2955 ugeth->p_init_enet_param_shadow->resinit5 =
2956 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2957 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2958 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2959 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2960 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2961
2962 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2963 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2964 if ((ug_info->largestexternallookupkeysize !=
2965 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
2966 && (ug_info->largestexternallookupkeysize !=
2967 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2968 && (ug_info->largestexternallookupkeysize !=
2969 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
890de95e
LY		 2970 if (netif_msg_ifup(ugeth))
2971 ugeth_err("%s: Invalid largest External Lookup Key Size.",
b39d66a8 2972 __func__);
ce973b14
LY		 2973 return -EINVAL;
2974 }
2975 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2976 ug_info->largestexternallookupkeysize;
18a8e864 2977 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 2978 if (ug_info->rxExtendedFiltering) {
2979 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2980 if (ug_info->largestexternallookupkeysize ==
2981 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2982 size +=
2983 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2984 if (ug_info->largestexternallookupkeysize ==
2985 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
2986 size +=
2987 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2988 }
2989
2990 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
2991 p_init_enet_param_shadow->rxthread[0]),
2992 (u8) (numThreadsRxNumerical + 1)
2993 /* Rx needs one extra for terminator */
2994 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
2995 ug_info->riscRx, 1)) != 0) {
890de95e
LY		 2996 if (netif_msg_ifup(ugeth))
2997 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 2998 __func__);
ce973b14
LY		 2999 return ret_val;
3000 }
3001
3002 ugeth->p_init_enet_param_shadow->txglobal =
3003 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3004 if ((ret_val =
3005 fill_init_enet_entries(ugeth,
3006 &(ugeth->p_init_enet_param_shadow->
3007 txthread[0]), numThreadsTxNumerical,
18a8e864 3008 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 3009 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3010 ug_info->riscTx, 0)) != 0) {
890de95e
LY		 3011 if (netif_msg_ifup(ugeth))
3012 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 3013 __func__);
ce973b14
LY		 3014 return ret_val;
3015 }
3016
3017 /* Load Rx bds with buffers */
3018 for (i = 0; i < ug_info->numQueuesRx; i++) {
3019 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
890de95e
LY		 3020 if (netif_msg_ifup(ugeth))
3021 ugeth_err("%s: Can not fill Rx bds with buffers.",
b39d66a8 3022 __func__);
ce973b14
LY		 3023 return ret_val;
3024 }
3025 }
3026
3027 /* Allocate InitEnet command parameter structure */
18a8e864 3028 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
4c35630c 3029 if (IS_ERR_VALUE(init_enet_pram_offset)) {
890de95e
LY		 3030 if (netif_msg_ifup(ugeth))
3031 ugeth_err
3032 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
b39d66a8 3033 __func__);
ce973b14
LY		 3034 return -ENOMEM;
3035 }
3036 p_init_enet_pram =
6fee40e9 3037 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
ce973b14
LY		 3038
3039 /* Copy shadow InitEnet command parameter structure into PRAM */
6fee40e9
AF		 3040 out_8(&p_init_enet_pram->resinit1,
3041 ugeth->p_init_enet_param_shadow->resinit1);
3042 out_8(&p_init_enet_pram->resinit2,
3043 ugeth->p_init_enet_param_shadow->resinit2);
3044 out_8(&p_init_enet_pram->resinit3,
3045 ugeth->p_init_enet_param_shadow->resinit3);
3046 out_8(&p_init_enet_pram->resinit4,
3047 ugeth->p_init_enet_param_shadow->resinit4);
ce973b14
LY		 3048 out_be16(&p_init_enet_pram->resinit5,
3049 ugeth->p_init_enet_param_shadow->resinit5);
6fee40e9
AF		 3050 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3051 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
ce973b14
LY		 3052 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3053 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3054 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3055 out_be32(&p_init_enet_pram->rxthread[i],
3056 ugeth->p_init_enet_param_shadow->rxthread[i]);
3057 out_be32(&p_init_enet_pram->txglobal,
3058 ugeth->p_init_enet_param_shadow->txglobal);
3059 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3060 out_be32(&p_init_enet_pram->txthread[i],
3061 ugeth->p_init_enet_param_shadow->txthread[i]);
3062
3063 /* Issue QE command */
3064 cecr_subblock =
3065 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 3066 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 3067 init_enet_pram_offset);
3068
3069 /* Free InitEnet command parameter */
3070 qe_muram_free(init_enet_pram_offset);
3071
3072 return 0;
3073}
3074
ce973b14
LY		 3075/* This is called by the kernel when a frame is ready for transmission. */
3076/* It is pointed to by the dev->hard_start_xmit function pointer */
3077static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3078{
18a8e864 3079 struct ucc_geth_private *ugeth = netdev_priv(dev);
d5b9049d
MR		 3080#ifdef CONFIG_UGETH_TX_ON_DEMAND
3081 struct ucc_fast_private *uccf;
3082#endif
6fee40e9 3083 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3084 u32 bd_status;
3085 u8 txQ = 0;
3086
b39d66a8 3087 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 3088
3089 spin_lock_irq(&ugeth->lock);
3090
09f75cd7 3091 dev->stats.tx_bytes += skb->len;
ce973b14
LY		 3092
3093 /* Start from the next BD that should be filled */
3094 bd = ugeth->txBd[txQ];
6fee40e9 3095 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3096 /* Save the skb pointer so we can free it later */
3097 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3098
3099 /* Update the current skb pointer (wrapping if this was the last) */
3100 ugeth->skb_curtx[txQ] =
3101 (ugeth->skb_curtx[txQ] +
3102 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3103
3104 /* set up the buffer descriptor */
6fee40e9 3105 out_be32(&((struct qe_bd __iomem *)bd)->buf,
7f80202b
AF		 3106 dma_map_single(&ugeth->dev->dev, skb->data,
3107 skb->len, DMA_TO_DEVICE));
ce973b14 3108
18a8e864 3109 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
ce973b14
LY		 3110
3111 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3112
18a8e864 3113 /* set bd status and length */
6fee40e9 3114 out_be32((u32 __iomem *)bd, bd_status);
ce973b14
LY		 3115
3116 dev->trans_start = jiffies;
3117
3118 /* Move to next BD in the ring */
3119 if (!(bd_status & T_W))
a394f013 3120 bd += sizeof(struct qe_bd);
ce973b14 3121 else
a394f013 3122 bd = ugeth->p_tx_bd_ring[txQ];
ce973b14
LY		 3123
3124 /* If the next BD still needs to be cleaned up, then the bds
3125 are full. We need to tell the kernel to stop sending us stuff. */
3126 if (bd == ugeth->confBd[txQ]) {
3127 if (!netif_queue_stopped(dev))
3128 netif_stop_queue(dev);
3129 }
3130
a394f013
LY		 3131 ugeth->txBd[txQ] = bd;
3132
ce973b14
LY		 3133 if (ugeth->p_scheduler) {
3134 ugeth->cpucount[txQ]++;
3135 /* Indicate to QE that there are more Tx bds ready for
3136 transmission */
3137 /* This is done by writing a running counter of the bd
3138 count to the scheduler PRAM. */
3139 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3140 }
3141
d5b9049d
MR		 3142#ifdef CONFIG_UGETH_TX_ON_DEMAND
3143 uccf = ugeth->uccf;
3144 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3145#endif
ce973b14
LY		 3146 spin_unlock_irq(&ugeth->lock);
3147
6f6881b8 3148 return 0;
ce973b14
LY		 3149}
3150
18a8e864 3151static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
ce973b14
LY		 3152{
3153 struct sk_buff *skb;
6fee40e9 3154 u8 __iomem *bd;
ce973b14
LY		 3155 u16 length, howmany = 0;
3156 u32 bd_status;
3157 u8 *bdBuffer;
4b8fdefa 3158 struct net_device *dev;
ce973b14 3159
b39d66a8 3160 ugeth_vdbg("%s: IN", __func__);
ce973b14 3161
88a15f2e
EM		 3162 dev = ugeth->dev;
3163
ce973b14
LY		 3164 /* collect received buffers */
3165 bd = ugeth->rxBd[rxQ];
3166
6fee40e9 3167 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3168
3169 /* while there are received buffers and BD is full (~R_E) */
3170 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
6fee40e9 3171 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
ce973b14
LY		 3172 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3173 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3174
3175 /* determine whether buffer is first, last, first and last
3176 (single buffer frame) or middle (not first and not last) */
3177 if (!skb ||
3178 (!(bd_status & (R_F | R_L))) ||
3179 (bd_status & R_ERRORS_FATAL)) {
890de95e
LY		 3180 if (netif_msg_rx_err(ugeth))
3181 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
b39d66a8 3182 __func__, __LINE__, (u32) skb);
ce973b14
LY		 3183 if (skb)
3184 dev_kfree_skb_any(skb);
3185
3186 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
09f75cd7 3187 dev->stats.rx_dropped++;
ce973b14 3188 } else {
09f75cd7 3189 dev->stats.rx_packets++;
ce973b14
LY		 3190 howmany++;
3191
3192 /* Prep the skb for the packet */
3193 skb_put(skb, length);
3194
3195 /* Tell the skb what kind of packet this is */
3196 skb->protocol = eth_type_trans(skb, ugeth->dev);
3197
09f75cd7 3198 dev->stats.rx_bytes += length;
ce973b14 3199 /* Send the packet up the stack */
ce973b14 3200 netif_receive_skb(skb);
ce973b14
LY		 3201 }
3202
ce973b14
LY		 3203 skb = get_new_skb(ugeth, bd);
3204 if (!skb) {
890de95e 3205 if (netif_msg_rx_err(ugeth))
b39d66a8 3206 ugeth_warn("%s: No Rx Data Buffer", __func__);
09f75cd7 3207 dev->stats.rx_dropped++;
ce973b14
LY		 3208 break;
3209 }
3210
3211 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3212
3213 /* update to point at the next skb */
3214 ugeth->skb_currx[rxQ] =
3215 (ugeth->skb_currx[rxQ] +
3216 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3217
3218 if (bd_status & R_W)
3219 bd = ugeth->p_rx_bd_ring[rxQ];
3220 else
18a8e864 3221 bd += sizeof(struct qe_bd);
ce973b14 3222
6fee40e9 3223 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3224 }
3225
3226 ugeth->rxBd[rxQ] = bd;
ce973b14
LY		 3227 return howmany;
3228}
3229
3230static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3231{
3232 /* Start from the next BD that should be filled */
18a8e864 3233 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9 3234 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3235 u32 bd_status;
3236
3237 bd = ugeth->confBd[txQ];
6fee40e9 3238 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3239
3240 /* Normal processing. */
3241 while ((bd_status & T_R) == 0) {
3242 /* BD contains already transmitted buffer. */
3243 /* Handle the transmitted buffer and release */
3244 /* the BD to be used with the current frame */
3245
a394f013 3246 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
ce973b14
LY		 3247 break;
3248
09f75cd7 3249 dev->stats.tx_packets++;
ce973b14
LY		 3250
3251 /* Free the sk buffer associated with this TxBD */
3252 dev_kfree_skb_irq(ugeth->
3253 tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3254 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3255 ugeth->skb_dirtytx[txQ] =
3256 (ugeth->skb_dirtytx[txQ] +
3257 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3258
3259 /* We freed a buffer, so now we can restart transmission */
3260 if (netif_queue_stopped(dev))
3261 netif_wake_queue(dev);
3262
3263 /* Advance the confirmation BD pointer */
3264 if (!(bd_status & T_W))
a394f013 3265 bd += sizeof(struct qe_bd);
ce973b14 3266 else
a394f013 3267 bd = ugeth->p_tx_bd_ring[txQ];
6fee40e9 3268 bd_status = in_be32((u32 __iomem *)bd);
ce973b14 3269 }
a394f013 3270 ugeth->confBd[txQ] = bd;
ce973b14
LY		 3271 return 0;
3272}
3273
bea3348e 3274static int ucc_geth_poll(struct napi_struct *napi, int budget)
ce973b14 3275{
bea3348e
SH		 3276 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3277 struct net_device *dev = ugeth->dev;
702ff12c 3278 struct ucc_geth_info *ug_info;
bea3348e 3279 int howmany, i;
ce973b14 3280
702ff12c
MR		 3281 ug_info = ugeth->ug_info;
3282
702ff12c 3283 howmany = 0;
bea3348e
SH		 3284 for (i = 0; i < ug_info->numQueuesRx; i++)
3285 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
702ff12c 3286
bea3348e
SH		 3287 if (howmany < budget) {
3288 struct ucc_fast_private *uccf;
3289 u32 uccm;
ce973b14 3290
908a7a16 3291 netif_rx_complete(napi);
702ff12c
MR		 3292 uccf = ugeth->uccf;
3293 uccm = in_be32(uccf->p_uccm);
3294 uccm |= UCCE_RX_EVENTS;
3295 out_be32(uccf->p_uccm, uccm);
3296 }
ce973b14 3297
bea3348e 3298 return howmany;
ce973b14 3299}
ce973b14 3300
7d12e780 3301static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
ce973b14 3302{
06efcad0 3303 struct net_device *dev = info;
18a8e864
LY		 3304 struct ucc_geth_private *ugeth = netdev_priv(dev);
3305 struct ucc_fast_private *uccf;
3306 struct ucc_geth_info *ug_info;
702ff12c
MR		 3307 register u32 ucce;
3308 register u32 uccm;
702ff12c
MR		 3309 register u32 tx_mask;
3310 u8 i;
ce973b14 3311
b39d66a8 3312 ugeth_vdbg("%s: IN", __func__);
ce973b14 3313
ce973b14
LY		 3314 uccf = ugeth->uccf;
3315 ug_info = ugeth->ug_info;
3316
702ff12c
MR		 3317 /* read and clear events */
3318 ucce = (u32) in_be32(uccf->p_ucce);
3319 uccm = (u32) in_be32(uccf->p_uccm);
3320 ucce &= uccm;
3321 out_be32(uccf->p_ucce, ucce);
ce973b14 3322
702ff12c
MR		 3323 /* check for receive events that require processing */
3324 if (ucce & UCCE_RX_EVENTS) {
908a7a16 3325 if (netif_rx_schedule_prep(&ugeth->napi)) {
bea3348e 3326 uccm &= ~UCCE_RX_EVENTS;
702ff12c 3327 out_be32(uccf->p_uccm, uccm);
908a7a16 3328 __netif_rx_schedule(&ugeth->napi);
702ff12c 3329 }
702ff12c 3330 }
ce973b14 3331
702ff12c
MR		 3332 /* Tx event processing */
3333 if (ucce & UCCE_TX_EVENTS) {
3334 spin_lock(&ugeth->lock);
3335 tx_mask = UCCE_TXBF_SINGLE_MASK;
ce973b14
LY		 3336 for (i = 0; i < ug_info->numQueuesTx; i++) {
3337 if (ucce & tx_mask)
3338 ucc_geth_tx(dev, i);
3339 ucce &= ~tx_mask;
3340 tx_mask <<= 1;
3341 }
702ff12c
MR		 3342 spin_unlock(&ugeth->lock);
3343 }
ce973b14 3344
702ff12c
MR		 3345 /* Errors and other events */
3346 if (ucce & UCCE_OTHER) {
ce973b14 3347 if (ucce & UCCE_BSY) {
09f75cd7 3348 dev->stats.rx_errors++;
ce973b14 3349 }
702ff12c 3350 if (ucce & UCCE_TXE) {
09f75cd7 3351 dev->stats.tx_errors++;
ce973b14
LY		 3352 }
3353 }
ce973b14
LY		 3354
3355 return IRQ_HANDLED;
3356}
3357
26d29ea7
AV		 3358#ifdef CONFIG_NET_POLL_CONTROLLER
3359/*
3360 * Polling 'interrupt' - used by things like netconsole to send skbs
3361 * without having to re-enable interrupts. It's not called while
3362 * the interrupt routine is executing.
3363 */
3364static void ucc_netpoll(struct net_device *dev)
3365{
3366 struct ucc_geth_private *ugeth = netdev_priv(dev);
3367 int irq = ugeth->ug_info->uf_info.irq;
3368
3369 disable_irq(irq);
3370 ucc_geth_irq_handler(irq, dev);
3371 enable_irq(irq);
3372}
3373#endif /* CONFIG_NET_POLL_CONTROLLER */
3374
ce973b14
LY		 3375/* Called when something needs to use the ethernet device */
3376/* Returns 0 for success. */
3377static int ucc_geth_open(struct net_device *dev)
3378{
18a8e864 3379 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14
LY		 3380 int err;
3381
b39d66a8 3382 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 3383
3384 /* Test station address */
3385 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
890de95e
LY		 3386 if (netif_msg_ifup(ugeth))
3387 ugeth_err("%s: Multicast address used for station address"
b39d66a8 3388 " - is this what you wanted?", __func__);
ce973b14
LY		 3389 return -EINVAL;
3390 }
3391
728de4c9
KP		 3392 err = ucc_struct_init(ugeth);
3393 if (err) {
890de95e
LY		 3394 if (netif_msg_ifup(ugeth))
3395 ugeth_err("%s: Cannot configure internal struct, aborting.", dev->name);
3e73fc9a 3396 goto out_err_stop;
728de4c9
KP		 3397 }
3398
bea3348e 3399 napi_enable(&ugeth->napi);
1a342d22 3400
ce973b14
LY		 3401 err = ucc_geth_startup(ugeth);
3402 if (err) {
890de95e
LY		 3403 if (netif_msg_ifup(ugeth))
3404 ugeth_err("%s: Cannot configure net device, aborting.",
3405 dev->name);
bea3348e 3406 goto out_err;
ce973b14
LY		 3407 }
3408
3409 err = adjust_enet_interface(ugeth);
3410 if (err) {
890de95e
LY		 3411 if (netif_msg_ifup(ugeth))
3412 ugeth_err("%s: Cannot configure net device, aborting.",
3413 dev->name);
bea3348e 3414 goto out_err;
ce973b14
LY		 3415 }
3416
3417 /* Set MACSTNADDR1, MACSTNADDR2 */
3418 /* For more details see the hardware spec. */
3419 init_mac_station_addr_regs(dev->dev_addr[0],
3420 dev->dev_addr[1],
3421 dev->dev_addr[2],
3422 dev->dev_addr[3],
3423 dev->dev_addr[4],
3424 dev->dev_addr[5],
3425 &ugeth->ug_regs->macstnaddr1,
3426 &ugeth->ug_regs->macstnaddr2);
3427
3428 err = init_phy(dev);
3429 if (err) {
890de95e
LY		 3430 if (netif_msg_ifup(ugeth))
3431 ugeth_err("%s: Cannot initialize PHY, aborting.", dev->name);
bea3348e 3432 goto out_err;
ce973b14 3433 }
728de4c9
KP		 3434
3435 phy_start(ugeth->phydev);
3436
67c2fb8f 3437 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
ce973b14 3438 if (err) {
890de95e 3439 if (netif_msg_ifup(ugeth))
67c2fb8f 3440 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
bea3348e 3441 goto out_err;
ce973b14 3442 }
ce973b14 3443
67c2fb8f
AV		 3444 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3445 0, "UCC Geth", dev);
ce973b14 3446 if (err) {
890de95e 3447 if (netif_msg_ifup(ugeth))
67c2fb8f
AV		 3448 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3449 dev->name);
bea3348e 3450 goto out_err;
ce973b14
LY		 3451 }
3452
3453 netif_start_queue(dev);
3454
3455 return err;
bea3348e
SH		 3456
3457out_err:
bea3348e 3458 napi_disable(&ugeth->napi);
3e73fc9a 3459out_err_stop:
ba574696 3460 ucc_geth_stop(ugeth);
bea3348e 3461 return err;
ce973b14
LY		 3462}
3463
3464/* Stops the kernel queue, and halts the controller */
3465static int ucc_geth_close(struct net_device *dev)
3466{
18a8e864 3467 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14 3468
b39d66a8 3469 ugeth_vdbg("%s: IN", __func__);
ce973b14 3470
bea3348e 3471 napi_disable(&ugeth->napi);
bea3348e 3472
ce973b14
LY		 3473 ucc_geth_stop(ugeth);
3474
67c2fb8f
AV		 3475 free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev);
3476
728de4c9
KP		 3477 phy_disconnect(ugeth->phydev);
3478 ugeth->phydev = NULL;
ce973b14
LY		 3479
3480 netif_stop_queue(dev);
3481
3482 return 0;
3483}
3484
fdb614c2
AV		 3485/* Reopen device. This will reset the MAC and PHY. */
3486static void ucc_geth_timeout_work(struct work_struct *work)
3487{
3488 struct ucc_geth_private *ugeth;
3489 struct net_device *dev;
3490
3491 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3492 dev = ugeth->dev;
3493
3494 ugeth_vdbg("%s: IN", __func__);
3495
3496 dev->stats.tx_errors++;
3497
3498 ugeth_dump_regs(ugeth);
3499
3500 if (dev->flags & IFF_UP) {
3501 /*
3502 * Must reset MAC *and* PHY. This is done by reopening
3503 * the device.
3504 */
3505 ucc_geth_close(dev);
3506 ucc_geth_open(dev);
3507 }
3508
3509 netif_tx_schedule_all(dev);
3510}
3511
3512/*
3513 * ucc_geth_timeout gets called when a packet has not been
3514 * transmitted after a set amount of time.
3515 */
3516static void ucc_geth_timeout(struct net_device *dev)
3517{
3518 struct ucc_geth_private *ugeth = netdev_priv(dev);
3519
3520 netif_carrier_off(dev);
3521 schedule_work(&ugeth->timeout_work);
3522}
3523
4e19b5c1 3524static phy_interface_t to_phy_interface(const char *phy_connection_type)
728de4c9 3525{
4e19b5c1 3526 if (strcasecmp(phy_connection_type, "mii") == 0)
728de4c9 3527 return PHY_INTERFACE_MODE_MII;
4e19b5c1 3528 if (strcasecmp(phy_connection_type, "gmii") == 0)
728de4c9 3529 return PHY_INTERFACE_MODE_GMII;
4e19b5c1 3530 if (strcasecmp(phy_connection_type, "tbi") == 0)
728de4c9 3531 return PHY_INTERFACE_MODE_TBI;
4e19b5c1 3532 if (strcasecmp(phy_connection_type, "rmii") == 0)
728de4c9 3533 return PHY_INTERFACE_MODE_RMII;
4e19b5c1 3534 if (strcasecmp(phy_connection_type, "rgmii") == 0)
728de4c9 3535 return PHY_INTERFACE_MODE_RGMII;
4e19b5c1 3536 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
728de4c9 3537 return PHY_INTERFACE_MODE_RGMII_ID;
bd0ceaab
KP		 3538 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3539 return PHY_INTERFACE_MODE_RGMII_TXID;
3540 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3541 return PHY_INTERFACE_MODE_RGMII_RXID;
4e19b5c1 3542 if (strcasecmp(phy_connection_type, "rtbi") == 0)
728de4c9
KP		 3543 return PHY_INTERFACE_MODE_RTBI;
3544
3545 return PHY_INTERFACE_MODE_MII;
3546}
3547
18a8e864 3548static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
ce973b14 3549{
18a8e864
LY		 3550 struct device *device = &ofdev->dev;
3551 struct device_node *np = ofdev->node;
728de4c9 3552 struct device_node *mdio;
ce973b14
LY		 3553 struct net_device *dev = NULL;
3554 struct ucc_geth_private *ugeth = NULL;
3555 struct ucc_geth_info *ug_info;
18a8e864
LY		 3556 struct resource res;
3557 struct device_node *phy;
728de4c9 3558 int err, ucc_num, max_speed = 0;
18a8e864 3559 const phandle *ph;
3d137fdd 3560 const u32 *fixed_link;
18a8e864 3561 const unsigned int *prop;
9fb1e350 3562 const char *sprop;
9b4c7a4e 3563 const void *mac_addr;
728de4c9
KP		 3564 phy_interface_t phy_interface;
3565 static const int enet_to_speed[] = {
3566 SPEED_10, SPEED_10, SPEED_10,
3567 SPEED_100, SPEED_100, SPEED_100,
3568 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3569 };
3570 static const phy_interface_t enet_to_phy_interface[] = {
3571 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3572 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3573 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3574 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3575 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3576 };
ce973b14 3577
b39d66a8 3578 ugeth_vdbg("%s: IN", __func__);
ce973b14 3579
56626f33
AV		 3580 prop = of_get_property(np, "cell-index", NULL);
3581 if (!prop) {
3582 prop = of_get_property(np, "device-id", NULL);
3583 if (!prop)
3584 return -ENODEV;
3585 }
3586
18a8e864
LY		 3587 ucc_num = *prop - 1;
3588 if ((ucc_num < 0) || (ucc_num > 7))
3589 return -ENODEV;
3590
3591 ug_info = &ugeth_info[ucc_num];
890de95e
LY		 3592 if (ug_info == NULL) {
3593 if (netif_msg_probe(&debug))
3594 ugeth_err("%s: [%d] Missing additional data!",
b39d66a8 3595 __func__, ucc_num);
890de95e
LY		 3596 return -ENODEV;
3597 }
3598
18a8e864 3599 ug_info->uf_info.ucc_num = ucc_num;
728de4c9 3600
9fb1e350
TT		 3601 sprop = of_get_property(np, "rx-clock-name", NULL);
3602 if (sprop) {
3603 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3604 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3605 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3606 printk(KERN_ERR
3607 "ucc_geth: invalid rx-clock-name property\n");
3608 return -EINVAL;
3609 }
3610 } else {
3611 prop = of_get_property(np, "rx-clock", NULL);
3612 if (!prop) {
3613 /* If both rx-clock-name and rx-clock are missing,
3614 we want to tell people to use rx-clock-name. */
3615 printk(KERN_ERR
3616 "ucc_geth: missing rx-clock-name property\n");
3617 return -EINVAL;
3618 }
3619 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3620 printk(KERN_ERR
3621 "ucc_geth: invalid rx-clock propperty\n");
3622 return -EINVAL;
3623 }
3624 ug_info->uf_info.rx_clock = *prop;
3625 }
3626
3627 sprop = of_get_property(np, "tx-clock-name", NULL);
3628 if (sprop) {
3629 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3630 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3631 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3632 printk(KERN_ERR
3633 "ucc_geth: invalid tx-clock-name property\n");
3634 return -EINVAL;
3635 }
3636 } else {
e410553f 3637 prop = of_get_property(np, "tx-clock", NULL);
9fb1e350
TT		 3638 if (!prop) {
3639 printk(KERN_ERR
3640 "ucc_geth: mising tx-clock-name property\n");
3641 return -EINVAL;
3642 }
3643 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3644 printk(KERN_ERR
3645 "ucc_geth: invalid tx-clock property\n");
3646 return -EINVAL;
3647 }
3648 ug_info->uf_info.tx_clock = *prop;
3649 }
3650
18a8e864
LY		 3651 err = of_address_to_resource(np, 0, &res);
3652 if (err)
3653 return -EINVAL;
3654
3655 ug_info->uf_info.regs = res.start;
3656 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3d137fdd
JT		 3657 fixed_link = of_get_property(np, "fixed-link", NULL);
3658 if (fixed_link) {
f38d1008 3659 snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "0");
3d137fdd
JT		 3660 ug_info->phy_address = fixed_link[0];
3661 phy = NULL;
3662 } else {
3663 ph = of_get_property(np, "phy-handle", NULL);
3664 phy = of_find_node_by_phandle(*ph);
18a8e864 3665
3d137fdd
JT		 3666 if (phy == NULL)
3667 return -ENODEV;
ce973b14 3668
3d137fdd
JT		 3669 /* set the PHY address */
3670 prop = of_get_property(phy, "reg", NULL);
3671 if (prop == NULL)
3672 return -1;
3673 ug_info->phy_address = *prop;
3674
3675 /* Set the bus id */
3676 mdio = of_get_parent(phy);
3677
3678 if (mdio == NULL)
3679 return -1;
18a8e864 3680
3d137fdd
JT		 3681 err = of_address_to_resource(mdio, 0, &res);
3682 of_node_put(mdio);
3683
3684 if (err)
3685 return -1;
3686
9d9326d3 3687 snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "%x", res.start);
3d137fdd 3688 }
728de4c9
KP		 3689
3690 /* get the phy interface type, or default to MII */
4e19b5c1 3691 prop = of_get_property(np, "phy-connection-type", NULL);
728de4c9
KP		 3692 if (!prop) {
3693 /* handle interface property present in old trees */
40cd3a45 3694 prop = of_get_property(phy, "interface", NULL);
4e19b5c1 3695 if (prop != NULL) {
728de4c9 3696 phy_interface = enet_to_phy_interface[*prop];
4e19b5c1
KP		 3697 max_speed = enet_to_speed[*prop];
3698 } else
728de4c9
KP		 3699 phy_interface = PHY_INTERFACE_MODE_MII;
3700 } else {
3701 phy_interface = to_phy_interface((const char *)prop);
3702 }
3703
4e19b5c1
KP		 3704 /* get speed, or derive from PHY interface */
3705 if (max_speed == 0)
728de4c9
KP		 3706 switch (phy_interface) {
3707 case PHY_INTERFACE_MODE_GMII:
3708 case PHY_INTERFACE_MODE_RGMII:
3709 case PHY_INTERFACE_MODE_RGMII_ID:
bd0ceaab
KP		 3710 case PHY_INTERFACE_MODE_RGMII_RXID:
3711 case PHY_INTERFACE_MODE_RGMII_TXID:
728de4c9
KP		 3712 case PHY_INTERFACE_MODE_TBI:
3713 case PHY_INTERFACE_MODE_RTBI:
3714 max_speed = SPEED_1000;
3715 break;
3716 default:
3717 max_speed = SPEED_100;
3718 break;
3719 }
728de4c9
KP		 3720
3721 if (max_speed == SPEED_1000) {
4e19b5c1 3722 /* configure muram FIFOs for gigabit operation */
728de4c9
KP		 3723 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3724 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3725 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3726 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3727 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3728 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
ffea31ed
JT		 3729 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3730 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
728de4c9
KP		 3731 }
3732
890de95e
LY		 3733 if (netif_msg_probe(&debug))
3734 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3735 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3736 ug_info->uf_info.irq);
ce973b14 3737
ce973b14
LY		 3738 /* Create an ethernet device instance */
3739 dev = alloc_etherdev(sizeof(*ugeth));
3740
3741 if (dev == NULL)
3742 return -ENOMEM;
3743
3744 ugeth = netdev_priv(dev);
3745 spin_lock_init(&ugeth->lock);
3746
80a9fad8
AV		 3747 /* Create CQs for hash tables */
3748 INIT_LIST_HEAD(&ugeth->group_hash_q);
3749 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3750
ce973b14
LY		 3751 dev_set_drvdata(device, dev);
3752
3753 /* Set the dev->base_addr to the gfar reg region */
3754 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3755
ce973b14
LY		 3756 SET_NETDEV_DEV(dev, device);
3757
3758 /* Fill in the dev structure */
ac421852 3759 uec_set_ethtool_ops(dev);
ce973b14
LY		 3760 dev->open = ucc_geth_open;
3761 dev->hard_start_xmit = ucc_geth_start_xmit;
3762 dev->tx_timeout = ucc_geth_timeout;
3763 dev->watchdog_timeo = TX_TIMEOUT;
1762a29a 3764 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
bea3348e 3765 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT);
26d29ea7
AV		 3766#ifdef CONFIG_NET_POLL_CONTROLLER
3767 dev->poll_controller = ucc_netpoll;
3768#endif
ce973b14 3769 dev->stop = ucc_geth_close;
ce973b14
LY		 3770// dev->change_mtu = ucc_geth_change_mtu;
3771 dev->mtu = 1500;
3772 dev->set_multicast_list = ucc_geth_set_multi;
ce973b14 3773
890de95e 3774 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
728de4c9
KP		 3775 ugeth->phy_interface = phy_interface;
3776 ugeth->max_speed = max_speed;
3777
ce973b14
LY		 3778 err = register_netdev(dev);
3779 if (err) {
890de95e
LY		 3780 if (netif_msg_probe(ugeth))
3781 ugeth_err("%s: Cannot register net device, aborting.",
3782 dev->name);
ce973b14
LY		 3783 free_netdev(dev);
3784 return err;
3785 }
3786
e9eb70c9 3787 mac_addr = of_get_mac_address(np);
9b4c7a4e
LY		 3788 if (mac_addr)
3789 memcpy(dev->dev_addr, mac_addr, 6);
ce973b14 3790
728de4c9
KP		 3791 ugeth->ug_info = ug_info;
3792 ugeth->dev = dev;
3793
ce973b14
LY		 3794 return 0;
3795}
3796
18a8e864 3797static int ucc_geth_remove(struct of_device* ofdev)
ce973b14 3798{
18a8e864 3799 struct device *device = &ofdev->dev;
ce973b14
LY		 3800 struct net_device *dev = dev_get_drvdata(device);
3801 struct ucc_geth_private *ugeth = netdev_priv(dev);
3802
80a9fad8 3803 unregister_netdev(dev);
ce973b14 3804 free_netdev(dev);
80a9fad8
AV		 3805 ucc_geth_memclean(ugeth);
3806 dev_set_drvdata(device, NULL);
ce973b14
LY		 3807
3808 return 0;
3809}
3810
18a8e864
LY		 3811static struct of_device_id ucc_geth_match[] = {
3812 {
3813 .type = "network",
3814 .compatible = "ucc_geth",
3815 },
3816 {},
3817};
3818
3819MODULE_DEVICE_TABLE(of, ucc_geth_match);
3820
3821static struct of_platform_driver ucc_geth_driver = {
3822 .name = DRV_NAME,
3823 .match_table = ucc_geth_match,
3824 .probe = ucc_geth_probe,
3825 .remove = ucc_geth_remove,
ce973b14
LY		 3826};
3827
3828static int __init ucc_geth_init(void)
3829{
728de4c9
KP		 3830 int i, ret;
3831
3832 ret = uec_mdio_init();
3833
3834 if (ret)
3835 return ret;
18a8e864 3836
890de95e
LY		 3837 if (netif_msg_drv(&debug))
3838 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
ce973b14
LY		 3839 for (i = 0; i < 8; i++)
3840 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3841 sizeof(ugeth_primary_info));
3842
728de4c9
KP		 3843 ret = of_register_platform_driver(&ucc_geth_driver);
3844
3845 if (ret)
3846 uec_mdio_exit();
3847
3848 return ret;
ce973b14
LY		 3849}
3850
3851static void __exit ucc_geth_exit(void)
3852{
a4f0c2ca 3853 of_unregister_platform_driver(&ucc_geth_driver);
728de4c9 3854 uec_mdio_exit();
ce973b14
LY		 3855}
3856
3857module_init(ucc_geth_init);
3858module_exit(ucc_geth_exit);
3859
3860MODULE_AUTHOR("Freescale Semiconductor, Inc");
3861MODULE_DESCRIPTION(DRV_DESC);
c2bcf00b 3862MODULE_VERSION(DRV_VERSION);
ce973b14 3863MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)