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net: convert print_mac to %pM
[linux-2.6-block.git] / drivers / net / tulip / uli526x.c
CommitLineData
4689ced9
PC		 1/*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
f3b197ac 12
4689ced9
PC		 13*/
14
15#define DRV_NAME "uli526x"
16#define DRV_VERSION "0.9.3"
17#define DRV_RELDATE "2005-7-29"
18
19#include <linux/module.h>
20
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/timer.h>
4689ced9
PC		 24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/slab.h>
27#include <linux/interrupt.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/skbuff.h>
34#include <linux/delay.h>
35#include <linux/spinlock.h>
6cafa99f 36#include <linux/dma-mapping.h>
1977f032 37#include <linux/bitops.h>
4689ced9
PC		 38
39#include <asm/processor.h>
4689ced9
PC		 40#include <asm/io.h>
41#include <asm/dma.h>
42#include <asm/uaccess.h>
43
44
45/* Board/System/Debug information/definition ---------------- */
46#define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
47#define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
48
49#define ULI526X_IO_SIZE 0x100
50#define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
51#define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
52#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
53#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
54#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55#define TX_BUF_ALLOC 0x600
56#define RX_ALLOC_SIZE 0x620
57#define ULI526X_RESET 1
58#define CR0_DEFAULT 0
945a7876 59#define CR6_DEFAULT 0x22200000
4689ced9
PC		 60#define CR7_DEFAULT 0x180c1
61#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
62#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
63#define MAX_PACKET_SIZE 1514
64#define ULI5261_MAX_MULTICAST 14
65#define RX_COPY_SIZE 100
66#define MAX_CHECK_PACKET 0x8000
67
68#define ULI526X_10MHF 0
69#define ULI526X_100MHF 1
70#define ULI526X_10MFD 4
71#define ULI526X_100MFD 5
72#define ULI526X_AUTO 8
73
74#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
75#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
76#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
77#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
78#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
79#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
80
81#define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
82#define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
83#define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
84
85#define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
86
87#define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
88
89
90/* CR9 definition: SROM/MII */
91#define CR9_SROM_READ 0x4800
92#define CR9_SRCS 0x1
93#define CR9_SRCLK 0x2
94#define CR9_CRDOUT 0x8
95#define SROM_DATA_0 0x0
96#define SROM_DATA_1 0x4
97#define PHY_DATA_1 0x20000
98#define PHY_DATA_0 0x00000
99#define MDCLKH 0x10000
100
101#define PHY_POWER_DOWN 0x800
102
103#define SROM_V41_CODE 0x14
104
945a7876
PC		 105#define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
107 udelay(5); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
109 udelay(5); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
111 udelay(5);
4689ced9
PC		 112
113/* Structure/enum declaration ------------------------------- */
114struct tx_desc {
c559a5bc 115 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
4689ced9
PC		 116 char *tx_buf_ptr; /* Data for us */
117 struct tx_desc *next_tx_desc;
118} __attribute__(( aligned(32) ));
119
120struct rx_desc {
c559a5bc 121 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
4689ced9
PC		 122 struct sk_buff *rx_skb_ptr; /* Data for us */
123 struct rx_desc *next_rx_desc;
124} __attribute__(( aligned(32) ));
125
126struct uli526x_board_info {
127 u32 chip_id; /* Chip vendor/Device ID */
945a7876 128 struct net_device *next_dev; /* next device */
4689ced9
PC		 129 struct pci_dev *pdev; /* PCI device */
130 spinlock_t lock;
131
132 long ioaddr; /* I/O base address */
133 u32 cr0_data;
134 u32 cr5_data;
135 u32 cr6_data;
136 u32 cr7_data;
137 u32 cr15_data;
138
139 /* pointer for memory physical address */
140 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
141 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
142 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
143 dma_addr_t first_tx_desc_dma;
144 dma_addr_t first_rx_desc_dma;
145
146 /* descriptor pointer */
147 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
148 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
149 unsigned char *desc_pool_ptr; /* descriptor pool memory */
150 struct tx_desc *first_tx_desc;
151 struct tx_desc *tx_insert_ptr;
152 struct tx_desc *tx_remove_ptr;
153 struct rx_desc *first_rx_desc;
154 struct rx_desc *rx_insert_ptr;
155 struct rx_desc *rx_ready_ptr; /* packet come pointer */
156 unsigned long tx_packet_cnt; /* transmitted packet count */
157 unsigned long rx_avail_cnt; /* available rx descriptor count */
158 unsigned long interval_rx_cnt; /* rx packet count a callback time */
159
160 u16 dbug_cnt;
161 u16 NIC_capability; /* NIC media capability */
162 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
163
164 u8 media_mode; /* user specify media mode */
165 u8 op_mode; /* real work media mode */
166 u8 phy_addr;
167 u8 link_failed; /* Ever link failed */
168 u8 wait_reset; /* Hardware failed, need to reset */
169 struct timer_list timer;
170
171 /* System defined statistic counter */
172 struct net_device_stats stats;
173
174 /* Driver defined statistic counter */
175 unsigned long tx_fifo_underrun;
176 unsigned long tx_loss_carrier;
177 unsigned long tx_no_carrier;
178 unsigned long tx_late_collision;
179 unsigned long tx_excessive_collision;
180 unsigned long tx_jabber_timeout;
181 unsigned long reset_count;
182 unsigned long reset_cr8;
183 unsigned long reset_fatal;
184 unsigned long reset_TXtimeout;
185
186 /* NIC SROM data */
187 unsigned char srom[128];
f3b197ac 188 u8 init;
4689ced9
PC		 189};
190
191enum uli526x_offsets {
192 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
193 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
194 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
195 DCR15 = 0x78
196};
197
198enum uli526x_CR6_bits {
199 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
200 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
201 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
202};
203
204/* Global variable declaration ----------------------------- */
205static int __devinitdata printed_version;
206static char version[] __devinitdata =
207 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
208 DRV_VERSION " (" DRV_RELDATE ")\n";
209
210static int uli526x_debug;
211static unsigned char uli526x_media_mode = ULI526X_AUTO;
212static u32 uli526x_cr6_user_set;
213
214/* For module input parameter */
215static int debug;
216static u32 cr6set;
99bb2579 217static int mode = 8;
4689ced9
PC		 218
219/* function declaration ------------------------------------- */
945a7876
PC		 220static int uli526x_open(struct net_device *);
221static int uli526x_start_xmit(struct sk_buff *, struct net_device *);
222static int uli526x_stop(struct net_device *);
223static struct net_device_stats * uli526x_get_stats(struct net_device *);
224static void uli526x_set_filter_mode(struct net_device *);
7282d491 225static const struct ethtool_ops netdev_ethtool_ops;
945a7876 226static u16 read_srom_word(long, int);
7d12e780 227static irqreturn_t uli526x_interrupt(int, void *);
7fa0cba3
AV		 228#ifdef CONFIG_NET_POLL_CONTROLLER
229static void uli526x_poll(struct net_device *dev);
230#endif
4689ced9
PC		 231static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
232static void allocate_rx_buffer(struct uli526x_board_info *);
233static void update_cr6(u32, unsigned long);
945a7876 234static void send_filter_frame(struct net_device *, int);
4689ced9
PC		 235static u16 phy_read(unsigned long, u8, u8, u32);
236static u16 phy_readby_cr10(unsigned long, u8, u8);
237static void phy_write(unsigned long, u8, u8, u16, u32);
238static void phy_writeby_cr10(unsigned long, u8, u8, u16);
239static void phy_write_1bit(unsigned long, u32, u32);
240static u16 phy_read_1bit(unsigned long, u32);
241static u8 uli526x_sense_speed(struct uli526x_board_info *);
242static void uli526x_process_mode(struct uli526x_board_info *);
243static void uli526x_timer(unsigned long);
945a7876
PC		 244static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
245static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
4689ced9 246static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
945a7876 247static void uli526x_dynamic_reset(struct net_device *);
4689ced9 248static void uli526x_free_rxbuffer(struct uli526x_board_info *);
945a7876 249static void uli526x_init(struct net_device *);
4689ced9
PC		 250static void uli526x_set_phyxcer(struct uli526x_board_info *);
251
945a7876 252/* ULI526X network board routine ---------------------------- */
4689ced9
PC		 253
254/*
945a7876 255 * Search ULI526X board, allocate space and register it
4689ced9
PC		 256 */
257
258static int __devinit uli526x_init_one (struct pci_dev *pdev,
259 const struct pci_device_id *ent)
260{
261 struct uli526x_board_info *db; /* board information structure */
262 struct net_device *dev;
263 int i, err;
f3b197ac 264
4689ced9
PC		 265 ULI526X_DBUG(0, "uli526x_init_one()", 0);
266
267 if (!printed_version++)
268 printk(version);
269
270 /* Init network device */
271 dev = alloc_etherdev(sizeof(*db));
272 if (dev == NULL)
273 return -ENOMEM;
4689ced9
PC		 274 SET_NETDEV_DEV(dev, &pdev->dev);
275
945a7876 276 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
4689ced9
PC		 277 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
278 err = -ENODEV;
279 goto err_out_free;
280 }
281
282 /* Enable Master/IO access, Disable memory access */
283 err = pci_enable_device(pdev);
284 if (err)
285 goto err_out_free;
286
287 if (!pci_resource_start(pdev, 0)) {
288 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
289 err = -ENODEV;
290 goto err_out_disable;
291 }
292
293 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
294 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
295 err = -ENODEV;
296 goto err_out_disable;
297 }
298
299 if (pci_request_regions(pdev, DRV_NAME)) {
300 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
301 err = -ENODEV;
302 goto err_out_disable;
303 }
304
4689ced9
PC		 305 /* Init system & device */
306 db = netdev_priv(dev);
307
308 /* Allocate Tx/Rx descriptor memory */
309 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
945a7876
PC		 310 if(db->desc_pool_ptr == NULL)
311 {
312 err = -ENOMEM;
313 goto err_out_nomem;
314 }
4689ced9 315 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
945a7876
PC		 316 if(db->buf_pool_ptr == NULL)
317 {
318 err = -ENOMEM;
319 goto err_out_nomem;
320 }
f3b197ac 321
4689ced9
PC		 322 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
323 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
324 db->buf_pool_start = db->buf_pool_ptr;
325 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
326
327 db->chip_id = ent->driver_data;
328 db->ioaddr = pci_resource_start(pdev, 0);
f3b197ac 329
4689ced9
PC		 330 db->pdev = pdev;
331 db->init = 1;
f3b197ac 332
4689ced9
PC		 333 dev->base_addr = db->ioaddr;
334 dev->irq = pdev->irq;
335 pci_set_drvdata(pdev, dev);
f3b197ac 336
4689ced9
PC		 337 /* Register some necessary functions */
338 dev->open = &uli526x_open;
339 dev->hard_start_xmit = &uli526x_start_xmit;
340 dev->stop = &uli526x_stop;
341 dev->get_stats = &uli526x_get_stats;
342 dev->set_multicast_list = &uli526x_set_filter_mode;
343 dev->ethtool_ops = &netdev_ethtool_ops;
7fa0cba3
AV		 344#ifdef CONFIG_NET_POLL_CONTROLLER
345 dev->poll_controller = &uli526x_poll;
346#endif
4689ced9
PC		 347 spin_lock_init(&db->lock);
348
f3b197ac 349
4689ced9
PC		 350 /* read 64 word srom data */
351 for (i = 0; i < 64; i++)
c559a5bc 352 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
4689ced9
PC		 353
354 /* Set Node address */
945a7876 355 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
4689ced9
PC		 356 {
357 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
358 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
359 outl(0, db->ioaddr + DCR14); //Clear reset port
360 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
361 outl(0, db->ioaddr + DCR14); //Clear reset port
362 outl(0, db->ioaddr + DCR13); //Clear CR13
363 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
364 //Read MAC address from CR14
365 for (i = 0; i < 6; i++)
366 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
367 //Read end
368 outl(0, db->ioaddr + DCR13); //Clear CR13
369 outl(0, db->ioaddr + DCR0); //Clear CR0
370 udelay(10);
371 }
372 else /*Exist SROM*/
373 {
374 for (i = 0; i < 6; i++)
375 dev->dev_addr[i] = db->srom[20 + i];
376 }
377 err = register_netdev (dev);
378 if (err)
379 goto err_out_res;
380
e174961c 381 printk(KERN_INFO "%s: ULi M%04lx at pci%s, %pM, irq %d.\n",
0795af57 382 dev->name,ent->driver_data >> 16,pci_name(pdev),
e174961c 383 dev->dev_addr, dev->irq);
4689ced9
PC		 384
385 pci_set_master(pdev);
386
387 return 0;
388
389err_out_res:
390 pci_release_regions(pdev);
945a7876
PC		 391err_out_nomem:
392 if(db->desc_pool_ptr)
393 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
394 db->desc_pool_ptr, db->desc_pool_dma_ptr);
f3b197ac 395
945a7876
PC		 396 if(db->buf_pool_ptr != NULL)
397 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
398 db->buf_pool_ptr, db->buf_pool_dma_ptr);
4689ced9
PC		 399err_out_disable:
400 pci_disable_device(pdev);
401err_out_free:
402 pci_set_drvdata(pdev, NULL);
403 free_netdev(dev);
404
405 return err;
406}
407
408
409static void __devexit uli526x_remove_one (struct pci_dev *pdev)
410{
411 struct net_device *dev = pci_get_drvdata(pdev);
412 struct uli526x_board_info *db = netdev_priv(dev);
413
414 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
415
945a7876
PC		 416 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
417 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
418 db->desc_pool_dma_ptr);
419 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
420 db->buf_pool_ptr, db->buf_pool_dma_ptr);
421 unregister_netdev(dev);
422 pci_release_regions(pdev);
423 free_netdev(dev); /* free board information */
424 pci_set_drvdata(pdev, NULL);
425 pci_disable_device(pdev);
4689ced9
PC		 426 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
427}
428
429
430/*
431 * Open the interface.
945a7876 432 * The interface is opened whenever "ifconfig" activates it.
4689ced9
PC		 433 */
434
945a7876 435static int uli526x_open(struct net_device *dev)
4689ced9
PC		 436{
437 int ret;
438 struct uli526x_board_info *db = netdev_priv(dev);
f3b197ac 439
4689ced9
PC		 440 ULI526X_DBUG(0, "uli526x_open", 0);
441
4689ced9
PC		 442 /* system variable init */
443 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
4689ced9
PC		 444 db->tx_packet_cnt = 0;
445 db->rx_avail_cnt = 0;
446 db->link_failed = 1;
447 netif_carrier_off(dev);
448 db->wait_reset = 0;
449
450 db->NIC_capability = 0xf; /* All capability*/
451 db->PHY_reg4 = 0x1e0;
452
453 /* CR6 operation mode decision */
454 db->cr6_data |= ULI526X_TXTH_256;
455 db->cr0_data = CR0_DEFAULT;
f3b197ac 456
945a7876 457 /* Initialize ULI526X board */
4689ced9
PC		 458 uli526x_init(dev);
459
afd8e399
AV		 460 ret = request_irq(dev->irq, &uli526x_interrupt, IRQF_SHARED, dev->name, dev);
461 if (ret)
462 return ret;
463
4689ced9
PC		 464 /* Active System Interface */
465 netif_wake_queue(dev);
466
467 /* set and active a timer process */
468 init_timer(&db->timer);
469 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
470 db->timer.data = (unsigned long)dev;
471 db->timer.function = &uli526x_timer;
472 add_timer(&db->timer);
473
474 return 0;
475}
476
477
945a7876 478/* Initialize ULI526X board
4689ced9 479 * Reset ULI526X board
945a7876 480 * Initialize TX/Rx descriptor chain structure
4689ced9
PC		 481 * Send the set-up frame
482 * Enable Tx/Rx machine
483 */
484
945a7876 485static void uli526x_init(struct net_device *dev)
4689ced9
PC		 486{
487 struct uli526x_board_info *db = netdev_priv(dev);
488 unsigned long ioaddr = db->ioaddr;
489 u8 phy_tmp;
7a7d23da 490 u8 timeout;
4689ced9
PC		 491 u16 phy_value;
492 u16 phy_reg_reset;
493
7a7d23da 494
4689ced9
PC		 495 ULI526X_DBUG(0, "uli526x_init()", 0);
496
497 /* Reset M526x MAC controller */
498 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
499 udelay(100);
500 outl(db->cr0_data, ioaddr + DCR0);
501 udelay(5);
502
503 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
504 db->phy_addr = 1;
505 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
506 {
507 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
508 if(phy_value != 0xffff&&phy_value!=0)
509 {
510 db->phy_addr = phy_tmp;
511 break;
512 }
513 }
514 if(phy_tmp == 32)
515 printk(KERN_WARNING "Can not find the phy address!!!");
516 /* Parser SROM and media mode */
517 db->media_mode = uli526x_media_mode;
518
7a7d23da 519 /* phyxcer capability setting */
4689ced9
PC		 520 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
521 phy_reg_reset = (phy_reg_reset | 0x8000);
522 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
7a7d23da
GG		 523
524 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
525 * functions") or phy data sheet for details on phy reset
526 */
4689ced9 527 udelay(500);
7a7d23da
GG		 528 timeout = 10;
529 while (timeout-- &&
530 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
531 udelay(100);
4689ced9
PC		 532
533 /* Process Phyxcer Media Mode */
534 uli526x_set_phyxcer(db);
535
536 /* Media Mode Process */
537 if ( !(db->media_mode & ULI526X_AUTO) )
538 db->op_mode = db->media_mode; /* Force Mode */
539
945a7876 540 /* Initialize Transmit/Receive decriptor and CR3/4 */
4689ced9
PC		 541 uli526x_descriptor_init(db, ioaddr);
542
543 /* Init CR6 to program M526X operation */
544 update_cr6(db->cr6_data, ioaddr);
545
546 /* Send setup frame */
547 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
548
549 /* Init CR7, interrupt active bit */
550 db->cr7_data = CR7_DEFAULT;
551 outl(db->cr7_data, ioaddr + DCR7);
552
553 /* Init CR15, Tx jabber and Rx watchdog timer */
554 outl(db->cr15_data, ioaddr + DCR15);
555
556 /* Enable ULI526X Tx/Rx function */
557 db->cr6_data |= CR6_RXSC | CR6_TXSC;
558 update_cr6(db->cr6_data, ioaddr);
559}
560
561
562/*
563 * Hardware start transmission.
564 * Send a packet to media from the upper layer.
565 */
566
945a7876 567static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev)
4689ced9
PC		 568{
569 struct uli526x_board_info *db = netdev_priv(dev);
570 struct tx_desc *txptr;
571 unsigned long flags;
572
573 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
574
575 /* Resource flag check */
576 netif_stop_queue(dev);
577
578 /* Too large packet check */
579 if (skb->len > MAX_PACKET_SIZE) {
580 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
581 dev_kfree_skb(skb);
582 return 0;
583 }
584
585 spin_lock_irqsave(&db->lock, flags);
586
587 /* No Tx resource check, it never happen nromally */
588 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
589 spin_unlock_irqrestore(&db->lock, flags);
590 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt);
591 return 1;
592 }
593
594 /* Disable NIC interrupt */
595 outl(0, dev->base_addr + DCR7);
596
597 /* transmit this packet */
598 txptr = db->tx_insert_ptr;
d626f62b 599 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
4689ced9
PC		 600 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
601
602 /* Point to next transmit free descriptor */
603 db->tx_insert_ptr = txptr->next_tx_desc;
604
605 /* Transmit Packet Process */
606 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
607 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
608 db->tx_packet_cnt++; /* Ready to send */
609 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
610 dev->trans_start = jiffies; /* saved time stamp */
611 }
612
613 /* Tx resource check */
614 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
615 netif_wake_queue(dev);
616
617 /* Restore CR7 to enable interrupt */
618 spin_unlock_irqrestore(&db->lock, flags);
619 outl(db->cr7_data, dev->base_addr + DCR7);
f3b197ac 620
4689ced9
PC		 621 /* free this SKB */
622 dev_kfree_skb(skb);
623
624 return 0;
625}
626
627
628/*
629 * Stop the interface.
630 * The interface is stopped when it is brought.
631 */
632
945a7876 633static int uli526x_stop(struct net_device *dev)
4689ced9
PC		 634{
635 struct uli526x_board_info *db = netdev_priv(dev);
636 unsigned long ioaddr = dev->base_addr;
637
638 ULI526X_DBUG(0, "uli526x_stop", 0);
639
640 /* disable system */
641 netif_stop_queue(dev);
642
643 /* deleted timer */
644 del_timer_sync(&db->timer);
645
646 /* Reset & stop ULI526X board */
647 outl(ULI526X_RESET, ioaddr + DCR0);
648 udelay(5);
649 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
650
651 /* free interrupt */
652 free_irq(dev->irq, dev);
653
654 /* free allocated rx buffer */
655 uli526x_free_rxbuffer(db);
656
657#if 0
658 /* show statistic counter */
659 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
660 db->tx_fifo_underrun, db->tx_excessive_collision,
661 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
662 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
663 db->reset_fatal, db->reset_TXtimeout);
664#endif
665
666 return 0;
667}
668
669
670/*
671 * M5261/M5263 insterrupt handler
672 * receive the packet to upper layer, free the transmitted packet
673 */
674
7d12e780 675static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
4689ced9 676{
945a7876 677 struct net_device *dev = dev_id;
4689ced9
PC		 678 struct uli526x_board_info *db = netdev_priv(dev);
679 unsigned long ioaddr = dev->base_addr;
680 unsigned long flags;
681
4689ced9
PC		 682 spin_lock_irqsave(&db->lock, flags);
683 outl(0, ioaddr + DCR7);
684
685 /* Got ULI526X status */
686 db->cr5_data = inl(ioaddr + DCR5);
687 outl(db->cr5_data, ioaddr + DCR5);
688 if ( !(db->cr5_data & 0x180c1) ) {
7fa0cba3 689 /* Restore CR7 to enable interrupt mask */
4689ced9 690 outl(db->cr7_data, ioaddr + DCR7);
7fa0cba3 691 spin_unlock_irqrestore(&db->lock, flags);
4689ced9
PC		 692 return IRQ_HANDLED;
693 }
694
4689ced9
PC		 695 /* Check system status */
696 if (db->cr5_data & 0x2000) {
697 /* system bus error happen */
698 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
699 db->reset_fatal++;
700 db->wait_reset = 1; /* Need to RESET */
701 spin_unlock_irqrestore(&db->lock, flags);
702 return IRQ_HANDLED;
703 }
704
705 /* Received the coming packet */
706 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
707 uli526x_rx_packet(dev, db);
708
709 /* reallocate rx descriptor buffer */
710 if (db->rx_avail_cnt<RX_DESC_CNT)
711 allocate_rx_buffer(db);
712
713 /* Free the transmitted descriptor */
714 if ( db->cr5_data & 0x01)
715 uli526x_free_tx_pkt(dev, db);
716
717 /* Restore CR7 to enable interrupt mask */
718 outl(db->cr7_data, ioaddr + DCR7);
719
720 spin_unlock_irqrestore(&db->lock, flags);
721 return IRQ_HANDLED;
722}
723
7fa0cba3
AV		 724#ifdef CONFIG_NET_POLL_CONTROLLER
725static void uli526x_poll(struct net_device *dev)
726{
727 /* ISR grabs the irqsave lock, so this should be safe */
728 uli526x_interrupt(dev->irq, dev);
729}
730#endif
4689ced9
PC		 731
732/*
733 * Free TX resource after TX complete
734 */
735
945a7876 736static void uli526x_free_tx_pkt(struct net_device *dev, struct uli526x_board_info * db)
4689ced9
PC		 737{
738 struct tx_desc *txptr;
4689ced9
PC		 739 u32 tdes0;
740
741 txptr = db->tx_remove_ptr;
742 while(db->tx_packet_cnt) {
743 tdes0 = le32_to_cpu(txptr->tdes0);
744 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
745 if (tdes0 & 0x80000000)
746 break;
747
748 /* A packet sent completed */
749 db->tx_packet_cnt--;
750 db->stats.tx_packets++;
751
752 /* Transmit statistic counter */
753 if ( tdes0 != 0x7fffffff ) {
754 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
755 db->stats.collisions += (tdes0 >> 3) & 0xf;
756 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
757 if (tdes0 & TDES0_ERR_MASK) {
758 db->stats.tx_errors++;
759 if (tdes0 & 0x0002) { /* UnderRun */
760 db->tx_fifo_underrun++;
761 if ( !(db->cr6_data & CR6_SFT) ) {
762 db->cr6_data = db->cr6_data | CR6_SFT;
763 update_cr6(db->cr6_data, db->ioaddr);
764 }
765 }
766 if (tdes0 & 0x0100)
767 db->tx_excessive_collision++;
768 if (tdes0 & 0x0200)
769 db->tx_late_collision++;
770 if (tdes0 & 0x0400)
771 db->tx_no_carrier++;
772 if (tdes0 & 0x0800)
773 db->tx_loss_carrier++;
774 if (tdes0 & 0x4000)
775 db->tx_jabber_timeout++;
776 }
777 }
778
779 txptr = txptr->next_tx_desc;
780 }/* End of while */
781
782 /* Update TX remove pointer to next */
783 db->tx_remove_ptr = txptr;
784
785 /* Resource available check */
786 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
787 netif_wake_queue(dev); /* Active upper layer, send again */
788}
789
790
791/*
792 * Receive the come packet and pass to upper layer
793 */
794
945a7876 795static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
4689ced9
PC		 796{
797 struct rx_desc *rxptr;
798 struct sk_buff *skb;
799 int rxlen;
800 u32 rdes0;
f3b197ac 801
4689ced9
PC		 802 rxptr = db->rx_ready_ptr;
803
804 while(db->rx_avail_cnt) {
805 rdes0 = le32_to_cpu(rxptr->rdes0);
806 if (rdes0 & 0x80000000) /* packet owner check */
807 {
808 break;
809 }
810
811 db->rx_avail_cnt--;
812 db->interval_rx_cnt++;
813
814 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
815 if ( (rdes0 & 0x300) != 0x300) {
816 /* A packet without First/Last flag */
817 /* reuse this SKB */
818 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
819 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
820 } else {
821 /* A packet with First/Last flag */
822 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
823
824 /* error summary bit check */
825 if (rdes0 & 0x8000) {
826 /* This is a error packet */
827 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
828 db->stats.rx_errors++;
829 if (rdes0 & 1)
830 db->stats.rx_fifo_errors++;
831 if (rdes0 & 2)
832 db->stats.rx_crc_errors++;
833 if (rdes0 & 0x80)
834 db->stats.rx_length_errors++;
835 }
836
837 if ( !(rdes0 & 0x8000) ||
838 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
839 skb = rxptr->rx_skb_ptr;
f3b197ac 840
4689ced9
PC		 841 /* Good packet, send to upper layer */
842 /* Shorst packet used new SKB */
843 if ( (rxlen < RX_COPY_SIZE) &&
844 ( (skb = dev_alloc_skb(rxlen + 2) )
845 != NULL) ) {
846 /* size less than COPY_SIZE, allocate a rxlen SKB */
4689ced9 847 skb_reserve(skb, 2); /* 16byte align */
27a884dc
ACM		 848 memcpy(skb_put(skb, rxlen),
849 skb_tail_pointer(rxptr->rx_skb_ptr),
850 rxlen);
4689ced9 851 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 852 } else
4689ced9 853 skb_put(skb, rxlen);
4c13eb66 854
4689ced9
PC		 855 skb->protocol = eth_type_trans(skb, dev);
856 netif_rx(skb);
857 dev->last_rx = jiffies;
858 db->stats.rx_packets++;
859 db->stats.rx_bytes += rxlen;
f3b197ac 860
4689ced9
PC		 861 } else {
862 /* Reuse SKB buffer when the packet is error */
863 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
864 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
865 }
866 }
867
868 rxptr = rxptr->next_rx_desc;
869 }
870
871 db->rx_ready_ptr = rxptr;
872}
873
874
875/*
876 * Get statistics from driver.
877 */
878
945a7876 879static struct net_device_stats * uli526x_get_stats(struct net_device *dev)
4689ced9
PC		 880{
881 struct uli526x_board_info *db = netdev_priv(dev);
882
883 ULI526X_DBUG(0, "uli526x_get_stats", 0);
884 return &db->stats;
885}
886
887
888/*
889 * Set ULI526X multicast address
890 */
891
945a7876 892static void uli526x_set_filter_mode(struct net_device * dev)
4689ced9
PC		 893{
894 struct uli526x_board_info *db = dev->priv;
895 unsigned long flags;
896
897 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
898 spin_lock_irqsave(&db->lock, flags);
899
900 if (dev->flags & IFF_PROMISC) {
901 ULI526X_DBUG(0, "Enable PROM Mode", 0);
902 db->cr6_data |= CR6_PM | CR6_PBF;
903 update_cr6(db->cr6_data, db->ioaddr);
904 spin_unlock_irqrestore(&db->lock, flags);
905 return;
906 }
907
908 if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) {
909 ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count);
910 db->cr6_data &= ~(CR6_PM | CR6_PBF);
911 db->cr6_data |= CR6_PAM;
912 spin_unlock_irqrestore(&db->lock, flags);
913 return;
914 }
915
916 ULI526X_DBUG(0, "Set multicast address", dev->mc_count);
917 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
918 spin_unlock_irqrestore(&db->lock, flags);
919}
920
921static void
922ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
923{
945a7876
PC		 924 ecmd->supported = (SUPPORTED_10baseT_Half |
925 SUPPORTED_10baseT_Full |
926 SUPPORTED_100baseT_Half |
927 SUPPORTED_100baseT_Full |
928 SUPPORTED_Autoneg |
929 SUPPORTED_MII);
f3b197ac 930
945a7876
PC		 931 ecmd->advertising = (ADVERTISED_10baseT_Half |
932 ADVERTISED_10baseT_Full |
933 ADVERTISED_100baseT_Half |
934 ADVERTISED_100baseT_Full |
935 ADVERTISED_Autoneg |
936 ADVERTISED_MII);
4689ced9
PC		 937
938
945a7876
PC		 939 ecmd->port = PORT_MII;
940 ecmd->phy_address = db->phy_addr;
4689ced9 941
945a7876 942 ecmd->transceiver = XCVR_EXTERNAL;
f3b197ac 943
4689ced9
PC		 944 ecmd->speed = 10;
945 ecmd->duplex = DUPLEX_HALF;
f3b197ac 946
4689ced9
PC		 947 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
948 {
f3b197ac 949 ecmd->speed = 100;
4689ced9
PC		 950 }
951 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
952 {
953 ecmd->duplex = DUPLEX_FULL;
954 }
955 if(db->link_failed)
956 {
957 ecmd->speed = -1;
f3b197ac 958 ecmd->duplex = -1;
4689ced9 959 }
f3b197ac 960
4689ced9 961 if (db->media_mode & ULI526X_AUTO)
f3b197ac 962 {
4689ced9
PC		 963 ecmd->autoneg = AUTONEG_ENABLE;
964 }
4689ced9
PC		 965}
966
967static void netdev_get_drvinfo(struct net_device *dev,
968 struct ethtool_drvinfo *info)
969{
970 struct uli526x_board_info *np = netdev_priv(dev);
971
972 strcpy(info->driver, DRV_NAME);
973 strcpy(info->version, DRV_VERSION);
974 if (np->pdev)
975 strcpy(info->bus_info, pci_name(np->pdev));
976 else
977 sprintf(info->bus_info, "EISA 0x%lx %d",
978 dev->base_addr, dev->irq);
979}
980
981static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
982 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 983
4689ced9 984 ULi_ethtool_gset(np, cmd);
f3b197ac 985
4689ced9
PC		 986 return 0;
987}
988
989static u32 netdev_get_link(struct net_device *dev) {
990 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 991
4689ced9
PC		 992 if(np->link_failed)
993 return 0;
994 else
995 return 1;
996}
997
998static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
999{
1000 wol->supported = WAKE_PHY | WAKE_MAGIC;
1001 wol->wolopts = 0;
1002}
1003
7282d491 1004static const struct ethtool_ops netdev_ethtool_ops = {
4689ced9
PC		 1005 .get_drvinfo = netdev_get_drvinfo,
1006 .get_settings = netdev_get_settings,
1007 .get_link = netdev_get_link,
1008 .get_wol = uli526x_get_wol,
1009};
1010
1011/*
1012 * A periodic timer routine
1013 * Dynamic media sense, allocate Rx buffer...
1014 */
1015
1016static void uli526x_timer(unsigned long data)
1017{
1018 u32 tmp_cr8;
1019 unsigned char tmp_cr12=0;
945a7876 1020 struct net_device *dev = (struct net_device *) data;
4689ced9
PC		 1021 struct uli526x_board_info *db = netdev_priv(dev);
1022 unsigned long flags;
1023 u8 TmpSpeed=10;
f3b197ac 1024
4689ced9
PC		 1025 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1026 spin_lock_irqsave(&db->lock, flags);
1027
f3b197ac 1028
4689ced9
PC		 1029 /* Dynamic reset ULI526X : system error or transmit time-out */
1030 tmp_cr8 = inl(db->ioaddr + DCR8);
1031 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1032 db->reset_cr8++;
1033 db->wait_reset = 1;
1034 }
1035 db->interval_rx_cnt = 0;
1036
1037 /* TX polling kick monitor */
1038 if ( db->tx_packet_cnt &&
1039 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
f3b197ac 1040 outl(0x1, dev->base_addr + DCR1); // Tx polling again
4689ced9 1041
f3b197ac 1042 // TX Timeout
4689ced9
PC		 1043 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1044 db->reset_TXtimeout++;
1045 db->wait_reset = 1;
1046 printk( "%s: Tx timeout - resetting\n",
1047 dev->name);
1048 }
1049 }
1050
1051 if (db->wait_reset) {
1052 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1053 db->reset_count++;
1054 uli526x_dynamic_reset(dev);
1055 db->timer.expires = ULI526X_TIMER_WUT;
1056 add_timer(&db->timer);
1057 spin_unlock_irqrestore(&db->lock, flags);
1058 return;
1059 }
1060
1061 /* Link status check, Dynamic media type change */
1062 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1063 tmp_cr12 = 3;
1064
1065 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1066 /* Link Failed */
1067 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1068 netif_carrier_off(dev);
1069 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1070 db->link_failed = 1;
1071
1072 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1073 /* AUTO don't need */
1074 if ( !(db->media_mode & 0x8) )
1075 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1076
1077 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1078 if (db->media_mode & ULI526X_AUTO) {
1079 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1080 update_cr6(db->cr6_data, db->ioaddr);
1081 }
1082 } else
1083 if ((tmp_cr12 & 0x3) && db->link_failed) {
1084 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1085 db->link_failed = 0;
1086
1087 /* Auto Sense Speed */
1088 if ( (db->media_mode & ULI526X_AUTO) &&
1089 uli526x_sense_speed(db) )
1090 db->link_failed = 1;
1091 uli526x_process_mode(db);
f3b197ac 1092
4689ced9
PC		 1093 if(db->link_failed==0)
1094 {
1095 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1096 {
1097 TmpSpeed = 100;
1098 }
1099 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1100 {
1101 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1102 }
1103 else
1104 {
1105 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1106 }
1107 netif_carrier_on(dev);
1108 }
1109 /* SHOW_MEDIA_TYPE(db->op_mode); */
1110 }
1111 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1112 {
1113 if(db->init==1)
1114 {
1115 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1116 netif_carrier_off(dev);
1117 }
1118 }
1119 db->init=0;
1120
1121 /* Timer active again */
1122 db->timer.expires = ULI526X_TIMER_WUT;
1123 add_timer(&db->timer);
1124 spin_unlock_irqrestore(&db->lock, flags);
1125}
1126
1127
1128/*
4689ced9
PC		 1129 * Stop ULI526X board
1130 * Free Tx/Rx allocated memory
b6aec32a 1131 * Init system variable
4689ced9
PC		 1132 */
1133
b6aec32a 1134static void uli526x_reset_prepare(struct net_device *dev)
4689ced9
PC		 1135{
1136 struct uli526x_board_info *db = netdev_priv(dev);
1137
4689ced9
PC		 1138 /* Sopt MAC controller */
1139 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1140 update_cr6(db->cr6_data, dev->base_addr);
1141 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1142 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1143
1144 /* Disable upper layer interface */
1145 netif_stop_queue(dev);
1146
1147 /* Free Rx Allocate buffer */
1148 uli526x_free_rxbuffer(db);
1149
1150 /* system variable init */
1151 db->tx_packet_cnt = 0;
1152 db->rx_avail_cnt = 0;
1153 db->link_failed = 1;
1154 db->init=1;
1155 db->wait_reset = 0;
b6aec32a
RW		 1156}
1157
1158
1159/*
1160 * Dynamic reset the ULI526X board
1161 * Stop ULI526X board
1162 * Free Tx/Rx allocated memory
1163 * Reset ULI526X board
1164 * Re-initialize ULI526X board
1165 */
1166
1167static void uli526x_dynamic_reset(struct net_device *dev)
1168{
1169 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1170
1171 uli526x_reset_prepare(dev);
4689ced9 1172
945a7876 1173 /* Re-initialize ULI526X board */
4689ced9
PC		 1174 uli526x_init(dev);
1175
1176 /* Restart upper layer interface */
1177 netif_wake_queue(dev);
1178}
1179
1180
b6aec32a
RW		 1181#ifdef CONFIG_PM
1182
1183/*
1184 * Suspend the interface.
1185 */
1186
1187static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1188{
1189 struct net_device *dev = pci_get_drvdata(pdev);
1190 pci_power_t power_state;
1191 int err;
1192
1193 ULI526X_DBUG(0, "uli526x_suspend", 0);
1194
1195 if (!netdev_priv(dev))
1196 return 0;
1197
1198 pci_save_state(pdev);
1199
1200 if (!netif_running(dev))
1201 return 0;
1202
1203 netif_device_detach(dev);
1204 uli526x_reset_prepare(dev);
1205
1206 power_state = pci_choose_state(pdev, state);
1207 pci_enable_wake(pdev, power_state, 0);
1208 err = pci_set_power_state(pdev, power_state);
1209 if (err) {
1210 netif_device_attach(dev);
1211 /* Re-initialize ULI526X board */
1212 uli526x_init(dev);
1213 /* Restart upper layer interface */
1214 netif_wake_queue(dev);
1215 }
1216
1217 return err;
1218}
1219
1220/*
1221 * Resume the interface.
1222 */
1223
1224static int uli526x_resume(struct pci_dev *pdev)
1225{
1226 struct net_device *dev = pci_get_drvdata(pdev);
1227 int err;
1228
1229 ULI526X_DBUG(0, "uli526x_resume", 0);
1230
1231 if (!netdev_priv(dev))
1232 return 0;
1233
1234 pci_restore_state(pdev);
1235
1236 if (!netif_running(dev))
1237 return 0;
1238
1239 err = pci_set_power_state(pdev, PCI_D0);
1240 if (err) {
1241 printk(KERN_WARNING "%s: Could not put device into D0\n",
1242 dev->name);
1243 return err;
1244 }
1245
1246 netif_device_attach(dev);
1247 /* Re-initialize ULI526X board */
1248 uli526x_init(dev);
1249 /* Restart upper layer interface */
1250 netif_wake_queue(dev);
1251
1252 return 0;
1253}
1254
1255#else /* !CONFIG_PM */
1256
1257#define uli526x_suspend NULL
1258#define uli526x_resume NULL
1259
1260#endif /* !CONFIG_PM */
1261
1262
4689ced9
PC		 1263/*
1264 * free all allocated rx buffer
1265 */
1266
1267static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1268{
1269 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1270
1271 /* free allocated rx buffer */
1272 while (db->rx_avail_cnt) {
1273 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1274 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1275 db->rx_avail_cnt--;
1276 }
1277}
1278
1279
1280/*
1281 * Reuse the SK buffer
1282 */
1283
1284static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1285{
1286 struct rx_desc *rxptr = db->rx_insert_ptr;
1287
1288 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1289 rxptr->rx_skb_ptr = skb;
27a884dc
ACM		 1290 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1291 skb_tail_pointer(skb),
1292 RX_ALLOC_SIZE,
1293 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1294 wmb();
1295 rxptr->rdes0 = cpu_to_le32(0x80000000);
1296 db->rx_avail_cnt++;
1297 db->rx_insert_ptr = rxptr->next_rx_desc;
1298 } else
1299 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1300}
1301
1302
1303/*
1304 * Initialize transmit/Receive descriptor
1305 * Using Chain structure, and allocate Tx/Rx buffer
1306 */
1307
1308static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1309{
1310 struct tx_desc *tmp_tx;
1311 struct rx_desc *tmp_rx;
1312 unsigned char *tmp_buf;
1313 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1314 dma_addr_t tmp_buf_dma;
1315 int i;
1316
1317 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1318
1319 /* tx descriptor start pointer */
1320 db->tx_insert_ptr = db->first_tx_desc;
1321 db->tx_remove_ptr = db->first_tx_desc;
1322 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1323
1324 /* rx descriptor start pointer */
1325 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1326 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1327 db->rx_insert_ptr = db->first_rx_desc;
1328 db->rx_ready_ptr = db->first_rx_desc;
1329 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1330
1331 /* Init Transmit chain */
1332 tmp_buf = db->buf_pool_start;
1333 tmp_buf_dma = db->buf_pool_dma_start;
1334 tmp_tx_dma = db->first_tx_desc_dma;
1335 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1336 tmp_tx->tx_buf_ptr = tmp_buf;
1337 tmp_tx->tdes0 = cpu_to_le32(0);
1338 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1339 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1340 tmp_tx_dma += sizeof(struct tx_desc);
1341 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1342 tmp_tx->next_tx_desc = tmp_tx + 1;
1343 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1344 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1345 }
1346 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1347 tmp_tx->next_tx_desc = db->first_tx_desc;
1348
1349 /* Init Receive descriptor chain */
1350 tmp_rx_dma=db->first_rx_desc_dma;
1351 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1352 tmp_rx->rdes0 = cpu_to_le32(0);
1353 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1354 tmp_rx_dma += sizeof(struct rx_desc);
1355 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1356 tmp_rx->next_rx_desc = tmp_rx + 1;
1357 }
1358 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1359 tmp_rx->next_rx_desc = db->first_rx_desc;
1360
1361 /* pre-allocate Rx buffer */
1362 allocate_rx_buffer(db);
1363}
1364
1365
1366/*
1367 * Update CR6 value
945a7876 1368 * Firstly stop ULI526X, then written value and start
4689ced9
PC		 1369 */
1370
1371static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1372{
1373
1374 outl(cr6_data, ioaddr + DCR6);
1375 udelay(5);
1376}
1377
1378
1379/*
1380 * Send a setup frame for M5261/M5263
945a7876 1381 * This setup frame initialize ULI526X address filter mode
4689ced9
PC		 1382 */
1383
e284e5c6
AV		 1384#ifdef __BIG_ENDIAN
1385#define FLT_SHIFT 16
1386#else
1387#define FLT_SHIFT 0
1388#endif
1389
945a7876 1390static void send_filter_frame(struct net_device *dev, int mc_cnt)
4689ced9
PC		 1391{
1392 struct uli526x_board_info *db = netdev_priv(dev);
1393 struct dev_mc_list *mcptr;
1394 struct tx_desc *txptr;
1395 u16 * addrptr;
1396 u32 * suptr;
1397 int i;
1398
1399 ULI526X_DBUG(0, "send_filter_frame()", 0);
1400
1401 txptr = db->tx_insert_ptr;
1402 suptr = (u32 *) txptr->tx_buf_ptr;
1403
1404 /* Node address */
1405 addrptr = (u16 *) dev->dev_addr;
e284e5c6
AV		 1406 *suptr++ = addrptr[0] << FLT_SHIFT;
1407 *suptr++ = addrptr[1] << FLT_SHIFT;
1408 *suptr++ = addrptr[2] << FLT_SHIFT;
4689ced9
PC		 1409
1410 /* broadcast address */
e284e5c6
AV		 1411 *suptr++ = 0xffff << FLT_SHIFT;
1412 *suptr++ = 0xffff << FLT_SHIFT;
1413 *suptr++ = 0xffff << FLT_SHIFT;
4689ced9
PC		 1414
1415 /* fit the multicast address */
1416 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1417 addrptr = (u16 *) mcptr->dmi_addr;
e284e5c6
AV		 1418 *suptr++ = addrptr[0] << FLT_SHIFT;
1419 *suptr++ = addrptr[1] << FLT_SHIFT;
1420 *suptr++ = addrptr[2] << FLT_SHIFT;
4689ced9
PC		 1421 }
1422
1423 for (; i<14; i++) {
e284e5c6
AV		 1424 *suptr++ = 0xffff << FLT_SHIFT;
1425 *suptr++ = 0xffff << FLT_SHIFT;
1426 *suptr++ = 0xffff << FLT_SHIFT;
4689ced9
PC		 1427 }
1428
1429 /* prepare the setup frame */
1430 db->tx_insert_ptr = txptr->next_tx_desc;
1431 txptr->tdes1 = cpu_to_le32(0x890000c0);
1432
1433 /* Resource Check and Send the setup packet */
1434 if (db->tx_packet_cnt < TX_DESC_CNT) {
1435 /* Resource Empty */
1436 db->tx_packet_cnt++;
1437 txptr->tdes0 = cpu_to_le32(0x80000000);
1438 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1439 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1440 update_cr6(db->cr6_data, dev->base_addr);
1441 dev->trans_start = jiffies;
1442 } else
1443 printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n");
1444}
1445
1446
1447/*
1448 * Allocate rx buffer,
1449 * As possible as allocate maxiumn Rx buffer
1450 */
1451
1452static void allocate_rx_buffer(struct uli526x_board_info *db)
1453{
1454 struct rx_desc *rxptr;
1455 struct sk_buff *skb;
1456
1457 rxptr = db->rx_insert_ptr;
1458
1459 while(db->rx_avail_cnt < RX_DESC_CNT) {
1460 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1461 break;
1462 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
27a884dc
ACM		 1463 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1464 skb_tail_pointer(skb),
1465 RX_ALLOC_SIZE,
1466 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1467 wmb();
1468 rxptr->rdes0 = cpu_to_le32(0x80000000);
1469 rxptr = rxptr->next_rx_desc;
1470 db->rx_avail_cnt++;
1471 }
1472
1473 db->rx_insert_ptr = rxptr;
1474}
1475
1476
1477/*
1478 * Read one word data from the serial ROM
1479 */
1480
1481static u16 read_srom_word(long ioaddr, int offset)
1482{
1483 int i;
1484 u16 srom_data = 0;
1485 long cr9_ioaddr = ioaddr + DCR9;
1486
1487 outl(CR9_SROM_READ, cr9_ioaddr);
1488 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1489
1490 /* Send the Read Command 110b */
1491 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1492 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1493 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1494
1495 /* Send the offset */
1496 for (i = 5; i >= 0; i--) {
1497 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1498 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1499 }
1500
1501 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1502
1503 for (i = 16; i > 0; i--) {
1504 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1505 udelay(5);
1506 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1507 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1508 udelay(5);
1509 }
1510
1511 outl(CR9_SROM_READ, cr9_ioaddr);
1512 return srom_data;
1513}
1514
1515
1516/*
1517 * Auto sense the media mode
1518 */
1519
1520static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1521{
1522 u8 ErrFlag = 0;
1523 u16 phy_mode;
1524
1525 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1526 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1527
1528 if ( (phy_mode & 0x24) == 0x24 ) {
f3b197ac 1529
4689ced9
PC		 1530 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1531 if(phy_mode&0x8000)
1532 phy_mode = 0x8000;
1533 else if(phy_mode&0x4000)
1534 phy_mode = 0x4000;
1535 else if(phy_mode&0x2000)
1536 phy_mode = 0x2000;
1537 else
1538 phy_mode = 0x1000;
f3b197ac 1539
4689ced9
PC		 1540 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1541 switch (phy_mode) {
1542 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1543 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1544 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1545 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1546 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1547 }
1548 } else {
1549 db->op_mode = ULI526X_10MHF;
1550 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1551 ErrFlag = 1;
1552 }
1553
1554 return ErrFlag;
1555}
1556
1557
1558/*
1559 * Set 10/100 phyxcer capability
1560 * AUTO mode : phyxcer register4 is NIC capability
1561 * Force mode: phyxcer register4 is the force media
1562 */
1563
1564static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1565{
1566 u16 phy_reg;
f3b197ac 1567
4689ced9
PC		 1568 /* Phyxcer capability setting */
1569 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1570
1571 if (db->media_mode & ULI526X_AUTO) {
1572 /* AUTO Mode */
1573 phy_reg |= db->PHY_reg4;
1574 } else {
1575 /* Force Mode */
1576 switch(db->media_mode) {
1577 case ULI526X_10MHF: phy_reg |= 0x20; break;
1578 case ULI526X_10MFD: phy_reg |= 0x40; break;
1579 case ULI526X_100MHF: phy_reg |= 0x80; break;
1580 case ULI526X_100MFD: phy_reg |= 0x100; break;
1581 }
f3b197ac 1582
4689ced9
PC		 1583 }
1584
1585 /* Write new capability to Phyxcer Reg4 */
1586 if ( !(phy_reg & 0x01e0)) {
1587 phy_reg|=db->PHY_reg4;
1588 db->media_mode|=ULI526X_AUTO;
1589 }
1590 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1591
1592 /* Restart Auto-Negotiation */
1593 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1594 udelay(50);
1595}
1596
1597
1598/*
1599 * Process op-mode
1600 AUTO mode : PHY controller in Auto-negotiation Mode
1601 * Force mode: PHY controller in force mode with HUB
1602 * N-way force capability with SWITCH
1603 */
1604
1605static void uli526x_process_mode(struct uli526x_board_info *db)
1606{
1607 u16 phy_reg;
1608
1609 /* Full Duplex Mode Check */
1610 if (db->op_mode & 0x4)
1611 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1612 else
1613 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1614
1615 update_cr6(db->cr6_data, db->ioaddr);
1616
1617 /* 10/100M phyxcer force mode need */
1618 if ( !(db->media_mode & 0x8)) {
1619 /* Forece Mode */
1620 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1621 if ( !(phy_reg & 0x1) ) {
1622 /* parter without N-Way capability */
1623 phy_reg = 0x0;
1624 switch(db->op_mode) {
1625 case ULI526X_10MHF: phy_reg = 0x0; break;
1626 case ULI526X_10MFD: phy_reg = 0x100; break;
1627 case ULI526X_100MHF: phy_reg = 0x2000; break;
1628 case ULI526X_100MFD: phy_reg = 0x2100; break;
1629 }
1630 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
4689ced9
PC		 1631 }
1632 }
1633}
1634
1635
1636/*
1637 * Write a word to Phy register
1638 */
1639
1640static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1641{
1642 u16 i;
1643 unsigned long ioaddr;
1644
1645 if(chip_id == PCI_ULI5263_ID)
1646 {
1647 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1648 return;
1649 }
1650 /* M5261/M5263 Chip */
1651 ioaddr = iobase + DCR9;
1652
1653 /* Send 33 synchronization clock to Phy controller */
1654 for (i = 0; i < 35; i++)
1655 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1656
1657 /* Send start command(01) to Phy */
1658 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1659 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1660
1661 /* Send write command(01) to Phy */
1662 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1663 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1664
1665 /* Send Phy address */
1666 for (i = 0x10; i > 0; i = i >> 1)
1667 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1668
1669 /* Send register address */
1670 for (i = 0x10; i > 0; i = i >> 1)
1671 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1672
1673 /* written trasnition */
1674 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1675 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1676
1677 /* Write a word data to PHY controller */
1678 for ( i = 0x8000; i > 0; i >>= 1)
1679 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
f3b197ac 1680
4689ced9
PC		 1681}
1682
1683
1684/*
1685 * Read a word data from phy register
1686 */
1687
1688static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1689{
1690 int i;
1691 u16 phy_data;
1692 unsigned long ioaddr;
1693
1694 if(chip_id == PCI_ULI5263_ID)
1695 return phy_readby_cr10(iobase, phy_addr, offset);
1696 /* M5261/M5263 Chip */
1697 ioaddr = iobase + DCR9;
f3b197ac 1698
4689ced9
PC		 1699 /* Send 33 synchronization clock to Phy controller */
1700 for (i = 0; i < 35; i++)
1701 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1702
1703 /* Send start command(01) to Phy */
1704 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1705 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1706
1707 /* Send read command(10) to Phy */
1708 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1709 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1710
1711 /* Send Phy address */
1712 for (i = 0x10; i > 0; i = i >> 1)
1713 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1714
1715 /* Send register address */
1716 for (i = 0x10; i > 0; i = i >> 1)
1717 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1718
1719 /* Skip transition state */
1720 phy_read_1bit(ioaddr, chip_id);
1721
1722 /* read 16bit data */
1723 for (phy_data = 0, i = 0; i < 16; i++) {
1724 phy_data <<= 1;
1725 phy_data |= phy_read_1bit(ioaddr, chip_id);
1726 }
1727
1728 return phy_data;
1729}
1730
1731static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1732{
1733 unsigned long ioaddr,cr10_value;
f3b197ac 1734
4689ced9
PC		 1735 ioaddr = iobase + DCR10;
1736 cr10_value = phy_addr;
1737 cr10_value = (cr10_value<<5) + offset;
1738 cr10_value = (cr10_value<<16) + 0x08000000;
1739 outl(cr10_value,ioaddr);
1740 udelay(1);
1741 while(1)
1742 {
1743 cr10_value = inl(ioaddr);
1744 if(cr10_value&0x10000000)
1745 break;
1746 }
1747 return (cr10_value&0x0ffff);
1748}
1749
1750static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1751{
1752 unsigned long ioaddr,cr10_value;
f3b197ac 1753
4689ced9
PC		 1754 ioaddr = iobase + DCR10;
1755 cr10_value = phy_addr;
1756 cr10_value = (cr10_value<<5) + offset;
1757 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1758 outl(cr10_value,ioaddr);
1759 udelay(1);
1760}
1761/*
1762 * Write one bit data to Phy Controller
1763 */
1764
1765static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1766{
1767 outl(phy_data , ioaddr); /* MII Clock Low */
1768 udelay(1);
1769 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1770 udelay(1);
1771 outl(phy_data , ioaddr); /* MII Clock Low */
1772 udelay(1);
1773}
1774
1775
1776/*
1777 * Read one bit phy data from PHY controller
1778 */
1779
1780static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1781{
1782 u16 phy_data;
f3b197ac 1783
4689ced9
PC		 1784 outl(0x50000 , ioaddr);
1785 udelay(1);
1786 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1787 outl(0x40000 , ioaddr);
1788 udelay(1);
1789
1790 return phy_data;
1791}
1792
1793
1794static struct pci_device_id uli526x_pci_tbl[] = {
1795 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1796 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1797 { 0, }
1798};
1799MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1800
1801
1802static struct pci_driver uli526x_driver = {
1803 .name = "uli526x",
1804 .id_table = uli526x_pci_tbl,
1805 .probe = uli526x_init_one,
1806 .remove = __devexit_p(uli526x_remove_one),
b6aec32a
RW		 1807 .suspend = uli526x_suspend,
1808 .resume = uli526x_resume,
4689ced9
PC		 1809};
1810
1811MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1812MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1813MODULE_LICENSE("GPL");
1814
c213460f
ES		 1815module_param(debug, int, 0644);
1816module_param(mode, int, 0);
1817module_param(cr6set, int, 0);
4689ced9
PC		 1818MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1819MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1820
1821/* Description:
1822 * when user used insmod to add module, system invoked init_module()
945a7876 1823 * to register the services.
4689ced9
PC		 1824 */
1825
1826static int __init uli526x_init_module(void)
1827{
4689ced9
PC		 1828
1829 printk(version);
1830 printed_version = 1;
1831
1832 ULI526X_DBUG(0, "init_module() ", debug);
1833
1834 if (debug)
1835 uli526x_debug = debug; /* set debug flag */
1836 if (cr6set)
1837 uli526x_cr6_user_set = cr6set;
1838
e1c3e501 1839 switch (mode) {
4689ced9
PC		 1840 case ULI526X_10MHF:
1841 case ULI526X_100MHF:
1842 case ULI526X_10MFD:
1843 case ULI526X_100MFD:
1844 uli526x_media_mode = mode;
1845 break;
e1c3e501
HK		 1846 default:
1847 uli526x_media_mode = ULI526X_AUTO;
4689ced9
PC		 1848 break;
1849 }
1850
e1c3e501 1851 return pci_register_driver(&uli526x_driver);
4689ced9
PC		 1852}
1853
1854
1855/*
1856 * Description:
1857 * when user used rmmod to delete module, system invoked clean_module()
1858 * to un-register all registered services.
1859 */
1860
1861static void __exit uli526x_cleanup_module(void)
1862{
1863 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1864 pci_unregister_driver(&uli526x_driver);
1865}
1866
1867module_init(uli526x_init_module);
1868module_exit(uli526x_cleanup_module);
Linux 6.x block layer and io_uring tree(s)