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[linux-2.6-block.git] / drivers / net / tulip / uli526x.c
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4689ced9
PC		 1/*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
f3b197ac 12
4689ced9
PC		 13*/
14
15#define DRV_NAME "uli526x"
16#define DRV_VERSION "0.9.3"
17#define DRV_RELDATE "2005-7-29"
18
19#include <linux/module.h>
20
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/timer.h>
4689ced9
PC		 24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/slab.h>
27#include <linux/interrupt.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/skbuff.h>
34#include <linux/delay.h>
35#include <linux/spinlock.h>
6cafa99f 36#include <linux/dma-mapping.h>
1977f032 37#include <linux/bitops.h>
4689ced9
PC		 38
39#include <asm/processor.h>
4689ced9
PC		 40#include <asm/io.h>
41#include <asm/dma.h>
42#include <asm/uaccess.h>
43
44
45/* Board/System/Debug information/definition ---------------- */
46#define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
47#define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
48
49#define ULI526X_IO_SIZE 0x100
50#define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
51#define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
52#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
53#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
54#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55#define TX_BUF_ALLOC 0x600
56#define RX_ALLOC_SIZE 0x620
57#define ULI526X_RESET 1
58#define CR0_DEFAULT 0
945a7876 59#define CR6_DEFAULT 0x22200000
4689ced9
PC		 60#define CR7_DEFAULT 0x180c1
61#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
62#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
63#define MAX_PACKET_SIZE 1514
64#define ULI5261_MAX_MULTICAST 14
65#define RX_COPY_SIZE 100
66#define MAX_CHECK_PACKET 0x8000
67
68#define ULI526X_10MHF 0
69#define ULI526X_100MHF 1
70#define ULI526X_10MFD 4
71#define ULI526X_100MFD 5
72#define ULI526X_AUTO 8
73
74#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
75#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
76#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
77#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
78#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
79#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
80
81#define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
82#define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
83#define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
84
85#define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
86
87#define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
88
89
90/* CR9 definition: SROM/MII */
91#define CR9_SROM_READ 0x4800
92#define CR9_SRCS 0x1
93#define CR9_SRCLK 0x2
94#define CR9_CRDOUT 0x8
95#define SROM_DATA_0 0x0
96#define SROM_DATA_1 0x4
97#define PHY_DATA_1 0x20000
98#define PHY_DATA_0 0x00000
99#define MDCLKH 0x10000
100
101#define PHY_POWER_DOWN 0x800
102
103#define SROM_V41_CODE 0x14
104
945a7876
PC		 105#define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
107 udelay(5); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
109 udelay(5); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
111 udelay(5);
4689ced9
PC		 112
113/* Structure/enum declaration ------------------------------- */
114struct tx_desc {
c559a5bc 115 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
4689ced9
PC		 116 char *tx_buf_ptr; /* Data for us */
117 struct tx_desc *next_tx_desc;
118} __attribute__(( aligned(32) ));
119
120struct rx_desc {
c559a5bc 121 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
4689ced9
PC		 122 struct sk_buff *rx_skb_ptr; /* Data for us */
123 struct rx_desc *next_rx_desc;
124} __attribute__(( aligned(32) ));
125
126struct uli526x_board_info {
127 u32 chip_id; /* Chip vendor/Device ID */
945a7876 128 struct net_device *next_dev; /* next device */
4689ced9
PC		 129 struct pci_dev *pdev; /* PCI device */
130 spinlock_t lock;
131
132 long ioaddr; /* I/O base address */
133 u32 cr0_data;
134 u32 cr5_data;
135 u32 cr6_data;
136 u32 cr7_data;
137 u32 cr15_data;
138
139 /* pointer for memory physical address */
140 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
141 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
142 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
143 dma_addr_t first_tx_desc_dma;
144 dma_addr_t first_rx_desc_dma;
145
146 /* descriptor pointer */
147 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
148 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
149 unsigned char *desc_pool_ptr; /* descriptor pool memory */
150 struct tx_desc *first_tx_desc;
151 struct tx_desc *tx_insert_ptr;
152 struct tx_desc *tx_remove_ptr;
153 struct rx_desc *first_rx_desc;
154 struct rx_desc *rx_insert_ptr;
155 struct rx_desc *rx_ready_ptr; /* packet come pointer */
156 unsigned long tx_packet_cnt; /* transmitted packet count */
157 unsigned long rx_avail_cnt; /* available rx descriptor count */
158 unsigned long interval_rx_cnt; /* rx packet count a callback time */
159
160 u16 dbug_cnt;
161 u16 NIC_capability; /* NIC media capability */
162 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
163
164 u8 media_mode; /* user specify media mode */
165 u8 op_mode; /* real work media mode */
166 u8 phy_addr;
167 u8 link_failed; /* Ever link failed */
168 u8 wait_reset; /* Hardware failed, need to reset */
169 struct timer_list timer;
170
171 /* System defined statistic counter */
172 struct net_device_stats stats;
173
174 /* Driver defined statistic counter */
175 unsigned long tx_fifo_underrun;
176 unsigned long tx_loss_carrier;
177 unsigned long tx_no_carrier;
178 unsigned long tx_late_collision;
179 unsigned long tx_excessive_collision;
180 unsigned long tx_jabber_timeout;
181 unsigned long reset_count;
182 unsigned long reset_cr8;
183 unsigned long reset_fatal;
184 unsigned long reset_TXtimeout;
185
186 /* NIC SROM data */
187 unsigned char srom[128];
f3b197ac 188 u8 init;
4689ced9
PC		 189};
190
191enum uli526x_offsets {
192 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
193 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
194 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
195 DCR15 = 0x78
196};
197
198enum uli526x_CR6_bits {
199 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
200 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
201 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
202};
203
204/* Global variable declaration ----------------------------- */
205static int __devinitdata printed_version;
206static char version[] __devinitdata =
207 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
208 DRV_VERSION " (" DRV_RELDATE ")\n";
209
210static int uli526x_debug;
211static unsigned char uli526x_media_mode = ULI526X_AUTO;
212static u32 uli526x_cr6_user_set;
213
214/* For module input parameter */
215static int debug;
216static u32 cr6set;
99bb2579 217static int mode = 8;
4689ced9
PC		 218
219/* function declaration ------------------------------------- */
945a7876
PC		 220static int uli526x_open(struct net_device *);
221static int uli526x_start_xmit(struct sk_buff *, struct net_device *);
222static int uli526x_stop(struct net_device *);
223static struct net_device_stats * uli526x_get_stats(struct net_device *);
224static void uli526x_set_filter_mode(struct net_device *);
7282d491 225static const struct ethtool_ops netdev_ethtool_ops;
945a7876 226static u16 read_srom_word(long, int);
7d12e780 227static irqreturn_t uli526x_interrupt(int, void *);
4689ced9
PC		 228static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
229static void allocate_rx_buffer(struct uli526x_board_info *);
230static void update_cr6(u32, unsigned long);
945a7876 231static void send_filter_frame(struct net_device *, int);
4689ced9
PC		 232static u16 phy_read(unsigned long, u8, u8, u32);
233static u16 phy_readby_cr10(unsigned long, u8, u8);
234static void phy_write(unsigned long, u8, u8, u16, u32);
235static void phy_writeby_cr10(unsigned long, u8, u8, u16);
236static void phy_write_1bit(unsigned long, u32, u32);
237static u16 phy_read_1bit(unsigned long, u32);
238static u8 uli526x_sense_speed(struct uli526x_board_info *);
239static void uli526x_process_mode(struct uli526x_board_info *);
240static void uli526x_timer(unsigned long);
945a7876
PC		 241static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
242static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
4689ced9 243static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
945a7876 244static void uli526x_dynamic_reset(struct net_device *);
4689ced9 245static void uli526x_free_rxbuffer(struct uli526x_board_info *);
945a7876 246static void uli526x_init(struct net_device *);
4689ced9
PC		 247static void uli526x_set_phyxcer(struct uli526x_board_info *);
248
945a7876 249/* ULI526X network board routine ---------------------------- */
4689ced9
PC		 250
251/*
945a7876 252 * Search ULI526X board, allocate space and register it
4689ced9
PC		 253 */
254
255static int __devinit uli526x_init_one (struct pci_dev *pdev,
256 const struct pci_device_id *ent)
257{
258 struct uli526x_board_info *db; /* board information structure */
259 struct net_device *dev;
260 int i, err;
0795af57 261 DECLARE_MAC_BUF(mac);
f3b197ac 262
4689ced9
PC		 263 ULI526X_DBUG(0, "uli526x_init_one()", 0);
264
265 if (!printed_version++)
266 printk(version);
267
268 /* Init network device */
269 dev = alloc_etherdev(sizeof(*db));
270 if (dev == NULL)
271 return -ENOMEM;
4689ced9
PC		 272 SET_NETDEV_DEV(dev, &pdev->dev);
273
945a7876 274 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
4689ced9
PC		 275 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
276 err = -ENODEV;
277 goto err_out_free;
278 }
279
280 /* Enable Master/IO access, Disable memory access */
281 err = pci_enable_device(pdev);
282 if (err)
283 goto err_out_free;
284
285 if (!pci_resource_start(pdev, 0)) {
286 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
287 err = -ENODEV;
288 goto err_out_disable;
289 }
290
291 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
292 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
293 err = -ENODEV;
294 goto err_out_disable;
295 }
296
297 if (pci_request_regions(pdev, DRV_NAME)) {
298 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
299 err = -ENODEV;
300 goto err_out_disable;
301 }
302
4689ced9
PC		 303 /* Init system & device */
304 db = netdev_priv(dev);
305
306 /* Allocate Tx/Rx descriptor memory */
307 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
945a7876
PC		 308 if(db->desc_pool_ptr == NULL)
309 {
310 err = -ENOMEM;
311 goto err_out_nomem;
312 }
4689ced9 313 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
945a7876
PC		 314 if(db->buf_pool_ptr == NULL)
315 {
316 err = -ENOMEM;
317 goto err_out_nomem;
318 }
f3b197ac 319
4689ced9
PC		 320 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
321 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
322 db->buf_pool_start = db->buf_pool_ptr;
323 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
324
325 db->chip_id = ent->driver_data;
326 db->ioaddr = pci_resource_start(pdev, 0);
f3b197ac 327
4689ced9
PC		 328 db->pdev = pdev;
329 db->init = 1;
f3b197ac 330
4689ced9
PC		 331 dev->base_addr = db->ioaddr;
332 dev->irq = pdev->irq;
333 pci_set_drvdata(pdev, dev);
f3b197ac 334
4689ced9
PC		 335 /* Register some necessary functions */
336 dev->open = &uli526x_open;
337 dev->hard_start_xmit = &uli526x_start_xmit;
338 dev->stop = &uli526x_stop;
339 dev->get_stats = &uli526x_get_stats;
340 dev->set_multicast_list = &uli526x_set_filter_mode;
341 dev->ethtool_ops = &netdev_ethtool_ops;
342 spin_lock_init(&db->lock);
343
f3b197ac 344
4689ced9
PC		 345 /* read 64 word srom data */
346 for (i = 0; i < 64; i++)
c559a5bc 347 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
4689ced9
PC		 348
349 /* Set Node address */
945a7876 350 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
4689ced9
PC		 351 {
352 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
353 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
354 outl(0, db->ioaddr + DCR14); //Clear reset port
355 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
356 outl(0, db->ioaddr + DCR14); //Clear reset port
357 outl(0, db->ioaddr + DCR13); //Clear CR13
358 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
359 //Read MAC address from CR14
360 for (i = 0; i < 6; i++)
361 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
362 //Read end
363 outl(0, db->ioaddr + DCR13); //Clear CR13
364 outl(0, db->ioaddr + DCR0); //Clear CR0
365 udelay(10);
366 }
367 else /*Exist SROM*/
368 {
369 for (i = 0; i < 6; i++)
370 dev->dev_addr[i] = db->srom[20 + i];
371 }
372 err = register_netdev (dev);
373 if (err)
374 goto err_out_res;
375
0795af57
JP		 376 printk(KERN_INFO "%s: ULi M%04lx at pci%s, %s, irq %d.\n",
377 dev->name,ent->driver_data >> 16,pci_name(pdev),
378 print_mac(mac, dev->dev_addr), dev->irq);
4689ced9
PC		 379
380 pci_set_master(pdev);
381
382 return 0;
383
384err_out_res:
385 pci_release_regions(pdev);
945a7876
PC		 386err_out_nomem:
387 if(db->desc_pool_ptr)
388 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
389 db->desc_pool_ptr, db->desc_pool_dma_ptr);
f3b197ac 390
945a7876
PC		 391 if(db->buf_pool_ptr != NULL)
392 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
393 db->buf_pool_ptr, db->buf_pool_dma_ptr);
4689ced9
PC		 394err_out_disable:
395 pci_disable_device(pdev);
396err_out_free:
397 pci_set_drvdata(pdev, NULL);
398 free_netdev(dev);
399
400 return err;
401}
402
403
404static void __devexit uli526x_remove_one (struct pci_dev *pdev)
405{
406 struct net_device *dev = pci_get_drvdata(pdev);
407 struct uli526x_board_info *db = netdev_priv(dev);
408
409 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
410
945a7876
PC		 411 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
412 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
413 db->desc_pool_dma_ptr);
414 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
415 db->buf_pool_ptr, db->buf_pool_dma_ptr);
416 unregister_netdev(dev);
417 pci_release_regions(pdev);
418 free_netdev(dev); /* free board information */
419 pci_set_drvdata(pdev, NULL);
420 pci_disable_device(pdev);
4689ced9
PC		 421 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
422}
423
424
425/*
426 * Open the interface.
945a7876 427 * The interface is opened whenever "ifconfig" activates it.
4689ced9
PC		 428 */
429
945a7876 430static int uli526x_open(struct net_device *dev)
4689ced9
PC		 431{
432 int ret;
433 struct uli526x_board_info *db = netdev_priv(dev);
f3b197ac 434
4689ced9
PC		 435 ULI526X_DBUG(0, "uli526x_open", 0);
436
1fb9df5d 437 ret = request_irq(dev->irq, &uli526x_interrupt, IRQF_SHARED, dev->name, dev);
4689ced9
PC		 438 if (ret)
439 return ret;
440
441 /* system variable init */
442 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
4689ced9
PC		 443 db->tx_packet_cnt = 0;
444 db->rx_avail_cnt = 0;
445 db->link_failed = 1;
446 netif_carrier_off(dev);
447 db->wait_reset = 0;
448
449 db->NIC_capability = 0xf; /* All capability*/
450 db->PHY_reg4 = 0x1e0;
451
452 /* CR6 operation mode decision */
453 db->cr6_data |= ULI526X_TXTH_256;
454 db->cr0_data = CR0_DEFAULT;
f3b197ac 455
945a7876 456 /* Initialize ULI526X board */
4689ced9
PC		 457 uli526x_init(dev);
458
459 /* Active System Interface */
460 netif_wake_queue(dev);
461
462 /* set and active a timer process */
463 init_timer(&db->timer);
464 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
465 db->timer.data = (unsigned long)dev;
466 db->timer.function = &uli526x_timer;
467 add_timer(&db->timer);
468
469 return 0;
470}
471
472
945a7876 473/* Initialize ULI526X board
4689ced9 474 * Reset ULI526X board
945a7876 475 * Initialize TX/Rx descriptor chain structure
4689ced9
PC		 476 * Send the set-up frame
477 * Enable Tx/Rx machine
478 */
479
945a7876 480static void uli526x_init(struct net_device *dev)
4689ced9
PC		 481{
482 struct uli526x_board_info *db = netdev_priv(dev);
483 unsigned long ioaddr = db->ioaddr;
484 u8 phy_tmp;
485 u16 phy_value;
486 u16 phy_reg_reset;
487
488 ULI526X_DBUG(0, "uli526x_init()", 0);
489
490 /* Reset M526x MAC controller */
491 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
492 udelay(100);
493 outl(db->cr0_data, ioaddr + DCR0);
494 udelay(5);
495
496 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
497 db->phy_addr = 1;
498 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
499 {
500 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
501 if(phy_value != 0xffff&&phy_value!=0)
502 {
503 db->phy_addr = phy_tmp;
504 break;
505 }
506 }
507 if(phy_tmp == 32)
508 printk(KERN_WARNING "Can not find the phy address!!!");
509 /* Parser SROM and media mode */
510 db->media_mode = uli526x_media_mode;
511
4689ced9
PC		 512 /* Phyxcer capability setting */
513 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
514 phy_reg_reset = (phy_reg_reset | 0x8000);
515 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
516 udelay(500);
517
518 /* Process Phyxcer Media Mode */
519 uli526x_set_phyxcer(db);
520
521 /* Media Mode Process */
522 if ( !(db->media_mode & ULI526X_AUTO) )
523 db->op_mode = db->media_mode; /* Force Mode */
524
945a7876 525 /* Initialize Transmit/Receive decriptor and CR3/4 */
4689ced9
PC		 526 uli526x_descriptor_init(db, ioaddr);
527
528 /* Init CR6 to program M526X operation */
529 update_cr6(db->cr6_data, ioaddr);
530
531 /* Send setup frame */
532 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
533
534 /* Init CR7, interrupt active bit */
535 db->cr7_data = CR7_DEFAULT;
536 outl(db->cr7_data, ioaddr + DCR7);
537
538 /* Init CR15, Tx jabber and Rx watchdog timer */
539 outl(db->cr15_data, ioaddr + DCR15);
540
541 /* Enable ULI526X Tx/Rx function */
542 db->cr6_data |= CR6_RXSC | CR6_TXSC;
543 update_cr6(db->cr6_data, ioaddr);
544}
545
546
547/*
548 * Hardware start transmission.
549 * Send a packet to media from the upper layer.
550 */
551
945a7876 552static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev)
4689ced9
PC		 553{
554 struct uli526x_board_info *db = netdev_priv(dev);
555 struct tx_desc *txptr;
556 unsigned long flags;
557
558 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
559
560 /* Resource flag check */
561 netif_stop_queue(dev);
562
563 /* Too large packet check */
564 if (skb->len > MAX_PACKET_SIZE) {
565 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
566 dev_kfree_skb(skb);
567 return 0;
568 }
569
570 spin_lock_irqsave(&db->lock, flags);
571
572 /* No Tx resource check, it never happen nromally */
573 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
574 spin_unlock_irqrestore(&db->lock, flags);
575 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt);
576 return 1;
577 }
578
579 /* Disable NIC interrupt */
580 outl(0, dev->base_addr + DCR7);
581
582 /* transmit this packet */
583 txptr = db->tx_insert_ptr;
d626f62b 584 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
4689ced9
PC		 585 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
586
587 /* Point to next transmit free descriptor */
588 db->tx_insert_ptr = txptr->next_tx_desc;
589
590 /* Transmit Packet Process */
591 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
592 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
593 db->tx_packet_cnt++; /* Ready to send */
594 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
595 dev->trans_start = jiffies; /* saved time stamp */
596 }
597
598 /* Tx resource check */
599 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
600 netif_wake_queue(dev);
601
602 /* Restore CR7 to enable interrupt */
603 spin_unlock_irqrestore(&db->lock, flags);
604 outl(db->cr7_data, dev->base_addr + DCR7);
f3b197ac 605
4689ced9
PC		 606 /* free this SKB */
607 dev_kfree_skb(skb);
608
609 return 0;
610}
611
612
613/*
614 * Stop the interface.
615 * The interface is stopped when it is brought.
616 */
617
945a7876 618static int uli526x_stop(struct net_device *dev)
4689ced9
PC		 619{
620 struct uli526x_board_info *db = netdev_priv(dev);
621 unsigned long ioaddr = dev->base_addr;
622
623 ULI526X_DBUG(0, "uli526x_stop", 0);
624
625 /* disable system */
626 netif_stop_queue(dev);
627
628 /* deleted timer */
629 del_timer_sync(&db->timer);
630
631 /* Reset & stop ULI526X board */
632 outl(ULI526X_RESET, ioaddr + DCR0);
633 udelay(5);
634 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
635
636 /* free interrupt */
637 free_irq(dev->irq, dev);
638
639 /* free allocated rx buffer */
640 uli526x_free_rxbuffer(db);
641
642#if 0
643 /* show statistic counter */
644 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
645 db->tx_fifo_underrun, db->tx_excessive_collision,
646 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
647 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
648 db->reset_fatal, db->reset_TXtimeout);
649#endif
650
651 return 0;
652}
653
654
655/*
656 * M5261/M5263 insterrupt handler
657 * receive the packet to upper layer, free the transmitted packet
658 */
659
7d12e780 660static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
4689ced9 661{
945a7876 662 struct net_device *dev = dev_id;
4689ced9
PC		 663 struct uli526x_board_info *db = netdev_priv(dev);
664 unsigned long ioaddr = dev->base_addr;
665 unsigned long flags;
666
4689ced9
PC		 667 spin_lock_irqsave(&db->lock, flags);
668 outl(0, ioaddr + DCR7);
669
670 /* Got ULI526X status */
671 db->cr5_data = inl(ioaddr + DCR5);
672 outl(db->cr5_data, ioaddr + DCR5);
673 if ( !(db->cr5_data & 0x180c1) ) {
674 spin_unlock_irqrestore(&db->lock, flags);
675 outl(db->cr7_data, ioaddr + DCR7);
676 return IRQ_HANDLED;
677 }
678
4689ced9
PC		 679 /* Check system status */
680 if (db->cr5_data & 0x2000) {
681 /* system bus error happen */
682 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
683 db->reset_fatal++;
684 db->wait_reset = 1; /* Need to RESET */
685 spin_unlock_irqrestore(&db->lock, flags);
686 return IRQ_HANDLED;
687 }
688
689 /* Received the coming packet */
690 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
691 uli526x_rx_packet(dev, db);
692
693 /* reallocate rx descriptor buffer */
694 if (db->rx_avail_cnt<RX_DESC_CNT)
695 allocate_rx_buffer(db);
696
697 /* Free the transmitted descriptor */
698 if ( db->cr5_data & 0x01)
699 uli526x_free_tx_pkt(dev, db);
700
701 /* Restore CR7 to enable interrupt mask */
702 outl(db->cr7_data, ioaddr + DCR7);
703
704 spin_unlock_irqrestore(&db->lock, flags);
705 return IRQ_HANDLED;
706}
707
708
709/*
710 * Free TX resource after TX complete
711 */
712
945a7876 713static void uli526x_free_tx_pkt(struct net_device *dev, struct uli526x_board_info * db)
4689ced9
PC		 714{
715 struct tx_desc *txptr;
4689ced9
PC		 716 u32 tdes0;
717
718 txptr = db->tx_remove_ptr;
719 while(db->tx_packet_cnt) {
720 tdes0 = le32_to_cpu(txptr->tdes0);
721 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
722 if (tdes0 & 0x80000000)
723 break;
724
725 /* A packet sent completed */
726 db->tx_packet_cnt--;
727 db->stats.tx_packets++;
728
729 /* Transmit statistic counter */
730 if ( tdes0 != 0x7fffffff ) {
731 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
732 db->stats.collisions += (tdes0 >> 3) & 0xf;
733 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
734 if (tdes0 & TDES0_ERR_MASK) {
735 db->stats.tx_errors++;
736 if (tdes0 & 0x0002) { /* UnderRun */
737 db->tx_fifo_underrun++;
738 if ( !(db->cr6_data & CR6_SFT) ) {
739 db->cr6_data = db->cr6_data | CR6_SFT;
740 update_cr6(db->cr6_data, db->ioaddr);
741 }
742 }
743 if (tdes0 & 0x0100)
744 db->tx_excessive_collision++;
745 if (tdes0 & 0x0200)
746 db->tx_late_collision++;
747 if (tdes0 & 0x0400)
748 db->tx_no_carrier++;
749 if (tdes0 & 0x0800)
750 db->tx_loss_carrier++;
751 if (tdes0 & 0x4000)
752 db->tx_jabber_timeout++;
753 }
754 }
755
756 txptr = txptr->next_tx_desc;
757 }/* End of while */
758
759 /* Update TX remove pointer to next */
760 db->tx_remove_ptr = txptr;
761
762 /* Resource available check */
763 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
764 netif_wake_queue(dev); /* Active upper layer, send again */
765}
766
767
768/*
769 * Receive the come packet and pass to upper layer
770 */
771
945a7876 772static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
4689ced9
PC		 773{
774 struct rx_desc *rxptr;
775 struct sk_buff *skb;
776 int rxlen;
777 u32 rdes0;
f3b197ac 778
4689ced9
PC		 779 rxptr = db->rx_ready_ptr;
780
781 while(db->rx_avail_cnt) {
782 rdes0 = le32_to_cpu(rxptr->rdes0);
783 if (rdes0 & 0x80000000) /* packet owner check */
784 {
785 break;
786 }
787
788 db->rx_avail_cnt--;
789 db->interval_rx_cnt++;
790
791 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
792 if ( (rdes0 & 0x300) != 0x300) {
793 /* A packet without First/Last flag */
794 /* reuse this SKB */
795 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
796 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
797 } else {
798 /* A packet with First/Last flag */
799 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
800
801 /* error summary bit check */
802 if (rdes0 & 0x8000) {
803 /* This is a error packet */
804 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
805 db->stats.rx_errors++;
806 if (rdes0 & 1)
807 db->stats.rx_fifo_errors++;
808 if (rdes0 & 2)
809 db->stats.rx_crc_errors++;
810 if (rdes0 & 0x80)
811 db->stats.rx_length_errors++;
812 }
813
814 if ( !(rdes0 & 0x8000) ||
815 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
816 skb = rxptr->rx_skb_ptr;
f3b197ac 817
4689ced9
PC		 818 /* Good packet, send to upper layer */
819 /* Shorst packet used new SKB */
820 if ( (rxlen < RX_COPY_SIZE) &&
821 ( (skb = dev_alloc_skb(rxlen + 2) )
822 != NULL) ) {
823 /* size less than COPY_SIZE, allocate a rxlen SKB */
4689ced9 824 skb_reserve(skb, 2); /* 16byte align */
27a884dc
ACM		 825 memcpy(skb_put(skb, rxlen),
826 skb_tail_pointer(rxptr->rx_skb_ptr),
827 rxlen);
4689ced9 828 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 829 } else
4689ced9 830 skb_put(skb, rxlen);
4c13eb66 831
4689ced9
PC		 832 skb->protocol = eth_type_trans(skb, dev);
833 netif_rx(skb);
834 dev->last_rx = jiffies;
835 db->stats.rx_packets++;
836 db->stats.rx_bytes += rxlen;
f3b197ac 837
4689ced9
PC		 838 } else {
839 /* Reuse SKB buffer when the packet is error */
840 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
841 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
842 }
843 }
844
845 rxptr = rxptr->next_rx_desc;
846 }
847
848 db->rx_ready_ptr = rxptr;
849}
850
851
852/*
853 * Get statistics from driver.
854 */
855
945a7876 856static struct net_device_stats * uli526x_get_stats(struct net_device *dev)
4689ced9
PC		 857{
858 struct uli526x_board_info *db = netdev_priv(dev);
859
860 ULI526X_DBUG(0, "uli526x_get_stats", 0);
861 return &db->stats;
862}
863
864
865/*
866 * Set ULI526X multicast address
867 */
868
945a7876 869static void uli526x_set_filter_mode(struct net_device * dev)
4689ced9
PC		 870{
871 struct uli526x_board_info *db = dev->priv;
872 unsigned long flags;
873
874 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
875 spin_lock_irqsave(&db->lock, flags);
876
877 if (dev->flags & IFF_PROMISC) {
878 ULI526X_DBUG(0, "Enable PROM Mode", 0);
879 db->cr6_data |= CR6_PM | CR6_PBF;
880 update_cr6(db->cr6_data, db->ioaddr);
881 spin_unlock_irqrestore(&db->lock, flags);
882 return;
883 }
884
885 if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) {
886 ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count);
887 db->cr6_data &= ~(CR6_PM | CR6_PBF);
888 db->cr6_data |= CR6_PAM;
889 spin_unlock_irqrestore(&db->lock, flags);
890 return;
891 }
892
893 ULI526X_DBUG(0, "Set multicast address", dev->mc_count);
894 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
895 spin_unlock_irqrestore(&db->lock, flags);
896}
897
898static void
899ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
900{
945a7876
PC		 901 ecmd->supported = (SUPPORTED_10baseT_Half |
902 SUPPORTED_10baseT_Full |
903 SUPPORTED_100baseT_Half |
904 SUPPORTED_100baseT_Full |
905 SUPPORTED_Autoneg |
906 SUPPORTED_MII);
f3b197ac 907
945a7876
PC		 908 ecmd->advertising = (ADVERTISED_10baseT_Half |
909 ADVERTISED_10baseT_Full |
910 ADVERTISED_100baseT_Half |
911 ADVERTISED_100baseT_Full |
912 ADVERTISED_Autoneg |
913 ADVERTISED_MII);
4689ced9
PC		 914
915
945a7876
PC		 916 ecmd->port = PORT_MII;
917 ecmd->phy_address = db->phy_addr;
4689ced9 918
945a7876 919 ecmd->transceiver = XCVR_EXTERNAL;
f3b197ac 920
4689ced9
PC		 921 ecmd->speed = 10;
922 ecmd->duplex = DUPLEX_HALF;
f3b197ac 923
4689ced9
PC		 924 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
925 {
f3b197ac 926 ecmd->speed = 100;
4689ced9
PC		 927 }
928 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
929 {
930 ecmd->duplex = DUPLEX_FULL;
931 }
932 if(db->link_failed)
933 {
934 ecmd->speed = -1;
f3b197ac 935 ecmd->duplex = -1;
4689ced9 936 }
f3b197ac 937
4689ced9 938 if (db->media_mode & ULI526X_AUTO)
f3b197ac 939 {
4689ced9
PC		 940 ecmd->autoneg = AUTONEG_ENABLE;
941 }
4689ced9
PC		 942}
943
944static void netdev_get_drvinfo(struct net_device *dev,
945 struct ethtool_drvinfo *info)
946{
947 struct uli526x_board_info *np = netdev_priv(dev);
948
949 strcpy(info->driver, DRV_NAME);
950 strcpy(info->version, DRV_VERSION);
951 if (np->pdev)
952 strcpy(info->bus_info, pci_name(np->pdev));
953 else
954 sprintf(info->bus_info, "EISA 0x%lx %d",
955 dev->base_addr, dev->irq);
956}
957
958static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
959 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 960
4689ced9 961 ULi_ethtool_gset(np, cmd);
f3b197ac 962
4689ced9
PC		 963 return 0;
964}
965
966static u32 netdev_get_link(struct net_device *dev) {
967 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 968
4689ced9
PC		 969 if(np->link_failed)
970 return 0;
971 else
972 return 1;
973}
974
975static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
976{
977 wol->supported = WAKE_PHY | WAKE_MAGIC;
978 wol->wolopts = 0;
979}
980
7282d491 981static const struct ethtool_ops netdev_ethtool_ops = {
4689ced9
PC		 982 .get_drvinfo = netdev_get_drvinfo,
983 .get_settings = netdev_get_settings,
984 .get_link = netdev_get_link,
985 .get_wol = uli526x_get_wol,
986};
987
988/*
989 * A periodic timer routine
990 * Dynamic media sense, allocate Rx buffer...
991 */
992
993static void uli526x_timer(unsigned long data)
994{
995 u32 tmp_cr8;
996 unsigned char tmp_cr12=0;
945a7876 997 struct net_device *dev = (struct net_device *) data;
4689ced9
PC		 998 struct uli526x_board_info *db = netdev_priv(dev);
999 unsigned long flags;
1000 u8 TmpSpeed=10;
f3b197ac 1001
4689ced9
PC		 1002 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1003 spin_lock_irqsave(&db->lock, flags);
1004
f3b197ac 1005
4689ced9
PC		 1006 /* Dynamic reset ULI526X : system error or transmit time-out */
1007 tmp_cr8 = inl(db->ioaddr + DCR8);
1008 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1009 db->reset_cr8++;
1010 db->wait_reset = 1;
1011 }
1012 db->interval_rx_cnt = 0;
1013
1014 /* TX polling kick monitor */
1015 if ( db->tx_packet_cnt &&
1016 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
f3b197ac 1017 outl(0x1, dev->base_addr + DCR1); // Tx polling again
4689ced9 1018
f3b197ac 1019 // TX Timeout
4689ced9
PC		 1020 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1021 db->reset_TXtimeout++;
1022 db->wait_reset = 1;
1023 printk( "%s: Tx timeout - resetting\n",
1024 dev->name);
1025 }
1026 }
1027
1028 if (db->wait_reset) {
1029 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1030 db->reset_count++;
1031 uli526x_dynamic_reset(dev);
1032 db->timer.expires = ULI526X_TIMER_WUT;
1033 add_timer(&db->timer);
1034 spin_unlock_irqrestore(&db->lock, flags);
1035 return;
1036 }
1037
1038 /* Link status check, Dynamic media type change */
1039 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1040 tmp_cr12 = 3;
1041
1042 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1043 /* Link Failed */
1044 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1045 netif_carrier_off(dev);
1046 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1047 db->link_failed = 1;
1048
1049 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1050 /* AUTO don't need */
1051 if ( !(db->media_mode & 0x8) )
1052 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1053
1054 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1055 if (db->media_mode & ULI526X_AUTO) {
1056 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1057 update_cr6(db->cr6_data, db->ioaddr);
1058 }
1059 } else
1060 if ((tmp_cr12 & 0x3) && db->link_failed) {
1061 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1062 db->link_failed = 0;
1063
1064 /* Auto Sense Speed */
1065 if ( (db->media_mode & ULI526X_AUTO) &&
1066 uli526x_sense_speed(db) )
1067 db->link_failed = 1;
1068 uli526x_process_mode(db);
f3b197ac 1069
4689ced9
PC		 1070 if(db->link_failed==0)
1071 {
1072 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1073 {
1074 TmpSpeed = 100;
1075 }
1076 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1077 {
1078 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1079 }
1080 else
1081 {
1082 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1083 }
1084 netif_carrier_on(dev);
1085 }
1086 /* SHOW_MEDIA_TYPE(db->op_mode); */
1087 }
1088 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1089 {
1090 if(db->init==1)
1091 {
1092 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1093 netif_carrier_off(dev);
1094 }
1095 }
1096 db->init=0;
1097
1098 /* Timer active again */
1099 db->timer.expires = ULI526X_TIMER_WUT;
1100 add_timer(&db->timer);
1101 spin_unlock_irqrestore(&db->lock, flags);
1102}
1103
1104
1105/*
4689ced9
PC		 1106 * Stop ULI526X board
1107 * Free Tx/Rx allocated memory
b6aec32a 1108 * Init system variable
4689ced9
PC		 1109 */
1110
b6aec32a 1111static void uli526x_reset_prepare(struct net_device *dev)
4689ced9
PC		 1112{
1113 struct uli526x_board_info *db = netdev_priv(dev);
1114
4689ced9
PC		 1115 /* Sopt MAC controller */
1116 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1117 update_cr6(db->cr6_data, dev->base_addr);
1118 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1119 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1120
1121 /* Disable upper layer interface */
1122 netif_stop_queue(dev);
1123
1124 /* Free Rx Allocate buffer */
1125 uli526x_free_rxbuffer(db);
1126
1127 /* system variable init */
1128 db->tx_packet_cnt = 0;
1129 db->rx_avail_cnt = 0;
1130 db->link_failed = 1;
1131 db->init=1;
1132 db->wait_reset = 0;
b6aec32a
RW		 1133}
1134
1135
1136/*
1137 * Dynamic reset the ULI526X board
1138 * Stop ULI526X board
1139 * Free Tx/Rx allocated memory
1140 * Reset ULI526X board
1141 * Re-initialize ULI526X board
1142 */
1143
1144static void uli526x_dynamic_reset(struct net_device *dev)
1145{
1146 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1147
1148 uli526x_reset_prepare(dev);
4689ced9 1149
945a7876 1150 /* Re-initialize ULI526X board */
4689ced9
PC		 1151 uli526x_init(dev);
1152
1153 /* Restart upper layer interface */
1154 netif_wake_queue(dev);
1155}
1156
1157
b6aec32a
RW		 1158#ifdef CONFIG_PM
1159
1160/*
1161 * Suspend the interface.
1162 */
1163
1164static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1165{
1166 struct net_device *dev = pci_get_drvdata(pdev);
1167 pci_power_t power_state;
1168 int err;
1169
1170 ULI526X_DBUG(0, "uli526x_suspend", 0);
1171
1172 if (!netdev_priv(dev))
1173 return 0;
1174
1175 pci_save_state(pdev);
1176
1177 if (!netif_running(dev))
1178 return 0;
1179
1180 netif_device_detach(dev);
1181 uli526x_reset_prepare(dev);
1182
1183 power_state = pci_choose_state(pdev, state);
1184 pci_enable_wake(pdev, power_state, 0);
1185 err = pci_set_power_state(pdev, power_state);
1186 if (err) {
1187 netif_device_attach(dev);
1188 /* Re-initialize ULI526X board */
1189 uli526x_init(dev);
1190 /* Restart upper layer interface */
1191 netif_wake_queue(dev);
1192 }
1193
1194 return err;
1195}
1196
1197/*
1198 * Resume the interface.
1199 */
1200
1201static int uli526x_resume(struct pci_dev *pdev)
1202{
1203 struct net_device *dev = pci_get_drvdata(pdev);
1204 int err;
1205
1206 ULI526X_DBUG(0, "uli526x_resume", 0);
1207
1208 if (!netdev_priv(dev))
1209 return 0;
1210
1211 pci_restore_state(pdev);
1212
1213 if (!netif_running(dev))
1214 return 0;
1215
1216 err = pci_set_power_state(pdev, PCI_D0);
1217 if (err) {
1218 printk(KERN_WARNING "%s: Could not put device into D0\n",
1219 dev->name);
1220 return err;
1221 }
1222
1223 netif_device_attach(dev);
1224 /* Re-initialize ULI526X board */
1225 uli526x_init(dev);
1226 /* Restart upper layer interface */
1227 netif_wake_queue(dev);
1228
1229 return 0;
1230}
1231
1232#else /* !CONFIG_PM */
1233
1234#define uli526x_suspend NULL
1235#define uli526x_resume NULL
1236
1237#endif /* !CONFIG_PM */
1238
1239
4689ced9
PC		 1240/*
1241 * free all allocated rx buffer
1242 */
1243
1244static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1245{
1246 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1247
1248 /* free allocated rx buffer */
1249 while (db->rx_avail_cnt) {
1250 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1251 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1252 db->rx_avail_cnt--;
1253 }
1254}
1255
1256
1257/*
1258 * Reuse the SK buffer
1259 */
1260
1261static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1262{
1263 struct rx_desc *rxptr = db->rx_insert_ptr;
1264
1265 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1266 rxptr->rx_skb_ptr = skb;
27a884dc
ACM		 1267 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1268 skb_tail_pointer(skb),
1269 RX_ALLOC_SIZE,
1270 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1271 wmb();
1272 rxptr->rdes0 = cpu_to_le32(0x80000000);
1273 db->rx_avail_cnt++;
1274 db->rx_insert_ptr = rxptr->next_rx_desc;
1275 } else
1276 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1277}
1278
1279
1280/*
1281 * Initialize transmit/Receive descriptor
1282 * Using Chain structure, and allocate Tx/Rx buffer
1283 */
1284
1285static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1286{
1287 struct tx_desc *tmp_tx;
1288 struct rx_desc *tmp_rx;
1289 unsigned char *tmp_buf;
1290 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1291 dma_addr_t tmp_buf_dma;
1292 int i;
1293
1294 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1295
1296 /* tx descriptor start pointer */
1297 db->tx_insert_ptr = db->first_tx_desc;
1298 db->tx_remove_ptr = db->first_tx_desc;
1299 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1300
1301 /* rx descriptor start pointer */
1302 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1303 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1304 db->rx_insert_ptr = db->first_rx_desc;
1305 db->rx_ready_ptr = db->first_rx_desc;
1306 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1307
1308 /* Init Transmit chain */
1309 tmp_buf = db->buf_pool_start;
1310 tmp_buf_dma = db->buf_pool_dma_start;
1311 tmp_tx_dma = db->first_tx_desc_dma;
1312 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1313 tmp_tx->tx_buf_ptr = tmp_buf;
1314 tmp_tx->tdes0 = cpu_to_le32(0);
1315 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1316 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1317 tmp_tx_dma += sizeof(struct tx_desc);
1318 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1319 tmp_tx->next_tx_desc = tmp_tx + 1;
1320 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1321 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1322 }
1323 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1324 tmp_tx->next_tx_desc = db->first_tx_desc;
1325
1326 /* Init Receive descriptor chain */
1327 tmp_rx_dma=db->first_rx_desc_dma;
1328 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1329 tmp_rx->rdes0 = cpu_to_le32(0);
1330 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1331 tmp_rx_dma += sizeof(struct rx_desc);
1332 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1333 tmp_rx->next_rx_desc = tmp_rx + 1;
1334 }
1335 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1336 tmp_rx->next_rx_desc = db->first_rx_desc;
1337
1338 /* pre-allocate Rx buffer */
1339 allocate_rx_buffer(db);
1340}
1341
1342
1343/*
1344 * Update CR6 value
945a7876 1345 * Firstly stop ULI526X, then written value and start
4689ced9
PC		 1346 */
1347
1348static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1349{
1350
1351 outl(cr6_data, ioaddr + DCR6);
1352 udelay(5);
1353}
1354
1355
1356/*
1357 * Send a setup frame for M5261/M5263
945a7876 1358 * This setup frame initialize ULI526X address filter mode
4689ced9
PC		 1359 */
1360
945a7876 1361static void send_filter_frame(struct net_device *dev, int mc_cnt)
4689ced9
PC		 1362{
1363 struct uli526x_board_info *db = netdev_priv(dev);
1364 struct dev_mc_list *mcptr;
1365 struct tx_desc *txptr;
1366 u16 * addrptr;
1367 u32 * suptr;
1368 int i;
1369
1370 ULI526X_DBUG(0, "send_filter_frame()", 0);
1371
1372 txptr = db->tx_insert_ptr;
1373 suptr = (u32 *) txptr->tx_buf_ptr;
1374
1375 /* Node address */
1376 addrptr = (u16 *) dev->dev_addr;
1377 *suptr++ = addrptr[0];
1378 *suptr++ = addrptr[1];
1379 *suptr++ = addrptr[2];
1380
1381 /* broadcast address */
1382 *suptr++ = 0xffff;
1383 *suptr++ = 0xffff;
1384 *suptr++ = 0xffff;
1385
1386 /* fit the multicast address */
1387 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1388 addrptr = (u16 *) mcptr->dmi_addr;
1389 *suptr++ = addrptr[0];
1390 *suptr++ = addrptr[1];
1391 *suptr++ = addrptr[2];
1392 }
1393
1394 for (; i<14; i++) {
1395 *suptr++ = 0xffff;
1396 *suptr++ = 0xffff;
1397 *suptr++ = 0xffff;
1398 }
1399
1400 /* prepare the setup frame */
1401 db->tx_insert_ptr = txptr->next_tx_desc;
1402 txptr->tdes1 = cpu_to_le32(0x890000c0);
1403
1404 /* Resource Check and Send the setup packet */
1405 if (db->tx_packet_cnt < TX_DESC_CNT) {
1406 /* Resource Empty */
1407 db->tx_packet_cnt++;
1408 txptr->tdes0 = cpu_to_le32(0x80000000);
1409 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1410 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1411 update_cr6(db->cr6_data, dev->base_addr);
1412 dev->trans_start = jiffies;
1413 } else
1414 printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n");
1415}
1416
1417
1418/*
1419 * Allocate rx buffer,
1420 * As possible as allocate maxiumn Rx buffer
1421 */
1422
1423static void allocate_rx_buffer(struct uli526x_board_info *db)
1424{
1425 struct rx_desc *rxptr;
1426 struct sk_buff *skb;
1427
1428 rxptr = db->rx_insert_ptr;
1429
1430 while(db->rx_avail_cnt < RX_DESC_CNT) {
1431 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1432 break;
1433 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
27a884dc
ACM		 1434 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1435 skb_tail_pointer(skb),
1436 RX_ALLOC_SIZE,
1437 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1438 wmb();
1439 rxptr->rdes0 = cpu_to_le32(0x80000000);
1440 rxptr = rxptr->next_rx_desc;
1441 db->rx_avail_cnt++;
1442 }
1443
1444 db->rx_insert_ptr = rxptr;
1445}
1446
1447
1448/*
1449 * Read one word data from the serial ROM
1450 */
1451
1452static u16 read_srom_word(long ioaddr, int offset)
1453{
1454 int i;
1455 u16 srom_data = 0;
1456 long cr9_ioaddr = ioaddr + DCR9;
1457
1458 outl(CR9_SROM_READ, cr9_ioaddr);
1459 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1460
1461 /* Send the Read Command 110b */
1462 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1463 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1464 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1465
1466 /* Send the offset */
1467 for (i = 5; i >= 0; i--) {
1468 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1469 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1470 }
1471
1472 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1473
1474 for (i = 16; i > 0; i--) {
1475 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1476 udelay(5);
1477 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1478 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1479 udelay(5);
1480 }
1481
1482 outl(CR9_SROM_READ, cr9_ioaddr);
1483 return srom_data;
1484}
1485
1486
1487/*
1488 * Auto sense the media mode
1489 */
1490
1491static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1492{
1493 u8 ErrFlag = 0;
1494 u16 phy_mode;
1495
1496 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1497 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1498
1499 if ( (phy_mode & 0x24) == 0x24 ) {
f3b197ac 1500
4689ced9
PC		 1501 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1502 if(phy_mode&0x8000)
1503 phy_mode = 0x8000;
1504 else if(phy_mode&0x4000)
1505 phy_mode = 0x4000;
1506 else if(phy_mode&0x2000)
1507 phy_mode = 0x2000;
1508 else
1509 phy_mode = 0x1000;
f3b197ac 1510
4689ced9
PC		 1511 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1512 switch (phy_mode) {
1513 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1514 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1515 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1516 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1517 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1518 }
1519 } else {
1520 db->op_mode = ULI526X_10MHF;
1521 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1522 ErrFlag = 1;
1523 }
1524
1525 return ErrFlag;
1526}
1527
1528
1529/*
1530 * Set 10/100 phyxcer capability
1531 * AUTO mode : phyxcer register4 is NIC capability
1532 * Force mode: phyxcer register4 is the force media
1533 */
1534
1535static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1536{
1537 u16 phy_reg;
f3b197ac 1538
4689ced9
PC		 1539 /* Phyxcer capability setting */
1540 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1541
1542 if (db->media_mode & ULI526X_AUTO) {
1543 /* AUTO Mode */
1544 phy_reg |= db->PHY_reg4;
1545 } else {
1546 /* Force Mode */
1547 switch(db->media_mode) {
1548 case ULI526X_10MHF: phy_reg |= 0x20; break;
1549 case ULI526X_10MFD: phy_reg |= 0x40; break;
1550 case ULI526X_100MHF: phy_reg |= 0x80; break;
1551 case ULI526X_100MFD: phy_reg |= 0x100; break;
1552 }
f3b197ac 1553
4689ced9
PC		 1554 }
1555
1556 /* Write new capability to Phyxcer Reg4 */
1557 if ( !(phy_reg & 0x01e0)) {
1558 phy_reg|=db->PHY_reg4;
1559 db->media_mode|=ULI526X_AUTO;
1560 }
1561 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1562
1563 /* Restart Auto-Negotiation */
1564 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1565 udelay(50);
1566}
1567
1568
1569/*
1570 * Process op-mode
1571 AUTO mode : PHY controller in Auto-negotiation Mode
1572 * Force mode: PHY controller in force mode with HUB
1573 * N-way force capability with SWITCH
1574 */
1575
1576static void uli526x_process_mode(struct uli526x_board_info *db)
1577{
1578 u16 phy_reg;
1579
1580 /* Full Duplex Mode Check */
1581 if (db->op_mode & 0x4)
1582 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1583 else
1584 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1585
1586 update_cr6(db->cr6_data, db->ioaddr);
1587
1588 /* 10/100M phyxcer force mode need */
1589 if ( !(db->media_mode & 0x8)) {
1590 /* Forece Mode */
1591 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1592 if ( !(phy_reg & 0x1) ) {
1593 /* parter without N-Way capability */
1594 phy_reg = 0x0;
1595 switch(db->op_mode) {
1596 case ULI526X_10MHF: phy_reg = 0x0; break;
1597 case ULI526X_10MFD: phy_reg = 0x100; break;
1598 case ULI526X_100MHF: phy_reg = 0x2000; break;
1599 case ULI526X_100MFD: phy_reg = 0x2100; break;
1600 }
1601 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
4689ced9
PC		 1602 }
1603 }
1604}
1605
1606
1607/*
1608 * Write a word to Phy register
1609 */
1610
1611static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1612{
1613 u16 i;
1614 unsigned long ioaddr;
1615
1616 if(chip_id == PCI_ULI5263_ID)
1617 {
1618 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1619 return;
1620 }
1621 /* M5261/M5263 Chip */
1622 ioaddr = iobase + DCR9;
1623
1624 /* Send 33 synchronization clock to Phy controller */
1625 for (i = 0; i < 35; i++)
1626 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1627
1628 /* Send start command(01) to Phy */
1629 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1630 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1631
1632 /* Send write command(01) to Phy */
1633 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1634 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1635
1636 /* Send Phy address */
1637 for (i = 0x10; i > 0; i = i >> 1)
1638 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1639
1640 /* Send register address */
1641 for (i = 0x10; i > 0; i = i >> 1)
1642 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1643
1644 /* written trasnition */
1645 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1646 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1647
1648 /* Write a word data to PHY controller */
1649 for ( i = 0x8000; i > 0; i >>= 1)
1650 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
f3b197ac 1651
4689ced9
PC		 1652}
1653
1654
1655/*
1656 * Read a word data from phy register
1657 */
1658
1659static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1660{
1661 int i;
1662 u16 phy_data;
1663 unsigned long ioaddr;
1664
1665 if(chip_id == PCI_ULI5263_ID)
1666 return phy_readby_cr10(iobase, phy_addr, offset);
1667 /* M5261/M5263 Chip */
1668 ioaddr = iobase + DCR9;
f3b197ac 1669
4689ced9
PC		 1670 /* Send 33 synchronization clock to Phy controller */
1671 for (i = 0; i < 35; i++)
1672 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1673
1674 /* Send start command(01) to Phy */
1675 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1676 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1677
1678 /* Send read command(10) to Phy */
1679 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1680 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1681
1682 /* Send Phy address */
1683 for (i = 0x10; i > 0; i = i >> 1)
1684 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1685
1686 /* Send register address */
1687 for (i = 0x10; i > 0; i = i >> 1)
1688 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1689
1690 /* Skip transition state */
1691 phy_read_1bit(ioaddr, chip_id);
1692
1693 /* read 16bit data */
1694 for (phy_data = 0, i = 0; i < 16; i++) {
1695 phy_data <<= 1;
1696 phy_data |= phy_read_1bit(ioaddr, chip_id);
1697 }
1698
1699 return phy_data;
1700}
1701
1702static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1703{
1704 unsigned long ioaddr,cr10_value;
f3b197ac 1705
4689ced9
PC		 1706 ioaddr = iobase + DCR10;
1707 cr10_value = phy_addr;
1708 cr10_value = (cr10_value<<5) + offset;
1709 cr10_value = (cr10_value<<16) + 0x08000000;
1710 outl(cr10_value,ioaddr);
1711 udelay(1);
1712 while(1)
1713 {
1714 cr10_value = inl(ioaddr);
1715 if(cr10_value&0x10000000)
1716 break;
1717 }
1718 return (cr10_value&0x0ffff);
1719}
1720
1721static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1722{
1723 unsigned long ioaddr,cr10_value;
f3b197ac 1724
4689ced9
PC		 1725 ioaddr = iobase + DCR10;
1726 cr10_value = phy_addr;
1727 cr10_value = (cr10_value<<5) + offset;
1728 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1729 outl(cr10_value,ioaddr);
1730 udelay(1);
1731}
1732/*
1733 * Write one bit data to Phy Controller
1734 */
1735
1736static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1737{
1738 outl(phy_data , ioaddr); /* MII Clock Low */
1739 udelay(1);
1740 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1741 udelay(1);
1742 outl(phy_data , ioaddr); /* MII Clock Low */
1743 udelay(1);
1744}
1745
1746
1747/*
1748 * Read one bit phy data from PHY controller
1749 */
1750
1751static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1752{
1753 u16 phy_data;
f3b197ac 1754
4689ced9
PC		 1755 outl(0x50000 , ioaddr);
1756 udelay(1);
1757 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1758 outl(0x40000 , ioaddr);
1759 udelay(1);
1760
1761 return phy_data;
1762}
1763
1764
1765static struct pci_device_id uli526x_pci_tbl[] = {
1766 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1767 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1768 { 0, }
1769};
1770MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1771
1772
1773static struct pci_driver uli526x_driver = {
1774 .name = "uli526x",
1775 .id_table = uli526x_pci_tbl,
1776 .probe = uli526x_init_one,
1777 .remove = __devexit_p(uli526x_remove_one),
b6aec32a
RW		 1778 .suspend = uli526x_suspend,
1779 .resume = uli526x_resume,
4689ced9
PC		 1780};
1781
1782MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1783MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1784MODULE_LICENSE("GPL");
1785
c213460f
ES		 1786module_param(debug, int, 0644);
1787module_param(mode, int, 0);
1788module_param(cr6set, int, 0);
4689ced9
PC		 1789MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1790MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1791
1792/* Description:
1793 * when user used insmod to add module, system invoked init_module()
945a7876 1794 * to register the services.
4689ced9
PC		 1795 */
1796
1797static int __init uli526x_init_module(void)
1798{
4689ced9
PC		 1799
1800 printk(version);
1801 printed_version = 1;
1802
1803 ULI526X_DBUG(0, "init_module() ", debug);
1804
1805 if (debug)
1806 uli526x_debug = debug; /* set debug flag */
1807 if (cr6set)
1808 uli526x_cr6_user_set = cr6set;
1809
e1c3e501 1810 switch (mode) {
4689ced9
PC		 1811 case ULI526X_10MHF:
1812 case ULI526X_100MHF:
1813 case ULI526X_10MFD:
1814 case ULI526X_100MFD:
1815 uli526x_media_mode = mode;
1816 break;
e1c3e501
HK		 1817 default:
1818 uli526x_media_mode = ULI526X_AUTO;
4689ced9
PC		 1819 break;
1820 }
1821
e1c3e501 1822 return pci_register_driver(&uli526x_driver);
4689ced9
PC		 1823}
1824
1825
1826/*
1827 * Description:
1828 * when user used rmmod to delete module, system invoked clean_module()
1829 * to un-register all registered services.
1830 */
1831
1832static void __exit uli526x_cleanup_module(void)
1833{
1834 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1835 pci_unregister_driver(&uli526x_driver);
1836}
1837
1838module_init(uli526x_init_module);
1839module_exit(uli526x_cleanup_module);
Linux 6.x block layer and io_uring tree(s)