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1da177e4 LT |
1 | /* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */ |
2 | ||
3 | /* | |
6b92801b | 4 | Maintained by Valerie Henson <val_henson@linux.intel.com> |
1da177e4 LT |
5 | Copyright 2000,2001 The Linux Kernel Team |
6 | Written/copyright 1994-2001 by Donald Becker. | |
7 | ||
8 | This software may be used and distributed according to the terms | |
9 | of the GNU General Public License, incorporated herein by reference. | |
10 | ||
11 | Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} | |
12 | for more information on this driver, or visit the project | |
13 | Web page at http://sourceforge.net/projects/tulip/ | |
14 | ||
15 | */ | |
16 | ||
1da177e4 LT |
17 | |
18 | #define DRV_NAME "tulip" | |
19 | #ifdef CONFIG_TULIP_NAPI | |
d5b20697 | 20 | #define DRV_VERSION "1.1.14-NAPI" /* Keep at least for test */ |
1da177e4 | 21 | #else |
d5b20697 | 22 | #define DRV_VERSION "1.1.14" |
1da177e4 LT |
23 | #endif |
24 | #define DRV_RELDATE "May 11, 2002" | |
25 | ||
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
29 | #include "tulip.h" | |
30 | #include <linux/init.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/mii.h> | |
34 | #include <linux/ethtool.h> | |
35 | #include <linux/crc32.h> | |
36 | #include <asm/unaligned.h> | |
37 | #include <asm/uaccess.h> | |
38 | ||
39 | #ifdef __sparc__ | |
40 | #include <asm/pbm.h> | |
41 | #endif | |
42 | ||
43 | static char version[] __devinitdata = | |
44 | "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n"; | |
45 | ||
46 | ||
47 | /* A few user-configurable values. */ | |
48 | ||
49 | /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ | |
50 | static unsigned int max_interrupt_work = 25; | |
51 | ||
52 | #define MAX_UNITS 8 | |
53 | /* Used to pass the full-duplex flag, etc. */ | |
54 | static int full_duplex[MAX_UNITS]; | |
55 | static int options[MAX_UNITS]; | |
56 | static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */ | |
57 | ||
58 | /* The possible media types that can be set in options[] are: */ | |
59 | const char * const medianame[32] = { | |
60 | "10baseT", "10base2", "AUI", "100baseTx", | |
61 | "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx", | |
62 | "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII", | |
63 | "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4", | |
64 | "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19", | |
65 | "","","","", "","","","", "","","","Transceiver reset", | |
66 | }; | |
67 | ||
68 | /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */ | |
69 | #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \ | |
70 | || defined(__sparc_) || defined(__ia64__) \ | |
71 | || defined(__sh__) || defined(__mips__) | |
72 | static int rx_copybreak = 1518; | |
73 | #else | |
74 | static int rx_copybreak = 100; | |
75 | #endif | |
76 | ||
77 | /* | |
78 | Set the bus performance register. | |
79 | Typical: Set 16 longword cache alignment, no burst limit. | |
80 | Cache alignment bits 15:14 Burst length 13:8 | |
81 | 0000 No alignment 0x00000000 unlimited 0800 8 longwords | |
82 | 4000 8 longwords 0100 1 longword 1000 16 longwords | |
83 | 8000 16 longwords 0200 2 longwords 2000 32 longwords | |
84 | C000 32 longwords 0400 4 longwords | |
85 | Warning: many older 486 systems are broken and require setting 0x00A04800 | |
86 | 8 longword cache alignment, 8 longword burst. | |
87 | ToDo: Non-Intel setting could be better. | |
88 | */ | |
89 | ||
90 | #if defined(__alpha__) || defined(__ia64__) | |
91 | static int csr0 = 0x01A00000 | 0xE000; | |
92 | #elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__) | |
93 | static int csr0 = 0x01A00000 | 0x8000; | |
94 | #elif defined(__sparc__) || defined(__hppa__) | |
95 | /* The UltraSparc PCI controllers will disconnect at every 64-byte | |
96 | * crossing anyways so it makes no sense to tell Tulip to burst | |
97 | * any more than that. | |
98 | */ | |
99 | static int csr0 = 0x01A00000 | 0x9000; | |
100 | #elif defined(__arm__) || defined(__sh__) | |
101 | static int csr0 = 0x01A00000 | 0x4800; | |
102 | #elif defined(__mips__) | |
103 | static int csr0 = 0x00200000 | 0x4000; | |
104 | #else | |
105 | #warning Processor architecture undefined! | |
106 | static int csr0 = 0x00A00000 | 0x4800; | |
107 | #endif | |
108 | ||
109 | /* Operational parameters that usually are not changed. */ | |
110 | /* Time in jiffies before concluding the transmitter is hung. */ | |
111 | #define TX_TIMEOUT (4*HZ) | |
112 | ||
113 | ||
114 | MODULE_AUTHOR("The Linux Kernel Team"); | |
115 | MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver"); | |
116 | MODULE_LICENSE("GPL"); | |
117 | MODULE_VERSION(DRV_VERSION); | |
118 | module_param(tulip_debug, int, 0); | |
119 | module_param(max_interrupt_work, int, 0); | |
120 | module_param(rx_copybreak, int, 0); | |
121 | module_param(csr0, int, 0); | |
122 | module_param_array(options, int, NULL, 0); | |
123 | module_param_array(full_duplex, int, NULL, 0); | |
124 | ||
125 | #define PFX DRV_NAME ": " | |
126 | ||
127 | #ifdef TULIP_DEBUG | |
128 | int tulip_debug = TULIP_DEBUG; | |
129 | #else | |
130 | int tulip_debug = 1; | |
131 | #endif | |
132 | ||
0bb3cf72 FR |
133 | static void tulip_timer(unsigned long data) |
134 | { | |
135 | struct net_device *dev = (struct net_device *)data; | |
136 | struct tulip_private *tp = netdev_priv(dev); | |
1da177e4 | 137 | |
0bb3cf72 FR |
138 | if (netif_running(dev)) |
139 | schedule_work(&tp->media_work); | |
140 | } | |
1da177e4 LT |
141 | |
142 | /* | |
143 | * This table use during operation for capabilities and media timer. | |
144 | * | |
145 | * It is indexed via the values in 'enum chips' | |
146 | */ | |
147 | ||
148 | struct tulip_chip_table tulip_tbl[] = { | |
149 | { }, /* placeholder for array, slot unused currently */ | |
150 | { }, /* placeholder for array, slot unused currently */ | |
151 | ||
152 | /* DC21140 */ | |
153 | { "Digital DS21140 Tulip", 128, 0x0001ebef, | |
0bb3cf72 FR |
154 | HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer, |
155 | tulip_media_task }, | |
1da177e4 LT |
156 | |
157 | /* DC21142, DC21143 */ | |
b892de0b | 158 | { "Digital DS21142/43 Tulip", 128, 0x0801fbff, |
1da177e4 | 159 | HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY |
0bb3cf72 | 160 | | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task }, |
1da177e4 LT |
161 | |
162 | /* LC82C168 */ | |
163 | { "Lite-On 82c168 PNIC", 256, 0x0001fbef, | |
0bb3cf72 | 164 | HAS_MII | HAS_PNICNWAY, pnic_timer, }, |
1da177e4 LT |
165 | |
166 | /* MX98713 */ | |
167 | { "Macronix 98713 PMAC", 128, 0x0001ebef, | |
0bb3cf72 | 168 | HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, }, |
1da177e4 LT |
169 | |
170 | /* MX98715 */ | |
171 | { "Macronix 98715 PMAC", 256, 0x0001ebef, | |
0bb3cf72 | 172 | HAS_MEDIA_TABLE, mxic_timer, }, |
1da177e4 LT |
173 | |
174 | /* MX98725 */ | |
175 | { "Macronix 98725 PMAC", 256, 0x0001ebef, | |
0bb3cf72 | 176 | HAS_MEDIA_TABLE, mxic_timer, }, |
1da177e4 LT |
177 | |
178 | /* AX88140 */ | |
179 | { "ASIX AX88140", 128, 0x0001fbff, | |
180 | HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY | |
0bb3cf72 | 181 | | IS_ASIX, tulip_timer, tulip_media_task }, |
1da177e4 LT |
182 | |
183 | /* PNIC2 */ | |
184 | { "Lite-On PNIC-II", 256, 0x0801fbff, | |
0bb3cf72 | 185 | HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, }, |
1da177e4 LT |
186 | |
187 | /* COMET */ | |
188 | { "ADMtek Comet", 256, 0x0001abef, | |
0bb3cf72 | 189 | HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, }, |
1da177e4 LT |
190 | |
191 | /* COMPEX9881 */ | |
192 | { "Compex 9881 PMAC", 128, 0x0001ebef, | |
0bb3cf72 | 193 | HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, }, |
1da177e4 LT |
194 | |
195 | /* I21145 */ | |
196 | { "Intel DS21145 Tulip", 128, 0x0801fbff, | |
197 | HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | |
0bb3cf72 | 198 | | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task }, |
1da177e4 LT |
199 | |
200 | /* DM910X */ | |
201 | { "Davicom DM9102/DM9102A", 128, 0x0001ebef, | |
202 | HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI, | |
0bb3cf72 | 203 | tulip_timer, tulip_media_task }, |
1da177e4 LT |
204 | |
205 | /* RS7112 */ | |
206 | { "Conexant LANfinity", 256, 0x0001ebef, | |
0bb3cf72 | 207 | HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task }, |
1da177e4 | 208 | |
1da177e4 LT |
209 | }; |
210 | ||
211 | ||
212 | static struct pci_device_id tulip_pci_tbl[] = { | |
213 | { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 }, | |
214 | { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 }, | |
215 | { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 }, | |
216 | { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 }, | |
217 | { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 }, | |
218 | /* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/ | |
219 | { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 }, | |
220 | { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 }, | |
221 | { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
222 | { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
223 | { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
224 | { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
225 | { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
226 | { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
227 | { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
228 | { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
229 | { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
230 | { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
231 | { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 }, | |
232 | { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 }, | |
233 | { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X }, | |
234 | { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X }, | |
235 | { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
236 | { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 }, | |
237 | { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
238 | { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
239 | { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
240 | { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
241 | { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT }, | |
242 | { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
243 | { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
244 | { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
245 | { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, | |
1da177e4 | 246 | { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */ |
9b25978e | 247 | { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */ |
1a449358 | 248 | { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, |
1da177e4 LT |
249 | { } /* terminate list */ |
250 | }; | |
251 | MODULE_DEVICE_TABLE(pci, tulip_pci_tbl); | |
252 | ||
253 | ||
254 | /* A full-duplex map for media types. */ | |
255 | const char tulip_media_cap[32] = | |
256 | {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, }; | |
257 | ||
258 | static void tulip_tx_timeout(struct net_device *dev); | |
259 | static void tulip_init_ring(struct net_device *dev); | |
260 | static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
261 | static int tulip_open(struct net_device *dev); | |
262 | static int tulip_close(struct net_device *dev); | |
263 | static void tulip_up(struct net_device *dev); | |
264 | static void tulip_down(struct net_device *dev); | |
265 | static struct net_device_stats *tulip_get_stats(struct net_device *dev); | |
266 | static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
267 | static void set_rx_mode(struct net_device *dev); | |
268 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
269 | static void poll_tulip(struct net_device *dev); | |
270 | #endif | |
271 | ||
272 | static void tulip_set_power_state (struct tulip_private *tp, | |
273 | int sleep, int snooze) | |
274 | { | |
275 | if (tp->flags & HAS_ACPI) { | |
276 | u32 tmp, newtmp; | |
277 | pci_read_config_dword (tp->pdev, CFDD, &tmp); | |
278 | newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze); | |
279 | if (sleep) | |
280 | newtmp |= CFDD_Sleep; | |
281 | else if (snooze) | |
282 | newtmp |= CFDD_Snooze; | |
283 | if (tmp != newtmp) | |
284 | pci_write_config_dword (tp->pdev, CFDD, newtmp); | |
285 | } | |
286 | ||
287 | } | |
288 | ||
289 | ||
290 | static void tulip_up(struct net_device *dev) | |
291 | { | |
292 | struct tulip_private *tp = netdev_priv(dev); | |
293 | void __iomem *ioaddr = tp->base_addr; | |
294 | int next_tick = 3*HZ; | |
295 | int i; | |
296 | ||
297 | /* Wake the chip from sleep/snooze mode. */ | |
298 | tulip_set_power_state (tp, 0, 0); | |
299 | ||
300 | /* On some chip revs we must set the MII/SYM port before the reset!? */ | |
301 | if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii)) | |
302 | iowrite32(0x00040000, ioaddr + CSR6); | |
303 | ||
304 | /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ | |
305 | iowrite32(0x00000001, ioaddr + CSR0); | |
40c0d879 | 306 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */ |
1da177e4 LT |
307 | udelay(100); |
308 | ||
309 | /* Deassert reset. | |
310 | Wait the specified 50 PCI cycles after a reset by initializing | |
311 | Tx and Rx queues and the address filter list. */ | |
312 | iowrite32(tp->csr0, ioaddr + CSR0); | |
40c0d879 | 313 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */ |
1da177e4 LT |
314 | udelay(100); |
315 | ||
316 | if (tulip_debug > 1) | |
317 | printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq); | |
318 | ||
319 | iowrite32(tp->rx_ring_dma, ioaddr + CSR3); | |
320 | iowrite32(tp->tx_ring_dma, ioaddr + CSR4); | |
321 | tp->cur_rx = tp->cur_tx = 0; | |
322 | tp->dirty_rx = tp->dirty_tx = 0; | |
323 | ||
324 | if (tp->flags & MC_HASH_ONLY) { | |
325 | u32 addr_low = le32_to_cpu(get_unaligned((u32 *)dev->dev_addr)); | |
326 | u32 addr_high = le16_to_cpu(get_unaligned((u16 *)(dev->dev_addr+4))); | |
327 | if (tp->chip_id == AX88140) { | |
328 | iowrite32(0, ioaddr + CSR13); | |
329 | iowrite32(addr_low, ioaddr + CSR14); | |
330 | iowrite32(1, ioaddr + CSR13); | |
331 | iowrite32(addr_high, ioaddr + CSR14); | |
332 | } else if (tp->flags & COMET_MAC_ADDR) { | |
333 | iowrite32(addr_low, ioaddr + 0xA4); | |
334 | iowrite32(addr_high, ioaddr + 0xA8); | |
335 | iowrite32(0, ioaddr + 0xAC); | |
336 | iowrite32(0, ioaddr + 0xB0); | |
337 | } | |
338 | } else { | |
339 | /* This is set_rx_mode(), but without starting the transmitter. */ | |
340 | u16 *eaddrs = (u16 *)dev->dev_addr; | |
341 | u16 *setup_frm = &tp->setup_frame[15*6]; | |
342 | dma_addr_t mapping; | |
343 | ||
344 | /* 21140 bug: you must add the broadcast address. */ | |
345 | memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame)); | |
346 | /* Fill the final entry of the table with our physical address. */ | |
347 | *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0]; | |
348 | *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1]; | |
349 | *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2]; | |
350 | ||
351 | mapping = pci_map_single(tp->pdev, tp->setup_frame, | |
352 | sizeof(tp->setup_frame), | |
353 | PCI_DMA_TODEVICE); | |
354 | tp->tx_buffers[tp->cur_tx].skb = NULL; | |
355 | tp->tx_buffers[tp->cur_tx].mapping = mapping; | |
356 | ||
357 | /* Put the setup frame on the Tx list. */ | |
358 | tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192); | |
359 | tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping); | |
360 | tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned); | |
361 | ||
362 | tp->cur_tx++; | |
363 | } | |
364 | ||
365 | tp->saved_if_port = dev->if_port; | |
366 | if (dev->if_port == 0) | |
367 | dev->if_port = tp->default_port; | |
368 | ||
369 | /* Allow selecting a default media. */ | |
370 | i = 0; | |
371 | if (tp->mtable == NULL) | |
372 | goto media_picked; | |
373 | if (dev->if_port) { | |
374 | int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 : | |
375 | (dev->if_port == 12 ? 0 : dev->if_port); | |
376 | for (i = 0; i < tp->mtable->leafcount; i++) | |
377 | if (tp->mtable->mleaf[i].media == looking_for) { | |
378 | printk(KERN_INFO "%s: Using user-specified media %s.\n", | |
379 | dev->name, medianame[dev->if_port]); | |
380 | goto media_picked; | |
381 | } | |
382 | } | |
383 | if ((tp->mtable->defaultmedia & 0x0800) == 0) { | |
384 | int looking_for = tp->mtable->defaultmedia & MEDIA_MASK; | |
385 | for (i = 0; i < tp->mtable->leafcount; i++) | |
386 | if (tp->mtable->mleaf[i].media == looking_for) { | |
387 | printk(KERN_INFO "%s: Using EEPROM-set media %s.\n", | |
388 | dev->name, medianame[looking_for]); | |
389 | goto media_picked; | |
390 | } | |
391 | } | |
392 | /* Start sensing first non-full-duplex media. */ | |
393 | for (i = tp->mtable->leafcount - 1; | |
394 | (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--) | |
395 | ; | |
396 | media_picked: | |
397 | ||
398 | tp->csr6 = 0; | |
399 | tp->cur_index = i; | |
400 | tp->nwayset = 0; | |
401 | ||
402 | if (dev->if_port) { | |
403 | if (tp->chip_id == DC21143 && | |
404 | (tulip_media_cap[dev->if_port] & MediaIsMII)) { | |
405 | /* We must reset the media CSRs when we force-select MII mode. */ | |
406 | iowrite32(0x0000, ioaddr + CSR13); | |
407 | iowrite32(0x0000, ioaddr + CSR14); | |
408 | iowrite32(0x0008, ioaddr + CSR15); | |
409 | } | |
410 | tulip_select_media(dev, 1); | |
411 | } else if (tp->chip_id == DC21142) { | |
412 | if (tp->mii_cnt) { | |
413 | tulip_select_media(dev, 1); | |
414 | if (tulip_debug > 1) | |
415 | printk(KERN_INFO "%s: Using MII transceiver %d, status " | |
416 | "%4.4x.\n", | |
417 | dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1)); | |
418 | iowrite32(csr6_mask_defstate, ioaddr + CSR6); | |
419 | tp->csr6 = csr6_mask_hdcap; | |
420 | dev->if_port = 11; | |
421 | iowrite32(0x0000, ioaddr + CSR13); | |
422 | iowrite32(0x0000, ioaddr + CSR14); | |
423 | } else | |
424 | t21142_start_nway(dev); | |
425 | } else if (tp->chip_id == PNIC2) { | |
426 | /* for initial startup advertise 10/100 Full and Half */ | |
427 | tp->sym_advertise = 0x01E0; | |
428 | /* enable autonegotiate end interrupt */ | |
429 | iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5); | |
430 | iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7); | |
431 | pnic2_start_nway(dev); | |
432 | } else if (tp->chip_id == LC82C168 && ! tp->medialock) { | |
433 | if (tp->mii_cnt) { | |
434 | dev->if_port = 11; | |
435 | tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0); | |
436 | iowrite32(0x0001, ioaddr + CSR15); | |
437 | } else if (ioread32(ioaddr + CSR5) & TPLnkPass) | |
438 | pnic_do_nway(dev); | |
439 | else { | |
440 | /* Start with 10mbps to do autonegotiation. */ | |
441 | iowrite32(0x32, ioaddr + CSR12); | |
442 | tp->csr6 = 0x00420000; | |
443 | iowrite32(0x0001B078, ioaddr + 0xB8); | |
444 | iowrite32(0x0201B078, ioaddr + 0xB8); | |
445 | next_tick = 1*HZ; | |
446 | } | |
447 | } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881) | |
448 | && ! tp->medialock) { | |
449 | dev->if_port = 0; | |
450 | tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0); | |
451 | iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80); | |
452 | } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) { | |
453 | /* Provided by BOLO, Macronix - 12/10/1998. */ | |
454 | dev->if_port = 0; | |
455 | tp->csr6 = 0x01a80200; | |
456 | iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80); | |
457 | iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0); | |
458 | } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) { | |
459 | /* Enable automatic Tx underrun recovery. */ | |
460 | iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88); | |
461 | dev->if_port = tp->mii_cnt ? 11 : 0; | |
462 | tp->csr6 = 0x00040000; | |
463 | } else if (tp->chip_id == AX88140) { | |
464 | tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100; | |
465 | } else | |
466 | tulip_select_media(dev, 1); | |
467 | ||
468 | /* Start the chip's Tx to process setup frame. */ | |
469 | tulip_stop_rxtx(tp); | |
470 | barrier(); | |
471 | udelay(5); | |
472 | iowrite32(tp->csr6 | TxOn, ioaddr + CSR6); | |
473 | ||
474 | /* Enable interrupts by setting the interrupt mask. */ | |
475 | iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5); | |
476 | iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7); | |
477 | tulip_start_rxtx(tp); | |
478 | iowrite32(0, ioaddr + CSR2); /* Rx poll demand */ | |
479 | ||
480 | if (tulip_debug > 2) { | |
481 | printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n", | |
482 | dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5), | |
483 | ioread32(ioaddr + CSR6)); | |
484 | } | |
485 | ||
486 | /* Set the timer to switch to check for link beat and perhaps switch | |
487 | to an alternate media type. */ | |
488 | tp->timer.expires = RUN_AT(next_tick); | |
489 | add_timer(&tp->timer); | |
490 | #ifdef CONFIG_TULIP_NAPI | |
491 | init_timer(&tp->oom_timer); | |
492 | tp->oom_timer.data = (unsigned long)dev; | |
493 | tp->oom_timer.function = oom_timer; | |
494 | #endif | |
495 | } | |
496 | ||
497 | static int | |
498 | tulip_open(struct net_device *dev) | |
499 | { | |
500 | int retval; | |
501 | ||
1fb9df5d | 502 | if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) |
1da177e4 LT |
503 | return retval; |
504 | ||
505 | tulip_init_ring (dev); | |
506 | ||
507 | tulip_up (dev); | |
508 | ||
509 | netif_start_queue (dev); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
514 | ||
515 | static void tulip_tx_timeout(struct net_device *dev) | |
516 | { | |
517 | struct tulip_private *tp = netdev_priv(dev); | |
518 | void __iomem *ioaddr = tp->base_addr; | |
519 | unsigned long flags; | |
520 | ||
521 | spin_lock_irqsave (&tp->lock, flags); | |
522 | ||
523 | if (tulip_media_cap[dev->if_port] & MediaIsMII) { | |
524 | /* Do nothing -- the media monitor should handle this. */ | |
525 | if (tulip_debug > 1) | |
526 | printk(KERN_WARNING "%s: Transmit timeout using MII device.\n", | |
527 | dev->name); | |
528 | } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142 | |
529 | || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881 | |
ea8f400c | 530 | || tp->chip_id == DM910X) { |
1da177e4 LT |
531 | printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, " |
532 | "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n", | |
533 | dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12), | |
534 | ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15)); | |
0bb3cf72 FR |
535 | tp->timeout_recovery = 1; |
536 | schedule_work(&tp->media_work); | |
537 | goto out_unlock; | |
1da177e4 LT |
538 | } else if (tp->chip_id == PNIC2) { |
539 | printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, " | |
540 | "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n", | |
541 | dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6), | |
542 | (int)ioread32(ioaddr + CSR7), (int)ioread32(ioaddr + CSR12)); | |
543 | } else { | |
544 | printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 " | |
545 | "%8.8x, resetting...\n", | |
546 | dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12)); | |
547 | dev->if_port = 0; | |
548 | } | |
549 | ||
550 | #if defined(way_too_many_messages) | |
551 | if (tulip_debug > 3) { | |
552 | int i; | |
553 | for (i = 0; i < RX_RING_SIZE; i++) { | |
554 | u8 *buf = (u8 *)(tp->rx_ring[i].buffer1); | |
555 | int j; | |
556 | printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x " | |
557 | "%2.2x %2.2x %2.2x.\n", | |
558 | i, (unsigned int)tp->rx_ring[i].status, | |
559 | (unsigned int)tp->rx_ring[i].length, | |
560 | (unsigned int)tp->rx_ring[i].buffer1, | |
561 | (unsigned int)tp->rx_ring[i].buffer2, | |
562 | buf[0], buf[1], buf[2]); | |
563 | for (j = 0; buf[j] != 0xee && j < 1600; j++) | |
564 | if (j < 100) printk(" %2.2x", buf[j]); | |
565 | printk(" j=%d.\n", j); | |
566 | } | |
567 | printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring); | |
568 | for (i = 0; i < RX_RING_SIZE; i++) | |
569 | printk(" %8.8x", (unsigned int)tp->rx_ring[i].status); | |
570 | printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring); | |
571 | for (i = 0; i < TX_RING_SIZE; i++) | |
572 | printk(" %8.8x", (unsigned int)tp->tx_ring[i].status); | |
573 | printk("\n"); | |
574 | } | |
575 | #endif | |
576 | ||
0bb3cf72 | 577 | tulip_tx_timeout_complete(tp, ioaddr); |
1da177e4 | 578 | |
0bb3cf72 | 579 | out_unlock: |
1da177e4 LT |
580 | spin_unlock_irqrestore (&tp->lock, flags); |
581 | dev->trans_start = jiffies; | |
582 | netif_wake_queue (dev); | |
583 | } | |
584 | ||
585 | ||
586 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
587 | static void tulip_init_ring(struct net_device *dev) | |
588 | { | |
589 | struct tulip_private *tp = netdev_priv(dev); | |
590 | int i; | |
591 | ||
592 | tp->susp_rx = 0; | |
593 | tp->ttimer = 0; | |
594 | tp->nir = 0; | |
595 | ||
596 | for (i = 0; i < RX_RING_SIZE; i++) { | |
597 | tp->rx_ring[i].status = 0x00000000; | |
598 | tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ); | |
599 | tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1)); | |
600 | tp->rx_buffers[i].skb = NULL; | |
601 | tp->rx_buffers[i].mapping = 0; | |
602 | } | |
603 | /* Mark the last entry as wrapping the ring. */ | |
604 | tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP); | |
605 | tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma); | |
606 | ||
607 | for (i = 0; i < RX_RING_SIZE; i++) { | |
608 | dma_addr_t mapping; | |
609 | ||
610 | /* Note the receive buffer must be longword aligned. | |
611 | dev_alloc_skb() provides 16 byte alignment. But do *not* | |
612 | use skb_reserve() to align the IP header! */ | |
613 | struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ); | |
614 | tp->rx_buffers[i].skb = skb; | |
615 | if (skb == NULL) | |
616 | break; | |
689be439 | 617 | mapping = pci_map_single(tp->pdev, skb->data, |
1da177e4 LT |
618 | PKT_BUF_SZ, PCI_DMA_FROMDEVICE); |
619 | tp->rx_buffers[i].mapping = mapping; | |
620 | skb->dev = dev; /* Mark as being used by this device. */ | |
621 | tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */ | |
622 | tp->rx_ring[i].buffer1 = cpu_to_le32(mapping); | |
623 | } | |
624 | tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
625 | ||
626 | /* The Tx buffer descriptor is filled in as needed, but we | |
627 | do need to clear the ownership bit. */ | |
628 | for (i = 0; i < TX_RING_SIZE; i++) { | |
629 | tp->tx_buffers[i].skb = NULL; | |
630 | tp->tx_buffers[i].mapping = 0; | |
631 | tp->tx_ring[i].status = 0x00000000; | |
632 | tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1)); | |
633 | } | |
634 | tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma); | |
635 | } | |
636 | ||
637 | static int | |
638 | tulip_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
639 | { | |
640 | struct tulip_private *tp = netdev_priv(dev); | |
641 | int entry; | |
642 | u32 flag; | |
643 | dma_addr_t mapping; | |
644 | ||
645 | spin_lock_irq(&tp->lock); | |
646 | ||
647 | /* Calculate the next Tx descriptor entry. */ | |
648 | entry = tp->cur_tx % TX_RING_SIZE; | |
649 | ||
650 | tp->tx_buffers[entry].skb = skb; | |
651 | mapping = pci_map_single(tp->pdev, skb->data, | |
652 | skb->len, PCI_DMA_TODEVICE); | |
653 | tp->tx_buffers[entry].mapping = mapping; | |
654 | tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping); | |
655 | ||
656 | if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */ | |
657 | flag = 0x60000000; /* No interrupt */ | |
658 | } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) { | |
659 | flag = 0xe0000000; /* Tx-done intr. */ | |
660 | } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) { | |
661 | flag = 0x60000000; /* No Tx-done intr. */ | |
662 | } else { /* Leave room for set_rx_mode() to fill entries. */ | |
663 | flag = 0xe0000000; /* Tx-done intr. */ | |
664 | netif_stop_queue(dev); | |
665 | } | |
666 | if (entry == TX_RING_SIZE-1) | |
667 | flag = 0xe0000000 | DESC_RING_WRAP; | |
668 | ||
669 | tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag); | |
670 | /* if we were using Transmit Automatic Polling, we would need a | |
671 | * wmb() here. */ | |
672 | tp->tx_ring[entry].status = cpu_to_le32(DescOwned); | |
673 | wmb(); | |
674 | ||
675 | tp->cur_tx++; | |
676 | ||
677 | /* Trigger an immediate transmit demand. */ | |
678 | iowrite32(0, tp->base_addr + CSR1); | |
679 | ||
680 | spin_unlock_irq(&tp->lock); | |
681 | ||
682 | dev->trans_start = jiffies; | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
687 | static void tulip_clean_tx_ring(struct tulip_private *tp) | |
688 | { | |
689 | unsigned int dirty_tx; | |
690 | ||
691 | for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0; | |
692 | dirty_tx++) { | |
693 | int entry = dirty_tx % TX_RING_SIZE; | |
694 | int status = le32_to_cpu(tp->tx_ring[entry].status); | |
695 | ||
696 | if (status < 0) { | |
697 | tp->stats.tx_errors++; /* It wasn't Txed */ | |
698 | tp->tx_ring[entry].status = 0; | |
699 | } | |
700 | ||
701 | /* Check for Tx filter setup frames. */ | |
702 | if (tp->tx_buffers[entry].skb == NULL) { | |
703 | /* test because dummy frames not mapped */ | |
704 | if (tp->tx_buffers[entry].mapping) | |
705 | pci_unmap_single(tp->pdev, | |
706 | tp->tx_buffers[entry].mapping, | |
707 | sizeof(tp->setup_frame), | |
708 | PCI_DMA_TODEVICE); | |
709 | continue; | |
710 | } | |
711 | ||
712 | pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping, | |
713 | tp->tx_buffers[entry].skb->len, | |
714 | PCI_DMA_TODEVICE); | |
715 | ||
716 | /* Free the original skb. */ | |
717 | dev_kfree_skb_irq(tp->tx_buffers[entry].skb); | |
718 | tp->tx_buffers[entry].skb = NULL; | |
719 | tp->tx_buffers[entry].mapping = 0; | |
720 | } | |
721 | } | |
722 | ||
723 | static void tulip_down (struct net_device *dev) | |
724 | { | |
725 | struct tulip_private *tp = netdev_priv(dev); | |
726 | void __iomem *ioaddr = tp->base_addr; | |
727 | unsigned long flags; | |
728 | ||
0bb3cf72 FR |
729 | flush_scheduled_work(); |
730 | ||
1da177e4 LT |
731 | del_timer_sync (&tp->timer); |
732 | #ifdef CONFIG_TULIP_NAPI | |
733 | del_timer_sync (&tp->oom_timer); | |
734 | #endif | |
735 | spin_lock_irqsave (&tp->lock, flags); | |
736 | ||
737 | /* Disable interrupts by clearing the interrupt mask. */ | |
738 | iowrite32 (0x00000000, ioaddr + CSR7); | |
739 | ||
740 | /* Stop the Tx and Rx processes. */ | |
741 | tulip_stop_rxtx(tp); | |
742 | ||
743 | /* prepare receive buffers */ | |
744 | tulip_refill_rx(dev); | |
745 | ||
746 | /* release any unconsumed transmit buffers */ | |
747 | tulip_clean_tx_ring(tp); | |
748 | ||
749 | if (ioread32 (ioaddr + CSR6) != 0xffffffff) | |
750 | tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff; | |
751 | ||
752 | spin_unlock_irqrestore (&tp->lock, flags); | |
753 | ||
754 | init_timer(&tp->timer); | |
755 | tp->timer.data = (unsigned long)dev; | |
756 | tp->timer.function = tulip_tbl[tp->chip_id].media_timer; | |
757 | ||
758 | dev->if_port = tp->saved_if_port; | |
759 | ||
760 | /* Leave the driver in snooze, not sleep, mode. */ | |
761 | tulip_set_power_state (tp, 0, 1); | |
762 | } | |
763 | ||
764 | ||
765 | static int tulip_close (struct net_device *dev) | |
766 | { | |
767 | struct tulip_private *tp = netdev_priv(dev); | |
768 | void __iomem *ioaddr = tp->base_addr; | |
769 | int i; | |
770 | ||
771 | netif_stop_queue (dev); | |
772 | ||
773 | tulip_down (dev); | |
774 | ||
775 | if (tulip_debug > 1) | |
776 | printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n", | |
777 | dev->name, ioread32 (ioaddr + CSR5)); | |
778 | ||
779 | free_irq (dev->irq, dev); | |
780 | ||
781 | /* Free all the skbuffs in the Rx queue. */ | |
782 | for (i = 0; i < RX_RING_SIZE; i++) { | |
783 | struct sk_buff *skb = tp->rx_buffers[i].skb; | |
784 | dma_addr_t mapping = tp->rx_buffers[i].mapping; | |
785 | ||
786 | tp->rx_buffers[i].skb = NULL; | |
787 | tp->rx_buffers[i].mapping = 0; | |
788 | ||
789 | tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */ | |
790 | tp->rx_ring[i].length = 0; | |
791 | tp->rx_ring[i].buffer1 = 0xBADF00D0; /* An invalid address. */ | |
792 | if (skb) { | |
793 | pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ, | |
794 | PCI_DMA_FROMDEVICE); | |
795 | dev_kfree_skb (skb); | |
796 | } | |
797 | } | |
798 | for (i = 0; i < TX_RING_SIZE; i++) { | |
799 | struct sk_buff *skb = tp->tx_buffers[i].skb; | |
800 | ||
801 | if (skb != NULL) { | |
802 | pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping, | |
803 | skb->len, PCI_DMA_TODEVICE); | |
804 | dev_kfree_skb (skb); | |
805 | } | |
806 | tp->tx_buffers[i].skb = NULL; | |
807 | tp->tx_buffers[i].mapping = 0; | |
808 | } | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | static struct net_device_stats *tulip_get_stats(struct net_device *dev) | |
814 | { | |
815 | struct tulip_private *tp = netdev_priv(dev); | |
816 | void __iomem *ioaddr = tp->base_addr; | |
817 | ||
818 | if (netif_running(dev)) { | |
819 | unsigned long flags; | |
820 | ||
821 | spin_lock_irqsave (&tp->lock, flags); | |
822 | ||
823 | tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff; | |
824 | ||
825 | spin_unlock_irqrestore(&tp->lock, flags); | |
826 | } | |
827 | ||
828 | return &tp->stats; | |
829 | } | |
830 | ||
831 | ||
832 | static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
833 | { | |
834 | struct tulip_private *np = netdev_priv(dev); | |
835 | strcpy(info->driver, DRV_NAME); | |
836 | strcpy(info->version, DRV_VERSION); | |
837 | strcpy(info->bus_info, pci_name(np->pdev)); | |
838 | } | |
839 | ||
7282d491 | 840 | static const struct ethtool_ops ops = { |
1da177e4 LT |
841 | .get_drvinfo = tulip_get_drvinfo |
842 | }; | |
843 | ||
844 | /* Provide ioctl() calls to examine the MII xcvr state. */ | |
845 | static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) | |
846 | { | |
847 | struct tulip_private *tp = netdev_priv(dev); | |
848 | void __iomem *ioaddr = tp->base_addr; | |
849 | struct mii_ioctl_data *data = if_mii(rq); | |
850 | const unsigned int phy_idx = 0; | |
851 | int phy = tp->phys[phy_idx] & 0x1f; | |
852 | unsigned int regnum = data->reg_num; | |
853 | ||
854 | switch (cmd) { | |
855 | case SIOCGMIIPHY: /* Get address of MII PHY in use. */ | |
856 | if (tp->mii_cnt) | |
857 | data->phy_id = phy; | |
858 | else if (tp->flags & HAS_NWAY) | |
859 | data->phy_id = 32; | |
860 | else if (tp->chip_id == COMET) | |
861 | data->phy_id = 1; | |
862 | else | |
863 | return -ENODEV; | |
864 | ||
865 | case SIOCGMIIREG: /* Read MII PHY register. */ | |
866 | if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) { | |
867 | int csr12 = ioread32 (ioaddr + CSR12); | |
868 | int csr14 = ioread32 (ioaddr + CSR14); | |
869 | switch (regnum) { | |
870 | case 0: | |
871 | if (((csr14<<5) & 0x1000) || | |
872 | (dev->if_port == 5 && tp->nwayset)) | |
873 | data->val_out = 0x1000; | |
874 | else | |
875 | data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0) | |
876 | | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0); | |
877 | break; | |
878 | case 1: | |
879 | data->val_out = | |
880 | 0x1848 + | |
881 | ((csr12&0x7000) == 0x5000 ? 0x20 : 0) + | |
882 | ((csr12&0x06) == 6 ? 0 : 4); | |
883 | data->val_out |= 0x6048; | |
884 | break; | |
885 | case 4: | |
886 | /* Advertised value, bogus 10baseTx-FD value from CSR6. */ | |
887 | data->val_out = | |
888 | ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) + | |
889 | ((csr14 >> 1) & 0x20) + 1; | |
890 | data->val_out |= ((csr14 >> 9) & 0x03C0); | |
891 | break; | |
892 | case 5: data->val_out = tp->lpar; break; | |
893 | default: data->val_out = 0; break; | |
894 | } | |
895 | } else { | |
896 | data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum); | |
897 | } | |
898 | return 0; | |
899 | ||
900 | case SIOCSMIIREG: /* Write MII PHY register. */ | |
901 | if (!capable (CAP_NET_ADMIN)) | |
902 | return -EPERM; | |
903 | if (regnum & ~0x1f) | |
904 | return -EINVAL; | |
905 | if (data->phy_id == phy) { | |
906 | u16 value = data->val_in; | |
907 | switch (regnum) { | |
908 | case 0: /* Check for autonegotiation on or reset. */ | |
909 | tp->full_duplex_lock = (value & 0x9000) ? 0 : 1; | |
910 | if (tp->full_duplex_lock) | |
911 | tp->full_duplex = (value & 0x0100) ? 1 : 0; | |
912 | break; | |
913 | case 4: | |
914 | tp->advertising[phy_idx] = | |
915 | tp->mii_advertise = data->val_in; | |
916 | break; | |
917 | } | |
918 | } | |
919 | if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) { | |
920 | u16 value = data->val_in; | |
921 | if (regnum == 0) { | |
922 | if ((value & 0x1200) == 0x1200) { | |
923 | if (tp->chip_id == PNIC2) { | |
924 | pnic2_start_nway (dev); | |
925 | } else { | |
926 | t21142_start_nway (dev); | |
927 | } | |
928 | } | |
929 | } else if (regnum == 4) | |
930 | tp->sym_advertise = value; | |
931 | } else { | |
932 | tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in); | |
933 | } | |
934 | return 0; | |
935 | default: | |
936 | return -EOPNOTSUPP; | |
937 | } | |
938 | ||
939 | return -EOPNOTSUPP; | |
940 | } | |
941 | ||
942 | ||
943 | /* Set or clear the multicast filter for this adaptor. | |
944 | Note that we only use exclusion around actually queueing the | |
945 | new frame, not around filling tp->setup_frame. This is non-deterministic | |
946 | when re-entered but still correct. */ | |
947 | ||
948 | #undef set_bit_le | |
949 | #define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0) | |
950 | ||
951 | static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev) | |
952 | { | |
953 | struct tulip_private *tp = netdev_priv(dev); | |
954 | u16 hash_table[32]; | |
955 | struct dev_mc_list *mclist; | |
956 | int i; | |
957 | u16 *eaddrs; | |
958 | ||
959 | memset(hash_table, 0, sizeof(hash_table)); | |
960 | set_bit_le(255, hash_table); /* Broadcast entry */ | |
961 | /* This should work on big-endian machines as well. */ | |
962 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
963 | i++, mclist = mclist->next) { | |
964 | int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff; | |
965 | ||
966 | set_bit_le(index, hash_table); | |
967 | ||
968 | } | |
969 | for (i = 0; i < 32; i++) { | |
970 | *setup_frm++ = hash_table[i]; | |
971 | *setup_frm++ = hash_table[i]; | |
972 | } | |
973 | setup_frm = &tp->setup_frame[13*6]; | |
974 | ||
975 | /* Fill the final entry with our physical address. */ | |
976 | eaddrs = (u16 *)dev->dev_addr; | |
977 | *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0]; | |
978 | *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1]; | |
979 | *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2]; | |
980 | } | |
981 | ||
982 | static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev) | |
983 | { | |
984 | struct tulip_private *tp = netdev_priv(dev); | |
985 | struct dev_mc_list *mclist; | |
986 | int i; | |
987 | u16 *eaddrs; | |
988 | ||
989 | /* We have <= 14 addresses so we can use the wonderful | |
990 | 16 address perfect filtering of the Tulip. */ | |
991 | for (i = 0, mclist = dev->mc_list; i < dev->mc_count; | |
992 | i++, mclist = mclist->next) { | |
993 | eaddrs = (u16 *)mclist->dmi_addr; | |
994 | *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++; | |
995 | *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++; | |
996 | *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++; | |
997 | } | |
998 | /* Fill the unused entries with the broadcast address. */ | |
999 | memset(setup_frm, 0xff, (15-i)*12); | |
1000 | setup_frm = &tp->setup_frame[15*6]; | |
1001 | ||
1002 | /* Fill the final entry with our physical address. */ | |
1003 | eaddrs = (u16 *)dev->dev_addr; | |
1004 | *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0]; | |
1005 | *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1]; | |
1006 | *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2]; | |
1007 | } | |
1008 | ||
1009 | ||
1010 | static void set_rx_mode(struct net_device *dev) | |
1011 | { | |
1012 | struct tulip_private *tp = netdev_priv(dev); | |
1013 | void __iomem *ioaddr = tp->base_addr; | |
1014 | int csr6; | |
1015 | ||
1016 | csr6 = ioread32(ioaddr + CSR6) & ~0x00D5; | |
1017 | ||
1018 | tp->csr6 &= ~0x00D5; | |
1019 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1020 | tp->csr6 |= AcceptAllMulticast | AcceptAllPhys; | |
1021 | csr6 |= AcceptAllMulticast | AcceptAllPhys; | |
1da177e4 LT |
1022 | } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) { |
1023 | /* Too many to filter well -- accept all multicasts. */ | |
1024 | tp->csr6 |= AcceptAllMulticast; | |
1025 | csr6 |= AcceptAllMulticast; | |
1026 | } else if (tp->flags & MC_HASH_ONLY) { | |
1027 | /* Some work-alikes have only a 64-entry hash filter table. */ | |
1028 | /* Should verify correctness on big-endian/__powerpc__ */ | |
1029 | struct dev_mc_list *mclist; | |
1030 | int i; | |
1031 | if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */ | |
1032 | tp->csr6 |= AcceptAllMulticast; | |
1033 | csr6 |= AcceptAllMulticast; | |
1034 | } else { | |
1035 | u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */ | |
1036 | int filterbit; | |
1037 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1038 | i++, mclist = mclist->next) { | |
1039 | if (tp->flags & COMET_MAC_ADDR) | |
1040 | filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr); | |
1041 | else | |
1042 | filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; | |
1043 | filterbit &= 0x3f; | |
1044 | mc_filter[filterbit >> 5] |= 1 << (filterbit & 31); | |
1045 | if (tulip_debug > 2) { | |
1046 | printk(KERN_INFO "%s: Added filter for %2.2x:%2.2x:%2.2x:" | |
1047 | "%2.2x:%2.2x:%2.2x %8.8x bit %d.\n", dev->name, | |
1048 | mclist->dmi_addr[0], mclist->dmi_addr[1], | |
1049 | mclist->dmi_addr[2], mclist->dmi_addr[3], | |
1050 | mclist->dmi_addr[4], mclist->dmi_addr[5], | |
1051 | ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit); | |
1052 | } | |
1053 | } | |
1054 | if (mc_filter[0] == tp->mc_filter[0] && | |
1055 | mc_filter[1] == tp->mc_filter[1]) | |
1056 | ; /* No change. */ | |
1057 | else if (tp->flags & IS_ASIX) { | |
1058 | iowrite32(2, ioaddr + CSR13); | |
1059 | iowrite32(mc_filter[0], ioaddr + CSR14); | |
1060 | iowrite32(3, ioaddr + CSR13); | |
1061 | iowrite32(mc_filter[1], ioaddr + CSR14); | |
1062 | } else if (tp->flags & COMET_MAC_ADDR) { | |
1063 | iowrite32(mc_filter[0], ioaddr + 0xAC); | |
1064 | iowrite32(mc_filter[1], ioaddr + 0xB0); | |
1065 | } | |
1066 | tp->mc_filter[0] = mc_filter[0]; | |
1067 | tp->mc_filter[1] = mc_filter[1]; | |
1068 | } | |
1069 | } else { | |
1070 | unsigned long flags; | |
1071 | u32 tx_flags = 0x08000000 | 192; | |
1072 | ||
1073 | /* Note that only the low-address shortword of setup_frame is valid! | |
1074 | The values are doubled for big-endian architectures. */ | |
1075 | if (dev->mc_count > 14) { /* Must use a multicast hash table. */ | |
1076 | build_setup_frame_hash(tp->setup_frame, dev); | |
1077 | tx_flags = 0x08400000 | 192; | |
1078 | } else { | |
1079 | build_setup_frame_perfect(tp->setup_frame, dev); | |
1080 | } | |
1081 | ||
1082 | spin_lock_irqsave(&tp->lock, flags); | |
1083 | ||
1084 | if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) { | |
1085 | /* Same setup recently queued, we need not add it. */ | |
1086 | } else { | |
1087 | unsigned int entry; | |
1088 | int dummy = -1; | |
1089 | ||
1090 | /* Now add this frame to the Tx list. */ | |
1091 | ||
1092 | entry = tp->cur_tx++ % TX_RING_SIZE; | |
1093 | ||
1094 | if (entry != 0) { | |
ea8f400c PC |
1095 | /* Avoid a chip errata by prefixing a dummy entry. */ |
1096 | tp->tx_buffers[entry].skb = NULL; | |
1097 | tp->tx_buffers[entry].mapping = 0; | |
1098 | tp->tx_ring[entry].length = | |
1099 | (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0; | |
1100 | tp->tx_ring[entry].buffer1 = 0; | |
1101 | /* Must set DescOwned later to avoid race with chip */ | |
1102 | dummy = entry; | |
1103 | entry = tp->cur_tx++ % TX_RING_SIZE; | |
1104 | ||
1da177e4 LT |
1105 | } |
1106 | ||
1107 | tp->tx_buffers[entry].skb = NULL; | |
1108 | tp->tx_buffers[entry].mapping = | |
1109 | pci_map_single(tp->pdev, tp->setup_frame, | |
1110 | sizeof(tp->setup_frame), | |
1111 | PCI_DMA_TODEVICE); | |
1112 | /* Put the setup frame on the Tx list. */ | |
1113 | if (entry == TX_RING_SIZE-1) | |
1114 | tx_flags |= DESC_RING_WRAP; /* Wrap ring. */ | |
1115 | tp->tx_ring[entry].length = cpu_to_le32(tx_flags); | |
1116 | tp->tx_ring[entry].buffer1 = | |
1117 | cpu_to_le32(tp->tx_buffers[entry].mapping); | |
1118 | tp->tx_ring[entry].status = cpu_to_le32(DescOwned); | |
1119 | if (dummy >= 0) | |
1120 | tp->tx_ring[dummy].status = cpu_to_le32(DescOwned); | |
1121 | if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2) | |
1122 | netif_stop_queue(dev); | |
1123 | ||
1124 | /* Trigger an immediate transmit demand. */ | |
1125 | iowrite32(0, ioaddr + CSR1); | |
1126 | } | |
1127 | ||
1128 | spin_unlock_irqrestore(&tp->lock, flags); | |
1129 | } | |
1130 | ||
1131 | iowrite32(csr6, ioaddr + CSR6); | |
1132 | } | |
1133 | ||
1134 | #ifdef CONFIG_TULIP_MWI | |
1135 | static void __devinit tulip_mwi_config (struct pci_dev *pdev, | |
1136 | struct net_device *dev) | |
1137 | { | |
1138 | struct tulip_private *tp = netdev_priv(dev); | |
1139 | u8 cache; | |
1140 | u16 pci_command; | |
1141 | u32 csr0; | |
1142 | ||
1143 | if (tulip_debug > 3) | |
1144 | printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev)); | |
1145 | ||
1146 | tp->csr0 = csr0 = 0; | |
1147 | ||
1148 | /* if we have any cache line size at all, we can do MRM */ | |
1149 | csr0 |= MRM; | |
1150 | ||
1151 | /* ...and barring hardware bugs, MWI */ | |
1152 | if (!(tp->chip_id == DC21143 && tp->revision == 65)) | |
1153 | csr0 |= MWI; | |
1154 | ||
1155 | /* set or disable MWI in the standard PCI command bit. | |
1156 | * Check for the case where mwi is desired but not available | |
1157 | */ | |
1158 | if (csr0 & MWI) pci_set_mwi(pdev); | |
1159 | else pci_clear_mwi(pdev); | |
1160 | ||
1161 | /* read result from hardware (in case bit refused to enable) */ | |
1162 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1163 | if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE))) | |
1164 | csr0 &= ~MWI; | |
1165 | ||
1166 | /* if cache line size hardwired to zero, no MWI */ | |
1167 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache); | |
1168 | if ((csr0 & MWI) && (cache == 0)) { | |
1169 | csr0 &= ~MWI; | |
1170 | pci_clear_mwi(pdev); | |
1171 | } | |
1172 | ||
1173 | /* assign per-cacheline-size cache alignment and | |
1174 | * burst length values | |
1175 | */ | |
1176 | switch (cache) { | |
1177 | case 8: | |
1178 | csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift); | |
1179 | break; | |
1180 | case 16: | |
1181 | csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift); | |
1182 | break; | |
1183 | case 32: | |
1184 | csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift); | |
1185 | break; | |
1186 | default: | |
1187 | cache = 0; | |
1188 | break; | |
1189 | } | |
1190 | ||
1191 | /* if we have a good cache line size, we by now have a good | |
1192 | * csr0, so save it and exit | |
1193 | */ | |
1194 | if (cache) | |
1195 | goto out; | |
1196 | ||
1197 | /* we don't have a good csr0 or cache line size, disable MWI */ | |
1198 | if (csr0 & MWI) { | |
1199 | pci_clear_mwi(pdev); | |
1200 | csr0 &= ~MWI; | |
1201 | } | |
1202 | ||
1203 | /* sane defaults for burst length and cache alignment | |
1204 | * originally from de4x5 driver | |
1205 | */ | |
1206 | csr0 |= (8 << BurstLenShift) | (1 << CALShift); | |
1207 | ||
1208 | out: | |
1209 | tp->csr0 = csr0; | |
1210 | if (tulip_debug > 2) | |
1211 | printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n", | |
1212 | pci_name(pdev), cache, csr0); | |
1213 | } | |
1214 | #endif | |
1215 | ||
1216 | /* | |
1217 | * Chips that have the MRM/reserved bit quirk and the burst quirk. That | |
1218 | * is the DM910X and the on chip ULi devices | |
1219 | */ | |
f3b197ac | 1220 | |
1da177e4 LT |
1221 | static int tulip_uli_dm_quirk(struct pci_dev *pdev) |
1222 | { | |
1223 | if (pdev->vendor == 0x1282 && pdev->device == 0x9102) | |
1224 | return 1; | |
1da177e4 LT |
1225 | return 0; |
1226 | } | |
1227 | ||
1228 | static int __devinit tulip_init_one (struct pci_dev *pdev, | |
1229 | const struct pci_device_id *ent) | |
1230 | { | |
1231 | struct tulip_private *tp; | |
1232 | /* See note below on the multiport cards. */ | |
1233 | static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'}; | |
1234 | static struct pci_device_id early_486_chipsets[] = { | |
1235 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) }, | |
1236 | { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) }, | |
1237 | { }, | |
1238 | }; | |
1239 | static int last_irq; | |
1240 | static int multiport_cnt; /* For four-port boards w/one EEPROM */ | |
1241 | u8 chip_rev; | |
1242 | int i, irq; | |
1243 | unsigned short sum; | |
1244 | unsigned char *ee_data; | |
1245 | struct net_device *dev; | |
1246 | void __iomem *ioaddr; | |
1247 | static int board_idx = -1; | |
1248 | int chip_idx = ent->driver_data; | |
1249 | const char *chip_name = tulip_tbl[chip_idx].chip_name; | |
1250 | unsigned int eeprom_missing = 0; | |
1251 | unsigned int force_csr0 = 0; | |
1252 | ||
1253 | #ifndef MODULE | |
1254 | static int did_version; /* Already printed version info. */ | |
1255 | if (tulip_debug > 0 && did_version++ == 0) | |
1256 | printk (KERN_INFO "%s", version); | |
1257 | #endif | |
1258 | ||
1259 | board_idx++; | |
1260 | ||
1261 | /* | |
1262 | * Lan media wire a tulip chip to a wan interface. Needs a very | |
1263 | * different driver (lmc driver) | |
1264 | */ | |
1265 | ||
1266 | if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) { | |
1267 | printk (KERN_ERR PFX "skipping LMC card.\n"); | |
1268 | return -ENODEV; | |
1269 | } | |
1270 | ||
1271 | /* | |
1272 | * Early DM9100's need software CRC and the DMFE driver | |
1273 | */ | |
1274 | ||
1275 | if (pdev->vendor == 0x1282 && pdev->device == 0x9100) | |
1276 | { | |
1277 | u32 dev_rev; | |
1278 | /* Read Chip revision */ | |
1279 | pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev); | |
1280 | if(dev_rev < 0x02000030) | |
1281 | { | |
1282 | printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n"); | |
1283 | return -ENODEV; | |
1284 | } | |
1285 | } | |
1286 | ||
1287 | /* | |
1288 | * Looks for early PCI chipsets where people report hangs | |
1289 | * without the workarounds being on. | |
1290 | */ | |
1291 | ||
1292 | /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache | |
f3b197ac | 1293 | aligned. Aries might need this too. The Saturn errata are not |
1da177e4 LT |
1294 | pretty reading but thankfully it's an old 486 chipset. |
1295 | ||
1296 | 2. The dreaded SiS496 486 chipset. Same workaround as Intel | |
1297 | Saturn. | |
1298 | */ | |
1299 | ||
1300 | if (pci_dev_present(early_486_chipsets)) { | |
1301 | csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift); | |
1302 | force_csr0 = 1; | |
1303 | } | |
1304 | ||
1305 | /* bugfix: the ASIX must have a burst limit or horrible things happen. */ | |
1306 | if (chip_idx == AX88140) { | |
1307 | if ((csr0 & 0x3f00) == 0) | |
1308 | csr0 |= 0x2000; | |
1309 | } | |
1310 | ||
1311 | /* PNIC doesn't have MWI/MRL/MRM... */ | |
1312 | if (chip_idx == LC82C168) | |
1313 | csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */ | |
1314 | ||
1315 | /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */ | |
1316 | if (tulip_uli_dm_quirk(pdev)) { | |
1317 | csr0 &= ~0x01f100ff; | |
1318 | #if defined(__sparc__) | |
1319 | csr0 = (csr0 & ~0xff00) | 0xe000; | |
1320 | #endif | |
1321 | } | |
1322 | /* | |
1323 | * And back to business | |
1324 | */ | |
1325 | ||
1326 | i = pci_enable_device(pdev); | |
1327 | if (i) { | |
1328 | printk (KERN_ERR PFX | |
1329 | "Cannot enable tulip board #%d, aborting\n", | |
1330 | board_idx); | |
1331 | return i; | |
1332 | } | |
1333 | ||
1334 | irq = pdev->irq; | |
1335 | ||
1336 | /* alloc_etherdev ensures aligned and zeroed private structures */ | |
1337 | dev = alloc_etherdev (sizeof (*tp)); | |
1338 | if (!dev) { | |
1339 | printk (KERN_ERR PFX "ether device alloc failed, aborting\n"); | |
1340 | return -ENOMEM; | |
1341 | } | |
1342 | ||
1343 | SET_MODULE_OWNER(dev); | |
1344 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1345 | if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) { | |
7c7459d1 | 1346 | printk (KERN_ERR PFX "%s: I/O region (0x%llx@0x%llx) too small, " |
1da177e4 | 1347 | "aborting\n", pci_name(pdev), |
7c7459d1 GKH |
1348 | (unsigned long long)pci_resource_len (pdev, 0), |
1349 | (unsigned long long)pci_resource_start (pdev, 0)); | |
1da177e4 LT |
1350 | goto err_out_free_netdev; |
1351 | } | |
1352 | ||
1353 | /* grab all resources from both PIO and MMIO regions, as we | |
1354 | * don't want anyone else messing around with our hardware */ | |
1355 | if (pci_request_regions (pdev, "tulip")) | |
1356 | goto err_out_free_netdev; | |
1357 | ||
7f2b1248 GG |
1358 | ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size); |
1359 | ||
1da177e4 LT |
1360 | if (!ioaddr) |
1361 | goto err_out_free_res; | |
1362 | ||
1363 | pci_read_config_byte (pdev, PCI_REVISION_ID, &chip_rev); | |
1364 | ||
1365 | /* | |
1366 | * initialize private data structure 'tp' | |
1367 | * it is zeroed and aligned in alloc_etherdev | |
1368 | */ | |
1369 | tp = netdev_priv(dev); | |
c4028958 | 1370 | tp->dev = dev; |
1da177e4 LT |
1371 | |
1372 | tp->rx_ring = pci_alloc_consistent(pdev, | |
1373 | sizeof(struct tulip_rx_desc) * RX_RING_SIZE + | |
1374 | sizeof(struct tulip_tx_desc) * TX_RING_SIZE, | |
1375 | &tp->rx_ring_dma); | |
1376 | if (!tp->rx_ring) | |
1377 | goto err_out_mtable; | |
1378 | tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE); | |
1379 | tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE; | |
1380 | ||
1381 | tp->chip_id = chip_idx; | |
1382 | tp->flags = tulip_tbl[chip_idx].flags; | |
1383 | tp->pdev = pdev; | |
1384 | tp->base_addr = ioaddr; | |
1385 | tp->revision = chip_rev; | |
1386 | tp->csr0 = csr0; | |
1387 | spin_lock_init(&tp->lock); | |
1388 | spin_lock_init(&tp->mii_lock); | |
1389 | init_timer(&tp->timer); | |
1390 | tp->timer.data = (unsigned long)dev; | |
1391 | tp->timer.function = tulip_tbl[tp->chip_id].media_timer; | |
1392 | ||
c4028958 | 1393 | INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task); |
0bb3cf72 | 1394 | |
1da177e4 LT |
1395 | dev->base_addr = (unsigned long)ioaddr; |
1396 | ||
1397 | #ifdef CONFIG_TULIP_MWI | |
1398 | if (!force_csr0 && (tp->flags & HAS_PCI_MWI)) | |
1399 | tulip_mwi_config (pdev, dev); | |
1400 | #else | |
1401 | /* MWI is broken for DC21143 rev 65... */ | |
1402 | if (chip_idx == DC21143 && chip_rev == 65) | |
1403 | tp->csr0 &= ~MWI; | |
1404 | #endif | |
1405 | ||
1406 | /* Stop the chip's Tx and Rx processes. */ | |
1407 | tulip_stop_rxtx(tp); | |
1408 | ||
1409 | pci_set_master(pdev); | |
1410 | ||
1411 | #ifdef CONFIG_GSC | |
1412 | if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) { | |
1413 | switch (pdev->subsystem_device) { | |
1414 | default: | |
1415 | break; | |
1416 | case 0x1061: | |
1417 | case 0x1062: | |
1418 | case 0x1063: | |
1419 | case 0x1098: | |
1420 | case 0x1099: | |
1421 | case 0x10EE: | |
1422 | tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE; | |
1423 | chip_name = "GSC DS21140 Tulip"; | |
1424 | } | |
1425 | } | |
1426 | #endif | |
1427 | ||
1428 | /* Clear the missed-packet counter. */ | |
1429 | ioread32(ioaddr + CSR8); | |
1430 | ||
1431 | /* The station address ROM is read byte serially. The register must | |
1432 | be polled, waiting for the value to be read bit serially from the | |
1433 | EEPROM. | |
1434 | */ | |
1435 | ee_data = tp->eeprom; | |
1436 | sum = 0; | |
1437 | if (chip_idx == LC82C168) { | |
1438 | for (i = 0; i < 3; i++) { | |
1439 | int value, boguscnt = 100000; | |
1440 | iowrite32(0x600 | i, ioaddr + 0x98); | |
1441 | do | |
1442 | value = ioread32(ioaddr + CSR9); | |
1443 | while (value < 0 && --boguscnt > 0); | |
1444 | put_unaligned(le16_to_cpu(value), ((u16*)dev->dev_addr) + i); | |
1445 | sum += value & 0xffff; | |
1446 | } | |
1447 | } else if (chip_idx == COMET) { | |
1448 | /* No need to read the EEPROM. */ | |
1449 | put_unaligned(cpu_to_le32(ioread32(ioaddr + 0xA4)), (u32 *)dev->dev_addr); | |
1450 | put_unaligned(cpu_to_le16(ioread32(ioaddr + 0xA8)), (u16 *)(dev->dev_addr + 4)); | |
1451 | for (i = 0; i < 6; i ++) | |
1452 | sum += dev->dev_addr[i]; | |
1453 | } else { | |
1454 | /* A serial EEPROM interface, we read now and sort it out later. */ | |
1455 | int sa_offset = 0; | |
1456 | int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6; | |
1457 | ||
1458 | for (i = 0; i < sizeof(tp->eeprom); i+=2) { | |
1459 | u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size); | |
1460 | ee_data[i] = data & 0xff; | |
1461 | ee_data[i + 1] = data >> 8; | |
1462 | } | |
1463 | ||
1464 | /* DEC now has a specification (see Notes) but early board makers | |
1465 | just put the address in the first EEPROM locations. */ | |
1466 | /* This does memcmp(ee_data, ee_data+16, 8) */ | |
1467 | for (i = 0; i < 8; i ++) | |
1468 | if (ee_data[i] != ee_data[16+i]) | |
1469 | sa_offset = 20; | |
1470 | if (chip_idx == CONEXANT) { | |
1471 | /* Check that the tuple type and length is correct. */ | |
1472 | if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6) | |
1473 | sa_offset = 0x19A; | |
1474 | } else if (ee_data[0] == 0xff && ee_data[1] == 0xff && | |
1475 | ee_data[2] == 0) { | |
1476 | sa_offset = 2; /* Grrr, damn Matrox boards. */ | |
1477 | multiport_cnt = 4; | |
1478 | } | |
1da177e4 LT |
1479 | #ifdef CONFIG_DDB5477 |
1480 | if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) { | |
1481 | /* DDB5477 MAC address in first EEPROM locations. */ | |
1482 | sa_offset = 0; | |
1483 | /* No media table either */ | |
1484 | tp->flags &= ~HAS_MEDIA_TABLE; | |
1485 | } | |
1486 | #endif | |
1487 | #ifdef CONFIG_MIPS_COBALT | |
f3b197ac | 1488 | if ((pdev->bus->number == 0) && |
1da177e4 LT |
1489 | ((PCI_SLOT(pdev->devfn) == 7) || |
1490 | (PCI_SLOT(pdev->devfn) == 12))) { | |
1491 | /* Cobalt MAC address in first EEPROM locations. */ | |
1492 | sa_offset = 0; | |
12755c16 RB |
1493 | /* Ensure our media table fixup get's applied */ |
1494 | memcpy(ee_data + 16, ee_data, 8); | |
1da177e4 LT |
1495 | } |
1496 | #endif | |
1497 | #ifdef CONFIG_GSC | |
1498 | /* Check to see if we have a broken srom */ | |
1499 | if (ee_data[0] == 0x61 && ee_data[1] == 0x10) { | |
1500 | /* pci_vendor_id and subsystem_id are swapped */ | |
1501 | ee_data[0] = ee_data[2]; | |
1502 | ee_data[1] = ee_data[3]; | |
1503 | ee_data[2] = 0x61; | |
1504 | ee_data[3] = 0x10; | |
1505 | ||
1506 | /* HSC-PCI boards need to be byte-swaped and shifted | |
1507 | * up 1 word. This shift needs to happen at the end | |
1508 | * of the MAC first because of the 2 byte overlap. | |
1509 | */ | |
1510 | for (i = 4; i >= 0; i -= 2) { | |
1511 | ee_data[17 + i + 3] = ee_data[17 + i]; | |
1512 | ee_data[16 + i + 5] = ee_data[16 + i]; | |
1513 | } | |
1514 | } | |
1515 | #endif | |
1516 | ||
1517 | for (i = 0; i < 6; i ++) { | |
1518 | dev->dev_addr[i] = ee_data[i + sa_offset]; | |
1519 | sum += ee_data[i + sa_offset]; | |
1520 | } | |
1521 | } | |
1522 | /* Lite-On boards have the address byte-swapped. */ | |
1523 | if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0 || dev->dev_addr[0] == 0x02) | |
1524 | && dev->dev_addr[1] == 0x00) | |
1525 | for (i = 0; i < 6; i+=2) { | |
1526 | char tmp = dev->dev_addr[i]; | |
1527 | dev->dev_addr[i] = dev->dev_addr[i+1]; | |
1528 | dev->dev_addr[i+1] = tmp; | |
1529 | } | |
1530 | /* On the Zynx 315 Etherarray and other multiport boards only the | |
1531 | first Tulip has an EEPROM. | |
1532 | On Sparc systems the mac address is held in the OBP property | |
1533 | "local-mac-address". | |
1534 | The addresses of the subsequent ports are derived from the first. | |
1535 | Many PCI BIOSes also incorrectly report the IRQ line, so we correct | |
1536 | that here as well. */ | |
1537 | if (sum == 0 || sum == 6*0xff) { | |
1538 | #if defined(__sparc__) | |
1539 | struct pcidev_cookie *pcp = pdev->sysdata; | |
1540 | #endif | |
1541 | eeprom_missing = 1; | |
1542 | for (i = 0; i < 5; i++) | |
1543 | dev->dev_addr[i] = last_phys_addr[i]; | |
1544 | dev->dev_addr[i] = last_phys_addr[i] + 1; | |
1545 | #if defined(__sparc__) | |
de8d28b1 DM |
1546 | if (pcp) { |
1547 | unsigned char *addr; | |
1548 | int len; | |
6aa20a22 | 1549 | |
de8d28b1 DM |
1550 | addr = of_get_property(pcp->prom_node, |
1551 | "local-mac-address", &len); | |
1552 | if (addr && len == 6) | |
1553 | memcpy(dev->dev_addr, addr, 6); | |
1da177e4 LT |
1554 | } |
1555 | #endif | |
b9c4c609 | 1556 | #if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */ |
1da177e4 LT |
1557 | if (last_irq) |
1558 | irq = last_irq; | |
1559 | #endif | |
1560 | } | |
1561 | ||
1562 | for (i = 0; i < 6; i++) | |
1563 | last_phys_addr[i] = dev->dev_addr[i]; | |
1564 | last_irq = irq; | |
1565 | dev->irq = irq; | |
1566 | ||
1567 | /* The lower four bits are the media type. */ | |
1568 | if (board_idx >= 0 && board_idx < MAX_UNITS) { | |
1569 | if (options[board_idx] & MEDIA_MASK) | |
1570 | tp->default_port = options[board_idx] & MEDIA_MASK; | |
1571 | if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0) | |
1572 | tp->full_duplex = 1; | |
1573 | if (mtu[board_idx] > 0) | |
1574 | dev->mtu = mtu[board_idx]; | |
1575 | } | |
1576 | if (dev->mem_start & MEDIA_MASK) | |
1577 | tp->default_port = dev->mem_start & MEDIA_MASK; | |
1578 | if (tp->default_port) { | |
1579 | printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n", | |
1580 | board_idx, medianame[tp->default_port & MEDIA_MASK]); | |
1581 | tp->medialock = 1; | |
1582 | if (tulip_media_cap[tp->default_port] & MediaAlwaysFD) | |
1583 | tp->full_duplex = 1; | |
1584 | } | |
1585 | if (tp->full_duplex) | |
1586 | tp->full_duplex_lock = 1; | |
1587 | ||
1588 | if (tulip_media_cap[tp->default_port] & MediaIsMII) { | |
1589 | u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 }; | |
1590 | tp->mii_advertise = media2advert[tp->default_port - 9]; | |
1591 | tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */ | |
1592 | } | |
1593 | ||
1594 | if (tp->flags & HAS_MEDIA_TABLE) { | |
1595 | sprintf(dev->name, "tulip%d", board_idx); /* hack */ | |
1596 | tulip_parse_eeprom(dev); | |
1597 | strcpy(dev->name, "eth%d"); /* un-hack */ | |
1598 | } | |
1599 | ||
1600 | if ((tp->flags & ALWAYS_CHECK_MII) || | |
1601 | (tp->mtable && tp->mtable->has_mii) || | |
1602 | ( ! tp->mtable && (tp->flags & HAS_MII))) { | |
1603 | if (tp->mtable && tp->mtable->has_mii) { | |
1604 | for (i = 0; i < tp->mtable->leafcount; i++) | |
1605 | if (tp->mtable->mleaf[i].media == 11) { | |
1606 | tp->cur_index = i; | |
1607 | tp->saved_if_port = dev->if_port; | |
1608 | tulip_select_media(dev, 2); | |
1609 | dev->if_port = tp->saved_if_port; | |
1610 | break; | |
1611 | } | |
1612 | } | |
1613 | ||
1614 | /* Find the connected MII xcvrs. | |
1615 | Doing this in open() would allow detecting external xcvrs | |
1616 | later, but takes much time. */ | |
1617 | tulip_find_mii (dev, board_idx); | |
1618 | } | |
1619 | ||
1620 | /* The Tulip-specific entries in the device structure. */ | |
1621 | dev->open = tulip_open; | |
1622 | dev->hard_start_xmit = tulip_start_xmit; | |
1623 | dev->tx_timeout = tulip_tx_timeout; | |
1624 | dev->watchdog_timeo = TX_TIMEOUT; | |
1625 | #ifdef CONFIG_TULIP_NAPI | |
1626 | dev->poll = tulip_poll; | |
1627 | dev->weight = 16; | |
1628 | #endif | |
1629 | dev->stop = tulip_close; | |
1630 | dev->get_stats = tulip_get_stats; | |
1631 | dev->do_ioctl = private_ioctl; | |
1632 | dev->set_multicast_list = set_rx_mode; | |
1633 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1634 | dev->poll_controller = &poll_tulip; | |
1635 | #endif | |
1636 | SET_ETHTOOL_OPS(dev, &ops); | |
1637 | ||
1638 | if (register_netdev(dev)) | |
1639 | goto err_out_free_ring; | |
1640 | ||
c69f4122 GG |
1641 | printk(KERN_INFO "%s: %s rev %d at " |
1642 | #ifdef CONFIG_TULIP_MMIO | |
1643 | "MMIO" | |
1644 | #else | |
1645 | "Port" | |
1646 | #endif | |
1647 | " %#llx,", dev->name, chip_name, chip_rev, | |
1648 | (unsigned long long) pci_resource_start(pdev, TULIP_BAR)); | |
1da177e4 LT |
1649 | pci_set_drvdata(pdev, dev); |
1650 | ||
1651 | if (eeprom_missing) | |
1652 | printk(" EEPROM not present,"); | |
1653 | for (i = 0; i < 6; i++) | |
1654 | printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]); | |
1655 | printk(", IRQ %d.\n", irq); | |
1656 | ||
1657 | if (tp->chip_id == PNIC2) | |
1658 | tp->link_change = pnic2_lnk_change; | |
1659 | else if (tp->flags & HAS_NWAY) | |
1660 | tp->link_change = t21142_lnk_change; | |
1661 | else if (tp->flags & HAS_PNICNWAY) | |
1662 | tp->link_change = pnic_lnk_change; | |
1663 | ||
1664 | /* Reset the xcvr interface and turn on heartbeat. */ | |
1665 | switch (chip_idx) { | |
1666 | case DC21140: | |
1667 | case DM910X: | |
1da177e4 LT |
1668 | default: |
1669 | if (tp->mtable) | |
1670 | iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12); | |
1671 | break; | |
1672 | case DC21142: | |
1673 | if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) { | |
1674 | iowrite32(csr6_mask_defstate, ioaddr + CSR6); | |
1675 | iowrite32(0x0000, ioaddr + CSR13); | |
1676 | iowrite32(0x0000, ioaddr + CSR14); | |
1677 | iowrite32(csr6_mask_hdcap, ioaddr + CSR6); | |
1678 | } else | |
1679 | t21142_start_nway(dev); | |
1680 | break; | |
1681 | case PNIC2: | |
1682 | /* just do a reset for sanity sake */ | |
1683 | iowrite32(0x0000, ioaddr + CSR13); | |
1684 | iowrite32(0x0000, ioaddr + CSR14); | |
1685 | break; | |
1686 | case LC82C168: | |
1687 | if ( ! tp->mii_cnt) { | |
1688 | tp->nway = 1; | |
1689 | tp->nwayset = 0; | |
1690 | iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6); | |
1691 | iowrite32(0x30, ioaddr + CSR12); | |
1692 | iowrite32(0x0001F078, ioaddr + CSR6); | |
1693 | iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */ | |
1694 | } | |
1695 | break; | |
1696 | case MX98713: | |
1697 | case COMPEX9881: | |
1698 | iowrite32(0x00000000, ioaddr + CSR6); | |
1699 | iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */ | |
1700 | iowrite32(0x00000001, ioaddr + CSR13); | |
1701 | break; | |
1702 | case MX98715: | |
1703 | case MX98725: | |
1704 | iowrite32(0x01a80000, ioaddr + CSR6); | |
1705 | iowrite32(0xFFFFFFFF, ioaddr + CSR14); | |
1706 | iowrite32(0x00001000, ioaddr + CSR12); | |
1707 | break; | |
1708 | case COMET: | |
1709 | /* No initialization necessary. */ | |
1710 | break; | |
1711 | } | |
1712 | ||
1713 | /* put the chip in snooze mode until opened */ | |
1714 | tulip_set_power_state (tp, 0, 1); | |
1715 | ||
1716 | return 0; | |
1717 | ||
1718 | err_out_free_ring: | |
1719 | pci_free_consistent (pdev, | |
1720 | sizeof (struct tulip_rx_desc) * RX_RING_SIZE + | |
1721 | sizeof (struct tulip_tx_desc) * TX_RING_SIZE, | |
1722 | tp->rx_ring, tp->rx_ring_dma); | |
1723 | ||
1724 | err_out_mtable: | |
b4558ea9 | 1725 | kfree (tp->mtable); |
1da177e4 LT |
1726 | pci_iounmap(pdev, ioaddr); |
1727 | ||
1728 | err_out_free_res: | |
1729 | pci_release_regions (pdev); | |
1730 | ||
1731 | err_out_free_netdev: | |
1732 | free_netdev (dev); | |
1733 | return -ENODEV; | |
1734 | } | |
1735 | ||
1736 | ||
1737 | #ifdef CONFIG_PM | |
1738 | ||
1739 | static int tulip_suspend (struct pci_dev *pdev, pm_message_t state) | |
1740 | { | |
1741 | struct net_device *dev = pci_get_drvdata(pdev); | |
1742 | ||
1fe2cb32 AB |
1743 | if (!dev) |
1744 | return -EINVAL; | |
1745 | ||
1746 | if (netif_running(dev)) | |
1747 | tulip_down(dev); | |
1748 | ||
1749 | netif_device_detach(dev); | |
1750 | free_irq(dev->irq, dev); | |
1751 | ||
1752 | pci_save_state(pdev); | |
1753 | pci_disable_device(pdev); | |
1754 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1755 | ||
1da177e4 LT |
1756 | return 0; |
1757 | } | |
1758 | ||
1759 | ||
1760 | static int tulip_resume(struct pci_dev *pdev) | |
1761 | { | |
1762 | struct net_device *dev = pci_get_drvdata(pdev); | |
1fe2cb32 | 1763 | int retval; |
1da177e4 | 1764 | |
1fe2cb32 AB |
1765 | if (!dev) |
1766 | return -EINVAL; | |
1767 | ||
1768 | pci_set_power_state(pdev, PCI_D0); | |
1769 | pci_restore_state(pdev); | |
1770 | ||
9f486ae1 VH |
1771 | if ((retval = pci_enable_device(pdev))) { |
1772 | printk (KERN_ERR "tulip: pci_enable_device failed in resume\n"); | |
1773 | return retval; | |
1774 | } | |
1fe2cb32 | 1775 | |
1fb9df5d | 1776 | if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) { |
1fe2cb32 AB |
1777 | printk (KERN_ERR "tulip: request_irq failed in resume\n"); |
1778 | return retval; | |
1da177e4 | 1779 | } |
1fe2cb32 AB |
1780 | |
1781 | netif_device_attach(dev); | |
1782 | ||
1783 | if (netif_running(dev)) | |
1784 | tulip_up(dev); | |
1785 | ||
1da177e4 LT |
1786 | return 0; |
1787 | } | |
1788 | ||
1789 | #endif /* CONFIG_PM */ | |
1790 | ||
1791 | ||
1792 | static void __devexit tulip_remove_one (struct pci_dev *pdev) | |
1793 | { | |
1794 | struct net_device *dev = pci_get_drvdata (pdev); | |
1795 | struct tulip_private *tp; | |
1796 | ||
1797 | if (!dev) | |
1798 | return; | |
1799 | ||
1800 | tp = netdev_priv(dev); | |
1801 | unregister_netdev(dev); | |
1802 | pci_free_consistent (pdev, | |
1803 | sizeof (struct tulip_rx_desc) * RX_RING_SIZE + | |
1804 | sizeof (struct tulip_tx_desc) * TX_RING_SIZE, | |
1805 | tp->rx_ring, tp->rx_ring_dma); | |
b4558ea9 | 1806 | kfree (tp->mtable); |
1da177e4 LT |
1807 | pci_iounmap(pdev, tp->base_addr); |
1808 | free_netdev (dev); | |
1809 | pci_release_regions (pdev); | |
1810 | pci_set_drvdata (pdev, NULL); | |
1811 | ||
1812 | /* pci_power_off (pdev, -1); */ | |
1813 | } | |
1814 | ||
1815 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1816 | /* | |
1817 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1818 | * without having to re-enable interrupts. It's not called while | |
1819 | * the interrupt routine is executing. | |
1820 | */ | |
1821 | ||
1822 | static void poll_tulip (struct net_device *dev) | |
1823 | { | |
1824 | /* disable_irq here is not very nice, but with the lockless | |
1825 | interrupt handler we have no other choice. */ | |
1826 | disable_irq(dev->irq); | |
7d12e780 | 1827 | tulip_interrupt (dev->irq, dev); |
1da177e4 LT |
1828 | enable_irq(dev->irq); |
1829 | } | |
1830 | #endif | |
1831 | ||
1832 | static struct pci_driver tulip_driver = { | |
1833 | .name = DRV_NAME, | |
1834 | .id_table = tulip_pci_tbl, | |
1835 | .probe = tulip_init_one, | |
1836 | .remove = __devexit_p(tulip_remove_one), | |
1837 | #ifdef CONFIG_PM | |
1838 | .suspend = tulip_suspend, | |
1839 | .resume = tulip_resume, | |
1840 | #endif /* CONFIG_PM */ | |
1841 | }; | |
1842 | ||
1843 | ||
1844 | static int __init tulip_init (void) | |
1845 | { | |
1846 | #ifdef MODULE | |
1847 | printk (KERN_INFO "%s", version); | |
1848 | #endif | |
1849 | ||
1850 | /* copy module parms into globals */ | |
1851 | tulip_rx_copybreak = rx_copybreak; | |
1852 | tulip_max_interrupt_work = max_interrupt_work; | |
1853 | ||
1854 | /* probe for and init boards */ | |
29917620 | 1855 | return pci_register_driver(&tulip_driver); |
1da177e4 LT |
1856 | } |
1857 | ||
1858 | ||
1859 | static void __exit tulip_cleanup (void) | |
1860 | { | |
1861 | pci_unregister_driver (&tulip_driver); | |
1862 | } | |
1863 | ||
1864 | ||
1865 | module_init(tulip_init); | |
1866 | module_exit(tulip_cleanup); |