projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] sparc: Port esp to new SBUS driver layer.
[linux-2.6-block.git] / drivers / net / sunhme.c
CommitLineData
1da177e4
LT		 1/* $Id: sunhme.c,v 1.124 2002/01/15 06:25:51 davem Exp $
2 * sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
3 * auto carrier detecting ethernet driver. Also known as the
4 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
5 *
6 * Copyright (C) 1996, 1998, 1999, 2002, 2003 David S. Miller (davem@redhat.com)
7 *
8 * Changes :
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
14 */
15
1da177e4
LT		 16#include <linux/config.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/fcntl.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/in.h>
24#include <linux/slab.h>
25#include <linux/string.h>
26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/ethtool.h>
29#include <linux/mii.h>
30#include <linux/crc32.h>
31#include <linux/random.h>
32#include <linux/errno.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
36#include <linux/bitops.h>
37
38#include <asm/system.h>
39#include <asm/io.h>
40#include <asm/dma.h>
41#include <asm/byteorder.h>
42
43#ifdef __sparc__
44#include <asm/idprom.h>
45#include <asm/sbus.h>
46#include <asm/openprom.h>
47#include <asm/oplib.h>
942a6bdd 48#include <asm/prom.h>
1da177e4
LT		 49#include <asm/auxio.h>
50#ifndef __sparc_v9__
51#include <asm/io-unit.h>
52#endif
53#endif
54#include <asm/uaccess.h>
55
56#include <asm/pgtable.h>
57#include <asm/irq.h>
58
59#ifdef CONFIG_PCI
60#include <linux/pci.h>
61#ifdef __sparc__
62#include <asm/pbm.h>
63#endif
64#endif
65
66#include "sunhme.h"
67
10158286
TC		 68#define DRV_NAME "sunhme"
69#define DRV_VERSION "2.02"
70#define DRV_RELDATE "8/24/03"
71#define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
72
73static char version[] =
74 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
1da177e4 75
10158286
TC		 76MODULE_VERSION(DRV_VERSION);
77MODULE_AUTHOR(DRV_AUTHOR);
78MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
79MODULE_LICENSE("GPL");
1da177e4
LT		 80
81static int macaddr[6];
82
83/* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
84module_param_array(macaddr, int, NULL, 0);
85MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
1da177e4
LT		 86
87static struct happy_meal *root_happy_dev;
88
89#ifdef CONFIG_SBUS
90static struct quattro *qfe_sbus_list;
91#endif
92
93#ifdef CONFIG_PCI
94static struct quattro *qfe_pci_list;
95#endif
96
97#undef HMEDEBUG
98#undef SXDEBUG
99#undef RXDEBUG
100#undef TXDEBUG
101#undef TXLOGGING
102
103#ifdef TXLOGGING
104struct hme_tx_logent {
105 unsigned int tstamp;
106 int tx_new, tx_old;
107 unsigned int action;
108#define TXLOG_ACTION_IRQ 0x01
109#define TXLOG_ACTION_TXMIT 0x02
110#define TXLOG_ACTION_TBUSY 0x04
111#define TXLOG_ACTION_NBUFS 0x08
112 unsigned int status;
113};
114#define TX_LOG_LEN 128
115static struct hme_tx_logent tx_log[TX_LOG_LEN];
116static int txlog_cur_entry;
117static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
118{
119 struct hme_tx_logent *tlp;
120 unsigned long flags;
121
122 save_and_cli(flags);
123 tlp = &tx_log[txlog_cur_entry];
124 tlp->tstamp = (unsigned int)jiffies;
125 tlp->tx_new = hp->tx_new;
126 tlp->tx_old = hp->tx_old;
127 tlp->action = a;
128 tlp->status = s;
129 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
130 restore_flags(flags);
131}
132static __inline__ void tx_dump_log(void)
133{
134 int i, this;
135
136 this = txlog_cur_entry;
137 for (i = 0; i < TX_LOG_LEN; i++) {
138 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
139 tx_log[this].tstamp,
140 tx_log[this].tx_new, tx_log[this].tx_old,
141 tx_log[this].action, tx_log[this].status);
142 this = (this + 1) & (TX_LOG_LEN - 1);
143 }
144}
145static __inline__ void tx_dump_ring(struct happy_meal *hp)
146{
147 struct hmeal_init_block *hb = hp->happy_block;
148 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
149 int i;
150
151 for (i = 0; i < TX_RING_SIZE; i+=4) {
152 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
153 i, i + 4,
154 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
155 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
156 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
157 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
158 }
159}
160#else
161#define tx_add_log(hp, a, s) do { } while(0)
162#define tx_dump_log() do { } while(0)
163#define tx_dump_ring(hp) do { } while(0)
164#endif
165
166#ifdef HMEDEBUG
167#define HMD(x) printk x
168#else
169#define HMD(x)
170#endif
171
172/* #define AUTO_SWITCH_DEBUG */
173
174#ifdef AUTO_SWITCH_DEBUG
175#define ASD(x) printk x
176#else
177#define ASD(x)
178#endif
179
180#define DEFAULT_IPG0 16 /* For lance-mode only */
181#define DEFAULT_IPG1 8 /* For all modes */
182#define DEFAULT_IPG2 4 /* For all modes */
183#define DEFAULT_JAMSIZE 4 /* Toe jam */
184
185#if defined(CONFIG_PCI) && defined(MODULE)
186/* This happy_pci_ids is declared __initdata because it is only used
187 as an advisory to depmod. If this is ported to the new PCI interface
188 where it could be referenced at any time due to hot plugging,
189 the __initdata reference should be removed. */
190
191static struct pci_device_id happymeal_pci_ids[] = {
192 {
193 .vendor = PCI_VENDOR_ID_SUN,
194 .device = PCI_DEVICE_ID_SUN_HAPPYMEAL,
195 .subvendor = PCI_ANY_ID,
196 .subdevice = PCI_ANY_ID,
197 },
198 { } /* Terminating entry */
199};
200
201MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
202
203#endif
204
205/* NOTE: In the descriptor writes one _must_ write the address
206 * member _first_. The card must not be allowed to see
207 * the updated descriptor flags until the address is
208 * correct. I've added a write memory barrier between
209 * the two stores so that I can sleep well at night... -DaveM
210 */
211
212#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
213static void sbus_hme_write32(void __iomem *reg, u32 val)
214{
215 sbus_writel(val, reg);
216}
217
218static u32 sbus_hme_read32(void __iomem *reg)
219{
220 return sbus_readl(reg);
221}
222
223static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
224{
225 rxd->rx_addr = addr;
226 wmb();
227 rxd->rx_flags = flags;
228}
229
230static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
231{
232 txd->tx_addr = addr;
233 wmb();
234 txd->tx_flags = flags;
235}
236
237static u32 sbus_hme_read_desc32(u32 *p)
238{
239 return *p;
240}
241
242static void pci_hme_write32(void __iomem *reg, u32 val)
243{
244 writel(val, reg);
245}
246
247static u32 pci_hme_read32(void __iomem *reg)
248{
249 return readl(reg);
250}
251
252static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
253{
254 rxd->rx_addr = cpu_to_le32(addr);
255 wmb();
256 rxd->rx_flags = cpu_to_le32(flags);
257}
258
259static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
260{
261 txd->tx_addr = cpu_to_le32(addr);
262 wmb();
263 txd->tx_flags = cpu_to_le32(flags);
264}
265
266static u32 pci_hme_read_desc32(u32 *p)
267{
268 return cpu_to_le32p(p);
269}
270
271#define hme_write32(__hp, __reg, __val) \
272 ((__hp)->write32((__reg), (__val)))
273#define hme_read32(__hp, __reg) \
274 ((__hp)->read32(__reg))
275#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
276 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
277#define hme_write_txd(__hp, __txd, __flags, __addr) \
278 ((__hp)->write_txd((__txd), (__flags), (__addr)))
279#define hme_read_desc32(__hp, __p) \
280 ((__hp)->read_desc32(__p))
281#define hme_dma_map(__hp, __ptr, __size, __dir) \
282 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
283#define hme_dma_unmap(__hp, __addr, __size, __dir) \
284 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
285#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
286 ((__hp)->dma_sync_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir)))
287#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
288 ((__hp)->dma_sync_for_device((__hp)->happy_dev, (__addr), (__size), (__dir)))
289#else
290#ifdef CONFIG_SBUS
291/* SBUS only compilation */
292#define hme_write32(__hp, __reg, __val) \
293 sbus_writel((__val), (__reg))
294#define hme_read32(__hp, __reg) \
295 sbus_readl(__reg)
296#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
297do { (__rxd)->rx_addr = (__addr); \
298 wmb(); \
299 (__rxd)->rx_flags = (__flags); \
300} while(0)
301#define hme_write_txd(__hp, __txd, __flags, __addr) \
302do { (__txd)->tx_addr = (__addr); \
303 wmb(); \
304 (__txd)->tx_flags = (__flags); \
305} while(0)
306#define hme_read_desc32(__hp, __p) (*(__p))
307#define hme_dma_map(__hp, __ptr, __size, __dir) \
308 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
309#define hme_dma_unmap(__hp, __addr, __size, __dir) \
310 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
311#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
312 sbus_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
313#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
314 sbus_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
315#else
316/* PCI only compilation */
317#define hme_write32(__hp, __reg, __val) \
318 writel((__val), (__reg))
319#define hme_read32(__hp, __reg) \
320 readl(__reg)
321#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
322do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
323 wmb(); \
324 (__rxd)->rx_flags = cpu_to_le32(__flags); \
325} while(0)
326#define hme_write_txd(__hp, __txd, __flags, __addr) \
327do { (__txd)->tx_addr = cpu_to_le32(__addr); \
328 wmb(); \
329 (__txd)->tx_flags = cpu_to_le32(__flags); \
330} while(0)
331#define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
332#define hme_dma_map(__hp, __ptr, __size, __dir) \
333 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
334#define hme_dma_unmap(__hp, __addr, __size, __dir) \
335 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
336#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
337 pci_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
338#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
339 pci_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
340#endif
341#endif
342
343
344#ifdef SBUS_DMA_BIDIRECTIONAL
345# define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
346#else
347# define DMA_BIDIRECTIONAL 0
348#endif
349
350#ifdef SBUS_DMA_FROMDEVICE
351# define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
352#else
353# define DMA_TODEVICE 1
354#endif
355
356#ifdef SBUS_DMA_TODEVICE
357# define DMA_TODEVICE SBUS_DMA_TODEVICE
358#else
359# define DMA_FROMDEVICE 2
360#endif
361
362
363/* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
364static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
365{
366 hme_write32(hp, tregs + TCVR_BBDATA, bit);
367 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
368 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
369}
370
371#if 0
372static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
373{
374 u32 ret;
375
376 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
377 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
378 ret = hme_read32(hp, tregs + TCVR_CFG);
379 if (internal)
380 ret &= TCV_CFG_MDIO0;
381 else
382 ret &= TCV_CFG_MDIO1;
383
384 return ret;
385}
386#endif
387
388static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
389{
390 u32 retval;
391
392 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
393 udelay(1);
394 retval = hme_read32(hp, tregs + TCVR_CFG);
395 if (internal)
396 retval &= TCV_CFG_MDIO0;
397 else
398 retval &= TCV_CFG_MDIO1;
399 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
400
401 return retval;
402}
403
404#define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
405
406static int happy_meal_bb_read(struct happy_meal *hp,
407 void __iomem *tregs, int reg)
408{
409 u32 tmp;
410 int retval = 0;
411 int i;
412
413 ASD(("happy_meal_bb_read: reg=%d ", reg));
414
415 /* Enable the MIF BitBang outputs. */
416 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
417
418 /* Force BitBang into the idle state. */
419 for (i = 0; i < 32; i++)
420 BB_PUT_BIT(hp, tregs, 1);
421
422 /* Give it the read sequence. */
423 BB_PUT_BIT(hp, tregs, 0);
424 BB_PUT_BIT(hp, tregs, 1);
425 BB_PUT_BIT(hp, tregs, 1);
426 BB_PUT_BIT(hp, tregs, 0);
427
428 /* Give it the PHY address. */
429 tmp = hp->paddr & 0xff;
430 for (i = 4; i >= 0; i--)
431 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
432
433 /* Tell it what register we want to read. */
434 tmp = (reg & 0xff);
435 for (i = 4; i >= 0; i--)
436 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
437
438 /* Close down the MIF BitBang outputs. */
439 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
440
441 /* Now read in the value. */
442 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
443 for (i = 15; i >= 0; i--)
444 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
445 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
446 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
447 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
448 ASD(("value=%x\n", retval));
449 return retval;
450}
451
452static void happy_meal_bb_write(struct happy_meal *hp,
453 void __iomem *tregs, int reg,
454 unsigned short value)
455{
456 u32 tmp;
457 int i;
458
459 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
460
461 /* Enable the MIF BitBang outputs. */
462 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
463
464 /* Force BitBang into the idle state. */
465 for (i = 0; i < 32; i++)
466 BB_PUT_BIT(hp, tregs, 1);
467
468 /* Give it write sequence. */
469 BB_PUT_BIT(hp, tregs, 0);
470 BB_PUT_BIT(hp, tregs, 1);
471 BB_PUT_BIT(hp, tregs, 0);
472 BB_PUT_BIT(hp, tregs, 1);
473
474 /* Give it the PHY address. */
475 tmp = (hp->paddr & 0xff);
476 for (i = 4; i >= 0; i--)
477 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
478
479 /* Tell it what register we will be writing. */
480 tmp = (reg & 0xff);
481 for (i = 4; i >= 0; i--)
482 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
483
484 /* Tell it to become ready for the bits. */
485 BB_PUT_BIT(hp, tregs, 1);
486 BB_PUT_BIT(hp, tregs, 0);
487
488 for (i = 15; i >= 0; i--)
489 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
490
491 /* Close down the MIF BitBang outputs. */
492 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
493}
494
495#define TCVR_READ_TRIES 16
496
497static int happy_meal_tcvr_read(struct happy_meal *hp,
498 void __iomem *tregs, int reg)
499{
500 int tries = TCVR_READ_TRIES;
501 int retval;
502
503 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
504 if (hp->tcvr_type == none) {
505 ASD(("no transceiver, value=TCVR_FAILURE\n"));
506 return TCVR_FAILURE;
507 }
508
509 if (!(hp->happy_flags & HFLAG_FENABLE)) {
510 ASD(("doing bit bang\n"));
511 return happy_meal_bb_read(hp, tregs, reg);
512 }
513
514 hme_write32(hp, tregs + TCVR_FRAME,
515 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
516 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
517 udelay(20);
518 if (!tries) {
519 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
520 return TCVR_FAILURE;
521 }
522 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
523 ASD(("value=%04x\n", retval));
524 return retval;
525}
526
527#define TCVR_WRITE_TRIES 16
528
529static void happy_meal_tcvr_write(struct happy_meal *hp,
530 void __iomem *tregs, int reg,
531 unsigned short value)
532{
533 int tries = TCVR_WRITE_TRIES;
534
535 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
536
537 /* Welcome to Sun Microsystems, can I take your order please? */
538 if (!(hp->happy_flags & HFLAG_FENABLE)) {
539 happy_meal_bb_write(hp, tregs, reg, value);
540 return;
541 }
542
543 /* Would you like fries with that? */
544 hme_write32(hp, tregs + TCVR_FRAME,
545 (FRAME_WRITE | (hp->paddr << 23) |
546 ((reg & 0xff) << 18) | (value & 0xffff)));
547 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
548 udelay(20);
549
550 /* Anything else? */
551 if (!tries)
552 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
553
554 /* Fifty-two cents is your change, have a nice day. */
555}
556
557/* Auto negotiation. The scheme is very simple. We have a timer routine
558 * that keeps watching the auto negotiation process as it progresses.
559 * The DP83840 is first told to start doing it's thing, we set up the time
560 * and place the timer state machine in it's initial state.
561 *
562 * Here the timer peeks at the DP83840 status registers at each click to see
563 * if the auto negotiation has completed, we assume here that the DP83840 PHY
564 * will time out at some point and just tell us what (didn't) happen. For
565 * complete coverage we only allow so many of the ticks at this level to run,
566 * when this has expired we print a warning message and try another strategy.
567 * This "other" strategy is to force the interface into various speed/duplex
568 * configurations and we stop when we see a link-up condition before the
569 * maximum number of "peek" ticks have occurred.
570 *
571 * Once a valid link status has been detected we configure the BigMAC and
572 * the rest of the Happy Meal to speak the most efficient protocol we could
573 * get a clean link for. The priority for link configurations, highest first
574 * is:
575 * 100 Base-T Full Duplex
576 * 100 Base-T Half Duplex
577 * 10 Base-T Full Duplex
578 * 10 Base-T Half Duplex
579 *
580 * We start a new timer now, after a successful auto negotiation status has
581 * been detected. This timer just waits for the link-up bit to get set in
582 * the BMCR of the DP83840. When this occurs we print a kernel log message
583 * describing the link type in use and the fact that it is up.
584 *
585 * If a fatal error of some sort is signalled and detected in the interrupt
586 * service routine, and the chip is reset, or the link is ifconfig'd down
587 * and then back up, this entire process repeats itself all over again.
588 */
589static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
590{
591 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
592
593 /* Downgrade from full to half duplex. Only possible
594 * via ethtool.
595 */
596 if (hp->sw_bmcr & BMCR_FULLDPLX) {
597 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
598 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
599 return 0;
600 }
601
602 /* Downgrade from 100 to 10. */
603 if (hp->sw_bmcr & BMCR_SPEED100) {
604 hp->sw_bmcr &= ~(BMCR_SPEED100);
605 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
606 return 0;
607 }
608
609 /* We've tried everything. */
610 return -1;
611}
612
613static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
614{
615 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
616 if (hp->tcvr_type == external)
617 printk("external ");
618 else
619 printk("internal ");
620 printk("transceiver at ");
621 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
622 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
623 if (hp->sw_lpa & LPA_100FULL)
624 printk("100Mb/s, Full Duplex.\n");
625 else
626 printk("100Mb/s, Half Duplex.\n");
627 } else {
628 if (hp->sw_lpa & LPA_10FULL)
629 printk("10Mb/s, Full Duplex.\n");
630 else
631 printk("10Mb/s, Half Duplex.\n");
632 }
633}
634
635static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
636{
637 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
638 if (hp->tcvr_type == external)
639 printk("external ");
640 else
641 printk("internal ");
642 printk("transceiver at ");
643 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
644 if (hp->sw_bmcr & BMCR_SPEED100)
645 printk("100Mb/s, ");
646 else
647 printk("10Mb/s, ");
648 if (hp->sw_bmcr & BMCR_FULLDPLX)
649 printk("Full Duplex.\n");
650 else
651 printk("Half Duplex.\n");
652}
653
654static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
655{
656 int full;
657
658 /* All we care about is making sure the bigmac tx_cfg has a
659 * proper duplex setting.
660 */
661 if (hp->timer_state == arbwait) {
662 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
663 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
664 goto no_response;
665 if (hp->sw_lpa & LPA_100FULL)
666 full = 1;
667 else if (hp->sw_lpa & LPA_100HALF)
668 full = 0;
669 else if (hp->sw_lpa & LPA_10FULL)
670 full = 1;
671 else
672 full = 0;
673 } else {
674 /* Forcing a link mode. */
675 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
676 if (hp->sw_bmcr & BMCR_FULLDPLX)
677 full = 1;
678 else
679 full = 0;
680 }
681
682 /* Before changing other bits in the tx_cfg register, and in
683 * general any of other the TX config registers too, you
684 * must:
685 * 1) Clear Enable
686 * 2) Poll with reads until that bit reads back as zero
687 * 3) Make TX configuration changes
688 * 4) Set Enable once more
689 */
690 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
691 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
692 ~(BIGMAC_TXCFG_ENABLE));
693 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
694 barrier();
695 if (full) {
696 hp->happy_flags |= HFLAG_FULL;
697 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
698 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
699 BIGMAC_TXCFG_FULLDPLX);
700 } else {
701 hp->happy_flags &= ~(HFLAG_FULL);
702 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
703 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
704 ~(BIGMAC_TXCFG_FULLDPLX));
705 }
706 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
707 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
708 BIGMAC_TXCFG_ENABLE);
709 return 0;
710no_response:
711 return 1;
712}
713
714static int happy_meal_init(struct happy_meal *hp);
715
716static int is_lucent_phy(struct happy_meal *hp)
717{
718 void __iomem *tregs = hp->tcvregs;
719 unsigned short mr2, mr3;
720 int ret = 0;
721
722 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
723 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
724 if ((mr2 & 0xffff) == 0x0180 &&
725 ((mr3 & 0xffff) >> 10) == 0x1d)
726 ret = 1;
727
728 return ret;
729}
730
731static void happy_meal_timer(unsigned long data)
732{
733 struct happy_meal *hp = (struct happy_meal *) data;
734 void __iomem *tregs = hp->tcvregs;
735 int restart_timer = 0;
736
737 spin_lock_irq(&hp->happy_lock);
738
739 hp->timer_ticks++;
740 switch(hp->timer_state) {
741 case arbwait:
742 /* Only allow for 5 ticks, thats 10 seconds and much too
743 * long to wait for arbitration to complete.
744 */
745 if (hp->timer_ticks >= 10) {
746 /* Enter force mode. */
747 do_force_mode:
748 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
749 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
750 hp->dev->name);
751 hp->sw_bmcr = BMCR_SPEED100;
752 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
753
754 if (!is_lucent_phy(hp)) {
755 /* OK, seems we need do disable the transceiver for the first
756 * tick to make sure we get an accurate link state at the
757 * second tick.
758 */
759 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
760 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
761 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
762 }
763 hp->timer_state = ltrywait;
764 hp->timer_ticks = 0;
765 restart_timer = 1;
766 } else {
767 /* Anything interesting happen? */
768 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
769 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
770 int ret;
771
772 /* Just what we've been waiting for... */
773 ret = set_happy_link_modes(hp, tregs);
774 if (ret) {
775 /* Ooops, something bad happened, go to force
776 * mode.
777 *
778 * XXX Broken hubs which don't support 802.3u
779 * XXX auto-negotiation make this happen as well.
780 */
781 goto do_force_mode;
782 }
783
784 /* Success, at least so far, advance our state engine. */
785 hp->timer_state = lupwait;
786 restart_timer = 1;
787 } else {
788 restart_timer = 1;
789 }
790 }
791 break;
792
793 case lupwait:
794 /* Auto negotiation was successful and we are awaiting a
795 * link up status. I have decided to let this timer run
796 * forever until some sort of error is signalled, reporting
797 * a message to the user at 10 second intervals.
798 */
799 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
800 if (hp->sw_bmsr & BMSR_LSTATUS) {
801 /* Wheee, it's up, display the link mode in use and put
802 * the timer to sleep.
803 */
804 display_link_mode(hp, tregs);
805 hp->timer_state = asleep;
806 restart_timer = 0;
807 } else {
808 if (hp->timer_ticks >= 10) {
809 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
810 "not completely up.\n", hp->dev->name);
811 hp->timer_ticks = 0;
812 restart_timer = 1;
813 } else {
814 restart_timer = 1;
815 }
816 }
817 break;
818
819 case ltrywait:
820 /* Making the timeout here too long can make it take
821 * annoyingly long to attempt all of the link mode
822 * permutations, but then again this is essentially
823 * error recovery code for the most part.
824 */
825 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
826 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
827 if (hp->timer_ticks == 1) {
828 if (!is_lucent_phy(hp)) {
829 /* Re-enable transceiver, we'll re-enable the transceiver next
830 * tick, then check link state on the following tick.
831 */
832 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
833 happy_meal_tcvr_write(hp, tregs,
834 DP83840_CSCONFIG, hp->sw_csconfig);
835 }
836 restart_timer = 1;
837 break;
838 }
839 if (hp->timer_ticks == 2) {
840 if (!is_lucent_phy(hp)) {
841 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
842 happy_meal_tcvr_write(hp, tregs,
843 DP83840_CSCONFIG, hp->sw_csconfig);
844 }
845 restart_timer = 1;
846 break;
847 }
848 if (hp->sw_bmsr & BMSR_LSTATUS) {
849 /* Force mode selection success. */
850 display_forced_link_mode(hp, tregs);
851 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
852 hp->timer_state = asleep;
853 restart_timer = 0;
854 } else {
855 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
856 int ret;
857
858 ret = try_next_permutation(hp, tregs);
859 if (ret == -1) {
860 /* Aieee, tried them all, reset the
861 * chip and try all over again.
862 */
863
864 /* Let the user know... */
865 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
866 hp->dev->name);
867
868 ret = happy_meal_init(hp);
869 if (ret) {
870 /* ho hum... */
871 printk(KERN_ERR "%s: Error, cannot re-init the "
872 "Happy Meal.\n", hp->dev->name);
873 }
874 goto out;
875 }
876 if (!is_lucent_phy(hp)) {
877 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
878 DP83840_CSCONFIG);
879 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
880 happy_meal_tcvr_write(hp, tregs,
881 DP83840_CSCONFIG, hp->sw_csconfig);
882 }
883 hp->timer_ticks = 0;
884 restart_timer = 1;
885 } else {
886 restart_timer = 1;
887 }
888 }
889 break;
890
891 case asleep:
892 default:
893 /* Can't happens.... */
894 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
895 hp->dev->name);
896 restart_timer = 0;
897 hp->timer_ticks = 0;
898 hp->timer_state = asleep; /* foo on you */
899 break;
900 };
901
902 if (restart_timer) {
903 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
904 add_timer(&hp->happy_timer);
905 }
906
907out:
908 spin_unlock_irq(&hp->happy_lock);
909}
910
911#define TX_RESET_TRIES 32
912#define RX_RESET_TRIES 32
913
914/* hp->happy_lock must be held */
915static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
916{
917 int tries = TX_RESET_TRIES;
918
919 HMD(("happy_meal_tx_reset: reset, "));
920
921 /* Would you like to try our SMCC Delux? */
922 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
923 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
924 udelay(20);
925
926 /* Lettuce, tomato, buggy hardware (no extra charge)? */
927 if (!tries)
928 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
929
930 /* Take care. */
931 HMD(("done\n"));
932}
933
934/* hp->happy_lock must be held */
935static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
936{
937 int tries = RX_RESET_TRIES;
938
939 HMD(("happy_meal_rx_reset: reset, "));
940
941 /* We have a special on GNU/Viking hardware bugs today. */
942 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
943 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
944 udelay(20);
945
946 /* Will that be all? */
947 if (!tries)
948 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
949
950 /* Don't forget your vik_1137125_wa. Have a nice day. */
951 HMD(("done\n"));
952}
953
954#define STOP_TRIES 16
955
956/* hp->happy_lock must be held */
957static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
958{
959 int tries = STOP_TRIES;
960
961 HMD(("happy_meal_stop: reset, "));
962
963 /* We're consolidating our STB products, it's your lucky day. */
964 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
965 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
966 udelay(20);
967
968 /* Come back next week when we are "Sun Microelectronics". */
969 if (!tries)
970 printk(KERN_ERR "happy meal: Fry guys.");
971
972 /* Remember: "Different name, same old buggy as shit hardware." */
973 HMD(("done\n"));
974}
975
976/* hp->happy_lock must be held */
977static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
978{
979 struct net_device_stats *stats = &hp->net_stats;
980
981 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
982 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
983
984 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
985 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
986
987 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
988 hme_write32(hp, bregs + BMAC_GLECTR, 0);
989
990 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
991
992 stats->collisions +=
993 (hme_read32(hp, bregs + BMAC_EXCTR) +
994 hme_read32(hp, bregs + BMAC_LTCTR));
995 hme_write32(hp, bregs + BMAC_EXCTR, 0);
996 hme_write32(hp, bregs + BMAC_LTCTR, 0);
997}
998
999/* hp->happy_lock must be held */
1000static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
1001{
1002 ASD(("happy_meal_poll_stop: "));
1003
1004 /* If polling disabled or not polling already, nothing to do. */
1005 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
1006 (HFLAG_POLLENABLE | HFLAG_POLL)) {
1007 HMD(("not polling, return\n"));
1008 return;
1009 }
1010
1011 /* Shut up the MIF. */
1012 ASD(("were polling, mif ints off, "));
1013 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1014
1015 /* Turn off polling. */
1016 ASD(("polling off, "));
1017 hme_write32(hp, tregs + TCVR_CFG,
1018 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
1019
1020 /* We are no longer polling. */
1021 hp->happy_flags &= ~(HFLAG_POLL);
1022
1023 /* Let the bits set. */
1024 udelay(200);
1025 ASD(("done\n"));
1026}
1027
1028/* Only Sun can take such nice parts and fuck up the programming interface
1029 * like this. Good job guys...
1030 */
1031#define TCVR_RESET_TRIES 16 /* It should reset quickly */
1032#define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
1033
1034/* hp->happy_lock must be held */
1035static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
1036{
1037 u32 tconfig;
1038 int result, tries = TCVR_RESET_TRIES;
1039
1040 tconfig = hme_read32(hp, tregs + TCVR_CFG);
1041 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1042 if (hp->tcvr_type == external) {
1043 ASD(("external<"));
1044 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1045 hp->tcvr_type = internal;
1046 hp->paddr = TCV_PADDR_ITX;
1047 ASD(("ISOLATE,"));
1048 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1049 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1050 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1051 if (result == TCVR_FAILURE) {
1052 ASD(("phyread_fail>\n"));
1053 return -1;
1054 }
1055 ASD(("phyread_ok,PSELECT>"));
1056 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1057 hp->tcvr_type = external;
1058 hp->paddr = TCV_PADDR_ETX;
1059 } else {
1060 if (tconfig & TCV_CFG_MDIO1) {
1061 ASD(("internal<PSELECT,"));
1062 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1063 ASD(("ISOLATE,"));
1064 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1065 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1066 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1067 if (result == TCVR_FAILURE) {
1068 ASD(("phyread_fail>\n"));
1069 return -1;
1070 }
1071 ASD(("phyread_ok,~PSELECT>"));
1072 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1073 hp->tcvr_type = internal;
1074 hp->paddr = TCV_PADDR_ITX;
1075 }
1076 }
1077
1078 ASD(("BMCR_RESET "));
1079 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1080
1081 while (--tries) {
1082 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1083 if (result == TCVR_FAILURE)
1084 return -1;
1085 hp->sw_bmcr = result;
1086 if (!(result & BMCR_RESET))
1087 break;
1088 udelay(20);
1089 }
1090 if (!tries) {
1091 ASD(("BMCR RESET FAILED!\n"));
1092 return -1;
1093 }
1094 ASD(("RESET_OK\n"));
1095
1096 /* Get fresh copies of the PHY registers. */
1097 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1098 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1099 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1100 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1101
1102 ASD(("UNISOLATE"));
1103 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1104 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1105
1106 tries = TCVR_UNISOLATE_TRIES;
1107 while (--tries) {
1108 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1109 if (result == TCVR_FAILURE)
1110 return -1;
1111 if (!(result & BMCR_ISOLATE))
1112 break;
1113 udelay(20);
1114 }
1115 if (!tries) {
1116 ASD((" FAILED!\n"));
1117 return -1;
1118 }
1119 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1120 if (!is_lucent_phy(hp)) {
1121 result = happy_meal_tcvr_read(hp, tregs,
1122 DP83840_CSCONFIG);
1123 happy_meal_tcvr_write(hp, tregs,
1124 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1125 }
1126 return 0;
1127}
1128
1129/* Figure out whether we have an internal or external transceiver.
1130 *
1131 * hp->happy_lock must be held
1132 */
1133static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1134{
1135 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1136
1137 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1138 if (hp->happy_flags & HFLAG_POLL) {
1139 /* If we are polling, we must stop to get the transceiver type. */
1140 ASD(("<polling> "));
1141 if (hp->tcvr_type == internal) {
1142 if (tconfig & TCV_CFG_MDIO1) {
1143 ASD(("<internal> <poll stop> "));
1144 happy_meal_poll_stop(hp, tregs);
1145 hp->paddr = TCV_PADDR_ETX;
1146 hp->tcvr_type = external;
1147 ASD(("<external>\n"));
1148 tconfig &= ~(TCV_CFG_PENABLE);
1149 tconfig |= TCV_CFG_PSELECT;
1150 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1151 }
1152 } else {
1153 if (hp->tcvr_type == external) {
1154 ASD(("<external> "));
1155 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1156 ASD(("<poll stop> "));
1157 happy_meal_poll_stop(hp, tregs);
1158 hp->paddr = TCV_PADDR_ITX;
1159 hp->tcvr_type = internal;
1160 ASD(("<internal>\n"));
1161 hme_write32(hp, tregs + TCVR_CFG,
1162 hme_read32(hp, tregs + TCVR_CFG) &
1163 ~(TCV_CFG_PSELECT));
1164 }
1165 ASD(("\n"));
1166 } else {
1167 ASD(("<none>\n"));
1168 }
1169 }
1170 } else {
1171 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1172
1173 /* Else we can just work off of the MDIO bits. */
1174 ASD(("<not polling> "));
1175 if (reread & TCV_CFG_MDIO1) {
1176 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1177 hp->paddr = TCV_PADDR_ETX;
1178 hp->tcvr_type = external;
1179 ASD(("<external>\n"));
1180 } else {
1181 if (reread & TCV_CFG_MDIO0) {
1182 hme_write32(hp, tregs + TCVR_CFG,
1183 tconfig & ~(TCV_CFG_PSELECT));
1184 hp->paddr = TCV_PADDR_ITX;
1185 hp->tcvr_type = internal;
1186 ASD(("<internal>\n"));
1187 } else {
1188 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1189 hp->tcvr_type = none; /* Grrr... */
1190 ASD(("<none>\n"));
1191 }
1192 }
1193 }
1194}
1195
1196/* The receive ring buffers are a bit tricky to get right. Here goes...
1197 *
1198 * The buffers we dma into must be 64 byte aligned. So we use a special
1199 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1200 * we really need.
1201 *
1202 * We use skb_reserve() to align the data block we get in the skb. We
1203 * also program the etxregs->cfg register to use an offset of 2. This
1204 * imperical constant plus the ethernet header size will always leave
1205 * us with a nicely aligned ip header once we pass things up to the
1206 * protocol layers.
1207 *
1208 * The numbers work out to:
1209 *
1210 * Max ethernet frame size 1518
1211 * Ethernet header size 14
1212 * Happy Meal base offset 2
1213 *
1214 * Say a skb data area is at 0xf001b010, and its size alloced is
1215 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1216 *
1217 * First our alloc_skb() routine aligns the data base to a 64 byte
1218 * boundary. We now have 0xf001b040 as our skb data address. We
1219 * plug this into the receive descriptor address.
1220 *
1221 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1222 * So now the data we will end up looking at starts at 0xf001b042. When
1223 * the packet arrives, we will check out the size received and subtract
1224 * this from the skb->length. Then we just pass the packet up to the
1225 * protocols as is, and allocate a new skb to replace this slot we have
1226 * just received from.
1227 *
1228 * The ethernet layer will strip the ether header from the front of the
1229 * skb we just sent to it, this leaves us with the ip header sitting
1230 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1231 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1232 * bit checksum is obtained from the low bits of the receive descriptor
1233 * flags, thus:
1234 *
1235 * skb->csum = rxd->rx_flags & 0xffff;
1236 * skb->ip_summed = CHECKSUM_HW;
1237 *
1238 * before sending off the skb to the protocols, and we are good as gold.
1239 */
1240static void happy_meal_clean_rings(struct happy_meal *hp)
1241{
1242 int i;
1243
1244 for (i = 0; i < RX_RING_SIZE; i++) {
1245 if (hp->rx_skbs[i] != NULL) {
1246 struct sk_buff *skb = hp->rx_skbs[i];
1247 struct happy_meal_rxd *rxd;
1248 u32 dma_addr;
1249
1250 rxd = &hp->happy_block->happy_meal_rxd[i];
1251 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1252 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1253 dev_kfree_skb_any(skb);
1254 hp->rx_skbs[i] = NULL;
1255 }
1256 }
1257
1258 for (i = 0; i < TX_RING_SIZE; i++) {
1259 if (hp->tx_skbs[i] != NULL) {
1260 struct sk_buff *skb = hp->tx_skbs[i];
1261 struct happy_meal_txd *txd;
1262 u32 dma_addr;
1263 int frag;
1264
1265 hp->tx_skbs[i] = NULL;
1266
1267 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1268 txd = &hp->happy_block->happy_meal_txd[i];
1269 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1270 hme_dma_unmap(hp, dma_addr,
1271 (hme_read_desc32(hp, &txd->tx_flags)
1272 & TXFLAG_SIZE),
1273 DMA_TODEVICE);
1274
1275 if (frag != skb_shinfo(skb)->nr_frags)
1276 i++;
1277 }
1278
1279 dev_kfree_skb_any(skb);
1280 }
1281 }
1282}
1283
1284/* hp->happy_lock must be held */
1285static void happy_meal_init_rings(struct happy_meal *hp)
1286{
1287 struct hmeal_init_block *hb = hp->happy_block;
1288 struct net_device *dev = hp->dev;
1289 int i;
1290
1291 HMD(("happy_meal_init_rings: counters to zero, "));
1292 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1293
1294 /* Free any skippy bufs left around in the rings. */
1295 HMD(("clean, "));
1296 happy_meal_clean_rings(hp);
1297
1298 /* Now get new skippy bufs for the receive ring. */
1299 HMD(("init rxring, "));
1300 for (i = 0; i < RX_RING_SIZE; i++) {
1301 struct sk_buff *skb;
1302
1303 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1304 if (!skb) {
1305 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1306 continue;
1307 }
1308 hp->rx_skbs[i] = skb;
1309 skb->dev = dev;
1310
1311 /* Because we reserve afterwards. */
1312 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1313 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1314 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1315 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1316 skb_reserve(skb, RX_OFFSET);
1317 }
1318
1319 HMD(("init txring, "));
1320 for (i = 0; i < TX_RING_SIZE; i++)
1321 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1322
1323 HMD(("done\n"));
1324}
1325
1326/* hp->happy_lock must be held */
1327static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1328 void __iomem *tregs,
1329 struct ethtool_cmd *ep)
1330{
1331 int timeout;
1332
1333 /* Read all of the registers we are interested in now. */
1334 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1335 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1336 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1337 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1338
1339 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1340
1341 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1342 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1343 /* Advertise everything we can support. */
1344 if (hp->sw_bmsr & BMSR_10HALF)
1345 hp->sw_advertise |= (ADVERTISE_10HALF);
1346 else
1347 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1348
1349 if (hp->sw_bmsr & BMSR_10FULL)
1350 hp->sw_advertise |= (ADVERTISE_10FULL);
1351 else
1352 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1353 if (hp->sw_bmsr & BMSR_100HALF)
1354 hp->sw_advertise |= (ADVERTISE_100HALF);
1355 else
1356 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1357 if (hp->sw_bmsr & BMSR_100FULL)
1358 hp->sw_advertise |= (ADVERTISE_100FULL);
1359 else
1360 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1361 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1362
1363 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1364 * XXX and this is because the DP83840 does not support it, changes
1365 * XXX would need to be made to the tx/rx logic in the driver as well
1366 * XXX so I completely skip checking for it in the BMSR for now.
1367 */
1368
1369#ifdef AUTO_SWITCH_DEBUG
1370 ASD(("%s: Advertising [ ", hp->dev->name));
1371 if (hp->sw_advertise & ADVERTISE_10HALF)
1372 ASD(("10H "));
1373 if (hp->sw_advertise & ADVERTISE_10FULL)
1374 ASD(("10F "));
1375 if (hp->sw_advertise & ADVERTISE_100HALF)
1376 ASD(("100H "));
1377 if (hp->sw_advertise & ADVERTISE_100FULL)
1378 ASD(("100F "));
1379#endif
1380
1381 /* Enable Auto-Negotiation, this is usually on already... */
1382 hp->sw_bmcr |= BMCR_ANENABLE;
1383 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1384
1385 /* Restart it to make sure it is going. */
1386 hp->sw_bmcr |= BMCR_ANRESTART;
1387 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1388
1389 /* BMCR_ANRESTART self clears when the process has begun. */
1390
1391 timeout = 64; /* More than enough. */
1392 while (--timeout) {
1393 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1394 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1395 break; /* got it. */
1396 udelay(10);
1397 }
1398 if (!timeout) {
1399 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1400 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1401 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1402 hp->dev->name);
1403 goto force_link;
1404 } else {
1405 hp->timer_state = arbwait;
1406 }
1407 } else {
1408force_link:
1409 /* Force the link up, trying first a particular mode.
1410 * Either we are here at the request of ethtool or
1411 * because the Happy Meal would not start to autoneg.
1412 */
1413
1414 /* Disable auto-negotiation in BMCR, enable the duplex and
1415 * speed setting, init the timer state machine, and fire it off.
1416 */
1417 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1418 hp->sw_bmcr = BMCR_SPEED100;
1419 } else {
1420 if (ep->speed == SPEED_100)
1421 hp->sw_bmcr = BMCR_SPEED100;
1422 else
1423 hp->sw_bmcr = 0;
1424 if (ep->duplex == DUPLEX_FULL)
1425 hp->sw_bmcr |= BMCR_FULLDPLX;
1426 }
1427 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1428
1429 if (!is_lucent_phy(hp)) {
1430 /* OK, seems we need do disable the transceiver for the first
1431 * tick to make sure we get an accurate link state at the
1432 * second tick.
1433 */
1434 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1435 DP83840_CSCONFIG);
1436 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1437 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1438 hp->sw_csconfig);
1439 }
1440 hp->timer_state = ltrywait;
1441 }
1442
1443 hp->timer_ticks = 0;
1444 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1445 hp->happy_timer.data = (unsigned long) hp;
1446 hp->happy_timer.function = &happy_meal_timer;
1447 add_timer(&hp->happy_timer);
1448}
1449
1450/* hp->happy_lock must be held */
1451static int happy_meal_init(struct happy_meal *hp)
1452{
1453 void __iomem *gregs = hp->gregs;
1454 void __iomem *etxregs = hp->etxregs;
1455 void __iomem *erxregs = hp->erxregs;
1456 void __iomem *bregs = hp->bigmacregs;
1457 void __iomem *tregs = hp->tcvregs;
1458 u32 regtmp, rxcfg;
1459 unsigned char *e = &hp->dev->dev_addr[0];
1460
1461 /* If auto-negotiation timer is running, kill it. */
1462 del_timer(&hp->happy_timer);
1463
1464 HMD(("happy_meal_init: happy_flags[%08x] ",
1465 hp->happy_flags));
1466 if (!(hp->happy_flags & HFLAG_INIT)) {
1467 HMD(("set HFLAG_INIT, "));
1468 hp->happy_flags |= HFLAG_INIT;
1469 happy_meal_get_counters(hp, bregs);
1470 }
1471
1472 /* Stop polling. */
1473 HMD(("to happy_meal_poll_stop\n"));
1474 happy_meal_poll_stop(hp, tregs);
1475
1476 /* Stop transmitter and receiver. */
1477 HMD(("happy_meal_init: to happy_meal_stop\n"));
1478 happy_meal_stop(hp, gregs);
1479
1480 /* Alloc and reset the tx/rx descriptor chains. */
1481 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1482 happy_meal_init_rings(hp);
1483
1484 /* Shut up the MIF. */
1485 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1486 hme_read32(hp, tregs + TCVR_IMASK)));
1487 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1488
1489 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1490 if (hp->happy_flags & HFLAG_FENABLE) {
1491 HMD(("use frame old[%08x], ",
1492 hme_read32(hp, tregs + TCVR_CFG)));
1493 hme_write32(hp, tregs + TCVR_CFG,
1494 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1495 } else {
1496 HMD(("use bitbang old[%08x], ",
1497 hme_read32(hp, tregs + TCVR_CFG)));
1498 hme_write32(hp, tregs + TCVR_CFG,
1499 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1500 }
1501
1502 /* Check the state of the transceiver. */
1503 HMD(("to happy_meal_transceiver_check\n"));
1504 happy_meal_transceiver_check(hp, tregs);
1505
1506 /* Put the Big Mac into a sane state. */
1507 HMD(("happy_meal_init: "));
1508 switch(hp->tcvr_type) {
1509 case none:
1510 /* Cannot operate if we don't know the transceiver type! */
1511 HMD(("AAIEEE no transceiver type, EAGAIN"));
1512 return -EAGAIN;
1513
1514 case internal:
1515 /* Using the MII buffers. */
1516 HMD(("internal, using MII, "));
1517 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1518 break;
1519
1520 case external:
1521 /* Not using the MII, disable it. */
1522 HMD(("external, disable MII, "));
1523 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1524 break;
1525 };
1526
1527 if (happy_meal_tcvr_reset(hp, tregs))
1528 return -EAGAIN;
1529
1530 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1531 HMD(("tx/rx reset, "));
1532 happy_meal_tx_reset(hp, bregs);
1533 happy_meal_rx_reset(hp, bregs);
1534
1535 /* Set jam size and inter-packet gaps to reasonable defaults. */
1536 HMD(("jsize/ipg1/ipg2, "));
1537 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1538 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1539 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1540
1541 /* Load up the MAC address and random seed. */
1542 HMD(("rseed/macaddr, "));
1543
1544 /* The docs recommend to use the 10LSB of our MAC here. */
1545 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1546
1547 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1548 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1549 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1550
1551 HMD(("htable, "));
1552 if ((hp->dev->flags & IFF_ALLMULTI) ||
1553 (hp->dev->mc_count > 64)) {
1554 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1555 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1556 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1557 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1558 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1559 u16 hash_table[4];
1560 struct dev_mc_list *dmi = hp->dev->mc_list;
1561 char *addrs;
1562 int i;
1563 u32 crc;
1564
1565 for (i = 0; i < 4; i++)
1566 hash_table[i] = 0;
1567
1568 for (i = 0; i < hp->dev->mc_count; i++) {
1569 addrs = dmi->dmi_addr;
1570 dmi = dmi->next;
1571
1572 if (!(*addrs & 1))
1573 continue;
1574
1575 crc = ether_crc_le(6, addrs);
1576 crc >>= 26;
1577 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1578 }
1579 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1580 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1581 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1582 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1583 } else {
1584 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1585 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1586 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1587 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1588 }
1589
1590 /* Set the RX and TX ring ptrs. */
1591 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1592 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1593 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1594 hme_write32(hp, erxregs + ERX_RING,
1595 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1596 hme_write32(hp, etxregs + ETX_RING,
1597 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1598
1599 /* Parity issues in the ERX unit of some HME revisions can cause some
1600 * registers to not be written unless their parity is even. Detect such
1601 * lost writes and simply rewrite with a low bit set (which will be ignored
1602 * since the rxring needs to be 2K aligned).
1603 */
1604 if (hme_read32(hp, erxregs + ERX_RING) !=
1605 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1606 hme_write32(hp, erxregs + ERX_RING,
1607 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1608 | 0x4);
1609
1610 /* Set the supported burst sizes. */
1611 HMD(("happy_meal_init: old[%08x] bursts<",
1612 hme_read32(hp, gregs + GREG_CFG)));
1613
1614#ifndef __sparc__
1615 /* It is always PCI and can handle 64byte bursts. */
1616 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1617#else
1618 if ((hp->happy_bursts & DMA_BURST64) &&
1619 ((hp->happy_flags & HFLAG_PCI) != 0
1620#ifdef CONFIG_SBUS
1621 || sbus_can_burst64(hp->happy_dev)
1622#endif
1623 || 0)) {
1624 u32 gcfg = GREG_CFG_BURST64;
1625
1626 /* I have no idea if I should set the extended
1627 * transfer mode bit for Cheerio, so for now I
1628 * do not. -DaveM
1629 */
1630#ifdef CONFIG_SBUS
1631 if ((hp->happy_flags & HFLAG_PCI) == 0 &&
1632 sbus_can_dma_64bit(hp->happy_dev)) {
1633 sbus_set_sbus64(hp->happy_dev,
1634 hp->happy_bursts);
1635 gcfg |= GREG_CFG_64BIT;
1636 }
1637#endif
1638
1639 HMD(("64>"));
1640 hme_write32(hp, gregs + GREG_CFG, gcfg);
1641 } else if (hp->happy_bursts & DMA_BURST32) {
1642 HMD(("32>"));
1643 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1644 } else if (hp->happy_bursts & DMA_BURST16) {
1645 HMD(("16>"));
1646 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1647 } else {
1648 HMD(("XXX>"));
1649 hme_write32(hp, gregs + GREG_CFG, 0);
1650 }
1651#endif /* __sparc__ */
1652
1653 /* Turn off interrupts we do not want to hear. */
1654 HMD((", enable global interrupts, "));
1655 hme_write32(hp, gregs + GREG_IMASK,
1656 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1657 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1658
1659 /* Set the transmit ring buffer size. */
1660 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1661 hme_read32(hp, etxregs + ETX_RSIZE)));
1662 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1663
1664 /* Enable transmitter DVMA. */
1665 HMD(("tx dma enable old[%08x], ",
1666 hme_read32(hp, etxregs + ETX_CFG)));
1667 hme_write32(hp, etxregs + ETX_CFG,
1668 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1669
1670 /* This chip really rots, for the receiver sometimes when you
1671 * write to its control registers not all the bits get there
1672 * properly. I cannot think of a sane way to provide complete
1673 * coverage for this hardware bug yet.
1674 */
1675 HMD(("erx regs bug old[%08x]\n",
1676 hme_read32(hp, erxregs + ERX_CFG)));
1677 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1678 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1679 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1680 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1681 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1682 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1683 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1684 /* XXX Should return failure here... */
1685 }
1686
1687 /* Enable Big Mac hash table filter. */
1688 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1689 hme_read32(hp, bregs + BMAC_RXCFG)));
1690 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1691 if (hp->dev->flags & IFF_PROMISC)
1692 rxcfg |= BIGMAC_RXCFG_PMISC;
1693 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1694
1695 /* Let the bits settle in the chip. */
1696 udelay(10);
1697
1698 /* Ok, configure the Big Mac transmitter. */
1699 HMD(("BIGMAC init, "));
1700 regtmp = 0;
1701 if (hp->happy_flags & HFLAG_FULL)
1702 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1703
1704 /* Don't turn on the "don't give up" bit for now. It could cause hme
1705 * to deadlock with the PHY if a Jabber occurs.
1706 */
1707 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1708
1709 /* Give up after 16 TX attempts. */
1710 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1711
1712 /* Enable the output drivers no matter what. */
1713 regtmp = BIGMAC_XCFG_ODENABLE;
1714
1715 /* If card can do lance mode, enable it. */
1716 if (hp->happy_flags & HFLAG_LANCE)
1717 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1718
1719 /* Disable the MII buffers if using external transceiver. */
1720 if (hp->tcvr_type == external)
1721 regtmp |= BIGMAC_XCFG_MIIDISAB;
1722
1723 HMD(("XIF config old[%08x], ",
1724 hme_read32(hp, bregs + BMAC_XIFCFG)));
1725 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1726
1727 /* Start things up. */
1728 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1729 hme_read32(hp, bregs + BMAC_TXCFG),
1730 hme_read32(hp, bregs + BMAC_RXCFG)));
1731 hme_write32(hp, bregs + BMAC_TXCFG,
1732 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1733 hme_write32(hp, bregs + BMAC_RXCFG,
1734 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1735
1736 /* Get the autonegotiation started, and the watch timer ticking. */
1737 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1738
1739 /* Success. */
1740 return 0;
1741}
1742
1743/* hp->happy_lock must be held */
1744static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1745{
1746 void __iomem *tregs = hp->tcvregs;
1747 void __iomem *bregs = hp->bigmacregs;
1748 void __iomem *gregs = hp->gregs;
1749
1750 happy_meal_stop(hp, gregs);
1751 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1752 if (hp->happy_flags & HFLAG_FENABLE)
1753 hme_write32(hp, tregs + TCVR_CFG,
1754 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1755 else
1756 hme_write32(hp, tregs + TCVR_CFG,
1757 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1758 happy_meal_transceiver_check(hp, tregs);
1759 switch(hp->tcvr_type) {
1760 case none:
1761 return;
1762 case internal:
1763 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1764 break;
1765 case external:
1766 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1767 break;
1768 };
1769 if (happy_meal_tcvr_reset(hp, tregs))
1770 return;
1771
1772 /* Latch PHY registers as of now. */
1773 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1774 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1775
1776 /* Advertise everything we can support. */
1777 if (hp->sw_bmsr & BMSR_10HALF)
1778 hp->sw_advertise |= (ADVERTISE_10HALF);
1779 else
1780 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1781
1782 if (hp->sw_bmsr & BMSR_10FULL)
1783 hp->sw_advertise |= (ADVERTISE_10FULL);
1784 else
1785 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1786 if (hp->sw_bmsr & BMSR_100HALF)
1787 hp->sw_advertise |= (ADVERTISE_100HALF);
1788 else
1789 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1790 if (hp->sw_bmsr & BMSR_100FULL)
1791 hp->sw_advertise |= (ADVERTISE_100FULL);
1792 else
1793 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1794
1795 /* Update the PHY advertisement register. */
1796 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1797}
1798
1799/* Once status is latched (by happy_meal_interrupt) it is cleared by
1800 * the hardware, so we cannot re-read it and get a correct value.
1801 *
1802 * hp->happy_lock must be held
1803 */
1804static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1805{
1806 int reset = 0;
1807
1808 /* Only print messages for non-counter related interrupts. */
1809 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1810 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1811 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1812 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1813 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1814 GREG_STAT_SLVPERR))
1815 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1816 hp->dev->name, status);
1817
1818 if (status & GREG_STAT_RFIFOVF) {
1819 /* Receive FIFO overflow is harmless and the hardware will take
1820 care of it, just some packets are lost. Who cares. */
1821 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1822 }
1823
1824 if (status & GREG_STAT_STSTERR) {
1825 /* BigMAC SQE link test failed. */
1826 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1827 reset = 1;
1828 }
1829
1830 if (status & GREG_STAT_TFIFO_UND) {
1831 /* Transmit FIFO underrun, again DMA error likely. */
1832 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1833 hp->dev->name);
1834 reset = 1;
1835 }
1836
1837 if (status & GREG_STAT_MAXPKTERR) {
1838 /* Driver error, tried to transmit something larger
1839 * than ethernet max mtu.
1840 */
1841 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1842 reset = 1;
1843 }
1844
1845 if (status & GREG_STAT_NORXD) {
1846 /* This is harmless, it just means the system is
1847 * quite loaded and the incoming packet rate was
1848 * faster than the interrupt handler could keep up
1849 * with.
1850 */
1851 printk(KERN_INFO "%s: Happy Meal out of receive "
1852 "descriptors, packet dropped.\n",
1853 hp->dev->name);
1854 }
1855
1856 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1857 /* All sorts of DMA receive errors. */
1858 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1859 if (status & GREG_STAT_RXERR)
1860 printk("GenericError ");
1861 if (status & GREG_STAT_RXPERR)
1862 printk("ParityError ");
1863 if (status & GREG_STAT_RXTERR)
1864 printk("RxTagBotch ");
1865 printk("]\n");
1866 reset = 1;
1867 }
1868
1869 if (status & GREG_STAT_EOPERR) {
1870 /* Driver bug, didn't set EOP bit in tx descriptor given
1871 * to the happy meal.
1872 */
1873 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1874 hp->dev->name);
1875 reset = 1;
1876 }
1877
1878 if (status & GREG_STAT_MIFIRQ) {
1879 /* MIF signalled an interrupt, were we polling it? */
1880 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1881 }
1882
1883 if (status &
1884 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1885 /* All sorts of transmit DMA errors. */
1886 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1887 if (status & GREG_STAT_TXEACK)
1888 printk("GenericError ");
1889 if (status & GREG_STAT_TXLERR)
1890 printk("LateError ");
1891 if (status & GREG_STAT_TXPERR)
1892 printk("ParityErro ");
1893 if (status & GREG_STAT_TXTERR)
1894 printk("TagBotch ");
1895 printk("]\n");
1896 reset = 1;
1897 }
1898
1899 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1900 /* Bus or parity error when cpu accessed happy meal registers
1901 * or it's internal FIFO's. Should never see this.
1902 */
1903 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1904 hp->dev->name,
1905 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1906 reset = 1;
1907 }
1908
1909 if (reset) {
1910 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1911 happy_meal_init(hp);
1912 return 1;
1913 }
1914 return 0;
1915}
1916
1917/* hp->happy_lock must be held */
1918static void happy_meal_mif_interrupt(struct happy_meal *hp)
1919{
1920 void __iomem *tregs = hp->tcvregs;
1921
1922 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1923 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1924 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1925
1926 /* Use the fastest transmission protocol possible. */
1927 if (hp->sw_lpa & LPA_100FULL) {
1928 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1929 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1930 } else if (hp->sw_lpa & LPA_100HALF) {
1931 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1932 hp->sw_bmcr |= BMCR_SPEED100;
1933 } else if (hp->sw_lpa & LPA_10FULL) {
1934 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1935 hp->sw_bmcr |= BMCR_FULLDPLX;
1936 } else {
1937 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1938 }
1939 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1940
1941 /* Finally stop polling and shut up the MIF. */
1942 happy_meal_poll_stop(hp, tregs);
1943}
1944
1945#ifdef TXDEBUG
1946#define TXD(x) printk x
1947#else
1948#define TXD(x)
1949#endif
1950
1951/* hp->happy_lock must be held */
1952static void happy_meal_tx(struct happy_meal *hp)
1953{
1954 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1955 struct happy_meal_txd *this;
1956 struct net_device *dev = hp->dev;
1957 int elem;
1958
1959 elem = hp->tx_old;
1960 TXD(("TX<"));
1961 while (elem != hp->tx_new) {
1962 struct sk_buff *skb;
1963 u32 flags, dma_addr, dma_len;
1964 int frag;
1965
1966 TXD(("[%d]", elem));
1967 this = &txbase[elem];
1968 flags = hme_read_desc32(hp, &this->tx_flags);
1969 if (flags & TXFLAG_OWN)
1970 break;
1971 skb = hp->tx_skbs[elem];
1972 if (skb_shinfo(skb)->nr_frags) {
1973 int last;
1974
1975 last = elem + skb_shinfo(skb)->nr_frags;
1976 last &= (TX_RING_SIZE - 1);
1977 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1978 if (flags & TXFLAG_OWN)
1979 break;
1980 }
1981 hp->tx_skbs[elem] = NULL;
1982 hp->net_stats.tx_bytes += skb->len;
1983
1984 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1985 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1986 dma_len = hme_read_desc32(hp, &this->tx_flags);
1987
1988 dma_len &= TXFLAG_SIZE;
1989 hme_dma_unmap(hp, dma_addr, dma_len, DMA_TODEVICE);
1990
1991 elem = NEXT_TX(elem);
1992 this = &txbase[elem];
1993 }
1994
1995 dev_kfree_skb_irq(skb);
1996 hp->net_stats.tx_packets++;
1997 }
1998 hp->tx_old = elem;
1999 TXD((">"));
2000
2001 if (netif_queue_stopped(dev) &&
2002 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
2003 netif_wake_queue(dev);
2004}
2005
2006#ifdef RXDEBUG
2007#define RXD(x) printk x
2008#else
2009#define RXD(x)
2010#endif
2011
2012/* Originally I used to handle the allocation failure by just giving back just
2013 * that one ring buffer to the happy meal. Problem is that usually when that
2014 * condition is triggered, the happy meal expects you to do something reasonable
2015 * with all of the packets it has DMA'd in. So now I just drop the entire
2016 * ring when we cannot get a new skb and give them all back to the happy meal,
2017 * maybe things will be "happier" now.
2018 *
2019 * hp->happy_lock must be held
2020 */
2021static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
2022{
2023 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
2024 struct happy_meal_rxd *this;
2025 int elem = hp->rx_new, drops = 0;
2026 u32 flags;
2027
2028 RXD(("RX<"));
2029 this = &rxbase[elem];
2030 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
2031 struct sk_buff *skb;
2032 int len = flags >> 16;
2033 u16 csum = flags & RXFLAG_CSUM;
2034 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2035
2036 RXD(("[%d ", elem));
2037
2038 /* Check for errors. */
2039 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2040 RXD(("ERR(%08x)]", flags));
2041 hp->net_stats.rx_errors++;
2042 if (len < ETH_ZLEN)
2043 hp->net_stats.rx_length_errors++;
2044 if (len & (RXFLAG_OVERFLOW >> 16)) {
2045 hp->net_stats.rx_over_errors++;
2046 hp->net_stats.rx_fifo_errors++;
2047 }
2048
2049 /* Return it to the Happy meal. */
2050 drop_it:
2051 hp->net_stats.rx_dropped++;
2052 hme_write_rxd(hp, this,
2053 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2054 dma_addr);
2055 goto next;
2056 }
2057 skb = hp->rx_skbs[elem];
2058 if (len > RX_COPY_THRESHOLD) {
2059 struct sk_buff *new_skb;
2060
2061 /* Now refill the entry, if we can. */
2062 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2063 if (new_skb == NULL) {
2064 drops++;
2065 goto drop_it;
2066 }
2067 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
2068 hp->rx_skbs[elem] = new_skb;
2069 new_skb->dev = dev;
2070 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
2071 hme_write_rxd(hp, this,
2072 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2073 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
2074 skb_reserve(new_skb, RX_OFFSET);
2075
2076 /* Trim the original skb for the netif. */
2077 skb_trim(skb, len);
2078 } else {
2079 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2080
2081 if (copy_skb == NULL) {
2082 drops++;
2083 goto drop_it;
2084 }
2085
2086 copy_skb->dev = dev;
2087 skb_reserve(copy_skb, 2);
2088 skb_put(copy_skb, len);
2089 hme_dma_sync_for_cpu(hp, dma_addr, len, DMA_FROMDEVICE);
2090 memcpy(copy_skb->data, skb->data, len);
2091 hme_dma_sync_for_device(hp, dma_addr, len, DMA_FROMDEVICE);
2092
2093 /* Reuse original ring buffer. */
2094 hme_write_rxd(hp, this,
2095 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2096 dma_addr);
2097
2098 skb = copy_skb;
2099 }
2100
2101 /* This card is _fucking_ hot... */
2102 skb->csum = ntohs(csum ^ 0xffff);
2103 skb->ip_summed = CHECKSUM_HW;
2104
2105 RXD(("len=%d csum=%4x]", len, csum));
2106 skb->protocol = eth_type_trans(skb, dev);
2107 netif_rx(skb);
2108
2109 dev->last_rx = jiffies;
2110 hp->net_stats.rx_packets++;
2111 hp->net_stats.rx_bytes += len;
2112 next:
2113 elem = NEXT_RX(elem);
2114 this = &rxbase[elem];
2115 }
2116 hp->rx_new = elem;
2117 if (drops)
2118 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2119 RXD((">"));
2120}
2121
2122static irqreturn_t happy_meal_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2123{
2124 struct net_device *dev = (struct net_device *) dev_id;
2125 struct happy_meal *hp = dev->priv;
2126 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2127
2128 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2129
2130 spin_lock(&hp->happy_lock);
2131
2132 if (happy_status & GREG_STAT_ERRORS) {
2133 HMD(("ERRORS "));
2134 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2135 goto out;
2136 }
2137
2138 if (happy_status & GREG_STAT_MIFIRQ) {
2139 HMD(("MIFIRQ "));
2140 happy_meal_mif_interrupt(hp);
2141 }
2142
2143 if (happy_status & GREG_STAT_TXALL) {
2144 HMD(("TXALL "));
2145 happy_meal_tx(hp);
2146 }
2147
2148 if (happy_status & GREG_STAT_RXTOHOST) {
2149 HMD(("RXTOHOST "));
2150 happy_meal_rx(hp, dev);
2151 }
2152
2153 HMD(("done\n"));
2154out:
2155 spin_unlock(&hp->happy_lock);
2156
2157 return IRQ_HANDLED;
2158}
2159
2160#ifdef CONFIG_SBUS
2161static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie, struct pt_regs *ptregs)
2162{
2163 struct quattro *qp = (struct quattro *) cookie;
2164 int i;
2165
2166 for (i = 0; i < 4; i++) {
2167 struct net_device *dev = qp->happy_meals[i];
2168 struct happy_meal *hp = dev->priv;
2169 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2170
2171 HMD(("quattro_interrupt: status=%08x ", happy_status));
2172
2173 if (!(happy_status & (GREG_STAT_ERRORS |
2174 GREG_STAT_MIFIRQ |
2175 GREG_STAT_TXALL |
2176 GREG_STAT_RXTOHOST)))
2177 continue;
2178
2179 spin_lock(&hp->happy_lock);
2180
2181 if (happy_status & GREG_STAT_ERRORS) {
2182 HMD(("ERRORS "));
2183 if (happy_meal_is_not_so_happy(hp, happy_status))
2184 goto next;
2185 }
2186
2187 if (happy_status & GREG_STAT_MIFIRQ) {
2188 HMD(("MIFIRQ "));
2189 happy_meal_mif_interrupt(hp);
2190 }
2191
2192 if (happy_status & GREG_STAT_TXALL) {
2193 HMD(("TXALL "));
2194 happy_meal_tx(hp);
2195 }
2196
2197 if (happy_status & GREG_STAT_RXTOHOST) {
2198 HMD(("RXTOHOST "));
2199 happy_meal_rx(hp, dev);
2200 }
2201
2202 next:
2203 spin_unlock(&hp->happy_lock);
2204 }
2205 HMD(("done\n"));
2206
2207 return IRQ_HANDLED;
2208}
2209#endif
2210
2211static int happy_meal_open(struct net_device *dev)
2212{
2213 struct happy_meal *hp = dev->priv;
2214 int res;
2215
2216 HMD(("happy_meal_open: "));
2217
2218 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2219 * into a single source which we register handling at probe time.
2220 */
2221 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2222 if (request_irq(dev->irq, &happy_meal_interrupt,
2223 SA_SHIRQ, dev->name, (void *)dev)) {
2224 HMD(("EAGAIN\n"));
1da177e4
LT		 2225 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2226 dev->irq);
1da177e4
LT		 2227
2228 return -EAGAIN;
2229 }
2230 }
2231
2232 HMD(("to happy_meal_init\n"));
2233
2234 spin_lock_irq(&hp->happy_lock);
2235 res = happy_meal_init(hp);
2236 spin_unlock_irq(&hp->happy_lock);
2237
2238 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2239 free_irq(dev->irq, dev);
2240 return res;
2241}
2242
2243static int happy_meal_close(struct net_device *dev)
2244{
2245 struct happy_meal *hp = dev->priv;
2246
2247 spin_lock_irq(&hp->happy_lock);
2248 happy_meal_stop(hp, hp->gregs);
2249 happy_meal_clean_rings(hp);
2250
2251 /* If auto-negotiation timer is running, kill it. */
2252 del_timer(&hp->happy_timer);
2253
2254 spin_unlock_irq(&hp->happy_lock);
2255
2256 /* On Quattro QFE cards, all hme interrupts are concentrated
2257 * into a single source which we register handling at probe
2258 * time and never unregister.
2259 */
2260 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2261 free_irq(dev->irq, dev);
2262
2263 return 0;
2264}
2265
2266#ifdef SXDEBUG
2267#define SXD(x) printk x
2268#else
2269#define SXD(x)
2270#endif
2271
2272static void happy_meal_tx_timeout(struct net_device *dev)
2273{
2274 struct happy_meal *hp = dev->priv;
2275
2276 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2277 tx_dump_log();
2278 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2279 hme_read32(hp, hp->gregs + GREG_STAT),
2280 hme_read32(hp, hp->etxregs + ETX_CFG),
2281 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2282
2283 spin_lock_irq(&hp->happy_lock);
2284 happy_meal_init(hp);
2285 spin_unlock_irq(&hp->happy_lock);
2286
2287 netif_wake_queue(dev);
2288}
2289
2290static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2291{
2292 struct happy_meal *hp = dev->priv;
2293 int entry;
2294 u32 tx_flags;
2295
2296 tx_flags = TXFLAG_OWN;
2297 if (skb->ip_summed == CHECKSUM_HW) {
2298 u32 csum_start_off, csum_stuff_off;
2299
2300 csum_start_off = (u32) (skb->h.raw - skb->data);
2301 csum_stuff_off = (u32) ((skb->h.raw + skb->csum) - skb->data);
2302
2303 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2304 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2305 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2306 }
2307
2308 spin_lock_irq(&hp->happy_lock);
2309
2310 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2311 netif_stop_queue(dev);
2312 spin_unlock_irq(&hp->happy_lock);
2313 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2314 dev->name);
2315 return 1;
2316 }
2317
2318 entry = hp->tx_new;
2319 SXD(("SX<l[%d]e[%d]>", len, entry));
2320 hp->tx_skbs[entry] = skb;
2321
2322 if (skb_shinfo(skb)->nr_frags == 0) {
2323 u32 mapping, len;
2324
2325 len = skb->len;
2326 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
2327 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2328 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2329 (tx_flags | (len & TXFLAG_SIZE)),
2330 mapping);
2331 entry = NEXT_TX(entry);
2332 } else {
2333 u32 first_len, first_mapping;
2334 int frag, first_entry = entry;
2335
2336 /* We must give this initial chunk to the device last.
2337 * Otherwise we could race with the device.
2338 */
2339 first_len = skb_headlen(skb);
2340 first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TODEVICE);
2341 entry = NEXT_TX(entry);
2342
2343 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2344 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2345 u32 len, mapping, this_txflags;
2346
2347 len = this_frag->size;
2348 mapping = hme_dma_map(hp,
2349 ((void *) page_address(this_frag->page) +
2350 this_frag->page_offset),
2351 len, DMA_TODEVICE);
2352 this_txflags = tx_flags;
2353 if (frag == skb_shinfo(skb)->nr_frags - 1)
2354 this_txflags |= TXFLAG_EOP;
2355 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2356 (this_txflags | (len & TXFLAG_SIZE)),
2357 mapping);
2358 entry = NEXT_TX(entry);
2359 }
2360 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2361 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2362 first_mapping);
2363 }
2364
2365 hp->tx_new = entry;
2366
2367 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2368 netif_stop_queue(dev);
2369
2370 /* Get it going. */
2371 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2372
2373 spin_unlock_irq(&hp->happy_lock);
2374
2375 dev->trans_start = jiffies;
2376
2377 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2378 return 0;
2379}
2380
2381static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2382{
2383 struct happy_meal *hp = dev->priv;
2384
2385 spin_lock_irq(&hp->happy_lock);
2386 happy_meal_get_counters(hp, hp->bigmacregs);
2387 spin_unlock_irq(&hp->happy_lock);
2388
2389 return &hp->net_stats;
2390}
2391
2392static void happy_meal_set_multicast(struct net_device *dev)
2393{
2394 struct happy_meal *hp = dev->priv;
2395 void __iomem *bregs = hp->bigmacregs;
2396 struct dev_mc_list *dmi = dev->mc_list;
2397 char *addrs;
2398 int i;
2399 u32 crc;
2400
2401 spin_lock_irq(&hp->happy_lock);
2402
2403 netif_stop_queue(dev);
2404
2405 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2406 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2407 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2408 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2409 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2410 } else if (dev->flags & IFF_PROMISC) {
2411 hme_write32(hp, bregs + BMAC_RXCFG,
2412 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2413 } else {
2414 u16 hash_table[4];
2415
2416 for (i = 0; i < 4; i++)
2417 hash_table[i] = 0;
2418
2419 for (i = 0; i < dev->mc_count; i++) {
2420 addrs = dmi->dmi_addr;
2421 dmi = dmi->next;
2422
2423 if (!(*addrs & 1))
2424 continue;
2425
2426 crc = ether_crc_le(6, addrs);
2427 crc >>= 26;
2428 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2429 }
2430 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2431 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2432 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2433 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2434 }
2435
2436 netif_wake_queue(dev);
2437
2438 spin_unlock_irq(&hp->happy_lock);
2439}
2440
2441/* Ethtool support... */
2442static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2443{
2444 struct happy_meal *hp = dev->priv;
2445
2446 cmd->supported =
2447 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2448 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2449 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2450
2451 /* XXX hardcoded stuff for now */
2452 cmd->port = PORT_TP; /* XXX no MII support */
2453 cmd->transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2454 cmd->phy_address = 0; /* XXX fixed PHYAD */
2455
2456 /* Record PHY settings. */
2457 spin_lock_irq(&hp->happy_lock);
2458 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2459 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2460 spin_unlock_irq(&hp->happy_lock);
2461
2462 if (hp->sw_bmcr & BMCR_ANENABLE) {
2463 cmd->autoneg = AUTONEG_ENABLE;
2464 cmd->speed =
2465 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2466 SPEED_100 : SPEED_10;
2467 if (cmd->speed == SPEED_100)
2468 cmd->duplex =
2469 (hp->sw_lpa & (LPA_100FULL)) ?
2470 DUPLEX_FULL : DUPLEX_HALF;
2471 else
2472 cmd->duplex =
2473 (hp->sw_lpa & (LPA_10FULL)) ?
2474 DUPLEX_FULL : DUPLEX_HALF;
2475 } else {
2476 cmd->autoneg = AUTONEG_DISABLE;
2477 cmd->speed =
2478 (hp->sw_bmcr & BMCR_SPEED100) ?
2479 SPEED_100 : SPEED_10;
2480 cmd->duplex =
2481 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2482 DUPLEX_FULL : DUPLEX_HALF;
2483 }
2484 return 0;
2485}
2486
2487static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2488{
2489 struct happy_meal *hp = dev->priv;
2490
2491 /* Verify the settings we care about. */
2492 if (cmd->autoneg != AUTONEG_ENABLE &&
2493 cmd->autoneg != AUTONEG_DISABLE)
2494 return -EINVAL;
2495 if (cmd->autoneg == AUTONEG_DISABLE &&
2496 ((cmd->speed != SPEED_100 &&
2497 cmd->speed != SPEED_10) ||
2498 (cmd->duplex != DUPLEX_HALF &&
2499 cmd->duplex != DUPLEX_FULL)))
2500 return -EINVAL;
2501
2502 /* Ok, do it to it. */
2503 spin_lock_irq(&hp->happy_lock);
2504 del_timer(&hp->happy_timer);
2505 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2506 spin_unlock_irq(&hp->happy_lock);
2507
2508 return 0;
2509}
2510
2511static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2512{
2513 struct happy_meal *hp = dev->priv;
2514
2515 strcpy(info->driver, "sunhme");
2516 strcpy(info->version, "2.02");
2517 if (hp->happy_flags & HFLAG_PCI) {
2518 struct pci_dev *pdev = hp->happy_dev;
2519 strcpy(info->bus_info, pci_name(pdev));
2520 }
2521#ifdef CONFIG_SBUS
2522 else {
2523 struct sbus_dev *sdev = hp->happy_dev;
2524 sprintf(info->bus_info, "SBUS:%d",
2525 sdev->slot);
2526 }
2527#endif
2528}
2529
2530static u32 hme_get_link(struct net_device *dev)
2531{
2532 struct happy_meal *hp = dev->priv;
2533
2534 spin_lock_irq(&hp->happy_lock);
2535 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2536 spin_unlock_irq(&hp->happy_lock);
2537
2538 return (hp->sw_bmsr & BMSR_LSTATUS);
2539}
2540
2541static struct ethtool_ops hme_ethtool_ops = {
2542 .get_settings = hme_get_settings,
2543 .set_settings = hme_set_settings,
2544 .get_drvinfo = hme_get_drvinfo,
2545 .get_link = hme_get_link,
2546};
2547
2548static int hme_version_printed;
2549
2550#ifdef CONFIG_SBUS
2551void __init quattro_get_ranges(struct quattro *qp)
2552{
2553 struct sbus_dev *sdev = qp->quattro_dev;
2554 int err;
2555
2556 err = prom_getproperty(sdev->prom_node,
2557 "ranges",
2558 (char *)&qp->ranges[0],
2559 sizeof(qp->ranges));
2560 if (err == 0 || err == -1) {
2561 qp->nranges = 0;
2562 return;
2563 }
2564 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2565}
2566
2567static void __init quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
2568{
2569 struct sbus_dev *sdev = hp->happy_dev;
2570 int rng;
2571
2572 for (rng = 0; rng < qp->nranges; rng++) {
2573 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2574 int reg;
2575
2576 for (reg = 0; reg < 5; reg++) {
2577 if (sdev->reg_addrs[reg].which_io ==
2578 rngp->ot_child_space)
2579 break;
2580 }
2581 if (reg == 5)
2582 continue;
2583
2584 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2585 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2586 }
2587}
2588
2589/* Given a happy meal sbus device, find it's quattro parent.
2590 * If none exist, allocate and return a new one.
2591 *
2592 * Return NULL on failure.
2593 */
2594static struct quattro * __init quattro_sbus_find(struct sbus_dev *goal_sdev)
2595{
2596 struct sbus_bus *sbus;
2597 struct sbus_dev *sdev;
2598 struct quattro *qp;
2599 int i;
2600
2601 if (qfe_sbus_list == NULL)
2602 goto found;
2603
2604 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2605 for (i = 0, sdev = qp->quattro_dev;
2606 (sdev != NULL) && (i < 4);
2607 sdev = sdev->next, i++) {
2608 if (sdev == goal_sdev)
2609 return qp;
2610 }
2611 }
2612 for_each_sbus(sbus) {
2613 for_each_sbusdev(sdev, sbus) {
2614 if (sdev == goal_sdev)
2615 goto found;
2616 }
2617 }
2618
2619 /* Cannot find quattro parent, fail. */
2620 return NULL;
2621
2622found:
2623 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2624 if (qp != NULL) {
2625 int i;
2626
2627 for (i = 0; i < 4; i++)
2628 qp->happy_meals[i] = NULL;
2629
2630 qp->quattro_dev = goal_sdev;
2631 qp->next = qfe_sbus_list;
2632 qfe_sbus_list = qp;
2633 quattro_get_ranges(qp);
2634 }
2635 return qp;
2636}
2637
2638/* After all quattro cards have been probed, we call these functions
2639 * to register the IRQ handlers.
2640 */
2641static void __init quattro_sbus_register_irqs(void)
2642{
2643 struct quattro *qp;
2644
2645 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2646 struct sbus_dev *sdev = qp->quattro_dev;
2647 int err;
2648
2649 err = request_irq(sdev->irqs[0],
2650 quattro_sbus_interrupt,
2651 SA_SHIRQ, "Quattro",
2652 qp);
2653 if (err != 0) {
2654 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2655 panic("QFE request irq");
2656 }
2657 }
2658}
2659#endif /* CONFIG_SBUS */
2660
2661#ifdef CONFIG_PCI
2662static struct quattro * __init quattro_pci_find(struct pci_dev *pdev)
2663{
2664 struct pci_dev *bdev = pdev->bus->self;
2665 struct quattro *qp;
2666
2667 if (!bdev) return NULL;
2668 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2669 struct pci_dev *qpdev = qp->quattro_dev;
2670
2671 if (qpdev == bdev)
2672 return qp;
2673 }
2674 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2675 if (qp != NULL) {
2676 int i;
2677
2678 for (i = 0; i < 4; i++)
2679 qp->happy_meals[i] = NULL;
2680
2681 qp->quattro_dev = bdev;
2682 qp->next = qfe_pci_list;
2683 qfe_pci_list = qp;
2684
2685 /* No range tricks necessary on PCI. */
2686 qp->nranges = 0;
2687 }
2688 return qp;
2689}
2690#endif /* CONFIG_PCI */
2691
2692#ifdef CONFIG_SBUS
2693static int __init happy_meal_sbus_init(struct sbus_dev *sdev, int is_qfe)
2694{
2695 struct quattro *qp = NULL;
2696 struct happy_meal *hp;
2697 struct net_device *dev;
2698 int i, qfe_slot = -1;
2699 int err = -ENODEV;
2700
2701 if (is_qfe) {
2702 qp = quattro_sbus_find(sdev);
2703 if (qp == NULL)
2704 goto err_out;
2705 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2706 if (qp->happy_meals[qfe_slot] == NULL)
2707 break;
2708 if (qfe_slot == 4)
2709 goto err_out;
2710 }
2711
2712 err = -ENOMEM;
2713 dev = alloc_etherdev(sizeof(struct happy_meal));
2714 if (!dev)
2715 goto err_out;
2716 SET_MODULE_OWNER(dev);
2717
2718 if (hme_version_printed++ == 0)
2719 printk(KERN_INFO "%s", version);
2720
2721 /* If user did not specify a MAC address specifically, use
2722 * the Quattro local-mac-address property...
2723 */
2724 for (i = 0; i < 6; i++) {
2725 if (macaddr[i] != 0)
2726 break;
2727 }
2728 if (i < 6) { /* a mac address was given */
2729 for (i = 0; i < 6; i++)
2730 dev->dev_addr[i] = macaddr[i];
2731 macaddr[5]++;
2732 } else if (qfe_slot != -1 &&
2733 prom_getproplen(sdev->prom_node,
2734 "local-mac-address") == 6) {
2735 prom_getproperty(sdev->prom_node, "local-mac-address",
2736 dev->dev_addr, 6);
2737 } else {
2738 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2739 }
2740
2741 hp = dev->priv;
2742
2743 hp->happy_dev = sdev;
2744
2745 spin_lock_init(&hp->happy_lock);
2746
2747 err = -ENODEV;
2748 if (sdev->num_registers != 5) {
2749 printk(KERN_ERR "happymeal: Device does not have 5 regs, it has %d.\n",
2750 sdev->num_registers);
2751 printk(KERN_ERR "happymeal: Would you like that for here or to go?\n");
2752 goto err_out_free_netdev;
2753 }
2754
2755 if (qp != NULL) {
2756 hp->qfe_parent = qp;
2757 hp->qfe_ent = qfe_slot;
2758 qp->happy_meals[qfe_slot] = dev;
2759 quattro_apply_ranges(qp, hp);
2760 }
2761
2762 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2763 GREG_REG_SIZE, "HME Global Regs");
2764 if (!hp->gregs) {
2765 printk(KERN_ERR "happymeal: Cannot map Happy Meal global registers.\n");
2766 goto err_out_free_netdev;
2767 }
2768
2769 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2770 ETX_REG_SIZE, "HME TX Regs");
2771 if (!hp->etxregs) {
2772 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Transmit registers.\n");
2773 goto err_out_iounmap;
2774 }
2775
2776 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2777 ERX_REG_SIZE, "HME RX Regs");
2778 if (!hp->erxregs) {
2779 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Receive registers.\n");
2780 goto err_out_iounmap;
2781 }
2782
2783 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2784 BMAC_REG_SIZE, "HME BIGMAC Regs");
2785 if (!hp->bigmacregs) {
2786 printk(KERN_ERR "happymeal: Cannot map Happy Meal BIGMAC registers.\n");
2787 goto err_out_iounmap;
2788 }
2789
2790 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2791 TCVR_REG_SIZE, "HME Tranceiver Regs");
2792 if (!hp->tcvregs) {
2793 printk(KERN_ERR "happymeal: Cannot map Happy Meal Tranceiver registers.\n");
2794 goto err_out_iounmap;
2795 }
2796
2797 hp->hm_revision = prom_getintdefault(sdev->prom_node, "hm-rev", 0xff);
2798 if (hp->hm_revision == 0xff)
2799 hp->hm_revision = 0xa0;
2800
2801 /* Now enable the feature flags we can. */
2802 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2803 hp->happy_flags = HFLAG_20_21;
2804 else if (hp->hm_revision != 0xa0)
2805 hp->happy_flags = HFLAG_NOT_A0;
2806
2807 if (qp != NULL)
2808 hp->happy_flags |= HFLAG_QUATTRO;
2809
2810 /* Get the supported DVMA burst sizes from our Happy SBUS. */
2811 hp->happy_bursts = prom_getintdefault(sdev->bus->prom_node,
2812 "burst-sizes", 0x00);
2813
2814 hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
2815 PAGE_SIZE,
2816 &hp->hblock_dvma);
2817 err = -ENOMEM;
2818 if (!hp->happy_block) {
2819 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2820 goto err_out_iounmap;
2821 }
2822
2823 /* Force check of the link first time we are brought up. */
2824 hp->linkcheck = 0;
2825
2826 /* Force timer state to 'asleep' with count of zero. */
2827 hp->timer_state = asleep;
2828 hp->timer_ticks = 0;
2829
2830 init_timer(&hp->happy_timer);
2831
2832 hp->dev = dev;
2833 dev->open = &happy_meal_open;
2834 dev->stop = &happy_meal_close;
2835 dev->hard_start_xmit = &happy_meal_start_xmit;
2836 dev->get_stats = &happy_meal_get_stats;
2837 dev->set_multicast_list = &happy_meal_set_multicast;
2838 dev->tx_timeout = &happy_meal_tx_timeout;
2839 dev->watchdog_timeo = 5*HZ;
2840 dev->ethtool_ops = &hme_ethtool_ops;
2841
2842 /* Happy Meal can do it all... except VLAN. */
2843 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_VLAN_CHALLENGED;
2844
2845 dev->irq = sdev->irqs[0];
2846
2847#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2848 /* Hook up PCI register/dma accessors. */
2849 hp->read_desc32 = sbus_hme_read_desc32;
2850 hp->write_txd = sbus_hme_write_txd;
2851 hp->write_rxd = sbus_hme_write_rxd;
2852 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
2853 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
2854 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
2855 sbus_dma_sync_single_for_cpu;
2856 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
2857 sbus_dma_sync_single_for_device;
2858 hp->read32 = sbus_hme_read32;
2859 hp->write32 = sbus_hme_write32;
2860#endif
2861
2862 /* Grrr, Happy Meal comes up by default not advertising
2863 * full duplex 100baseT capabilities, fix this.
2864 */
2865 spin_lock_irq(&hp->happy_lock);
2866 happy_meal_set_initial_advertisement(hp);
2867 spin_unlock_irq(&hp->happy_lock);
2868
2869 if (register_netdev(hp->dev)) {
2870 printk(KERN_ERR "happymeal: Cannot register net device, "
2871 "aborting.\n");
2872 goto err_out_free_consistent;
2873 }
2874
2875 if (qfe_slot != -1)
2876 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2877 dev->name, qfe_slot);
2878 else
2879 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2880 dev->name);
2881
2882 for (i = 0; i < 6; i++)
2883 printk("%2.2x%c",
2884 dev->dev_addr[i], i == 5 ? ' ' : ':');
2885 printk("\n");
2886
2887 /* We are home free at this point, link us in to the happy
2888 * device list.
2889 */
2890 hp->next_module = root_happy_dev;
2891 root_happy_dev = hp;
2892
2893 return 0;
2894
2895err_out_free_consistent:
2896 sbus_free_consistent(hp->happy_dev,
2897 PAGE_SIZE,
2898 hp->happy_block,
2899 hp->hblock_dvma);
2900
2901err_out_iounmap:
2902 if (hp->gregs)
2903 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
2904 if (hp->etxregs)
2905 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
2906 if (hp->erxregs)
2907 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
2908 if (hp->bigmacregs)
2909 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
2910 if (hp->tcvregs)
2911 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
2912
2913err_out_free_netdev:
2914 free_netdev(dev);
2915
2916err_out:
2917 return err;
2918}
2919#endif
2920
2921#ifdef CONFIG_PCI
2922#ifndef __sparc__
2923static int is_quattro_p(struct pci_dev *pdev)
2924{
2925 struct pci_dev *busdev = pdev->bus->self;
2926 struct list_head *tmp;
2927 int n_hmes;
2928
2929 if (busdev == NULL ||
2930 busdev->vendor != PCI_VENDOR_ID_DEC ||
2931 busdev->device != PCI_DEVICE_ID_DEC_21153)
2932 return 0;
2933
2934 n_hmes = 0;
2935 tmp = pdev->bus->devices.next;
2936 while (tmp != &pdev->bus->devices) {
2937 struct pci_dev *this_pdev = pci_dev_b(tmp);
2938
2939 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2940 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2941 n_hmes++;
2942
2943 tmp = tmp->next;
2944 }
2945
2946 if (n_hmes != 4)
2947 return 0;
2948
2949 return 1;
2950}
2951
2952/* Fetch MAC address from vital product data of PCI ROM. */
ce1289ad 2953static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
1da177e4
LT		 2954{
2955 int this_offset;
2956
2957 for (this_offset = 0x20; this_offset < len; this_offset++) {
2958 void __iomem *p = rom_base + this_offset;
2959
2960 if (readb(p + 0) != 0x90 ||
2961 readb(p + 1) != 0x00 ||
2962 readb(p + 2) != 0x09 ||
2963 readb(p + 3) != 0x4e ||
2964 readb(p + 4) != 0x41 ||
2965 readb(p + 5) != 0x06)
2966 continue;
2967
2968 this_offset += 6;
2969 p += 6;
2970
2971 if (index == 0) {
2972 int i;
2973
2974 for (i = 0; i < 6; i++)
2975 dev_addr[i] = readb(p + i);
ce1289ad 2976 return 1;
1da177e4
LT		 2977 }
2978 index--;
2979 }
ce1289ad 2980 return 0;
1da177e4
LT		 2981}
2982
2983static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2984{
ce1289ad
WT		 2985 size_t size;
2986 void __iomem *p = pci_map_rom(pdev, &size);
1da177e4 2987
ce1289ad
WT		 2988 if (p) {
2989 int index = 0;
2990 int found;
1da177e4 2991
ce1289ad
WT		 2992 if (is_quattro_p(pdev))
2993 index = PCI_SLOT(pdev->devfn);
1da177e4 2994
ce1289ad
WT		 2995 found = readb(p) == 0x55 &&
2996 readb(p + 1) == 0xaa &&
2997 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2998 pci_unmap_rom(pdev, p);
2999 if (found)
3000 return;
3001 }
1da177e4 3002
1da177e4
LT		 3003 /* Sun MAC prefix then 3 random bytes. */
3004 dev_addr[0] = 0x08;
3005 dev_addr[1] = 0x00;
3006 dev_addr[2] = 0x20;
3007 get_random_bytes(&dev_addr[3], 3);
3008 return;
3009}
3010#endif /* !(__sparc__) */
3011
3012static int __init happy_meal_pci_init(struct pci_dev *pdev)
3013{
3014 struct quattro *qp = NULL;
3015#ifdef __sparc__
3016 struct pcidev_cookie *pcp;
1da177e4
LT		 3017#endif
3018 struct happy_meal *hp;
3019 struct net_device *dev;
3020 void __iomem *hpreg_base;
3021 unsigned long hpreg_res;
3022 int i, qfe_slot = -1;
3023 char prom_name[64];
3024 int err;
3025
3026 /* Now make sure pci_dev cookie is there. */
3027#ifdef __sparc__
3028 pcp = pdev->sysdata;
de8d28b1 3029 if (pcp == NULL) {
1da177e4
LT		 3030 printk(KERN_ERR "happymeal(PCI): Some PCI device info missing\n");
3031 return -ENODEV;
3032 }
1da177e4 3033
de8d28b1 3034 strcpy(prom_name, pcp->prom_node->name);
1da177e4
LT		 3035#else
3036 if (is_quattro_p(pdev))
3037 strcpy(prom_name, "SUNW,qfe");
3038 else
3039 strcpy(prom_name, "SUNW,hme");
3040#endif
3041
3042 err = -ENODEV;
3043 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
3044 qp = quattro_pci_find(pdev);
3045 if (qp == NULL)
3046 goto err_out;
3047 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
3048 if (qp->happy_meals[qfe_slot] == NULL)
3049 break;
3050 if (qfe_slot == 4)
3051 goto err_out;
3052 }
3053
3054 dev = alloc_etherdev(sizeof(struct happy_meal));
3055 err = -ENOMEM;
3056 if (!dev)
3057 goto err_out;
3058 SET_MODULE_OWNER(dev);
3059 SET_NETDEV_DEV(dev, &pdev->dev);
3060
3061 if (hme_version_printed++ == 0)
3062 printk(KERN_INFO "%s", version);
3063
3064 dev->base_addr = (long) pdev;
3065
3066 hp = (struct happy_meal *)dev->priv;
3067 memset(hp, 0, sizeof(*hp));
3068
3069 hp->happy_dev = pdev;
3070
3071 spin_lock_init(&hp->happy_lock);
3072
3073 if (qp != NULL) {
3074 hp->qfe_parent = qp;
3075 hp->qfe_ent = qfe_slot;
3076 qp->happy_meals[qfe_slot] = dev;
3077 }
3078
3079 hpreg_res = pci_resource_start(pdev, 0);
3080 err = -ENODEV;
3081 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3082 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
3083 goto err_out_clear_quattro;
3084 }
3085 if (pci_request_regions(pdev, DRV_NAME)) {
3086 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
3087 "aborting.\n");
3088 goto err_out_clear_quattro;
3089 }
3090
3091 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == 0) {
3092 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3093 goto err_out_free_res;
3094 }
3095
3096 for (i = 0; i < 6; i++) {
3097 if (macaddr[i] != 0)
3098 break;
3099 }
3100 if (i < 6) { /* a mac address was given */
3101 for (i = 0; i < 6; i++)
3102 dev->dev_addr[i] = macaddr[i];
3103 macaddr[5]++;
3104 } else {
3105#ifdef __sparc__
de8d28b1
DM		 3106 unsigned char *addr;
3107 int len;
3108
1da177e4 3109 if (qfe_slot != -1 &&
de8d28b1
DM		 3110 (addr = of_get_property(pcp->prom_node,
3111 "local-mac-address", &len)) != NULL
3112 && len == 6) {
3113 memcpy(dev->dev_addr, addr, 6);
1da177e4
LT		 3114 } else {
3115 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3116 }
3117#else
3118 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3119#endif
3120 }
3121
3122 /* Layout registers. */
3123 hp->gregs = (hpreg_base + 0x0000UL);
3124 hp->etxregs = (hpreg_base + 0x2000UL);
3125 hp->erxregs = (hpreg_base + 0x4000UL);
3126 hp->bigmacregs = (hpreg_base + 0x6000UL);
3127 hp->tcvregs = (hpreg_base + 0x7000UL);
3128
3129#ifdef __sparc__
de8d28b1 3130 hp->hm_revision = of_getintprop_default(pcp->prom_node, "hm-rev", 0xff);
1da177e4
LT		 3131 if (hp->hm_revision == 0xff) {
3132 unsigned char prev;
3133
3134 pci_read_config_byte(pdev, PCI_REVISION_ID, &prev);
3135 hp->hm_revision = 0xc0 | (prev & 0x0f);
3136 }
3137#else
3138 /* works with this on non-sparc hosts */
3139 hp->hm_revision = 0x20;
3140#endif
3141
3142 /* Now enable the feature flags we can. */
3143 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3144 hp->happy_flags = HFLAG_20_21;
3145 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3146 hp->happy_flags = HFLAG_NOT_A0;
3147
3148 if (qp != NULL)
3149 hp->happy_flags |= HFLAG_QUATTRO;
3150
3151 /* And of course, indicate this is PCI. */
3152 hp->happy_flags |= HFLAG_PCI;
3153
3154#ifdef __sparc__
3155 /* Assume PCI happy meals can handle all burst sizes. */
3156 hp->happy_bursts = DMA_BURSTBITS;
3157#endif
3158
3159 hp->happy_block = (struct hmeal_init_block *)
3160 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
3161
3162 err = -ENODEV;
3163 if (!hp->happy_block) {
3164 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3165 goto err_out_iounmap;
3166 }
3167
3168 hp->linkcheck = 0;
3169 hp->timer_state = asleep;
3170 hp->timer_ticks = 0;
3171
3172 init_timer(&hp->happy_timer);
3173
3174 hp->dev = dev;
3175 dev->open = &happy_meal_open;
3176 dev->stop = &happy_meal_close;
3177 dev->hard_start_xmit = &happy_meal_start_xmit;
3178 dev->get_stats = &happy_meal_get_stats;
3179 dev->set_multicast_list = &happy_meal_set_multicast;
3180 dev->tx_timeout = &happy_meal_tx_timeout;
3181 dev->watchdog_timeo = 5*HZ;
3182 dev->ethtool_ops = &hme_ethtool_ops;
3183 dev->irq = pdev->irq;
3184 dev->dma = 0;
3185
3186 /* Happy Meal can do it all... */
3187 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3188
3189#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3190 /* Hook up PCI register/dma accessors. */
3191 hp->read_desc32 = pci_hme_read_desc32;
3192 hp->write_txd = pci_hme_write_txd;
3193 hp->write_rxd = pci_hme_write_rxd;
3194 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
3195 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
3196 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
3197 pci_dma_sync_single_for_cpu;
3198 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
3199 pci_dma_sync_single_for_device;
3200 hp->read32 = pci_hme_read32;
3201 hp->write32 = pci_hme_write32;
3202#endif
3203
3204 /* Grrr, Happy Meal comes up by default not advertising
3205 * full duplex 100baseT capabilities, fix this.
3206 */
3207 spin_lock_irq(&hp->happy_lock);
3208 happy_meal_set_initial_advertisement(hp);
3209 spin_unlock_irq(&hp->happy_lock);
3210
3211 if (register_netdev(hp->dev)) {
3212 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3213 "aborting.\n");
3214 goto err_out_iounmap;
3215 }
3216
3217 if (!qfe_slot) {
3218 struct pci_dev *qpdev = qp->quattro_dev;
3219
3220 prom_name[0] = 0;
3221 if (!strncmp(dev->name, "eth", 3)) {
3222 int i = simple_strtoul(dev->name + 3, NULL, 10);
3223 sprintf(prom_name, "-%d", i + 3);
3224 }
3225 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3226 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3227 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3228 printk("DEC 21153 PCI Bridge\n");
3229 else
3230 printk("unknown bridge %04x.%04x\n",
3231 qpdev->vendor, qpdev->device);
3232 }
3233
3234 if (qfe_slot != -1)
3235 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3236 dev->name, qfe_slot);
3237 else
3238 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3239 dev->name);
3240
3241 for (i = 0; i < 6; i++)
3242 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':');
3243
3244 printk("\n");
3245
3246 /* We are home free at this point, link us in to the happy
3247 * device list.
3248 */
3249 hp->next_module = root_happy_dev;
3250 root_happy_dev = hp;
3251
3252 return 0;
3253
3254err_out_iounmap:
3255 iounmap(hp->gregs);
3256
3257err_out_free_res:
3258 pci_release_regions(pdev);
3259
3260err_out_clear_quattro:
3261 if (qp != NULL)
3262 qp->happy_meals[qfe_slot] = NULL;
3263
3264 free_netdev(dev);
3265
3266err_out:
3267 return err;
3268}
3269#endif
3270
3271#ifdef CONFIG_SBUS
3272static int __init happy_meal_sbus_probe(void)
3273{
3274 struct sbus_bus *sbus;
3275 struct sbus_dev *sdev;
3276 int cards = 0;
3277 char model[128];
3278
3279 for_each_sbus(sbus) {
3280 for_each_sbusdev(sdev, sbus) {
3281 char *name = sdev->prom_name;
3282
3283 if (!strcmp(name, "SUNW,hme")) {
3284 cards++;
3285 prom_getstring(sdev->prom_node, "model",
3286 model, sizeof(model));
3287 if (!strcmp(model, "SUNW,sbus-qfe"))
3288 happy_meal_sbus_init(sdev, 1);
3289 else
3290 happy_meal_sbus_init(sdev, 0);
3291 } else if (!strcmp(name, "qfe") ||
3292 !strcmp(name, "SUNW,qfe")) {
3293 cards++;
3294 happy_meal_sbus_init(sdev, 1);
3295 }
3296 }
3297 }
3298 if (cards != 0)
3299 quattro_sbus_register_irqs();
3300 return cards;
3301}
3302#endif
3303
3304#ifdef CONFIG_PCI
3305static int __init happy_meal_pci_probe(void)
3306{
3307 struct pci_dev *pdev = NULL;
3308 int cards = 0;
3309
3310 while ((pdev = pci_find_device(PCI_VENDOR_ID_SUN,
3311 PCI_DEVICE_ID_SUN_HAPPYMEAL, pdev)) != NULL) {
3312 if (pci_enable_device(pdev))
3313 continue;
3314 pci_set_master(pdev);
3315 cards++;
3316 happy_meal_pci_init(pdev);
3317 }
3318 return cards;
3319}
3320#endif
3321
3322static int __init happy_meal_probe(void)
3323{
3324 static int called = 0;
3325 int cards;
3326
3327 root_happy_dev = NULL;
3328
3329 if (called)
3330 return -ENODEV;
3331 called++;
3332
3333 cards = 0;
3334#ifdef CONFIG_SBUS
3335 cards += happy_meal_sbus_probe();
3336#endif
3337#ifdef CONFIG_PCI
3338 cards += happy_meal_pci_probe();
3339#endif
3340 if (!cards)
3341 return -ENODEV;
3342 return 0;
3343}
3344
3345
3346static void __exit happy_meal_cleanup_module(void)
3347{
3348#ifdef CONFIG_SBUS
3349 struct quattro *last_seen_qfe = NULL;
3350#endif
3351
3352 while (root_happy_dev) {
3353 struct happy_meal *hp = root_happy_dev;
3354 struct happy_meal *next = root_happy_dev->next_module;
3355 struct net_device *dev = hp->dev;
3356
3357 /* Unregister netdev before unmapping registers as this
3358 * call can end up trying to access those registers.
3359 */
3360 unregister_netdev(dev);
3361
3362#ifdef CONFIG_SBUS
3363 if (!(hp->happy_flags & HFLAG_PCI)) {
3364 if (hp->happy_flags & HFLAG_QUATTRO) {
3365 if (hp->qfe_parent != last_seen_qfe) {
3366 free_irq(dev->irq, hp->qfe_parent);
3367 last_seen_qfe = hp->qfe_parent;
3368 }
3369 }
3370
3371 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
3372 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
3373 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
3374 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
3375 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
3376 sbus_free_consistent(hp->happy_dev,
3377 PAGE_SIZE,
3378 hp->happy_block,
3379 hp->hblock_dvma);
3380 }
3381#endif
3382#ifdef CONFIG_PCI
3383 if ((hp->happy_flags & HFLAG_PCI)) {
3384 pci_free_consistent(hp->happy_dev,
3385 PAGE_SIZE,
3386 hp->happy_block,
3387 hp->hblock_dvma);
3388 iounmap(hp->gregs);
3389 pci_release_regions(hp->happy_dev);
3390 }
3391#endif
3392 free_netdev(dev);
3393
3394 root_happy_dev = next;
3395 }
3396
3397 /* Now cleanup the quattro lists. */
3398#ifdef CONFIG_SBUS
3399 while (qfe_sbus_list) {
3400 struct quattro *qfe = qfe_sbus_list;
3401 struct quattro *next = qfe->next;
3402
3403 kfree(qfe);
3404
3405 qfe_sbus_list = next;
3406 }
3407#endif
3408#ifdef CONFIG_PCI
3409 while (qfe_pci_list) {
3410 struct quattro *qfe = qfe_pci_list;
3411 struct quattro *next = qfe->next;
3412
3413 kfree(qfe);
3414
3415 qfe_pci_list = next;
3416 }
3417#endif
3418}
3419
3420module_init(happy_meal_probe);
3421module_exit(happy_meal_cleanup_module);
Linux 6.x block layer and io_uring tree(s)