[linux-block.git] / drivers / net / stmmac / common.h

/*******************************************************************************
  STMMAC Common Header File

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include "descs.h"
#include <linux/netdevice.h>

struct stmmac_extra_stats {
	/* Transmit errors */
	unsigned long tx_underflow ____cacheline_aligned;
	unsigned long tx_carrier;
	unsigned long tx_losscarrier;
	unsigned long tx_heartbeat;
	unsigned long tx_deferred;
	unsigned long tx_vlan;
	unsigned long tx_jabber;
	unsigned long tx_frame_flushed;
	unsigned long tx_payload_error;
	unsigned long tx_ip_header_error;
	/* Receive errors */
	unsigned long rx_desc;
	unsigned long rx_partial;
	unsigned long rx_runt;
	unsigned long rx_toolong;
	unsigned long rx_collision;
	unsigned long rx_crc;
	unsigned long rx_lenght;
	unsigned long rx_mii;
	unsigned long rx_multicast;
	unsigned long rx_gmac_overflow;
	unsigned long rx_watchdog;
	unsigned long da_rx_filter_fail;
	unsigned long sa_rx_filter_fail;
	unsigned long rx_missed_cntr;
	unsigned long rx_overflow_cntr;
	unsigned long rx_vlan;
	/* Tx/Rx IRQ errors */
	unsigned long tx_undeflow_irq;
	unsigned long tx_process_stopped_irq;
	unsigned long tx_jabber_irq;
	unsigned long rx_overflow_irq;
	unsigned long rx_buf_unav_irq;
	unsigned long rx_process_stopped_irq;
	unsigned long rx_watchdog_irq;
	unsigned long tx_early_irq;
	unsigned long fatal_bus_error_irq;
	/* Extra info */
	unsigned long threshold;
	unsigned long tx_pkt_n;
	unsigned long rx_pkt_n;
	unsigned long poll_n;
	unsigned long sched_timer_n;
	unsigned long normal_irq_n;
};

#define HASH_TABLE_SIZE 64
#define PAUSE_TIME 0x200

/* Flow Control defines */
#define FLOW_OFF	0
#define FLOW_RX		1
#define FLOW_TX		2
#define FLOW_AUTO	(FLOW_TX | FLOW_RX)

#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */

#define HW_CSUM 1
#define NO_HW_CSUM 0
enum rx_frame_status { /* IPC status */
	good_frame = 0,
	discard_frame = 1,
	csum_none = 2,
};

enum tx_dma_irq_status {
	tx_hard_error = 1,
	tx_hard_error_bump_tc = 2,
	handle_tx_rx = 3,
};

/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
#define BUF_SIZE_16KiB 16384
#define BUF_SIZE_8KiB 8192
#define BUF_SIZE_4KiB 4096
#define BUF_SIZE_2KiB 2048

/* Power Down and WOL */
#define PMT_NOT_SUPPORTED 0
#define PMT_SUPPORTED 1

/* Common MAC defines */
#define MAC_CTRL_REG		0x00000000	/* MAC Control */
#define MAC_ENABLE_TX		0x00000008	/* Transmitter Enable */
#define MAC_RNABLE_RX		0x00000004	/* Receiver Enable */

/* MAC Management Counters register */
#define MMC_CONTROL		0x00000100	/* MMC Control */
#define MMC_HIGH_INTR		0x00000104	/* MMC High Interrupt */
#define MMC_LOW_INTR		0x00000108	/* MMC Low Interrupt */
#define MMC_HIGH_INTR_MASK	0x0000010c	/* MMC High Interrupt Mask */
#define MMC_LOW_INTR_MASK	0x00000110	/* MMC Low Interrupt Mask */

#define MMC_CONTROL_MAX_FRM_MASK	0x0003ff8	/* Maximum Frame Size */
#define MMC_CONTROL_MAX_FRM_SHIFT	3
#define MMC_CONTROL_MAX_FRAME		0x7FF

struct stmmac_desc_ops {
	/* DMA RX descriptor ring initialization */
	void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
			      int disable_rx_ic);
	/* DMA TX descriptor ring initialization */
	void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);

	/* Invoked by the xmit function to prepare the tx descriptor */
	void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
				 int csum_flag);
	/* Set/get the owner of the descriptor */
	void (*set_tx_owner) (struct dma_desc *p);
	int (*get_tx_owner) (struct dma_desc *p);
	/* Invoked by the xmit function to close the tx descriptor */
	void (*close_tx_desc) (struct dma_desc *p);
	/* Clean the tx descriptor as soon as the tx irq is received */
	void (*release_tx_desc) (struct dma_desc *p);
	/* Clear interrupt on tx frame completion. When this bit is
	 * set an interrupt happens as soon as the frame is transmitted */
	void (*clear_tx_ic) (struct dma_desc *p);
	/* Last tx segment reports the transmit status */
	int (*get_tx_ls) (struct dma_desc *p);
	/* Return the transmit status looking at the TDES1 */
	int (*tx_status) (void *data, struct stmmac_extra_stats *x,
			  struct dma_desc *p, unsigned long ioaddr);
	/* Get the buffer size from the descriptor */
	int (*get_tx_len) (struct dma_desc *p);
	/* Handle extra events on specific interrupts hw dependent */
	int (*get_rx_owner) (struct dma_desc *p);
	void (*set_rx_owner) (struct dma_desc *p);
	/* Get the receive frame size */
	int (*get_rx_frame_len) (struct dma_desc *p);
	/* Return the reception status looking at the RDES1 */
	int (*rx_status) (void *data, struct stmmac_extra_stats *x,
			  struct dma_desc *p);
};

struct stmmac_dma_ops {
	/* DMA core initialization */
	int (*init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
	/* Dump DMA registers */
	void (*dump_regs) (unsigned long ioaddr);
	/* Set tx/rx threshold in the csr6 register
	 * An invalid value enables the store-and-forward mode */
	void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode);
	/* To track extra statistic (if supported) */
	void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
				   unsigned long ioaddr);
	void (*enable_dma_transmission) (unsigned long ioaddr);
	void (*enable_dma_irq) (unsigned long ioaddr);
	void (*disable_dma_irq) (unsigned long ioaddr);
	void (*start_tx) (unsigned long ioaddr);
	void (*stop_tx) (unsigned long ioaddr);
	void (*start_rx) (unsigned long ioaddr);
	void (*stop_rx) (unsigned long ioaddr);
	int (*dma_interrupt) (unsigned long ioaddr,
			      struct stmmac_extra_stats *x);
};

struct stmmac_ops {
	/* MAC core initialization */
	void (*core_init) (unsigned long ioaddr) ____cacheline_aligned;
	/* Dump MAC registers */
	void (*dump_regs) (unsigned long ioaddr);
	/* Handle extra events on specific interrupts hw dependent */
	void (*host_irq_status) (unsigned long ioaddr);
	/* Multicast filter setting */
	void (*set_filter) (struct net_device *dev);
	/* Flow control setting */
	void (*flow_ctrl) (unsigned long ioaddr, unsigned int duplex,
			   unsigned int fc, unsigned int pause_time);
	/* Set power management mode (e.g. magic frame) */
	void (*pmt) (unsigned long ioaddr, unsigned long mode);
	/* Set/Get Unicast MAC addresses */
	void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr,
			       unsigned int reg_n);
	void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr,
			       unsigned int reg_n);
};

struct mac_link {
	int port;
	int duplex;
	int speed;
};

struct mii_regs {
	unsigned int addr;	/* MII Address */
	unsigned int data;	/* MII Data */
};

struct mac_device_info {
	struct stmmac_ops	*mac;
	struct stmmac_desc_ops	*desc;
	struct stmmac_dma_ops	*dma;
	unsigned int pmt;	/* support Power-Down */
	struct mii_regs mii;	/* MII register Addresses */
	struct mac_link link;
};

struct mac_device_info *dwmac1000_setup(unsigned long addr);
struct mac_device_info *dwmac100_setup(unsigned long addr);

extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
				unsigned int high, unsigned int low);
extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
				unsigned int high, unsigned int low);
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	STMMAC Common Header File
	3
	4	Copyright (C) 2007-2009 STMicroelectronics Ltd
	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	23	*******************************************************************************/
	24
	25	#include "descs.h"
5e33c791	26	#include <linux/netdevice.h>
47dd7a54	27
47dd7a54 GC	28	struct stmmac_extra_stats {
	29	/* Transmit errors */
	30	unsigned long tx_underflow ____cacheline_aligned;
	31	unsigned long tx_carrier;
	32	unsigned long tx_losscarrier;
	33	unsigned long tx_heartbeat;
	34	unsigned long tx_deferred;
	35	unsigned long tx_vlan;
	36	unsigned long tx_jabber;
	37	unsigned long tx_frame_flushed;
	38	unsigned long tx_payload_error;
	39	unsigned long tx_ip_header_error;
	40	/* Receive errors */
	41	unsigned long rx_desc;
	42	unsigned long rx_partial;
	43	unsigned long rx_runt;
	44	unsigned long rx_toolong;
	45	unsigned long rx_collision;
	46	unsigned long rx_crc;
	47	unsigned long rx_lenght;
	48	unsigned long rx_mii;
	49	unsigned long rx_multicast;
	50	unsigned long rx_gmac_overflow;
	51	unsigned long rx_watchdog;
	52	unsigned long da_rx_filter_fail;
	53	unsigned long sa_rx_filter_fail;
	54	unsigned long rx_missed_cntr;
	55	unsigned long rx_overflow_cntr;
	56	unsigned long rx_vlan;
	57	/* Tx/Rx IRQ errors */
	58	unsigned long tx_undeflow_irq;
	59	unsigned long tx_process_stopped_irq;
	60	unsigned long tx_jabber_irq;
	61	unsigned long rx_overflow_irq;
	62	unsigned long rx_buf_unav_irq;
	63	unsigned long rx_process_stopped_irq;
	64	unsigned long rx_watchdog_irq;
	65	unsigned long tx_early_irq;
	66	unsigned long fatal_bus_error_irq;
	67	/* Extra info */
	68	unsigned long threshold;
	69	unsigned long tx_pkt_n;
	70	unsigned long rx_pkt_n;
	71	unsigned long poll_n;
	72	unsigned long sched_timer_n;
	73	unsigned long normal_irq_n;
	74	};
	75
aec7ff27 GC	76	#define HASH_TABLE_SIZE 64
	77	#define PAUSE_TIME 0x200
	78
	79	/* Flow Control defines */
	80	#define FLOW_OFF 0
	81	#define FLOW_RX 1
	82	#define FLOW_TX 2
	83	#define FLOW_AUTO (FLOW_TX \| FLOW_RX)
	84
	85	#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
	86
	87	#define HW_CSUM 1
	88	#define NO_HW_CSUM 0
	89	enum rx_frame_status { /* IPC status */
47dd7a54 GC	90	good_frame = 0,
	91	discard_frame = 1,
	92	csum_none = 2,
	93	};
	94
aec7ff27 GC	95	enum tx_dma_irq_status {
	96	tx_hard_error = 1,
	97	tx_hard_error_bump_tc = 2,
	98	handle_tx_rx = 3,
	99	};
47dd7a54	100
aec7ff27 GC	101	/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
	102	#define BUF_SIZE_16KiB 16384
	103	#define BUF_SIZE_8KiB 8192
	104	#define BUF_SIZE_4KiB 4096
	105	#define BUF_SIZE_2KiB 2048
47dd7a54	106
aec7ff27 GC	107	/* Power Down and WOL */
	108	#define PMT_NOT_SUPPORTED 0
	109	#define PMT_SUPPORTED 1
47dd7a54	110
aec7ff27 GC	111	/* Common MAC defines */
	112	#define MAC_CTRL_REG 0x00000000 /* MAC Control */
	113	#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
	114	#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54	115
aec7ff27 GC	116	/* MAC Management Counters register */
	117	#define MMC_CONTROL 0x00000100 /* MMC Control */
	118	#define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
	119	#define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
	120	#define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
	121	#define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
47dd7a54	122
aec7ff27 GC	123	#define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
	124	#define MMC_CONTROL_MAX_FRM_SHIFT 3
	125	#define MMC_CONTROL_MAX_FRAME 0x7FF
47dd7a54	126
db98a0b0 GC	127	struct stmmac_desc_ops {
db98a0b0 GC	128	/* DMA RX descriptor ring initialization */
47dd7a54	129	void (init_rx_desc) (struct dma_desc p, unsigned int ring_size,
db98a0b0 GC	130	int disable_rx_ic);
db98a0b0 GC	131	/* DMA TX descriptor ring initialization */
47dd7a54 GC	132	void (init_tx_desc) (struct dma_desc p, unsigned int ring_size);
	133
	134	/* Invoked by the xmit function to prepare the tx descriptor */
	135	void (prepare_tx_desc) (struct dma_desc p, int is_fs, int len,
	136	int csum_flag);
	137	/* Set/get the owner of the descriptor */
	138	void (set_tx_owner) (struct dma_desc p);
	139	int (get_tx_owner) (struct dma_desc p);
	140	/* Invoked by the xmit function to close the tx descriptor */
	141	void (close_tx_desc) (struct dma_desc p);
	142	/* Clean the tx descriptor as soon as the tx irq is received */
	143	void (release_tx_desc) (struct dma_desc p);
	144	/* Clear interrupt on tx frame completion. When this bit is
	145	* set an interrupt happens as soon as the frame is transmitted */
	146	void (clear_tx_ic) (struct dma_desc p);
	147	/* Last tx segment reports the transmit status */
	148	int (get_tx_ls) (struct dma_desc p);
	149	/* Return the transmit status looking at the TDES1 */
	150	int (tx_status) (void data, struct stmmac_extra_stats *x,
	151	struct dma_desc *p, unsigned long ioaddr);
	152	/* Get the buffer size from the descriptor */
	153	int (get_tx_len) (struct dma_desc p);
	154	/* Handle extra events on specific interrupts hw dependent */
47dd7a54 GC	155	int (get_rx_owner) (struct dma_desc p);
	156	void (set_rx_owner) (struct dma_desc p);
	157	/* Get the receive frame size */
	158	int (get_rx_frame_len) (struct dma_desc p);
	159	/* Return the reception status looking at the RDES1 */
	160	int (rx_status) (void data, struct stmmac_extra_stats *x,
	161	struct dma_desc *p);
db98a0b0 GC	162	};
	163
	164	struct stmmac_dma_ops {
	165	/* DMA core initialization */
	166	int (*init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
	167	/* Dump DMA registers */
	168	void (*dump_regs) (unsigned long ioaddr);
	169	/* Set tx/rx threshold in the csr6 register
	170	* An invalid value enables the store-and-forward mode */
	171	void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode);
	172	/* To track extra statistic (if supported) */
	173	void (dma_diagnostic_fr) (void data, struct stmmac_extra_stats *x,
	174	unsigned long ioaddr);
aec7ff27 GC	175	void (*enable_dma_transmission) (unsigned long ioaddr);
	176	void (*enable_dma_irq) (unsigned long ioaddr);
	177	void (*disable_dma_irq) (unsigned long ioaddr);
	178	void (*start_tx) (unsigned long ioaddr);
	179	void (*stop_tx) (unsigned long ioaddr);
	180	void (*start_rx) (unsigned long ioaddr);
	181	void (*stop_rx) (unsigned long ioaddr);
	182	int (*dma_interrupt) (unsigned long ioaddr,
	183	struct stmmac_extra_stats *x);
db98a0b0 GC	184	};
	185
	186	struct stmmac_ops {
	187	/* MAC core initialization */
	188	void (*core_init) (unsigned long ioaddr) ____cacheline_aligned;
	189	/* Dump MAC registers */
	190	void (*dump_regs) (unsigned long ioaddr);
	191	/* Handle extra events on specific interrupts hw dependent */
	192	void (*host_irq_status) (unsigned long ioaddr);
47dd7a54 GC	193	/* Multicast filter setting */
	194	void (set_filter) (struct net_device dev);
	195	/* Flow control setting */
	196	void (*flow_ctrl) (unsigned long ioaddr, unsigned int duplex,
	197	unsigned int fc, unsigned int pause_time);
	198	/* Set power management mode (e.g. magic frame) */
	199	void (*pmt) (unsigned long ioaddr, unsigned long mode);
	200	/* Set/Get Unicast MAC addresses */
	201	void (set_umac_addr) (unsigned long ioaddr, unsigned char addr,
db98a0b0	202	unsigned int reg_n);
47dd7a54	203	void (get_umac_addr) (unsigned long ioaddr, unsigned char addr,
db98a0b0	204	unsigned int reg_n);
47dd7a54 GC	205	};
	206
	207	struct mac_link {
	208	int port;
	209	int duplex;
	210	int speed;
	211	};
	212
	213	struct mii_regs {
	214	unsigned int addr; /* MII Address */
	215	unsigned int data; /* MII Data */
	216	};
	217
47dd7a54	218	struct mac_device_info {
db98a0b0 GC	219	struct stmmac_ops *mac;
	220	struct stmmac_desc_ops *desc;
	221	struct stmmac_dma_ops *dma;
	222	unsigned int pmt; /* support Power-Down */
	223	struct mii_regs mii; /* MII register Addresses */
	224	struct mac_link link;
47dd7a54 GC	225	};
47dd7a54 GC	226
21d437cc	227	struct mac_device_info *dwmac1000_setup(unsigned long addr);
7e848ae1	228	struct mac_device_info *dwmac100_setup(unsigned long addr);
aec7ff27 GC	229
	230	extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
	231	unsigned int high, unsigned int low);
	232	extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
	233	unsigned int high, unsigned int low);