[linux-block.git] / drivers / net / spider_net.h

/*
 * Network device driver for Cell Processor-Based Blade
 *
 * (C) Copyright IBM Corp. 2005
 *
 * Authors : Utz Bacher <utz.bacher@de.ibm.com>
 *           Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef _SPIDER_NET_H
#define _SPIDER_NET_H

#include "sungem_phy.h"

extern int spider_net_stop(struct net_device *netdev);
extern int spider_net_open(struct net_device *netdev);

extern struct ethtool_ops spider_net_ethtool_ops;

extern char spider_net_driver_name[];

#define SPIDER_NET_MAX_FRAME			2312
#define SPIDER_NET_MAX_MTU			2294
#define SPIDER_NET_MIN_MTU			64

#define SPIDER_NET_RXBUF_ALIGN			128

#define SPIDER_NET_RX_DESCRIPTORS_DEFAULT	256
#define SPIDER_NET_RX_DESCRIPTORS_MIN		16
#define SPIDER_NET_RX_DESCRIPTORS_MAX		512

#define SPIDER_NET_TX_DESCRIPTORS_DEFAULT	256
#define SPIDER_NET_TX_DESCRIPTORS_MIN		16
#define SPIDER_NET_TX_DESCRIPTORS_MAX		512

#define SPIDER_NET_TX_TIMER			20

#define SPIDER_NET_RX_CSUM_DEFAULT		1

#define SPIDER_NET_WATCHDOG_TIMEOUT		50*HZ
#define SPIDER_NET_NAPI_WEIGHT			64

#define SPIDER_NET_FIRMWARE_SEQS	6
#define SPIDER_NET_FIRMWARE_SEQWORDS	1024
#define SPIDER_NET_FIRMWARE_LEN		(SPIDER_NET_FIRMWARE_SEQS * \
					 SPIDER_NET_FIRMWARE_SEQWORDS * \
					 sizeof(u32))
#define SPIDER_NET_FIRMWARE_NAME	"spider_fw.bin"

/** spider_net SMMIO registers */
#define SPIDER_NET_GHIINT0STS		0x00000000
#define SPIDER_NET_GHIINT1STS		0x00000004
#define SPIDER_NET_GHIINT2STS		0x00000008
#define SPIDER_NET_GHIINT0MSK		0x00000010
#define SPIDER_NET_GHIINT1MSK		0x00000014
#define SPIDER_NET_GHIINT2MSK		0x00000018

#define SPIDER_NET_GRESUMINTNUM		0x00000020
#define SPIDER_NET_GREINTNUM		0x00000024

#define SPIDER_NET_GFFRMNUM		0x00000028
#define SPIDER_NET_GFAFRMNUM		0x0000002c
#define SPIDER_NET_GFBFRMNUM		0x00000030
#define SPIDER_NET_GFCFRMNUM		0x00000034
#define SPIDER_NET_GFDFRMNUM		0x00000038

/* clear them (don't use it) */
#define SPIDER_NET_GFREECNNUM		0x0000003c
#define SPIDER_NET_GONETIMENUM		0x00000040

#define SPIDER_NET_GTOUTFRMNUM		0x00000044

#define SPIDER_NET_GTXMDSET		0x00000050
#define SPIDER_NET_GPCCTRL		0x00000054
#define SPIDER_NET_GRXMDSET		0x00000058
#define SPIDER_NET_GIPSECINIT		0x0000005c
#define SPIDER_NET_GFTRESTRT		0x00000060
#define SPIDER_NET_GRXDMAEN		0x00000064
#define SPIDER_NET_GMRWOLCTRL		0x00000068
#define SPIDER_NET_GPCWOPCMD		0x0000006c
#define SPIDER_NET_GPCROPCMD		0x00000070
#define SPIDER_NET_GTTFRMCNT		0x00000078
#define SPIDER_NET_GTESTMD		0x0000007c

#define SPIDER_NET_GSINIT		0x00000080
#define SPIDER_NET_GSnPRGADR		0x00000084
#define SPIDER_NET_GSnPRGDAT		0x00000088

#define SPIDER_NET_GMACOPEMD		0x00000100
#define SPIDER_NET_GMACLENLMT		0x00000108
#define SPIDER_NET_GMACINTEN		0x00000118
#define SPIDER_NET_GMACPHYCTRL		0x00000120

#define SPIDER_NET_GMACAPAUSE		0x00000154
#define SPIDER_NET_GMACTXPAUSE		0x00000164

#define SPIDER_NET_GMACMODE		0x000001b0
#define SPIDER_NET_GMACBSTLMT		0x000001b4

#define SPIDER_NET_GMACUNIMACU		0x000001c0
#define SPIDER_NET_GMACUNIMACL		0x000001c8

#define SPIDER_NET_GMRMHFILnR		0x00000400
#define SPIDER_NET_MULTICAST_HASHES	256

#define SPIDER_NET_GMRUAFILnR		0x00000500
#define SPIDER_NET_GMRUA0FIL15R		0x00000578

#define SPIDER_NET_GTTQMSK		0x00000934

/* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
 * 0x00000b.. for DMA controller B, etc. */
#define SPIDER_NET_GDADCHA		0x00000a00
#define SPIDER_NET_GDADMACCNTR		0x00000a04
#define SPIDER_NET_GDACTDPA		0x00000a08
#define SPIDER_NET_GDACTDCNT		0x00000a0c
#define SPIDER_NET_GDACDBADDR		0x00000a20
#define SPIDER_NET_GDACDBSIZE		0x00000a24
#define SPIDER_NET_GDACNEXTDA		0x00000a28
#define SPIDER_NET_GDACCOMST		0x00000a2c
#define SPIDER_NET_GDAWBCOMST		0x00000a30
#define SPIDER_NET_GDAWBRSIZE		0x00000a34
#define SPIDER_NET_GDAWBVSIZE		0x00000a38
#define SPIDER_NET_GDAWBTRST		0x00000a3c
#define SPIDER_NET_GDAWBTRERR		0x00000a40

/* TX DMA controller registers */
#define SPIDER_NET_GDTDCHA		0x00000e00
#define SPIDER_NET_GDTDMACCNTR		0x00000e04
#define SPIDER_NET_GDTCDPA		0x00000e08
#define SPIDER_NET_GDTDMASEL		0x00000e14

#define SPIDER_NET_ECMODE		0x00000f00
/* clock and reset control register */
#define SPIDER_NET_CKRCTRL		0x00000ff0

/** SCONFIG registers */
#define SPIDER_NET_SCONFIG_IOACTE	0x00002810

/** interrupt mask registers */
#define SPIDER_NET_INT0_MASK_VALUE	0x3f7fe2c7
#define SPIDER_NET_INT1_MASK_VALUE	0xffff7ff7
/* no MAC aborts -> auto retransmission */
#define SPIDER_NET_INT2_MASK_VALUE	0xffef7ff1

/* we rely on flagged descriptor interrupts */
#define SPIDER_NET_FRAMENUM_VALUE	0x00000000
/* set this first, then the FRAMENUM_VALUE */
#define SPIDER_NET_GFXFRAMES_VALUE	0x00000000

#define SPIDER_NET_STOP_SEQ_VALUE	0x00000000
#define SPIDER_NET_RUN_SEQ_VALUE	0x0000007e

#define SPIDER_NET_PHY_CTRL_VALUE	0x00040040
/* #define SPIDER_NET_PHY_CTRL_VALUE	0x01070080*/
#define SPIDER_NET_RXMODE_VALUE		0x00000011
/* auto retransmission in case of MAC aborts */
#define SPIDER_NET_TXMODE_VALUE		0x00010000
#define SPIDER_NET_RESTART_VALUE	0x00000000
#define SPIDER_NET_WOL_VALUE		0x00001111
#if 0
#define SPIDER_NET_WOL_VALUE		0x00000000
#endif
#define SPIDER_NET_IPSECINIT_VALUE	0x6f716f71

/* pause frames: automatic, no upper retransmission count */
/* outside loopback mode: ETOMOD signal dont matter, not connected */
#define SPIDER_NET_OPMODE_VALUE		0x00000063
/*#define SPIDER_NET_OPMODE_VALUE		0x001b0062*/
#define SPIDER_NET_LENLMT_VALUE		0x00000908

#define SPIDER_NET_MACAPAUSE_VALUE	0x00000800 /* about 1 ms */
#define SPIDER_NET_TXPAUSE_VALUE	0x00000000

#define SPIDER_NET_MACMODE_VALUE	0x00000001
#define SPIDER_NET_BURSTLMT_VALUE	0x00000200 /* about 16 us */

/* 1(0)					enable r/tx dma
 *  0000000				fixed to 0
 *
 *         000000			fixed to 0
 *               0(1)			en/disable descr writeback on force end
 *                0(1)			force end
 *
 *                 000000		fixed to 0
 *                       00		burst alignment: 128 bytes
 *
 *                         00000	fixed to 0
 *                              0	descr writeback size 32 bytes
 *                               0(1)	descr chain end interrupt enable
 *                                0(1)	descr status writeback enable */

/* to set RX_DMA_EN */
#define SPIDER_NET_DMA_RX_VALUE		0x80000000
#define SPIDER_NET_DMA_RX_FEND_VALUE	0x00030003
/* to set TX_DMA_EN */
#define SPIDER_NET_DMA_TX_VALUE		0x80000000
#define SPIDER_NET_DMA_TX_FEND_VALUE	0x00030003

/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
#define SPIDER_NET_UA_DESCR_VALUE	0x00080000
#define SPIDER_NET_PROMISC_VALUE	0x00080000
#define SPIDER_NET_NONPROMISC_VALUE	0x00000000

#define SPIDER_NET_DMASEL_VALUE		0x00000001

#define SPIDER_NET_ECMODE_VALUE		0x00000000

#define SPIDER_NET_CKRCTRL_RUN_VALUE	0x1fff010f
#define SPIDER_NET_CKRCTRL_STOP_VALUE	0x0000010f

#define SPIDER_NET_SBIMSTATE_VALUE	0x00000000
#define SPIDER_NET_SBTMSTATE_VALUE	0x00000000

/* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
 * with 1 << SPIDER_NET_... */
enum spider_net_int0_status {
	SPIDER_NET_GPHYINT = 0,
	SPIDER_NET_GMAC2INT,
	SPIDER_NET_GMAC1INT,
	SPIDER_NET_GIPSINT,
	SPIDER_NET_GFIFOINT,
	SPIDER_NET_GDMACINT,
	SPIDER_NET_GSYSINT,
	SPIDER_NET_GPWOPCMPINT,
	SPIDER_NET_GPROPCMPINT,
	SPIDER_NET_GPWFFINT,
	SPIDER_NET_GRMDADRINT,
	SPIDER_NET_GRMARPINT,
	SPIDER_NET_GRMMPINT,
	SPIDER_NET_GDTDEN0INT,
	SPIDER_NET_GDDDEN0INT,
	SPIDER_NET_GDCDEN0INT,
	SPIDER_NET_GDBDEN0INT,
	SPIDER_NET_GDADEN0INT,
	SPIDER_NET_GDTFDCINT,
	SPIDER_NET_GDDFDCINT,
	SPIDER_NET_GDCFDCINT,
	SPIDER_NET_GDBFDCINT,
	SPIDER_NET_GDAFDCINT,
	SPIDER_NET_GTTEDINT,
	SPIDER_NET_GDTDCEINT,
	SPIDER_NET_GRFDNMINT,
	SPIDER_NET_GRFCNMINT,
	SPIDER_NET_GRFBNMINT,
	SPIDER_NET_GRFANMINT,
	SPIDER_NET_GRFNMINT,
	SPIDER_NET_G1TMCNTINT,
	SPIDER_NET_GFREECNTINT
};
/* GHIINT1STS bits */
enum spider_net_int1_status {
	SPIDER_NET_GTMFLLINT = 0,
	SPIDER_NET_GRMFLLINT,
	SPIDER_NET_GTMSHTINT,
	SPIDER_NET_GDTINVDINT,
	SPIDER_NET_GRFDFLLINT,
	SPIDER_NET_GDDDCEINT,
	SPIDER_NET_GDDINVDINT,
	SPIDER_NET_GRFCFLLINT,
	SPIDER_NET_GDCDCEINT,
	SPIDER_NET_GDCINVDINT,
	SPIDER_NET_GRFBFLLINT,
	SPIDER_NET_GDBDCEINT,
	SPIDER_NET_GDBINVDINT,
	SPIDER_NET_GRFAFLLINT,
	SPIDER_NET_GDADCEINT,
	SPIDER_NET_GDAINVDINT,
	SPIDER_NET_GDTRSERINT,
	SPIDER_NET_GDDRSERINT,
	SPIDER_NET_GDCRSERINT,
	SPIDER_NET_GDBRSERINT,
	SPIDER_NET_GDARSERINT,
	SPIDER_NET_GDSERINT,
	SPIDER_NET_GDTPTERINT,
	SPIDER_NET_GDDPTERINT,
	SPIDER_NET_GDCPTERINT,
	SPIDER_NET_GDBPTERINT,
	SPIDER_NET_GDAPTERINT
};
/* GHIINT2STS bits */
enum spider_net_int2_status {
	SPIDER_NET_GPROPERINT = 0,
	SPIDER_NET_GMCTCRSNGINT,
	SPIDER_NET_GMCTLCOLINT,
	SPIDER_NET_GMCTTMOTINT,
	SPIDER_NET_GMCRCAERINT,
	SPIDER_NET_GMCRCALERINT,
	SPIDER_NET_GMCRALNERINT,
	SPIDER_NET_GMCROVRINT,
	SPIDER_NET_GMCRRNTINT,
	SPIDER_NET_GMCRRXERINT,
	SPIDER_NET_GTITCSERINT,
	SPIDER_NET_GTIFMTERINT,
	SPIDER_NET_GTIPKTRVKINT,
	SPIDER_NET_GTISPINGINT,
	SPIDER_NET_GTISADNGINT,
	SPIDER_NET_GTISPDNGINT,
	SPIDER_NET_GRIFMTERINT,
	SPIDER_NET_GRIPKTRVKINT,
	SPIDER_NET_GRISPINGINT,
	SPIDER_NET_GRISADNGINT,
	SPIDER_NET_GRISPDNGINT
};

#define SPIDER_NET_TXINT	( (1 << SPIDER_NET_GTTEDINT) | \
				  (1 << SPIDER_NET_GDTDCEINT) | \
				  (1 << SPIDER_NET_GDTFDCINT) )

/* we rely on flagged descriptor interrupts*/
#define SPIDER_NET_RXINT	( (1 << SPIDER_NET_GDAFDCINT) | \
				  (1 << SPIDER_NET_GRMFLLINT) )

#define SPIDER_NET_ERRINT	( 0xffffffff & \
				  (~SPIDER_NET_TXINT) & \
				  (~SPIDER_NET_RXINT) )

#define SPIDER_NET_GPREXEC		0x80000000
#define SPIDER_NET_GPRDAT_MASK		0x0000ffff

/* descriptor bits
 *
 * 1010					descriptor ready
 *     0				descr in middle of chain
 *      000				fixed to 0
 *
 *         0				no interrupt on completion
 *          000				fixed to 0
 *             1			no ipsec processing
 *              1			last descriptor for this frame
 *               00			no checksum
 *               10			tcp checksum
 *               11			udp checksum
 *
 *                 00			fixed to 0
 *                   0			fixed to 0
 *                    0			no interrupt on response errors
 *                     0		no interrupt on invalid descr
 *                      0		no interrupt on dma process termination
 *                       0		no interrupt on descr chain end
 *                        0		no interrupt on descr complete
 *
 *                         000		fixed to 0
 *                            0		response error interrupt status
 *                             0	invalid descr status
 *                              0	dma termination status
 *                               0	descr chain end status
 *                                0	descr complete status */
#define SPIDER_NET_DMAC_CMDSTAT_NOCS	0xa00c0000
#define SPIDER_NET_DMAC_CMDSTAT_TCPCS	0xa00e0000
#define SPIDER_NET_DMAC_CMDSTAT_UDPCS	0xa00f0000
#define SPIDER_NET_DESCR_IND_PROC_SHIFT	28
#define SPIDER_NET_DESCR_IND_PROC_MASKO	0x0fffffff

/* descr ready, descr is in middle of chain, get interrupt on completion */
#define SPIDER_NET_DMAC_RX_CARDOWNED	0xa0800000

enum spider_net_descr_status {
	SPIDER_NET_DESCR_COMPLETE		= 0x00, /* used in rx and tx */
	SPIDER_NET_DESCR_RESPONSE_ERROR		= 0x01, /* used in rx and tx */
	SPIDER_NET_DESCR_PROTECTION_ERROR	= 0x02, /* used in rx and tx */
	SPIDER_NET_DESCR_FRAME_END		= 0x04, /* used in rx */
	SPIDER_NET_DESCR_FORCE_END		= 0x05, /* used in rx and tx */
	SPIDER_NET_DESCR_CARDOWNED		= 0x0a, /* used in rx and tx */
	SPIDER_NET_DESCR_NOT_IN_USE /* any other value */
};

struct spider_net_descr {
	/* as defined by the hardware */
	u32 buf_addr;
	u32 buf_size;
	u32 next_descr_addr;
	u32 dmac_cmd_status;
	u32 result_size;
	u32 valid_size;	/* all zeroes for tx */
	u32 data_status;
	u32 data_error;	/* all zeroes for tx */

	/* used in the driver */
	struct sk_buff *skb;
	u32 bus_addr;
	struct spider_net_descr *next;
	struct spider_net_descr *prev;
} __attribute__((aligned(32)));

struct spider_net_descr_chain {
	/* we walk from tail to head */
	struct spider_net_descr *head;
	struct spider_net_descr *tail;
};

/* descriptor data_status bits */
#define SPIDER_NET_RX_IPCHK		29
#define SPIDER_NET_RX_TCPCHK		28
#define SPIDER_NET_VLAN_PACKET		21
#define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \
					  (1 << SPIDER_NET_RX_TCPCHK) )

/* descriptor data_error bits */
#define SPIDER_NET_RX_IPCHKERR		27
#define SPIDER_NET_RX_RXTCPCHKERR	28

#define SPIDER_NET_DATA_ERR_CKSUM_MASK	(1 << SPIDER_NET_RX_IPCHKERR)

/* the cases we don't pass the packet to the stack.
 * 701b8000 would be correct, but every packets gets that flag */
#define SPIDER_NET_DESTROY_RX_FLAGS	0x700b8000

#define SPIDER_NET_DESCR_SIZE		32

/* this will be bigger some time */
struct spider_net_options {
	int rx_csum; /* for rx: if 0 ip_summed=NONE,
			if 1 and hw has verified, ip_summed=UNNECESSARY */
};

#define SPIDER_NET_DEFAULT_MSG		( NETIF_MSG_DRV | \
					  NETIF_MSG_PROBE | \
					  NETIF_MSG_LINK | \
					  NETIF_MSG_TIMER | \
					  NETIF_MSG_IFDOWN | \
					  NETIF_MSG_IFUP | \
					  NETIF_MSG_RX_ERR | \
					  NETIF_MSG_TX_ERR | \
					  NETIF_MSG_TX_QUEUED | \
					  NETIF_MSG_INTR | \
					  NETIF_MSG_TX_DONE | \
					  NETIF_MSG_RX_STATUS | \
					  NETIF_MSG_PKTDATA | \
					  NETIF_MSG_HW | \
					  NETIF_MSG_WOL )

struct spider_net_card {
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct mii_phy phy;

	void __iomem *regs;

	struct spider_net_descr_chain tx_chain;
	struct spider_net_descr_chain rx_chain;
	atomic_t rx_chain_refill;
	atomic_t tx_chain_release;

	struct net_device_stats netdev_stats;

	struct spider_net_options options;

	spinlock_t intmask_lock;
	struct tasklet_struct rxram_full_tl;
	struct timer_list tx_timer;

	struct work_struct tx_timeout_task;
	atomic_t tx_timeout_task_counter;
	wait_queue_head_t waitq;

	/* for ethtool */
	int msg_enable;

	struct spider_net_descr descr[0];
};

#define pr_err(fmt,arg...) \
	printk(KERN_ERR fmt ,##arg)

#endif
Commit	Line	Data
aaec0fab JO	1	/*
	2	* Network device driver for Cell Processor-Based Blade
	3	*
	4	* (C) Copyright IBM Corp. 2005
	5	*
	6	* Authors : Utz Bacher <utz.bacher@de.ibm.com>
	7	* Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2, or (at your option)
	12	* any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	22	*/
	23
	24	#ifndef _SPIDER_NET_H
	25	#define _SPIDER_NET_H
	26
	27	#include "sungem_phy.h"
	28
	29	extern int spider_net_stop(struct net_device *netdev);
	30	extern int spider_net_open(struct net_device *netdev);
	31
	32	extern struct ethtool_ops spider_net_ethtool_ops;
	33
	34	extern char spider_net_driver_name[];
	35
11f1a52b AB	36	#define SPIDER_NET_MAX_FRAME 2312
11f1a52b AB	37	#define SPIDER_NET_MAX_MTU 2294
aaec0fab JO	38	#define SPIDER_NET_MIN_MTU 64
	39
	40	#define SPIDER_NET_RXBUF_ALIGN 128
	41
11f1a52b	42	#define SPIDER_NET_RX_DESCRIPTORS_DEFAULT 256
aaec0fab	43	#define SPIDER_NET_RX_DESCRIPTORS_MIN 16
11f1a52b	44	#define SPIDER_NET_RX_DESCRIPTORS_MAX 512
aaec0fab	45
11f1a52b	46	#define SPIDER_NET_TX_DESCRIPTORS_DEFAULT 256
aaec0fab	47	#define SPIDER_NET_TX_DESCRIPTORS_MIN 16
11f1a52b AB	48	#define SPIDER_NET_TX_DESCRIPTORS_MAX 512
	49
	50	#define SPIDER_NET_TX_TIMER 20
aaec0fab JO	51
	52	#define SPIDER_NET_RX_CSUM_DEFAULT 1
	53
11f1a52b AB	54	#define SPIDER_NET_WATCHDOG_TIMEOUT 50*HZ
11f1a52b AB	55	#define SPIDER_NET_NAPI_WEIGHT 64
aaec0fab	56
11f1a52b AB	57	#define SPIDER_NET_FIRMWARE_SEQS 6
	58	#define SPIDER_NET_FIRMWARE_SEQWORDS 1024
	59	#define SPIDER_NET_FIRMWARE_LEN (SPIDER_NET_FIRMWARE_SEQS * \
	60	SPIDER_NET_FIRMWARE_SEQWORDS * \
	61	sizeof(u32))
aaec0fab JO	62	#define SPIDER_NET_FIRMWARE_NAME "spider_fw.bin"
	63
	64	/** spider_net SMMIO registers */
	65	#define SPIDER_NET_GHIINT0STS 0x00000000
	66	#define SPIDER_NET_GHIINT1STS 0x00000004
	67	#define SPIDER_NET_GHIINT2STS 0x00000008
	68	#define SPIDER_NET_GHIINT0MSK 0x00000010
	69	#define SPIDER_NET_GHIINT1MSK 0x00000014
	70	#define SPIDER_NET_GHIINT2MSK 0x00000018
	71
	72	#define SPIDER_NET_GRESUMINTNUM 0x00000020
	73	#define SPIDER_NET_GREINTNUM 0x00000024
	74
	75	#define SPIDER_NET_GFFRMNUM 0x00000028
	76	#define SPIDER_NET_GFAFRMNUM 0x0000002c
	77	#define SPIDER_NET_GFBFRMNUM 0x00000030
	78	#define SPIDER_NET_GFCFRMNUM 0x00000034
	79	#define SPIDER_NET_GFDFRMNUM 0x00000038
	80
	81	/* clear them (don't use it) */
	82	#define SPIDER_NET_GFREECNNUM 0x0000003c
	83	#define SPIDER_NET_GONETIMENUM 0x00000040
	84
	85	#define SPIDER_NET_GTOUTFRMNUM 0x00000044
	86
	87	#define SPIDER_NET_GTXMDSET 0x00000050
	88	#define SPIDER_NET_GPCCTRL 0x00000054
	89	#define SPIDER_NET_GRXMDSET 0x00000058
	90	#define SPIDER_NET_GIPSECINIT 0x0000005c
	91	#define SPIDER_NET_GFTRESTRT 0x00000060
	92	#define SPIDER_NET_GRXDMAEN 0x00000064
	93	#define SPIDER_NET_GMRWOLCTRL 0x00000068
	94	#define SPIDER_NET_GPCWOPCMD 0x0000006c
	95	#define SPIDER_NET_GPCROPCMD 0x00000070
	96	#define SPIDER_NET_GTTFRMCNT 0x00000078
	97	#define SPIDER_NET_GTESTMD 0x0000007c
	98
	99	#define SPIDER_NET_GSINIT 0x00000080
	100	#define SPIDER_NET_GSnPRGADR 0x00000084
	101	#define SPIDER_NET_GSnPRGDAT 0x00000088
	102
	103	#define SPIDER_NET_GMACOPEMD 0x00000100
	104	#define SPIDER_NET_GMACLENLMT 0x00000108
	105	#define SPIDER_NET_GMACINTEN 0x00000118
	106	#define SPIDER_NET_GMACPHYCTRL 0x00000120
	107
	108	#define SPIDER_NET_GMACAPAUSE 0x00000154
	109	#define SPIDER_NET_GMACTXPAUSE 0x00000164
	110
	111	#define SPIDER_NET_GMACMODE 0x000001b0
	112	#define SPIDER_NET_GMACBSTLMT 0x000001b4
	113
	114	#define SPIDER_NET_GMACUNIMACU 0x000001c0
	115	#define SPIDER_NET_GMACUNIMACL 0x000001c8
	116
	117	#define SPIDER_NET_GMRMHFILnR 0x00000400
	118	#define SPIDER_NET_MULTICAST_HASHES 256
	119
	120	#define SPIDER_NET_GMRUAFILnR 0x00000500
	121	#define SPIDER_NET_GMRUA0FIL15R 0x00000578
	122
b636d17a JO	123	#define SPIDER_NET_GTTQMSK 0x00000934
b636d17a JO	124
aaec0fab JO	125	/* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
	126	* 0x00000b.. for DMA controller B, etc. */
	127	#define SPIDER_NET_GDADCHA 0x00000a00
	128	#define SPIDER_NET_GDADMACCNTR 0x00000a04
	129	#define SPIDER_NET_GDACTDPA 0x00000a08
	130	#define SPIDER_NET_GDACTDCNT 0x00000a0c
	131	#define SPIDER_NET_GDACDBADDR 0x00000a20
	132	#define SPIDER_NET_GDACDBSIZE 0x00000a24
	133	#define SPIDER_NET_GDACNEXTDA 0x00000a28
	134	#define SPIDER_NET_GDACCOMST 0x00000a2c
	135	#define SPIDER_NET_GDAWBCOMST 0x00000a30
	136	#define SPIDER_NET_GDAWBRSIZE 0x00000a34
	137	#define SPIDER_NET_GDAWBVSIZE 0x00000a38
	138	#define SPIDER_NET_GDAWBTRST 0x00000a3c
	139	#define SPIDER_NET_GDAWBTRERR 0x00000a40
	140
	141	/* TX DMA controller registers */
	142	#define SPIDER_NET_GDTDCHA 0x00000e00
	143	#define SPIDER_NET_GDTDMACCNTR 0x00000e04
	144	#define SPIDER_NET_GDTCDPA 0x00000e08
	145	#define SPIDER_NET_GDTDMASEL 0x00000e14
	146
	147	#define SPIDER_NET_ECMODE 0x00000f00
	148	/* clock and reset control register */
	149	#define SPIDER_NET_CKRCTRL 0x00000ff0
	150
	151	/** SCONFIG registers */
	152	#define SPIDER_NET_SCONFIG_IOACTE 0x00002810
	153
11f1a52b AB	154	/** interrupt mask registers */
	155	#define SPIDER_NET_INT0_MASK_VALUE 0x3f7fe2c7
	156	#define SPIDER_NET_INT1_MASK_VALUE 0xffff7ff7
aaec0fab	157	/* no MAC aborts -> auto retransmission */
11f1a52b	158	#define SPIDER_NET_INT2_MASK_VALUE 0xffef7ff1
aaec0fab	159
aaec0fab JO	160	/* we rely on flagged descriptor interrupts */
	161	#define SPIDER_NET_FRAMENUM_VALUE 0x00000000
	162	/* set this first, then the FRAMENUM_VALUE */
	163	#define SPIDER_NET_GFXFRAMES_VALUE 0x00000000
	164
	165	#define SPIDER_NET_STOP_SEQ_VALUE 0x00000000
	166	#define SPIDER_NET_RUN_SEQ_VALUE 0x0000007e
	167
	168	#define SPIDER_NET_PHY_CTRL_VALUE 0x00040040
	169	/* #define SPIDER_NET_PHY_CTRL_VALUE 0x01070080*/
	170	#define SPIDER_NET_RXMODE_VALUE 0x00000011
	171	/* auto retransmission in case of MAC aborts */
	172	#define SPIDER_NET_TXMODE_VALUE 0x00010000
	173	#define SPIDER_NET_RESTART_VALUE 0x00000000
	174	#define SPIDER_NET_WOL_VALUE 0x00001111
	175	#if 0
	176	#define SPIDER_NET_WOL_VALUE 0x00000000
	177	#endif
11f1a52b	178	#define SPIDER_NET_IPSECINIT_VALUE 0x6f716f71
aaec0fab JO	179
	180	/* pause frames: automatic, no upper retransmission count */
	181	/* outside loopback mode: ETOMOD signal dont matter, not connected */
	182	#define SPIDER_NET_OPMODE_VALUE 0x00000063
	183	/#define SPIDER_NET_OPMODE_VALUE 0x001b0062/
	184	#define SPIDER_NET_LENLMT_VALUE 0x00000908
	185
	186	#define SPIDER_NET_MACAPAUSE_VALUE 0x00000800 /* about 1 ms */
	187	#define SPIDER_NET_TXPAUSE_VALUE 0x00000000
	188
	189	#define SPIDER_NET_MACMODE_VALUE 0x00000001
	190	#define SPIDER_NET_BURSTLMT_VALUE 0x00000200 /* about 16 us */
	191
	192	/* 1(0) enable r/tx dma
	193	* 0000000 fixed to 0
	194	*
	195	* 000000 fixed to 0
	196	* 0(1) en/disable descr writeback on force end
	197	* 0(1) force end
	198	*
	199	* 000000 fixed to 0
	200	* 00 burst alignment: 128 bytes
	201	*
	202	* 00000 fixed to 0
	203	* 0 descr writeback size 32 bytes
	204	* 0(1) descr chain end interrupt enable
	205	* 0(1) descr status writeback enable */
	206
	207	/* to set RX_DMA_EN */
	208	#define SPIDER_NET_DMA_RX_VALUE 0x80000000
	209	#define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003
	210	/* to set TX_DMA_EN */
	211	#define SPIDER_NET_DMA_TX_VALUE 0x80000000
	212	#define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003
	213
	214	/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
	215	#define SPIDER_NET_UA_DESCR_VALUE 0x00080000
	216	#define SPIDER_NET_PROMISC_VALUE 0x00080000
	217	#define SPIDER_NET_NONPROMISC_VALUE 0x00000000
	218
	219	#define SPIDER_NET_DMASEL_VALUE 0x00000001
	220
	221	#define SPIDER_NET_ECMODE_VALUE 0x00000000
	222
	223	#define SPIDER_NET_CKRCTRL_RUN_VALUE 0x1fff010f
	224	#define SPIDER_NET_CKRCTRL_STOP_VALUE 0x0000010f
	225
	226	#define SPIDER_NET_SBIMSTATE_VALUE 0x00000000
	227	#define SPIDER_NET_SBTMSTATE_VALUE 0x00000000
	228
	229	/* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
	230	* with 1 << SPIDER_NET_... */
	231	enum spider_net_int0_status {
	232	SPIDER_NET_GPHYINT = 0,
	233	SPIDER_NET_GMAC2INT,
	234	SPIDER_NET_GMAC1INT,
	235	SPIDER_NET_GIPSINT,
	236	SPIDER_NET_GFIFOINT,
	237	SPIDER_NET_GDMACINT,
	238	SPIDER_NET_GSYSINT,
	239	SPIDER_NET_GPWOPCMPINT,
	240	SPIDER_NET_GPROPCMPINT,
	241	SPIDER_NET_GPWFFINT,
	242	SPIDER_NET_GRMDADRINT,
243	SPIDER_NET_GRMARPINT,
244	SPIDER_NET_GRMMPINT,
245	SPIDER_NET_GDTDEN0INT,
246	SPIDER_NET_GDDDEN0INT,
247	SPIDER_NET_GDCDEN0INT,
248	SPIDER_NET_GDBDEN0INT,
249	SPIDER_NET_GDADEN0INT,
250	SPIDER_NET_GDTFDCINT,
251	SPIDER_NET_GDDFDCINT,
252	SPIDER_NET_GDCFDCINT,
253	SPIDER_NET_GDBFDCINT,
254	SPIDER_NET_GDAFDCINT,
255	SPIDER_NET_GTTEDINT,
256	SPIDER_NET_GDTDCEINT,
257	SPIDER_NET_GRFDNMINT,
258	SPIDER_NET_GRFCNMINT,
259	SPIDER_NET_GRFBNMINT,
260	SPIDER_NET_GRFANMINT,
261	SPIDER_NET_GRFNMINT,
262	SPIDER_NET_G1TMCNTINT,
263	SPIDER_NET_GFREECNTINT
264	};
265	/* GHIINT1STS bits */
266	enum spider_net_int1_status {
267	SPIDER_NET_GTMFLLINT = 0,
268	SPIDER_NET_GRMFLLINT,
269	SPIDER_NET_GTMSHTINT,
270	SPIDER_NET_GDTINVDINT,
271	SPIDER_NET_GRFDFLLINT,
272	SPIDER_NET_GDDDCEINT,
273	SPIDER_NET_GDDINVDINT,
274	SPIDER_NET_GRFCFLLINT,
275	SPIDER_NET_GDCDCEINT,
276	SPIDER_NET_GDCINVDINT,
277	SPIDER_NET_GRFBFLLINT,
278	SPIDER_NET_GDBDCEINT,
279	SPIDER_NET_GDBINVDINT,
280	SPIDER_NET_GRFAFLLINT,
281	SPIDER_NET_GDADCEINT,
282	SPIDER_NET_GDAINVDINT,
283	SPIDER_NET_GDTRSERINT,
284	SPIDER_NET_GDDRSERINT,
285	SPIDER_NET_GDCRSERINT,
286	SPIDER_NET_GDBRSERINT,
287	SPIDER_NET_GDARSERINT,
288	SPIDER_NET_GDSERINT,
289	SPIDER_NET_GDTPTERINT,
290	SPIDER_NET_GDDPTERINT,
291	SPIDER_NET_GDCPTERINT,
292	SPIDER_NET_GDBPTERINT,
293	SPIDER_NET_GDAPTERINT
294	};
295	/* GHIINT2STS bits */
296	enum spider_net_int2_status {
297	SPIDER_NET_GPROPERINT = 0,
298	SPIDER_NET_GMCTCRSNGINT,
299	SPIDER_NET_GMCTLCOLINT,
300	SPIDER_NET_GMCTTMOTINT,
301	SPIDER_NET_GMCRCAERINT,
302	SPIDER_NET_GMCRCALERINT,
303	SPIDER_NET_GMCRALNERINT,
304	SPIDER_NET_GMCROVRINT,
305	SPIDER_NET_GMCRRNTINT,
306	SPIDER_NET_GMCRRXERINT,
307	SPIDER_NET_GTITCSERINT,
308	SPIDER_NET_GTIFMTERINT,
309	SPIDER_NET_GTIPKTRVKINT,
310	SPIDER_NET_GTISPINGINT,
311	SPIDER_NET_GTISADNGINT,
312	SPIDER_NET_GTISPDNGINT,
313	SPIDER_NET_GRIFMTERINT,
314	SPIDER_NET_GRIPKTRVKINT,
315	SPIDER_NET_GRISPINGINT,
316	SPIDER_NET_GRISADNGINT,
317	SPIDER_NET_GRISPDNGINT
318	};
319
320	#define SPIDER_NET_TXINT ( (1 << SPIDER_NET_GTTEDINT) \| \
321	(1 << SPIDER_NET_GDTDCEINT) \| \
322	(1 << SPIDER_NET_GDTFDCINT) )
323
324	/* we rely on flagged descriptor interrupts*/
325	#define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) \| \
326	(1 << SPIDER_NET_GRMFLLINT) )
327
11f1a52b AB	328	#define SPIDER_NET_ERRINT ( 0xffffffff & \
	329	(~SPIDER_NET_TXINT) & \
	330	(~SPIDER_NET_RXINT) )
	331
aaec0fab JO	332	#define SPIDER_NET_GPREXEC 0x80000000
	333	#define SPIDER_NET_GPRDAT_MASK 0x0000ffff
	334
	335	/* descriptor bits
	336	*
	337	* 1010 descriptor ready
	338	* 0 descr in middle of chain
	339	* 000 fixed to 0
	340	*
	341	* 0 no interrupt on completion
	342	* 000 fixed to 0
	343	* 1 no ipsec processing
	344	* 1 last descriptor for this frame
	345	* 00 no checksum
	346	* 10 tcp checksum
	347	* 11 udp checksum
	348	*
	349	* 00 fixed to 0
	350	* 0 fixed to 0
	351	* 0 no interrupt on response errors
	352	* 0 no interrupt on invalid descr
	353	* 0 no interrupt on dma process termination
	354	* 0 no interrupt on descr chain end
	355	* 0 no interrupt on descr complete
	356	*
	357	* 000 fixed to 0
	358	* 0 response error interrupt status
	359	* 0 invalid descr status
	360	* 0 dma termination status
	361	* 0 descr chain end status
	362	* 0 descr complete status */
	363	#define SPIDER_NET_DMAC_CMDSTAT_NOCS 0xa00c0000
	364	#define SPIDER_NET_DMAC_CMDSTAT_TCPCS 0xa00e0000
	365	#define SPIDER_NET_DMAC_CMDSTAT_UDPCS 0xa00f0000
	366	#define SPIDER_NET_DESCR_IND_PROC_SHIFT 28
	367	#define SPIDER_NET_DESCR_IND_PROC_MASKO 0x0fffffff
	368
	369	/* descr ready, descr is in middle of chain, get interrupt on completion */
	370	#define SPIDER_NET_DMAC_RX_CARDOWNED 0xa0800000
	371
aaec0fab JO	372	enum spider_net_descr_status {
	373	SPIDER_NET_DESCR_COMPLETE = 0x00, /* used in rx and tx */
	374	SPIDER_NET_DESCR_RESPONSE_ERROR = 0x01, /* used in rx and tx */
	375	SPIDER_NET_DESCR_PROTECTION_ERROR = 0x02, /* used in rx and tx */
	376	SPIDER_NET_DESCR_FRAME_END = 0x04, /* used in rx */
	377	SPIDER_NET_DESCR_FORCE_END = 0x05, /* used in rx and tx */
	378	SPIDER_NET_DESCR_CARDOWNED = 0x0a, /* used in rx and tx */
	379	SPIDER_NET_DESCR_NOT_IN_USE /* any other value */
	380	};
	381
	382	struct spider_net_descr {
	383	/* as defined by the hardware */
8e0a613b	384	u32 buf_addr;
aaec0fab	385	u32 buf_size;
8e0a613b	386	u32 next_descr_addr;
aaec0fab JO	387	u32 dmac_cmd_status;
	388	u32 result_size;
	389	u32 valid_size; /* all zeroes for tx */
	390	u32 data_status;
	391	u32 data_error; /* all zeroes for tx */
	392
	393	/* used in the driver */
	394	struct sk_buff *skb;
11f1a52b	395	u32 bus_addr;
aaec0fab JO	396	struct spider_net_descr *next;
	397	struct spider_net_descr *prev;
	398	} __attribute__((aligned(32)));
	399
	400	struct spider_net_descr_chain {
	401	/* we walk from tail to head */
	402	struct spider_net_descr *head;
	403	struct spider_net_descr *tail;
	404	};
	405
	406	/* descriptor data_status bits */
11f1a52b AB	407	#define SPIDER_NET_RX_IPCHK 29
11f1a52b AB	408	#define SPIDER_NET_RX_TCPCHK 28
aaec0fab	409	#define SPIDER_NET_VLAN_PACKET 21
11f1a52b AB	410	#define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) \| \
11f1a52b AB	411	(1 << SPIDER_NET_RX_TCPCHK) )
aaec0fab JO	412
aaec0fab JO	413	/* descriptor data_error bits */
11f1a52b AB	414	#define SPIDER_NET_RX_IPCHKERR 27
	415	#define SPIDER_NET_RX_RXTCPCHKERR 28
	416
	417	#define SPIDER_NET_DATA_ERR_CKSUM_MASK (1 << SPIDER_NET_RX_IPCHKERR)
aaec0fab	418
11f1a52b AB	419	/* the cases we don't pass the packet to the stack.
	420	* 701b8000 would be correct, but every packets gets that flag */
	421	#define SPIDER_NET_DESTROY_RX_FLAGS 0x700b8000
aaec0fab JO	422
	423	#define SPIDER_NET_DESCR_SIZE 32
	424
	425	/* this will be bigger some time */
	426	struct spider_net_options {
	427	int rx_csum; /* for rx: if 0 ip_summed=NONE,
	428	if 1 and hw has verified, ip_summed=UNNECESSARY */
	429	};
	430
	431	#define SPIDER_NET_DEFAULT_MSG ( NETIF_MSG_DRV \| \
	432	NETIF_MSG_PROBE \| \
	433	NETIF_MSG_LINK \| \
	434	NETIF_MSG_TIMER \| \
	435	NETIF_MSG_IFDOWN \| \
	436	NETIF_MSG_IFUP \| \
	437	NETIF_MSG_RX_ERR \| \
	438	NETIF_MSG_TX_ERR \| \
	439	NETIF_MSG_TX_QUEUED \| \
	440	NETIF_MSG_INTR \| \
	441	NETIF_MSG_TX_DONE \| \
	442	NETIF_MSG_RX_STATUS \| \
	443	NETIF_MSG_PKTDATA \| \
	444	NETIF_MSG_HW \| \
	445	NETIF_MSG_WOL )
	446
	447	struct spider_net_card {
	448	struct net_device *netdev;
	449	struct pci_dev *pdev;
	450	struct mii_phy phy;
	451
	452	void __iomem *regs;
	453
	454	struct spider_net_descr_chain tx_chain;
	455	struct spider_net_descr_chain rx_chain;
11f1a52b AB	456	atomic_t rx_chain_refill;
11f1a52b AB	457	atomic_t tx_chain_release;
aaec0fab JO	458
	459	struct net_device_stats netdev_stats;
	460
	461	struct spider_net_options options;
	462
	463	spinlock_t intmask_lock;
11f1a52b AB	464	struct tasklet_struct rxram_full_tl;
11f1a52b AB	465	struct timer_list tx_timer;
aaec0fab JO	466
	467	struct work_struct tx_timeout_task;
	468	atomic_t tx_timeout_task_counter;
	469	wait_queue_head_t waitq;
	470
	471	/* for ethtool */
	472	int msg_enable;
	473
	474	struct spider_net_descr descr[0];
	475	};
	476
	477	#define pr_err(fmt,arg...) \
	478	printk(KERN_ERR fmt ,##arg)
	479
	480	#endif