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1da177e4 LT |
1 | /*------------------------------------------------------------------------ |
2 | . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. | |
3 | . | |
4 | . Copyright (C) 1996 by Erik Stahlman | |
5 | . Copyright (C) 2001 Standard Microsystems Corporation | |
6 | . Developed by Simple Network Magic Corporation | |
7 | . Copyright (C) 2003 Monta Vista Software, Inc. | |
8 | . Unified SMC91x driver by Nicolas Pitre | |
9 | . | |
10 | . This program is free software; you can redistribute it and/or modify | |
11 | . it under the terms of the GNU General Public License as published by | |
12 | . the Free Software Foundation; either version 2 of the License, or | |
13 | . (at your option) any later version. | |
14 | . | |
15 | . This program is distributed in the hope that it will be useful, | |
16 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | . GNU General Public License for more details. | |
19 | . | |
20 | . You should have received a copy of the GNU General Public License | |
21 | . along with this program; if not, write to the Free Software | |
22 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | . | |
24 | . Information contained in this file was obtained from the LAN91C111 | |
25 | . manual from SMC. To get a copy, if you really want one, you can find | |
26 | . information under www.smsc.com. | |
27 | . | |
28 | . Authors | |
29 | . Erik Stahlman <erik@vt.edu> | |
30 | . Daris A Nevil <dnevil@snmc.com> | |
31 | . Nicolas Pitre <nico@cam.org> | |
32 | . | |
33 | ---------------------------------------------------------------------------*/ | |
34 | #ifndef _SMC91X_H_ | |
35 | #define _SMC91X_H_ | |
36 | ||
37 | ||
38 | /* | |
39 | * Define your architecture specific bus configuration parameters here. | |
40 | */ | |
41 | ||
42 | #if defined(CONFIG_ARCH_LUBBOCK) | |
43 | ||
44 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
45 | #define SMC_CAN_USE_8BIT 0 | |
46 | #define SMC_CAN_USE_16BIT 1 | |
47 | #define SMC_CAN_USE_32BIT 0 | |
48 | #define SMC_NOWAIT 1 | |
49 | ||
50 | /* The first two address lines aren't connected... */ | |
51 | #define SMC_IO_SHIFT 2 | |
52 | ||
53 | #define SMC_inw(a, r) readw((a) + (r)) | |
54 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
55 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
56 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
57 | ||
58 | #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) | |
59 | ||
60 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
61 | #define SMC_CAN_USE_8BIT 0 | |
62 | #define SMC_CAN_USE_16BIT 1 | |
63 | #define SMC_CAN_USE_32BIT 0 | |
64 | #define SMC_NOWAIT 1 | |
65 | ||
66 | #define SMC_IO_SHIFT 0 | |
67 | ||
68 | #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r))) | |
69 | #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v) | |
70 | #define SMC_insw(a, r, p, l) \ | |
71 | do { \ | |
72 | unsigned long __port = (a) + (r); \ | |
73 | u16 *__p = (u16 *)(p); \ | |
74 | int __l = (l); \ | |
75 | insw(__port, __p, __l); \ | |
76 | while (__l > 0) { \ | |
77 | *__p = swab16(*__p); \ | |
78 | __p++; \ | |
79 | __l--; \ | |
80 | } \ | |
81 | } while (0) | |
82 | #define SMC_outsw(a, r, p, l) \ | |
83 | do { \ | |
84 | unsigned long __port = (a) + (r); \ | |
85 | u16 *__p = (u16 *)(p); \ | |
86 | int __l = (l); \ | |
87 | while (__l > 0) { \ | |
88 | /* Believe it or not, the swab isn't needed. */ \ | |
89 | outw( /* swab16 */ (*__p++), __port); \ | |
90 | __l--; \ | |
91 | } \ | |
92 | } while (0) | |
9ded96f2 | 93 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
94 | |
95 | #elif defined(CONFIG_SA1100_PLEB) | |
96 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
97 | #define SMC_CAN_USE_8BIT 1 | |
98 | #define SMC_CAN_USE_16BIT 1 | |
99 | #define SMC_CAN_USE_32BIT 0 | |
100 | #define SMC_IO_SHIFT 0 | |
101 | #define SMC_NOWAIT 1 | |
102 | ||
1cf99be5 RK |
103 | #define SMC_inb(a, r) readb((a) + (r)) |
104 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
105 | #define SMC_inw(a, r) readw((a) + (r)) | |
106 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
107 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
108 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
109 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
110 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
1da177e4 | 111 | |
9ded96f2 | 112 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
113 | |
114 | #elif defined(CONFIG_SA1100_ASSABET) | |
115 | ||
116 | #include <asm/arch/neponset.h> | |
117 | ||
118 | /* We can only do 8-bit reads and writes in the static memory space. */ | |
119 | #define SMC_CAN_USE_8BIT 1 | |
120 | #define SMC_CAN_USE_16BIT 0 | |
121 | #define SMC_CAN_USE_32BIT 0 | |
122 | #define SMC_NOWAIT 1 | |
123 | ||
124 | /* The first two address lines aren't connected... */ | |
125 | #define SMC_IO_SHIFT 2 | |
126 | ||
127 | #define SMC_inb(a, r) readb((a) + (r)) | |
128 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
129 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
130 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
131 | ||
b0348b90 LB |
132 | #elif defined(CONFIG_MACH_LOGICPD_PXA270) |
133 | ||
134 | #define SMC_CAN_USE_8BIT 0 | |
135 | #define SMC_CAN_USE_16BIT 1 | |
136 | #define SMC_CAN_USE_32BIT 0 | |
137 | #define SMC_IO_SHIFT 0 | |
138 | #define SMC_NOWAIT 1 | |
b0348b90 | 139 | |
b0348b90 | 140 | #define SMC_inw(a, r) readw((a) + (r)) |
b0348b90 | 141 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) |
b0348b90 LB |
142 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
143 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
144 | ||
1da177e4 LT |
145 | #elif defined(CONFIG_ARCH_INNOKOM) || \ |
146 | defined(CONFIG_MACH_MAINSTONE) || \ | |
147 | defined(CONFIG_ARCH_PXA_IDP) || \ | |
148 | defined(CONFIG_ARCH_RAMSES) | |
149 | ||
150 | #define SMC_CAN_USE_8BIT 1 | |
151 | #define SMC_CAN_USE_16BIT 1 | |
152 | #define SMC_CAN_USE_32BIT 1 | |
153 | #define SMC_IO_SHIFT 0 | |
154 | #define SMC_NOWAIT 1 | |
155 | #define SMC_USE_PXA_DMA 1 | |
156 | ||
157 | #define SMC_inb(a, r) readb((a) + (r)) | |
158 | #define SMC_inw(a, r) readw((a) + (r)) | |
159 | #define SMC_inl(a, r) readl((a) + (r)) | |
160 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
161 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
162 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
163 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
164 | ||
165 | /* We actually can't write halfwords properly if not word aligned */ | |
166 | static inline void | |
eb1d6988 | 167 | SMC_outw(u16 val, void __iomem *ioaddr, int reg) |
1da177e4 LT |
168 | { |
169 | if (reg & 2) { | |
170 | unsigned int v = val << 16; | |
171 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; | |
172 | writel(v, ioaddr + (reg & ~2)); | |
173 | } else { | |
174 | writew(val, ioaddr + reg); | |
175 | } | |
176 | } | |
177 | ||
178 | #elif defined(CONFIG_ARCH_OMAP) | |
179 | ||
180 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
181 | #define SMC_CAN_USE_8BIT 0 | |
182 | #define SMC_CAN_USE_16BIT 1 | |
183 | #define SMC_CAN_USE_32BIT 0 | |
184 | #define SMC_IO_SHIFT 0 | |
185 | #define SMC_NOWAIT 1 | |
186 | ||
1da177e4 LT |
187 | #define SMC_inw(a, r) readw((a) + (r)) |
188 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
189 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
190 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
1da177e4 | 191 | |
5f13e7ec DB |
192 | #include <asm/mach-types.h> |
193 | #include <asm/arch/cpu.h> | |
194 | ||
9ded96f2 | 195 | #define SMC_IRQ_FLAGS (( \ |
5f13e7ec DB |
196 | machine_is_omap_h2() \ |
197 | || machine_is_omap_h3() \ | |
af44f5bf | 198 | || (machine_is_omap_innovator() && !cpu_is_omap1510()) \ |
1fb9df5d | 199 | ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING) |
5f13e7ec DB |
200 | |
201 | ||
1da177e4 LT |
202 | #elif defined(CONFIG_SH_SH4202_MICRODEV) |
203 | ||
204 | #define SMC_CAN_USE_8BIT 0 | |
205 | #define SMC_CAN_USE_16BIT 1 | |
206 | #define SMC_CAN_USE_32BIT 0 | |
207 | ||
208 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) | |
209 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) | |
210 | #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) | |
211 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) | |
212 | #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) | |
213 | #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) | |
214 | #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) | |
215 | #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) | |
216 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) | |
217 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) | |
218 | ||
9ded96f2 | 219 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
220 | |
221 | #elif defined(CONFIG_ISA) | |
222 | ||
223 | #define SMC_CAN_USE_8BIT 1 | |
224 | #define SMC_CAN_USE_16BIT 1 | |
225 | #define SMC_CAN_USE_32BIT 0 | |
226 | ||
227 | #define SMC_inb(a, r) inb((a) + (r)) | |
228 | #define SMC_inw(a, r) inw((a) + (r)) | |
229 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) | |
230 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) | |
231 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
232 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
233 | ||
234 | #elif defined(CONFIG_M32R) | |
235 | ||
236 | #define SMC_CAN_USE_8BIT 0 | |
237 | #define SMC_CAN_USE_16BIT 1 | |
238 | #define SMC_CAN_USE_32BIT 0 | |
239 | ||
f3ac9fbf HT |
240 | #define SMC_inb(a, r) inb((u32)a) + (r)) |
241 | #define SMC_inw(a, r) inw(((u32)a) + (r)) | |
242 | #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) | |
243 | #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) | |
244 | #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l) | |
245 | #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l) | |
1da177e4 | 246 | |
9ded96f2 | 247 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
248 | |
249 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
250 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
251 | ||
d4adcffb MS |
252 | #elif defined(CONFIG_MACH_LPD79520) \ |
253 | || defined(CONFIG_MACH_LPD7A400) \ | |
254 | || defined(CONFIG_MACH_LPD7A404) | |
1da177e4 | 255 | |
d4adcffb MS |
256 | /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the |
257 | * way that the CPU handles chip selects and the way that the SMC chip | |
258 | * expects the chip select to operate. Refer to | |
1da177e4 | 259 | * Documentation/arm/Sharp-LH/IOBarrier for details. The read from |
d4adcffb MS |
260 | * IOBARRIER is a byte, in order that we read the least-common |
261 | * denominator. It would be wasteful to read 32 bits from an 8-bit | |
262 | * accessible region. | |
1da177e4 LT |
263 | * |
264 | * There is no explicit protection against interrupts intervening | |
265 | * between the writew and the IOBARRIER. In SMC ISR there is a | |
266 | * preamble that performs an IOBARRIER in the extremely unlikely event | |
267 | * that the driver interrupts itself between a writew to the chip an | |
268 | * the IOBARRIER that follows *and* the cache is large enough that the | |
269 | * first off-chip access while handing the interrupt is to the SMC | |
270 | * chip. Other devices in the same address space as the SMC chip must | |
271 | * be aware of the potential for trouble and perform a similar | |
272 | * IOBARRIER on entry to their ISR. | |
273 | */ | |
274 | ||
275 | #include <asm/arch/constants.h> /* IOBARRIER_VIRT */ | |
276 | ||
277 | #define SMC_CAN_USE_8BIT 0 | |
278 | #define SMC_CAN_USE_16BIT 1 | |
279 | #define SMC_CAN_USE_32BIT 0 | |
280 | #define SMC_NOWAIT 0 | |
d4adcffb | 281 | #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT) |
1da177e4 | 282 | |
d4adcffb MS |
283 | #define SMC_inw(a,r)\ |
284 | ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; }) | |
285 | #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; }) | |
1da177e4 | 286 | |
d4adcffb MS |
287 | #define SMC_insw LPD7_SMC_insw |
288 | static inline void LPD7_SMC_insw (unsigned char* a, int r, | |
289 | unsigned char* p, int l) | |
290 | { | |
291 | unsigned short* ps = (unsigned short*) p; | |
292 | while (l-- > 0) { | |
293 | *ps++ = readw (a + r); | |
294 | LPD7X_IOBARRIER; | |
295 | } | |
296 | } | |
09779c6d | 297 | |
d4adcffb MS |
298 | #define SMC_outsw LPD7_SMC_outsw |
299 | static inline void LPD7_SMC_outsw (unsigned char* a, int r, | |
300 | unsigned char* p, int l) | |
1da177e4 LT |
301 | { |
302 | unsigned short* ps = (unsigned short*) p; | |
303 | while (l-- > 0) { | |
304 | writew (*ps++, a + r); | |
d4adcffb | 305 | LPD7X_IOBARRIER; |
1da177e4 LT |
306 | } |
307 | } | |
308 | ||
d4adcffb | 309 | #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER |
1da177e4 LT |
310 | |
311 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
312 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
313 | ||
55793455 PP |
314 | #elif defined(CONFIG_SOC_AU1X00) |
315 | ||
316 | #include <au1xxx.h> | |
317 | ||
318 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
319 | #define SMC_CAN_USE_8BIT 0 | |
320 | #define SMC_CAN_USE_16BIT 1 | |
321 | #define SMC_CAN_USE_32BIT 0 | |
322 | #define SMC_IO_SHIFT 0 | |
323 | #define SMC_NOWAIT 1 | |
324 | ||
325 | #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r))) | |
326 | #define SMC_insw(a, r, p, l) \ | |
327 | do { \ | |
328 | unsigned long _a = (unsigned long)((a) + (r)); \ | |
329 | int _l = (l); \ | |
330 | u16 *_p = (u16 *)(p); \ | |
331 | while (_l-- > 0) \ | |
332 | *_p++ = au_readw(_a); \ | |
333 | } while(0) | |
334 | #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r))) | |
335 | #define SMC_outsw(a, r, p, l) \ | |
336 | do { \ | |
337 | unsigned long _a = (unsigned long)((a) + (r)); \ | |
338 | int _l = (l); \ | |
339 | const u16 *_p = (const u16 *)(p); \ | |
340 | while (_l-- > 0) \ | |
341 | au_writew(*_p++ , _a); \ | |
342 | } while(0) | |
343 | ||
9ded96f2 | 344 | #define SMC_IRQ_FLAGS (0) |
55793455 | 345 | |
8431adfd DS |
346 | #elif defined(CONFIG_ARCH_VERSATILE) |
347 | ||
348 | #define SMC_CAN_USE_8BIT 1 | |
349 | #define SMC_CAN_USE_16BIT 1 | |
350 | #define SMC_CAN_USE_32BIT 1 | |
351 | #define SMC_NOWAIT 1 | |
352 | ||
353 | #define SMC_inb(a, r) readb((a) + (r)) | |
354 | #define SMC_inw(a, r) readw((a) + (r)) | |
355 | #define SMC_inl(a, r) readl((a) + (r)) | |
356 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
357 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
358 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
359 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
6432dc1f DS |
360 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) |
361 | ||
362 | #define SMC_IRQ_FLAGS (0) | |
363 | ||
364 | #elif defined(CONFIG_ARCH_VERSATILE) | |
365 | ||
366 | #define SMC_CAN_USE_8BIT 1 | |
367 | #define SMC_CAN_USE_16BIT 1 | |
368 | #define SMC_CAN_USE_32BIT 1 | |
369 | #define SMC_NOWAIT 1 | |
370 | ||
371 | #define SMC_inb(a, r) readb((a) + (r)) | |
372 | #define SMC_inw(a, r) readw((a) + (r)) | |
373 | #define SMC_inl(a, r) readl((a) + (r)) | |
374 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
375 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
376 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
377 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
8431adfd DS |
378 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) |
379 | ||
380 | #define SMC_IRQ_FLAGS (0) | |
381 | ||
6fd7587b DS |
382 | #elif defined(CONFIG_ARCH_VERSATILE) |
383 | ||
384 | #define SMC_CAN_USE_8BIT 1 | |
385 | #define SMC_CAN_USE_16BIT 1 | |
386 | #define SMC_CAN_USE_32BIT 1 | |
387 | #define SMC_NOWAIT 1 | |
388 | ||
389 | #define SMC_inb(a, r) readb((a) + (r)) | |
390 | #define SMC_inw(a, r) readw((a) + (r)) | |
391 | #define SMC_inl(a, r) readl((a) + (r)) | |
392 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
393 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
394 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
395 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
396 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
397 | ||
398 | #define SMC_IRQ_FLAGS (0) | |
399 | ||
1da177e4 LT |
400 | #else |
401 | ||
402 | #define SMC_CAN_USE_8BIT 1 | |
403 | #define SMC_CAN_USE_16BIT 1 | |
404 | #define SMC_CAN_USE_32BIT 1 | |
405 | #define SMC_NOWAIT 1 | |
406 | ||
407 | #define SMC_inb(a, r) readb((a) + (r)) | |
408 | #define SMC_inw(a, r) readw((a) + (r)) | |
409 | #define SMC_inl(a, r) readl((a) + (r)) | |
410 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
411 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
412 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
413 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
414 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
415 | ||
416 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | |
417 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
418 | ||
419 | #endif | |
420 | ||
1da177e4 LT |
421 | #ifdef SMC_USE_PXA_DMA |
422 | /* | |
423 | * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is | |
424 | * always happening in irq context so no need to worry about races. TX is | |
425 | * different and probably not worth it for that reason, and not as critical | |
426 | * as RX which can overrun memory and lose packets. | |
427 | */ | |
428 | #include <linux/dma-mapping.h> | |
429 | #include <asm/dma.h> | |
430 | #include <asm/arch/pxa-regs.h> | |
431 | ||
432 | #ifdef SMC_insl | |
433 | #undef SMC_insl | |
434 | #define SMC_insl(a, r, p, l) \ | |
435 | smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) | |
436 | static inline void | |
eb1d6988 | 437 | smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, |
1da177e4 LT |
438 | u_char *buf, int len) |
439 | { | |
440 | dma_addr_t dmabuf; | |
441 | ||
442 | /* fallback if no DMA available */ | |
443 | if (dma == (unsigned char)-1) { | |
444 | readsl(ioaddr + reg, buf, len); | |
445 | return; | |
446 | } | |
447 | ||
448 | /* 64 bit alignment is required for memory to memory DMA */ | |
449 | if ((long)buf & 4) { | |
450 | *((u32 *)buf) = SMC_inl(ioaddr, reg); | |
451 | buf += 4; | |
452 | len--; | |
453 | } | |
454 | ||
455 | len *= 4; | |
456 | dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); | |
457 | DCSR(dma) = DCSR_NODESC; | |
458 | DTADR(dma) = dmabuf; | |
459 | DSADR(dma) = physaddr + reg; | |
460 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
461 | DCMD_WIDTH4 | (DCMD_LENGTH & len)); | |
462 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
463 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
464 | cpu_relax(); | |
465 | DCSR(dma) = 0; | |
466 | dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); | |
467 | } | |
468 | #endif | |
469 | ||
470 | #ifdef SMC_insw | |
471 | #undef SMC_insw | |
472 | #define SMC_insw(a, r, p, l) \ | |
473 | smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) | |
474 | static inline void | |
eb1d6988 | 475 | smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, |
1da177e4 LT |
476 | u_char *buf, int len) |
477 | { | |
478 | dma_addr_t dmabuf; | |
479 | ||
480 | /* fallback if no DMA available */ | |
481 | if (dma == (unsigned char)-1) { | |
482 | readsw(ioaddr + reg, buf, len); | |
483 | return; | |
484 | } | |
485 | ||
486 | /* 64 bit alignment is required for memory to memory DMA */ | |
487 | while ((long)buf & 6) { | |
488 | *((u16 *)buf) = SMC_inw(ioaddr, reg); | |
489 | buf += 2; | |
490 | len--; | |
491 | } | |
492 | ||
493 | len *= 2; | |
494 | dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); | |
495 | DCSR(dma) = DCSR_NODESC; | |
496 | DTADR(dma) = dmabuf; | |
497 | DSADR(dma) = physaddr + reg; | |
498 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
499 | DCMD_WIDTH2 | (DCMD_LENGTH & len)); | |
500 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
501 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
502 | cpu_relax(); | |
503 | DCSR(dma) = 0; | |
504 | dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); | |
505 | } | |
506 | #endif | |
507 | ||
508 | static void | |
509 | smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs) | |
510 | { | |
511 | DCSR(dma) = 0; | |
512 | } | |
513 | #endif /* SMC_USE_PXA_DMA */ | |
514 | ||
515 | ||
09779c6d NP |
516 | /* |
517 | * Everything a particular hardware setup needs should have been defined | |
518 | * at this point. Add stubs for the undefined cases, mainly to avoid | |
519 | * compilation warnings since they'll be optimized away, or to prevent buggy | |
520 | * use of them. | |
521 | */ | |
522 | ||
523 | #if ! SMC_CAN_USE_32BIT | |
524 | #define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) | |
525 | #define SMC_outl(x, ioaddr, reg) BUG() | |
526 | #define SMC_insl(a, r, p, l) BUG() | |
527 | #define SMC_outsl(a, r, p, l) BUG() | |
528 | #endif | |
529 | ||
530 | #if !defined(SMC_insl) || !defined(SMC_outsl) | |
531 | #define SMC_insl(a, r, p, l) BUG() | |
532 | #define SMC_outsl(a, r, p, l) BUG() | |
533 | #endif | |
534 | ||
535 | #if ! SMC_CAN_USE_16BIT | |
536 | ||
537 | /* | |
538 | * Any 16-bit access is performed with two 8-bit accesses if the hardware | |
539 | * can't do it directly. Most registers are 16-bit so those are mandatory. | |
540 | */ | |
541 | #define SMC_outw(x, ioaddr, reg) \ | |
542 | do { \ | |
543 | unsigned int __val16 = (x); \ | |
544 | SMC_outb( __val16, ioaddr, reg ); \ | |
545 | SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ | |
546 | } while (0) | |
547 | #define SMC_inw(ioaddr, reg) \ | |
548 | ({ \ | |
549 | unsigned int __val16; \ | |
550 | __val16 = SMC_inb( ioaddr, reg ); \ | |
551 | __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ | |
552 | __val16; \ | |
553 | }) | |
554 | ||
555 | #define SMC_insw(a, r, p, l) BUG() | |
556 | #define SMC_outsw(a, r, p, l) BUG() | |
557 | ||
558 | #endif | |
559 | ||
560 | #if !defined(SMC_insw) || !defined(SMC_outsw) | |
561 | #define SMC_insw(a, r, p, l) BUG() | |
562 | #define SMC_outsw(a, r, p, l) BUG() | |
563 | #endif | |
564 | ||
565 | #if ! SMC_CAN_USE_8BIT | |
566 | #define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) | |
567 | #define SMC_outb(x, ioaddr, reg) BUG() | |
568 | #define SMC_insb(a, r, p, l) BUG() | |
569 | #define SMC_outsb(a, r, p, l) BUG() | |
570 | #endif | |
571 | ||
572 | #if !defined(SMC_insb) || !defined(SMC_outsb) | |
573 | #define SMC_insb(a, r, p, l) BUG() | |
574 | #define SMC_outsb(a, r, p, l) BUG() | |
575 | #endif | |
576 | ||
577 | #ifndef SMC_CAN_USE_DATACS | |
578 | #define SMC_CAN_USE_DATACS 0 | |
579 | #endif | |
580 | ||
1da177e4 LT |
581 | #ifndef SMC_IO_SHIFT |
582 | #define SMC_IO_SHIFT 0 | |
583 | #endif | |
09779c6d NP |
584 | |
585 | #ifndef SMC_IRQ_FLAGS | |
1fb9df5d | 586 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING |
09779c6d NP |
587 | #endif |
588 | ||
589 | #ifndef SMC_INTERRUPT_PREAMBLE | |
590 | #define SMC_INTERRUPT_PREAMBLE | |
591 | #endif | |
592 | ||
593 | ||
594 | /* Because of bank switching, the LAN91x uses only 16 I/O ports */ | |
1da177e4 LT |
595 | #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) |
596 | #define SMC_DATA_EXTENT (4) | |
597 | ||
598 | /* | |
599 | . Bank Select Register: | |
600 | . | |
601 | . yyyy yyyy 0000 00xx | |
602 | . xx = bank number | |
603 | . yyyy yyyy = 0x33, for identification purposes. | |
604 | */ | |
605 | #define BANK_SELECT (14 << SMC_IO_SHIFT) | |
606 | ||
607 | ||
608 | // Transmit Control Register | |
609 | /* BANK 0 */ | |
610 | #define TCR_REG SMC_REG(0x0000, 0) | |
611 | #define TCR_ENABLE 0x0001 // When 1 we can transmit | |
612 | #define TCR_LOOP 0x0002 // Controls output pin LBK | |
613 | #define TCR_FORCOL 0x0004 // When 1 will force a collision | |
614 | #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 | |
615 | #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames | |
616 | #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier | |
617 | #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation | |
618 | #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error | |
619 | #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback | |
620 | #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode | |
621 | ||
622 | #define TCR_CLEAR 0 /* do NOTHING */ | |
623 | /* the default settings for the TCR register : */ | |
624 | #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) | |
625 | ||
626 | ||
627 | // EPH Status Register | |
628 | /* BANK 0 */ | |
629 | #define EPH_STATUS_REG SMC_REG(0x0002, 0) | |
630 | #define ES_TX_SUC 0x0001 // Last TX was successful | |
631 | #define ES_SNGL_COL 0x0002 // Single collision detected for last tx | |
632 | #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx | |
633 | #define ES_LTX_MULT 0x0008 // Last tx was a multicast | |
634 | #define ES_16COL 0x0010 // 16 Collisions Reached | |
635 | #define ES_SQET 0x0020 // Signal Quality Error Test | |
636 | #define ES_LTXBRD 0x0040 // Last tx was a broadcast | |
637 | #define ES_TXDEFR 0x0080 // Transmit Deferred | |
638 | #define ES_LATCOL 0x0200 // Late collision detected on last tx | |
639 | #define ES_LOSTCARR 0x0400 // Lost Carrier Sense | |
640 | #define ES_EXC_DEF 0x0800 // Excessive Deferral | |
641 | #define ES_CTR_ROL 0x1000 // Counter Roll Over indication | |
642 | #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin | |
643 | #define ES_TXUNRN 0x8000 // Tx Underrun | |
644 | ||
645 | ||
646 | // Receive Control Register | |
647 | /* BANK 0 */ | |
648 | #define RCR_REG SMC_REG(0x0004, 0) | |
649 | #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted | |
650 | #define RCR_PRMS 0x0002 // Enable promiscuous mode | |
651 | #define RCR_ALMUL 0x0004 // When set accepts all multicast frames | |
652 | #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets | |
653 | #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets | |
654 | #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision | |
655 | #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier | |
656 | #define RCR_SOFTRST 0x8000 // resets the chip | |
657 | ||
658 | /* the normal settings for the RCR register : */ | |
659 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
660 | #define RCR_CLEAR 0x0 // set it to a base state | |
661 | ||
662 | ||
663 | // Counter Register | |
664 | /* BANK 0 */ | |
665 | #define COUNTER_REG SMC_REG(0x0006, 0) | |
666 | ||
667 | ||
668 | // Memory Information Register | |
669 | /* BANK 0 */ | |
670 | #define MIR_REG SMC_REG(0x0008, 0) | |
671 | ||
672 | ||
673 | // Receive/Phy Control Register | |
674 | /* BANK 0 */ | |
675 | #define RPC_REG SMC_REG(0x000A, 0) | |
676 | #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. | |
677 | #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode | |
678 | #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode | |
679 | #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb | |
680 | #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb | |
681 | #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect | |
682 | #define RPC_LED_RES (0x01) // LED = Reserved | |
683 | #define RPC_LED_10 (0x02) // LED = 10Mbps link detect | |
684 | #define RPC_LED_FD (0x03) // LED = Full Duplex Mode | |
685 | #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred | |
686 | #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect | |
687 | #define RPC_LED_TX (0x06) // LED = TX packet occurred | |
688 | #define RPC_LED_RX (0x07) // LED = RX packet occurred | |
689 | ||
690 | #ifndef RPC_LSA_DEFAULT | |
691 | #define RPC_LSA_DEFAULT RPC_LED_100 | |
692 | #endif | |
693 | #ifndef RPC_LSB_DEFAULT | |
694 | #define RPC_LSB_DEFAULT RPC_LED_FD | |
695 | #endif | |
696 | ||
697 | #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) | |
698 | ||
699 | ||
700 | /* Bank 0 0x0C is reserved */ | |
701 | ||
702 | // Bank Select Register | |
703 | /* All Banks */ | |
704 | #define BSR_REG 0x000E | |
705 | ||
706 | ||
707 | // Configuration Reg | |
708 | /* BANK 1 */ | |
709 | #define CONFIG_REG SMC_REG(0x0000, 1) | |
710 | #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy | |
711 | #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL | |
712 | #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus | |
713 | #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. | |
714 | ||
715 | // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low | |
716 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
717 | ||
718 | ||
719 | // Base Address Register | |
720 | /* BANK 1 */ | |
721 | #define BASE_REG SMC_REG(0x0002, 1) | |
722 | ||
723 | ||
724 | // Individual Address Registers | |
725 | /* BANK 1 */ | |
726 | #define ADDR0_REG SMC_REG(0x0004, 1) | |
727 | #define ADDR1_REG SMC_REG(0x0006, 1) | |
728 | #define ADDR2_REG SMC_REG(0x0008, 1) | |
729 | ||
730 | ||
731 | // General Purpose Register | |
732 | /* BANK 1 */ | |
733 | #define GP_REG SMC_REG(0x000A, 1) | |
734 | ||
735 | ||
736 | // Control Register | |
737 | /* BANK 1 */ | |
738 | #define CTL_REG SMC_REG(0x000C, 1) | |
739 | #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received | |
740 | #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically | |
741 | #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt | |
742 | #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt | |
743 | #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt | |
744 | #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store | |
745 | #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers | |
746 | #define CTL_STORE 0x0001 // When set stores registers into EEPROM | |
747 | ||
748 | ||
749 | // MMU Command Register | |
750 | /* BANK 2 */ | |
751 | #define MMU_CMD_REG SMC_REG(0x0000, 2) | |
752 | #define MC_BUSY 1 // When 1 the last release has not completed | |
753 | #define MC_NOP (0<<5) // No Op | |
754 | #define MC_ALLOC (1<<5) // OR with number of 256 byte packets | |
755 | #define MC_RESET (2<<5) // Reset MMU to initial state | |
756 | #define MC_REMOVE (3<<5) // Remove the current rx packet | |
757 | #define MC_RELEASE (4<<5) // Remove and release the current rx packet | |
758 | #define MC_FREEPKT (5<<5) // Release packet in PNR register | |
759 | #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit | |
760 | #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs | |
761 | ||
762 | ||
763 | // Packet Number Register | |
764 | /* BANK 2 */ | |
765 | #define PN_REG SMC_REG(0x0002, 2) | |
766 | ||
767 | ||
768 | // Allocation Result Register | |
769 | /* BANK 2 */ | |
770 | #define AR_REG SMC_REG(0x0003, 2) | |
771 | #define AR_FAILED 0x80 // Alocation Failed | |
772 | ||
773 | ||
774 | // TX FIFO Ports Register | |
775 | /* BANK 2 */ | |
776 | #define TXFIFO_REG SMC_REG(0x0004, 2) | |
777 | #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty | |
778 | ||
779 | // RX FIFO Ports Register | |
780 | /* BANK 2 */ | |
781 | #define RXFIFO_REG SMC_REG(0x0005, 2) | |
782 | #define RXFIFO_REMPTY 0x80 // RX FIFO Empty | |
783 | ||
784 | #define FIFO_REG SMC_REG(0x0004, 2) | |
785 | ||
786 | // Pointer Register | |
787 | /* BANK 2 */ | |
788 | #define PTR_REG SMC_REG(0x0006, 2) | |
789 | #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area | |
790 | #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access | |
791 | #define PTR_READ 0x2000 // When 1 the operation is a read | |
792 | ||
793 | ||
794 | // Data Register | |
795 | /* BANK 2 */ | |
796 | #define DATA_REG SMC_REG(0x0008, 2) | |
797 | ||
798 | ||
799 | // Interrupt Status/Acknowledge Register | |
800 | /* BANK 2 */ | |
801 | #define INT_REG SMC_REG(0x000C, 2) | |
802 | ||
803 | ||
804 | // Interrupt Mask Register | |
805 | /* BANK 2 */ | |
806 | #define IM_REG SMC_REG(0x000D, 2) | |
807 | #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt | |
808 | #define IM_ERCV_INT 0x40 // Early Receive Interrupt | |
809 | #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section | |
810 | #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns | |
811 | #define IM_ALLOC_INT 0x08 // Set when allocation request is completed | |
812 | #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty | |
813 | #define IM_TX_INT 0x02 // Transmit Interrupt | |
814 | #define IM_RCV_INT 0x01 // Receive Interrupt | |
815 | ||
816 | ||
817 | // Multicast Table Registers | |
818 | /* BANK 3 */ | |
819 | #define MCAST_REG1 SMC_REG(0x0000, 3) | |
820 | #define MCAST_REG2 SMC_REG(0x0002, 3) | |
821 | #define MCAST_REG3 SMC_REG(0x0004, 3) | |
822 | #define MCAST_REG4 SMC_REG(0x0006, 3) | |
823 | ||
824 | ||
825 | // Management Interface Register (MII) | |
826 | /* BANK 3 */ | |
827 | #define MII_REG SMC_REG(0x0008, 3) | |
828 | #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup | |
829 | #define MII_MDOE 0x0008 // MII Output Enable | |
830 | #define MII_MCLK 0x0004 // MII Clock, pin MDCLK | |
831 | #define MII_MDI 0x0002 // MII Input, pin MDI | |
832 | #define MII_MDO 0x0001 // MII Output, pin MDO | |
833 | ||
834 | ||
835 | // Revision Register | |
836 | /* BANK 3 */ | |
837 | /* ( hi: chip id low: rev # ) */ | |
838 | #define REV_REG SMC_REG(0x000A, 3) | |
839 | ||
840 | ||
841 | // Early RCV Register | |
842 | /* BANK 3 */ | |
843 | /* this is NOT on SMC9192 */ | |
844 | #define ERCV_REG SMC_REG(0x000C, 3) | |
845 | #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received | |
846 | #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask | |
847 | ||
848 | ||
849 | // External Register | |
850 | /* BANK 7 */ | |
851 | #define EXT_REG SMC_REG(0x0000, 7) | |
852 | ||
853 | ||
854 | #define CHIP_9192 3 | |
855 | #define CHIP_9194 4 | |
856 | #define CHIP_9195 5 | |
857 | #define CHIP_9196 6 | |
858 | #define CHIP_91100 7 | |
859 | #define CHIP_91100FD 8 | |
860 | #define CHIP_91111FD 9 | |
861 | ||
862 | static const char * chip_ids[ 16 ] = { | |
863 | NULL, NULL, NULL, | |
864 | /* 3 */ "SMC91C90/91C92", | |
865 | /* 4 */ "SMC91C94", | |
866 | /* 5 */ "SMC91C95", | |
867 | /* 6 */ "SMC91C96", | |
868 | /* 7 */ "SMC91C100", | |
869 | /* 8 */ "SMC91C100FD", | |
870 | /* 9 */ "SMC91C11xFD", | |
871 | NULL, NULL, NULL, | |
872 | NULL, NULL, NULL}; | |
873 | ||
874 | ||
1da177e4 LT |
875 | /* |
876 | . Receive status bits | |
877 | */ | |
878 | #define RS_ALGNERR 0x8000 | |
879 | #define RS_BRODCAST 0x4000 | |
880 | #define RS_BADCRC 0x2000 | |
881 | #define RS_ODDFRAME 0x1000 | |
882 | #define RS_TOOLONG 0x0800 | |
883 | #define RS_TOOSHORT 0x0400 | |
884 | #define RS_MULTICAST 0x0001 | |
885 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
886 | ||
887 | ||
888 | /* | |
889 | * PHY IDs | |
890 | * LAN83C183 == LAN91C111 Internal PHY | |
891 | */ | |
892 | #define PHY_LAN83C183 0x0016f840 | |
893 | #define PHY_LAN83C180 0x02821c50 | |
894 | ||
895 | /* | |
896 | * PHY Register Addresses (LAN91C111 Internal PHY) | |
897 | * | |
898 | * Generic PHY registers can be found in <linux/mii.h> | |
899 | * | |
900 | * These phy registers are specific to our on-board phy. | |
901 | */ | |
902 | ||
903 | // PHY Configuration Register 1 | |
904 | #define PHY_CFG1_REG 0x10 | |
905 | #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled | |
906 | #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled | |
907 | #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down | |
908 | #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler | |
909 | #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable | |
910 | #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled | |
911 | #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) | |
912 | #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db | |
913 | #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust | |
914 | #define PHY_CFG1_TLVL_MASK 0x003C | |
915 | #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time | |
916 | ||
917 | ||
918 | // PHY Configuration Register 2 | |
919 | #define PHY_CFG2_REG 0x11 | |
920 | #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled | |
921 | #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled | |
922 | #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) | |
923 | #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo | |
924 | ||
925 | // PHY Status Output (and Interrupt status) Register | |
926 | #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) | |
927 | #define PHY_INT_INT 0x8000 // 1=bits have changed since last read | |
928 | #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected | |
929 | #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync | |
930 | #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx | |
931 | #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx | |
932 | #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx | |
933 | #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected | |
934 | #define PHY_INT_JAB 0x0100 // 1=Jabber detected | |
935 | #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode | |
936 | #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex | |
937 | ||
938 | // PHY Interrupt/Status Mask Register | |
939 | #define PHY_MASK_REG 0x13 // Interrupt Mask | |
940 | // Uses the same bit definitions as PHY_INT_REG | |
941 | ||
942 | ||
943 | /* | |
944 | * SMC91C96 ethernet config and status registers. | |
945 | * These are in the "attribute" space. | |
946 | */ | |
947 | #define ECOR 0x8000 | |
948 | #define ECOR_RESET 0x80 | |
949 | #define ECOR_LEVEL_IRQ 0x40 | |
950 | #define ECOR_WR_ATTRIB 0x04 | |
951 | #define ECOR_ENABLE 0x01 | |
952 | ||
953 | #define ECSR 0x8002 | |
954 | #define ECSR_IOIS8 0x20 | |
955 | #define ECSR_PWRDWN 0x04 | |
956 | #define ECSR_INT 0x02 | |
957 | ||
958 | #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) | |
959 | ||
960 | ||
961 | /* | |
962 | * Macros to abstract register access according to the data bus | |
963 | * capabilities. Please use those and not the in/out primitives. | |
964 | * Note: the following macros do *not* select the bank -- this must | |
965 | * be done separately as needed in the main code. The SMC_REG() macro | |
966 | * only uses the bank argument for debugging purposes (when enabled). | |
09779c6d NP |
967 | * |
968 | * Note: despite inline functions being safer, everything leading to this | |
969 | * should preferably be macros to let BUG() display the line number in | |
970 | * the core source code since we're interested in the top call site | |
971 | * not in any inline function location. | |
1da177e4 LT |
972 | */ |
973 | ||
974 | #if SMC_DEBUG > 0 | |
975 | #define SMC_REG(reg, bank) \ | |
976 | ({ \ | |
977 | int __b = SMC_CURRENT_BANK(); \ | |
978 | if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ | |
979 | printk( "%s: bank reg screwed (0x%04x)\n", \ | |
980 | CARDNAME, __b ); \ | |
981 | BUG(); \ | |
982 | } \ | |
983 | reg<<SMC_IO_SHIFT; \ | |
984 | }) | |
985 | #else | |
986 | #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT) | |
987 | #endif | |
988 | ||
09779c6d NP |
989 | /* |
990 | * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not | |
991 | * aligned to a 32 bit boundary. I tell you that does exist! | |
992 | * Fortunately the affected register accesses can be easily worked around | |
993 | * since we can write zeroes to the preceeding 16 bits without adverse | |
994 | * effects and use a 32-bit access. | |
995 | * | |
996 | * Enforce it on any 32-bit capable setup for now. | |
997 | */ | |
998 | #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT | |
999 | ||
1000 | #define SMC_GET_PN() \ | |
1001 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \ | |
1002 | : (SMC_inw(ioaddr, PN_REG) & 0xFF) ) | |
1003 | ||
1004 | #define SMC_SET_PN(x) \ | |
1005 | do { \ | |
1006 | if (SMC_MUST_ALIGN_WRITE) \ | |
1007 | SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \ | |
1008 | else if (SMC_CAN_USE_8BIT) \ | |
1009 | SMC_outb(x, ioaddr, PN_REG); \ | |
1010 | else \ | |
1011 | SMC_outw(x, ioaddr, PN_REG); \ | |
1012 | } while (0) | |
1013 | ||
1014 | #define SMC_GET_AR() \ | |
1015 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \ | |
1016 | : (SMC_inw(ioaddr, PN_REG) >> 8) ) | |
1017 | ||
1018 | #define SMC_GET_TXFIFO() \ | |
1019 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \ | |
1020 | : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) ) | |
1021 | ||
1022 | #define SMC_GET_RXFIFO() \ | |
1023 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \ | |
1024 | : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) ) | |
1025 | ||
1026 | #define SMC_GET_INT() \ | |
1027 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \ | |
1028 | : (SMC_inw(ioaddr, INT_REG) & 0xFF) ) | |
1029 | ||
1da177e4 LT |
1030 | #define SMC_ACK_INT(x) \ |
1031 | do { \ | |
09779c6d NP |
1032 | if (SMC_CAN_USE_8BIT) \ |
1033 | SMC_outb(x, ioaddr, INT_REG); \ | |
1034 | else { \ | |
1035 | unsigned long __flags; \ | |
1036 | int __mask; \ | |
1037 | local_irq_save(__flags); \ | |
1038 | __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ | |
1039 | SMC_outw( __mask | (x), ioaddr, INT_REG ); \ | |
1040 | local_irq_restore(__flags); \ | |
1041 | } \ | |
1042 | } while (0) | |
1043 | ||
1044 | #define SMC_GET_INT_MASK() \ | |
1045 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \ | |
1046 | : (SMC_inw( ioaddr, INT_REG ) >> 8) ) | |
1047 | ||
1048 | #define SMC_SET_INT_MASK(x) \ | |
1049 | do { \ | |
1050 | if (SMC_CAN_USE_8BIT) \ | |
1051 | SMC_outb(x, ioaddr, IM_REG); \ | |
1052 | else \ | |
1053 | SMC_outw((x) << 8, ioaddr, INT_REG); \ | |
1054 | } while (0) | |
1055 | ||
1056 | #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT) | |
1057 | ||
1058 | #define SMC_SELECT_BANK(x) \ | |
1059 | do { \ | |
1060 | if (SMC_MUST_ALIGN_WRITE) \ | |
1061 | SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ | |
1062 | else \ | |
1063 | SMC_outw(x, ioaddr, BANK_SELECT); \ | |
1064 | } while (0) | |
1065 | ||
1066 | #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG) | |
1067 | ||
1068 | #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG) | |
1069 | ||
1070 | #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG) | |
1071 | ||
1072 | #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG) | |
1073 | ||
1074 | #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG) | |
1075 | ||
1076 | #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG) | |
1077 | ||
1078 | #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG) | |
1079 | ||
1080 | #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG) | |
1081 | ||
1082 | #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG) | |
1083 | ||
1084 | #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG) | |
1085 | ||
1086 | #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG) | |
1087 | ||
1088 | #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG) | |
1089 | ||
1090 | #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG) | |
1091 | ||
1092 | #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG) | |
1093 | ||
1094 | #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG) | |
1095 | ||
1096 | #define SMC_SET_PTR(x) \ | |
1097 | do { \ | |
1098 | if (SMC_MUST_ALIGN_WRITE) \ | |
1099 | SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \ | |
1100 | else \ | |
1101 | SMC_outw(x, ioaddr, PTR_REG); \ | |
1da177e4 | 1102 | } while (0) |
1da177e4 | 1103 | |
09779c6d NP |
1104 | #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG) |
1105 | ||
1106 | #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG) | |
1107 | ||
1108 | #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG) | |
1109 | ||
1110 | #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG) | |
1111 | ||
1112 | #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG) | |
1113 | ||
1114 | #define SMC_SET_RPC(x) \ | |
1115 | do { \ | |
1116 | if (SMC_MUST_ALIGN_WRITE) \ | |
1117 | SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \ | |
1118 | else \ | |
1119 | SMC_outw(x, ioaddr, RPC_REG); \ | |
1120 | } while (0) | |
1121 | ||
1122 | #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG) | |
1123 | ||
1124 | #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG) | |
1da177e4 LT |
1125 | |
1126 | #ifndef SMC_GET_MAC_ADDR | |
1127 | #define SMC_GET_MAC_ADDR(addr) \ | |
1128 | do { \ | |
1129 | unsigned int __v; \ | |
1130 | __v = SMC_inw( ioaddr, ADDR0_REG ); \ | |
1131 | addr[0] = __v; addr[1] = __v >> 8; \ | |
1132 | __v = SMC_inw( ioaddr, ADDR1_REG ); \ | |
1133 | addr[2] = __v; addr[3] = __v >> 8; \ | |
1134 | __v = SMC_inw( ioaddr, ADDR2_REG ); \ | |
1135 | addr[4] = __v; addr[5] = __v >> 8; \ | |
1136 | } while (0) | |
1137 | #endif | |
1138 | ||
1139 | #define SMC_SET_MAC_ADDR(addr) \ | |
1140 | do { \ | |
1141 | SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ | |
1142 | SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ | |
1143 | SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ | |
1144 | } while (0) | |
1145 | ||
1146 | #define SMC_SET_MCAST(x) \ | |
1147 | do { \ | |
1148 | const unsigned char *mt = (x); \ | |
1149 | SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ | |
1150 | SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ | |
1151 | SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ | |
1152 | SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ | |
1153 | } while (0) | |
1154 | ||
1da177e4 LT |
1155 | #define SMC_PUT_PKT_HDR(status, length) \ |
1156 | do { \ | |
09779c6d NP |
1157 | if (SMC_CAN_USE_32BIT) \ |
1158 | SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \ | |
1159 | else { \ | |
1160 | SMC_outw(status, ioaddr, DATA_REG); \ | |
1161 | SMC_outw(length, ioaddr, DATA_REG); \ | |
1162 | } \ | |
1da177e4 | 1163 | } while (0) |
1da177e4 | 1164 | |
09779c6d | 1165 | #define SMC_GET_PKT_HDR(status, length) \ |
1da177e4 | 1166 | do { \ |
09779c6d NP |
1167 | if (SMC_CAN_USE_32BIT) { \ |
1168 | unsigned int __val = SMC_inl(ioaddr, DATA_REG); \ | |
1169 | (status) = __val & 0xffff; \ | |
1170 | (length) = __val >> 16; \ | |
1171 | } else { \ | |
1172 | (status) = SMC_inw(ioaddr, DATA_REG); \ | |
1173 | (length) = SMC_inw(ioaddr, DATA_REG); \ | |
1da177e4 LT |
1174 | } \ |
1175 | } while (0) | |
1da177e4 | 1176 | |
09779c6d | 1177 | #define SMC_PUSH_DATA(p, l) \ |
1da177e4 | 1178 | do { \ |
09779c6d NP |
1179 | if (SMC_CAN_USE_32BIT) { \ |
1180 | void *__ptr = (p); \ | |
1181 | int __len = (l); \ | |
1182 | void *__ioaddr = ioaddr; \ | |
1183 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ | |
1184 | __len -= 2; \ | |
1185 | SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \ | |
1186 | __ptr += 2; \ | |
1187 | } \ | |
1188 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1189 | __ioaddr = lp->datacs; \ | |
1190 | SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \ | |
1191 | if (__len & 2) { \ | |
1192 | __ptr += (__len & ~3); \ | |
1193 | SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \ | |
1194 | } \ | |
1195 | } else if (SMC_CAN_USE_16BIT) \ | |
1196 | SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \ | |
1197 | else if (SMC_CAN_USE_8BIT) \ | |
1198 | SMC_outsb(ioaddr, DATA_REG, p, l); \ | |
1da177e4 | 1199 | } while (0) |
1da177e4 LT |
1200 | |
1201 | #define SMC_PULL_DATA(p, l) \ | |
09779c6d NP |
1202 | do { \ |
1203 | if (SMC_CAN_USE_32BIT) { \ | |
1204 | void *__ptr = (p); \ | |
1205 | int __len = (l); \ | |
1206 | void *__ioaddr = ioaddr; \ | |
1207 | if ((unsigned long)__ptr & 2) { \ | |
1208 | /* \ | |
1209 | * We want 32bit alignment here. \ | |
1210 | * Since some buses perform a full \ | |
1211 | * 32bit fetch even for 16bit data \ | |
1212 | * we can't use SMC_inw() here. \ | |
1213 | * Back both source (on-chip) and \ | |
1214 | * destination pointers of 2 bytes. \ | |
1215 | * This is possible since the call to \ | |
1216 | * SMC_GET_PKT_HDR() already advanced \ | |
1217 | * the source pointer of 4 bytes, and \ | |
1218 | * the skb_reserve(skb, 2) advanced \ | |
1219 | * the destination pointer of 2 bytes. \ | |
1220 | */ \ | |
1221 | __ptr -= 2; \ | |
1222 | __len += 2; \ | |
1223 | SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ | |
1224 | } \ | |
1225 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1226 | __ioaddr = lp->datacs; \ | |
1da177e4 | 1227 | __len += 2; \ |
09779c6d NP |
1228 | SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \ |
1229 | } else if (SMC_CAN_USE_16BIT) \ | |
1230 | SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \ | |
1231 | else if (SMC_CAN_USE_8BIT) \ | |
1232 | SMC_insb(ioaddr, DATA_REG, p, l); \ | |
1233 | } while (0) | |
1da177e4 LT |
1234 | |
1235 | #endif /* _SMC91X_H_ */ |