projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
smc911x: fix 16-bit I/O operations
[linux-2.6-block.git] / drivers / net / smc911x.c
CommitLineData
0a0c72c9
DM		 1/*
2 * smc911x.c
3 * This is a driver for SMSC's LAN911{5,6,7,8} single-chip Ethernet devices.
4 *
5 * Copyright (C) 2005 Sensoria Corp
6 * Derived from the unified SMC91x driver by Nicolas Pitre
d5498bef 7 * and the smsc911x.c reference driver by SMSC
0a0c72c9
DM		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 * Arguments:
24 * watchdog = TX watchdog timeout
25 * tx_fifo_kb = Size of TX FIFO in KB
26 *
27 * History:
28 * 04/16/05 Dustin McIntire Initial version
29 */
30static const char version[] =
31 "smc911x.c: v1.0 04-16-2005 by Dustin McIntire <dustin@sensoria.com>\n";
32
33/* Debugging options */
34#define ENABLE_SMC_DEBUG_RX 0
35#define ENABLE_SMC_DEBUG_TX 0
36#define ENABLE_SMC_DEBUG_DMA 0
37#define ENABLE_SMC_DEBUG_PKTS 0
38#define ENABLE_SMC_DEBUG_MISC 0
39#define ENABLE_SMC_DEBUG_FUNC 0
40
41#define SMC_DEBUG_RX ((ENABLE_SMC_DEBUG_RX ? 1 : 0) << 0)
42#define SMC_DEBUG_TX ((ENABLE_SMC_DEBUG_TX ? 1 : 0) << 1)
43#define SMC_DEBUG_DMA ((ENABLE_SMC_DEBUG_DMA ? 1 : 0) << 2)
44#define SMC_DEBUG_PKTS ((ENABLE_SMC_DEBUG_PKTS ? 1 : 0) << 3)
45#define SMC_DEBUG_MISC ((ENABLE_SMC_DEBUG_MISC ? 1 : 0) << 4)
46#define SMC_DEBUG_FUNC ((ENABLE_SMC_DEBUG_FUNC ? 1 : 0) << 5)
47
48#ifndef SMC_DEBUG
49#define SMC_DEBUG ( SMC_DEBUG_RX | \
50 SMC_DEBUG_TX | \
51 SMC_DEBUG_DMA | \
52 SMC_DEBUG_PKTS | \
53 SMC_DEBUG_MISC | \
54 SMC_DEBUG_FUNC \
55 )
56#endif
57
0a0c72c9
DM		 58#include <linux/init.h>
59#include <linux/module.h>
60#include <linux/kernel.h>
61#include <linux/sched.h>
62#include <linux/slab.h>
63#include <linux/delay.h>
64#include <linux/interrupt.h>
65#include <linux/errno.h>
66#include <linux/ioport.h>
67#include <linux/crc32.h>
68#include <linux/device.h>
69#include <linux/platform_device.h>
70#include <linux/spinlock.h>
71#include <linux/ethtool.h>
72#include <linux/mii.h>
73#include <linux/workqueue.h>
74
75#include <linux/netdevice.h>
76#include <linux/etherdevice.h>
77#include <linux/skbuff.h>
78
79#include <asm/io.h>
0a0c72c9
DM		 80
81#include "smc911x.h"
82
83/*
84 * Transmit timeout, default 5 seconds.
85 */
86static int watchdog = 5000;
87module_param(watchdog, int, 0400);
88MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
89
90static int tx_fifo_kb=8;
91module_param(tx_fifo_kb, int, 0400);
92MODULE_PARM_DESC(tx_fifo_kb,"transmit FIFO size in KB (1<x<15)(default=8)");
93
94MODULE_LICENSE("GPL");
72abb461 95MODULE_ALIAS("platform:smc911x");
0a0c72c9
DM		 96
97/*
98 * The internal workings of the driver. If you are changing anything
99 * here with the SMC stuff, you should have the datasheet and know
100 * what you are doing.
101 */
102#define CARDNAME "smc911x"
103
104/*
105 * Use power-down feature of the chip
106 */
107#define POWER_DOWN 1
108
109
110/* store this information for the driver.. */
111struct smc911x_local {
112 /*
113 * If I have to wait until the DMA is finished and ready to reload a
d5498bef 114 * packet, I will store the skbuff here. Then, the DMA will send it
0a0c72c9
DM		 115 * out and free it.
116 */
117 struct sk_buff *pending_tx_skb;
118
0a0c72c9
DM		 119 /* version/revision of the SMC911x chip */
120 u16 version;
121 u16 revision;
122
123 /* FIFO sizes */
124 int tx_fifo_kb;
125 int tx_fifo_size;
126 int rx_fifo_size;
127 int afc_cfg;
128
129 /* Contains the current active receive/phy mode */
130 int ctl_rfduplx;
131 int ctl_rspeed;
132
133 u32 msg_enable;
134 u32 phy_type;
135 struct mii_if_info mii;
136
137 /* work queue */
138 struct work_struct phy_configure;
139 int work_pending;
140
141 int tx_throttle;
142 spinlock_t lock;
143
ef8142a5
AM		 144 struct net_device *netdev;
145
0a0c72c9
DM		 146#ifdef SMC_USE_DMA
147 /* DMA needs the physical address of the chip */
148 u_long physaddr;
149 int rxdma;
150 int txdma;
151 int rxdma_active;
152 int txdma_active;
153 struct sk_buff *current_rx_skb;
154 struct sk_buff *current_tx_skb;
155 struct device *dev;
156#endif
157};
158
159#if SMC_DEBUG > 0
160#define DBG(n, args...) \
161 do { \
162 if (SMC_DEBUG & (n)) \
163 printk(args); \
164 } while (0)
165
166#define PRINTK(args...) printk(args)
167#else
168#define DBG(n, args...) do { } while (0)
169#define PRINTK(args...) printk(KERN_DEBUG args)
170#endif
171
172#if SMC_DEBUG_PKTS > 0
173static void PRINT_PKT(u_char *buf, int length)
174{
175 int i;
176 int remainder;
177 int lines;
178
179 lines = length / 16;
180 remainder = length % 16;
181
182 for (i = 0; i < lines ; i ++) {
183 int cur;
184 for (cur = 0; cur < 8; cur++) {
185 u_char a, b;
186 a = *buf++;
187 b = *buf++;
188 printk("%02x%02x ", a, b);
189 }
190 printk("\n");
191 }
192 for (i = 0; i < remainder/2 ; i++) {
193 u_char a, b;
194 a = *buf++;
195 b = *buf++;
196 printk("%02x%02x ", a, b);
197 }
198 printk("\n");
199}
200#else
201#define PRINT_PKT(x...) do { } while (0)
202#endif
203
204
205/* this enables an interrupt in the interrupt mask register */
206#define SMC_ENABLE_INT(x) do { \
207 unsigned int __mask; \
208 unsigned long __flags; \
209 spin_lock_irqsave(&lp->lock, __flags); \
210 __mask = SMC_GET_INT_EN(); \
211 __mask |= (x); \
212 SMC_SET_INT_EN(__mask); \
213 spin_unlock_irqrestore(&lp->lock, __flags); \
214} while (0)
215
216/* this disables an interrupt from the interrupt mask register */
217#define SMC_DISABLE_INT(x) do { \
218 unsigned int __mask; \
219 unsigned long __flags; \
220 spin_lock_irqsave(&lp->lock, __flags); \
221 __mask = SMC_GET_INT_EN(); \
222 __mask &= ~(x); \
223 SMC_SET_INT_EN(__mask); \
224 spin_unlock_irqrestore(&lp->lock, __flags); \
225} while (0)
226
227/*
228 * this does a soft reset on the device
229 */
230static void smc911x_reset(struct net_device *dev)
231{
232 unsigned long ioaddr = dev->base_addr;
233 struct smc911x_local *lp = netdev_priv(dev);
234 unsigned int reg, timeout=0, resets=1;
235 unsigned long flags;
236
237 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
238
239 /* Take out of PM setting first */
240 if ((SMC_GET_PMT_CTRL() & PMT_CTRL_READY_) == 0) {
241 /* Write to the bytetest will take out of powerdown */
d5498bef 242 SMC_SET_BYTE_TEST(0);
0a0c72c9
DM		 243 timeout=10;
244 do {
245 udelay(10);
246 reg = SMC_GET_PMT_CTRL() & PMT_CTRL_READY_;
db2961c5 247 } while (--timeout && !reg);
0a0c72c9
DM		 248 if (timeout == 0) {
249 PRINTK("%s: smc911x_reset timeout waiting for PM restore\n", dev->name);
250 return;
251 }
252 }
253
254 /* Disable all interrupts */
255 spin_lock_irqsave(&lp->lock, flags);
256 SMC_SET_INT_EN(0);
257 spin_unlock_irqrestore(&lp->lock, flags);
258
259 while (resets--) {
260 SMC_SET_HW_CFG(HW_CFG_SRST_);
261 timeout=10;
262 do {
263 udelay(10);
264 reg = SMC_GET_HW_CFG();
265 /* If chip indicates reset timeout then try again */
266 if (reg & HW_CFG_SRST_TO_) {
267 PRINTK("%s: chip reset timeout, retrying...\n", dev->name);
268 resets++;
269 break;
270 }
db2961c5 271 } while (--timeout && (reg & HW_CFG_SRST_));
0a0c72c9
DM		 272 }
273 if (timeout == 0) {
274 PRINTK("%s: smc911x_reset timeout waiting for reset\n", dev->name);
275 return;
276 }
277
278 /* make sure EEPROM has finished loading before setting GPIO_CFG */
279 timeout=1000;
280 while ( timeout-- && (SMC_GET_E2P_CMD() & E2P_CMD_EPC_BUSY_)) {
281 udelay(10);
282 }
283 if (timeout == 0){
284 PRINTK("%s: smc911x_reset timeout waiting for EEPROM busy\n", dev->name);
285 return;
286 }
287
288 /* Initialize interrupts */
289 SMC_SET_INT_EN(0);
290 SMC_ACK_INT(-1);
291
292 /* Reset the FIFO level and flow control settings */
293 SMC_SET_HW_CFG((lp->tx_fifo_kb & 0xF) << 16);
294//TODO: Figure out what appropriate pause time is
295 SMC_SET_FLOW(FLOW_FCPT_ | FLOW_FCEN_);
296 SMC_SET_AFC_CFG(lp->afc_cfg);
297
298
299 /* Set to LED outputs */
300 SMC_SET_GPIO_CFG(0x70070000);
301
d5498bef 302 /*
0a0c72c9 303 * Deassert IRQ for 1*10us for edge type interrupts
d5498bef 304 * and drive IRQ pin push-pull
0a0c72c9
DM		 305 */
306 SMC_SET_IRQ_CFG( (1 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_ );
307
308 /* clear anything saved */
309 if (lp->pending_tx_skb != NULL) {
310 dev_kfree_skb (lp->pending_tx_skb);
311 lp->pending_tx_skb = NULL;
09f75cd7
JG		 312 dev->stats.tx_errors++;
313 dev->stats.tx_aborted_errors++;
0a0c72c9
DM		 314 }
315}
316
317/*
318 * Enable Interrupts, Receive, and Transmit
319 */
320static void smc911x_enable(struct net_device *dev)
321{
322 unsigned long ioaddr = dev->base_addr;
323 struct smc911x_local *lp = netdev_priv(dev);
324 unsigned mask, cfg, cr;
325 unsigned long flags;
326
327 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
328
329 SMC_SET_MAC_ADDR(dev->dev_addr);
330
331 /* Enable TX */
332 cfg = SMC_GET_HW_CFG();
333 cfg &= HW_CFG_TX_FIF_SZ_ | 0xFFF;
334 cfg |= HW_CFG_SF_;
335 SMC_SET_HW_CFG(cfg);
336 SMC_SET_FIFO_TDA(0xFF);
337 /* Update TX stats on every 64 packets received or every 1 sec */
338 SMC_SET_FIFO_TSL(64);
339 SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000);
340
341 spin_lock_irqsave(&lp->lock, flags);
342 SMC_GET_MAC_CR(cr);
343 cr |= MAC_CR_TXEN_ | MAC_CR_HBDIS_;
344 SMC_SET_MAC_CR(cr);
345 SMC_SET_TX_CFG(TX_CFG_TX_ON_);
346 spin_unlock_irqrestore(&lp->lock, flags);
347
348 /* Add 2 byte padding to start of packets */
349 SMC_SET_RX_CFG((2<<8) & RX_CFG_RXDOFF_);
350
351 /* Turn on receiver and enable RX */
352 if (cr & MAC_CR_RXEN_)
353 DBG(SMC_DEBUG_RX, "%s: Receiver already enabled\n", dev->name);
354
355 spin_lock_irqsave(&lp->lock, flags);
356 SMC_SET_MAC_CR( cr | MAC_CR_RXEN_ );
357 spin_unlock_irqrestore(&lp->lock, flags);
358
359 /* Interrupt on every received packet */
360 SMC_SET_FIFO_RSA(0x01);
361 SMC_SET_FIFO_RSL(0x00);
362
363 /* now, enable interrupts */
d5498bef
JG		 364 mask = INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_ | INT_EN_RSFL_EN_ |
365 INT_EN_GPT_INT_EN_ | INT_EN_RXDFH_INT_EN_ | INT_EN_RXE_EN_ |
0a0c72c9
DM		 366 INT_EN_PHY_INT_EN_;
367 if (IS_REV_A(lp->revision))
368 mask|=INT_EN_RDFL_EN_;
369 else {
370 mask|=INT_EN_RDFO_EN_;
371 }
372 SMC_ENABLE_INT(mask);
373}
374
375/*
376 * this puts the device in an inactive state
377 */
378static void smc911x_shutdown(struct net_device *dev)
379{
380 unsigned long ioaddr = dev->base_addr;
381 struct smc911x_local *lp = netdev_priv(dev);
382 unsigned cr;
383 unsigned long flags;
384
385 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", CARDNAME, __FUNCTION__);
386
387 /* Disable IRQ's */
388 SMC_SET_INT_EN(0);
389
390 /* Turn of Rx and TX */
391 spin_lock_irqsave(&lp->lock, flags);
392 SMC_GET_MAC_CR(cr);
393 cr &= ~(MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
394 SMC_SET_MAC_CR(cr);
395 SMC_SET_TX_CFG(TX_CFG_STOP_TX_);
396 spin_unlock_irqrestore(&lp->lock, flags);
397}
398
399static inline void smc911x_drop_pkt(struct net_device *dev)
d5498bef 400{
0a0c72c9
DM		 401 unsigned long ioaddr = dev->base_addr;
402 unsigned int fifo_count, timeout, reg;
403
404 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n", CARDNAME, __FUNCTION__);
d5498bef 405 fifo_count = SMC_GET_RX_FIFO_INF() & 0xFFFF;
0a0c72c9
DM		 406 if (fifo_count <= 4) {
407 /* Manually dump the packet data */
408 while (fifo_count--)
409 SMC_GET_RX_FIFO();
410 } else {
411 /* Fast forward through the bad packet */
412 SMC_SET_RX_DP_CTRL(RX_DP_CTRL_FFWD_BUSY_);
413 timeout=50;
414 do {
415 udelay(10);
416 reg = SMC_GET_RX_DP_CTRL() & RX_DP_CTRL_FFWD_BUSY_;
db2961c5 417 } while (--timeout && reg);
0a0c72c9
DM		 418 if (timeout == 0) {
419 PRINTK("%s: timeout waiting for RX fast forward\n", dev->name);
420 }
421 }
422}
423
424/*
425 * This is the procedure to handle the receipt of a packet.
426 * It should be called after checking for packet presence in
d5498bef 427 * the RX status FIFO. It must be called with the spin lock
0a0c72c9
DM		 428 * already held.
429 */
430static inline void smc911x_rcv(struct net_device *dev)
431{
0a0c72c9
DM		 432 unsigned long ioaddr = dev->base_addr;
433 unsigned int pkt_len, status;
434 struct sk_buff *skb;
435 unsigned char *data;
436
d5498bef 437 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n",
0a0c72c9
DM		 438 dev->name, __FUNCTION__);
439 status = SMC_GET_RX_STS_FIFO();
d5498bef 440 DBG(SMC_DEBUG_RX, "%s: Rx pkt len %d status 0x%08x \n",
0a0c72c9
DM		 441 dev->name, (status & 0x3fff0000) >> 16, status & 0xc000ffff);
442 pkt_len = (status & RX_STS_PKT_LEN_) >> 16;
d5498bef 443 if (status & RX_STS_ES_) {
0a0c72c9 444 /* Deal with a bad packet */
09f75cd7 445 dev->stats.rx_errors++;
d5498bef 446 if (status & RX_STS_CRC_ERR_)
09f75cd7 447 dev->stats.rx_crc_errors++;
0a0c72c9
DM		 448 else {
449 if (status & RX_STS_LEN_ERR_)
09f75cd7 450 dev->stats.rx_length_errors++;
d5498bef 451 if (status & RX_STS_MCAST_)
09f75cd7 452 dev->stats.multicast++;
0a0c72c9
DM		 453 }
454 /* Remove the bad packet data from the RX FIFO */
455 smc911x_drop_pkt(dev);
456 } else {
457 /* Receive a valid packet */
458 /* Alloc a buffer with extra room for DMA alignment */
459 skb=dev_alloc_skb(pkt_len+32);
460 if (unlikely(skb == NULL)) {
461 PRINTK( "%s: Low memory, rcvd packet dropped.\n",
462 dev->name);
09f75cd7 463 dev->stats.rx_dropped++;
0a0c72c9
DM		 464 smc911x_drop_pkt(dev);
465 return;
466 }
d5498bef 467 /* Align IP header to 32 bits
0a0c72c9 468 * Note that the device is configured to add a 2
d5498bef 469 * byte padding to the packet start, so we really
0a0c72c9
DM		 470 * want to write to the orignal data pointer */
471 data = skb->data;
472 skb_reserve(skb, 2);
473 skb_put(skb,pkt_len-4);
474#ifdef SMC_USE_DMA
475 {
a9b121c4 476 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM		 477 unsigned int fifo;
478 /* Lower the FIFO threshold if possible */
479 fifo = SMC_GET_FIFO_INT();
480 if (fifo & 0xFF) fifo--;
481 DBG(SMC_DEBUG_RX, "%s: Setting RX stat FIFO threshold to %d\n",
482 dev->name, fifo & 0xff);
483 SMC_SET_FIFO_INT(fifo);
484 /* Setup RX DMA */
485 SMC_SET_RX_CFG(RX_CFG_RX_END_ALGN16_ | ((2<<8) & RX_CFG_RXDOFF_));
486 lp->rxdma_active = 1;
487 lp->current_rx_skb = skb;
488 SMC_PULL_DATA(data, (pkt_len+2+15) & ~15);
489 /* Packet processing deferred to DMA RX interrupt */
490 }
491#else
492 SMC_SET_RX_CFG(RX_CFG_RX_END_ALGN4_ | ((2<<8) & RX_CFG_RXDOFF_));
493 SMC_PULL_DATA(data, pkt_len+2+3);
494
b4cf2058 495 DBG(SMC_DEBUG_PKTS, "%s: Received packet\n", dev->name);
0a0c72c9
DM		 496 PRINT_PKT(data, ((pkt_len - 4) <= 64) ? pkt_len - 4 : 64);
497 dev->last_rx = jiffies;
0a0c72c9
DM		 498 skb->protocol = eth_type_trans(skb, dev);
499 netif_rx(skb);
09f75cd7
JG		 500 dev->stats.rx_packets++;
501 dev->stats.rx_bytes += pkt_len-4;
0a0c72c9
DM		 502#endif
503 }
504}
505
506/*
507 * This is called to actually send a packet to the chip.
508 */
509static void smc911x_hardware_send_pkt(struct net_device *dev)
510{
511 struct smc911x_local *lp = netdev_priv(dev);
512 unsigned long ioaddr = dev->base_addr;
513 struct sk_buff *skb;
514 unsigned int cmdA, cmdB, len;
515 unsigned char *buf;
516 unsigned long flags;
517
518 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n", dev->name, __FUNCTION__);
519 BUG_ON(lp->pending_tx_skb == NULL);
520
521 skb = lp->pending_tx_skb;
522 lp->pending_tx_skb = NULL;
523
d5498bef
JG		 524 /* cmdA {25:24] data alignment [20:16] start offset [10:0] buffer length */
525 /* cmdB {31:16] pkt tag [10:0] length */
0a0c72c9
DM		 526#ifdef SMC_USE_DMA
527 /* 16 byte buffer alignment mode */
528 buf = (char*)((u32)(skb->data) & ~0xF);
d5498bef 529 len = (skb->len + 0xF + ((u32)skb->data & 0xF)) & ~0xF;
0a0c72c9
DM		 530 cmdA = (1<<24) | (((u32)skb->data & 0xF)<<16) |
531 TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
532 skb->len;
533#else
534 buf = (char*)((u32)skb->data & ~0x3);
d5498bef 535 len = (skb->len + 3 + ((u32)skb->data & 3)) & ~0x3;
0a0c72c9
DM		 536 cmdA = (((u32)skb->data & 0x3) << 16) |
537 TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
538 skb->len;
539#endif
d5498bef 540 /* tag is packet length so we can use this in stats update later */
0a0c72c9 541 cmdB = (skb->len << 16) | (skb->len & 0x7FF);
d5498bef 542
0a0c72c9
DM		 543 DBG(SMC_DEBUG_TX, "%s: TX PKT LENGTH 0x%04x (%d) BUF 0x%p CMDA 0x%08x CMDB 0x%08x\n",
544 dev->name, len, len, buf, cmdA, cmdB);
545 SMC_SET_TX_FIFO(cmdA);
546 SMC_SET_TX_FIFO(cmdB);
547
548 DBG(SMC_DEBUG_PKTS, "%s: Transmitted packet\n", dev->name);
549 PRINT_PKT(buf, len <= 64 ? len : 64);
550
551 /* Send pkt via PIO or DMA */
552#ifdef SMC_USE_DMA
553 lp->current_tx_skb = skb;
554 SMC_PUSH_DATA(buf, len);
555 /* DMA complete IRQ will free buffer and set jiffies */
556#else
557 SMC_PUSH_DATA(buf, len);
558 dev->trans_start = jiffies;
559 dev_kfree_skb(skb);
560#endif
561 spin_lock_irqsave(&lp->lock, flags);
562 if (!lp->tx_throttle) {
563 netif_wake_queue(dev);
564 }
565 spin_unlock_irqrestore(&lp->lock, flags);
566 SMC_ENABLE_INT(INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_);
567}
568
569/*
570 * Since I am not sure if I will have enough room in the chip's ram
571 * to store the packet, I call this routine which either sends it
572 * now, or set the card to generates an interrupt when ready
573 * for the packet.
574 */
575static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
576{
577 struct smc911x_local *lp = netdev_priv(dev);
578 unsigned long ioaddr = dev->base_addr;
579 unsigned int free;
580 unsigned long flags;
581
d5498bef 582 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n",
0a0c72c9
DM		 583 dev->name, __FUNCTION__);
584
585 BUG_ON(lp->pending_tx_skb != NULL);
586
587 free = SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TDFREE_;
588 DBG(SMC_DEBUG_TX, "%s: TX free space %d\n", dev->name, free);
589
590 /* Turn off the flow when running out of space in FIFO */
591 if (free <= SMC911X_TX_FIFO_LOW_THRESHOLD) {
d5498bef 592 DBG(SMC_DEBUG_TX, "%s: Disabling data flow due to low FIFO space (%d)\n",
0a0c72c9
DM		 593 dev->name, free);
594 spin_lock_irqsave(&lp->lock, flags);
595 /* Reenable when at least 1 packet of size MTU present */
596 SMC_SET_FIFO_TDA((SMC911X_TX_FIFO_LOW_THRESHOLD)/64);
597 lp->tx_throttle = 1;
598 netif_stop_queue(dev);
599 spin_unlock_irqrestore(&lp->lock, flags);
600 }
601
d5498bef 602 /* Drop packets when we run out of space in TX FIFO
0a0c72c9 603 * Account for overhead required for:
d5498bef
JG		 604 *
605 * Tx command words 8 bytes
0a0c72c9
DM		 606 * Start offset 15 bytes
607 * End padding 15 bytes
d5498bef 608 */
0a0c72c9 609 if (unlikely(free < (skb->len + 8 + 15 + 15))) {
d5498bef 610 printk("%s: No Tx free space %d < %d\n",
0a0c72c9
DM		 611 dev->name, free, skb->len);
612 lp->pending_tx_skb = NULL;
09f75cd7
JG		 613 dev->stats.tx_errors++;
614 dev->stats.tx_dropped++;
0a0c72c9
DM		 615 dev_kfree_skb(skb);
616 return 0;
617 }
d5498bef 618
0a0c72c9
DM		 619#ifdef SMC_USE_DMA
620 {
621 /* If the DMA is already running then defer this packet Tx until
d5498bef 622 * the DMA IRQ starts it
0a0c72c9
DM		 623 */
624 spin_lock_irqsave(&lp->lock, flags);
625 if (lp->txdma_active) {
626 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: Tx DMA running, deferring packet\n", dev->name);
627 lp->pending_tx_skb = skb;
628 netif_stop_queue(dev);
629 spin_unlock_irqrestore(&lp->lock, flags);
630 return 0;
631 } else {
632 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: Activating Tx DMA\n", dev->name);
633 lp->txdma_active = 1;
634 }
635 spin_unlock_irqrestore(&lp->lock, flags);
636 }
637#endif
638 lp->pending_tx_skb = skb;
639 smc911x_hardware_send_pkt(dev);
640
641 return 0;
642}
643
644/*
645 * This handles a TX status interrupt, which is only called when:
646 * - a TX error occurred, or
647 * - TX of a packet completed.
648 */
649static void smc911x_tx(struct net_device *dev)
650{
651 unsigned long ioaddr = dev->base_addr;
652 struct smc911x_local *lp = netdev_priv(dev);
653 unsigned int tx_status;
654
d5498bef 655 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n",
0a0c72c9
DM		 656 dev->name, __FUNCTION__);
657
658 /* Collect the TX status */
659 while (((SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TSUSED_) >> 16) != 0) {
d5498bef
JG		 660 DBG(SMC_DEBUG_TX, "%s: Tx stat FIFO used 0x%04x\n",
661 dev->name,
0a0c72c9
DM		 662 (SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TSUSED_) >> 16);
663 tx_status = SMC_GET_TX_STS_FIFO();
09f75cd7
JG		 664 dev->stats.tx_packets++;
665 dev->stats.tx_bytes+=tx_status>>16;
d5498bef
JG		 666 DBG(SMC_DEBUG_TX, "%s: Tx FIFO tag 0x%04x status 0x%04x\n",
667 dev->name, (tx_status & 0xffff0000) >> 16,
0a0c72c9 668 tx_status & 0x0000ffff);
d5498bef 669 /* count Tx errors, but ignore lost carrier errors when in
0a0c72c9 670 * full-duplex mode */
d5498bef 671 if ((tx_status & TX_STS_ES_) && !(lp->ctl_rfduplx &&
0a0c72c9 672 !(tx_status & 0x00000306))) {
09f75cd7 673 dev->stats.tx_errors++;
0a0c72c9
DM		 674 }
675 if (tx_status & TX_STS_MANY_COLL_) {
09f75cd7
JG		 676 dev->stats.collisions+=16;
677 dev->stats.tx_aborted_errors++;
0a0c72c9 678 } else {
09f75cd7 679 dev->stats.collisions+=(tx_status & TX_STS_COLL_CNT_) >> 3;
0a0c72c9
DM		 680 }
681 /* carrier error only has meaning for half-duplex communication */
d5498bef 682 if ((tx_status & (TX_STS_LOC_ | TX_STS_NO_CARR_)) &&
0a0c72c9 683 !lp->ctl_rfduplx) {
09f75cd7 684 dev->stats.tx_carrier_errors++;
d5498bef 685 }
0a0c72c9 686 if (tx_status & TX_STS_LATE_COLL_) {
09f75cd7
JG		 687 dev->stats.collisions++;
688 dev->stats.tx_aborted_errors++;
0a0c72c9
DM		 689 }
690 }
691}
692
693
694/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
695/*
696 * Reads a register from the MII Management serial interface
697 */
698
699static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg)
700{
701 unsigned long ioaddr = dev->base_addr;
702 unsigned int phydata;
703
704 SMC_GET_MII(phyreg, phyaddr, phydata);
705
706 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%02x, phydata=0x%04x\n",
707 __FUNCTION__, phyaddr, phyreg, phydata);
708 return phydata;
709}
710
711
712/*
713 * Writes a register to the MII Management serial interface
714 */
715static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg,
716 int phydata)
717{
718 unsigned long ioaddr = dev->base_addr;
719
720 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
721 __FUNCTION__, phyaddr, phyreg, phydata);
722
723 SMC_SET_MII(phyreg, phyaddr, phydata);
724}
725
726/*
727 * Finds and reports the PHY address (115 and 117 have external
728 * PHY interface 118 has internal only
729 */
730static void smc911x_phy_detect(struct net_device *dev)
731{
732 unsigned long ioaddr = dev->base_addr;
733 struct smc911x_local *lp = netdev_priv(dev);
734 int phyaddr;
735 unsigned int cfg, id1, id2;
736
737 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
738
739 lp->phy_type = 0;
740
741 /*
742 * Scan all 32 PHY addresses if necessary, starting at
743 * PHY#1 to PHY#31, and then PHY#0 last.
744 */
745 switch(lp->version) {
746 case 0x115:
747 case 0x117:
d5498bef 748 cfg = SMC_GET_HW_CFG();
0a0c72c9
DM		 749 if (cfg & HW_CFG_EXT_PHY_DET_) {
750 cfg &= ~HW_CFG_PHY_CLK_SEL_;
751 cfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
752 SMC_SET_HW_CFG(cfg);
753 udelay(10); /* Wait for clocks to stop */
754
755 cfg |= HW_CFG_EXT_PHY_EN_;
756 SMC_SET_HW_CFG(cfg);
757 udelay(10); /* Wait for clocks to stop */
758
759 cfg &= ~HW_CFG_PHY_CLK_SEL_;
760 cfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
761 SMC_SET_HW_CFG(cfg);
762 udelay(10); /* Wait for clocks to stop */
763
764 cfg |= HW_CFG_SMI_SEL_;
765 SMC_SET_HW_CFG(cfg);
766
767 for (phyaddr = 1; phyaddr < 32; ++phyaddr) {
768
769 /* Read the PHY identifiers */
770 SMC_GET_PHY_ID1(phyaddr & 31, id1);
771 SMC_GET_PHY_ID2(phyaddr & 31, id2);
772
773 /* Make sure it is a valid identifier */
d5498bef
JG		 774 if (id1 != 0x0000 && id1 != 0xffff &&
775 id1 != 0x8000 && id2 != 0x0000 &&
0a0c72c9
DM		 776 id2 != 0xffff && id2 != 0x8000) {
777 /* Save the PHY's address */
778 lp->mii.phy_id = phyaddr & 31;
779 lp->phy_type = id1 << 16 | id2;
780 break;
781 }
782 }
783 }
784 default:
785 /* Internal media only */
786 SMC_GET_PHY_ID1(1, id1);
787 SMC_GET_PHY_ID2(1, id2);
788 /* Save the PHY's address */
789 lp->mii.phy_id = 1;
790 lp->phy_type = id1 << 16 | id2;
791 }
792
793 DBG(SMC_DEBUG_MISC, "%s: phy_id1=0x%x, phy_id2=0x%x phyaddr=0x%d\n",
794 dev->name, id1, id2, lp->mii.phy_id);
795}
796
797/*
798 * Sets the PHY to a configuration as determined by the user.
799 * Called with spin_lock held.
800 */
801static int smc911x_phy_fixed(struct net_device *dev)
802{
803 struct smc911x_local *lp = netdev_priv(dev);
804 unsigned long ioaddr = dev->base_addr;
805 int phyaddr = lp->mii.phy_id;
806 int bmcr;
807
808 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
809
810 /* Enter Link Disable state */
811 SMC_GET_PHY_BMCR(phyaddr, bmcr);
812 bmcr |= BMCR_PDOWN;
813 SMC_SET_PHY_BMCR(phyaddr, bmcr);
814
815 /*
816 * Set our fixed capabilities
817 * Disable auto-negotiation
818 */
819 bmcr &= ~BMCR_ANENABLE;
820 if (lp->ctl_rfduplx)
821 bmcr |= BMCR_FULLDPLX;
822
823 if (lp->ctl_rspeed == 100)
824 bmcr |= BMCR_SPEED100;
825
826 /* Write our capabilities to the phy control register */
827 SMC_SET_PHY_BMCR(phyaddr, bmcr);
828
829 /* Re-Configure the Receive/Phy Control register */
830 bmcr &= ~BMCR_PDOWN;
831 SMC_SET_PHY_BMCR(phyaddr, bmcr);
832
833 return 1;
834}
835
836/*
837 * smc911x_phy_reset - reset the phy
838 * @dev: net device
839 * @phy: phy address
840 *
841 * Issue a software reset for the specified PHY and
842 * wait up to 100ms for the reset to complete. We should
843 * not access the PHY for 50ms after issuing the reset.
844 *
845 * The time to wait appears to be dependent on the PHY.
846 *
847 */
848static int smc911x_phy_reset(struct net_device *dev, int phy)
849{
850 struct smc911x_local *lp = netdev_priv(dev);
851 unsigned long ioaddr = dev->base_addr;
852 int timeout;
853 unsigned long flags;
854 unsigned int reg;
855
856 DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __FUNCTION__);
857
858 spin_lock_irqsave(&lp->lock, flags);
859 reg = SMC_GET_PMT_CTRL();
860 reg &= ~0xfffff030;
861 reg |= PMT_CTRL_PHY_RST_;
862 SMC_SET_PMT_CTRL(reg);
863 spin_unlock_irqrestore(&lp->lock, flags);
864 for (timeout = 2; timeout; timeout--) {
865 msleep(50);
866 spin_lock_irqsave(&lp->lock, flags);
867 reg = SMC_GET_PMT_CTRL();
868 spin_unlock_irqrestore(&lp->lock, flags);
869 if (!(reg & PMT_CTRL_PHY_RST_)) {
d5498bef 870 /* extra delay required because the phy may
0a0c72c9 871 * not be completed with its reset
d5498bef 872 * when PHY_BCR_RESET_ is cleared. 256us
0a0c72c9
DM		 873 * should suffice, but use 500us to be safe
874 */
875 udelay(500);
876 break;
877 }
878 }
879
880 return reg & PMT_CTRL_PHY_RST_;
881}
882
883/*
884 * smc911x_phy_powerdown - powerdown phy
885 * @dev: net device
886 * @phy: phy address
887 *
888 * Power down the specified PHY
889 */
890static void smc911x_phy_powerdown(struct net_device *dev, int phy)
891{
892 unsigned long ioaddr = dev->base_addr;
893 unsigned int bmcr;
894
895 /* Enter Link Disable state */
896 SMC_GET_PHY_BMCR(phy, bmcr);
897 bmcr |= BMCR_PDOWN;
898 SMC_SET_PHY_BMCR(phy, bmcr);
899}
900
901/*
902 * smc911x_phy_check_media - check the media status and adjust BMCR
903 * @dev: net device
904 * @init: set true for initialisation
905 *
906 * Select duplex mode depending on negotiation state. This
907 * also updates our carrier state.
908 */
909static void smc911x_phy_check_media(struct net_device *dev, int init)
910{
911 struct smc911x_local *lp = netdev_priv(dev);
912 unsigned long ioaddr = dev->base_addr;
913 int phyaddr = lp->mii.phy_id;
914 unsigned int bmcr, cr;
915
916 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
917
918 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
919 /* duplex state has changed */
920 SMC_GET_PHY_BMCR(phyaddr, bmcr);
921 SMC_GET_MAC_CR(cr);
922 if (lp->mii.full_duplex) {
923 DBG(SMC_DEBUG_MISC, "%s: Configuring for full-duplex mode\n", dev->name);
924 bmcr |= BMCR_FULLDPLX;
925 cr |= MAC_CR_RCVOWN_;
926 } else {
927 DBG(SMC_DEBUG_MISC, "%s: Configuring for half-duplex mode\n", dev->name);
928 bmcr &= ~BMCR_FULLDPLX;
929 cr &= ~MAC_CR_RCVOWN_;
930 }
931 SMC_SET_PHY_BMCR(phyaddr, bmcr);
932 SMC_SET_MAC_CR(cr);
933 }
934}
935
936/*
937 * Configures the specified PHY through the MII management interface
938 * using Autonegotiation.
939 * Calls smc911x_phy_fixed() if the user has requested a certain config.
940 * If RPC ANEG bit is set, the media selection is dependent purely on
941 * the selection by the MII (either in the MII BMCR reg or the result
942 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection
943 * is controlled by the RPC SPEED and RPC DPLX bits.
944 */
ef8142a5 945static void smc911x_phy_configure(struct work_struct *work)
0a0c72c9 946{
ef8142a5
AM		 947 struct smc911x_local *lp = container_of(work, struct smc911x_local,
948 phy_configure);
949 struct net_device *dev = lp->netdev;
0a0c72c9
DM		 950 unsigned long ioaddr = dev->base_addr;
951 int phyaddr = lp->mii.phy_id;
952 int my_phy_caps; /* My PHY capabilities */
953 int my_ad_caps; /* My Advertised capabilities */
954 int status;
955 unsigned long flags;
956
957 DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __FUNCTION__);
958
959 /*
960 * We should not be called if phy_type is zero.
961 */
962 if (lp->phy_type == 0)
24d8f6ad 963 goto smc911x_phy_configure_exit_nolock;
0a0c72c9
DM		 964
965 if (smc911x_phy_reset(dev, phyaddr)) {
966 printk("%s: PHY reset timed out\n", dev->name);
24d8f6ad 967 goto smc911x_phy_configure_exit_nolock;
0a0c72c9
DM		 968 }
969 spin_lock_irqsave(&lp->lock, flags);
970
971 /*
972 * Enable PHY Interrupts (for register 18)
973 * Interrupts listed here are enabled
974 */
975 SMC_SET_PHY_INT_MASK(phyaddr, PHY_INT_MASK_ENERGY_ON_ |
976 PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_REMOTE_FAULT_ |
977 PHY_INT_MASK_LINK_DOWN_);
978
979 /* If the user requested no auto neg, then go set his request */
980 if (lp->mii.force_media) {
981 smc911x_phy_fixed(dev);
982 goto smc911x_phy_configure_exit;
983 }
984
985 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
986 SMC_GET_PHY_BMSR(phyaddr, my_phy_caps);
987 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
988 printk(KERN_INFO "Auto negotiation NOT supported\n");
989 smc911x_phy_fixed(dev);
990 goto smc911x_phy_configure_exit;
991 }
992
993 /* CSMA capable w/ both pauses */
994 my_ad_caps = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
995
996 if (my_phy_caps & BMSR_100BASE4)
997 my_ad_caps |= ADVERTISE_100BASE4;
998 if (my_phy_caps & BMSR_100FULL)
999 my_ad_caps |= ADVERTISE_100FULL;
1000 if (my_phy_caps & BMSR_100HALF)
1001 my_ad_caps |= ADVERTISE_100HALF;
1002 if (my_phy_caps & BMSR_10FULL)
1003 my_ad_caps |= ADVERTISE_10FULL;
1004 if (my_phy_caps & BMSR_10HALF)
1005 my_ad_caps |= ADVERTISE_10HALF;
1006
1007 /* Disable capabilities not selected by our user */
1008 if (lp->ctl_rspeed != 100)
1009 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
1010
1011 if (!lp->ctl_rfduplx)
1012 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
1013
1014 /* Update our Auto-Neg Advertisement Register */
1015 SMC_SET_PHY_MII_ADV(phyaddr, my_ad_caps);
1016 lp->mii.advertising = my_ad_caps;
1017
1018 /*
1019 * Read the register back. Without this, it appears that when
1020 * auto-negotiation is restarted, sometimes it isn't ready and
1021 * the link does not come up.
1022 */
1023 udelay(10);
1024 SMC_GET_PHY_MII_ADV(phyaddr, status);
1025
1026 DBG(SMC_DEBUG_MISC, "%s: phy caps=0x%04x\n", dev->name, my_phy_caps);
1027 DBG(SMC_DEBUG_MISC, "%s: phy advertised caps=0x%04x\n", dev->name, my_ad_caps);
1028
1029 /* Restart auto-negotiation process in order to advertise my caps */
1030 SMC_SET_PHY_BMCR(phyaddr, BMCR_ANENABLE | BMCR_ANRESTART);
1031
1032 smc911x_phy_check_media(dev, 1);
1033
1034smc911x_phy_configure_exit:
1035 spin_unlock_irqrestore(&lp->lock, flags);
24d8f6ad 1036smc911x_phy_configure_exit_nolock:
0a0c72c9
DM		 1037 lp->work_pending = 0;
1038}
1039
1040/*
1041 * smc911x_phy_interrupt
1042 *
1043 * Purpose: Handle interrupts relating to PHY register 18. This is
1044 * called from the "hard" interrupt handler under our private spinlock.
1045 */
1046static void smc911x_phy_interrupt(struct net_device *dev)
1047{
1048 struct smc911x_local *lp = netdev_priv(dev);
1049 unsigned long ioaddr = dev->base_addr;
1050 int phyaddr = lp->mii.phy_id;
1051 int status;
1052
1053 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1054
1055 if (lp->phy_type == 0)
1056 return;
1057
1058 smc911x_phy_check_media(dev, 0);
1059 /* read to clear status bits */
1060 SMC_GET_PHY_INT_SRC(phyaddr,status);
d5498bef 1061 DBG(SMC_DEBUG_MISC, "%s: PHY interrupt status 0x%04x\n",
0a0c72c9 1062 dev->name, status & 0xffff);
d5498bef 1063 DBG(SMC_DEBUG_MISC, "%s: AFC_CFG 0x%08x\n",
0a0c72c9
DM		 1064 dev->name, SMC_GET_AFC_CFG());
1065}
1066
1067/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
1068
1069/*
1070 * This is the main routine of the driver, to handle the device when
1071 * it needs some attention.
1072 */
7d12e780 1073static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
0a0c72c9
DM		 1074{
1075 struct net_device *dev = dev_id;
1076 unsigned long ioaddr = dev->base_addr;
1077 struct smc911x_local *lp = netdev_priv(dev);
1078 unsigned int status, mask, timeout;
1079 unsigned int rx_overrun=0, cr, pkts;
1080 unsigned long flags;
1081
1082 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1083
1084 spin_lock_irqsave(&lp->lock, flags);
1085
1086 /* Spurious interrupt check */
1087 if ((SMC_GET_IRQ_CFG() & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) !=
1088 (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) {
a4d09272 1089 spin_unlock_irqrestore(&lp->lock, flags);
0a0c72c9
DM		 1090 return IRQ_NONE;
1091 }
1092
1093 mask = SMC_GET_INT_EN();
1094 SMC_SET_INT_EN(0);
1095
1096 /* set a timeout value, so I don't stay here forever */
1097 timeout = 8;
1098
1099
1100 do {
1101 status = SMC_GET_INT();
1102
1103 DBG(SMC_DEBUG_MISC, "%s: INT 0x%08x MASK 0x%08x OUTSIDE MASK 0x%08x\n",
1104 dev->name, status, mask, status & ~mask);
1105
1106 status &= mask;
1107 if (!status)
1108 break;
1109
1110 /* Handle SW interrupt condition */
1111 if (status & INT_STS_SW_INT_) {
1112 SMC_ACK_INT(INT_STS_SW_INT_);
1113 mask &= ~INT_EN_SW_INT_EN_;
1114 }
1115 /* Handle various error conditions */
1116 if (status & INT_STS_RXE_) {
1117 SMC_ACK_INT(INT_STS_RXE_);
09f75cd7 1118 dev->stats.rx_errors++;
d5498bef 1119 }
0a0c72c9
DM		 1120 if (status & INT_STS_RXDFH_INT_) {
1121 SMC_ACK_INT(INT_STS_RXDFH_INT_);
09f75cd7 1122 dev->stats.rx_dropped+=SMC_GET_RX_DROP();
0a0c72c9
DM		 1123 }
1124 /* Undocumented interrupt-what is the right thing to do here? */
1125 if (status & INT_STS_RXDF_INT_) {
1126 SMC_ACK_INT(INT_STS_RXDF_INT_);
1127 }
1128
1129 /* Rx Data FIFO exceeds set level */
1130 if (status & INT_STS_RDFL_) {
1131 if (IS_REV_A(lp->revision)) {
1132 rx_overrun=1;
1133 SMC_GET_MAC_CR(cr);
1134 cr &= ~MAC_CR_RXEN_;
1135 SMC_SET_MAC_CR(cr);
1136 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
09f75cd7
JG		 1137 dev->stats.rx_errors++;
1138 dev->stats.rx_fifo_errors++;
0a0c72c9
DM		 1139 }
1140 SMC_ACK_INT(INT_STS_RDFL_);
1141 }
1142 if (status & INT_STS_RDFO_) {
1143 if (!IS_REV_A(lp->revision)) {
1144 SMC_GET_MAC_CR(cr);
1145 cr &= ~MAC_CR_RXEN_;
1146 SMC_SET_MAC_CR(cr);
1147 rx_overrun=1;
1148 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
09f75cd7
JG		 1149 dev->stats.rx_errors++;
1150 dev->stats.rx_fifo_errors++;
0a0c72c9
DM		 1151 }
1152 SMC_ACK_INT(INT_STS_RDFO_);
1153 }
1154 /* Handle receive condition */
1155 if ((status & INT_STS_RSFL_) || rx_overrun) {
1156 unsigned int fifo;
1157 DBG(SMC_DEBUG_RX, "%s: RX irq\n", dev->name);
d5498bef
JG		 1158 fifo = SMC_GET_RX_FIFO_INF();
1159 pkts = (fifo & RX_FIFO_INF_RXSUSED_) >> 16;
1160 DBG(SMC_DEBUG_RX, "%s: Rx FIFO pkts %d, bytes %d\n",
0a0c72c9
DM		 1161 dev->name, pkts, fifo & 0xFFFF );
1162 if (pkts != 0) {
1163#ifdef SMC_USE_DMA
1164 unsigned int fifo;
1165 if (lp->rxdma_active){
d5498bef 1166 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA,
0a0c72c9
DM		 1167 "%s: RX DMA active\n", dev->name);
1168 /* The DMA is already running so up the IRQ threshold */
1169 fifo = SMC_GET_FIFO_INT() & ~0xFF;
1170 fifo |= pkts & 0xFF;
d5498bef 1171 DBG(SMC_DEBUG_RX,
0a0c72c9
DM		 1172 "%s: Setting RX stat FIFO threshold to %d\n",
1173 dev->name, fifo & 0xff);
1174 SMC_SET_FIFO_INT(fifo);
1175 } else
1176#endif
1177 smc911x_rcv(dev);
1178 }
1179 SMC_ACK_INT(INT_STS_RSFL_);
1180 }
1181 /* Handle transmit FIFO available */
1182 if (status & INT_STS_TDFA_) {
1183 DBG(SMC_DEBUG_TX, "%s: TX data FIFO space available irq\n", dev->name);
1184 SMC_SET_FIFO_TDA(0xFF);
1185 lp->tx_throttle = 0;
1186#ifdef SMC_USE_DMA
1187 if (!lp->txdma_active)
1188#endif
1189 netif_wake_queue(dev);
1190 SMC_ACK_INT(INT_STS_TDFA_);
1191 }
1192 /* Handle transmit done condition */
1193#if 1
1194 if (status & (INT_STS_TSFL_ | INT_STS_GPT_INT_)) {
d5498bef
JG		 1195 DBG(SMC_DEBUG_TX | SMC_DEBUG_MISC,
1196 "%s: Tx stat FIFO limit (%d) /GPT irq\n",
0a0c72c9
DM		 1197 dev->name, (SMC_GET_FIFO_INT() & 0x00ff0000) >> 16);
1198 smc911x_tx(dev);
1199 SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000);
1200 SMC_ACK_INT(INT_STS_TSFL_);
1201 SMC_ACK_INT(INT_STS_TSFL_ | INT_STS_GPT_INT_);
1202 }
1203#else
1204 if (status & INT_STS_TSFL_) {
1205 DBG(SMC_DEBUG_TX, "%s: TX status FIFO limit (%d) irq \n", dev->name, );
1206 smc911x_tx(dev);
1207 SMC_ACK_INT(INT_STS_TSFL_);
1208 }
1209
1210 if (status & INT_STS_GPT_INT_) {
d5498bef
JG		 1211 DBG(SMC_DEBUG_RX, "%s: IRQ_CFG 0x%08x FIFO_INT 0x%08x RX_CFG 0x%08x\n",
1212 dev->name,
1213 SMC_GET_IRQ_CFG(),
1214 SMC_GET_FIFO_INT(),
0a0c72c9
DM		 1215 SMC_GET_RX_CFG());
1216 DBG(SMC_DEBUG_RX, "%s: Rx Stat FIFO Used 0x%02x "
1217 "Data FIFO Used 0x%04x Stat FIFO 0x%08x\n",
d5498bef
JG		 1218 dev->name,
1219 (SMC_GET_RX_FIFO_INF() & 0x00ff0000) >> 16,
1220 SMC_GET_RX_FIFO_INF() & 0xffff,
0a0c72c9
DM		 1221 SMC_GET_RX_STS_FIFO_PEEK());
1222 SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000);
1223 SMC_ACK_INT(INT_STS_GPT_INT_);
1224 }
1225#endif
1226
3a4fa0a2 1227 /* Handle PHY interrupt condition */
0a0c72c9
DM		 1228 if (status & INT_STS_PHY_INT_) {
1229 DBG(SMC_DEBUG_MISC, "%s: PHY irq\n", dev->name);
1230 smc911x_phy_interrupt(dev);
1231 SMC_ACK_INT(INT_STS_PHY_INT_);
1232 }
1233 } while (--timeout);
1234
1235 /* restore mask state */
1236 SMC_SET_INT_EN(mask);
1237
d5498bef 1238 DBG(SMC_DEBUG_MISC, "%s: Interrupt done (%d loops)\n",
0a0c72c9
DM		 1239 dev->name, 8-timeout);
1240
1241 spin_unlock_irqrestore(&lp->lock, flags);
1242
1243 DBG(3, "%s: Interrupt done (%d loops)\n", dev->name, 8-timeout);
1244
1245 return IRQ_HANDLED;
1246}
1247
1248#ifdef SMC_USE_DMA
1249static void
7d12e780 1250smc911x_tx_dma_irq(int dma, void *data)
0a0c72c9
DM		 1251{
1252 struct net_device *dev = (struct net_device *)data;
1253 struct smc911x_local *lp = netdev_priv(dev);
1254 struct sk_buff *skb = lp->current_tx_skb;
1255 unsigned long flags;
1256
1257 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1258
1259 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: TX DMA irq handler\n", dev->name);
1260 /* Clear the DMA interrupt sources */
1261 SMC_DMA_ACK_IRQ(dev, dma);
1262 BUG_ON(skb == NULL);
1263 dma_unmap_single(NULL, tx_dmabuf, tx_dmalen, DMA_TO_DEVICE);
1264 dev->trans_start = jiffies;
1265 dev_kfree_skb_irq(skb);
1266 lp->current_tx_skb = NULL;
1267 if (lp->pending_tx_skb != NULL)
1268 smc911x_hardware_send_pkt(dev);
1269 else {
d5498bef 1270 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA,
0a0c72c9
DM		 1271 "%s: No pending Tx packets. DMA disabled\n", dev->name);
1272 spin_lock_irqsave(&lp->lock, flags);
1273 lp->txdma_active = 0;
1274 if (!lp->tx_throttle) {
1275 netif_wake_queue(dev);
1276 }
1277 spin_unlock_irqrestore(&lp->lock, flags);
1278 }
1279
d5498bef 1280 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA,
0a0c72c9
DM		 1281 "%s: TX DMA irq completed\n", dev->name);
1282}
1283static void
7d12e780 1284smc911x_rx_dma_irq(int dma, void *data)
0a0c72c9
DM		 1285{
1286 struct net_device *dev = (struct net_device *)data;
1287 unsigned long ioaddr = dev->base_addr;
1288 struct smc911x_local *lp = netdev_priv(dev);
1289 struct sk_buff *skb = lp->current_rx_skb;
1290 unsigned long flags;
1291 unsigned int pkts;
1292
1293 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1294 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, "%s: RX DMA irq handler\n", dev->name);
1295 /* Clear the DMA interrupt sources */
1296 SMC_DMA_ACK_IRQ(dev, dma);
1297 dma_unmap_single(NULL, rx_dmabuf, rx_dmalen, DMA_FROM_DEVICE);
1298 BUG_ON(skb == NULL);
1299 lp->current_rx_skb = NULL;
1300 PRINT_PKT(skb->data, skb->len);
1301 dev->last_rx = jiffies;
0a0c72c9 1302 skb->protocol = eth_type_trans(skb, dev);
09f75cd7
JG		 1303 dev->stats.rx_packets++;
1304 dev->stats.rx_bytes += skb->len;
d30f53ae 1305 netif_rx(skb);
0a0c72c9
DM		 1306
1307 spin_lock_irqsave(&lp->lock, flags);
d5498bef 1308 pkts = (SMC_GET_RX_FIFO_INF() & RX_FIFO_INF_RXSUSED_) >> 16;
0a0c72c9
DM		 1309 if (pkts != 0) {
1310 smc911x_rcv(dev);
1311 }else {
1312 lp->rxdma_active = 0;
1313 }
1314 spin_unlock_irqrestore(&lp->lock, flags);
d5498bef
JG		 1315 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA,
1316 "%s: RX DMA irq completed. DMA RX FIFO PKTS %d\n",
0a0c72c9
DM		 1317 dev->name, pkts);
1318}
1319#endif /* SMC_USE_DMA */
1320
1321#ifdef CONFIG_NET_POLL_CONTROLLER
1322/*
1323 * Polling receive - used by netconsole and other diagnostic tools
1324 * to allow network i/o with interrupts disabled.
1325 */
1326static void smc911x_poll_controller(struct net_device *dev)
1327{
1328 disable_irq(dev->irq);
9b6d2efe 1329 smc911x_interrupt(dev->irq, dev);
0a0c72c9
DM		 1330 enable_irq(dev->irq);
1331}
1332#endif
1333
1334/* Our watchdog timed out. Called by the networking layer */
1335static void smc911x_timeout(struct net_device *dev)
1336{
1337 struct smc911x_local *lp = netdev_priv(dev);
1338 unsigned long ioaddr = dev->base_addr;
1339 int status, mask;
1340 unsigned long flags;
1341
1342 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1343
1344 spin_lock_irqsave(&lp->lock, flags);
1345 status = SMC_GET_INT();
1346 mask = SMC_GET_INT_EN();
1347 spin_unlock_irqrestore(&lp->lock, flags);
1348 DBG(SMC_DEBUG_MISC, "%s: INT 0x%02x MASK 0x%02x \n",
1349 dev->name, status, mask);
1350
1351 /* Dump the current TX FIFO contents and restart */
d5498bef
JG		 1352 mask = SMC_GET_TX_CFG();
1353 SMC_SET_TX_CFG(mask | TX_CFG_TXS_DUMP_ | TX_CFG_TXD_DUMP_);
0a0c72c9
DM		 1354 /*
1355 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1356 * smc911x_phy_configure() calls msleep() which calls schedule_timeout()
1357 * which calls schedule(). Hence we use a work queue.
1358 */
1359 if (lp->phy_type != 0) {
1360 if (schedule_work(&lp->phy_configure)) {
1361 lp->work_pending = 1;
1362 }
1363 }
1364
1365 /* We can accept TX packets again */
1366 dev->trans_start = jiffies;
1367 netif_wake_queue(dev);
1368}
1369
1370/*
1371 * This routine will, depending on the values passed to it,
1372 * either make it accept multicast packets, go into
1373 * promiscuous mode (for TCPDUMP and cousins) or accept
1374 * a select set of multicast packets
1375 */
1376static void smc911x_set_multicast_list(struct net_device *dev)
1377{
1378 struct smc911x_local *lp = netdev_priv(dev);
1379 unsigned long ioaddr = dev->base_addr;
1380 unsigned int multicast_table[2];
1381 unsigned int mcr, update_multicast = 0;
1382 unsigned long flags;
0a0c72c9
DM		 1383
1384 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1385
1386 spin_lock_irqsave(&lp->lock, flags);
1387 SMC_GET_MAC_CR(mcr);
1388 spin_unlock_irqrestore(&lp->lock, flags);
1389
1390 if (dev->flags & IFF_PROMISC) {
1391
1392 DBG(SMC_DEBUG_MISC, "%s: RCR_PRMS\n", dev->name);
1393 mcr |= MAC_CR_PRMS_;
1394 }
1395 /*
1396 * Here, I am setting this to accept all multicast packets.
1397 * I don't need to zero the multicast table, because the flag is
1398 * checked before the table is
1399 */
1400 else if (dev->flags & IFF_ALLMULTI || dev->mc_count > 16) {
1401 DBG(SMC_DEBUG_MISC, "%s: RCR_ALMUL\n", dev->name);
1402 mcr |= MAC_CR_MCPAS_;
1403 }
1404
1405 /*
1406 * This sets the internal hardware table to filter out unwanted
1407 * multicast packets before they take up memory.
1408 *
1409 * The SMC chip uses a hash table where the high 6 bits of the CRC of
1410 * address are the offset into the table. If that bit is 1, then the
1411 * multicast packet is accepted. Otherwise, it's dropped silently.
1412 *
1413 * To use the 6 bits as an offset into the table, the high 1 bit is
1414 * the number of the 32 bit register, while the low 5 bits are the bit
1415 * within that register.
1416 */
1417 else if (dev->mc_count) {
1418 int i;
1419 struct dev_mc_list *cur_addr;
1420
1421 /* Set the Hash perfec mode */
1422 mcr |= MAC_CR_HPFILT_;
1423
1424 /* start with a table of all zeros: reject all */
1425 memset(multicast_table, 0, sizeof(multicast_table));
1426
1427 cur_addr = dev->mc_list;
1428 for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
7b31f7ff 1429 u32 position;
0a0c72c9
DM		 1430
1431 /* do we have a pointer here? */
1432 if (!cur_addr)
1433 break;
1434 /* make sure this is a multicast address -
1435 shouldn't this be a given if we have it here ? */
1436 if (!(*cur_addr->dmi_addr & 1))
1437 continue;
1438
7b31f7ff
PK		 1439 /* upper 6 bits are used as hash index */
1440 position = ether_crc(ETH_ALEN, cur_addr->dmi_addr)>>26;
0a0c72c9 1441
7b31f7ff 1442 multicast_table[position>>5] |= 1 << (position&0x1f);
0a0c72c9
DM		 1443 }
1444
1445 /* be sure I get rid of flags I might have set */
1446 mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1447
1448 /* now, the table can be loaded into the chipset */
1449 update_multicast = 1;
1450 } else {
d5498bef 1451 DBG(SMC_DEBUG_MISC, "%s: ~(MAC_CR_PRMS_|MAC_CR_MCPAS_)\n",
0a0c72c9
DM		 1452 dev->name);
1453 mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1454
1455 /*
1456 * since I'm disabling all multicast entirely, I need to
1457 * clear the multicast list
1458 */
1459 memset(multicast_table, 0, sizeof(multicast_table));
1460 update_multicast = 1;
1461 }
1462
1463 spin_lock_irqsave(&lp->lock, flags);
1464 SMC_SET_MAC_CR(mcr);
1465 if (update_multicast) {
d5498bef
JG		 1466 DBG(SMC_DEBUG_MISC,
1467 "%s: update mcast hash table 0x%08x 0x%08x\n",
0a0c72c9
DM		 1468 dev->name, multicast_table[0], multicast_table[1]);
1469 SMC_SET_HASHL(multicast_table[0]);
1470 SMC_SET_HASHH(multicast_table[1]);
1471 }
1472 spin_unlock_irqrestore(&lp->lock, flags);
1473}
1474
1475
1476/*
1477 * Open and Initialize the board
1478 *
1479 * Set up everything, reset the card, etc..
1480 */
1481static int
1482smc911x_open(struct net_device *dev)
1483{
ef8142a5
AM		 1484 struct smc911x_local *lp = netdev_priv(dev);
1485
0a0c72c9
DM		 1486 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1487
1488 /*
1489 * Check that the address is valid. If its not, refuse
1490 * to bring the device up. The user must specify an
1491 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1492 */
1493 if (!is_valid_ether_addr(dev->dev_addr)) {
1494 PRINTK("%s: no valid ethernet hw addr\n", __FUNCTION__);
1495 return -EINVAL;
1496 }
1497
1498 /* reset the hardware */
1499 smc911x_reset(dev);
1500
1501 /* Configure the PHY, initialize the link state */
ef8142a5 1502 smc911x_phy_configure(&lp->phy_configure);
0a0c72c9
DM		 1503
1504 /* Turn on Tx + Rx */
1505 smc911x_enable(dev);
1506
1507 netif_start_queue(dev);
1508
1509 return 0;
1510}
1511
1512/*
1513 * smc911x_close
1514 *
1515 * this makes the board clean up everything that it can
1516 * and not talk to the outside world. Caused by
1517 * an 'ifconfig ethX down'
1518 */
1519static int smc911x_close(struct net_device *dev)
1520{
1521 struct smc911x_local *lp = netdev_priv(dev);
1522
1523 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1524
1525 netif_stop_queue(dev);
1526 netif_carrier_off(dev);
1527
1528 /* clear everything */
1529 smc911x_shutdown(dev);
1530
1531 if (lp->phy_type != 0) {
1532 /* We need to ensure that no calls to
1533 * smc911x_phy_configure are pending.
1534
1535 * flush_scheduled_work() cannot be called because we
1536 * are running with the netlink semaphore held (from
1537 * devinet_ioctl()) and the pending work queue
1538 * contains linkwatch_event() (scheduled by
1539 * netif_carrier_off() above). linkwatch_event() also
1540 * wants the netlink semaphore.
1541 */
1542 while (lp->work_pending)
1543 schedule();
1544 smc911x_phy_powerdown(dev, lp->mii.phy_id);
1545 }
1546
1547 if (lp->pending_tx_skb) {
1548 dev_kfree_skb(lp->pending_tx_skb);
1549 lp->pending_tx_skb = NULL;
1550 }
1551
1552 return 0;
1553}
1554
0a0c72c9
DM		 1555/*
1556 * Ethtool support
1557 */
1558static int
1559smc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1560{
1561 struct smc911x_local *lp = netdev_priv(dev);
1562 unsigned long ioaddr = dev->base_addr;
1563 int ret, status;
1564 unsigned long flags;
1565
1566 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1567 cmd->maxtxpkt = 1;
1568 cmd->maxrxpkt = 1;
1569
1570 if (lp->phy_type != 0) {
1571 spin_lock_irqsave(&lp->lock, flags);
1572 ret = mii_ethtool_gset(&lp->mii, cmd);
1573 spin_unlock_irqrestore(&lp->lock, flags);
1574 } else {
1575 cmd->supported = SUPPORTED_10baseT_Half |
1576 SUPPORTED_10baseT_Full |
1577 SUPPORTED_TP | SUPPORTED_AUI;
1578
1579 if (lp->ctl_rspeed == 10)
1580 cmd->speed = SPEED_10;
1581 else if (lp->ctl_rspeed == 100)
1582 cmd->speed = SPEED_100;
1583
1584 cmd->autoneg = AUTONEG_DISABLE;
1585 if (lp->mii.phy_id==1)
1586 cmd->transceiver = XCVR_INTERNAL;
1587 else
1588 cmd->transceiver = XCVR_EXTERNAL;
1589 cmd->port = 0;
1590 SMC_GET_PHY_SPECIAL(lp->mii.phy_id, status);
d5498bef
JG		 1591 cmd->duplex =
1592 (status & (PHY_SPECIAL_SPD_10FULL_ | PHY_SPECIAL_SPD_100FULL_)) ?
0a0c72c9
DM		 1593 DUPLEX_FULL : DUPLEX_HALF;
1594 ret = 0;
1595 }
1596
1597 return ret;
1598}
1599
1600static int
1601smc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1602{
1603 struct smc911x_local *lp = netdev_priv(dev);
1604 int ret;
1605 unsigned long flags;
1606
1607 if (lp->phy_type != 0) {
1608 spin_lock_irqsave(&lp->lock, flags);
1609 ret = mii_ethtool_sset(&lp->mii, cmd);
1610 spin_unlock_irqrestore(&lp->lock, flags);
1611 } else {
1612 if (cmd->autoneg != AUTONEG_DISABLE ||
1613 cmd->speed != SPEED_10 ||
1614 (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) ||
1615 (cmd->port != PORT_TP && cmd->port != PORT_AUI))
1616 return -EINVAL;
1617
1618 lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL;
1619
1620 ret = 0;
1621 }
1622
1623 return ret;
1624}
1625
1626static void
1627smc911x_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1628{
1629 strncpy(info->driver, CARDNAME, sizeof(info->driver));
1630 strncpy(info->version, version, sizeof(info->version));
43cb76d9 1631 strncpy(info->bus_info, dev->dev.parent->bus_id, sizeof(info->bus_info));
0a0c72c9
DM		 1632}
1633
1634static int smc911x_ethtool_nwayreset(struct net_device *dev)
1635{
1636 struct smc911x_local *lp = netdev_priv(dev);
1637 int ret = -EINVAL;
1638 unsigned long flags;
1639
1640 if (lp->phy_type != 0) {
1641 spin_lock_irqsave(&lp->lock, flags);
1642 ret = mii_nway_restart(&lp->mii);
1643 spin_unlock_irqrestore(&lp->lock, flags);
1644 }
1645
1646 return ret;
1647}
1648
1649static u32 smc911x_ethtool_getmsglevel(struct net_device *dev)
1650{
1651 struct smc911x_local *lp = netdev_priv(dev);
1652 return lp->msg_enable;
1653}
1654
1655static void smc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1656{
1657 struct smc911x_local *lp = netdev_priv(dev);
1658 lp->msg_enable = level;
1659}
1660
1661static int smc911x_ethtool_getregslen(struct net_device *dev)
1662{
1663 /* System regs + MAC regs + PHY regs */
d5498bef
JG		 1664 return (((E2P_CMD - ID_REV)/4 + 1) +
1665 (WUCSR - MAC_CR)+1 + 32) * sizeof(u32);
0a0c72c9
DM		 1666}
1667
d5498bef 1668static void smc911x_ethtool_getregs(struct net_device *dev,
0a0c72c9
DM		 1669 struct ethtool_regs* regs, void *buf)
1670{
1671 unsigned long ioaddr = dev->base_addr;
1672 struct smc911x_local *lp = netdev_priv(dev);
1673 unsigned long flags;
1674 u32 reg,i,j=0;
1675 u32 *data = (u32*)buf;
1676
1677 regs->version = lp->version;
1678 for(i=ID_REV;i<=E2P_CMD;i+=4) {
d5498bef 1679 data[j++] = SMC_inl(ioaddr,i);
0a0c72c9
DM		 1680 }
1681 for(i=MAC_CR;i<=WUCSR;i++) {
1682 spin_lock_irqsave(&lp->lock, flags);
1683 SMC_GET_MAC_CSR(i, reg);
1684 spin_unlock_irqrestore(&lp->lock, flags);
d5498bef 1685 data[j++] = reg;
0a0c72c9
DM		 1686 }
1687 for(i=0;i<=31;i++) {
1688 spin_lock_irqsave(&lp->lock, flags);
1689 SMC_GET_MII(i, lp->mii.phy_id, reg);
1690 spin_unlock_irqrestore(&lp->lock, flags);
d5498bef 1691 data[j++] = reg & 0xFFFF;
0a0c72c9
DM		 1692 }
1693}
1694
1695static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
1696{
1697 unsigned long ioaddr = dev->base_addr;
1698 unsigned int timeout;
1699 int e2p_cmd;
1700
1701 e2p_cmd = SMC_GET_E2P_CMD();
1702 for(timeout=10;(e2p_cmd & E2P_CMD_EPC_BUSY_) && timeout; timeout--) {
1703 if (e2p_cmd & E2P_CMD_EPC_TIMEOUT_) {
d5498bef 1704 PRINTK("%s: %s timeout waiting for EEPROM to respond\n",
0a0c72c9
DM		 1705 dev->name, __FUNCTION__);
1706 return -EFAULT;
d5498bef 1707 }
0a0c72c9
DM		 1708 mdelay(1);
1709 e2p_cmd = SMC_GET_E2P_CMD();
1710 }
1711 if (timeout == 0) {
d5498bef 1712 PRINTK("%s: %s timeout waiting for EEPROM CMD not busy\n",
0a0c72c9
DM		 1713 dev->name, __FUNCTION__);
1714 return -ETIMEDOUT;
1715 }
1716 return 0;
1717}
1718
d5498bef 1719static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev,
0a0c72c9
DM		 1720 int cmd, int addr)
1721{
1722 unsigned long ioaddr = dev->base_addr;
1723 int ret;
1724
d5498bef 1725 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
0a0c72c9 1726 return ret;
d5498bef
JG		 1727 SMC_SET_E2P_CMD(E2P_CMD_EPC_BUSY_ |
1728 ((cmd) & (0x7<<28)) |
0a0c72c9
DM		 1729 ((addr) & 0xFF));
1730 return 0;
1731}
1732
d5498bef 1733static inline int smc911x_ethtool_read_eeprom_byte(struct net_device *dev,
0a0c72c9
DM		 1734 u8 *data)
1735{
1736 unsigned long ioaddr = dev->base_addr;
1737 int ret;
1738
d5498bef 1739 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
0a0c72c9
DM		 1740 return ret;
1741 *data = SMC_GET_E2P_DATA();
1742 return 0;
1743}
1744
d5498bef 1745static inline int smc911x_ethtool_write_eeprom_byte(struct net_device *dev,
0a0c72c9
DM		 1746 u8 data)
1747{
1748 unsigned long ioaddr = dev->base_addr;
1749 int ret;
1750
d5498bef 1751 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
0a0c72c9
DM		 1752 return ret;
1753 SMC_SET_E2P_DATA(data);
1754 return 0;
1755}
1756
d5498bef 1757static int smc911x_ethtool_geteeprom(struct net_device *dev,
0a0c72c9
DM		 1758 struct ethtool_eeprom *eeprom, u8 *data)
1759{
1760 u8 eebuf[SMC911X_EEPROM_LEN];
1761 int i, ret;
1762
1763 for(i=0;i<SMC911X_EEPROM_LEN;i++) {
1764 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_READ_, i ))!=0)
1765 return ret;
1766 if ((ret=smc911x_ethtool_read_eeprom_byte(dev, &eebuf[i]))!=0)
1767 return ret;
1768 }
1769 memcpy(data, eebuf+eeprom->offset, eeprom->len);
d5498bef 1770 return 0;
0a0c72c9
DM		 1771}
1772
d5498bef 1773static int smc911x_ethtool_seteeprom(struct net_device *dev,
0a0c72c9
DM		 1774 struct ethtool_eeprom *eeprom, u8 *data)
1775{
1776 int i, ret;
1777
1778 /* Enable erase */
1779 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWEN_, 0 ))!=0)
1780 return ret;
1781 for(i=eeprom->offset;i<(eeprom->offset+eeprom->len);i++) {
1782 /* erase byte */
1783 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_ERASE_, i ))!=0)
1784 return ret;
1785 /* write byte */
1786 if ((ret=smc911x_ethtool_write_eeprom_byte(dev, *data))!=0)
1787 return ret;
1788 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_WRITE_, i ))!=0)
1789 return ret;
1790 }
1791 return 0;
1792}
1793
1794static int smc911x_ethtool_geteeprom_len(struct net_device *dev)
1795{
1796 return SMC911X_EEPROM_LEN;
1797}
1798
7282d491 1799static const struct ethtool_ops smc911x_ethtool_ops = {
0a0c72c9
DM		 1800 .get_settings = smc911x_ethtool_getsettings,
1801 .set_settings = smc911x_ethtool_setsettings,
1802 .get_drvinfo = smc911x_ethtool_getdrvinfo,
1803 .get_msglevel = smc911x_ethtool_getmsglevel,
1804 .set_msglevel = smc911x_ethtool_setmsglevel,
1805 .nway_reset = smc911x_ethtool_nwayreset,
1806 .get_link = ethtool_op_get_link,
1807 .get_regs_len = smc911x_ethtool_getregslen,
1808 .get_regs = smc911x_ethtool_getregs,
1809 .get_eeprom_len = smc911x_ethtool_geteeprom_len,
1810 .get_eeprom = smc911x_ethtool_geteeprom,
1811 .set_eeprom = smc911x_ethtool_seteeprom,
1812};
1813
1814/*
1815 * smc911x_findirq
1816 *
1817 * This routine has a simple purpose -- make the SMC chip generate an
1818 * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1819 */
1820static int __init smc911x_findirq(unsigned long ioaddr)
1821{
1822 int timeout = 20;
1823 unsigned long cookie;
1824
1825 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
1826
1827 cookie = probe_irq_on();
1828
1829 /*
1830 * Force a SW interrupt
1831 */
1832
1833 SMC_SET_INT_EN(INT_EN_SW_INT_EN_);
1834
1835 /*
1836 * Wait until positive that the interrupt has been generated
1837 */
1838 do {
1839 int int_status;
1840 udelay(10);
1841 int_status = SMC_GET_INT_EN();
1842 if (int_status & INT_EN_SW_INT_EN_)
1843 break; /* got the interrupt */
1844 } while (--timeout);
1845
1846 /*
1847 * there is really nothing that I can do here if timeout fails,
1848 * as autoirq_report will return a 0 anyway, which is what I
1849 * want in this case. Plus, the clean up is needed in both
1850 * cases.
1851 */
1852
1853 /* and disable all interrupts again */
1854 SMC_SET_INT_EN(0);
1855
1856 /* and return what I found */
1857 return probe_irq_off(cookie);
1858}
1859
1860/*
1861 * Function: smc911x_probe(unsigned long ioaddr)
1862 *
1863 * Purpose:
1864 * Tests to see if a given ioaddr points to an SMC911x chip.
1865 * Returns a 0 on success
1866 *
1867 * Algorithm:
1868 * (1) see if the endian word is OK
1869 * (1) see if I recognize the chip ID in the appropriate register
1870 *
1871 * Here I do typical initialization tasks.
1872 *
1873 * o Initialize the structure if needed
1874 * o print out my vanity message if not done so already
1875 * o print out what type of hardware is detected
1876 * o print out the ethernet address
1877 * o find the IRQ
1878 * o set up my private data
1879 * o configure the dev structure with my subroutines
1880 * o actually GRAB the irq.
1881 * o GRAB the region
1882 */
1883static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
1884{
1885 struct smc911x_local *lp = netdev_priv(dev);
1886 int i, retval;
1887 unsigned int val, chip_id, revision;
1888 const char *version_string;
1889
1890 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1891
1892 /* First, see if the endian word is recognized */
1893 val = SMC_GET_BYTE_TEST();
1894 DBG(SMC_DEBUG_MISC, "%s: endian probe returned 0x%04x\n", CARDNAME, val);
1895 if (val != 0x87654321) {
1896 printk(KERN_ERR "Invalid chip endian 0x08%x\n",val);
1897 retval = -ENODEV;
1898 goto err_out;
1899 }
1900
1901 /*
1902 * check if the revision register is something that I
1903 * recognize. These might need to be added to later,
1904 * as future revisions could be added.
1905 */
1906 chip_id = SMC_GET_PN();
1907 DBG(SMC_DEBUG_MISC, "%s: id probe returned 0x%04x\n", CARDNAME, chip_id);
1908 for(i=0;chip_ids[i].id != 0; i++) {
1909 if (chip_ids[i].id == chip_id) break;
1910 }
1911 if (!chip_ids[i].id) {
1912 printk(KERN_ERR "Unknown chip ID %04x\n", chip_id);
1913 retval = -ENODEV;
1914 goto err_out;
1915 }
1916 version_string = chip_ids[i].name;
1917
1918 revision = SMC_GET_REV();
1919 DBG(SMC_DEBUG_MISC, "%s: revision = 0x%04x\n", CARDNAME, revision);
1920
1921 /* At this point I'll assume that the chip is an SMC911x. */
1922 DBG(SMC_DEBUG_MISC, "%s: Found a %s\n", CARDNAME, chip_ids[i].name);
1923
1924 /* Validate the TX FIFO size requested */
1925 if ((tx_fifo_kb < 2) || (tx_fifo_kb > 14)) {
1926 printk(KERN_ERR "Invalid TX FIFO size requested %d\n", tx_fifo_kb);
1927 retval = -EINVAL;
1928 goto err_out;
1929 }
d5498bef 1930
0a0c72c9
DM		 1931 /* fill in some of the fields */
1932 dev->base_addr = ioaddr;
1933 lp->version = chip_ids[i].id;
1934 lp->revision = revision;
1935 lp->tx_fifo_kb = tx_fifo_kb;
1936 /* Reverse calculate the RX FIFO size from the TX */
1937 lp->tx_fifo_size=(lp->tx_fifo_kb<<10) - 512;
1938 lp->rx_fifo_size= ((0x4000 - 512 - lp->tx_fifo_size) / 16) * 15;
1939
1940 /* Set the automatic flow control values */
1941 switch(lp->tx_fifo_kb) {
d5498bef 1942 /*
0a0c72c9
DM		 1943 * AFC_HI is about ((Rx Data Fifo Size)*2/3)/64
1944 * AFC_LO is AFC_HI/2
1945 * BACK_DUR is about 5uS*(AFC_LO) rounded down
1946 */
1947 case 2:/* 13440 Rx Data Fifo Size */
1948 lp->afc_cfg=0x008C46AF;break;
1949 case 3:/* 12480 Rx Data Fifo Size */
1950 lp->afc_cfg=0x0082419F;break;
1951 case 4:/* 11520 Rx Data Fifo Size */
1952 lp->afc_cfg=0x00783C9F;break;
1953 case 5:/* 10560 Rx Data Fifo Size */
1954 lp->afc_cfg=0x006E374F;break;
1955 case 6:/* 9600 Rx Data Fifo Size */
1956 lp->afc_cfg=0x0064328F;break;
1957 case 7:/* 8640 Rx Data Fifo Size */
1958 lp->afc_cfg=0x005A2D7F;break;
1959 case 8:/* 7680 Rx Data Fifo Size */
1960 lp->afc_cfg=0x0050287F;break;
1961 case 9:/* 6720 Rx Data Fifo Size */
1962 lp->afc_cfg=0x0046236F;break;
1963 case 10:/* 5760 Rx Data Fifo Size */
1964 lp->afc_cfg=0x003C1E6F;break;
1965 case 11:/* 4800 Rx Data Fifo Size */
1966 lp->afc_cfg=0x0032195F;break;
d5498bef 1967 /*
0a0c72c9
DM		 1968 * AFC_HI is ~1520 bytes less than RX Data Fifo Size
1969 * AFC_LO is AFC_HI/2
1970 * BACK_DUR is about 5uS*(AFC_LO) rounded down
1971 */
1972 case 12:/* 3840 Rx Data Fifo Size */
1973 lp->afc_cfg=0x0024124F;break;
1974 case 13:/* 2880 Rx Data Fifo Size */
1975 lp->afc_cfg=0x0015073F;break;
1976 case 14:/* 1920 Rx Data Fifo Size */
1977 lp->afc_cfg=0x0006032F;break;
1978 default:
d5498bef 1979 PRINTK("%s: ERROR -- no AFC_CFG setting found",
0a0c72c9
DM		 1980 dev->name);
1981 break;
1982 }
1983
d5498bef
JG		 1984 DBG(SMC_DEBUG_MISC | SMC_DEBUG_TX | SMC_DEBUG_RX,
1985 "%s: tx_fifo %d rx_fifo %d afc_cfg 0x%08x\n", CARDNAME,
0a0c72c9
DM		 1986 lp->tx_fifo_size, lp->rx_fifo_size, lp->afc_cfg);
1987
1988 spin_lock_init(&lp->lock);
1989
1990 /* Get the MAC address */
1991 SMC_GET_MAC_ADDR(dev->dev_addr);
1992
1993 /* now, reset the chip, and put it into a known state */
1994 smc911x_reset(dev);
1995
1996 /*
1997 * If dev->irq is 0, then the device has to be banged on to see
1998 * what the IRQ is.
1999 *
2000 * Specifying an IRQ is done with the assumption that the user knows
2001 * what (s)he is doing. No checking is done!!!!
2002 */
2003 if (dev->irq < 1) {
2004 int trials;
2005
2006 trials = 3;
2007 while (trials--) {
2008 dev->irq = smc911x_findirq(ioaddr);
2009 if (dev->irq)
2010 break;
2011 /* kick the card and try again */
2012 smc911x_reset(dev);
2013 }
2014 }
2015 if (dev->irq == 0) {
2016 printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n",
2017 dev->name);
2018 retval = -ENODEV;
2019 goto err_out;
2020 }
2021 dev->irq = irq_canonicalize(dev->irq);
2022
2023 /* Fill in the fields of the device structure with ethernet values. */
2024 ether_setup(dev);
2025
2026 dev->open = smc911x_open;
2027 dev->stop = smc911x_close;
2028 dev->hard_start_xmit = smc911x_hard_start_xmit;
2029 dev->tx_timeout = smc911x_timeout;
2030 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
0a0c72c9
DM		 2031 dev->set_multicast_list = smc911x_set_multicast_list;
2032 dev->ethtool_ops = &smc911x_ethtool_ops;
2033#ifdef CONFIG_NET_POLL_CONTROLLER
2034 dev->poll_controller = smc911x_poll_controller;
2035#endif
2036
ef8142a5 2037 INIT_WORK(&lp->phy_configure, smc911x_phy_configure);
0a0c72c9
DM		 2038 lp->mii.phy_id_mask = 0x1f;
2039 lp->mii.reg_num_mask = 0x1f;
2040 lp->mii.force_media = 0;
2041 lp->mii.full_duplex = 0;
2042 lp->mii.dev = dev;
2043 lp->mii.mdio_read = smc911x_phy_read;
2044 lp->mii.mdio_write = smc911x_phy_write;
2045
2046 /*
2047 * Locate the phy, if any.
2048 */
2049 smc911x_phy_detect(dev);
2050
2051 /* Set default parameters */
2052 lp->msg_enable = NETIF_MSG_LINK;
2053 lp->ctl_rfduplx = 1;
2054 lp->ctl_rspeed = 100;
2055
2056 /* Grab the IRQ */
f2773a29 2057 retval = request_irq(dev->irq, &smc911x_interrupt,
726d722e 2058 IRQF_SHARED | SMC_IRQ_SENSE, dev->name, dev);
0a0c72c9
DM		 2059 if (retval)
2060 goto err_out;
2061
0a0c72c9
DM		 2062#ifdef SMC_USE_DMA
2063 lp->rxdma = SMC_DMA_REQUEST(dev, smc911x_rx_dma_irq);
2064 lp->txdma = SMC_DMA_REQUEST(dev, smc911x_tx_dma_irq);
2065 lp->rxdma_active = 0;
2066 lp->txdma_active = 0;
2067 dev->dma = lp->rxdma;
2068#endif
2069
2070 retval = register_netdev(dev);
2071 if (retval == 0) {
2072 /* now, print out the card info, in a short format.. */
2073 printk("%s: %s (rev %d) at %#lx IRQ %d",
2074 dev->name, version_string, lp->revision,
2075 dev->base_addr, dev->irq);
2076
2077#ifdef SMC_USE_DMA
2078 if (lp->rxdma != -1)
2079 printk(" RXDMA %d ", lp->rxdma);
2080
2081 if (lp->txdma != -1)
2082 printk("TXDMA %d", lp->txdma);
2083#endif
2084 printk("\n");
2085 if (!is_valid_ether_addr(dev->dev_addr)) {
2086 printk("%s: Invalid ethernet MAC address. Please "
2087 "set using ifconfig\n", dev->name);
2088 } else {
2089 /* Print the Ethernet address */
2090 printk("%s: Ethernet addr: ", dev->name);
2091 for (i = 0; i < 5; i++)
2092 printk("%2.2x:", dev->dev_addr[i]);
2093 printk("%2.2x\n", dev->dev_addr[5]);
2094 }
2095
2096 if (lp->phy_type == 0) {
2097 PRINTK("%s: No PHY found\n", dev->name);
2098 } else if ((lp->phy_type & ~0xff) == LAN911X_INTERNAL_PHY_ID) {
2099 PRINTK("%s: LAN911x Internal PHY\n", dev->name);
2100 } else {
2101 PRINTK("%s: External PHY 0x%08x\n", dev->name, lp->phy_type);
2102 }
2103 }
d5498bef 2104
0a0c72c9
DM		 2105err_out:
2106#ifdef SMC_USE_DMA
2107 if (retval) {
2108 if (lp->rxdma != -1) {
2109 SMC_DMA_FREE(dev, lp->rxdma);
2110 }
2111 if (lp->txdma != -1) {
2112 SMC_DMA_FREE(dev, lp->txdma);
2113 }
2114 }
2115#endif
2116 return retval;
2117}
2118
2119/*
2120 * smc911x_init(void)
2121 *
2122 * Output:
2123 * 0 --> there is a device
2124 * anything else, error
2125 */
2126static int smc911x_drv_probe(struct platform_device *pdev)
2127{
2128 struct net_device *ndev;
2129 struct resource *res;
ef8142a5 2130 struct smc911x_local *lp;
0a0c72c9
DM		 2131 unsigned int *addr;
2132 int ret;
2133
2134 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
2135 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2136 if (!res) {
2137 ret = -ENODEV;
2138 goto out;
2139 }
2140
2141 /*
2142 * Request the regions.
2143 */
2144 if (!request_mem_region(res->start, SMC911X_IO_EXTENT, CARDNAME)) {
2145 ret = -EBUSY;
2146 goto out;
2147 }
2148
2149 ndev = alloc_etherdev(sizeof(struct smc911x_local));
2150 if (!ndev) {
2151 printk("%s: could not allocate device.\n", CARDNAME);
2152 ret = -ENOMEM;
2153 goto release_1;
2154 }
0a0c72c9
DM		 2155 SET_NETDEV_DEV(ndev, &pdev->dev);
2156
2157 ndev->dma = (unsigned char)-1;
2158 ndev->irq = platform_get_irq(pdev, 0);
ef8142a5
AM		 2159 lp = netdev_priv(ndev);
2160 lp->netdev = ndev;
0a0c72c9
DM		 2161
2162 addr = ioremap(res->start, SMC911X_IO_EXTENT);
2163 if (!addr) {
2164 ret = -ENOMEM;
2165 goto release_both;
2166 }
2167
2168 platform_set_drvdata(pdev, ndev);
2169 ret = smc911x_probe(ndev, (unsigned long)addr);
2170 if (ret != 0) {
2171 platform_set_drvdata(pdev, NULL);
2172 iounmap(addr);
2173release_both:
2174 free_netdev(ndev);
2175release_1:
2176 release_mem_region(res->start, SMC911X_IO_EXTENT);
2177out:
2178 printk("%s: not found (%d).\n", CARDNAME, ret);
2179 }
2180#ifdef SMC_USE_DMA
2181 else {
0a0c72c9
DM		 2182 lp->physaddr = res->start;
2183 lp->dev = &pdev->dev;
2184 }
2185#endif
2186
2187 return ret;
2188}
2189
2190static int smc911x_drv_remove(struct platform_device *pdev)
2191{
2192 struct net_device *ndev = platform_get_drvdata(pdev);
2193 struct resource *res;
2194
2195 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
2196 platform_set_drvdata(pdev, NULL);
2197
2198 unregister_netdev(ndev);
2199
2200 free_irq(ndev->irq, ndev);
2201
2202#ifdef SMC_USE_DMA
2203 {
2204 struct smc911x_local *lp = netdev_priv(ndev);
2205 if (lp->rxdma != -1) {
2206 SMC_DMA_FREE(dev, lp->rxdma);
2207 }
2208 if (lp->txdma != -1) {
2209 SMC_DMA_FREE(dev, lp->txdma);
2210 }
2211 }
2212#endif
2213 iounmap((void *)ndev->base_addr);
2214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2215 release_mem_region(res->start, SMC911X_IO_EXTENT);
2216
2217 free_netdev(ndev);
2218 return 0;
2219}
2220
2221static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state)
2222{
2223 struct net_device *ndev = platform_get_drvdata(dev);
2224 unsigned long ioaddr = ndev->base_addr;
2225
2226 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
2227 if (ndev) {
2228 if (netif_running(ndev)) {
2229 netif_device_detach(ndev);
2230 smc911x_shutdown(ndev);
2231#if POWER_DOWN
2232 /* Set D2 - Energy detect only setting */
2233 SMC_SET_PMT_CTRL(2<<12);
2234#endif
2235 }
2236 }
2237 return 0;
2238}
2239
2240static int smc911x_drv_resume(struct platform_device *dev)
2241{
2242 struct net_device *ndev = platform_get_drvdata(dev);
2243
2244 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
2245 if (ndev) {
2246 struct smc911x_local *lp = netdev_priv(ndev);
2247
2248 if (netif_running(ndev)) {
2249 smc911x_reset(ndev);
2250 smc911x_enable(ndev);
2251 if (lp->phy_type != 0)
ef8142a5 2252 smc911x_phy_configure(&lp->phy_configure);
0a0c72c9
DM		 2253 netif_device_attach(ndev);
2254 }
2255 }
2256 return 0;
2257}
2258
2259static struct platform_driver smc911x_driver = {
2260 .probe = smc911x_drv_probe,
2261 .remove = smc911x_drv_remove,
2262 .suspend = smc911x_drv_suspend,
2263 .resume = smc911x_drv_resume,
2264 .driver = {
2265 .name = CARDNAME,
72abb461 2266 .owner = THIS_MODULE,
0a0c72c9
DM		 2267 },
2268};
d5498bef 2269
0a0c72c9
DM		 2270static int __init smc911x_init(void)
2271{
2272 return platform_driver_register(&smc911x_driver);
2273}
2274
2275static void __exit smc911x_cleanup(void)
2276{
2277 platform_driver_unregister(&smc911x_driver);
2278}
2279
2280module_init(smc911x_init);
2281module_exit(smc911x_cleanup);
Linux 6.x block layer and io_uring tree(s)