Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
798b6b19 | 13 | * the Free Software Foundation; either version 2 of the License. |
cd28ab6a SH |
14 | * |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
18 | * GNU General Public License for more details. |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
ada1db5c JP |
25 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
26 | ||
793b883e | 27 | #include <linux/crc32.h> |
cd28ab6a | 28 | #include <linux/kernel.h> |
cd28ab6a SH |
29 | #include <linux/module.h> |
30 | #include <linux/netdevice.h> | |
d0bbccfa | 31 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
32 | #include <linux/etherdevice.h> |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/ip.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c9bdd4b5 | 37 | #include <net/ip.h> |
cd28ab6a SH |
38 | #include <linux/tcp.h> |
39 | #include <linux/in.h> | |
40 | #include <linux/delay.h> | |
91c86df5 | 41 | #include <linux/workqueue.h> |
d1f13708 | 42 | #include <linux/if_vlan.h> |
d70cd51a | 43 | #include <linux/prefetch.h> |
3cf26753 | 44 | #include <linux/debugfs.h> |
ef743d33 | 45 | #include <linux/mii.h> |
cd28ab6a SH |
46 | |
47 | #include <asm/irq.h> | |
48 | ||
49 | #include "sky2.h" | |
50 | ||
51 | #define DRV_NAME "sky2" | |
e0a67e2d | 52 | #define DRV_VERSION "1.28" |
cd28ab6a SH |
53 | |
54 | /* | |
55 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
56 | * that are organized into three (receive, transmit, status) different rings | |
14d0263f | 57 | * similar to Tigon3. |
cd28ab6a SH |
58 | */ |
59 | ||
14d0263f | 60 | #define RX_LE_SIZE 1024 |
cd28ab6a | 61 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
14d0263f | 62 | #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) |
13210ce5 | 63 | #define RX_DEF_PENDING RX_MAX_PENDING |
793b883e | 64 | |
ee5f68fe | 65 | /* This is the worst case number of transmit list elements for a single skb: |
07e31637 SH |
66 | VLAN:GSO + CKSUM + Data + skb_frags * DMA */ |
67 | #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) | |
e9c1be80 | 68 | #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) |
efe91932 | 69 | #define TX_MAX_PENDING 1024 |
ee5f68fe | 70 | #define TX_DEF_PENDING 127 |
cd28ab6a | 71 | |
cd28ab6a SH |
72 | #define TX_WATCHDOG (5 * HZ) |
73 | #define NAPI_WEIGHT 64 | |
74 | #define PHY_RETRIES 1000 | |
75 | ||
f4331a6d SH |
76 | #define SKY2_EEPROM_MAGIC 0x9955aabb |
77 | ||
060b946c | 78 | #define RING_NEXT(x, s) (((x)+1) & ((s)-1)) |
cb5d9547 | 79 | |
cd28ab6a | 80 | static const u32 default_msg = |
793b883e SH |
81 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
82 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
3be92a70 | 83 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; |
cd28ab6a | 84 | |
793b883e | 85 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
86 | module_param(debug, int, 0); |
87 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
88 | ||
14d0263f | 89 | static int copybreak __read_mostly = 128; |
bdb5c58e SH |
90 | module_param(copybreak, int, 0); |
91 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
92 | ||
fb2690a9 SH |
93 | static int disable_msi = 0; |
94 | module_param(disable_msi, int, 0); | |
95 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
96 | ||
e6cac9ba | 97 | static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = { |
e5b74c7d SH |
98 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ |
99 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ | |
e30a4ac2 | 100 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */ |
2d2a3871 | 101 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ |
2f4a66ad | 102 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ |
508f89e7 | 103 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ |
f1a0b6f5 | 104 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ |
e5b74c7d SH |
105 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ |
106 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ | |
107 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ | |
108 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ | |
109 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ | |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ | |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ | |
05745c4a | 117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ |
a3b4fced | 118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ |
e5b74c7d | 119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ |
5a37a68d | 120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ |
05745c4a | 121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ |
e5b74c7d SH |
122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ |
123 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ | |
124 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ | |
125 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ | |
126 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ | |
05745c4a | 127 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ |
e5b74c7d SH |
128 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ |
129 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ | |
130 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ | |
f1a0b6f5 SH |
131 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ |
132 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ | |
69161611 | 133 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ |
5a37a68d | 134 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ |
ed4d4161 SH |
135 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ |
136 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ | |
0ce8b98d | 137 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ |
0f5aac70 | 138 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ |
cd28ab6a SH |
139 | { 0 } |
140 | }; | |
793b883e | 141 | |
cd28ab6a SH |
142 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
143 | ||
144 | /* Avoid conditionals by using array */ | |
145 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
146 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
f4ea431b | 147 | static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; |
cd28ab6a | 148 | |
d1b139c0 SH |
149 | static void sky2_set_multicast(struct net_device *dev); |
150 | ||
af043aa5 | 151 | /* Access to PHY via serial interconnect */ |
ef743d33 | 152 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
153 | { |
154 | int i; | |
155 | ||
156 | gma_write16(hw, port, GM_SMI_DATA, val); | |
157 | gma_write16(hw, port, GM_SMI_CTRL, | |
158 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
159 | ||
160 | for (i = 0; i < PHY_RETRIES; i++) { | |
af043aa5 SH |
161 | u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); |
162 | if (ctrl == 0xffff) | |
163 | goto io_error; | |
164 | ||
165 | if (!(ctrl & GM_SMI_CT_BUSY)) | |
ef743d33 | 166 | return 0; |
af043aa5 SH |
167 | |
168 | udelay(10); | |
cd28ab6a | 169 | } |
ef743d33 | 170 | |
060b946c | 171 | dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 172 | return -ETIMEDOUT; |
af043aa5 SH |
173 | |
174 | io_error: | |
175 | dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); | |
176 | return -EIO; | |
cd28ab6a SH |
177 | } |
178 | ||
ef743d33 | 179 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
180 | { |
181 | int i; | |
182 | ||
793b883e | 183 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
184 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
185 | ||
186 | for (i = 0; i < PHY_RETRIES; i++) { | |
af043aa5 SH |
187 | u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); |
188 | if (ctrl == 0xffff) | |
189 | goto io_error; | |
190 | ||
191 | if (ctrl & GM_SMI_CT_RD_VAL) { | |
ef743d33 | 192 | *val = gma_read16(hw, port, GM_SMI_DATA); |
193 | return 0; | |
194 | } | |
195 | ||
af043aa5 | 196 | udelay(10); |
cd28ab6a SH |
197 | } |
198 | ||
af043aa5 | 199 | dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); |
ef743d33 | 200 | return -ETIMEDOUT; |
af043aa5 SH |
201 | io_error: |
202 | dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); | |
203 | return -EIO; | |
ef743d33 | 204 | } |
205 | ||
af043aa5 | 206 | static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) |
ef743d33 | 207 | { |
208 | u16 v; | |
af043aa5 | 209 | __gm_phy_read(hw, port, reg, &v); |
ef743d33 | 210 | return v; |
cd28ab6a SH |
211 | } |
212 | ||
5afa0a9c | 213 | |
ae306cca SH |
214 | static void sky2_power_on(struct sky2_hw *hw) |
215 | { | |
216 | /* switch power to VCC (WA for VAUX problem) */ | |
217 | sky2_write8(hw, B0_POWER_CTRL, | |
218 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
5afa0a9c | 219 | |
ae306cca SH |
220 | /* disable Core Clock Division, */ |
221 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
d3bcfbeb | 222 | |
4b7c47aa | 223 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) |
ae306cca SH |
224 | /* enable bits are inverted */ |
225 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
226 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
227 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
228 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
229 | else | |
230 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
977bdf06 | 231 | |
ea76e635 | 232 | if (hw->flags & SKY2_HW_ADV_POWER_CTL) { |
fc99fe06 | 233 | u32 reg; |
5afa0a9c | 234 | |
b32f40c4 | 235 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
b2345773 | 236 | |
b32f40c4 | 237 | reg = sky2_pci_read32(hw, PCI_DEV_REG4); |
fc99fe06 SH |
238 | /* set all bits to 0 except bits 15..12 and 8 */ |
239 | reg &= P_ASPM_CONTROL_MSK; | |
b32f40c4 | 240 | sky2_pci_write32(hw, PCI_DEV_REG4, reg); |
fc99fe06 | 241 | |
b32f40c4 | 242 | reg = sky2_pci_read32(hw, PCI_DEV_REG5); |
fc99fe06 SH |
243 | /* set all bits to 0 except bits 28 & 27 */ |
244 | reg &= P_CTL_TIM_VMAIN_AV_MSK; | |
b32f40c4 | 245 | sky2_pci_write32(hw, PCI_DEV_REG5, reg); |
fc99fe06 | 246 | |
b32f40c4 | 247 | sky2_pci_write32(hw, PCI_CFG_REG_1, 0); |
8f70920f | 248 | |
5f8ae5c5 | 249 | sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); |
250 | ||
8f70920f SH |
251 | /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ |
252 | reg = sky2_read32(hw, B2_GP_IO); | |
253 | reg |= GLB_GPIO_STAT_RACE_DIS; | |
254 | sky2_write32(hw, B2_GP_IO, reg); | |
b2345773 SH |
255 | |
256 | sky2_read32(hw, B2_GP_IO); | |
5afa0a9c | 257 | } |
10547ae2 SH |
258 | |
259 | /* Turn on "driver loaded" LED */ | |
260 | sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); | |
ae306cca | 261 | } |
5afa0a9c | 262 | |
ae306cca SH |
263 | static void sky2_power_aux(struct sky2_hw *hw) |
264 | { | |
4b7c47aa | 265 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) |
ae306cca SH |
266 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); |
267 | else | |
268 | /* enable bits are inverted */ | |
269 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
270 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
271 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
272 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
273 | ||
c23ddf8f SH |
274 | /* switch power to VAUX if supported and PME from D3cold */ |
275 | if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && | |
276 | pci_pme_capable(hw->pdev, PCI_D3cold)) | |
ae306cca SH |
277 | sky2_write8(hw, B0_POWER_CTRL, |
278 | (PC_VAUX_ENA | PC_VCC_ENA | | |
279 | PC_VAUX_ON | PC_VCC_OFF)); | |
10547ae2 SH |
280 | |
281 | /* turn off "driver loaded LED" */ | |
282 | sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); | |
5afa0a9c | 283 | } |
284 | ||
d3bcfbeb | 285 | static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) |
cd28ab6a SH |
286 | { |
287 | u16 reg; | |
288 | ||
289 | /* disable all GMAC IRQ's */ | |
290 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
793b883e | 291 | |
cd28ab6a SH |
292 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
293 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
294 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
295 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
296 | ||
297 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
298 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
299 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
300 | } | |
301 | ||
16ad91e1 SH |
302 | /* flow control to advertise bits */ |
303 | static const u16 copper_fc_adv[] = { | |
304 | [FC_NONE] = 0, | |
305 | [FC_TX] = PHY_M_AN_ASP, | |
306 | [FC_RX] = PHY_M_AN_PC, | |
307 | [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, | |
308 | }; | |
309 | ||
310 | /* flow control to advertise bits when using 1000BaseX */ | |
311 | static const u16 fiber_fc_adv[] = { | |
df3fe1f3 | 312 | [FC_NONE] = PHY_M_P_NO_PAUSE_X, |
16ad91e1 SH |
313 | [FC_TX] = PHY_M_P_ASYM_MD_X, |
314 | [FC_RX] = PHY_M_P_SYM_MD_X, | |
df3fe1f3 | 315 | [FC_BOTH] = PHY_M_P_BOTH_MD_X, |
16ad91e1 SH |
316 | }; |
317 | ||
318 | /* flow control to GMA disable bits */ | |
319 | static const u16 gm_fc_disable[] = { | |
320 | [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, | |
321 | [FC_TX] = GM_GPCR_FC_RX_DIS, | |
322 | [FC_RX] = GM_GPCR_FC_TX_DIS, | |
323 | [FC_BOTH] = 0, | |
324 | }; | |
325 | ||
326 | ||
cd28ab6a SH |
327 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) |
328 | { | |
329 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
2eaba1a2 | 330 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; |
cd28ab6a | 331 | |
0ea065e5 | 332 | if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && |
ea76e635 | 333 | !(hw->flags & SKY2_HW_NEWER_PHY)) { |
cd28ab6a SH |
334 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
335 | ||
336 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 337 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
338 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
339 | ||
53419c68 | 340 | /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ |
cd28ab6a | 341 | if (hw->chip_id == CHIP_ID_YUKON_EC) |
53419c68 | 342 | /* set downshift counter to 3x and enable downshift */ |
cd28ab6a SH |
343 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; |
344 | else | |
53419c68 SH |
345 | /* set master & slave downshift counter to 1x */ |
346 | ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); | |
cd28ab6a SH |
347 | |
348 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
349 | } | |
350 | ||
351 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
b89165f2 | 352 | if (sky2_is_copper(hw)) { |
05745c4a | 353 | if (!(hw->flags & SKY2_HW_GIGABIT)) { |
cd28ab6a SH |
354 | /* enable automatic crossover */ |
355 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
6d3105d5 SH |
356 | |
357 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && | |
358 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | |
359 | u16 spec; | |
360 | ||
361 | /* Enable Class A driver for FE+ A0 */ | |
362 | spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); | |
363 | spec |= PHY_M_FESC_SEL_CL_A; | |
364 | gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); | |
365 | } | |
cd28ab6a SH |
366 | } else { |
367 | /* disable energy detect */ | |
368 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
369 | ||
370 | /* enable automatic crossover */ | |
371 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
372 | ||
53419c68 | 373 | /* downshift on PHY 88E1112 and 88E1149 is changed */ |
8e95a202 JP |
374 | if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && |
375 | (hw->flags & SKY2_HW_NEWER_PHY)) { | |
53419c68 | 376 | /* set downshift counter to 3x and enable downshift */ |
cd28ab6a SH |
377 | ctrl &= ~PHY_M_PC_DSC_MSK; |
378 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
379 | } | |
380 | } | |
cd28ab6a SH |
381 | } else { |
382 | /* workaround for deviation #4.88 (CRC errors) */ | |
383 | /* disable Automatic Crossover */ | |
384 | ||
385 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
b89165f2 | 386 | } |
cd28ab6a | 387 | |
b89165f2 SH |
388 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
389 | ||
390 | /* special setup for PHY 88E1112 Fiber */ | |
ea76e635 | 391 | if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { |
b89165f2 | 392 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a | 393 | |
b89165f2 SH |
394 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ |
395 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
396 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
397 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
398 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
399 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
400 | ||
401 | if (hw->pmd_type == 'P') { | |
cd28ab6a SH |
402 | /* select page 1 to access Fiber registers */ |
403 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
b89165f2 SH |
404 | |
405 | /* for SFP-module set SIGDET polarity to low */ | |
406 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
407 | ctrl |= PHY_M_FIB_SIGD_POL; | |
34dd962b | 408 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
cd28ab6a | 409 | } |
b89165f2 SH |
410 | |
411 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
cd28ab6a SH |
412 | } |
413 | ||
7800fddc | 414 | ctrl = PHY_CT_RESET; |
cd28ab6a SH |
415 | ct1000 = 0; |
416 | adv = PHY_AN_CSMA; | |
2eaba1a2 | 417 | reg = 0; |
cd28ab6a | 418 | |
0ea065e5 | 419 | if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { |
b89165f2 | 420 | if (sky2_is_copper(hw)) { |
cd28ab6a SH |
421 | if (sky2->advertising & ADVERTISED_1000baseT_Full) |
422 | ct1000 |= PHY_M_1000C_AFD; | |
423 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
424 | ct1000 |= PHY_M_1000C_AHD; | |
425 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
426 | adv |= PHY_M_AN_100_FD; | |
427 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
428 | adv |= PHY_M_AN_100_HD; | |
429 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
430 | adv |= PHY_M_AN_10_FD; | |
431 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
432 | adv |= PHY_M_AN_10_HD; | |
709c6e7b | 433 | |
b89165f2 SH |
434 | } else { /* special defines for FIBER (88E1040S only) */ |
435 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
436 | adv |= PHY_M_AN_1000X_AFD; | |
437 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
438 | adv |= PHY_M_AN_1000X_AHD; | |
709c6e7b | 439 | } |
cd28ab6a SH |
440 | |
441 | /* Restart Auto-negotiation */ | |
442 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
443 | } else { | |
444 | /* forced speed/duplex settings */ | |
445 | ct1000 = PHY_M_1000C_MSE; | |
446 | ||
0ea065e5 SH |
447 | /* Disable auto update for duplex flow control and duplex */ |
448 | reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; | |
cd28ab6a SH |
449 | |
450 | switch (sky2->speed) { | |
451 | case SPEED_1000: | |
452 | ctrl |= PHY_CT_SP1000; | |
2eaba1a2 | 453 | reg |= GM_GPCR_SPEED_1000; |
cd28ab6a SH |
454 | break; |
455 | case SPEED_100: | |
456 | ctrl |= PHY_CT_SP100; | |
2eaba1a2 | 457 | reg |= GM_GPCR_SPEED_100; |
cd28ab6a SH |
458 | break; |
459 | } | |
460 | ||
2eaba1a2 SH |
461 | if (sky2->duplex == DUPLEX_FULL) { |
462 | reg |= GM_GPCR_DUP_FULL; | |
463 | ctrl |= PHY_CT_DUP_MD; | |
16ad91e1 SH |
464 | } else if (sky2->speed < SPEED_1000) |
465 | sky2->flow_mode = FC_NONE; | |
0ea065e5 | 466 | } |
2eaba1a2 | 467 | |
0ea065e5 SH |
468 | if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { |
469 | if (sky2_is_copper(hw)) | |
470 | adv |= copper_fc_adv[sky2->flow_mode]; | |
471 | else | |
472 | adv |= fiber_fc_adv[sky2->flow_mode]; | |
473 | } else { | |
474 | reg |= GM_GPCR_AU_FCT_DIS; | |
16ad91e1 | 475 | reg |= gm_fc_disable[sky2->flow_mode]; |
2eaba1a2 SH |
476 | |
477 | /* Forward pause packets to GMAC? */ | |
16ad91e1 | 478 | if (sky2->flow_mode & FC_RX) |
2eaba1a2 SH |
479 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
480 | else | |
481 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
cd28ab6a SH |
482 | } |
483 | ||
2eaba1a2 SH |
484 | gma_write16(hw, port, GM_GP_CTRL, reg); |
485 | ||
05745c4a | 486 | if (hw->flags & SKY2_HW_GIGABIT) |
cd28ab6a SH |
487 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); |
488 | ||
489 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
490 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
491 | ||
492 | /* Setup Phy LED's */ | |
493 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
494 | ledover = 0; | |
495 | ||
496 | switch (hw->chip_id) { | |
497 | case CHIP_ID_YUKON_FE: | |
498 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
499 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
500 | ||
501 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
502 | ||
503 | /* delete ACT LED control bits */ | |
504 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
505 | /* change ACT LED control to blink mode */ | |
506 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
507 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
508 | break; | |
509 | ||
05745c4a SH |
510 | case CHIP_ID_YUKON_FE_P: |
511 | /* Enable Link Partner Next Page */ | |
512 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
513 | ctrl |= PHY_M_PC_ENA_LIP_NP; | |
514 | ||
515 | /* disable Energy Detect and enable scrambler */ | |
516 | ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); | |
517 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
518 | ||
519 | /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ | |
520 | ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | | |
521 | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | | |
522 | PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); | |
523 | ||
524 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
525 | break; | |
526 | ||
cd28ab6a | 527 | case CHIP_ID_YUKON_XL: |
793b883e | 528 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
529 | |
530 | /* select page 3 to access LED control register */ | |
531 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
532 | ||
533 | /* set LED Function Control register */ | |
ed6d32c7 SH |
534 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
535 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
536 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
537 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
538 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
539 | |
540 | /* set Polarity Control register */ | |
541 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
542 | (PHY_M_POLC_LS1_P_MIX(4) | |
543 | PHY_M_POLC_IS0_P_MIX(4) | | |
544 | PHY_M_POLC_LOS_CTRL(2) | | |
545 | PHY_M_POLC_INIT_CTRL(2) | | |
546 | PHY_M_POLC_STA1_CTRL(2) | | |
547 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
548 | |
549 | /* restore page register */ | |
793b883e | 550 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a | 551 | break; |
93745494 | 552 | |
ed6d32c7 | 553 | case CHIP_ID_YUKON_EC_U: |
93745494 | 554 | case CHIP_ID_YUKON_EX: |
ed4d4161 | 555 | case CHIP_ID_YUKON_SUPR: |
ed6d32c7 SH |
556 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
557 | ||
558 | /* select page 3 to access LED control register */ | |
559 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
560 | ||
561 | /* set LED Function Control register */ | |
562 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
563 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
564 | PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ | |
565 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
566 | PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ | |
567 | ||
568 | /* set Blink Rate in LED Timer Control Register */ | |
569 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, | |
570 | ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); | |
571 | /* restore page register */ | |
572 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
573 | break; | |
cd28ab6a SH |
574 | |
575 | default: | |
576 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
577 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
a84d0a3d | 578 | |
cd28ab6a | 579 | /* turn off the Rx LED (LED_RX) */ |
a84d0a3d | 580 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); |
cd28ab6a SH |
581 | } |
582 | ||
0ce8b98d | 583 | if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { |
977bdf06 | 584 | /* apply fixes in PHY AFE */ |
ed6d32c7 SH |
585 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); |
586 | ||
977bdf06 | 587 | /* increase differential signal amplitude in 10BASE-T */ |
ed6d32c7 SH |
588 | gm_phy_write(hw, port, 0x18, 0xaa99); |
589 | gm_phy_write(hw, port, 0x17, 0x2011); | |
cd28ab6a | 590 | |
0ce8b98d SH |
591 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { |
592 | /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ | |
593 | gm_phy_write(hw, port, 0x18, 0xa204); | |
594 | gm_phy_write(hw, port, 0x17, 0x2002); | |
595 | } | |
977bdf06 SH |
596 | |
597 | /* set page register to 0 */ | |
9467a8fc | 598 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); |
05745c4a SH |
599 | } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
600 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | |
601 | /* apply workaround for integrated resistors calibration */ | |
602 | gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); | |
603 | gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); | |
0f5aac70 SH |
604 | } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { |
605 | /* apply fixes in PHY AFE */ | |
606 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); | |
607 | ||
608 | /* apply RDAC termination workaround */ | |
609 | gm_phy_write(hw, port, 24, 0x2800); | |
610 | gm_phy_write(hw, port, 23, 0x2001); | |
611 | ||
612 | /* set page register back to 0 */ | |
613 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); | |
e1a74b37 SH |
614 | } else if (hw->chip_id != CHIP_ID_YUKON_EX && |
615 | hw->chip_id < CHIP_ID_YUKON_SUPR) { | |
05745c4a | 616 | /* no effect on Yukon-XL */ |
977bdf06 | 617 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); |
cd28ab6a | 618 | |
8e95a202 JP |
619 | if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) || |
620 | sky2->speed == SPEED_100) { | |
977bdf06 | 621 | /* turn on 100 Mbps LED (LED_LINK100) */ |
a84d0a3d | 622 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); |
977bdf06 | 623 | } |
cd28ab6a | 624 | |
977bdf06 SH |
625 | if (ledover) |
626 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
627 | ||
628 | } | |
2eaba1a2 | 629 | |
d571b694 | 630 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
0ea065e5 | 631 | if (sky2->flags & SKY2_FLAG_AUTO_SPEED) |
cd28ab6a SH |
632 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); |
633 | else | |
634 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
635 | } | |
636 | ||
b96936da SH |
637 | static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; |
638 | static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; | |
639 | ||
640 | static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) | |
d3bcfbeb | 641 | { |
642 | u32 reg1; | |
d3bcfbeb | 643 | |
a40ccc68 | 644 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
b32f40c4 | 645 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
b96936da | 646 | reg1 &= ~phy_power[port]; |
d3bcfbeb | 647 | |
4b7c47aa | 648 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) |
ff35164e SH |
649 | reg1 |= coma_mode[port]; |
650 | ||
b32f40c4 | 651 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
a40ccc68 | 652 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
82637e80 | 653 | sky2_pci_read32(hw, PCI_DEV_REG1); |
f71eb1a2 SH |
654 | |
655 | if (hw->chip_id == CHIP_ID_YUKON_FE) | |
656 | gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); | |
657 | else if (hw->flags & SKY2_HW_ADV_POWER_CTL) | |
658 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
b96936da | 659 | } |
167f53d0 | 660 | |
b96936da SH |
661 | static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) |
662 | { | |
663 | u32 reg1; | |
db99b988 SH |
664 | u16 ctrl; |
665 | ||
666 | /* release GPHY Control reset */ | |
667 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
668 | ||
669 | /* release GMAC reset */ | |
670 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
671 | ||
672 | if (hw->flags & SKY2_HW_NEWER_PHY) { | |
673 | /* select page 2 to access MAC control register */ | |
674 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
675 | ||
676 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
677 | /* allow GMII Power Down */ | |
678 | ctrl &= ~PHY_M_MAC_GMIF_PUP; | |
679 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
680 | ||
681 | /* set page register back to 0 */ | |
682 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); | |
683 | } | |
684 | ||
685 | /* setup General Purpose Control Register */ | |
686 | gma_write16(hw, port, GM_GP_CTRL, | |
0ea065e5 SH |
687 | GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | |
688 | GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | | |
689 | GM_GPCR_AU_SPD_DIS); | |
db99b988 SH |
690 | |
691 | if (hw->chip_id != CHIP_ID_YUKON_EC) { | |
692 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
e484d5f5 RW |
693 | /* select page 2 to access MAC control register */ |
694 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
db99b988 | 695 | |
e484d5f5 | 696 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); |
db99b988 SH |
697 | /* enable Power Down */ |
698 | ctrl |= PHY_M_PC_POW_D_ENA; | |
699 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
e484d5f5 RW |
700 | |
701 | /* set page register back to 0 */ | |
702 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); | |
db99b988 SH |
703 | } |
704 | ||
705 | /* set IEEE compatible Power Down Mode (dev. #4.99) */ | |
706 | gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); | |
707 | } | |
b96936da | 708 | |
a40ccc68 | 709 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
b96936da | 710 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
db99b988 | 711 | reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ |
b96936da | 712 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
a40ccc68 | 713 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
d3bcfbeb | 714 | } |
715 | ||
38000a94 BP |
716 | /* Enable Rx/Tx */ |
717 | static void sky2_enable_rx_tx(struct sky2_port *sky2) | |
718 | { | |
719 | struct sky2_hw *hw = sky2->hw; | |
720 | unsigned port = sky2->port; | |
721 | u16 reg; | |
722 | ||
723 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
724 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
725 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
726 | } | |
727 | ||
1b537565 SH |
728 | /* Force a renegotiation */ |
729 | static void sky2_phy_reinit(struct sky2_port *sky2) | |
730 | { | |
e07b1aa8 | 731 | spin_lock_bh(&sky2->phy_lock); |
1b537565 | 732 | sky2_phy_init(sky2->hw, sky2->port); |
38000a94 | 733 | sky2_enable_rx_tx(sky2); |
e07b1aa8 | 734 | spin_unlock_bh(&sky2->phy_lock); |
1b537565 SH |
735 | } |
736 | ||
e3173832 SH |
737 | /* Put device in state to listen for Wake On Lan */ |
738 | static void sky2_wol_init(struct sky2_port *sky2) | |
739 | { | |
740 | struct sky2_hw *hw = sky2->hw; | |
741 | unsigned port = sky2->port; | |
742 | enum flow_control save_mode; | |
743 | u16 ctrl; | |
e3173832 SH |
744 | |
745 | /* Bring hardware out of reset */ | |
746 | sky2_write16(hw, B0_CTST, CS_RST_CLR); | |
747 | sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
748 | ||
749 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
750 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
751 | ||
752 | /* Force to 10/100 | |
753 | * sky2_reset will re-enable on resume | |
754 | */ | |
755 | save_mode = sky2->flow_mode; | |
756 | ctrl = sky2->advertising; | |
757 | ||
758 | sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); | |
759 | sky2->flow_mode = FC_NONE; | |
b96936da SH |
760 | |
761 | spin_lock_bh(&sky2->phy_lock); | |
762 | sky2_phy_power_up(hw, port); | |
763 | sky2_phy_init(hw, port); | |
764 | spin_unlock_bh(&sky2->phy_lock); | |
e3173832 SH |
765 | |
766 | sky2->flow_mode = save_mode; | |
767 | sky2->advertising = ctrl; | |
768 | ||
769 | /* Set GMAC to no flow control and auto update for speed/duplex */ | |
770 | gma_write16(hw, port, GM_GP_CTRL, | |
771 | GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| | |
772 | GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); | |
773 | ||
774 | /* Set WOL address */ | |
775 | memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), | |
776 | sky2->netdev->dev_addr, ETH_ALEN); | |
777 | ||
778 | /* Turn on appropriate WOL control bits */ | |
779 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); | |
780 | ctrl = 0; | |
781 | if (sky2->wol & WAKE_PHY) | |
782 | ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; | |
783 | else | |
784 | ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; | |
785 | ||
786 | if (sky2->wol & WAKE_MAGIC) | |
787 | ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; | |
788 | else | |
a419aef8 | 789 | ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; |
e3173832 SH |
790 | |
791 | ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; | |
792 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); | |
793 | ||
5f8ae5c5 | 794 | /* Disable PiG firmware */ |
795 | sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); | |
796 | ||
e3173832 SH |
797 | /* block receiver */ |
798 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
e3173832 SH |
799 | } |
800 | ||
69161611 SH |
801 | static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) |
802 | { | |
05745c4a SH |
803 | struct net_device *dev = hw->dev[port]; |
804 | ||
ed4d4161 SH |
805 | if ( (hw->chip_id == CHIP_ID_YUKON_EX && |
806 | hw->chip_rev != CHIP_REV_YU_EX_A0) || | |
877c8570 | 807 | hw->chip_id >= CHIP_ID_YUKON_FE_P) { |
ed4d4161 | 808 | /* Yukon-Extreme B0 and further Extreme devices */ |
44dde56d | 809 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); |
810 | } else if (dev->mtu > ETH_DATA_LEN) { | |
811 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
812 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), | |
813 | (ECU_JUMBO_WM << 16) | ECU_AE_THR); | |
05745c4a | 814 | |
44dde56d | 815 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); |
816 | } else | |
817 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); | |
69161611 SH |
818 | } |
819 | ||
cd28ab6a SH |
820 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) |
821 | { | |
822 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
823 | u16 reg; | |
25cccecc | 824 | u32 rx_reg; |
cd28ab6a SH |
825 | int i; |
826 | const u8 *addr = hw->dev[port]->dev_addr; | |
827 | ||
f350339c SH |
828 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
829 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
cd28ab6a SH |
830 | |
831 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
832 | ||
4b7c47aa | 833 | if (hw->chip_id == CHIP_ID_YUKON_XL && |
834 | hw->chip_rev == CHIP_REV_YU_XL_A0 && | |
835 | port == 1) { | |
cd28ab6a SH |
836 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
837 | /* clear GMAC 1 Control reset */ | |
838 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
839 | do { | |
840 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
841 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
842 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
843 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
844 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
845 | } | |
846 | ||
793b883e | 847 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a | 848 | |
2eaba1a2 SH |
849 | /* Enable Transmit FIFO Underrun */ |
850 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); | |
851 | ||
e07b1aa8 | 852 | spin_lock_bh(&sky2->phy_lock); |
b96936da | 853 | sky2_phy_power_up(hw, port); |
cd28ab6a | 854 | sky2_phy_init(hw, port); |
e07b1aa8 | 855 | spin_unlock_bh(&sky2->phy_lock); |
cd28ab6a SH |
856 | |
857 | /* MIB clear */ | |
858 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
859 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
860 | ||
43f2f104 SH |
861 | for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) |
862 | gma_read16(hw, port, i); | |
cd28ab6a SH |
863 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
864 | ||
865 | /* transmit control */ | |
866 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
867 | ||
868 | /* receive control reg: unicast + multicast + no FCS */ | |
869 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 870 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
871 | |
872 | /* transmit flow control */ | |
873 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
874 | ||
875 | /* transmit parameter */ | |
876 | gma_write16(hw, port, GM_TX_PARAM, | |
877 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
878 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
879 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
880 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
881 | ||
882 | /* serial mode register */ | |
883 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
6b1a3aef | 884 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
cd28ab6a | 885 | |
6b1a3aef | 886 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
887 | reg |= GM_SMOD_JUMBO_ENA; |
888 | ||
c1cd0a85 | 889 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
890 | hw->chip_rev == CHIP_REV_YU_EC_U_B1) | |
891 | reg |= GM_NEW_FLOW_CTRL; | |
892 | ||
cd28ab6a SH |
893 | gma_write16(hw, port, GM_SERIAL_MODE, reg); |
894 | ||
cd28ab6a SH |
895 | /* virtual address for data */ |
896 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
897 | ||
793b883e SH |
898 | /* physical address: used for pause frames */ |
899 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
900 | ||
901 | /* ignore counter overflows */ | |
cd28ab6a SH |
902 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
903 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
904 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
905 | ||
906 | /* Configure Rx MAC FIFO */ | |
907 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
25cccecc | 908 | rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; |
05745c4a SH |
909 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
910 | hw->chip_id == CHIP_ID_YUKON_FE_P) | |
25cccecc | 911 | rx_reg |= GMF_RX_OVER_ON; |
69161611 | 912 | |
25cccecc | 913 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); |
cd28ab6a | 914 | |
798fdd07 SH |
915 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
916 | /* Hardware errata - clear flush mask */ | |
917 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); | |
918 | } else { | |
919 | /* Flush Rx MAC FIFO on any flow control or error */ | |
920 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); | |
921 | } | |
cd28ab6a | 922 | |
8df9a876 | 923 | /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ |
05745c4a SH |
924 | reg = RX_GMF_FL_THR_DEF + 1; |
925 | /* Another magic mystery workaround from sk98lin */ | |
926 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && | |
927 | hw->chip_rev == CHIP_REV_YU_FE2_A0) | |
928 | reg = 0x178; | |
929 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); | |
cd28ab6a SH |
930 | |
931 | /* Configure Tx MAC FIFO */ | |
932 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
933 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 | 934 | |
25985edc | 935 | /* On chips without ram buffer, pause is controlled by MAC level */ |
39dbd958 | 936 | if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { |
d6b54d24 | 937 | /* Pause threshold is scaled by 8 in bytes */ |
8e95a202 JP |
938 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
939 | hw->chip_rev == CHIP_REV_YU_FE2_A0) | |
d6b54d24 SH |
940 | reg = 1568 / 8; |
941 | else | |
942 | reg = 1024 / 8; | |
943 | sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); | |
944 | sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); | |
b628ed98 | 945 | |
69161611 | 946 | sky2_set_tx_stfwd(hw, port); |
5a5b1ea0 | 947 | } |
948 | ||
e970d1f8 SH |
949 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
950 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | |
951 | /* disable dynamic watermark */ | |
952 | reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); | |
953 | reg &= ~TX_DYN_WM_ENA; | |
954 | sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); | |
955 | } | |
cd28ab6a SH |
956 | } |
957 | ||
67712901 SH |
958 | /* Assign Ram Buffer allocation to queue */ |
959 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) | |
cd28ab6a | 960 | { |
67712901 SH |
961 | u32 end; |
962 | ||
963 | /* convert from K bytes to qwords used for hw register */ | |
964 | start *= 1024/8; | |
965 | space *= 1024/8; | |
966 | end = start + space - 1; | |
793b883e | 967 | |
cd28ab6a SH |
968 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
969 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
970 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
971 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
972 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
973 | ||
974 | if (q == Q_R1 || q == Q_R2) { | |
1c28f6ba | 975 | u32 tp = space - space/4; |
793b883e | 976 | |
1c28f6ba SH |
977 | /* On receive queue's set the thresholds |
978 | * give receiver priority when > 3/4 full | |
979 | * send pause when down to 2K | |
980 | */ | |
981 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); | |
982 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); | |
793b883e | 983 | |
1c28f6ba SH |
984 | tp = space - 2048/8; |
985 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); | |
986 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); | |
cd28ab6a SH |
987 | } else { |
988 | /* Enable store & forward on Tx queue's because | |
989 | * Tx FIFO is only 1K on Yukon | |
990 | */ | |
991 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
992 | } | |
993 | ||
994 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 995 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
996 | } |
997 | ||
cd28ab6a | 998 | /* Setup Bus Memory Interface */ |
af4ed7e6 | 999 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
cd28ab6a SH |
1000 | { |
1001 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
1002 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
1003 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
af4ed7e6 | 1004 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
cd28ab6a SH |
1005 | } |
1006 | ||
cd28ab6a SH |
1007 | /* Setup prefetch unit registers. This is the interface between |
1008 | * hardware and driver list elements | |
1009 | */ | |
8cc048e3 | 1010 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
d6e74b6b | 1011 | dma_addr_t addr, u32 last) |
cd28ab6a | 1012 | { |
cd28ab6a SH |
1013 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
1014 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
d6e74b6b SH |
1015 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); |
1016 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); | |
cd28ab6a SH |
1017 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); |
1018 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
1019 | |
1020 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
1021 | } |
1022 | ||
9b289c33 | 1023 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) |
793b883e | 1024 | { |
9b289c33 | 1025 | struct sky2_tx_le *le = sky2->tx_le + *slot; |
793b883e | 1026 | |
ee5f68fe | 1027 | *slot = RING_NEXT(*slot, sky2->tx_ring_size); |
291ea614 | 1028 | le->ctrl = 0; |
793b883e SH |
1029 | return le; |
1030 | } | |
cd28ab6a | 1031 | |
88f5f0ca SH |
1032 | static void tx_init(struct sky2_port *sky2) |
1033 | { | |
1034 | struct sky2_tx_le *le; | |
1035 | ||
1036 | sky2->tx_prod = sky2->tx_cons = 0; | |
1037 | sky2->tx_tcpsum = 0; | |
1038 | sky2->tx_last_mss = 0; | |
1039 | ||
9b289c33 | 1040 | le = get_tx_le(sky2, &sky2->tx_prod); |
88f5f0ca SH |
1041 | le->addr = 0; |
1042 | le->opcode = OP_ADDR64 | HW_OWNER; | |
5dce95e5 | 1043 | sky2->tx_last_upper = 0; |
88f5f0ca SH |
1044 | } |
1045 | ||
290d4de5 SH |
1046 | /* Update chip's next pointer */ |
1047 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) | |
cd28ab6a | 1048 | { |
50432cb5 | 1049 | /* Make sure write' to descriptors are complete before we tell hardware */ |
762c2de2 | 1050 | wmb(); |
50432cb5 SH |
1051 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
1052 | ||
1053 | /* Synchronize I/O on since next processor may write to tail */ | |
1054 | mmiowb(); | |
cd28ab6a SH |
1055 | } |
1056 | ||
793b883e | 1057 | |
cd28ab6a SH |
1058 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
1059 | { | |
1060 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
cb5d9547 | 1061 | sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); |
291ea614 | 1062 | le->ctrl = 0; |
cd28ab6a SH |
1063 | return le; |
1064 | } | |
1065 | ||
060b946c | 1066 | static unsigned sky2_get_rx_threshold(struct sky2_port *sky2) |
39ef110b MM |
1067 | { |
1068 | unsigned size; | |
1069 | ||
1070 | /* Space needed for frame data + headers rounded up */ | |
1071 | size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); | |
1072 | ||
1073 | /* Stopping point for hardware truncation */ | |
1074 | return (size - 8) / sizeof(u32); | |
1075 | } | |
1076 | ||
060b946c | 1077 | static unsigned sky2_get_rx_data_size(struct sky2_port *sky2) |
39ef110b MM |
1078 | { |
1079 | struct rx_ring_info *re; | |
1080 | unsigned size; | |
1081 | ||
1082 | /* Space needed for frame data + headers rounded up */ | |
1083 | size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); | |
1084 | ||
1085 | sky2->rx_nfrags = size >> PAGE_SHIFT; | |
1086 | BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); | |
1087 | ||
1088 | /* Compute residue after pages */ | |
1089 | size -= sky2->rx_nfrags << PAGE_SHIFT; | |
1090 | ||
1091 | /* Optimize to handle small packets and headers */ | |
1092 | if (size < copybreak) | |
1093 | size = copybreak; | |
1094 | if (size < ETH_HLEN) | |
1095 | size = ETH_HLEN; | |
1096 | ||
1097 | return size; | |
1098 | } | |
1099 | ||
14d0263f | 1100 | /* Build description to hardware for one receive segment */ |
060b946c | 1101 | static void sky2_rx_add(struct sky2_port *sky2, u8 op, |
14d0263f | 1102 | dma_addr_t map, unsigned len) |
cd28ab6a SH |
1103 | { |
1104 | struct sky2_rx_le *le; | |
1105 | ||
86c6887e | 1106 | if (sizeof(dma_addr_t) > sizeof(u32)) { |
cd28ab6a | 1107 | le = sky2_next_rx(sky2); |
86c6887e | 1108 | le->addr = cpu_to_le32(upper_32_bits(map)); |
cd28ab6a SH |
1109 | le->opcode = OP_ADDR64 | HW_OWNER; |
1110 | } | |
793b883e | 1111 | |
cd28ab6a | 1112 | le = sky2_next_rx(sky2); |
d6e74b6b | 1113 | le->addr = cpu_to_le32(lower_32_bits(map)); |
734d1868 | 1114 | le->length = cpu_to_le16(len); |
14d0263f | 1115 | le->opcode = op | HW_OWNER; |
cd28ab6a SH |
1116 | } |
1117 | ||
14d0263f SH |
1118 | /* Build description to hardware for one possibly fragmented skb */ |
1119 | static void sky2_rx_submit(struct sky2_port *sky2, | |
1120 | const struct rx_ring_info *re) | |
1121 | { | |
1122 | int i; | |
1123 | ||
1124 | sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); | |
1125 | ||
1126 | for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) | |
1127 | sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); | |
1128 | } | |
1129 | ||
1130 | ||
454e6cb6 | 1131 | static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, |
14d0263f SH |
1132 | unsigned size) |
1133 | { | |
1134 | struct sk_buff *skb = re->skb; | |
1135 | int i; | |
1136 | ||
1137 | re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); | |
3fbd9187 | 1138 | if (pci_dma_mapping_error(pdev, re->data_addr)) |
1139 | goto mapping_error; | |
454e6cb6 | 1140 | |
7cd26ce5 | 1141 | dma_unmap_len_set(re, data_size, size); |
14d0263f | 1142 | |
3fbd9187 | 1143 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
1144 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1145 | ||
1146 | re->frag_addr[i] = pci_map_page(pdev, frag->page, | |
1147 | frag->page_offset, | |
1148 | frag->size, | |
14d0263f | 1149 | PCI_DMA_FROMDEVICE); |
3fbd9187 | 1150 | |
1151 | if (pci_dma_mapping_error(pdev, re->frag_addr[i])) | |
1152 | goto map_page_error; | |
1153 | } | |
454e6cb6 | 1154 | return 0; |
3fbd9187 | 1155 | |
1156 | map_page_error: | |
1157 | while (--i >= 0) { | |
1158 | pci_unmap_page(pdev, re->frag_addr[i], | |
1159 | skb_shinfo(skb)->frags[i].size, | |
1160 | PCI_DMA_FROMDEVICE); | |
1161 | } | |
1162 | ||
7cd26ce5 | 1163 | pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), |
3fbd9187 | 1164 | PCI_DMA_FROMDEVICE); |
1165 | ||
1166 | mapping_error: | |
1167 | if (net_ratelimit()) | |
1168 | dev_warn(&pdev->dev, "%s: rx mapping error\n", | |
1169 | skb->dev->name); | |
1170 | return -EIO; | |
14d0263f SH |
1171 | } |
1172 | ||
1173 | static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) | |
1174 | { | |
1175 | struct sk_buff *skb = re->skb; | |
1176 | int i; | |
1177 | ||
7cd26ce5 | 1178 | pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), |
14d0263f SH |
1179 | PCI_DMA_FROMDEVICE); |
1180 | ||
1181 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) | |
1182 | pci_unmap_page(pdev, re->frag_addr[i], | |
1183 | skb_shinfo(skb)->frags[i].size, | |
1184 | PCI_DMA_FROMDEVICE); | |
1185 | } | |
793b883e | 1186 | |
cd28ab6a SH |
1187 | /* Tell chip where to start receive checksum. |
1188 | * Actually has two checksums, but set both same to avoid possible byte | |
1189 | * order problems. | |
1190 | */ | |
793b883e | 1191 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a | 1192 | { |
ea76e635 | 1193 | struct sky2_rx_le *le = sky2_next_rx(sky2); |
793b883e | 1194 | |
ea76e635 SH |
1195 | le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); |
1196 | le->ctrl = 0; | |
1197 | le->opcode = OP_TCPSTART | HW_OWNER; | |
cd28ab6a | 1198 | |
ea76e635 SH |
1199 | sky2_write32(sky2->hw, |
1200 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
f5d64037 | 1201 | (sky2->netdev->features & NETIF_F_RXCSUM) |
0ea065e5 | 1202 | ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); |
cd28ab6a SH |
1203 | } |
1204 | ||
bf73130d | 1205 | /* Enable/disable receive hash calculation (RSS) */ |
f5d64037 | 1206 | static void rx_set_rss(struct net_device *dev, u32 features) |
bf73130d SH |
1207 | { |
1208 | struct sky2_port *sky2 = netdev_priv(dev); | |
1209 | struct sky2_hw *hw = sky2->hw; | |
1210 | int i, nkeys = 4; | |
1211 | ||
1212 | /* Supports IPv6 and other modes */ | |
1213 | if (hw->flags & SKY2_HW_NEW_LE) { | |
1214 | nkeys = 10; | |
1215 | sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); | |
1216 | } | |
1217 | ||
1218 | /* Program RSS initial values */ | |
f5d64037 | 1219 | if (features & NETIF_F_RXHASH) { |
bf73130d SH |
1220 | u32 key[nkeys]; |
1221 | ||
1222 | get_random_bytes(key, nkeys * sizeof(u32)); | |
1223 | for (i = 0; i < nkeys; i++) | |
1224 | sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), | |
1225 | key[i]); | |
1226 | ||
1227 | /* Need to turn on (undocumented) flag to make hashing work */ | |
1228 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), | |
1229 | RX_STFW_ENA); | |
1230 | ||
1231 | sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
1232 | BMU_ENA_RX_RSS_HASH); | |
1233 | } else | |
1234 | sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
1235 | BMU_DIS_RX_RSS_HASH); | |
1236 | } | |
1237 | ||
6b1a3aef | 1238 | /* |
1239 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
1240 | * reach the end of packet and since we can't make sure that we have | |
1241 | * incoming data, we must reset the BMU while it is not doing a DMA | |
1242 | * transfer. Since it is possible that the RX path is still active, | |
1243 | * the RX RAM buffer will be stopped first, so any possible incoming | |
1244 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
1245 | * BMU is polled until any DMA in progress is ended and only then it | |
1246 | * will be reset. | |
1247 | */ | |
1248 | static void sky2_rx_stop(struct sky2_port *sky2) | |
1249 | { | |
1250 | struct sky2_hw *hw = sky2->hw; | |
1251 | unsigned rxq = rxqaddr[sky2->port]; | |
1252 | int i; | |
1253 | ||
1254 | /* disable the RAM Buffer receive queue */ | |
1255 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
1256 | ||
1257 | for (i = 0; i < 0xffff; i++) | |
1258 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
1259 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
1260 | goto stopped; | |
1261 | ||
ada1db5c | 1262 | netdev_warn(sky2->netdev, "receiver stop failed\n"); |
6b1a3aef | 1263 | stopped: |
1264 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
1265 | ||
1266 | /* reset the Rx prefetch unit */ | |
1267 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
3d1454dd | 1268 | mmiowb(); |
6b1a3aef | 1269 | } |
793b883e | 1270 | |
d571b694 | 1271 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
1272 | static void sky2_rx_clean(struct sky2_port *sky2) |
1273 | { | |
1274 | unsigned i; | |
1275 | ||
1276 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 1277 | for (i = 0; i < sky2->rx_pending; i++) { |
291ea614 | 1278 | struct rx_ring_info *re = sky2->rx_ring + i; |
cd28ab6a SH |
1279 | |
1280 | if (re->skb) { | |
14d0263f | 1281 | sky2_rx_unmap_skb(sky2->hw->pdev, re); |
cd28ab6a SH |
1282 | kfree_skb(re->skb); |
1283 | re->skb = NULL; | |
1284 | } | |
1285 | } | |
1286 | } | |
1287 | ||
ef743d33 | 1288 | /* Basic MII support */ |
1289 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1290 | { | |
1291 | struct mii_ioctl_data *data = if_mii(ifr); | |
1292 | struct sky2_port *sky2 = netdev_priv(dev); | |
1293 | struct sky2_hw *hw = sky2->hw; | |
1294 | int err = -EOPNOTSUPP; | |
1295 | ||
1296 | if (!netif_running(dev)) | |
1297 | return -ENODEV; /* Phy still in reset */ | |
1298 | ||
d89e1343 | 1299 | switch (cmd) { |
ef743d33 | 1300 | case SIOCGMIIPHY: |
1301 | data->phy_id = PHY_ADDR_MARV; | |
1302 | ||
1303 | /* fallthru */ | |
1304 | case SIOCGMIIREG: { | |
1305 | u16 val = 0; | |
91c86df5 | 1306 | |
e07b1aa8 | 1307 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 | 1308 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
e07b1aa8 | 1309 | spin_unlock_bh(&sky2->phy_lock); |
91c86df5 | 1310 | |
ef743d33 | 1311 | data->val_out = val; |
1312 | break; | |
1313 | } | |
1314 | ||
1315 | case SIOCSMIIREG: | |
e07b1aa8 | 1316 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 | 1317 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
1318 | data->val_in); | |
e07b1aa8 | 1319 | spin_unlock_bh(&sky2->phy_lock); |
ef743d33 | 1320 | break; |
1321 | } | |
1322 | return err; | |
1323 | } | |
1324 | ||
f5d64037 | 1325 | #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO) |
d494eacd | 1326 | |
f5d64037 | 1327 | static void sky2_vlan_mode(struct net_device *dev, u32 features) |
d494eacd SH |
1328 | { |
1329 | struct sky2_port *sky2 = netdev_priv(dev); | |
1330 | struct sky2_hw *hw = sky2->hw; | |
1331 | u16 port = sky2->port; | |
1332 | ||
f5d64037 | 1333 | if (features & NETIF_F_HW_VLAN_RX) |
86aa7785 SH |
1334 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), |
1335 | RX_VLAN_STRIP_ON); | |
1336 | else | |
1337 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), | |
1338 | RX_VLAN_STRIP_OFF); | |
d494eacd | 1339 | |
f5d64037 | 1340 | if (features & NETIF_F_HW_VLAN_TX) { |
86aa7785 SH |
1341 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
1342 | TX_VLAN_TAG_ON); | |
f5d64037 MM |
1343 | |
1344 | dev->vlan_features |= SKY2_VLAN_OFFLOADS; | |
1345 | } else { | |
86aa7785 SH |
1346 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
1347 | TX_VLAN_TAG_OFF); | |
d1f13708 | 1348 | |
86aa7785 | 1349 | /* Can't do transmit offload of vlan without hw vlan */ |
f5d64037 | 1350 | dev->vlan_features &= ~SKY2_VLAN_OFFLOADS; |
86aa7785 | 1351 | } |
d1f13708 | 1352 | } |
d1f13708 | 1353 | |
bd1c6869 SH |
1354 | /* Amount of required worst case padding in rx buffer */ |
1355 | static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) | |
1356 | { | |
1357 | return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; | |
1358 | } | |
1359 | ||
82788c7a | 1360 | /* |
14d0263f SH |
1361 | * Allocate an skb for receiving. If the MTU is large enough |
1362 | * make the skb non-linear with a fragment list of pages. | |
82788c7a | 1363 | */ |
14d0263f | 1364 | static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2) |
82788c7a SH |
1365 | { |
1366 | struct sk_buff *skb; | |
14d0263f | 1367 | int i; |
82788c7a | 1368 | |
724b6942 SH |
1369 | skb = netdev_alloc_skb(sky2->netdev, |
1370 | sky2->rx_data_size + sky2_rx_pad(sky2->hw)); | |
bd1c6869 SH |
1371 | if (!skb) |
1372 | goto nomem; | |
1373 | ||
39dbd958 | 1374 | if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { |
f03b8654 SH |
1375 | unsigned char *start; |
1376 | /* | |
1377 | * Workaround for a bug in FIFO that cause hang | |
1378 | * if the FIFO if the receive buffer is not 64 byte aligned. | |
1379 | * The buffer returned from netdev_alloc_skb is | |
1380 | * aligned except if slab debugging is enabled. | |
1381 | */ | |
f03b8654 SH |
1382 | start = PTR_ALIGN(skb->data, 8); |
1383 | skb_reserve(skb, start - skb->data); | |
bd1c6869 | 1384 | } else |
f03b8654 | 1385 | skb_reserve(skb, NET_IP_ALIGN); |
14d0263f SH |
1386 | |
1387 | for (i = 0; i < sky2->rx_nfrags; i++) { | |
1388 | struct page *page = alloc_page(GFP_ATOMIC); | |
1389 | ||
1390 | if (!page) | |
1391 | goto free_partial; | |
1392 | skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); | |
82788c7a SH |
1393 | } |
1394 | ||
1395 | return skb; | |
14d0263f SH |
1396 | free_partial: |
1397 | kfree_skb(skb); | |
1398 | nomem: | |
1399 | return NULL; | |
82788c7a SH |
1400 | } |
1401 | ||
55c9dd35 SH |
1402 | static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) |
1403 | { | |
1404 | sky2_put_idx(sky2->hw, rxq, sky2->rx_put); | |
1405 | } | |
1406 | ||
200ac492 MM |
1407 | static int sky2_alloc_rx_skbs(struct sky2_port *sky2) |
1408 | { | |
1409 | struct sky2_hw *hw = sky2->hw; | |
1410 | unsigned i; | |
1411 | ||
1412 | sky2->rx_data_size = sky2_get_rx_data_size(sky2); | |
1413 | ||
1414 | /* Fill Rx ring */ | |
1415 | for (i = 0; i < sky2->rx_pending; i++) { | |
1416 | struct rx_ring_info *re = sky2->rx_ring + i; | |
1417 | ||
1418 | re->skb = sky2_rx_alloc(sky2); | |
1419 | if (!re->skb) | |
1420 | return -ENOMEM; | |
1421 | ||
1422 | if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { | |
1423 | dev_kfree_skb(re->skb); | |
1424 | re->skb = NULL; | |
1425 | return -ENOMEM; | |
1426 | } | |
1427 | } | |
1428 | return 0; | |
1429 | } | |
1430 | ||
cd28ab6a | 1431 | /* |
200ac492 | 1432 | * Setup receiver buffer pool. |
14d0263f SH |
1433 | * Normal case this ends up creating one list element for skb |
1434 | * in the receive ring. Worst case if using large MTU and each | |
1435 | * allocation falls on a different 64 bit region, that results | |
1436 | * in 6 list elements per ring entry. | |
1437 | * One element is used for checksum enable/disable, and one | |
1438 | * extra to avoid wrap. | |
cd28ab6a | 1439 | */ |
200ac492 | 1440 | static void sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 1441 | { |
6b1a3aef | 1442 | struct sky2_hw *hw = sky2->hw; |
14d0263f | 1443 | struct rx_ring_info *re; |
6b1a3aef | 1444 | unsigned rxq = rxqaddr[sky2->port]; |
39ef110b | 1445 | unsigned i, thresh; |
cd28ab6a | 1446 | |
6b1a3aef | 1447 | sky2->rx_put = sky2->rx_next = 0; |
af4ed7e6 | 1448 | sky2_qset(hw, rxq); |
977bdf06 | 1449 | |
c3905bc4 SH |
1450 | /* On PCI express lowering the watermark gives better performance */ |
1451 | if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) | |
1452 | sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); | |
1453 | ||
1454 | /* These chips have no ram buffer? | |
1455 | * MAC Rx RAM Read is controlled by hardware */ | |
8df9a876 | 1456 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
c1cd0a85 | 1457 | hw->chip_rev > CHIP_REV_YU_EC_U_A0) |
f449c7c1 | 1458 | sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); |
977bdf06 | 1459 | |
6b1a3aef | 1460 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
1461 | ||
ea76e635 SH |
1462 | if (!(hw->flags & SKY2_HW_NEW_LE)) |
1463 | rx_set_checksum(sky2); | |
14d0263f | 1464 | |
bf73130d | 1465 | if (!(hw->flags & SKY2_HW_RSS_BROKEN)) |
f5d64037 | 1466 | rx_set_rss(sky2->netdev, sky2->netdev->features); |
bf73130d | 1467 | |
200ac492 | 1468 | /* submit Rx ring */ |
793b883e | 1469 | for (i = 0; i < sky2->rx_pending; i++) { |
14d0263f | 1470 | re = sky2->rx_ring + i; |
14d0263f | 1471 | sky2_rx_submit(sky2, re); |
cd28ab6a SH |
1472 | } |
1473 | ||
a1433ac4 SH |
1474 | /* |
1475 | * The receiver hangs if it receives frames larger than the | |
1476 | * packet buffer. As a workaround, truncate oversize frames, but | |
1477 | * the register is limited to 9 bits, so if you do frames > 2052 | |
1478 | * you better get the MTU right! | |
1479 | */ | |
39ef110b | 1480 | thresh = sky2_get_rx_threshold(sky2); |
a1433ac4 SH |
1481 | if (thresh > 0x1ff) |
1482 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); | |
1483 | else { | |
1484 | sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); | |
1485 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); | |
1486 | } | |
1487 | ||
6b1a3aef | 1488 | /* Tell chip about available buffers */ |
55c9dd35 | 1489 | sky2_rx_update(sky2, rxq); |
877c8570 SH |
1490 | |
1491 | if (hw->chip_id == CHIP_ID_YUKON_EX || | |
1492 | hw->chip_id == CHIP_ID_YUKON_SUPR) { | |
1493 | /* | |
1494 | * Disable flushing of non ASF packets; | |
1495 | * must be done after initializing the BMUs; | |
1496 | * drivers without ASF support should do this too, otherwise | |
1497 | * it may happen that they cannot run on ASF devices; | |
1498 | * remember that the MAC FIFO isn't reset during initialization. | |
1499 | */ | |
1500 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); | |
1501 | } | |
1502 | ||
1503 | if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { | |
1504 | /* Enable RX Home Address & Routing Header checksum fix */ | |
1505 | sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), | |
1506 | RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA); | |
1507 | ||
1508 | /* Enable TX Home Address & Routing Header checksum fix */ | |
1509 | sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), | |
1510 | TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN); | |
1511 | } | |
cd28ab6a SH |
1512 | } |
1513 | ||
90bbebb4 MM |
1514 | static int sky2_alloc_buffers(struct sky2_port *sky2) |
1515 | { | |
1516 | struct sky2_hw *hw = sky2->hw; | |
1517 | ||
1518 | /* must be power of 2 */ | |
1519 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
1520 | sky2->tx_ring_size * | |
1521 | sizeof(struct sky2_tx_le), | |
1522 | &sky2->tx_le_map); | |
1523 | if (!sky2->tx_le) | |
1524 | goto nomem; | |
1525 | ||
1526 | sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info), | |
1527 | GFP_KERNEL); | |
1528 | if (!sky2->tx_ring) | |
1529 | goto nomem; | |
1530 | ||
1531 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
1532 | &sky2->rx_le_map); | |
1533 | if (!sky2->rx_le) | |
1534 | goto nomem; | |
1535 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
1536 | ||
1537 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), | |
1538 | GFP_KERNEL); | |
1539 | if (!sky2->rx_ring) | |
1540 | goto nomem; | |
1541 | ||
200ac492 | 1542 | return sky2_alloc_rx_skbs(sky2); |
90bbebb4 MM |
1543 | nomem: |
1544 | return -ENOMEM; | |
1545 | } | |
1546 | ||
1547 | static void sky2_free_buffers(struct sky2_port *sky2) | |
1548 | { | |
1549 | struct sky2_hw *hw = sky2->hw; | |
1550 | ||
200ac492 MM |
1551 | sky2_rx_clean(sky2); |
1552 | ||
90bbebb4 MM |
1553 | if (sky2->rx_le) { |
1554 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1555 | sky2->rx_le, sky2->rx_le_map); | |
1556 | sky2->rx_le = NULL; | |
1557 | } | |
1558 | if (sky2->tx_le) { | |
1559 | pci_free_consistent(hw->pdev, | |
1560 | sky2->tx_ring_size * sizeof(struct sky2_tx_le), | |
1561 | sky2->tx_le, sky2->tx_le_map); | |
1562 | sky2->tx_le = NULL; | |
1563 | } | |
1564 | kfree(sky2->tx_ring); | |
1565 | kfree(sky2->rx_ring); | |
1566 | ||
1567 | sky2->tx_ring = NULL; | |
1568 | sky2->rx_ring = NULL; | |
1569 | } | |
1570 | ||
ea0f71e5 | 1571 | static void sky2_hw_up(struct sky2_port *sky2) |
cd28ab6a | 1572 | { |
cd28ab6a SH |
1573 | struct sky2_hw *hw = sky2->hw; |
1574 | unsigned port = sky2->port; | |
ea0f71e5 MM |
1575 | u32 ramsize; |
1576 | int cap; | |
843a46f4 | 1577 | struct net_device *otherdev = hw->dev[sky2->port^1]; |
cd28ab6a | 1578 | |
ea0f71e5 MM |
1579 | tx_init(sky2); |
1580 | ||
ee7abb04 SH |
1581 | /* |
1582 | * On dual port PCI-X card, there is an problem where status | |
1583 | * can be received out of order due to split transactions | |
843a46f4 | 1584 | */ |
ee7abb04 SH |
1585 | if (otherdev && netif_running(otherdev) && |
1586 | (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { | |
ee7abb04 SH |
1587 | u16 cmd; |
1588 | ||
b32f40c4 | 1589 | cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); |
ee7abb04 | 1590 | cmd &= ~PCI_X_CMD_MAX_SPLIT; |
b32f40c4 | 1591 | sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); |
ea0f71e5 | 1592 | } |
cd28ab6a | 1593 | |
cd28ab6a SH |
1594 | sky2_mac_init(hw, port); |
1595 | ||
e0c28116 SH |
1596 | /* Register is number of 4K blocks on internal RAM buffer. */ |
1597 | ramsize = sky2_read8(hw, B2_E_0) * 4; | |
1598 | if (ramsize > 0) { | |
67712901 | 1599 | u32 rxspace; |
cd28ab6a | 1600 | |
ada1db5c | 1601 | netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize); |
67712901 SH |
1602 | if (ramsize < 16) |
1603 | rxspace = ramsize / 2; | |
1604 | else | |
1605 | rxspace = 8 + (2*(ramsize - 16))/3; | |
cd28ab6a | 1606 | |
67712901 SH |
1607 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); |
1608 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); | |
1609 | ||
1610 | /* Make sure SyncQ is disabled */ | |
1611 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
1612 | RB_RST_SET); | |
1613 | } | |
793b883e | 1614 | |
af4ed7e6 | 1615 | sky2_qset(hw, txqaddr[port]); |
5a5b1ea0 | 1616 | |
69161611 SH |
1617 | /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ |
1618 | if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) | |
1619 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); | |
1620 | ||
977bdf06 | 1621 | /* Set almost empty threshold */ |
8e95a202 JP |
1622 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
1623 | hw->chip_rev == CHIP_REV_YU_EC_U_A0) | |
b628ed98 | 1624 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); |
5a5b1ea0 | 1625 | |
6b1a3aef | 1626 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
ee5f68fe | 1627 | sky2->tx_ring_size - 1); |
cd28ab6a | 1628 | |
f5d64037 MM |
1629 | sky2_vlan_mode(sky2->netdev, sky2->netdev->features); |
1630 | netdev_update_features(sky2->netdev); | |
d494eacd | 1631 | |
200ac492 | 1632 | sky2_rx_start(sky2); |
ea0f71e5 MM |
1633 | } |
1634 | ||
1635 | /* Bring up network interface. */ | |
1636 | static int sky2_up(struct net_device *dev) | |
1637 | { | |
1638 | struct sky2_port *sky2 = netdev_priv(dev); | |
1639 | struct sky2_hw *hw = sky2->hw; | |
1640 | unsigned port = sky2->port; | |
1641 | u32 imask; | |
1642 | int err; | |
1643 | ||
1644 | netif_carrier_off(dev); | |
1645 | ||
1646 | err = sky2_alloc_buffers(sky2); | |
1647 | if (err) | |
1648 | goto err_out; | |
1649 | ||
1650 | sky2_hw_up(sky2); | |
cd28ab6a | 1651 | |
cd28ab6a | 1652 | /* Enable interrupts from phy/mac for port */ |
e07b1aa8 | 1653 | imask = sky2_read32(hw, B0_IMSK); |
f4ea431b | 1654 | imask |= portirq_msk[port]; |
e07b1aa8 | 1655 | sky2_write32(hw, B0_IMSK, imask); |
1fd82f3c | 1656 | sky2_read32(hw, B0_IMSK); |
e07b1aa8 | 1657 | |
6c35abae | 1658 | netif_info(sky2, ifup, dev, "enabling interface\n"); |
af18d8b8 | 1659 | |
cd28ab6a SH |
1660 | return 0; |
1661 | ||
1662 | err_out: | |
90bbebb4 | 1663 | sky2_free_buffers(sky2); |
cd28ab6a SH |
1664 | return err; |
1665 | } | |
1666 | ||
793b883e | 1667 | /* Modular subtraction in ring */ |
ee5f68fe | 1668 | static inline int tx_inuse(const struct sky2_port *sky2) |
793b883e | 1669 | { |
ee5f68fe | 1670 | return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); |
793b883e | 1671 | } |
cd28ab6a | 1672 | |
793b883e SH |
1673 | /* Number of list elements available for next tx */ |
1674 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1675 | { |
ee5f68fe | 1676 | return sky2->tx_pending - tx_inuse(sky2); |
cd28ab6a SH |
1677 | } |
1678 | ||
793b883e | 1679 | /* Estimate of number of transmit list elements required */ |
28bd181a | 1680 | static unsigned tx_le_req(const struct sk_buff *skb) |
cd28ab6a | 1681 | { |
793b883e SH |
1682 | unsigned count; |
1683 | ||
07e31637 SH |
1684 | count = (skb_shinfo(skb)->nr_frags + 1) |
1685 | * (sizeof(dma_addr_t) / sizeof(u32)); | |
793b883e | 1686 | |
89114afd | 1687 | if (skb_is_gso(skb)) |
793b883e | 1688 | ++count; |
07e31637 SH |
1689 | else if (sizeof(dma_addr_t) == sizeof(u32)) |
1690 | ++count; /* possible vlan */ | |
793b883e | 1691 | |
84fa7933 | 1692 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
793b883e SH |
1693 | ++count; |
1694 | ||
1695 | return count; | |
cd28ab6a SH |
1696 | } |
1697 | ||
f6815077 | 1698 | static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) |
6b84daca SH |
1699 | { |
1700 | if (re->flags & TX_MAP_SINGLE) | |
7cd26ce5 FT |
1701 | pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr), |
1702 | dma_unmap_len(re, maplen), | |
6b84daca SH |
1703 | PCI_DMA_TODEVICE); |
1704 | else if (re->flags & TX_MAP_PAGE) | |
7cd26ce5 FT |
1705 | pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr), |
1706 | dma_unmap_len(re, maplen), | |
6b84daca | 1707 | PCI_DMA_TODEVICE); |
f6815077 | 1708 | re->flags = 0; |
6b84daca SH |
1709 | } |
1710 | ||
793b883e SH |
1711 | /* |
1712 | * Put one packet in ring for transmit. | |
1713 | * A single packet can generate multiple list elements, and | |
1714 | * the number of ring elements will probably be less than the number | |
1715 | * of list elements used. | |
1716 | */ | |
61357325 SH |
1717 | static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, |
1718 | struct net_device *dev) | |
cd28ab6a SH |
1719 | { |
1720 | struct sky2_port *sky2 = netdev_priv(dev); | |
1721 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1722 | struct sky2_tx_le *le = NULL; |
6cdbbdf3 | 1723 | struct tx_ring_info *re; |
9b289c33 | 1724 | unsigned i, len; |
cd28ab6a | 1725 | dma_addr_t mapping; |
5dce95e5 SH |
1726 | u32 upper; |
1727 | u16 slot; | |
cd28ab6a SH |
1728 | u16 mss; |
1729 | u8 ctrl; | |
1730 | ||
2bb8c262 SH |
1731 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) |
1732 | return NETDEV_TX_BUSY; | |
cd28ab6a | 1733 | |
cd28ab6a SH |
1734 | len = skb_headlen(skb); |
1735 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
793b883e | 1736 | |
454e6cb6 SH |
1737 | if (pci_dma_mapping_error(hw->pdev, mapping)) |
1738 | goto mapping_error; | |
1739 | ||
9b289c33 | 1740 | slot = sky2->tx_prod; |
6c35abae JP |
1741 | netif_printk(sky2, tx_queued, KERN_DEBUG, dev, |
1742 | "tx queued, slot %u, len %d\n", slot, skb->len); | |
454e6cb6 | 1743 | |
86c6887e | 1744 | /* Send high bits if needed */ |
5dce95e5 SH |
1745 | upper = upper_32_bits(mapping); |
1746 | if (upper != sky2->tx_last_upper) { | |
9b289c33 | 1747 | le = get_tx_le(sky2, &slot); |
5dce95e5 SH |
1748 | le->addr = cpu_to_le32(upper); |
1749 | sky2->tx_last_upper = upper; | |
793b883e | 1750 | le->opcode = OP_ADDR64 | HW_OWNER; |
793b883e | 1751 | } |
cd28ab6a SH |
1752 | |
1753 | /* Check for TCP Segmentation Offload */ | |
7967168c | 1754 | mss = skb_shinfo(skb)->gso_size; |
793b883e | 1755 | if (mss != 0) { |
ea76e635 SH |
1756 | |
1757 | if (!(hw->flags & SKY2_HW_NEW_LE)) | |
69161611 SH |
1758 | mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); |
1759 | ||
1760 | if (mss != sky2->tx_last_mss) { | |
9b289c33 | 1761 | le = get_tx_le(sky2, &slot); |
69161611 | 1762 | le->addr = cpu_to_le32(mss); |
ea76e635 SH |
1763 | |
1764 | if (hw->flags & SKY2_HW_NEW_LE) | |
69161611 SH |
1765 | le->opcode = OP_MSS | HW_OWNER; |
1766 | else | |
1767 | le->opcode = OP_LRGLEN | HW_OWNER; | |
e07560cd | 1768 | sky2->tx_last_mss = mss; |
1769 | } | |
cd28ab6a SH |
1770 | } |
1771 | ||
cd28ab6a | 1772 | ctrl = 0; |
86aa7785 | 1773 | |
d1f13708 | 1774 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ |
eab6d18d | 1775 | if (vlan_tx_tag_present(skb)) { |
d1f13708 | 1776 | if (!le) { |
9b289c33 | 1777 | le = get_tx_le(sky2, &slot); |
f65b138c | 1778 | le->addr = 0; |
d1f13708 | 1779 | le->opcode = OP_VLAN|HW_OWNER; |
d1f13708 | 1780 | } else |
1781 | le->opcode |= OP_VLAN; | |
1782 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); | |
1783 | ctrl |= INS_VLAN; | |
1784 | } | |
d1f13708 | 1785 | |
1786 | /* Handle TCP checksum offload */ | |
84fa7933 | 1787 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
69161611 | 1788 | /* On Yukon EX (some versions) encoding change. */ |
ea76e635 | 1789 | if (hw->flags & SKY2_HW_AUTO_TX_SUM) |
69161611 SH |
1790 | ctrl |= CALSUM; /* auto checksum */ |
1791 | else { | |
1792 | const unsigned offset = skb_transport_offset(skb); | |
1793 | u32 tcpsum; | |
1794 | ||
1795 | tcpsum = offset << 16; /* sum start */ | |
1796 | tcpsum |= offset + skb->csum_offset; /* sum write */ | |
1797 | ||
1798 | ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1799 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) | |
1800 | ctrl |= UDPTCP; | |
1801 | ||
1802 | if (tcpsum != sky2->tx_tcpsum) { | |
1803 | sky2->tx_tcpsum = tcpsum; | |
1804 | ||
9b289c33 | 1805 | le = get_tx_le(sky2, &slot); |
69161611 SH |
1806 | le->addr = cpu_to_le32(tcpsum); |
1807 | le->length = 0; /* initial checksum value */ | |
1808 | le->ctrl = 1; /* one packet */ | |
1809 | le->opcode = OP_TCPLISW | HW_OWNER; | |
1810 | } | |
1d179332 | 1811 | } |
cd28ab6a SH |
1812 | } |
1813 | ||
6b84daca SH |
1814 | re = sky2->tx_ring + slot; |
1815 | re->flags = TX_MAP_SINGLE; | |
7cd26ce5 FT |
1816 | dma_unmap_addr_set(re, mapaddr, mapping); |
1817 | dma_unmap_len_set(re, maplen, len); | |
6b84daca | 1818 | |
9b289c33 | 1819 | le = get_tx_le(sky2, &slot); |
d6e74b6b | 1820 | le->addr = cpu_to_le32(lower_32_bits(mapping)); |
cd28ab6a SH |
1821 | le->length = cpu_to_le16(len); |
1822 | le->ctrl = ctrl; | |
793b883e | 1823 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1824 | |
cd28ab6a SH |
1825 | |
1826 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
291ea614 | 1827 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
cd28ab6a SH |
1828 | |
1829 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
1830 | frag->size, PCI_DMA_TODEVICE); | |
86c6887e | 1831 | |
454e6cb6 SH |
1832 | if (pci_dma_mapping_error(hw->pdev, mapping)) |
1833 | goto mapping_unwind; | |
1834 | ||
5dce95e5 SH |
1835 | upper = upper_32_bits(mapping); |
1836 | if (upper != sky2->tx_last_upper) { | |
9b289c33 | 1837 | le = get_tx_le(sky2, &slot); |
5dce95e5 SH |
1838 | le->addr = cpu_to_le32(upper); |
1839 | sky2->tx_last_upper = upper; | |
793b883e | 1840 | le->opcode = OP_ADDR64 | HW_OWNER; |
cd28ab6a SH |
1841 | } |
1842 | ||
6b84daca SH |
1843 | re = sky2->tx_ring + slot; |
1844 | re->flags = TX_MAP_PAGE; | |
7cd26ce5 FT |
1845 | dma_unmap_addr_set(re, mapaddr, mapping); |
1846 | dma_unmap_len_set(re, maplen, frag->size); | |
6b84daca | 1847 | |
9b289c33 | 1848 | le = get_tx_le(sky2, &slot); |
d6e74b6b | 1849 | le->addr = cpu_to_le32(lower_32_bits(mapping)); |
cd28ab6a SH |
1850 | le->length = cpu_to_le16(frag->size); |
1851 | le->ctrl = ctrl; | |
793b883e | 1852 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1853 | } |
6cdbbdf3 | 1854 | |
6b84daca | 1855 | re->skb = skb; |
cd28ab6a SH |
1856 | le->ctrl |= EOP; |
1857 | ||
9b289c33 MM |
1858 | sky2->tx_prod = slot; |
1859 | ||
97bda706 | 1860 | if (tx_avail(sky2) <= MAX_SKB_TX_LE) |
1861 | netif_stop_queue(dev); | |
b19666d9 | 1862 | |
290d4de5 | 1863 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); |
cd28ab6a | 1864 | |
cd28ab6a | 1865 | return NETDEV_TX_OK; |
454e6cb6 SH |
1866 | |
1867 | mapping_unwind: | |
ee5f68fe | 1868 | for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { |
454e6cb6 SH |
1869 | re = sky2->tx_ring + i; |
1870 | ||
6b84daca | 1871 | sky2_tx_unmap(hw->pdev, re); |
454e6cb6 SH |
1872 | } |
1873 | ||
454e6cb6 SH |
1874 | mapping_error: |
1875 | if (net_ratelimit()) | |
1876 | dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); | |
1877 | dev_kfree_skb(skb); | |
1878 | return NETDEV_TX_OK; | |
cd28ab6a SH |
1879 | } |
1880 | ||
cd28ab6a | 1881 | /* |
793b883e SH |
1882 | * Free ring elements from starting at tx_cons until "done" |
1883 | * | |
481cea4a SH |
1884 | * NB: |
1885 | * 1. The hardware will tell us about partial completion of multi-part | |
291ea614 | 1886 | * buffers so make sure not to free skb to early. |
481cea4a SH |
1887 | * 2. This may run in parallel start_xmit because the it only |
1888 | * looks at the tail of the queue of FIFO (tx_cons), not | |
1889 | * the head (tx_prod) | |
cd28ab6a | 1890 | */ |
d11c13e7 | 1891 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 1892 | { |
d11c13e7 | 1893 | struct net_device *dev = sky2->netdev; |
291ea614 | 1894 | unsigned idx; |
cd28ab6a | 1895 | |
ee5f68fe | 1896 | BUG_ON(done >= sky2->tx_ring_size); |
2224795d | 1897 | |
291ea614 | 1898 | for (idx = sky2->tx_cons; idx != done; |
ee5f68fe | 1899 | idx = RING_NEXT(idx, sky2->tx_ring_size)) { |
291ea614 | 1900 | struct tx_ring_info *re = sky2->tx_ring + idx; |
6b84daca | 1901 | struct sk_buff *skb = re->skb; |
291ea614 | 1902 | |
6b84daca | 1903 | sky2_tx_unmap(sky2->hw->pdev, re); |
bd1c6869 | 1904 | |
6b84daca | 1905 | if (skb) { |
6c35abae JP |
1906 | netif_printk(sky2, tx_done, KERN_DEBUG, dev, |
1907 | "tx done %u\n", idx); | |
3cf26753 | 1908 | |
0885a30b | 1909 | u64_stats_update_begin(&sky2->tx_stats.syncp); |
1910 | ++sky2->tx_stats.packets; | |
1911 | sky2->tx_stats.bytes += skb->len; | |
1912 | u64_stats_update_end(&sky2->tx_stats.syncp); | |
bd1c6869 | 1913 | |
f6815077 | 1914 | re->skb = NULL; |
724b6942 | 1915 | dev_kfree_skb_any(skb); |
2bf56fe2 | 1916 | |
ee5f68fe | 1917 | sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); |
cd28ab6a | 1918 | } |
793b883e | 1919 | } |
793b883e | 1920 | |
291ea614 | 1921 | sky2->tx_cons = idx; |
50432cb5 | 1922 | smp_mb(); |
cd28ab6a SH |
1923 | } |
1924 | ||
264bb4fa | 1925 | static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) |
a510996b | 1926 | { |
a510996b MM |
1927 | /* Disable Force Sync bit and Enable Alloc bit */ |
1928 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
1929 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
1930 | ||
1931 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
1932 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
1933 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
1934 | ||
1935 | /* Reset the PCI FIFO of the async Tx queue */ | |
1936 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), | |
1937 | BMU_RST_SET | BMU_FIFO_RST); | |
1938 | ||
1939 | /* Reset the Tx prefetch units */ | |
1940 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
1941 | PREF_UNIT_RST_SET); | |
1942 | ||
1943 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
1944 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
1945 | } | |
1946 | ||
f2b31cb3 | 1947 | static void sky2_hw_down(struct sky2_port *sky2) |
cd28ab6a | 1948 | { |
cd28ab6a SH |
1949 | struct sky2_hw *hw = sky2->hw; |
1950 | unsigned port = sky2->port; | |
f2b31cb3 | 1951 | u16 ctrl; |
cd28ab6a | 1952 | |
d104acaf SH |
1953 | /* Force flow control off */ |
1954 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e | 1955 | |
cd28ab6a SH |
1956 | /* Stop transmitter */ |
1957 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
1958 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
1959 | ||
1960 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 1961 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
1962 | |
1963 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 1964 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
1965 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
1966 | ||
1967 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
1968 | ||
1969 | /* Workaround shared GMAC reset */ | |
8e95a202 JP |
1970 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && |
1971 | port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
1972 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1973 | ||
cd28ab6a | 1974 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); |
cd28ab6a | 1975 | |
6c83504f SH |
1976 | /* Force any delayed status interrrupt and NAPI */ |
1977 | sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); | |
1978 | sky2_write32(hw, STAT_TX_TIMER_CNT, 0); | |
1979 | sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); | |
1980 | sky2_read8(hw, STAT_ISR_TIMER_CTRL); | |
1981 | ||
a947a39d MM |
1982 | sky2_rx_stop(sky2); |
1983 | ||
0da6d7b3 | 1984 | spin_lock_bh(&sky2->phy_lock); |
b96936da | 1985 | sky2_phy_power_down(hw, port); |
0da6d7b3 | 1986 | spin_unlock_bh(&sky2->phy_lock); |
d3bcfbeb | 1987 | |
264bb4fa MM |
1988 | sky2_tx_reset(hw, port); |
1989 | ||
481cea4a SH |
1990 | /* Free any pending frames stuck in HW queue */ |
1991 | sky2_tx_complete(sky2, sky2->tx_prod); | |
f2b31cb3 MM |
1992 | } |
1993 | ||
1994 | /* Network shutdown */ | |
1995 | static int sky2_down(struct net_device *dev) | |
1996 | { | |
1997 | struct sky2_port *sky2 = netdev_priv(dev); | |
8a0c9228 | 1998 | struct sky2_hw *hw = sky2->hw; |
f2b31cb3 MM |
1999 | |
2000 | /* Never really got started! */ | |
2001 | if (!sky2->tx_le) | |
2002 | return 0; | |
2003 | ||
6c35abae | 2004 | netif_info(sky2, ifdown, dev, "disabling interface\n"); |
f2b31cb3 | 2005 | |
8a0c9228 MM |
2006 | /* Disable port IRQ */ |
2007 | sky2_write32(hw, B0_IMSK, | |
2008 | sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]); | |
2009 | sky2_read32(hw, B0_IMSK); | |
2010 | ||
2011 | synchronize_irq(hw->pdev->irq); | |
2012 | napi_synchronize(&hw->napi); | |
2013 | ||
f2b31cb3 | 2014 | sky2_hw_down(sky2); |
481cea4a | 2015 | |
90bbebb4 | 2016 | sky2_free_buffers(sky2); |
1b537565 | 2017 | |
cd28ab6a SH |
2018 | return 0; |
2019 | } | |
2020 | ||
2021 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
2022 | { | |
ea76e635 | 2023 | if (hw->flags & SKY2_HW_FIBRE_PHY) |
793b883e SH |
2024 | return SPEED_1000; |
2025 | ||
05745c4a SH |
2026 | if (!(hw->flags & SKY2_HW_GIGABIT)) { |
2027 | if (aux & PHY_M_PS_SPEED_100) | |
2028 | return SPEED_100; | |
2029 | else | |
2030 | return SPEED_10; | |
2031 | } | |
cd28ab6a SH |
2032 | |
2033 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
2034 | case PHY_M_PS_SPEED_1000: | |
2035 | return SPEED_1000; | |
2036 | case PHY_M_PS_SPEED_100: | |
2037 | return SPEED_100; | |
2038 | default: | |
2039 | return SPEED_10; | |
2040 | } | |
2041 | } | |
2042 | ||
2043 | static void sky2_link_up(struct sky2_port *sky2) | |
2044 | { | |
2045 | struct sky2_hw *hw = sky2->hw; | |
2046 | unsigned port = sky2->port; | |
16ad91e1 SH |
2047 | static const char *fc_name[] = { |
2048 | [FC_NONE] = "none", | |
2049 | [FC_TX] = "tx", | |
2050 | [FC_RX] = "rx", | |
2051 | [FC_BOTH] = "both", | |
2052 | }; | |
cd28ab6a | 2053 | |
38000a94 | 2054 | sky2_enable_rx_tx(sky2); |
cd28ab6a SH |
2055 | |
2056 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
2057 | ||
2058 | netif_carrier_on(sky2->netdev); | |
cd28ab6a | 2059 | |
75e80683 | 2060 | mod_timer(&hw->watchdog_timer, jiffies + 1); |
32c2c300 | 2061 | |
cd28ab6a | 2062 | /* Turn on link LED */ |
793b883e | 2063 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
2064 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
2065 | ||
6c35abae JP |
2066 | netif_info(sky2, link, sky2->netdev, |
2067 | "Link is up at %d Mbps, %s duplex, flow control %s\n", | |
2068 | sky2->speed, | |
2069 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
2070 | fc_name[sky2->flow_status]); | |
cd28ab6a SH |
2071 | } |
2072 | ||
2073 | static void sky2_link_down(struct sky2_port *sky2) | |
2074 | { | |
2075 | struct sky2_hw *hw = sky2->hw; | |
2076 | unsigned port = sky2->port; | |
2077 | u16 reg; | |
2078 | ||
2079 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
2080 | ||
2081 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
2082 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
2083 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
cd28ab6a | 2084 | |
cd28ab6a | 2085 | netif_carrier_off(sky2->netdev); |
cd28ab6a | 2086 | |
809aaaae | 2087 | /* Turn off link LED */ |
cd28ab6a SH |
2088 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); |
2089 | ||
6c35abae | 2090 | netif_info(sky2, link, sky2->netdev, "Link is down\n"); |
2eaba1a2 | 2091 | |
cd28ab6a SH |
2092 | sky2_phy_init(hw, port); |
2093 | } | |
2094 | ||
16ad91e1 SH |
2095 | static enum flow_control sky2_flow(int rx, int tx) |
2096 | { | |
2097 | if (rx) | |
2098 | return tx ? FC_BOTH : FC_RX; | |
2099 | else | |
2100 | return tx ? FC_TX : FC_NONE; | |
2101 | } | |
2102 | ||
793b883e SH |
2103 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
2104 | { | |
2105 | struct sky2_hw *hw = sky2->hw; | |
2106 | unsigned port = sky2->port; | |
da4c1ff4 | 2107 | u16 advert, lpa; |
793b883e | 2108 | |
da4c1ff4 | 2109 | advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); |
793b883e | 2110 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); |
793b883e | 2111 | if (lpa & PHY_M_AN_RF) { |
ada1db5c | 2112 | netdev_err(sky2->netdev, "remote fault\n"); |
793b883e SH |
2113 | return -1; |
2114 | } | |
2115 | ||
793b883e | 2116 | if (!(aux & PHY_M_PS_SPDUP_RES)) { |
ada1db5c | 2117 | netdev_err(sky2->netdev, "speed/duplex mismatch\n"); |
793b883e SH |
2118 | return -1; |
2119 | } | |
2120 | ||
793b883e | 2121 | sky2->speed = sky2_phy_speed(hw, aux); |
7c74ac1c | 2122 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; |
793b883e | 2123 | |
da4c1ff4 SH |
2124 | /* Since the pause result bits seem to in different positions on |
2125 | * different chips. look at registers. | |
2126 | */ | |
ea76e635 | 2127 | if (hw->flags & SKY2_HW_FIBRE_PHY) { |
da4c1ff4 SH |
2128 | /* Shift for bits in fiber PHY */ |
2129 | advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); | |
2130 | lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); | |
2131 | ||
2132 | if (advert & ADVERTISE_1000XPAUSE) | |
2133 | advert |= ADVERTISE_PAUSE_CAP; | |
2134 | if (advert & ADVERTISE_1000XPSE_ASYM) | |
2135 | advert |= ADVERTISE_PAUSE_ASYM; | |
2136 | if (lpa & LPA_1000XPAUSE) | |
2137 | lpa |= LPA_PAUSE_CAP; | |
2138 | if (lpa & LPA_1000XPAUSE_ASYM) | |
2139 | lpa |= LPA_PAUSE_ASYM; | |
2140 | } | |
793b883e | 2141 | |
da4c1ff4 SH |
2142 | sky2->flow_status = FC_NONE; |
2143 | if (advert & ADVERTISE_PAUSE_CAP) { | |
2144 | if (lpa & LPA_PAUSE_CAP) | |
2145 | sky2->flow_status = FC_BOTH; | |
2146 | else if (advert & ADVERTISE_PAUSE_ASYM) | |
2147 | sky2->flow_status = FC_RX; | |
2148 | } else if (advert & ADVERTISE_PAUSE_ASYM) { | |
2149 | if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) | |
2150 | sky2->flow_status = FC_TX; | |
2151 | } | |
793b883e | 2152 | |
8e95a202 JP |
2153 | if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 && |
2154 | !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) | |
16ad91e1 | 2155 | sky2->flow_status = FC_NONE; |
2eaba1a2 | 2156 | |
da4c1ff4 | 2157 | if (sky2->flow_status & FC_TX) |
793b883e SH |
2158 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
2159 | else | |
2160 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
2161 | ||
2162 | return 0; | |
2163 | } | |
cd28ab6a | 2164 | |
e07b1aa8 SH |
2165 | /* Interrupt from PHY */ |
2166 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
cd28ab6a | 2167 | { |
e07b1aa8 SH |
2168 | struct net_device *dev = hw->dev[port]; |
2169 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a SH |
2170 | u16 istatus, phystat; |
2171 | ||
ebc646f6 SH |
2172 | if (!netif_running(dev)) |
2173 | return; | |
2174 | ||
e07b1aa8 SH |
2175 | spin_lock(&sky2->phy_lock); |
2176 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); | |
2177 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
2178 | ||
6c35abae JP |
2179 | netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n", |
2180 | istatus, phystat); | |
cd28ab6a | 2181 | |
0ea065e5 | 2182 | if (istatus & PHY_M_IS_AN_COMPL) { |
9badba25 | 2183 | if (sky2_autoneg_done(sky2, phystat) == 0 && |
2184 | !netif_carrier_ok(dev)) | |
793b883e SH |
2185 | sky2_link_up(sky2); |
2186 | goto out; | |
2187 | } | |
cd28ab6a | 2188 | |
793b883e SH |
2189 | if (istatus & PHY_M_IS_LSP_CHANGE) |
2190 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 2191 | |
793b883e SH |
2192 | if (istatus & PHY_M_IS_DUP_CHANGE) |
2193 | sky2->duplex = | |
2194 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 2195 | |
793b883e SH |
2196 | if (istatus & PHY_M_IS_LST_CHANGE) { |
2197 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 2198 | sky2_link_up(sky2); |
793b883e SH |
2199 | else |
2200 | sky2_link_down(sky2); | |
cd28ab6a | 2201 | } |
793b883e | 2202 | out: |
e07b1aa8 | 2203 | spin_unlock(&sky2->phy_lock); |
cd28ab6a SH |
2204 | } |
2205 | ||
0f5aac70 SH |
2206 | /* Special quick link interrupt (Yukon-2 Optima only) */ |
2207 | static void sky2_qlink_intr(struct sky2_hw *hw) | |
2208 | { | |
2209 | struct sky2_port *sky2 = netdev_priv(hw->dev[0]); | |
2210 | u32 imask; | |
2211 | u16 phy; | |
2212 | ||
2213 | /* disable irq */ | |
2214 | imask = sky2_read32(hw, B0_IMSK); | |
2215 | imask &= ~Y2_IS_PHY_QLNK; | |
2216 | sky2_write32(hw, B0_IMSK, imask); | |
2217 | ||
2218 | /* reset PHY Link Detect */ | |
2219 | phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); | |
a40ccc68 | 2220 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
0f5aac70 | 2221 | sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); |
a40ccc68 | 2222 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
0f5aac70 SH |
2223 | |
2224 | sky2_link_up(sky2); | |
2225 | } | |
2226 | ||
62335ab0 | 2227 | /* Transmit timeout is only called if we are running, carrier is up |
302d1252 SH |
2228 | * and tx queue is full (stopped). |
2229 | */ | |
cd28ab6a SH |
2230 | static void sky2_tx_timeout(struct net_device *dev) |
2231 | { | |
2232 | struct sky2_port *sky2 = netdev_priv(dev); | |
8cc048e3 | 2233 | struct sky2_hw *hw = sky2->hw; |
cd28ab6a | 2234 | |
6c35abae | 2235 | netif_err(sky2, timer, dev, "tx timeout\n"); |
cd28ab6a | 2236 | |
ada1db5c JP |
2237 | netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n", |
2238 | sky2->tx_cons, sky2->tx_prod, | |
2239 | sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), | |
2240 | sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); | |
8f24664d | 2241 | |
81906791 SH |
2242 | /* can't restart safely under softirq */ |
2243 | schedule_work(&hw->restart_work); | |
cd28ab6a SH |
2244 | } |
2245 | ||
2246 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) | |
2247 | { | |
6b1a3aef | 2248 | struct sky2_port *sky2 = netdev_priv(dev); |
2249 | struct sky2_hw *hw = sky2->hw; | |
b628ed98 | 2250 | unsigned port = sky2->port; |
6b1a3aef | 2251 | int err; |
2252 | u16 ctl, mode; | |
e07b1aa8 | 2253 | u32 imask; |
cd28ab6a | 2254 | |
44dde56d | 2255 | /* MTU size outside the spec */ |
cd28ab6a SH |
2256 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) |
2257 | return -EINVAL; | |
2258 | ||
44dde56d | 2259 | /* MTU > 1500 on yukon FE and FE+ not allowed */ |
05745c4a SH |
2260 | if (new_mtu > ETH_DATA_LEN && |
2261 | (hw->chip_id == CHIP_ID_YUKON_FE || | |
2262 | hw->chip_id == CHIP_ID_YUKON_FE_P)) | |
d2adf4f6 SH |
2263 | return -EINVAL; |
2264 | ||
6b1a3aef | 2265 | if (!netif_running(dev)) { |
2266 | dev->mtu = new_mtu; | |
f5d64037 | 2267 | netdev_update_features(dev); |
6b1a3aef | 2268 | return 0; |
2269 | } | |
2270 | ||
e07b1aa8 | 2271 | imask = sky2_read32(hw, B0_IMSK); |
6b1a3aef | 2272 | sky2_write32(hw, B0_IMSK, 0); |
2273 | ||
018d1c66 | 2274 | dev->trans_start = jiffies; /* prevent tx timeout */ |
bea3348e | 2275 | napi_disable(&hw->napi); |
df01093b | 2276 | netif_tx_disable(dev); |
018d1c66 | 2277 | |
e07b1aa8 SH |
2278 | synchronize_irq(hw->pdev->irq); |
2279 | ||
39dbd958 | 2280 | if (!(hw->flags & SKY2_HW_RAM_BUFFER)) |
69161611 | 2281 | sky2_set_tx_stfwd(hw, port); |
b628ed98 SH |
2282 | |
2283 | ctl = gma_read16(hw, port, GM_GP_CTRL); | |
2284 | gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
6b1a3aef | 2285 | sky2_rx_stop(sky2); |
2286 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
2287 | |
2288 | dev->mtu = new_mtu; | |
f5d64037 | 2289 | netdev_update_features(dev); |
14d0263f | 2290 | |
6b1a3aef | 2291 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
2292 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
2293 | ||
2294 | if (dev->mtu > ETH_DATA_LEN) | |
2295 | mode |= GM_SMOD_JUMBO_ENA; | |
2296 | ||
b628ed98 | 2297 | gma_write16(hw, port, GM_SERIAL_MODE, mode); |
cd28ab6a | 2298 | |
b628ed98 | 2299 | sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 2300 | |
200ac492 MM |
2301 | err = sky2_alloc_rx_skbs(sky2); |
2302 | if (!err) | |
2303 | sky2_rx_start(sky2); | |
2304 | else | |
2305 | sky2_rx_clean(sky2); | |
e07b1aa8 | 2306 | sky2_write32(hw, B0_IMSK, imask); |
018d1c66 | 2307 | |
d1d08d12 | 2308 | sky2_read32(hw, B0_Y2_SP_LISR); |
bea3348e SH |
2309 | napi_enable(&hw->napi); |
2310 | ||
1b537565 SH |
2311 | if (err) |
2312 | dev_close(dev); | |
2313 | else { | |
b628ed98 | 2314 | gma_write16(hw, port, GM_GP_CTRL, ctl); |
1b537565 | 2315 | |
1b537565 SH |
2316 | netif_wake_queue(dev); |
2317 | } | |
2318 | ||
cd28ab6a SH |
2319 | return err; |
2320 | } | |
2321 | ||
14d0263f SH |
2322 | /* For small just reuse existing skb for next receive */ |
2323 | static struct sk_buff *receive_copy(struct sky2_port *sky2, | |
2324 | const struct rx_ring_info *re, | |
2325 | unsigned length) | |
2326 | { | |
2327 | struct sk_buff *skb; | |
2328 | ||
89d71a66 | 2329 | skb = netdev_alloc_skb_ip_align(sky2->netdev, length); |
14d0263f | 2330 | if (likely(skb)) { |
14d0263f SH |
2331 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, |
2332 | length, PCI_DMA_FROMDEVICE); | |
d626f62b | 2333 | skb_copy_from_linear_data(re->skb, skb->data, length); |
14d0263f SH |
2334 | skb->ip_summed = re->skb->ip_summed; |
2335 | skb->csum = re->skb->csum; | |
2336 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, | |
2337 | length, PCI_DMA_FROMDEVICE); | |
2338 | re->skb->ip_summed = CHECKSUM_NONE; | |
489b10c1 | 2339 | skb_put(skb, length); |
14d0263f SH |
2340 | } |
2341 | return skb; | |
2342 | } | |
2343 | ||
2344 | /* Adjust length of skb with fragments to match received data */ | |
2345 | static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, | |
2346 | unsigned int length) | |
2347 | { | |
2348 | int i, num_frags; | |
2349 | unsigned int size; | |
2350 | ||
2351 | /* put header into skb */ | |
2352 | size = min(length, hdr_space); | |
2353 | skb->tail += size; | |
2354 | skb->len += size; | |
2355 | length -= size; | |
2356 | ||
2357 | num_frags = skb_shinfo(skb)->nr_frags; | |
2358 | for (i = 0; i < num_frags; i++) { | |
2359 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2360 | ||
2361 | if (length == 0) { | |
2362 | /* don't need this page */ | |
2363 | __free_page(frag->page); | |
2364 | --skb_shinfo(skb)->nr_frags; | |
2365 | } else { | |
2366 | size = min(length, (unsigned) PAGE_SIZE); | |
2367 | ||
2368 | frag->size = size; | |
2369 | skb->data_len += size; | |
2370 | skb->truesize += size; | |
2371 | skb->len += size; | |
2372 | length -= size; | |
2373 | } | |
2374 | } | |
2375 | } | |
2376 | ||
2377 | /* Normal packet - take skb from ring element and put in a new one */ | |
2378 | static struct sk_buff *receive_new(struct sky2_port *sky2, | |
2379 | struct rx_ring_info *re, | |
2380 | unsigned int length) | |
2381 | { | |
3fbd9187 | 2382 | struct sk_buff *skb; |
2383 | struct rx_ring_info nre; | |
14d0263f SH |
2384 | unsigned hdr_space = sky2->rx_data_size; |
2385 | ||
3fbd9187 | 2386 | nre.skb = sky2_rx_alloc(sky2); |
2387 | if (unlikely(!nre.skb)) | |
2388 | goto nobuf; | |
2389 | ||
2390 | if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) | |
2391 | goto nomap; | |
14d0263f SH |
2392 | |
2393 | skb = re->skb; | |
2394 | sky2_rx_unmap_skb(sky2->hw->pdev, re); | |
14d0263f | 2395 | prefetch(skb->data); |
3fbd9187 | 2396 | *re = nre; |
14d0263f SH |
2397 | |
2398 | if (skb_shinfo(skb)->nr_frags) | |
2399 | skb_put_frags(skb, hdr_space, length); | |
2400 | else | |
489b10c1 | 2401 | skb_put(skb, length); |
14d0263f | 2402 | return skb; |
3fbd9187 | 2403 | |
2404 | nomap: | |
2405 | dev_kfree_skb(nre.skb); | |
2406 | nobuf: | |
2407 | return NULL; | |
14d0263f SH |
2408 | } |
2409 | ||
cd28ab6a SH |
2410 | /* |
2411 | * Receive one packet. | |
d571b694 | 2412 | * For larger packets, get new buffer. |
cd28ab6a | 2413 | */ |
497d7c86 | 2414 | static struct sk_buff *sky2_receive(struct net_device *dev, |
cd28ab6a SH |
2415 | u16 length, u32 status) |
2416 | { | |
497d7c86 | 2417 | struct sky2_port *sky2 = netdev_priv(dev); |
291ea614 | 2418 | struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 2419 | struct sk_buff *skb = NULL; |
d6532232 SH |
2420 | u16 count = (status & GMR_FS_LEN) >> 16; |
2421 | ||
86aa7785 SH |
2422 | if (status & GMR_FS_VLAN) |
2423 | count -= VLAN_HLEN; /* Account for vlan tag */ | |
cd28ab6a | 2424 | |
6c35abae JP |
2425 | netif_printk(sky2, rx_status, KERN_DEBUG, dev, |
2426 | "rx slot %u status 0x%x len %d\n", | |
2427 | sky2->rx_next, status, length); | |
cd28ab6a | 2428 | |
793b883e | 2429 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
d70cd51a | 2430 | prefetch(sky2->rx_ring + sky2->rx_next); |
cd28ab6a | 2431 | |
3b12e014 SH |
2432 | /* This chip has hardware problems that generates bogus status. |
2433 | * So do only marginal checking and expect higher level protocols | |
2434 | * to handle crap frames. | |
2435 | */ | |
2436 | if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && | |
2437 | sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && | |
2438 | length != count) | |
2439 | goto okay; | |
2440 | ||
42eeea01 | 2441 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
2442 | goto error; |
2443 | ||
42eeea01 | 2444 | if (!(status & GMR_FS_RX_OK)) |
2445 | goto resubmit; | |
2446 | ||
d6532232 SH |
2447 | /* if length reported by DMA does not match PHY, packet was truncated */ |
2448 | if (length != count) | |
0885a30b | 2449 | goto error; |
71749531 | 2450 | |
3b12e014 | 2451 | okay: |
14d0263f SH |
2452 | if (length < copybreak) |
2453 | skb = receive_copy(sky2, re, length); | |
2454 | else | |
2455 | skb = receive_new(sky2, re, length); | |
90c30335 SH |
2456 | |
2457 | dev->stats.rx_dropped += (skb == NULL); | |
2458 | ||
793b883e | 2459 | resubmit: |
14d0263f | 2460 | sky2_rx_submit(sky2, re); |
79e57d32 | 2461 | |
cd28ab6a SH |
2462 | return skb; |
2463 | ||
2464 | error: | |
7138a0f5 | 2465 | ++dev->stats.rx_errors; |
6e15b712 | 2466 | |
6c35abae JP |
2467 | if (net_ratelimit()) |
2468 | netif_info(sky2, rx_err, dev, | |
2469 | "rx error, status 0x%x length %d\n", status, length); | |
793b883e | 2470 | |
793b883e | 2471 | goto resubmit; |
cd28ab6a SH |
2472 | } |
2473 | ||
e07b1aa8 SH |
2474 | /* Transmit complete */ |
2475 | static inline void sky2_tx_done(struct net_device *dev, u16 last) | |
13b97b74 | 2476 | { |
e07b1aa8 | 2477 | struct sky2_port *sky2 = netdev_priv(dev); |
302d1252 | 2478 | |
8a0c9228 | 2479 | if (netif_running(dev)) { |
e07b1aa8 | 2480 | sky2_tx_complete(sky2, last); |
8a0c9228 MM |
2481 | |
2482 | /* Wake unless it's detached, and called e.g. from sky2_down() */ | |
2483 | if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) | |
2484 | netif_wake_queue(dev); | |
2485 | } | |
cd28ab6a SH |
2486 | } |
2487 | ||
37e5a243 SH |
2488 | static inline void sky2_skb_rx(const struct sky2_port *sky2, |
2489 | u32 status, struct sk_buff *skb) | |
2490 | { | |
86aa7785 SH |
2491 | if (status & GMR_FS_VLAN) |
2492 | __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag)); | |
2493 | ||
37e5a243 SH |
2494 | if (skb->ip_summed == CHECKSUM_NONE) |
2495 | netif_receive_skb(skb); | |
2496 | else | |
2497 | napi_gro_receive(&sky2->hw->napi, skb); | |
2498 | } | |
2499 | ||
bf15fe99 SH |
2500 | static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, |
2501 | unsigned packets, unsigned bytes) | |
2502 | { | |
0885a30b | 2503 | struct net_device *dev = hw->dev[port]; |
2504 | struct sky2_port *sky2 = netdev_priv(dev); | |
bf15fe99 | 2505 | |
0885a30b | 2506 | if (packets == 0) |
2507 | return; | |
2508 | ||
2509 | u64_stats_update_begin(&sky2->rx_stats.syncp); | |
2510 | sky2->rx_stats.packets += packets; | |
2511 | sky2->rx_stats.bytes += bytes; | |
2512 | u64_stats_update_end(&sky2->rx_stats.syncp); | |
2513 | ||
2514 | dev->last_rx = jiffies; | |
2515 | sky2_rx_update(netdev_priv(dev), rxqaddr[port]); | |
bf15fe99 SH |
2516 | } |
2517 | ||
375c5688 | 2518 | static void sky2_rx_checksum(struct sky2_port *sky2, u32 status) |
2519 | { | |
2520 | /* If this happens then driver assuming wrong format for chip type */ | |
2521 | BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); | |
2522 | ||
2523 | /* Both checksum counters are programmed to start at | |
2524 | * the same offset, so unless there is a problem they | |
2525 | * should match. This failure is an early indication that | |
2526 | * hardware receive checksumming won't work. | |
2527 | */ | |
2528 | if (likely((u16)(status >> 16) == (u16)status)) { | |
2529 | struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb; | |
2530 | skb->ip_summed = CHECKSUM_COMPLETE; | |
2531 | skb->csum = le16_to_cpu(status); | |
2532 | } else { | |
2533 | dev_notice(&sky2->hw->pdev->dev, | |
2534 | "%s: receive checksum problem (status = %#x)\n", | |
2535 | sky2->netdev->name, status); | |
2536 | ||
f5d64037 MM |
2537 | /* Disable checksum offload |
2538 | * It will be reenabled on next ndo_set_features, but if it's | |
2539 | * really broken, will get disabled again | |
2540 | */ | |
2541 | sky2->netdev->features &= ~NETIF_F_RXCSUM; | |
375c5688 | 2542 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2543 | BMU_DIS_RX_CHKSUM); | |
2544 | } | |
2545 | } | |
2546 | ||
bf73130d SH |
2547 | static void sky2_rx_hash(struct sky2_port *sky2, u32 status) |
2548 | { | |
2549 | struct sk_buff *skb; | |
2550 | ||
2551 | skb = sky2->rx_ring[sky2->rx_next].skb; | |
2552 | skb->rxhash = le32_to_cpu(status); | |
2553 | } | |
2554 | ||
e07b1aa8 | 2555 | /* Process status response ring */ |
26691830 | 2556 | static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) |
cd28ab6a | 2557 | { |
e07b1aa8 | 2558 | int work_done = 0; |
bf15fe99 SH |
2559 | unsigned int total_bytes[2] = { 0 }; |
2560 | unsigned int total_packets[2] = { 0 }; | |
a8fd6266 | 2561 | |
af2a58ac | 2562 | rmb(); |
26691830 | 2563 | do { |
55c9dd35 | 2564 | struct sky2_port *sky2; |
13210ce5 | 2565 | struct sky2_status_le *le = hw->st_le + hw->st_idx; |
ab5adecb | 2566 | unsigned port; |
13210ce5 | 2567 | struct net_device *dev; |
cd28ab6a | 2568 | struct sk_buff *skb; |
cd28ab6a SH |
2569 | u32 status; |
2570 | u16 length; | |
ab5adecb SH |
2571 | u8 opcode = le->opcode; |
2572 | ||
2573 | if (!(opcode & HW_OWNER)) | |
2574 | break; | |
cd28ab6a | 2575 | |
efe91932 | 2576 | hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); |
bea86103 | 2577 | |
ab5adecb | 2578 | port = le->css & CSS_LINK_BIT; |
69161611 | 2579 | dev = hw->dev[port]; |
13210ce5 | 2580 | sky2 = netdev_priv(dev); |
f65b138c SH |
2581 | length = le16_to_cpu(le->length); |
2582 | status = le32_to_cpu(le->status); | |
cd28ab6a | 2583 | |
ab5adecb SH |
2584 | le->opcode = 0; |
2585 | switch (opcode & ~HW_OWNER) { | |
cd28ab6a | 2586 | case OP_RXSTAT: |
bf15fe99 SH |
2587 | total_packets[port]++; |
2588 | total_bytes[port] += length; | |
90c30335 | 2589 | |
497d7c86 | 2590 | skb = sky2_receive(dev, length, status); |
90c30335 | 2591 | if (!skb) |
55c9dd35 | 2592 | break; |
13210ce5 | 2593 | |
69161611 | 2594 | /* This chip reports checksum status differently */ |
05745c4a | 2595 | if (hw->flags & SKY2_HW_NEW_LE) { |
f5d64037 | 2596 | if ((dev->features & NETIF_F_RXCSUM) && |
69161611 SH |
2597 | (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && |
2598 | (le->css & CSS_TCPUDPCSOK)) | |
2599 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
2600 | else | |
2601 | skb->ip_summed = CHECKSUM_NONE; | |
2602 | } | |
2603 | ||
13210ce5 | 2604 | skb->protocol = eth_type_trans(skb, dev); |
13210ce5 | 2605 | |
37e5a243 | 2606 | sky2_skb_rx(sky2, status, skb); |
13210ce5 | 2607 | |
22e11703 | 2608 | /* Stop after net poll weight */ |
13210ce5 | 2609 | if (++work_done >= to_do) |
2610 | goto exit_loop; | |
cd28ab6a SH |
2611 | break; |
2612 | ||
d1f13708 | 2613 | case OP_RXVLAN: |
2614 | sky2->rx_tag = length; | |
2615 | break; | |
2616 | ||
2617 | case OP_RXCHKSVLAN: | |
2618 | sky2->rx_tag = length; | |
2619 | /* fall through */ | |
cd28ab6a | 2620 | case OP_RXCHKS: |
f5d64037 | 2621 | if (likely(dev->features & NETIF_F_RXCSUM)) |
375c5688 | 2622 | sky2_rx_checksum(sky2, status); |
cd28ab6a SH |
2623 | break; |
2624 | ||
bf73130d SH |
2625 | case OP_RSS_HASH: |
2626 | sky2_rx_hash(sky2, status); | |
2627 | break; | |
2628 | ||
cd28ab6a | 2629 | case OP_TXINDEXLE: |
13b97b74 | 2630 | /* TX index reports status for both ports */ |
f55925d7 | 2631 | sky2_tx_done(hw->dev[0], status & 0xfff); |
e07b1aa8 SH |
2632 | if (hw->dev[1]) |
2633 | sky2_tx_done(hw->dev[1], | |
2634 | ((status >> 24) & 0xff) | |
2635 | | (u16)(length & 0xf) << 8); | |
cd28ab6a SH |
2636 | break; |
2637 | ||
cd28ab6a SH |
2638 | default: |
2639 | if (net_ratelimit()) | |
ada1db5c | 2640 | pr_warning("unknown status opcode 0x%x\n", opcode); |
cd28ab6a | 2641 | } |
26691830 | 2642 | } while (hw->st_idx != idx); |
cd28ab6a | 2643 | |
fe2a24df SH |
2644 | /* Fully processed status ring so clear irq */ |
2645 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); | |
2646 | ||
13210ce5 | 2647 | exit_loop: |
bf15fe99 SH |
2648 | sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); |
2649 | sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); | |
22e11703 | 2650 | |
e07b1aa8 | 2651 | return work_done; |
cd28ab6a SH |
2652 | } |
2653 | ||
2654 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
2655 | { | |
2656 | struct net_device *dev = hw->dev[port]; | |
2657 | ||
3be92a70 | 2658 | if (net_ratelimit()) |
ada1db5c | 2659 | netdev_info(dev, "hw error interrupt status 0x%x\n", status); |
cd28ab6a SH |
2660 | |
2661 | if (status & Y2_IS_PAR_RD1) { | |
3be92a70 | 2662 | if (net_ratelimit()) |
ada1db5c | 2663 | netdev_err(dev, "ram data read parity error\n"); |
cd28ab6a SH |
2664 | /* Clear IRQ */ |
2665 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
2666 | } | |
2667 | ||
2668 | if (status & Y2_IS_PAR_WR1) { | |
3be92a70 | 2669 | if (net_ratelimit()) |
ada1db5c | 2670 | netdev_err(dev, "ram data write parity error\n"); |
cd28ab6a SH |
2671 | |
2672 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
2673 | } | |
2674 | ||
2675 | if (status & Y2_IS_PAR_MAC1) { | |
3be92a70 | 2676 | if (net_ratelimit()) |
ada1db5c | 2677 | netdev_err(dev, "MAC parity error\n"); |
cd28ab6a SH |
2678 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); |
2679 | } | |
2680 | ||
2681 | if (status & Y2_IS_PAR_RX1) { | |
3be92a70 | 2682 | if (net_ratelimit()) |
ada1db5c | 2683 | netdev_err(dev, "RX parity error\n"); |
cd28ab6a SH |
2684 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); |
2685 | } | |
2686 | ||
2687 | if (status & Y2_IS_TCP_TXA1) { | |
3be92a70 | 2688 | if (net_ratelimit()) |
ada1db5c | 2689 | netdev_err(dev, "TCP segmentation error\n"); |
cd28ab6a SH |
2690 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); |
2691 | } | |
2692 | } | |
2693 | ||
2694 | static void sky2_hw_intr(struct sky2_hw *hw) | |
2695 | { | |
555382cb | 2696 | struct pci_dev *pdev = hw->pdev; |
cd28ab6a | 2697 | u32 status = sky2_read32(hw, B0_HWE_ISRC); |
555382cb SH |
2698 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); |
2699 | ||
2700 | status &= hwmsk; | |
cd28ab6a | 2701 | |
793b883e | 2702 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 2703 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2704 | |
2705 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
2706 | u16 pci_err; |
2707 | ||
a40ccc68 | 2708 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
b32f40c4 | 2709 | pci_err = sky2_pci_read16(hw, PCI_STATUS); |
3be92a70 | 2710 | if (net_ratelimit()) |
555382cb | 2711 | dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", |
b02a9258 | 2712 | pci_err); |
cd28ab6a | 2713 | |
b32f40c4 | 2714 | sky2_pci_write16(hw, PCI_STATUS, |
167f53d0 | 2715 | pci_err | PCI_STATUS_ERROR_BITS); |
a40ccc68 | 2716 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
cd28ab6a SH |
2717 | } |
2718 | ||
2719 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 2720 | /* PCI-Express uncorrectable Error occurred */ |
555382cb | 2721 | u32 err; |
cd28ab6a | 2722 | |
a40ccc68 | 2723 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
7782c8c4 SH |
2724 | err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); |
2725 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, | |
2726 | 0xfffffffful); | |
3be92a70 | 2727 | if (net_ratelimit()) |
555382cb | 2728 | dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); |
cf06ffb4 | 2729 | |
7782c8c4 | 2730 | sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); |
a40ccc68 | 2731 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
cd28ab6a SH |
2732 | } |
2733 | ||
2734 | if (status & Y2_HWE_L1_MASK) | |
2735 | sky2_hw_error(hw, 0, status); | |
2736 | status >>= 8; | |
2737 | if (status & Y2_HWE_L1_MASK) | |
2738 | sky2_hw_error(hw, 1, status); | |
2739 | } | |
2740 | ||
2741 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
2742 | { | |
2743 | struct net_device *dev = hw->dev[port]; | |
2744 | struct sky2_port *sky2 = netdev_priv(dev); | |
2745 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
2746 | ||
6c35abae | 2747 | netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status); |
cd28ab6a | 2748 | |
a3caeada SH |
2749 | if (status & GM_IS_RX_CO_OV) |
2750 | gma_read16(hw, port, GM_RX_IRQ_SRC); | |
2751 | ||
2752 | if (status & GM_IS_TX_CO_OV) | |
2753 | gma_read16(hw, port, GM_TX_IRQ_SRC); | |
2754 | ||
cd28ab6a | 2755 | if (status & GM_IS_RX_FF_OR) { |
7138a0f5 | 2756 | ++dev->stats.rx_fifo_errors; |
cd28ab6a SH |
2757 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); |
2758 | } | |
2759 | ||
2760 | if (status & GM_IS_TX_FF_UR) { | |
7138a0f5 | 2761 | ++dev->stats.tx_fifo_errors; |
cd28ab6a SH |
2762 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); |
2763 | } | |
cd28ab6a SH |
2764 | } |
2765 | ||
40b01727 | 2766 | /* This should never happen it is a bug. */ |
c119731d | 2767 | static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) |
d257924e SH |
2768 | { |
2769 | struct net_device *dev = hw->dev[port]; | |
c119731d | 2770 | u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); |
d257924e | 2771 | |
ada1db5c | 2772 | dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", |
c119731d SH |
2773 | dev->name, (unsigned) q, (unsigned) idx, |
2774 | (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); | |
d257924e | 2775 | |
40b01727 | 2776 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); |
d257924e | 2777 | } |
cd28ab6a | 2778 | |
75e80683 SH |
2779 | static int sky2_rx_hung(struct net_device *dev) |
2780 | { | |
2781 | struct sky2_port *sky2 = netdev_priv(dev); | |
2782 | struct sky2_hw *hw = sky2->hw; | |
2783 | unsigned port = sky2->port; | |
2784 | unsigned rxq = rxqaddr[port]; | |
2785 | u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); | |
2786 | u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); | |
2787 | u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); | |
2788 | u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); | |
2789 | ||
2790 | /* If idle and MAC or PCI is stuck */ | |
2791 | if (sky2->check.last == dev->last_rx && | |
2792 | ((mac_rp == sky2->check.mac_rp && | |
2793 | mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || | |
2794 | /* Check if the PCI RX hang */ | |
2795 | (fifo_rp == sky2->check.fifo_rp && | |
2796 | fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { | |
ada1db5c JP |
2797 | netdev_printk(KERN_DEBUG, dev, |
2798 | "hung mac %d:%d fifo %d (%d:%d)\n", | |
2799 | mac_lev, mac_rp, fifo_lev, | |
2800 | fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); | |
75e80683 SH |
2801 | return 1; |
2802 | } else { | |
2803 | sky2->check.last = dev->last_rx; | |
2804 | sky2->check.mac_rp = mac_rp; | |
2805 | sky2->check.mac_lev = mac_lev; | |
2806 | sky2->check.fifo_rp = fifo_rp; | |
2807 | sky2->check.fifo_lev = fifo_lev; | |
2808 | return 0; | |
2809 | } | |
2810 | } | |
2811 | ||
32c2c300 | 2812 | static void sky2_watchdog(unsigned long arg) |
d27ed387 | 2813 | { |
01bd7564 | 2814 | struct sky2_hw *hw = (struct sky2_hw *) arg; |
d27ed387 | 2815 | |
75e80683 | 2816 | /* Check for lost IRQ once a second */ |
32c2c300 | 2817 | if (sky2_read32(hw, B0_ISRC)) { |
bea3348e | 2818 | napi_schedule(&hw->napi); |
75e80683 SH |
2819 | } else { |
2820 | int i, active = 0; | |
2821 | ||
2822 | for (i = 0; i < hw->ports; i++) { | |
bea3348e | 2823 | struct net_device *dev = hw->dev[i]; |
75e80683 SH |
2824 | if (!netif_running(dev)) |
2825 | continue; | |
2826 | ++active; | |
2827 | ||
2828 | /* For chips with Rx FIFO, check if stuck */ | |
39dbd958 | 2829 | if ((hw->flags & SKY2_HW_RAM_BUFFER) && |
75e80683 | 2830 | sky2_rx_hung(dev)) { |
ada1db5c | 2831 | netdev_info(dev, "receiver hang detected\n"); |
75e80683 SH |
2832 | schedule_work(&hw->restart_work); |
2833 | return; | |
2834 | } | |
2835 | } | |
2836 | ||
2837 | if (active == 0) | |
2838 | return; | |
32c2c300 | 2839 | } |
01bd7564 | 2840 | |
75e80683 | 2841 | mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); |
d27ed387 SH |
2842 | } |
2843 | ||
40b01727 SH |
2844 | /* Hardware/software error handling */ |
2845 | static void sky2_err_intr(struct sky2_hw *hw, u32 status) | |
cd28ab6a | 2846 | { |
40b01727 SH |
2847 | if (net_ratelimit()) |
2848 | dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); | |
cd28ab6a | 2849 | |
1e5f1283 SH |
2850 | if (status & Y2_IS_HW_ERR) |
2851 | sky2_hw_intr(hw); | |
d257924e | 2852 | |
1e5f1283 SH |
2853 | if (status & Y2_IS_IRQ_MAC1) |
2854 | sky2_mac_intr(hw, 0); | |
cd28ab6a | 2855 | |
1e5f1283 SH |
2856 | if (status & Y2_IS_IRQ_MAC2) |
2857 | sky2_mac_intr(hw, 1); | |
cd28ab6a | 2858 | |
1e5f1283 | 2859 | if (status & Y2_IS_CHK_RX1) |
c119731d | 2860 | sky2_le_error(hw, 0, Q_R1); |
d257924e | 2861 | |
1e5f1283 | 2862 | if (status & Y2_IS_CHK_RX2) |
c119731d | 2863 | sky2_le_error(hw, 1, Q_R2); |
d257924e | 2864 | |
1e5f1283 | 2865 | if (status & Y2_IS_CHK_TXA1) |
c119731d | 2866 | sky2_le_error(hw, 0, Q_XA1); |
d257924e | 2867 | |
1e5f1283 | 2868 | if (status & Y2_IS_CHK_TXA2) |
c119731d | 2869 | sky2_le_error(hw, 1, Q_XA2); |
40b01727 SH |
2870 | } |
2871 | ||
bea3348e | 2872 | static int sky2_poll(struct napi_struct *napi, int work_limit) |
40b01727 | 2873 | { |
bea3348e | 2874 | struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); |
40b01727 | 2875 | u32 status = sky2_read32(hw, B0_Y2_SP_EISR); |
6f535763 | 2876 | int work_done = 0; |
26691830 | 2877 | u16 idx; |
40b01727 SH |
2878 | |
2879 | if (unlikely(status & Y2_IS_ERROR)) | |
2880 | sky2_err_intr(hw, status); | |
2881 | ||
2882 | if (status & Y2_IS_IRQ_PHY1) | |
2883 | sky2_phy_intr(hw, 0); | |
2884 | ||
2885 | if (status & Y2_IS_IRQ_PHY2) | |
2886 | sky2_phy_intr(hw, 1); | |
cd28ab6a | 2887 | |
0f5aac70 SH |
2888 | if (status & Y2_IS_PHY_QLNK) |
2889 | sky2_qlink_intr(hw); | |
2890 | ||
26691830 SH |
2891 | while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { |
2892 | work_done += sky2_status_intr(hw, work_limit - work_done, idx); | |
6f535763 DM |
2893 | |
2894 | if (work_done >= work_limit) | |
26691830 SH |
2895 | goto done; |
2896 | } | |
6f535763 | 2897 | |
26691830 SH |
2898 | napi_complete(napi); |
2899 | sky2_read32(hw, B0_Y2_SP_LISR); | |
2900 | done: | |
6f535763 | 2901 | |
bea3348e | 2902 | return work_done; |
e07b1aa8 SH |
2903 | } |
2904 | ||
7d12e780 | 2905 | static irqreturn_t sky2_intr(int irq, void *dev_id) |
e07b1aa8 SH |
2906 | { |
2907 | struct sky2_hw *hw = dev_id; | |
e07b1aa8 SH |
2908 | u32 status; |
2909 | ||
2910 | /* Reading this mask interrupts as side effect */ | |
2911 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
2912 | if (status == 0 || status == ~0) | |
2913 | return IRQ_NONE; | |
793b883e | 2914 | |
e07b1aa8 | 2915 | prefetch(&hw->st_le[hw->st_idx]); |
bea3348e SH |
2916 | |
2917 | napi_schedule(&hw->napi); | |
793b883e | 2918 | |
cd28ab6a SH |
2919 | return IRQ_HANDLED; |
2920 | } | |
2921 | ||
2922 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2923 | static void sky2_netpoll(struct net_device *dev) | |
2924 | { | |
2925 | struct sky2_port *sky2 = netdev_priv(dev); | |
2926 | ||
bea3348e | 2927 | napi_schedule(&sky2->hw->napi); |
cd28ab6a SH |
2928 | } |
2929 | #endif | |
2930 | ||
2931 | /* Chip internal frequency for clock calculations */ | |
05745c4a | 2932 | static u32 sky2_mhz(const struct sky2_hw *hw) |
cd28ab6a | 2933 | { |
793b883e | 2934 | switch (hw->chip_id) { |
cd28ab6a | 2935 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 2936 | case CHIP_ID_YUKON_EC_U: |
93745494 | 2937 | case CHIP_ID_YUKON_EX: |
ed4d4161 | 2938 | case CHIP_ID_YUKON_SUPR: |
0ce8b98d | 2939 | case CHIP_ID_YUKON_UL_2: |
0f5aac70 | 2940 | case CHIP_ID_YUKON_OPT: |
05745c4a SH |
2941 | return 125; |
2942 | ||
cd28ab6a | 2943 | case CHIP_ID_YUKON_FE: |
05745c4a SH |
2944 | return 100; |
2945 | ||
2946 | case CHIP_ID_YUKON_FE_P: | |
2947 | return 50; | |
2948 | ||
2949 | case CHIP_ID_YUKON_XL: | |
2950 | return 156; | |
2951 | ||
2952 | default: | |
2953 | BUG(); | |
cd28ab6a SH |
2954 | } |
2955 | } | |
2956 | ||
fb17358f | 2957 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
cd28ab6a | 2958 | { |
fb17358f | 2959 | return sky2_mhz(hw) * us; |
cd28ab6a SH |
2960 | } |
2961 | ||
fb17358f | 2962 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
cd28ab6a | 2963 | { |
fb17358f | 2964 | return clk / sky2_mhz(hw); |
cd28ab6a SH |
2965 | } |
2966 | ||
fb17358f | 2967 | |
e3173832 | 2968 | static int __devinit sky2_init(struct sky2_hw *hw) |
cd28ab6a | 2969 | { |
b89165f2 | 2970 | u8 t8; |
cd28ab6a | 2971 | |
167f53d0 | 2972 | /* Enable all clocks and check for bad PCI access */ |
b32f40c4 | 2973 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
451af335 | 2974 | |
cd28ab6a | 2975 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
08c06d8a | 2976 | |
cd28ab6a | 2977 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); |
ea76e635 SH |
2978 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; |
2979 | ||
060b946c | 2980 | switch (hw->chip_id) { |
ea76e635 | 2981 | case CHIP_ID_YUKON_XL: |
39dbd958 | 2982 | hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; |
bf73130d SH |
2983 | if (hw->chip_rev < CHIP_REV_YU_XL_A2) |
2984 | hw->flags |= SKY2_HW_RSS_BROKEN; | |
ea76e635 SH |
2985 | break; |
2986 | ||
2987 | case CHIP_ID_YUKON_EC_U: | |
2988 | hw->flags = SKY2_HW_GIGABIT | |
2989 | | SKY2_HW_NEWER_PHY | |
2990 | | SKY2_HW_ADV_POWER_CTL; | |
2991 | break; | |
2992 | ||
2993 | case CHIP_ID_YUKON_EX: | |
2994 | hw->flags = SKY2_HW_GIGABIT | |
2995 | | SKY2_HW_NEWER_PHY | |
2996 | | SKY2_HW_NEW_LE | |
2997 | | SKY2_HW_ADV_POWER_CTL; | |
2998 | ||
2999 | /* New transmit checksum */ | |
3000 | if (hw->chip_rev != CHIP_REV_YU_EX_B0) | |
3001 | hw->flags |= SKY2_HW_AUTO_TX_SUM; | |
3002 | break; | |
3003 | ||
3004 | case CHIP_ID_YUKON_EC: | |
3005 | /* This rev is really old, and requires untested workarounds */ | |
3006 | if (hw->chip_rev == CHIP_REV_YU_EC_A1) { | |
3007 | dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); | |
3008 | return -EOPNOTSUPP; | |
3009 | } | |
bf73130d | 3010 | hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; |
ea76e635 SH |
3011 | break; |
3012 | ||
3013 | case CHIP_ID_YUKON_FE: | |
bf73130d | 3014 | hw->flags = SKY2_HW_RSS_BROKEN; |
ea76e635 SH |
3015 | break; |
3016 | ||
05745c4a SH |
3017 | case CHIP_ID_YUKON_FE_P: |
3018 | hw->flags = SKY2_HW_NEWER_PHY | |
3019 | | SKY2_HW_NEW_LE | |
3020 | | SKY2_HW_AUTO_TX_SUM | |
3021 | | SKY2_HW_ADV_POWER_CTL; | |
86aa7785 SH |
3022 | |
3023 | /* The workaround for status conflicts VLAN tag detection. */ | |
3024 | if (hw->chip_rev == CHIP_REV_YU_FE2_A0) | |
3025 | hw->flags |= SKY2_HW_VLAN_BROKEN; | |
05745c4a | 3026 | break; |
ed4d4161 SH |
3027 | |
3028 | case CHIP_ID_YUKON_SUPR: | |
3029 | hw->flags = SKY2_HW_GIGABIT | |
3030 | | SKY2_HW_NEWER_PHY | |
3031 | | SKY2_HW_NEW_LE | |
3032 | | SKY2_HW_AUTO_TX_SUM | |
3033 | | SKY2_HW_ADV_POWER_CTL; | |
3034 | break; | |
3035 | ||
0ce8b98d | 3036 | case CHIP_ID_YUKON_UL_2: |
b338682d TI |
3037 | hw->flags = SKY2_HW_GIGABIT |
3038 | | SKY2_HW_ADV_POWER_CTL; | |
3039 | break; | |
3040 | ||
0f5aac70 | 3041 | case CHIP_ID_YUKON_OPT: |
0ce8b98d | 3042 | hw->flags = SKY2_HW_GIGABIT |
b338682d | 3043 | | SKY2_HW_NEW_LE |
0ce8b98d SH |
3044 | | SKY2_HW_ADV_POWER_CTL; |
3045 | break; | |
3046 | ||
ea76e635 | 3047 | default: |
b02a9258 SH |
3048 | dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", |
3049 | hw->chip_id); | |
cd28ab6a SH |
3050 | return -EOPNOTSUPP; |
3051 | } | |
3052 | ||
ea76e635 SH |
3053 | hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); |
3054 | if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') | |
3055 | hw->flags |= SKY2_HW_FIBRE_PHY; | |
290d4de5 | 3056 | |
e3173832 SH |
3057 | hw->ports = 1; |
3058 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
3059 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
3060 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
3061 | ++hw->ports; | |
3062 | } | |
3063 | ||
74a61ebf MM |
3064 | if (sky2_read8(hw, B2_E_0)) |
3065 | hw->flags |= SKY2_HW_RAM_BUFFER; | |
3066 | ||
e3173832 SH |
3067 | return 0; |
3068 | } | |
3069 | ||
3070 | static void sky2_reset(struct sky2_hw *hw) | |
3071 | { | |
555382cb | 3072 | struct pci_dev *pdev = hw->pdev; |
e3173832 | 3073 | u16 status; |
555382cb SH |
3074 | int i, cap; |
3075 | u32 hwe_mask = Y2_HWE_ALL_MASK; | |
e3173832 | 3076 | |
cd28ab6a | 3077 | /* disable ASF */ |
acd12dde | 3078 | if (hw->chip_id == CHIP_ID_YUKON_EX |
3079 | || hw->chip_id == CHIP_ID_YUKON_SUPR) { | |
3080 | sky2_write32(hw, CPU_WDOG, 0); | |
4f44d8ba SH |
3081 | status = sky2_read16(hw, HCU_CCSR); |
3082 | status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | | |
3083 | HCU_CCSR_UC_STATE_MSK); | |
acd12dde | 3084 | /* |
3085 | * CPU clock divider shouldn't be used because | |
3086 | * - ASF firmware may malfunction | |
3087 | * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks | |
3088 | */ | |
3089 | status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK; | |
4f44d8ba | 3090 | sky2_write16(hw, HCU_CCSR, status); |
acd12dde | 3091 | sky2_write32(hw, CPU_WDOG, 0); |
4f44d8ba SH |
3092 | } else |
3093 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
3094 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
cd28ab6a SH |
3095 | |
3096 | /* do a SW reset */ | |
3097 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
3098 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
3099 | ||
ac93a394 SH |
3100 | /* allow writes to PCI config */ |
3101 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
3102 | ||
cd28ab6a | 3103 | /* clear PCI errors, if any */ |
b32f40c4 | 3104 | status = sky2_pci_read16(hw, PCI_STATUS); |
167f53d0 | 3105 | status |= PCI_STATUS_ERROR_BITS; |
b32f40c4 | 3106 | sky2_pci_write16(hw, PCI_STATUS, status); |
cd28ab6a SH |
3107 | |
3108 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
3109 | ||
555382cb SH |
3110 | cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
3111 | if (cap) { | |
7782c8c4 SH |
3112 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, |
3113 | 0xfffffffful); | |
555382cb SH |
3114 | |
3115 | /* If error bit is stuck on ignore it */ | |
3116 | if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) | |
3117 | dev_info(&pdev->dev, "ignoring stuck error report bit\n"); | |
7782c8c4 | 3118 | else |
555382cb SH |
3119 | hwe_mask |= Y2_IS_PCI_EXP; |
3120 | } | |
cd28ab6a | 3121 | |
ae306cca | 3122 | sky2_power_on(hw); |
a40ccc68 | 3123 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
cd28ab6a SH |
3124 | |
3125 | for (i = 0; i < hw->ports; i++) { | |
3126 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
3127 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
69161611 | 3128 | |
ed4d4161 SH |
3129 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
3130 | hw->chip_id == CHIP_ID_YUKON_SUPR) | |
69161611 SH |
3131 | sky2_write16(hw, SK_REG(i, GMAC_CTRL), |
3132 | GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | |
3133 | | GMC_BYP_RETR_ON); | |
877c8570 SH |
3134 | |
3135 | } | |
3136 | ||
3137 | if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { | |
3138 | /* enable MACSec clock gating */ | |
3139 | sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); | |
cd28ab6a SH |
3140 | } |
3141 | ||
0f5aac70 SH |
3142 | if (hw->chip_id == CHIP_ID_YUKON_OPT) { |
3143 | u16 reg; | |
3144 | u32 msk; | |
3145 | ||
3146 | if (hw->chip_rev == 0) { | |
3147 | /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */ | |
3148 | sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); | |
3149 | ||
3150 | /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */ | |
3151 | reg = 10; | |
3152 | } else { | |
3153 | /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */ | |
3154 | reg = 3; | |
3155 | } | |
3156 | ||
3157 | reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; | |
3158 | ||
3159 | /* reset PHY Link Detect */ | |
a40ccc68 | 3160 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
0f5aac70 SH |
3161 | sky2_pci_write16(hw, PSM_CONFIG_REG4, |
3162 | reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT); | |
3163 | sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); | |
3164 | ||
3165 | ||
3166 | /* enable PHY Quick Link */ | |
3167 | msk = sky2_read32(hw, B0_IMSK); | |
3168 | msk |= Y2_IS_PHY_QLNK; | |
3169 | sky2_write32(hw, B0_IMSK, msk); | |
3170 | ||
3171 | /* check if PSMv2 was running before */ | |
3172 | reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); | |
3173 | if (reg & PCI_EXP_LNKCTL_ASPMC) { | |
8b055431 | 3174 | cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
0f5aac70 SH |
3175 | /* restore the PCIe Link Control register */ |
3176 | sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg); | |
3177 | } | |
a40ccc68 | 3178 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
0f5aac70 SH |
3179 | |
3180 | /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ | |
3181 | sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); | |
3182 | } | |
3183 | ||
793b883e SH |
3184 | /* Clear I2C IRQ noise */ |
3185 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
3186 | |
3187 | /* turn off hardware timer (unused) */ | |
3188 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
3189 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 3190 | |
69634ee7 SH |
3191 | /* Turn off descriptor polling */ |
3192 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); | |
cd28ab6a SH |
3193 | |
3194 | /* Turn off receive timestamp */ | |
3195 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 3196 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
3197 | |
3198 | /* enable the Tx Arbiters */ | |
3199 | for (i = 0; i < hw->ports; i++) | |
3200 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
3201 | ||
3202 | /* Initialize ram interface */ | |
3203 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 3204 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
3205 | |
3206 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
3207 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
3208 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
3209 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
3210 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
3211 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
3212 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
3213 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
3214 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
3215 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
3216 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
3217 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
3218 | } | |
3219 | ||
555382cb | 3220 | sky2_write32(hw, B0_HWE_IMSK, hwe_mask); |
cd28ab6a | 3221 | |
cd28ab6a | 3222 | for (i = 0; i < hw->ports; i++) |
d3bcfbeb | 3223 | sky2_gmac_reset(hw, i); |
cd28ab6a | 3224 | |
efe91932 | 3225 | memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); |
cd28ab6a SH |
3226 | hw->st_idx = 0; |
3227 | ||
3228 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
3229 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
3230 | ||
3231 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 3232 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
3233 | |
3234 | /* Set the list last index */ | |
efe91932 | 3235 | sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); |
cd28ab6a | 3236 | |
290d4de5 SH |
3237 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
3238 | sky2_write8(hw, STAT_FIFO_WM, 16); | |
cd28ab6a | 3239 | |
290d4de5 SH |
3240 | /* set Status-FIFO ISR watermark */ |
3241 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
3242 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); | |
3243 | else | |
3244 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | |
cd28ab6a | 3245 | |
290d4de5 | 3246 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
77b3d6a2 SH |
3247 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); |
3248 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | |
cd28ab6a | 3249 | |
793b883e | 3250 | /* enable status unit */ |
cd28ab6a SH |
3251 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
3252 | ||
3253 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
3254 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
3255 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
e3173832 SH |
3256 | } |
3257 | ||
af18d8b8 SH |
3258 | /* Take device down (offline). |
3259 | * Equivalent to doing dev_stop() but this does not | |
25985edc | 3260 | * inform upper layers of the transition. |
af18d8b8 SH |
3261 | */ |
3262 | static void sky2_detach(struct net_device *dev) | |
3263 | { | |
3264 | if (netif_running(dev)) { | |
c36531b9 | 3265 | netif_tx_lock(dev); |
af18d8b8 | 3266 | netif_device_detach(dev); /* stop txq */ |
c36531b9 | 3267 | netif_tx_unlock(dev); |
af18d8b8 SH |
3268 | sky2_down(dev); |
3269 | } | |
3270 | } | |
3271 | ||
3272 | /* Bring device back after doing sky2_detach */ | |
3273 | static int sky2_reattach(struct net_device *dev) | |
3274 | { | |
3275 | int err = 0; | |
3276 | ||
3277 | if (netif_running(dev)) { | |
3278 | err = sky2_up(dev); | |
3279 | if (err) { | |
ada1db5c | 3280 | netdev_info(dev, "could not restart %d\n", err); |
af18d8b8 SH |
3281 | dev_close(dev); |
3282 | } else { | |
3283 | netif_device_attach(dev); | |
3284 | sky2_set_multicast(dev); | |
3285 | } | |
3286 | } | |
3287 | ||
3288 | return err; | |
3289 | } | |
3290 | ||
d72ff8fa | 3291 | static void sky2_all_down(struct sky2_hw *hw) |
81906791 | 3292 | { |
af18d8b8 | 3293 | int i; |
81906791 | 3294 | |
d72ff8fa | 3295 | sky2_read32(hw, B0_IMSK); |
8cfcbe99 | 3296 | sky2_write32(hw, B0_IMSK, 0); |
93135a3b MM |
3297 | synchronize_irq(hw->pdev->irq); |
3298 | napi_disable(&hw->napi); | |
8a0c9228 MM |
3299 | |
3300 | for (i = 0; i < hw->ports; i++) { | |
3301 | struct net_device *dev = hw->dev[i]; | |
3302 | struct sky2_port *sky2 = netdev_priv(dev); | |
3303 | ||
3304 | if (!netif_running(dev)) | |
3305 | continue; | |
3306 | ||
3307 | netif_carrier_off(dev); | |
3308 | netif_tx_disable(dev); | |
3309 | sky2_hw_down(sky2); | |
3310 | } | |
d72ff8fa | 3311 | } |
8a0c9228 | 3312 | |
d72ff8fa MM |
3313 | static void sky2_all_up(struct sky2_hw *hw) |
3314 | { | |
3315 | u32 imask = Y2_IS_BASE; | |
3316 | int i; | |
81906791 | 3317 | |
8a0c9228 MM |
3318 | for (i = 0; i < hw->ports; i++) { |
3319 | struct net_device *dev = hw->dev[i]; | |
3320 | struct sky2_port *sky2 = netdev_priv(dev); | |
3321 | ||
3322 | if (!netif_running(dev)) | |
3323 | continue; | |
3324 | ||
3325 | sky2_hw_up(sky2); | |
37652522 | 3326 | sky2_set_multicast(dev); |
d72ff8fa | 3327 | imask |= portirq_msk[i]; |
8a0c9228 MM |
3328 | netif_wake_queue(dev); |
3329 | } | |
3330 | ||
3331 | sky2_write32(hw, B0_IMSK, imask); | |
3332 | sky2_read32(hw, B0_IMSK); | |
3333 | ||
3334 | sky2_read32(hw, B0_Y2_SP_LISR); | |
3335 | napi_enable(&hw->napi); | |
d72ff8fa MM |
3336 | } |
3337 | ||
3338 | static void sky2_restart(struct work_struct *work) | |
3339 | { | |
3340 | struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); | |
3341 | ||
3342 | rtnl_lock(); | |
3343 | ||
3344 | sky2_all_down(hw); | |
3345 | sky2_reset(hw); | |
3346 | sky2_all_up(hw); | |
81906791 | 3347 | |
81906791 SH |
3348 | rtnl_unlock(); |
3349 | } | |
3350 | ||
e3173832 SH |
3351 | static inline u8 sky2_wol_supported(const struct sky2_hw *hw) |
3352 | { | |
3353 | return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; | |
3354 | } | |
3355 | ||
3356 | static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3357 | { | |
3358 | const struct sky2_port *sky2 = netdev_priv(dev); | |
3359 | ||
3360 | wol->supported = sky2_wol_supported(sky2->hw); | |
3361 | wol->wolopts = sky2->wol; | |
3362 | } | |
3363 | ||
3364 | static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3365 | { | |
3366 | struct sky2_port *sky2 = netdev_priv(dev); | |
3367 | struct sky2_hw *hw = sky2->hw; | |
0f333d10 RW |
3368 | bool enable_wakeup = false; |
3369 | int i; | |
cd28ab6a | 3370 | |
8e95a202 JP |
3371 | if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || |
3372 | !device_can_wakeup(&hw->pdev->dev)) | |
e3173832 SH |
3373 | return -EOPNOTSUPP; |
3374 | ||
3375 | sky2->wol = wol->wolopts; | |
0f333d10 RW |
3376 | |
3377 | for (i = 0; i < hw->ports; i++) { | |
3378 | struct net_device *dev = hw->dev[i]; | |
3379 | struct sky2_port *sky2 = netdev_priv(dev); | |
3380 | ||
3381 | if (sky2->wol) | |
3382 | enable_wakeup = true; | |
3383 | } | |
3384 | device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); | |
3385 | ||
cd28ab6a SH |
3386 | return 0; |
3387 | } | |
3388 | ||
28bd181a | 3389 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
cd28ab6a | 3390 | { |
b89165f2 SH |
3391 | if (sky2_is_copper(hw)) { |
3392 | u32 modes = SUPPORTED_10baseT_Half | |
3393 | | SUPPORTED_10baseT_Full | |
3394 | | SUPPORTED_100baseT_Half | |
2aca31e7 | 3395 | | SUPPORTED_100baseT_Full; |
cd28ab6a | 3396 | |
ea76e635 | 3397 | if (hw->flags & SKY2_HW_GIGABIT) |
cd28ab6a | 3398 | modes |= SUPPORTED_1000baseT_Half |
b89165f2 SH |
3399 | | SUPPORTED_1000baseT_Full; |
3400 | return modes; | |
cd28ab6a | 3401 | } else |
2aca31e7 SH |
3402 | return SUPPORTED_1000baseT_Half |
3403 | | SUPPORTED_1000baseT_Full; | |
cd28ab6a SH |
3404 | } |
3405 | ||
793b883e | 3406 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
3407 | { |
3408 | struct sky2_port *sky2 = netdev_priv(dev); | |
3409 | struct sky2_hw *hw = sky2->hw; | |
3410 | ||
3411 | ecmd->transceiver = XCVR_INTERNAL; | |
3412 | ecmd->supported = sky2_supported_modes(hw); | |
3413 | ecmd->phy_address = PHY_ADDR_MARV; | |
b89165f2 | 3414 | if (sky2_is_copper(hw)) { |
cd28ab6a | 3415 | ecmd->port = PORT_TP; |
b89165f2 | 3416 | ecmd->speed = sky2->speed; |
2aca31e7 | 3417 | ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP; |
b89165f2 SH |
3418 | } else { |
3419 | ecmd->speed = SPEED_1000; | |
cd28ab6a | 3420 | ecmd->port = PORT_FIBRE; |
2aca31e7 | 3421 | ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
b89165f2 | 3422 | } |
cd28ab6a SH |
3423 | |
3424 | ecmd->advertising = sky2->advertising; | |
0ea065e5 SH |
3425 | ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) |
3426 | ? AUTONEG_ENABLE : AUTONEG_DISABLE; | |
cd28ab6a SH |
3427 | ecmd->duplex = sky2->duplex; |
3428 | return 0; | |
3429 | } | |
3430 | ||
3431 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
3432 | { | |
3433 | struct sky2_port *sky2 = netdev_priv(dev); | |
3434 | const struct sky2_hw *hw = sky2->hw; | |
3435 | u32 supported = sky2_supported_modes(hw); | |
3436 | ||
3437 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2aca31e7 SH |
3438 | if (ecmd->advertising & ~supported) |
3439 | return -EINVAL; | |
3440 | ||
3441 | if (sky2_is_copper(hw)) | |
3442 | sky2->advertising = ecmd->advertising | | |
3443 | ADVERTISED_TP | | |
3444 | ADVERTISED_Autoneg; | |
3445 | else | |
3446 | sky2->advertising = ecmd->advertising | | |
3447 | ADVERTISED_FIBRE | | |
3448 | ADVERTISED_Autoneg; | |
3449 | ||
0ea065e5 | 3450 | sky2->flags |= SKY2_FLAG_AUTO_SPEED; |
cd28ab6a SH |
3451 | sky2->duplex = -1; |
3452 | sky2->speed = -1; | |
3453 | } else { | |
3454 | u32 setting; | |
3455 | ||
793b883e | 3456 | switch (ecmd->speed) { |
cd28ab6a SH |
3457 | case SPEED_1000: |
3458 | if (ecmd->duplex == DUPLEX_FULL) | |
3459 | setting = SUPPORTED_1000baseT_Full; | |
3460 | else if (ecmd->duplex == DUPLEX_HALF) | |
3461 | setting = SUPPORTED_1000baseT_Half; | |
3462 | else | |
3463 | return -EINVAL; | |
3464 | break; | |
3465 | case SPEED_100: | |
3466 | if (ecmd->duplex == DUPLEX_FULL) | |
3467 | setting = SUPPORTED_100baseT_Full; | |
3468 | else if (ecmd->duplex == DUPLEX_HALF) | |
3469 | setting = SUPPORTED_100baseT_Half; | |
3470 | else | |
3471 | return -EINVAL; | |
3472 | break; | |
3473 | ||
3474 | case SPEED_10: | |
3475 | if (ecmd->duplex == DUPLEX_FULL) | |
3476 | setting = SUPPORTED_10baseT_Full; | |
3477 | else if (ecmd->duplex == DUPLEX_HALF) | |
3478 | setting = SUPPORTED_10baseT_Half; | |
3479 | else | |
3480 | return -EINVAL; | |
3481 | break; | |
3482 | default: | |
3483 | return -EINVAL; | |
3484 | } | |
3485 | ||
3486 | if ((setting & supported) == 0) | |
3487 | return -EINVAL; | |
3488 | ||
3489 | sky2->speed = ecmd->speed; | |
3490 | sky2->duplex = ecmd->duplex; | |
0ea065e5 | 3491 | sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; |
cd28ab6a SH |
3492 | } |
3493 | ||
d1b139c0 | 3494 | if (netif_running(dev)) { |
1b537565 | 3495 | sky2_phy_reinit(sky2); |
d1b139c0 SH |
3496 | sky2_set_multicast(dev); |
3497 | } | |
cd28ab6a SH |
3498 | |
3499 | return 0; | |
3500 | } | |
3501 | ||
3502 | static void sky2_get_drvinfo(struct net_device *dev, | |
3503 | struct ethtool_drvinfo *info) | |
3504 | { | |
3505 | struct sky2_port *sky2 = netdev_priv(dev); | |
3506 | ||
3507 | strcpy(info->driver, DRV_NAME); | |
3508 | strcpy(info->version, DRV_VERSION); | |
3509 | strcpy(info->fw_version, "N/A"); | |
3510 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); | |
3511 | } | |
3512 | ||
3513 | static const struct sky2_stat { | |
793b883e SH |
3514 | char name[ETH_GSTRING_LEN]; |
3515 | u16 offset; | |
cd28ab6a SH |
3516 | } sky2_stats[] = { |
3517 | { "tx_bytes", GM_TXO_OK_HI }, | |
3518 | { "rx_bytes", GM_RXO_OK_HI }, | |
3519 | { "tx_broadcast", GM_TXF_BC_OK }, | |
3520 | { "rx_broadcast", GM_RXF_BC_OK }, | |
3521 | { "tx_multicast", GM_TXF_MC_OK }, | |
3522 | { "rx_multicast", GM_RXF_MC_OK }, | |
3523 | { "tx_unicast", GM_TXF_UC_OK }, | |
3524 | { "rx_unicast", GM_RXF_UC_OK }, | |
3525 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
3526 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
eadfa7dd | 3527 | { "collisions", GM_TXF_COL }, |
cd28ab6a SH |
3528 | { "late_collision",GM_TXF_LAT_COL }, |
3529 | { "aborted", GM_TXF_ABO_COL }, | |
eadfa7dd | 3530 | { "single_collisions", GM_TXF_SNG_COL }, |
cd28ab6a | 3531 | { "multi_collisions", GM_TXF_MUL_COL }, |
eadfa7dd | 3532 | |
d2604540 | 3533 | { "rx_short", GM_RXF_SHT }, |
cd28ab6a | 3534 | { "rx_runt", GM_RXE_FRAG }, |
eadfa7dd SH |
3535 | { "rx_64_byte_packets", GM_RXF_64B }, |
3536 | { "rx_65_to_127_byte_packets", GM_RXF_127B }, | |
3537 | { "rx_128_to_255_byte_packets", GM_RXF_255B }, | |
3538 | { "rx_256_to_511_byte_packets", GM_RXF_511B }, | |
3539 | { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, | |
3540 | { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, | |
3541 | { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, | |
cd28ab6a | 3542 | { "rx_too_long", GM_RXF_LNG_ERR }, |
eadfa7dd SH |
3543 | { "rx_fifo_overflow", GM_RXE_FIFO_OV }, |
3544 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
cd28ab6a | 3545 | { "rx_fcs_error", GM_RXF_FCS_ERR }, |
eadfa7dd SH |
3546 | |
3547 | { "tx_64_byte_packets", GM_TXF_64B }, | |
3548 | { "tx_65_to_127_byte_packets", GM_TXF_127B }, | |
3549 | { "tx_128_to_255_byte_packets", GM_TXF_255B }, | |
3550 | { "tx_256_to_511_byte_packets", GM_TXF_511B }, | |
3551 | { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, | |
3552 | { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, | |
3553 | { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, | |
3554 | { "tx_fifo_underrun", GM_TXE_FIFO_UR }, | |
cd28ab6a SH |
3555 | }; |
3556 | ||
cd28ab6a SH |
3557 | static u32 sky2_get_msglevel(struct net_device *netdev) |
3558 | { | |
3559 | struct sky2_port *sky2 = netdev_priv(netdev); | |
3560 | return sky2->msg_enable; | |
3561 | } | |
3562 | ||
9a7ae0a9 SH |
3563 | static int sky2_nway_reset(struct net_device *dev) |
3564 | { | |
3565 | struct sky2_port *sky2 = netdev_priv(dev); | |
9a7ae0a9 | 3566 | |
0ea065e5 | 3567 | if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) |
9a7ae0a9 SH |
3568 | return -EINVAL; |
3569 | ||
1b537565 | 3570 | sky2_phy_reinit(sky2); |
d1b139c0 | 3571 | sky2_set_multicast(dev); |
9a7ae0a9 SH |
3572 | |
3573 | return 0; | |
3574 | } | |
3575 | ||
793b883e | 3576 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
3577 | { |
3578 | struct sky2_hw *hw = sky2->hw; | |
3579 | unsigned port = sky2->port; | |
3580 | int i; | |
3581 | ||
0885a30b | 3582 | data[0] = get_stats64(hw, port, GM_TXO_OK_LO); |
3583 | data[1] = get_stats64(hw, port, GM_RXO_OK_LO); | |
cd28ab6a | 3584 | |
793b883e | 3585 | for (i = 2; i < count; i++) |
0885a30b | 3586 | data[i] = get_stats32(hw, port, sky2_stats[i].offset); |
cd28ab6a SH |
3587 | } |
3588 | ||
cd28ab6a SH |
3589 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
3590 | { | |
3591 | struct sky2_port *sky2 = netdev_priv(netdev); | |
3592 | sky2->msg_enable = value; | |
3593 | } | |
3594 | ||
b9f2c044 | 3595 | static int sky2_get_sset_count(struct net_device *dev, int sset) |
cd28ab6a | 3596 | { |
b9f2c044 JG |
3597 | switch (sset) { |
3598 | case ETH_SS_STATS: | |
3599 | return ARRAY_SIZE(sky2_stats); | |
3600 | default: | |
3601 | return -EOPNOTSUPP; | |
3602 | } | |
cd28ab6a SH |
3603 | } |
3604 | ||
3605 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 3606 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
3607 | { |
3608 | struct sky2_port *sky2 = netdev_priv(dev); | |
3609 | ||
793b883e | 3610 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
3611 | } |
3612 | ||
793b883e | 3613 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
3614 | { |
3615 | int i; | |
3616 | ||
3617 | switch (stringset) { | |
3618 | case ETH_SS_STATS: | |
3619 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
3620 | memcpy(data + i * ETH_GSTRING_LEN, | |
3621 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
3622 | break; | |
3623 | } | |
3624 | } | |
3625 | ||
cd28ab6a SH |
3626 | static int sky2_set_mac_address(struct net_device *dev, void *p) |
3627 | { | |
3628 | struct sky2_port *sky2 = netdev_priv(dev); | |
a8ab1ec0 SH |
3629 | struct sky2_hw *hw = sky2->hw; |
3630 | unsigned port = sky2->port; | |
3631 | const struct sockaddr *addr = p; | |
cd28ab6a SH |
3632 | |
3633 | if (!is_valid_ether_addr(addr->sa_data)) | |
3634 | return -EADDRNOTAVAIL; | |
3635 | ||
cd28ab6a | 3636 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
a8ab1ec0 | 3637 | memcpy_toio(hw->regs + B2_MAC_1 + port * 8, |
cd28ab6a | 3638 | dev->dev_addr, ETH_ALEN); |
a8ab1ec0 | 3639 | memcpy_toio(hw->regs + B2_MAC_2 + port * 8, |
cd28ab6a | 3640 | dev->dev_addr, ETH_ALEN); |
1b537565 | 3641 | |
a8ab1ec0 SH |
3642 | /* virtual address for data */ |
3643 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
3644 | ||
3645 | /* physical address: used for pause frames */ | |
3646 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
1b537565 SH |
3647 | |
3648 | return 0; | |
cd28ab6a SH |
3649 | } |
3650 | ||
060b946c | 3651 | static inline void sky2_add_filter(u8 filter[8], const u8 *addr) |
a052b52f SH |
3652 | { |
3653 | u32 bit; | |
3654 | ||
3655 | bit = ether_crc(ETH_ALEN, addr) & 63; | |
3656 | filter[bit >> 3] |= 1 << (bit & 7); | |
3657 | } | |
3658 | ||
cd28ab6a SH |
3659 | static void sky2_set_multicast(struct net_device *dev) |
3660 | { | |
3661 | struct sky2_port *sky2 = netdev_priv(dev); | |
3662 | struct sky2_hw *hw = sky2->hw; | |
3663 | unsigned port = sky2->port; | |
22bedad3 | 3664 | struct netdev_hw_addr *ha; |
cd28ab6a SH |
3665 | u16 reg; |
3666 | u8 filter[8]; | |
a052b52f SH |
3667 | int rx_pause; |
3668 | static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; | |
cd28ab6a | 3669 | |
a052b52f | 3670 | rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); |
cd28ab6a SH |
3671 | memset(filter, 0, sizeof(filter)); |
3672 | ||
3673 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
3674 | reg |= GM_RXCR_UCF_ENA; | |
3675 | ||
d571b694 | 3676 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 3677 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
a052b52f | 3678 | else if (dev->flags & IFF_ALLMULTI) |
cd28ab6a | 3679 | memset(filter, 0xff, sizeof(filter)); |
4cd24eaf | 3680 | else if (netdev_mc_empty(dev) && !rx_pause) |
cd28ab6a SH |
3681 | reg &= ~GM_RXCR_MCF_ENA; |
3682 | else { | |
cd28ab6a SH |
3683 | reg |= GM_RXCR_MCF_ENA; |
3684 | ||
a052b52f SH |
3685 | if (rx_pause) |
3686 | sky2_add_filter(filter, pause_mc_addr); | |
3687 | ||
22bedad3 JP |
3688 | netdev_for_each_mc_addr(ha, dev) |
3689 | sky2_add_filter(filter, ha->addr); | |
cd28ab6a SH |
3690 | } |
3691 | ||
cd28ab6a | 3692 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 3693 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 3694 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 3695 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 3696 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 3697 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 3698 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 3699 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
3700 | |
3701 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
3702 | } | |
3703 | ||
0885a30b | 3704 | static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev, |
3705 | struct rtnl_link_stats64 *stats) | |
3706 | { | |
3707 | struct sky2_port *sky2 = netdev_priv(dev); | |
3708 | struct sky2_hw *hw = sky2->hw; | |
3709 | unsigned port = sky2->port; | |
3710 | unsigned int start; | |
3711 | u64 _bytes, _packets; | |
3712 | ||
3713 | do { | |
3714 | start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp); | |
3715 | _bytes = sky2->rx_stats.bytes; | |
3716 | _packets = sky2->rx_stats.packets; | |
3717 | } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start)); | |
3718 | ||
3719 | stats->rx_packets = _packets; | |
3720 | stats->rx_bytes = _bytes; | |
3721 | ||
3722 | do { | |
3723 | start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp); | |
3724 | _bytes = sky2->tx_stats.bytes; | |
3725 | _packets = sky2->tx_stats.packets; | |
3726 | } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start)); | |
3727 | ||
3728 | stats->tx_packets = _packets; | |
3729 | stats->tx_bytes = _bytes; | |
3730 | ||
3731 | stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) | |
3732 | + get_stats32(hw, port, GM_RXF_BC_OK); | |
3733 | ||
3734 | stats->collisions = get_stats32(hw, port, GM_TXF_COL); | |
3735 | ||
3736 | stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); | |
3737 | stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); | |
3738 | stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) | |
3739 | + get_stats32(hw, port, GM_RXE_FRAG); | |
3740 | stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); | |
3741 | ||
3742 | stats->rx_dropped = dev->stats.rx_dropped; | |
3743 | stats->rx_fifo_errors = dev->stats.rx_fifo_errors; | |
3744 | stats->tx_fifo_errors = dev->stats.tx_fifo_errors; | |
3745 | ||
3746 | return stats; | |
3747 | } | |
3748 | ||
cd28ab6a SH |
3749 | /* Can have one global because blinking is controlled by |
3750 | * ethtool and that is always under RTNL mutex | |
3751 | */ | |
a84d0a3d | 3752 | static void sky2_led(struct sky2_port *sky2, enum led_mode mode) |
cd28ab6a | 3753 | { |
a84d0a3d SH |
3754 | struct sky2_hw *hw = sky2->hw; |
3755 | unsigned port = sky2->port; | |
793b883e | 3756 | |
a84d0a3d SH |
3757 | spin_lock_bh(&sky2->phy_lock); |
3758 | if (hw->chip_id == CHIP_ID_YUKON_EC_U || | |
3759 | hw->chip_id == CHIP_ID_YUKON_EX || | |
3760 | hw->chip_id == CHIP_ID_YUKON_SUPR) { | |
3761 | u16 pg; | |
793b883e SH |
3762 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
3763 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
793b883e | 3764 | |
a84d0a3d SH |
3765 | switch (mode) { |
3766 | case MO_LED_OFF: | |
3767 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3768 | PHY_M_LEDC_LOS_CTRL(8) | | |
3769 | PHY_M_LEDC_INIT_CTRL(8) | | |
3770 | PHY_M_LEDC_STA1_CTRL(8) | | |
3771 | PHY_M_LEDC_STA0_CTRL(8)); | |
3772 | break; | |
3773 | case MO_LED_ON: | |
3774 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3775 | PHY_M_LEDC_LOS_CTRL(9) | | |
3776 | PHY_M_LEDC_INIT_CTRL(9) | | |
3777 | PHY_M_LEDC_STA1_CTRL(9) | | |
3778 | PHY_M_LEDC_STA0_CTRL(9)); | |
3779 | break; | |
3780 | case MO_LED_BLINK: | |
3781 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3782 | PHY_M_LEDC_LOS_CTRL(0xa) | | |
3783 | PHY_M_LEDC_INIT_CTRL(0xa) | | |
3784 | PHY_M_LEDC_STA1_CTRL(0xa) | | |
3785 | PHY_M_LEDC_STA0_CTRL(0xa)); | |
3786 | break; | |
3787 | case MO_LED_NORM: | |
3788 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3789 | PHY_M_LEDC_LOS_CTRL(1) | | |
3790 | PHY_M_LEDC_INIT_CTRL(8) | | |
3791 | PHY_M_LEDC_STA1_CTRL(7) | | |
3792 | PHY_M_LEDC_STA0_CTRL(7)); | |
3793 | } | |
793b883e | 3794 | |
a84d0a3d SH |
3795 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
3796 | } else | |
7d2e3cb7 | 3797 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
a84d0a3d SH |
3798 | PHY_M_LED_MO_DUP(mode) | |
3799 | PHY_M_LED_MO_10(mode) | | |
3800 | PHY_M_LED_MO_100(mode) | | |
3801 | PHY_M_LED_MO_1000(mode) | | |
3802 | PHY_M_LED_MO_RX(mode) | | |
3803 | PHY_M_LED_MO_TX(mode)); | |
3804 | ||
3805 | spin_unlock_bh(&sky2->phy_lock); | |
cd28ab6a SH |
3806 | } |
3807 | ||
3808 | /* blink LED's for finding board */ | |
74e532ff | 3809 | static int sky2_set_phys_id(struct net_device *dev, |
3810 | enum ethtool_phys_id_state state) | |
cd28ab6a SH |
3811 | { |
3812 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a | 3813 | |
74e532ff | 3814 | switch (state) { |
3815 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 3816 | return 1; /* cycle on/off once per second */ |
74e532ff | 3817 | case ETHTOOL_ID_INACTIVE: |
3818 | sky2_led(sky2, MO_LED_NORM); | |
3819 | break; | |
3820 | case ETHTOOL_ID_ON: | |
a84d0a3d | 3821 | sky2_led(sky2, MO_LED_ON); |
74e532ff | 3822 | break; |
3823 | case ETHTOOL_ID_OFF: | |
a84d0a3d | 3824 | sky2_led(sky2, MO_LED_OFF); |
74e532ff | 3825 | break; |
793b883e | 3826 | } |
cd28ab6a SH |
3827 | |
3828 | return 0; | |
3829 | } | |
3830 | ||
3831 | static void sky2_get_pauseparam(struct net_device *dev, | |
3832 | struct ethtool_pauseparam *ecmd) | |
3833 | { | |
3834 | struct sky2_port *sky2 = netdev_priv(dev); | |
3835 | ||
16ad91e1 SH |
3836 | switch (sky2->flow_mode) { |
3837 | case FC_NONE: | |
3838 | ecmd->tx_pause = ecmd->rx_pause = 0; | |
3839 | break; | |
3840 | case FC_TX: | |
3841 | ecmd->tx_pause = 1, ecmd->rx_pause = 0; | |
3842 | break; | |
3843 | case FC_RX: | |
3844 | ecmd->tx_pause = 0, ecmd->rx_pause = 1; | |
3845 | break; | |
3846 | case FC_BOTH: | |
3847 | ecmd->tx_pause = ecmd->rx_pause = 1; | |
3848 | } | |
3849 | ||
0ea065e5 SH |
3850 | ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) |
3851 | ? AUTONEG_ENABLE : AUTONEG_DISABLE; | |
cd28ab6a SH |
3852 | } |
3853 | ||
3854 | static int sky2_set_pauseparam(struct net_device *dev, | |
3855 | struct ethtool_pauseparam *ecmd) | |
3856 | { | |
3857 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a | 3858 | |
0ea065e5 SH |
3859 | if (ecmd->autoneg == AUTONEG_ENABLE) |
3860 | sky2->flags |= SKY2_FLAG_AUTO_PAUSE; | |
3861 | else | |
3862 | sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; | |
3863 | ||
16ad91e1 | 3864 | sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); |
cd28ab6a | 3865 | |
16ad91e1 SH |
3866 | if (netif_running(dev)) |
3867 | sky2_phy_reinit(sky2); | |
cd28ab6a | 3868 | |
2eaba1a2 | 3869 | return 0; |
cd28ab6a SH |
3870 | } |
3871 | ||
fb17358f SH |
3872 | static int sky2_get_coalesce(struct net_device *dev, |
3873 | struct ethtool_coalesce *ecmd) | |
3874 | { | |
3875 | struct sky2_port *sky2 = netdev_priv(dev); | |
3876 | struct sky2_hw *hw = sky2->hw; | |
3877 | ||
3878 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) | |
3879 | ecmd->tx_coalesce_usecs = 0; | |
3880 | else { | |
3881 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); | |
3882 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); | |
3883 | } | |
3884 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); | |
3885 | ||
3886 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) | |
3887 | ecmd->rx_coalesce_usecs = 0; | |
3888 | else { | |
3889 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); | |
3890 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); | |
3891 | } | |
3892 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); | |
3893 | ||
3894 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) | |
3895 | ecmd->rx_coalesce_usecs_irq = 0; | |
3896 | else { | |
3897 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); | |
3898 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); | |
3899 | } | |
3900 | ||
3901 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); | |
3902 | ||
3903 | return 0; | |
3904 | } | |
3905 | ||
3906 | /* Note: this affect both ports */ | |
3907 | static int sky2_set_coalesce(struct net_device *dev, | |
3908 | struct ethtool_coalesce *ecmd) | |
3909 | { | |
3910 | struct sky2_port *sky2 = netdev_priv(dev); | |
3911 | struct sky2_hw *hw = sky2->hw; | |
77b3d6a2 | 3912 | const u32 tmax = sky2_clk2us(hw, 0x0ffffff); |
fb17358f | 3913 | |
77b3d6a2 SH |
3914 | if (ecmd->tx_coalesce_usecs > tmax || |
3915 | ecmd->rx_coalesce_usecs > tmax || | |
3916 | ecmd->rx_coalesce_usecs_irq > tmax) | |
fb17358f SH |
3917 | return -EINVAL; |
3918 | ||
ee5f68fe | 3919 | if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) |
fb17358f | 3920 | return -EINVAL; |
ff81fbbe | 3921 | if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) |
fb17358f | 3922 | return -EINVAL; |
060b946c | 3923 | if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING) |
fb17358f SH |
3924 | return -EINVAL; |
3925 | ||
3926 | if (ecmd->tx_coalesce_usecs == 0) | |
3927 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
3928 | else { | |
3929 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
3930 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); | |
3931 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
3932 | } | |
3933 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); | |
3934 | ||
3935 | if (ecmd->rx_coalesce_usecs == 0) | |
3936 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
3937 | else { | |
3938 | sky2_write32(hw, STAT_LEV_TIMER_INI, | |
3939 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); | |
3940 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
3941 | } | |
3942 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); | |
3943 | ||
3944 | if (ecmd->rx_coalesce_usecs_irq == 0) | |
3945 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); | |
3946 | else { | |
d28d4870 | 3947 | sky2_write32(hw, STAT_ISR_TIMER_INI, |
fb17358f SH |
3948 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); |
3949 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
3950 | } | |
3951 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); | |
3952 | return 0; | |
3953 | } | |
3954 | ||
793b883e SH |
3955 | static void sky2_get_ringparam(struct net_device *dev, |
3956 | struct ethtool_ringparam *ering) | |
3957 | { | |
3958 | struct sky2_port *sky2 = netdev_priv(dev); | |
3959 | ||
3960 | ering->rx_max_pending = RX_MAX_PENDING; | |
3961 | ering->rx_mini_max_pending = 0; | |
3962 | ering->rx_jumbo_max_pending = 0; | |
ee5f68fe | 3963 | ering->tx_max_pending = TX_MAX_PENDING; |
793b883e SH |
3964 | |
3965 | ering->rx_pending = sky2->rx_pending; | |
3966 | ering->rx_mini_pending = 0; | |
3967 | ering->rx_jumbo_pending = 0; | |
3968 | ering->tx_pending = sky2->tx_pending; | |
3969 | } | |
3970 | ||
3971 | static int sky2_set_ringparam(struct net_device *dev, | |
3972 | struct ethtool_ringparam *ering) | |
3973 | { | |
3974 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e SH |
3975 | |
3976 | if (ering->rx_pending > RX_MAX_PENDING || | |
3977 | ering->rx_pending < 8 || | |
ee5f68fe SH |
3978 | ering->tx_pending < TX_MIN_PENDING || |
3979 | ering->tx_pending > TX_MAX_PENDING) | |
793b883e SH |
3980 | return -EINVAL; |
3981 | ||
af18d8b8 | 3982 | sky2_detach(dev); |
793b883e SH |
3983 | |
3984 | sky2->rx_pending = ering->rx_pending; | |
3985 | sky2->tx_pending = ering->tx_pending; | |
ee5f68fe | 3986 | sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1); |
793b883e | 3987 | |
af18d8b8 | 3988 | return sky2_reattach(dev); |
793b883e SH |
3989 | } |
3990 | ||
793b883e SH |
3991 | static int sky2_get_regs_len(struct net_device *dev) |
3992 | { | |
6e4cbb34 | 3993 | return 0x4000; |
793b883e SH |
3994 | } |
3995 | ||
c32bbff8 MM |
3996 | static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) |
3997 | { | |
3998 | /* This complicated switch statement is to make sure and | |
3999 | * only access regions that are unreserved. | |
4000 | * Some blocks are only valid on dual port cards. | |
4001 | */ | |
4002 | switch (b) { | |
4003 | /* second port */ | |
4004 | case 5: /* Tx Arbiter 2 */ | |
4005 | case 9: /* RX2 */ | |
4006 | case 14 ... 15: /* TX2 */ | |
4007 | case 17: case 19: /* Ram Buffer 2 */ | |
4008 | case 22 ... 23: /* Tx Ram Buffer 2 */ | |
4009 | case 25: /* Rx MAC Fifo 1 */ | |
4010 | case 27: /* Tx MAC Fifo 2 */ | |
4011 | case 31: /* GPHY 2 */ | |
4012 | case 40 ... 47: /* Pattern Ram 2 */ | |
4013 | case 52: case 54: /* TCP Segmentation 2 */ | |
4014 | case 112 ... 116: /* GMAC 2 */ | |
4015 | return hw->ports > 1; | |
4016 | ||
4017 | case 0: /* Control */ | |
4018 | case 2: /* Mac address */ | |
4019 | case 4: /* Tx Arbiter 1 */ | |
4020 | case 7: /* PCI express reg */ | |
4021 | case 8: /* RX1 */ | |
4022 | case 12 ... 13: /* TX1 */ | |
4023 | case 16: case 18:/* Rx Ram Buffer 1 */ | |
4024 | case 20 ... 21: /* Tx Ram Buffer 1 */ | |
4025 | case 24: /* Rx MAC Fifo 1 */ | |
4026 | case 26: /* Tx MAC Fifo 1 */ | |
4027 | case 28 ... 29: /* Descriptor and status unit */ | |
4028 | case 30: /* GPHY 1*/ | |
4029 | case 32 ... 39: /* Pattern Ram 1 */ | |
4030 | case 48: case 50: /* TCP Segmentation 1 */ | |
4031 | case 56 ... 60: /* PCI space */ | |
4032 | case 80 ... 84: /* GMAC 1 */ | |
4033 | return 1; | |
4034 | ||
4035 | default: | |
4036 | return 0; | |
4037 | } | |
4038 | } | |
4039 | ||
793b883e SH |
4040 | /* |
4041 | * Returns copy of control register region | |
3ead5db7 | 4042 | * Note: ethtool_get_regs always provides full size (16k) buffer |
793b883e SH |
4043 | */ |
4044 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
4045 | void *p) | |
4046 | { | |
4047 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 4048 | const void __iomem *io = sky2->hw->regs; |
295b54c4 | 4049 | unsigned int b; |
793b883e SH |
4050 | |
4051 | regs->version = 1; | |
793b883e | 4052 | |
295b54c4 | 4053 | for (b = 0; b < 128; b++) { |
c32bbff8 MM |
4054 | /* skip poisonous diagnostic ram region in block 3 */ |
4055 | if (b == 3) | |
295b54c4 | 4056 | memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); |
c32bbff8 | 4057 | else if (sky2_reg_access_ok(sky2->hw, b)) |
295b54c4 | 4058 | memcpy_fromio(p, io, 128); |
c32bbff8 | 4059 | else |
295b54c4 | 4060 | memset(p, 0, 128); |
3ead5db7 | 4061 | |
295b54c4 SH |
4062 | p += 128; |
4063 | io += 128; | |
4064 | } | |
793b883e | 4065 | } |
cd28ab6a | 4066 | |
f4331a6d SH |
4067 | static int sky2_get_eeprom_len(struct net_device *dev) |
4068 | { | |
4069 | struct sky2_port *sky2 = netdev_priv(dev); | |
b32f40c4 | 4070 | struct sky2_hw *hw = sky2->hw; |
f4331a6d SH |
4071 | u16 reg2; |
4072 | ||
b32f40c4 | 4073 | reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); |
f4331a6d SH |
4074 | return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); |
4075 | } | |
4076 | ||
1413235c | 4077 | static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) |
f4331a6d | 4078 | { |
1413235c | 4079 | unsigned long start = jiffies; |
f4331a6d | 4080 | |
1413235c SH |
4081 | while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { |
4082 | /* Can take up to 10.6 ms for write */ | |
4083 | if (time_after(jiffies, start + HZ/4)) { | |
ada1db5c | 4084 | dev_err(&hw->pdev->dev, "VPD cycle timed out\n"); |
1413235c SH |
4085 | return -ETIMEDOUT; |
4086 | } | |
4087 | mdelay(1); | |
4088 | } | |
167f53d0 | 4089 | |
1413235c SH |
4090 | return 0; |
4091 | } | |
167f53d0 | 4092 | |
1413235c SH |
4093 | static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, |
4094 | u16 offset, size_t length) | |
4095 | { | |
4096 | int rc = 0; | |
4097 | ||
4098 | while (length > 0) { | |
4099 | u32 val; | |
4100 | ||
4101 | sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); | |
4102 | rc = sky2_vpd_wait(hw, cap, 0); | |
4103 | if (rc) | |
4104 | break; | |
4105 | ||
4106 | val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); | |
4107 | ||
4108 | memcpy(data, &val, min(sizeof(val), length)); | |
4109 | offset += sizeof(u32); | |
4110 | data += sizeof(u32); | |
4111 | length -= sizeof(u32); | |
4112 | } | |
4113 | ||
4114 | return rc; | |
f4331a6d SH |
4115 | } |
4116 | ||
1413235c SH |
4117 | static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, |
4118 | u16 offset, unsigned int length) | |
f4331a6d | 4119 | { |
1413235c SH |
4120 | unsigned int i; |
4121 | int rc = 0; | |
4122 | ||
4123 | for (i = 0; i < length; i += sizeof(u32)) { | |
4124 | u32 val = *(u32 *)(data + i); | |
4125 | ||
4126 | sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); | |
4127 | sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); | |
4128 | ||
4129 | rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); | |
4130 | if (rc) | |
4131 | break; | |
4132 | } | |
4133 | return rc; | |
f4331a6d SH |
4134 | } |
4135 | ||
4136 | static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
4137 | u8 *data) | |
4138 | { | |
4139 | struct sky2_port *sky2 = netdev_priv(dev); | |
4140 | int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); | |
f4331a6d SH |
4141 | |
4142 | if (!cap) | |
4143 | return -EINVAL; | |
4144 | ||
4145 | eeprom->magic = SKY2_EEPROM_MAGIC; | |
4146 | ||
1413235c | 4147 | return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); |
f4331a6d SH |
4148 | } |
4149 | ||
4150 | static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
4151 | u8 *data) | |
4152 | { | |
4153 | struct sky2_port *sky2 = netdev_priv(dev); | |
4154 | int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); | |
f4331a6d SH |
4155 | |
4156 | if (!cap) | |
4157 | return -EINVAL; | |
4158 | ||
4159 | if (eeprom->magic != SKY2_EEPROM_MAGIC) | |
4160 | return -EINVAL; | |
4161 | ||
1413235c SH |
4162 | /* Partial writes not supported */ |
4163 | if ((eeprom->offset & 3) || (eeprom->len & 3)) | |
4164 | return -EINVAL; | |
f4331a6d | 4165 | |
1413235c | 4166 | return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); |
f4331a6d SH |
4167 | } |
4168 | ||
f5d64037 | 4169 | static u32 sky2_fix_features(struct net_device *dev, u32 features) |
bf73130d | 4170 | { |
f5d64037 MM |
4171 | const struct sky2_port *sky2 = netdev_priv(dev); |
4172 | const struct sky2_hw *hw = sky2->hw; | |
bf73130d | 4173 | |
f5d64037 MM |
4174 | /* In order to do Jumbo packets on these chips, need to turn off the |
4175 | * transmit store/forward. Therefore checksum offload won't work. | |
4176 | */ | |
4177 | if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) | |
4178 | features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM); | |
86aa7785 | 4179 | |
f5d64037 MM |
4180 | return features; |
4181 | } | |
86aa7785 | 4182 | |
f5d64037 MM |
4183 | static int sky2_set_features(struct net_device *dev, u32 features) |
4184 | { | |
4185 | struct sky2_port *sky2 = netdev_priv(dev); | |
4186 | u32 changed = dev->features ^ features; | |
86aa7785 | 4187 | |
f5d64037 MM |
4188 | if (changed & NETIF_F_RXCSUM) { |
4189 | u32 on = features & NETIF_F_RXCSUM; | |
4190 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
4191 | on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
4192 | } | |
bf73130d | 4193 | |
f5d64037 MM |
4194 | if (changed & NETIF_F_RXHASH) |
4195 | rx_set_rss(dev, features); | |
86aa7785 | 4196 | |
f5d64037 MM |
4197 | if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX)) |
4198 | sky2_vlan_mode(dev, features); | |
bf73130d SH |
4199 | |
4200 | return 0; | |
4201 | } | |
f4331a6d | 4202 | |
7282d491 | 4203 | static const struct ethtool_ops sky2_ethtool_ops = { |
f4331a6d SH |
4204 | .get_settings = sky2_get_settings, |
4205 | .set_settings = sky2_set_settings, | |
4206 | .get_drvinfo = sky2_get_drvinfo, | |
4207 | .get_wol = sky2_get_wol, | |
4208 | .set_wol = sky2_set_wol, | |
4209 | .get_msglevel = sky2_get_msglevel, | |
4210 | .set_msglevel = sky2_set_msglevel, | |
4211 | .nway_reset = sky2_nway_reset, | |
4212 | .get_regs_len = sky2_get_regs_len, | |
4213 | .get_regs = sky2_get_regs, | |
4214 | .get_link = ethtool_op_get_link, | |
4215 | .get_eeprom_len = sky2_get_eeprom_len, | |
4216 | .get_eeprom = sky2_get_eeprom, | |
4217 | .set_eeprom = sky2_set_eeprom, | |
f4331a6d SH |
4218 | .get_strings = sky2_get_strings, |
4219 | .get_coalesce = sky2_get_coalesce, | |
4220 | .set_coalesce = sky2_set_coalesce, | |
4221 | .get_ringparam = sky2_get_ringparam, | |
4222 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
4223 | .get_pauseparam = sky2_get_pauseparam, |
4224 | .set_pauseparam = sky2_set_pauseparam, | |
74e532ff | 4225 | .set_phys_id = sky2_set_phys_id, |
b9f2c044 | 4226 | .get_sset_count = sky2_get_sset_count, |
cd28ab6a SH |
4227 | .get_ethtool_stats = sky2_get_ethtool_stats, |
4228 | }; | |
4229 | ||
3cf26753 SH |
4230 | #ifdef CONFIG_SKY2_DEBUG |
4231 | ||
4232 | static struct dentry *sky2_debug; | |
4233 | ||
e4c2abe2 SH |
4234 | |
4235 | /* | |
4236 | * Read and parse the first part of Vital Product Data | |
4237 | */ | |
4238 | #define VPD_SIZE 128 | |
4239 | #define VPD_MAGIC 0x82 | |
4240 | ||
4241 | static const struct vpd_tag { | |
4242 | char tag[2]; | |
4243 | char *label; | |
4244 | } vpd_tags[] = { | |
4245 | { "PN", "Part Number" }, | |
4246 | { "EC", "Engineering Level" }, | |
4247 | { "MN", "Manufacturer" }, | |
4248 | { "SN", "Serial Number" }, | |
4249 | { "YA", "Asset Tag" }, | |
4250 | { "VL", "First Error Log Message" }, | |
4251 | { "VF", "Second Error Log Message" }, | |
4252 | { "VB", "Boot Agent ROM Configuration" }, | |
4253 | { "VE", "EFI UNDI Configuration" }, | |
4254 | }; | |
4255 | ||
4256 | static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) | |
4257 | { | |
4258 | size_t vpd_size; | |
4259 | loff_t offs; | |
4260 | u8 len; | |
4261 | unsigned char *buf; | |
4262 | u16 reg2; | |
4263 | ||
4264 | reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); | |
4265 | vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); | |
4266 | ||
4267 | seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); | |
4268 | buf = kmalloc(vpd_size, GFP_KERNEL); | |
4269 | if (!buf) { | |
4270 | seq_puts(seq, "no memory!\n"); | |
4271 | return; | |
4272 | } | |
4273 | ||
4274 | if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { | |
4275 | seq_puts(seq, "VPD read failed\n"); | |
4276 | goto out; | |
4277 | } | |
4278 | ||
4279 | if (buf[0] != VPD_MAGIC) { | |
4280 | seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]); | |
4281 | goto out; | |
4282 | } | |
4283 | len = buf[1]; | |
4284 | if (len == 0 || len > vpd_size - 4) { | |
4285 | seq_printf(seq, "Invalid id length: %d\n", len); | |
4286 | goto out; | |
4287 | } | |
4288 | ||
4289 | seq_printf(seq, "%.*s\n", len, buf + 3); | |
4290 | offs = len + 3; | |
4291 | ||
4292 | while (offs < vpd_size - 4) { | |
4293 | int i; | |
4294 | ||
4295 | if (!memcmp("RW", buf + offs, 2)) /* end marker */ | |
4296 | break; | |
4297 | len = buf[offs + 2]; | |
4298 | if (offs + len + 3 >= vpd_size) | |
4299 | break; | |
4300 | ||
4301 | for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) { | |
4302 | if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) { | |
4303 | seq_printf(seq, " %s: %.*s\n", | |
4304 | vpd_tags[i].label, len, buf + offs + 3); | |
4305 | break; | |
4306 | } | |
4307 | } | |
4308 | offs += len + 3; | |
4309 | } | |
4310 | out: | |
4311 | kfree(buf); | |
4312 | } | |
4313 | ||
3cf26753 SH |
4314 | static int sky2_debug_show(struct seq_file *seq, void *v) |
4315 | { | |
4316 | struct net_device *dev = seq->private; | |
4317 | const struct sky2_port *sky2 = netdev_priv(dev); | |
bea3348e | 4318 | struct sky2_hw *hw = sky2->hw; |
3cf26753 SH |
4319 | unsigned port = sky2->port; |
4320 | unsigned idx, last; | |
4321 | int sop; | |
4322 | ||
e4c2abe2 | 4323 | sky2_show_vpd(seq, hw); |
3cf26753 | 4324 | |
e4c2abe2 | 4325 | seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n", |
3cf26753 SH |
4326 | sky2_read32(hw, B0_ISRC), |
4327 | sky2_read32(hw, B0_IMSK), | |
4328 | sky2_read32(hw, B0_Y2_SP_ICR)); | |
4329 | ||
e4c2abe2 SH |
4330 | if (!netif_running(dev)) { |
4331 | seq_printf(seq, "network not running\n"); | |
4332 | return 0; | |
4333 | } | |
4334 | ||
bea3348e | 4335 | napi_disable(&hw->napi); |
3cf26753 SH |
4336 | last = sky2_read16(hw, STAT_PUT_IDX); |
4337 | ||
efe91932 | 4338 | seq_printf(seq, "Status ring %u\n", hw->st_size); |
3cf26753 SH |
4339 | if (hw->st_idx == last) |
4340 | seq_puts(seq, "Status ring (empty)\n"); | |
4341 | else { | |
4342 | seq_puts(seq, "Status ring\n"); | |
efe91932 | 4343 | for (idx = hw->st_idx; idx != last && idx < hw->st_size; |
4344 | idx = RING_NEXT(idx, hw->st_size)) { | |
3cf26753 SH |
4345 | const struct sky2_status_le *le = hw->st_le + idx; |
4346 | seq_printf(seq, "[%d] %#x %d %#x\n", | |
4347 | idx, le->opcode, le->length, le->status); | |
4348 | } | |
4349 | seq_puts(seq, "\n"); | |
4350 | } | |
4351 | ||
4352 | seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", | |
4353 | sky2->tx_cons, sky2->tx_prod, | |
4354 | sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), | |
4355 | sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); | |
4356 | ||
4357 | /* Dump contents of tx ring */ | |
4358 | sop = 1; | |
ee5f68fe SH |
4359 | for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; |
4360 | idx = RING_NEXT(idx, sky2->tx_ring_size)) { | |
3cf26753 SH |
4361 | const struct sky2_tx_le *le = sky2->tx_le + idx; |
4362 | u32 a = le32_to_cpu(le->addr); | |
4363 | ||
4364 | if (sop) | |
4365 | seq_printf(seq, "%u:", idx); | |
4366 | sop = 0; | |
4367 | ||
060b946c | 4368 | switch (le->opcode & ~HW_OWNER) { |
3cf26753 SH |
4369 | case OP_ADDR64: |
4370 | seq_printf(seq, " %#x:", a); | |
4371 | break; | |
4372 | case OP_LRGLEN: | |
4373 | seq_printf(seq, " mtu=%d", a); | |
4374 | break; | |
4375 | case OP_VLAN: | |
4376 | seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); | |
4377 | break; | |
4378 | case OP_TCPLISW: | |
4379 | seq_printf(seq, " csum=%#x", a); | |
4380 | break; | |
4381 | case OP_LARGESEND: | |
4382 | seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); | |
4383 | break; | |
4384 | case OP_PACKET: | |
4385 | seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); | |
4386 | break; | |
4387 | case OP_BUFFER: | |
4388 | seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); | |
4389 | break; | |
4390 | default: | |
4391 | seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, | |
4392 | a, le16_to_cpu(le->length)); | |
4393 | } | |
4394 | ||
4395 | if (le->ctrl & EOP) { | |
4396 | seq_putc(seq, '\n'); | |
4397 | sop = 1; | |
4398 | } | |
4399 | } | |
4400 | ||
4401 | seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", | |
4402 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), | |
c409c34b | 4403 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), |
3cf26753 SH |
4404 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); |
4405 | ||
d1d08d12 | 4406 | sky2_read32(hw, B0_Y2_SP_LISR); |
bea3348e | 4407 | napi_enable(&hw->napi); |
3cf26753 SH |
4408 | return 0; |
4409 | } | |
4410 | ||
4411 | static int sky2_debug_open(struct inode *inode, struct file *file) | |
4412 | { | |
4413 | return single_open(file, sky2_debug_show, inode->i_private); | |
4414 | } | |
4415 | ||
4416 | static const struct file_operations sky2_debug_fops = { | |
4417 | .owner = THIS_MODULE, | |
4418 | .open = sky2_debug_open, | |
4419 | .read = seq_read, | |
4420 | .llseek = seq_lseek, | |
4421 | .release = single_release, | |
4422 | }; | |
4423 | ||
4424 | /* | |
4425 | * Use network device events to create/remove/rename | |
4426 | * debugfs file entries | |
4427 | */ | |
4428 | static int sky2_device_event(struct notifier_block *unused, | |
4429 | unsigned long event, void *ptr) | |
4430 | { | |
4431 | struct net_device *dev = ptr; | |
5b296bc9 | 4432 | struct sky2_port *sky2 = netdev_priv(dev); |
3cf26753 | 4433 | |
1436b301 | 4434 | if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug) |
5b296bc9 | 4435 | return NOTIFY_DONE; |
3cf26753 | 4436 | |
060b946c | 4437 | switch (event) { |
5b296bc9 SH |
4438 | case NETDEV_CHANGENAME: |
4439 | if (sky2->debugfs) { | |
4440 | sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, | |
4441 | sky2_debug, dev->name); | |
4442 | } | |
4443 | break; | |
3cf26753 | 4444 | |
5b296bc9 SH |
4445 | case NETDEV_GOING_DOWN: |
4446 | if (sky2->debugfs) { | |
ada1db5c | 4447 | netdev_printk(KERN_DEBUG, dev, "remove debugfs\n"); |
5b296bc9 SH |
4448 | debugfs_remove(sky2->debugfs); |
4449 | sky2->debugfs = NULL; | |
3cf26753 | 4450 | } |
5b296bc9 SH |
4451 | break; |
4452 | ||
4453 | case NETDEV_UP: | |
4454 | sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO, | |
4455 | sky2_debug, dev, | |
4456 | &sky2_debug_fops); | |
4457 | if (IS_ERR(sky2->debugfs)) | |
4458 | sky2->debugfs = NULL; | |
3cf26753 SH |
4459 | } |
4460 | ||
4461 | return NOTIFY_DONE; | |
4462 | } | |
4463 | ||
4464 | static struct notifier_block sky2_notifier = { | |
4465 | .notifier_call = sky2_device_event, | |
4466 | }; | |
4467 | ||
4468 | ||
4469 | static __init void sky2_debug_init(void) | |
4470 | { | |
4471 | struct dentry *ent; | |
4472 | ||
4473 | ent = debugfs_create_dir("sky2", NULL); | |
4474 | if (!ent || IS_ERR(ent)) | |
4475 | return; | |
4476 | ||
4477 | sky2_debug = ent; | |
4478 | register_netdevice_notifier(&sky2_notifier); | |
4479 | } | |
4480 | ||
4481 | static __exit void sky2_debug_cleanup(void) | |
4482 | { | |
4483 | if (sky2_debug) { | |
4484 | unregister_netdevice_notifier(&sky2_notifier); | |
4485 | debugfs_remove(sky2_debug); | |
4486 | sky2_debug = NULL; | |
4487 | } | |
4488 | } | |
4489 | ||
4490 | #else | |
4491 | #define sky2_debug_init() | |
4492 | #define sky2_debug_cleanup() | |
4493 | #endif | |
4494 | ||
1436b301 SH |
4495 | /* Two copies of network device operations to handle special case of |
4496 | not allowing netpoll on second port */ | |
4497 | static const struct net_device_ops sky2_netdev_ops[2] = { | |
4498 | { | |
4499 | .ndo_open = sky2_up, | |
4500 | .ndo_stop = sky2_down, | |
00829823 | 4501 | .ndo_start_xmit = sky2_xmit_frame, |
1436b301 SH |
4502 | .ndo_do_ioctl = sky2_ioctl, |
4503 | .ndo_validate_addr = eth_validate_addr, | |
4504 | .ndo_set_mac_address = sky2_set_mac_address, | |
4505 | .ndo_set_multicast_list = sky2_set_multicast, | |
4506 | .ndo_change_mtu = sky2_change_mtu, | |
f5d64037 MM |
4507 | .ndo_fix_features = sky2_fix_features, |
4508 | .ndo_set_features = sky2_set_features, | |
1436b301 | 4509 | .ndo_tx_timeout = sky2_tx_timeout, |
0885a30b | 4510 | .ndo_get_stats64 = sky2_get_stats, |
1436b301 SH |
4511 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4512 | .ndo_poll_controller = sky2_netpoll, | |
4513 | #endif | |
4514 | }, | |
4515 | { | |
4516 | .ndo_open = sky2_up, | |
4517 | .ndo_stop = sky2_down, | |
00829823 | 4518 | .ndo_start_xmit = sky2_xmit_frame, |
1436b301 SH |
4519 | .ndo_do_ioctl = sky2_ioctl, |
4520 | .ndo_validate_addr = eth_validate_addr, | |
4521 | .ndo_set_mac_address = sky2_set_mac_address, | |
4522 | .ndo_set_multicast_list = sky2_set_multicast, | |
4523 | .ndo_change_mtu = sky2_change_mtu, | |
f5d64037 MM |
4524 | .ndo_fix_features = sky2_fix_features, |
4525 | .ndo_set_features = sky2_set_features, | |
1436b301 | 4526 | .ndo_tx_timeout = sky2_tx_timeout, |
0885a30b | 4527 | .ndo_get_stats64 = sky2_get_stats, |
1436b301 SH |
4528 | }, |
4529 | }; | |
3cf26753 | 4530 | |
cd28ab6a SH |
4531 | /* Initialize network device */ |
4532 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |
e3173832 | 4533 | unsigned port, |
be63a21c | 4534 | int highmem, int wol) |
cd28ab6a SH |
4535 | { |
4536 | struct sky2_port *sky2; | |
4537 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
4538 | ||
4539 | if (!dev) { | |
898eb71c | 4540 | dev_err(&hw->pdev->dev, "etherdev alloc failed\n"); |
cd28ab6a SH |
4541 | return NULL; |
4542 | } | |
4543 | ||
cd28ab6a | 4544 | SET_NETDEV_DEV(dev, &hw->pdev->dev); |
ef743d33 | 4545 | dev->irq = hw->pdev->irq; |
cd28ab6a | 4546 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); |
cd28ab6a | 4547 | dev->watchdog_timeo = TX_WATCHDOG; |
1436b301 | 4548 | dev->netdev_ops = &sky2_netdev_ops[port]; |
cd28ab6a SH |
4549 | |
4550 | sky2 = netdev_priv(dev); | |
4551 | sky2->netdev = dev; | |
4552 | sky2->hw = hw; | |
4553 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
4554 | ||
cd28ab6a | 4555 | /* Auto speed and flow control */ |
0ea065e5 SH |
4556 | sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; |
4557 | if (hw->chip_id != CHIP_ID_YUKON_XL) | |
f5d64037 | 4558 | dev->hw_features |= NETIF_F_RXCSUM; |
0ea065e5 | 4559 | |
16ad91e1 SH |
4560 | sky2->flow_mode = FC_BOTH; |
4561 | ||
cd28ab6a SH |
4562 | sky2->duplex = -1; |
4563 | sky2->speed = -1; | |
4564 | sky2->advertising = sky2_supported_modes(hw); | |
be63a21c | 4565 | sky2->wol = wol; |
75d070c5 | 4566 | |
e07b1aa8 | 4567 | spin_lock_init(&sky2->phy_lock); |
ee5f68fe | 4568 | |
793b883e | 4569 | sky2->tx_pending = TX_DEF_PENDING; |
ee5f68fe | 4570 | sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1); |
290d4de5 | 4571 | sky2->rx_pending = RX_DEF_PENDING; |
cd28ab6a SH |
4572 | |
4573 | hw->dev[port] = dev; | |
4574 | ||
4575 | sky2->port = port; | |
4576 | ||
f5d64037 | 4577 | dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO; |
86aa7785 | 4578 | |
cd28ab6a SH |
4579 | if (highmem) |
4580 | dev->features |= NETIF_F_HIGHDMA; | |
cd28ab6a | 4581 | |
bf73130d SH |
4582 | /* Enable receive hashing unless hardware is known broken */ |
4583 | if (!(hw->flags & SKY2_HW_RSS_BROKEN)) | |
f5d64037 MM |
4584 | dev->hw_features |= NETIF_F_RXHASH; |
4585 | ||
4586 | if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { | |
4587 | dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
4588 | dev->vlan_features |= SKY2_VLAN_OFFLOADS; | |
4589 | } | |
bf73130d | 4590 | |
f5d64037 | 4591 | dev->features |= dev->hw_features; |
d1f13708 | 4592 | |
cd28ab6a | 4593 | /* read the mac address */ |
793b883e | 4594 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
2995bfb7 | 4595 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
cd28ab6a | 4596 | |
cd28ab6a SH |
4597 | return dev; |
4598 | } | |
4599 | ||
28bd181a | 4600 | static void __devinit sky2_show_addr(struct net_device *dev) |
cd28ab6a SH |
4601 | { |
4602 | const struct sky2_port *sky2 = netdev_priv(dev); | |
4603 | ||
6c35abae | 4604 | netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr); |
cd28ab6a SH |
4605 | } |
4606 | ||
fb2690a9 | 4607 | /* Handle software interrupt used during MSI test */ |
7d12e780 | 4608 | static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id) |
fb2690a9 SH |
4609 | { |
4610 | struct sky2_hw *hw = dev_id; | |
4611 | u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
4612 | ||
4613 | if (status == 0) | |
4614 | return IRQ_NONE; | |
4615 | ||
4616 | if (status & Y2_IS_IRQ_SW) { | |
ea76e635 | 4617 | hw->flags |= SKY2_HW_USE_MSI; |
fb2690a9 SH |
4618 | wake_up(&hw->msi_wait); |
4619 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
4620 | } | |
4621 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | |
4622 | ||
4623 | return IRQ_HANDLED; | |
4624 | } | |
4625 | ||
4626 | /* Test interrupt path by forcing a a software IRQ */ | |
4627 | static int __devinit sky2_test_msi(struct sky2_hw *hw) | |
4628 | { | |
4629 | struct pci_dev *pdev = hw->pdev; | |
4630 | int err; | |
4631 | ||
060b946c | 4632 | init_waitqueue_head(&hw->msi_wait); |
bb507fe1 | 4633 | |
fb2690a9 SH |
4634 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); |
4635 | ||
b0a20ded | 4636 | err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); |
fb2690a9 | 4637 | if (err) { |
b02a9258 | 4638 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); |
fb2690a9 SH |
4639 | return err; |
4640 | } | |
4641 | ||
fb2690a9 | 4642 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); |
bb507fe1 | 4643 | sky2_read8(hw, B0_CTST); |
fb2690a9 | 4644 | |
ea76e635 | 4645 | wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); |
fb2690a9 | 4646 | |
ea76e635 | 4647 | if (!(hw->flags & SKY2_HW_USE_MSI)) { |
fb2690a9 | 4648 | /* MSI test failed, go back to INTx mode */ |
b02a9258 SH |
4649 | dev_info(&pdev->dev, "No interrupt generated using MSI, " |
4650 | "switching to INTx mode.\n"); | |
fb2690a9 SH |
4651 | |
4652 | err = -EOPNOTSUPP; | |
4653 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
4654 | } | |
4655 | ||
4656 | sky2_write32(hw, B0_IMSK, 0); | |
2bffc23a | 4657 | sky2_read32(hw, B0_IMSK); |
fb2690a9 SH |
4658 | |
4659 | free_irq(pdev->irq, hw); | |
4660 | ||
4661 | return err; | |
4662 | } | |
4663 | ||
c7127a34 SH |
4664 | /* This driver supports yukon2 chipset only */ |
4665 | static const char *sky2_name(u8 chipid, char *buf, int sz) | |
4666 | { | |
4667 | const char *name[] = { | |
4668 | "XL", /* 0xb3 */ | |
4669 | "EC Ultra", /* 0xb4 */ | |
4670 | "Extreme", /* 0xb5 */ | |
4671 | "EC", /* 0xb6 */ | |
4672 | "FE", /* 0xb7 */ | |
4673 | "FE+", /* 0xb8 */ | |
4674 | "Supreme", /* 0xb9 */ | |
0ce8b98d | 4675 | "UL 2", /* 0xba */ |
0f5aac70 SH |
4676 | "Unknown", /* 0xbb */ |
4677 | "Optima", /* 0xbc */ | |
c7127a34 SH |
4678 | }; |
4679 | ||
dae3a511 | 4680 | if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT) |
c7127a34 SH |
4681 | strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz); |
4682 | else | |
4683 | snprintf(buf, sz, "(chip %#x)", chipid); | |
4684 | return buf; | |
4685 | } | |
4686 | ||
cd28ab6a SH |
4687 | static int __devinit sky2_probe(struct pci_dev *pdev, |
4688 | const struct pci_device_id *ent) | |
4689 | { | |
7f60c64b | 4690 | struct net_device *dev; |
cd28ab6a | 4691 | struct sky2_hw *hw; |
be63a21c | 4692 | int err, using_dac = 0, wol_default; |
3834507d | 4693 | u32 reg; |
c7127a34 | 4694 | char buf1[16]; |
cd28ab6a | 4695 | |
793b883e SH |
4696 | err = pci_enable_device(pdev); |
4697 | if (err) { | |
b02a9258 | 4698 | dev_err(&pdev->dev, "cannot enable PCI device\n"); |
cd28ab6a SH |
4699 | goto err_out; |
4700 | } | |
4701 | ||
6cc90a5a SH |
4702 | /* Get configuration information |
4703 | * Note: only regular PCI config access once to test for HW issues | |
4704 | * other PCI access through shared memory for speed and to | |
4705 | * avoid MMCONFIG problems. | |
4706 | */ | |
4707 | err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
4708 | if (err) { | |
4709 | dev_err(&pdev->dev, "PCI read config failed\n"); | |
4710 | goto err_out; | |
4711 | } | |
4712 | ||
4713 | if (~reg == 0) { | |
4714 | dev_err(&pdev->dev, "PCI configuration read error\n"); | |
4715 | goto err_out; | |
4716 | } | |
4717 | ||
793b883e SH |
4718 | err = pci_request_regions(pdev, DRV_NAME); |
4719 | if (err) { | |
b02a9258 | 4720 | dev_err(&pdev->dev, "cannot obtain PCI resources\n"); |
44a1d2e5 | 4721 | goto err_out_disable; |
cd28ab6a SH |
4722 | } |
4723 | ||
4724 | pci_set_master(pdev); | |
4725 | ||
d1f3d4dd | 4726 | if (sizeof(dma_addr_t) > sizeof(u32) && |
6a35528a | 4727 | !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) { |
d1f3d4dd | 4728 | using_dac = 1; |
6a35528a | 4729 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
d1f3d4dd | 4730 | if (err < 0) { |
b02a9258 SH |
4731 | dev_err(&pdev->dev, "unable to obtain 64 bit DMA " |
4732 | "for consistent allocations\n"); | |
d1f3d4dd SH |
4733 | goto err_out_free_regions; |
4734 | } | |
d1f3d4dd | 4735 | } else { |
284901a9 | 4736 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cd28ab6a | 4737 | if (err) { |
b02a9258 | 4738 | dev_err(&pdev->dev, "no usable DMA configuration\n"); |
cd28ab6a SH |
4739 | goto err_out_free_regions; |
4740 | } | |
4741 | } | |
d1f3d4dd | 4742 | |
3834507d SH |
4743 | |
4744 | #ifdef __BIG_ENDIAN | |
4745 | /* The sk98lin vendor driver uses hardware byte swapping but | |
4746 | * this driver uses software swapping. | |
4747 | */ | |
4748 | reg &= ~PCI_REV_DESC; | |
060b946c | 4749 | err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); |
3834507d SH |
4750 | if (err) { |
4751 | dev_err(&pdev->dev, "PCI write config failed\n"); | |
4752 | goto err_out_free_regions; | |
4753 | } | |
4754 | #endif | |
4755 | ||
9d731d77 | 4756 | wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; |
be63a21c | 4757 | |
cd28ab6a | 4758 | err = -ENOMEM; |
66466797 SH |
4759 | |
4760 | hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") | |
4761 | + strlen(pci_name(pdev)) + 1, GFP_KERNEL); | |
cd28ab6a | 4762 | if (!hw) { |
b02a9258 | 4763 | dev_err(&pdev->dev, "cannot allocate hardware struct\n"); |
cd28ab6a SH |
4764 | goto err_out_free_regions; |
4765 | } | |
4766 | ||
cd28ab6a | 4767 | hw->pdev = pdev; |
66466797 | 4768 | sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); |
cd28ab6a SH |
4769 | |
4770 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
4771 | if (!hw->regs) { | |
b02a9258 | 4772 | dev_err(&pdev->dev, "cannot map device registers\n"); |
cd28ab6a SH |
4773 | goto err_out_free_hw; |
4774 | } | |
4775 | ||
e3173832 | 4776 | err = sky2_init(hw); |
cd28ab6a | 4777 | if (err) |
793b883e | 4778 | goto err_out_iounmap; |
cd28ab6a | 4779 | |
efe91932 | 4780 | /* ring for status responses */ |
bf73130d | 4781 | hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); |
efe91932 | 4782 | hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), |
4783 | &hw->st_dma); | |
4784 | if (!hw->st_le) | |
4785 | goto err_out_reset; | |
4786 | ||
c844d483 SH |
4787 | dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", |
4788 | sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); | |
cd28ab6a | 4789 | |
e3173832 SH |
4790 | sky2_reset(hw); |
4791 | ||
be63a21c | 4792 | dev = sky2_init_netdev(hw, 0, using_dac, wol_default); |
7f60c64b | 4793 | if (!dev) { |
4794 | err = -ENOMEM; | |
cd28ab6a | 4795 | goto err_out_free_pci; |
7f60c64b | 4796 | } |
cd28ab6a | 4797 | |
9fa1b1f3 SH |
4798 | if (!disable_msi && pci_enable_msi(pdev) == 0) { |
4799 | err = sky2_test_msi(hw); | |
4800 | if (err == -EOPNOTSUPP) | |
4801 | pci_disable_msi(pdev); | |
4802 | else if (err) | |
4803 | goto err_out_free_netdev; | |
4804 | } | |
4805 | ||
793b883e SH |
4806 | err = register_netdev(dev); |
4807 | if (err) { | |
b02a9258 | 4808 | dev_err(&pdev->dev, "cannot register net device\n"); |
cd28ab6a SH |
4809 | goto err_out_free_netdev; |
4810 | } | |
4811 | ||
33cb7d33 BP |
4812 | netif_carrier_off(dev); |
4813 | ||
6de16237 SH |
4814 | netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); |
4815 | ||
ea76e635 SH |
4816 | err = request_irq(pdev->irq, sky2_intr, |
4817 | (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, | |
66466797 | 4818 | hw->irq_name, hw); |
9fa1b1f3 | 4819 | if (err) { |
b02a9258 | 4820 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); |
9fa1b1f3 SH |
4821 | goto err_out_unregister; |
4822 | } | |
4823 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); | |
6de16237 | 4824 | napi_enable(&hw->napi); |
9fa1b1f3 | 4825 | |
cd28ab6a SH |
4826 | sky2_show_addr(dev); |
4827 | ||
7f60c64b | 4828 | if (hw->ports > 1) { |
4829 | struct net_device *dev1; | |
4830 | ||
ca519274 | 4831 | err = -ENOMEM; |
be63a21c | 4832 | dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); |
ca519274 SH |
4833 | if (dev1 && (err = register_netdev(dev1)) == 0) |
4834 | sky2_show_addr(dev1); | |
4835 | else { | |
b02a9258 SH |
4836 | dev_warn(&pdev->dev, |
4837 | "register of second port failed (%d)\n", err); | |
cd28ab6a | 4838 | hw->dev[1] = NULL; |
ca519274 SH |
4839 | hw->ports = 1; |
4840 | if (dev1) | |
4841 | free_netdev(dev1); | |
4842 | } | |
cd28ab6a SH |
4843 | } |
4844 | ||
32c2c300 | 4845 | setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw); |
81906791 SH |
4846 | INIT_WORK(&hw->restart_work, sky2_restart); |
4847 | ||
793b883e | 4848 | pci_set_drvdata(pdev, hw); |
1ae861e6 | 4849 | pdev->d3_delay = 150; |
793b883e | 4850 | |
cd28ab6a SH |
4851 | return 0; |
4852 | ||
793b883e | 4853 | err_out_unregister: |
ea76e635 | 4854 | if (hw->flags & SKY2_HW_USE_MSI) |
b0a20ded | 4855 | pci_disable_msi(pdev); |
793b883e | 4856 | unregister_netdev(dev); |
cd28ab6a SH |
4857 | err_out_free_netdev: |
4858 | free_netdev(dev); | |
cd28ab6a | 4859 | err_out_free_pci: |
efe91932 | 4860 | pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), |
4861 | hw->st_le, hw->st_dma); | |
4862 | err_out_reset: | |
793b883e | 4863 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
4864 | err_out_iounmap: |
4865 | iounmap(hw->regs); | |
4866 | err_out_free_hw: | |
4867 | kfree(hw); | |
4868 | err_out_free_regions: | |
4869 | pci_release_regions(pdev); | |
44a1d2e5 | 4870 | err_out_disable: |
cd28ab6a | 4871 | pci_disable_device(pdev); |
cd28ab6a | 4872 | err_out: |
549a68c3 | 4873 | pci_set_drvdata(pdev, NULL); |
cd28ab6a SH |
4874 | return err; |
4875 | } | |
4876 | ||
4877 | static void __devexit sky2_remove(struct pci_dev *pdev) | |
4878 | { | |
793b883e | 4879 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
6de16237 | 4880 | int i; |
cd28ab6a | 4881 | |
793b883e | 4882 | if (!hw) |
cd28ab6a SH |
4883 | return; |
4884 | ||
32c2c300 | 4885 | del_timer_sync(&hw->watchdog_timer); |
6de16237 | 4886 | cancel_work_sync(&hw->restart_work); |
d27ed387 | 4887 | |
b877fe28 | 4888 | for (i = hw->ports-1; i >= 0; --i) |
6de16237 | 4889 | unregister_netdev(hw->dev[i]); |
81906791 | 4890 | |
d27ed387 | 4891 | sky2_write32(hw, B0_IMSK, 0); |
cd28ab6a | 4892 | |
ae306cca SH |
4893 | sky2_power_aux(hw); |
4894 | ||
793b883e | 4895 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 4896 | sky2_read8(hw, B0_CTST); |
cd28ab6a SH |
4897 | |
4898 | free_irq(pdev->irq, hw); | |
ea76e635 | 4899 | if (hw->flags & SKY2_HW_USE_MSI) |
b0a20ded | 4900 | pci_disable_msi(pdev); |
efe91932 | 4901 | pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), |
4902 | hw->st_le, hw->st_dma); | |
cd28ab6a SH |
4903 | pci_release_regions(pdev); |
4904 | pci_disable_device(pdev); | |
793b883e | 4905 | |
b877fe28 | 4906 | for (i = hw->ports-1; i >= 0; --i) |
6de16237 SH |
4907 | free_netdev(hw->dev[i]); |
4908 | ||
cd28ab6a SH |
4909 | iounmap(hw->regs); |
4910 | kfree(hw); | |
5afa0a9c | 4911 | |
cd28ab6a SH |
4912 | pci_set_drvdata(pdev, NULL); |
4913 | } | |
4914 | ||
0f333d10 | 4915 | static int sky2_suspend(struct device *dev) |
cd28ab6a | 4916 | { |
0f333d10 | 4917 | struct pci_dev *pdev = to_pci_dev(dev); |
793b883e | 4918 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
0f333d10 | 4919 | int i; |
cd28ab6a | 4920 | |
549a68c3 SH |
4921 | if (!hw) |
4922 | return 0; | |
4923 | ||
063a0b38 SH |
4924 | del_timer_sync(&hw->watchdog_timer); |
4925 | cancel_work_sync(&hw->restart_work); | |
4926 | ||
19720737 | 4927 | rtnl_lock(); |
3403aca2 MM |
4928 | |
4929 | sky2_all_down(hw); | |
f05267e7 | 4930 | for (i = 0; i < hw->ports; i++) { |
cd28ab6a | 4931 | struct net_device *dev = hw->dev[i]; |
e3173832 | 4932 | struct sky2_port *sky2 = netdev_priv(dev); |
cd28ab6a | 4933 | |
e3173832 SH |
4934 | if (sky2->wol) |
4935 | sky2_wol_init(sky2); | |
cd28ab6a SH |
4936 | } |
4937 | ||
ae306cca | 4938 | sky2_power_aux(hw); |
19720737 | 4939 | rtnl_unlock(); |
e3173832 | 4940 | |
2ccc99b7 | 4941 | return 0; |
cd28ab6a SH |
4942 | } |
4943 | ||
94252763 | 4944 | #ifdef CONFIG_PM_SLEEP |
0f333d10 | 4945 | static int sky2_resume(struct device *dev) |
cd28ab6a | 4946 | { |
0f333d10 | 4947 | struct pci_dev *pdev = to_pci_dev(dev); |
793b883e | 4948 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
3403aca2 | 4949 | int err; |
cd28ab6a | 4950 | |
549a68c3 SH |
4951 | if (!hw) |
4952 | return 0; | |
4953 | ||
1ad5b4a5 | 4954 | /* Re-enable all clocks */ |
a0db28b8 | 4955 | err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0); |
4956 | if (err) { | |
4957 | dev_err(&pdev->dev, "PCI write config failed\n"); | |
4958 | goto out; | |
4959 | } | |
1ad5b4a5 | 4960 | |
3403aca2 | 4961 | rtnl_lock(); |
e3173832 | 4962 | sky2_reset(hw); |
3403aca2 | 4963 | sky2_all_up(hw); |
af18d8b8 | 4964 | rtnl_unlock(); |
eb35cf60 | 4965 | |
ae306cca | 4966 | return 0; |
08c06d8a | 4967 | out: |
af18d8b8 | 4968 | |
b02a9258 | 4969 | dev_err(&pdev->dev, "resume failed (%d)\n", err); |
ae306cca | 4970 | pci_disable_device(pdev); |
08c06d8a | 4971 | return err; |
cd28ab6a | 4972 | } |
0f333d10 RW |
4973 | |
4974 | static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); | |
4975 | #define SKY2_PM_OPS (&sky2_pm_ops) | |
4976 | ||
4977 | #else | |
4978 | ||
4979 | #define SKY2_PM_OPS NULL | |
cd28ab6a SH |
4980 | #endif |
4981 | ||
e3173832 SH |
4982 | static void sky2_shutdown(struct pci_dev *pdev) |
4983 | { | |
0f333d10 RW |
4984 | sky2_suspend(&pdev->dev); |
4985 | pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); | |
4986 | pci_set_power_state(pdev, PCI_D3hot); | |
e3173832 SH |
4987 | } |
4988 | ||
cd28ab6a | 4989 | static struct pci_driver sky2_driver = { |
793b883e SH |
4990 | .name = DRV_NAME, |
4991 | .id_table = sky2_id_table, | |
4992 | .probe = sky2_probe, | |
4993 | .remove = __devexit_p(sky2_remove), | |
e3173832 | 4994 | .shutdown = sky2_shutdown, |
0f333d10 | 4995 | .driver.pm = SKY2_PM_OPS, |
cd28ab6a SH |
4996 | }; |
4997 | ||
4998 | static int __init sky2_init_module(void) | |
4999 | { | |
ada1db5c | 5000 | pr_info("driver version " DRV_VERSION "\n"); |
c844d483 | 5001 | |
3cf26753 | 5002 | sky2_debug_init(); |
50241c4c | 5003 | return pci_register_driver(&sky2_driver); |
cd28ab6a SH |
5004 | } |
5005 | ||
5006 | static void __exit sky2_cleanup_module(void) | |
5007 | { | |
5008 | pci_unregister_driver(&sky2_driver); | |
3cf26753 | 5009 | sky2_debug_cleanup(); |
cd28ab6a SH |
5010 | } |
5011 | ||
5012 | module_init(sky2_init_module); | |
5013 | module_exit(sky2_cleanup_module); | |
5014 | ||
5015 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
65ebe634 | 5016 | MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); |
cd28ab6a | 5017 | MODULE_LICENSE("GPL"); |
5f4f9dc1 | 5018 | MODULE_VERSION(DRV_VERSION); |