sky2: simplify list element error
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH
1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
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14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
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18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
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27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
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30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
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43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
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50#include "sky2.h"
51
52#define DRV_NAME "sky2"
deeb16dc 53#define DRV_VERSION "1.24"
cd28ab6a
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54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH
60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH
66
67#define TX_RING_SIZE 512
e9c1be80 68#define TX_DEF_PENDING 128
b19666d9 69#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
cd28ab6a 71
793b883e 72#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 73#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH
74#define TX_WATCHDOG (5 * HZ)
75#define NAPI_WEIGHT 64
76#define PHY_RETRIES 1000
77
f4331a6d
SH
78#define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
cb5d9547
SH
81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH
89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
14d0263f 92static int copybreak __read_mostly = 128;
bdb5c58e
SH
93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH
96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
e6cac9ba 100static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
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140 { 0 }
141};
793b883e 142
cd28ab6a
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143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0
SH
150static void sky2_set_multicast(struct net_device *dev);
151
af043aa5 152/* Access to PHY via serial interconnect */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH
154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
af043aa5
SH
168
169 udelay(10);
cd28ab6a 170 }
ef743d33 171
af043aa5 172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 173 return -ETIMEDOUT;
af043aa5
SH
174
175io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
cd28ab6a
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178}
179
ef743d33 180static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
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181{
182 int i;
183
793b883e 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
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185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
af043aa5 197 udelay(10);
cd28ab6a
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198 }
199
af043aa5 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 201 return -ETIMEDOUT;
af043aa5
SH
202io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
ef743d33 205}
206
af043aa5 207static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 208{
209 u16 v;
af043aa5 210 __gm_phy_read(hw, port, reg, &v);
ef743d33 211 return v;
cd28ab6a
SH
212}
213
5afa0a9c 214
ae306cca
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215static void sky2_power_on(struct sky2_hw *hw)
216{
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 220
ae306cca
SH
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 223
ae306cca
SH
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 232
ea76e635 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 234 u32 reg;
5afa0a9c 235
b32f40c4 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 237
b32f40c4 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 247
b32f40c4 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH
249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH
254
255 sky2_read32(hw, B2_GP_IO);
5afa0a9c 256 }
ae306cca 257}
5afa0a9c 258
ae306cca
SH
259static void sky2_power_aux(struct sky2_hw *hw)
260{
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 275}
276
d3bcfbeb 277static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH
278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 283
cd28ab6a
SH
284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
16ad91e1
SH
294/* flow control to advertise bits */
295static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300};
301
302/* flow control to advertise bits when using 1000BaseX */
303static const u16 fiber_fc_adv[] = {
df3fe1f3 304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH
305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH
308};
309
310/* flow control to GMA disable bits */
311static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316};
317
318
cd28ab6a
SH
319static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320{
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 323
0ea065e5 324 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH
326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 329 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH
330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
53419c68 332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 333 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 334 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH
335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
53419c68
SH
337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH
339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 344 if (sky2_is_copper(hw)) {
05745c4a 345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH
346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH
348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
cd28ab6a
SH
358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
53419c68 365 /* downshift on PHY 88E1112 and 88E1149 is changed */
0ea065e5 366 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED)
ea76e635 367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 368 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH
369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
cd28ab6a
SH
373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 378 }
cd28ab6a 379
b89165f2
SH
380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
ea76e635 383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 385
b89165f2
SH
386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
cd28ab6a
SH
394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH
396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 401 }
b89165f2
SH
402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH
404 }
405
7800fddc 406 ctrl = PHY_CT_RESET;
cd28ab6a
SH
407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
2eaba1a2 409 reg = 0;
cd28ab6a 410
0ea065e5 411 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 412 if (sky2_is_copper(hw)) {
cd28ab6a
SH
413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
709c6e7b 425
b89165f2
SH
426 } else { /* special defines for FIBER (88E1040S only) */
427 if (sky2->advertising & ADVERTISED_1000baseT_Full)
428 adv |= PHY_M_AN_1000X_AFD;
429 if (sky2->advertising & ADVERTISED_1000baseT_Half)
430 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 431 }
cd28ab6a
SH
432
433 /* Restart Auto-negotiation */
434 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
435 } else {
436 /* forced speed/duplex settings */
437 ct1000 = PHY_M_1000C_MSE;
438
0ea065e5
SH
439 /* Disable auto update for duplex flow control and duplex */
440 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH
441
442 switch (sky2->speed) {
443 case SPEED_1000:
444 ctrl |= PHY_CT_SP1000;
2eaba1a2 445 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH
446 break;
447 case SPEED_100:
448 ctrl |= PHY_CT_SP100;
2eaba1a2 449 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH
450 break;
451 }
452
2eaba1a2
SH
453 if (sky2->duplex == DUPLEX_FULL) {
454 reg |= GM_GPCR_DUP_FULL;
455 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH
456 } else if (sky2->speed < SPEED_1000)
457 sky2->flow_mode = FC_NONE;
0ea065e5 458 }
2eaba1a2 459
0ea065e5
SH
460 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
461 if (sky2_is_copper(hw))
462 adv |= copper_fc_adv[sky2->flow_mode];
463 else
464 adv |= fiber_fc_adv[sky2->flow_mode];
465 } else {
466 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 467 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH
468
469 /* Forward pause packets to GMAC? */
16ad91e1 470 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH
471 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
472 else
473 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH
474 }
475
2eaba1a2
SH
476 gma_write16(hw, port, GM_GP_CTRL, reg);
477
05745c4a 478 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH
479 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
480
481 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
482 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
483
484 /* Setup Phy LED's */
485 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
486 ledover = 0;
487
488 switch (hw->chip_id) {
489 case CHIP_ID_YUKON_FE:
490 /* on 88E3082 these bits are at 11..9 (shifted left) */
491 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
492
493 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
494
495 /* delete ACT LED control bits */
496 ctrl &= ~PHY_M_FELP_LED1_MSK;
497 /* change ACT LED control to blink mode */
498 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
499 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
500 break;
501
05745c4a
SH
502 case CHIP_ID_YUKON_FE_P:
503 /* Enable Link Partner Next Page */
504 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
505 ctrl |= PHY_M_PC_ENA_LIP_NP;
506
507 /* disable Energy Detect and enable scrambler */
508 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
509 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
510
511 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
512 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
513 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
514 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
515
516 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
517 break;
518
cd28ab6a 519 case CHIP_ID_YUKON_XL:
793b883e 520 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH
521
522 /* select page 3 to access LED control register */
523 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
524
525 /* set LED Function Control register */
ed6d32c7
SH
526 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
527 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
528 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
529 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
530 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH
531
532 /* set Polarity Control register */
533 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH
534 (PHY_M_POLC_LS1_P_MIX(4) |
535 PHY_M_POLC_IS0_P_MIX(4) |
536 PHY_M_POLC_LOS_CTRL(2) |
537 PHY_M_POLC_INIT_CTRL(2) |
538 PHY_M_POLC_STA1_CTRL(2) |
539 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH
540
541 /* restore page register */
793b883e 542 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 543 break;
93745494 544
ed6d32c7 545 case CHIP_ID_YUKON_EC_U:
93745494 546 case CHIP_ID_YUKON_EX:
ed4d4161 547 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH
548 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
549
550 /* select page 3 to access LED control register */
551 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
552
553 /* set LED Function Control register */
554 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
555 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
556 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
557 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
558 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
559
560 /* set Blink Rate in LED Timer Control Register */
561 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
562 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
563 /* restore page register */
564 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
565 break;
cd28ab6a
SH
566
567 default:
568 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
569 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 570
cd28ab6a 571 /* turn off the Rx LED (LED_RX) */
a84d0a3d 572 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH
573 }
574
0ce8b98d 575 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 576 /* apply fixes in PHY AFE */
ed6d32c7
SH
577 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
578
977bdf06 579 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH
580 gm_phy_write(hw, port, 0x18, 0xaa99);
581 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 582
0ce8b98d
SH
583 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
584 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
585 gm_phy_write(hw, port, 0x18, 0xa204);
586 gm_phy_write(hw, port, 0x17, 0x2002);
587 }
977bdf06
SH
588
589 /* set page register to 0 */
9467a8fc 590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH
591 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
592 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
593 /* apply workaround for integrated resistors calibration */
594 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
595 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH
596 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
597 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 598 /* no effect on Yukon-XL */
977bdf06 599 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 600
0ea065e5
SH
601 if ( !(sky2->flags & SKY2_FLAG_AUTO_SPEED)
602 || sky2->speed == SPEED_100) {
977bdf06 603 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 604 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 605 }
cd28ab6a 606
977bdf06
SH
607 if (ledover)
608 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
609
610 }
2eaba1a2 611
d571b694 612 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 613 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH
614 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
615 else
616 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
617}
618
b96936da
SH
619static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
620static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
621
622static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 623{
624 u32 reg1;
d3bcfbeb 625
82637e80 626 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 627 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 628 reg1 &= ~phy_power[port];
d3bcfbeb 629
b96936da 630 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH
631 reg1 |= coma_mode[port];
632
b32f40c4 633 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH
634 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
635 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH
636
637 if (hw->chip_id == CHIP_ID_YUKON_FE)
638 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
639 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
640 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 641}
167f53d0 642
b96936da
SH
643static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
644{
645 u32 reg1;
db99b988
SH
646 u16 ctrl;
647
648 /* release GPHY Control reset */
649 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
650
651 /* release GMAC reset */
652 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
653
654 if (hw->flags & SKY2_HW_NEWER_PHY) {
655 /* select page 2 to access MAC control register */
656 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
657
658 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
659 /* allow GMII Power Down */
660 ctrl &= ~PHY_M_MAC_GMIF_PUP;
661 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
662
663 /* set page register back to 0 */
664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
665 }
666
667 /* setup General Purpose Control Register */
668 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH
669 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
670 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
671 GM_GPCR_AU_SPD_DIS);
db99b988
SH
672
673 if (hw->chip_id != CHIP_ID_YUKON_EC) {
674 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW
675 /* select page 2 to access MAC control register */
676 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 677
e484d5f5 678 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH
679 /* enable Power Down */
680 ctrl |= PHY_M_PC_POW_D_ENA;
681 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW
682
683 /* set page register back to 0 */
684 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH
685 }
686
687 /* set IEEE compatible Power Down Mode (dev. #4.99) */
688 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
689 }
b96936da
SH
690
691 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
692 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 693 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH
694 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
695 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 696}
697
1b537565
SH
698/* Force a renegotiation */
699static void sky2_phy_reinit(struct sky2_port *sky2)
700{
e07b1aa8 701 spin_lock_bh(&sky2->phy_lock);
1b537565 702 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 703 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH
704}
705
e3173832
SH
706/* Put device in state to listen for Wake On Lan */
707static void sky2_wol_init(struct sky2_port *sky2)
708{
709 struct sky2_hw *hw = sky2->hw;
710 unsigned port = sky2->port;
711 enum flow_control save_mode;
712 u16 ctrl;
713 u32 reg1;
714
715 /* Bring hardware out of reset */
716 sky2_write16(hw, B0_CTST, CS_RST_CLR);
717 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
718
719 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
720 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
721
722 /* Force to 10/100
723 * sky2_reset will re-enable on resume
724 */
725 save_mode = sky2->flow_mode;
726 ctrl = sky2->advertising;
727
728 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
729 sky2->flow_mode = FC_NONE;
b96936da
SH
730
731 spin_lock_bh(&sky2->phy_lock);
732 sky2_phy_power_up(hw, port);
733 sky2_phy_init(hw, port);
734 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH
735
736 sky2->flow_mode = save_mode;
737 sky2->advertising = ctrl;
738
739 /* Set GMAC to no flow control and auto update for speed/duplex */
740 gma_write16(hw, port, GM_GP_CTRL,
741 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
742 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
743
744 /* Set WOL address */
745 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
746 sky2->netdev->dev_addr, ETH_ALEN);
747
748 /* Turn on appropriate WOL control bits */
749 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
750 ctrl = 0;
751 if (sky2->wol & WAKE_PHY)
752 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
753 else
754 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
755
756 if (sky2->wol & WAKE_MAGIC)
757 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
758 else
759 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
760
761 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
762 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
763
764 /* Turn on legacy PCI-Express PME mode */
b32f40c4 765 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 766 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 767 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH
768
769 /* block receiver */
770 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
771
772}
773
69161611
SH
774static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
775{
05745c4a
SH
776 struct net_device *dev = hw->dev[port];
777
ed4d4161
SH
778 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
779 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
780 hw->chip_id == CHIP_ID_YUKON_FE_P ||
781 hw->chip_id == CHIP_ID_YUKON_SUPR) {
782 /* Yukon-Extreme B0 and further Extreme devices */
783 /* enable Store & Forward mode for TX */
05745c4a 784
ed4d4161
SH
785 if (dev->mtu <= ETH_DATA_LEN)
786 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
787 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 788
ed4d4161
SH
789 else
790 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
791 TX_JUMBO_ENA| TX_STFW_ENA);
792 } else {
793 if (dev->mtu <= ETH_DATA_LEN)
794 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
795 else {
796 /* set Tx GMAC FIFO Almost Empty Threshold */
797 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
798 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 799
ed4d4161
SH
800 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
801
802 /* Can't do offload because of lack of store/forward */
803 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
804 }
69161611
SH
805 }
806}
807
cd28ab6a
SH
808static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
809{
810 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
811 u16 reg;
25cccecc 812 u32 rx_reg;
cd28ab6a
SH
813 int i;
814 const u8 *addr = hw->dev[port]->dev_addr;
815
f350339c
SH
816 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
817 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH
818
819 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
820
793b883e 821 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH
822 /* WA DEV_472 -- looks like crossed wires on port 2 */
823 /* clear GMAC 1 Control reset */
824 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
825 do {
826 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
827 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
828 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
829 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
830 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
831 }
832
793b883e 833 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 834
2eaba1a2
SH
835 /* Enable Transmit FIFO Underrun */
836 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
837
e07b1aa8 838 spin_lock_bh(&sky2->phy_lock);
b96936da 839 sky2_phy_power_up(hw, port);
cd28ab6a 840 sky2_phy_init(hw, port);
e07b1aa8 841 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH
842
843 /* MIB clear */
844 reg = gma_read16(hw, port, GM_PHY_ADDR);
845 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
846
43f2f104
SH
847 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
848 gma_read16(hw, port, i);
cd28ab6a
SH
849 gma_write16(hw, port, GM_PHY_ADDR, reg);
850
851 /* transmit control */
852 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
853
854 /* receive control reg: unicast + multicast + no FCS */
855 gma_write16(hw, port, GM_RX_CTRL,
793b883e 856 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH
857
858 /* transmit flow control */
859 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
860
861 /* transmit parameter */
862 gma_write16(hw, port, GM_TX_PARAM,
863 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
864 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
865 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
866 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
867
868 /* serial mode register */
869 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 870 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 871
6b1a3aef 872 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH
873 reg |= GM_SMOD_JUMBO_ENA;
874
875 gma_write16(hw, port, GM_SERIAL_MODE, reg);
876
cd28ab6a
SH
877 /* virtual address for data */
878 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
879
793b883e
SH
880 /* physical address: used for pause frames */
881 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
882
883 /* ignore counter overflows */
cd28ab6a
SH
884 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
885 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
886 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
887
888 /* Configure Rx MAC FIFO */
889 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 890 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH
891 if (hw->chip_id == CHIP_ID_YUKON_EX ||
892 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 893 rx_reg |= GMF_RX_OVER_ON;
69161611 894
25cccecc 895 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 896
798fdd07
SH
897 if (hw->chip_id == CHIP_ID_YUKON_XL) {
898 /* Hardware errata - clear flush mask */
899 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
900 } else {
901 /* Flush Rx MAC FIFO on any flow control or error */
902 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
903 }
cd28ab6a 904
8df9a876 905 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH
906 reg = RX_GMF_FL_THR_DEF + 1;
907 /* Another magic mystery workaround from sk98lin */
908 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
909 hw->chip_rev == CHIP_REV_YU_FE2_A0)
910 reg = 0x178;
911 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH
912
913 /* Configure Tx MAC FIFO */
914 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
915 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 916
e0c28116 917 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 918 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 919 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 920 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 921
69161611 922 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 923 }
924
e970d1f8
SH
925 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
926 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
927 /* disable dynamic watermark */
928 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
929 reg &= ~TX_DYN_WM_ENA;
930 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
931 }
cd28ab6a
SH
932}
933
67712901
SH
934/* Assign Ram Buffer allocation to queue */
935static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 936{
67712901
SH
937 u32 end;
938
939 /* convert from K bytes to qwords used for hw register */
940 start *= 1024/8;
941 space *= 1024/8;
942 end = start + space - 1;
793b883e 943
cd28ab6a
SH
944 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
945 sky2_write32(hw, RB_ADDR(q, RB_START), start);
946 sky2_write32(hw, RB_ADDR(q, RB_END), end);
947 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
948 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
949
950 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 951 u32 tp = space - space/4;
793b883e 952
1c28f6ba
SH
953 /* On receive queue's set the thresholds
954 * give receiver priority when > 3/4 full
955 * send pause when down to 2K
956 */
957 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
958 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 959
1c28f6ba
SH
960 tp = space - 2048/8;
961 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
962 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH
963 } else {
964 /* Enable store & forward on Tx queue's because
965 * Tx FIFO is only 1K on Yukon
966 */
967 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
968 }
969
970 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 971 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH
972}
973
cd28ab6a 974/* Setup Bus Memory Interface */
af4ed7e6 975static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH
976{
977 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
978 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
979 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 980 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH
981}
982
cd28ab6a
SH
983/* Setup prefetch unit registers. This is the interface between
984 * hardware and driver list elements
985 */
8cc048e3 986static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 987 dma_addr_t addr, u32 last)
cd28ab6a 988{
cd28ab6a
SH
989 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
990 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH
991 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
992 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH
993 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
994 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH
995
996 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH
997}
998
9b289c33 999static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1000{
9b289c33 1001 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1002
9b289c33 1003 *slot = RING_NEXT(*slot, TX_RING_SIZE);
291ea614 1004 le->ctrl = 0;
793b883e
SH
1005 return le;
1006}
cd28ab6a 1007
88f5f0ca
SH
1008static void tx_init(struct sky2_port *sky2)
1009{
1010 struct sky2_tx_le *le;
1011
1012 sky2->tx_prod = sky2->tx_cons = 0;
1013 sky2->tx_tcpsum = 0;
1014 sky2->tx_last_mss = 0;
1015
9b289c33 1016 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH
1017 le->addr = 0;
1018 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1019 sky2->tx_last_upper = 0;
88f5f0ca
SH
1020}
1021
291ea614
SH
1022static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1023 struct sky2_tx_le *le)
1024{
1025 return sky2->tx_ring + (le - sky2->tx_le);
1026}
1027
290d4de5
SH
1028/* Update chip's next pointer */
1029static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1030{
50432cb5 1031 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1032 wmb();
50432cb5
SH
1033 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1034
1035 /* Synchronize I/O on since next processor may write to tail */
1036 mmiowb();
cd28ab6a
SH
1037}
1038
793b883e 1039
cd28ab6a
SH
1040static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1041{
1042 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1043 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1044 le->ctrl = 0;
cd28ab6a
SH
1045 return le;
1046}
1047
14d0263f
SH
1048/* Build description to hardware for one receive segment */
1049static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1050 dma_addr_t map, unsigned len)
cd28ab6a
SH
1051{
1052 struct sky2_rx_le *le;
1053
86c6887e 1054 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1055 le = sky2_next_rx(sky2);
86c6887e 1056 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH
1057 le->opcode = OP_ADDR64 | HW_OWNER;
1058 }
793b883e 1059
cd28ab6a 1060 le = sky2_next_rx(sky2);
d6e74b6b 1061 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1062 le->length = cpu_to_le16(len);
14d0263f 1063 le->opcode = op | HW_OWNER;
cd28ab6a
SH
1064}
1065
14d0263f
SH
1066/* Build description to hardware for one possibly fragmented skb */
1067static void sky2_rx_submit(struct sky2_port *sky2,
1068 const struct rx_ring_info *re)
1069{
1070 int i;
1071
1072 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1073
1074 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1075 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1076}
1077
1078
454e6cb6 1079static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH
1080 unsigned size)
1081{
1082 struct sk_buff *skb = re->skb;
1083 int i;
1084
1085 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH
1086 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1087 return -EIO;
1088
14d0263f
SH
1089 pci_unmap_len_set(re, data_size, size);
1090
1091 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1092 re->frag_addr[i] = pci_map_page(pdev,
1093 skb_shinfo(skb)->frags[i].page,
1094 skb_shinfo(skb)->frags[i].page_offset,
1095 skb_shinfo(skb)->frags[i].size,
1096 PCI_DMA_FROMDEVICE);
454e6cb6 1097 return 0;
14d0263f
SH
1098}
1099
1100static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1101{
1102 struct sk_buff *skb = re->skb;
1103 int i;
1104
1105 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1106 PCI_DMA_FROMDEVICE);
1107
1108 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1109 pci_unmap_page(pdev, re->frag_addr[i],
1110 skb_shinfo(skb)->frags[i].size,
1111 PCI_DMA_FROMDEVICE);
1112}
793b883e 1113
cd28ab6a
SH
1114/* Tell chip where to start receive checksum.
1115 * Actually has two checksums, but set both same to avoid possible byte
1116 * order problems.
1117 */
793b883e 1118static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1119{
ea76e635 1120 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1121
ea76e635
SH
1122 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1123 le->ctrl = 0;
1124 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1125
ea76e635
SH
1126 sky2_write32(sky2->hw,
1127 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH
1128 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1129 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH
1130}
1131
6b1a3aef 1132/*
1133 * The RX Stop command will not work for Yukon-2 if the BMU does not
1134 * reach the end of packet and since we can't make sure that we have
1135 * incoming data, we must reset the BMU while it is not doing a DMA
1136 * transfer. Since it is possible that the RX path is still active,
1137 * the RX RAM buffer will be stopped first, so any possible incoming
1138 * data will not trigger a DMA. After the RAM buffer is stopped, the
1139 * BMU is polled until any DMA in progress is ended and only then it
1140 * will be reset.
1141 */
1142static void sky2_rx_stop(struct sky2_port *sky2)
1143{
1144 struct sky2_hw *hw = sky2->hw;
1145 unsigned rxq = rxqaddr[sky2->port];
1146 int i;
1147
1148 /* disable the RAM Buffer receive queue */
1149 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1150
1151 for (i = 0; i < 0xffff; i++)
1152 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1153 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1154 goto stopped;
1155
1156 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1157 sky2->netdev->name);
1158stopped:
1159 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1160
1161 /* reset the Rx prefetch unit */
1162 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1163 mmiowb();
6b1a3aef 1164}
793b883e 1165
d571b694 1166/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH
1167static void sky2_rx_clean(struct sky2_port *sky2)
1168{
1169 unsigned i;
1170
1171 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1172 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1173 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH
1174
1175 if (re->skb) {
14d0263f 1176 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH
1177 kfree_skb(re->skb);
1178 re->skb = NULL;
1179 }
1180 }
bd1c6869 1181 skb_queue_purge(&sky2->rx_recycle);
cd28ab6a
SH
1182}
1183
ef743d33 1184/* Basic MII support */
1185static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1186{
1187 struct mii_ioctl_data *data = if_mii(ifr);
1188 struct sky2_port *sky2 = netdev_priv(dev);
1189 struct sky2_hw *hw = sky2->hw;
1190 int err = -EOPNOTSUPP;
1191
1192 if (!netif_running(dev))
1193 return -ENODEV; /* Phy still in reset */
1194
d89e1343 1195 switch (cmd) {
ef743d33 1196 case SIOCGMIIPHY:
1197 data->phy_id = PHY_ADDR_MARV;
1198
1199 /* fallthru */
1200 case SIOCGMIIREG: {
1201 u16 val = 0;
91c86df5 1202
e07b1aa8 1203 spin_lock_bh(&sky2->phy_lock);
ef743d33 1204 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1205 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1206
ef743d33 1207 data->val_out = val;
1208 break;
1209 }
1210
1211 case SIOCSMIIREG:
1212 if (!capable(CAP_NET_ADMIN))
1213 return -EPERM;
1214
e07b1aa8 1215 spin_lock_bh(&sky2->phy_lock);
ef743d33 1216 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1217 data->val_in);
e07b1aa8 1218 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1219 break;
1220 }
1221 return err;
1222}
1223
d1f13708 1224#ifdef SKY2_VLAN_TAG_USED
d494eacd 1225static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1226{
d494eacd 1227 if (onoff) {
3d4e66f5
SH
1228 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1229 RX_VLAN_STRIP_ON);
1230 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1231 TX_VLAN_TAG_ON);
1232 } else {
1233 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1234 RX_VLAN_STRIP_OFF);
1235 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1236 TX_VLAN_TAG_OFF);
1237 }
d494eacd
SH
1238}
1239
1240static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1241{
1242 struct sky2_port *sky2 = netdev_priv(dev);
1243 struct sky2_hw *hw = sky2->hw;
1244 u16 port = sky2->port;
1245
1246 netif_tx_lock_bh(dev);
1247 napi_disable(&hw->napi);
1248
1249 sky2->vlgrp = grp;
1250 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1251
d1d08d12 1252 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1253 napi_enable(&hw->napi);
2bb8c262 1254 netif_tx_unlock_bh(dev);
d1f13708 1255}
1256#endif
1257
bd1c6869
SH
1258/* Amount of required worst case padding in rx buffer */
1259static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1260{
1261 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1262}
1263
82788c7a 1264/*
14d0263f
SH
1265 * Allocate an skb for receiving. If the MTU is large enough
1266 * make the skb non-linear with a fragment list of pages.
82788c7a 1267 */
14d0263f 1268static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH
1269{
1270 struct sk_buff *skb;
14d0263f 1271 int i;
82788c7a 1272
bd1c6869
SH
1273 skb = __skb_dequeue(&sky2->rx_recycle);
1274 if (!skb)
1275 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size
1276 + sky2_rx_pad(sky2->hw));
1277 if (!skb)
1278 goto nomem;
1279
39dbd958 1280 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH
1281 unsigned char *start;
1282 /*
1283 * Workaround for a bug in FIFO that cause hang
1284 * if the FIFO if the receive buffer is not 64 byte aligned.
1285 * The buffer returned from netdev_alloc_skb is
1286 * aligned except if slab debugging is enabled.
1287 */
f03b8654
SH
1288 start = PTR_ALIGN(skb->data, 8);
1289 skb_reserve(skb, start - skb->data);
bd1c6869 1290 } else
f03b8654 1291 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH
1292
1293 for (i = 0; i < sky2->rx_nfrags; i++) {
1294 struct page *page = alloc_page(GFP_ATOMIC);
1295
1296 if (!page)
1297 goto free_partial;
1298 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH
1299 }
1300
1301 return skb;
14d0263f
SH
1302free_partial:
1303 kfree_skb(skb);
1304nomem:
1305 return NULL;
82788c7a
SH
1306}
1307
55c9dd35
SH
1308static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1309{
1310 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1311}
1312
cd28ab6a
SH
1313/*
1314 * Allocate and setup receiver buffer pool.
14d0263f
SH
1315 * Normal case this ends up creating one list element for skb
1316 * in the receive ring. Worst case if using large MTU and each
1317 * allocation falls on a different 64 bit region, that results
1318 * in 6 list elements per ring entry.
1319 * One element is used for checksum enable/disable, and one
1320 * extra to avoid wrap.
cd28ab6a 1321 */
6b1a3aef 1322static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1323{
6b1a3aef 1324 struct sky2_hw *hw = sky2->hw;
14d0263f 1325 struct rx_ring_info *re;
6b1a3aef 1326 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1327 unsigned i, size, thresh;
cd28ab6a 1328
6b1a3aef 1329 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1330 sky2_qset(hw, rxq);
977bdf06 1331
c3905bc4
SH
1332 /* On PCI express lowering the watermark gives better performance */
1333 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1334 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1335
1336 /* These chips have no ram buffer?
1337 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1338 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH
1339 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1340 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1341 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1342
6b1a3aef 1343 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1344
ea76e635
SH
1345 if (!(hw->flags & SKY2_HW_NEW_LE))
1346 rx_set_checksum(sky2);
14d0263f
SH
1347
1348 /* Space needed for frame data + headers rounded up */
f957da2a 1349 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH
1350
1351 /* Stopping point for hardware truncation */
1352 thresh = (size - 8) / sizeof(u32);
1353
5f06eba4 1354 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH
1355 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1356
5f06eba4
SH
1357 /* Compute residue after pages */
1358 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1359
5f06eba4
SH
1360 /* Optimize to handle small packets and headers */
1361 if (size < copybreak)
1362 size = copybreak;
1363 if (size < ETH_HLEN)
1364 size = ETH_HLEN;
14d0263f 1365
14d0263f
SH
1366 sky2->rx_data_size = size;
1367
bd1c6869
SH
1368 skb_queue_head_init(&sky2->rx_recycle);
1369
14d0263f 1370 /* Fill Rx ring */
793b883e 1371 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1372 re = sky2->rx_ring + i;
cd28ab6a 1373
14d0263f 1374 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH
1375 if (!re->skb)
1376 goto nomem;
1377
454e6cb6
SH
1378 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1379 dev_kfree_skb(re->skb);
1380 re->skb = NULL;
1381 goto nomem;
1382 }
1383
14d0263f 1384 sky2_rx_submit(sky2, re);
cd28ab6a
SH
1385 }
1386
a1433ac4
SH
1387 /*
1388 * The receiver hangs if it receives frames larger than the
1389 * packet buffer. As a workaround, truncate oversize frames, but
1390 * the register is limited to 9 bits, so if you do frames > 2052
1391 * you better get the MTU right!
1392 */
a1433ac4
SH
1393 if (thresh > 0x1ff)
1394 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1395 else {
1396 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1397 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1398 }
1399
6b1a3aef 1400 /* Tell chip about available buffers */
55c9dd35 1401 sky2_rx_update(sky2, rxq);
cd28ab6a
SH
1402 return 0;
1403nomem:
1404 sky2_rx_clean(sky2);
1405 return -ENOMEM;
1406}
1407
1408/* Bring up network interface. */
1409static int sky2_up(struct net_device *dev)
1410{
1411 struct sky2_port *sky2 = netdev_priv(dev);
1412 struct sky2_hw *hw = sky2->hw;
1413 unsigned port = sky2->port;
e0c28116 1414 u32 imask, ramsize;
ee7abb04 1415 int cap, err = -ENOMEM;
843a46f4 1416 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1417
ee7abb04
SH
1418 /*
1419 * On dual port PCI-X card, there is an problem where status
1420 * can be received out of order due to split transactions
843a46f4 1421 */
ee7abb04
SH
1422 if (otherdev && netif_running(otherdev) &&
1423 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH
1424 u16 cmd;
1425
b32f40c4 1426 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1427 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH
1428 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1429
ee7abb04 1430 }
843a46f4 1431
55d7b4e6
SH
1432 netif_carrier_off(dev);
1433
cd28ab6a
SH
1434 /* must be power of 2 */
1435 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH
1436 TX_RING_SIZE *
1437 sizeof(struct sky2_tx_le),
cd28ab6a
SH
1438 &sky2->tx_le_map);
1439 if (!sky2->tx_le)
1440 goto err_out;
1441
6cdbbdf3 1442 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH
1443 GFP_KERNEL);
1444 if (!sky2->tx_ring)
1445 goto err_out;
88f5f0ca
SH
1446
1447 tx_init(sky2);
cd28ab6a
SH
1448
1449 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1450 &sky2->rx_le_map);
1451 if (!sky2->rx_le)
1452 goto err_out;
1453 memset(sky2->rx_le, 0, RX_LE_BYTES);
1454
291ea614 1455 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH
1456 GFP_KERNEL);
1457 if (!sky2->rx_ring)
1458 goto err_out;
1459
1460 sky2_mac_init(hw, port);
1461
e0c28116
SH
1462 /* Register is number of 4K blocks on internal RAM buffer. */
1463 ramsize = sky2_read8(hw, B2_E_0) * 4;
1464 if (ramsize > 0) {
67712901 1465 u32 rxspace;
cd28ab6a 1466
39dbd958 1467 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1468 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH
1469 if (ramsize < 16)
1470 rxspace = ramsize / 2;
1471 else
1472 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1473
67712901
SH
1474 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1475 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1476
1477 /* Make sure SyncQ is disabled */
1478 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1479 RB_RST_SET);
1480 }
793b883e 1481
af4ed7e6 1482 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1483
69161611
SH
1484 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1485 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1486 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1487
977bdf06 1488 /* Set almost empty threshold */
c2716fb4
SH
1489 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1490 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1491 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1492
6b1a3aef 1493 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1494 TX_RING_SIZE - 1);
cd28ab6a 1495
d494eacd
SH
1496#ifdef SKY2_VLAN_TAG_USED
1497 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1498#endif
1499
6b1a3aef 1500 err = sky2_rx_start(sky2);
6de16237 1501 if (err)
cd28ab6a
SH
1502 goto err_out;
1503
cd28ab6a 1504 /* Enable interrupts from phy/mac for port */
e07b1aa8 1505 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1506 imask |= portirq_msk[port];
e07b1aa8 1507 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1508 sky2_read32(hw, B0_IMSK);
e07b1aa8 1509
a11da890
AD
1510 if (netif_msg_ifup(sky2))
1511 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1512
cd28ab6a
SH
1513 return 0;
1514
1515err_out:
1b537565 1516 if (sky2->rx_le) {
cd28ab6a
SH
1517 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1518 sky2->rx_le, sky2->rx_le_map);
1b537565
SH
1519 sky2->rx_le = NULL;
1520 }
1521 if (sky2->tx_le) {
cd28ab6a
SH
1522 pci_free_consistent(hw->pdev,
1523 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1524 sky2->tx_le, sky2->tx_le_map);
1b537565
SH
1525 sky2->tx_le = NULL;
1526 }
1527 kfree(sky2->tx_ring);
1528 kfree(sky2->rx_ring);
cd28ab6a 1529
1b537565
SH
1530 sky2->tx_ring = NULL;
1531 sky2->rx_ring = NULL;
cd28ab6a
SH
1532 return err;
1533}
1534
793b883e
SH
1535/* Modular subtraction in ring */
1536static inline int tx_dist(unsigned tail, unsigned head)
1537{
cb5d9547 1538 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1539}
cd28ab6a 1540
793b883e
SH
1541/* Number of list elements available for next tx */
1542static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1543{
793b883e 1544 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH
1545}
1546
793b883e 1547/* Estimate of number of transmit list elements required */
28bd181a 1548static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1549{
793b883e
SH
1550 unsigned count;
1551
1552 count = sizeof(dma_addr_t) / sizeof(u32);
1553 count += skb_shinfo(skb)->nr_frags * count;
1554
89114afd 1555 if (skb_is_gso(skb))
793b883e
SH
1556 ++count;
1557
84fa7933 1558 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH
1559 ++count;
1560
1561 return count;
cd28ab6a
SH
1562}
1563
793b883e
SH
1564/*
1565 * Put one packet in ring for transmit.
1566 * A single packet can generate multiple list elements, and
1567 * the number of ring elements will probably be less than the number
1568 * of list elements used.
1569 */
cd28ab6a
SH
1570static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1571{
1572 struct sky2_port *sky2 = netdev_priv(dev);
1573 struct sky2_hw *hw = sky2->hw;
d1f13708 1574 struct sky2_tx_le *le = NULL;
6cdbbdf3 1575 struct tx_ring_info *re;
9b289c33 1576 unsigned i, len;
cd28ab6a 1577 dma_addr_t mapping;
5dce95e5
SH
1578 u32 upper;
1579 u16 slot;
cd28ab6a
SH
1580 u16 mss;
1581 u8 ctrl;
1582
2bb8c262
SH
1583 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1584 return NETDEV_TX_BUSY;
cd28ab6a 1585
cd28ab6a
SH
1586 len = skb_headlen(skb);
1587 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1588
454e6cb6
SH
1589 if (pci_dma_mapping_error(hw->pdev, mapping))
1590 goto mapping_error;
1591
9b289c33 1592 slot = sky2->tx_prod;
454e6cb6
SH
1593 if (unlikely(netif_msg_tx_queued(sky2)))
1594 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1595 dev->name, slot, skb->len);
454e6cb6 1596
86c6887e 1597 /* Send high bits if needed */
5dce95e5
SH
1598 upper = upper_32_bits(mapping);
1599 if (upper != sky2->tx_last_upper) {
9b289c33 1600 le = get_tx_le(sky2, &slot);
5dce95e5
SH
1601 le->addr = cpu_to_le32(upper);
1602 sky2->tx_last_upper = upper;
793b883e 1603 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1604 }
cd28ab6a
SH
1605
1606 /* Check for TCP Segmentation Offload */
7967168c 1607 mss = skb_shinfo(skb)->gso_size;
793b883e 1608 if (mss != 0) {
ea76e635
SH
1609
1610 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH
1611 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1612
1613 if (mss != sky2->tx_last_mss) {
9b289c33 1614 le = get_tx_le(sky2, &slot);
69161611 1615 le->addr = cpu_to_le32(mss);
ea76e635
SH
1616
1617 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH
1618 le->opcode = OP_MSS | HW_OWNER;
1619 else
1620 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1621 sky2->tx_last_mss = mss;
1622 }
cd28ab6a
SH
1623 }
1624
cd28ab6a 1625 ctrl = 0;
d1f13708 1626#ifdef SKY2_VLAN_TAG_USED
1627 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1628 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1629 if (!le) {
9b289c33 1630 le = get_tx_le(sky2, &slot);
f65b138c 1631 le->addr = 0;
d1f13708 1632 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1633 } else
1634 le->opcode |= OP_VLAN;
1635 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1636 ctrl |= INS_VLAN;
1637 }
1638#endif
1639
1640 /* Handle TCP checksum offload */
84fa7933 1641 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1642 /* On Yukon EX (some versions) encoding change. */
ea76e635 1643 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH
1644 ctrl |= CALSUM; /* auto checksum */
1645 else {
1646 const unsigned offset = skb_transport_offset(skb);
1647 u32 tcpsum;
1648
1649 tcpsum = offset << 16; /* sum start */
1650 tcpsum |= offset + skb->csum_offset; /* sum write */
1651
1652 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1653 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1654 ctrl |= UDPTCP;
1655
1656 if (tcpsum != sky2->tx_tcpsum) {
1657 sky2->tx_tcpsum = tcpsum;
1658
9b289c33 1659 le = get_tx_le(sky2, &slot);
69161611
SH
1660 le->addr = cpu_to_le32(tcpsum);
1661 le->length = 0; /* initial checksum value */
1662 le->ctrl = 1; /* one packet */
1663 le->opcode = OP_TCPLISW | HW_OWNER;
1664 }
1d179332 1665 }
cd28ab6a
SH
1666 }
1667
9b289c33 1668 le = get_tx_le(sky2, &slot);
d6e74b6b 1669 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH
1670 le->length = cpu_to_le16(len);
1671 le->ctrl = ctrl;
793b883e 1672 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1673
291ea614 1674 re = tx_le_re(sky2, le);
cd28ab6a 1675 re->skb = skb;
6cdbbdf3 1676 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1677 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH
1678
1679 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1680 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH
1681
1682 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1683 frag->size, PCI_DMA_TODEVICE);
86c6887e 1684
454e6cb6
SH
1685 if (pci_dma_mapping_error(hw->pdev, mapping))
1686 goto mapping_unwind;
1687
5dce95e5
SH
1688 upper = upper_32_bits(mapping);
1689 if (upper != sky2->tx_last_upper) {
9b289c33 1690 le = get_tx_le(sky2, &slot);
5dce95e5
SH
1691 le->addr = cpu_to_le32(upper);
1692 sky2->tx_last_upper = upper;
793b883e 1693 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH
1694 }
1695
9b289c33 1696 le = get_tx_le(sky2, &slot);
d6e74b6b 1697 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH
1698 le->length = cpu_to_le16(frag->size);
1699 le->ctrl = ctrl;
793b883e 1700 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1701
291ea614
SH
1702 re = tx_le_re(sky2, le);
1703 re->skb = skb;
1704 pci_unmap_addr_set(re, mapaddr, mapping);
1705 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1706 }
6cdbbdf3 1707
cd28ab6a
SH
1708 le->ctrl |= EOP;
1709
9b289c33
MM
1710 sky2->tx_prod = slot;
1711
97bda706 1712 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1713 netif_stop_queue(dev);
b19666d9 1714
290d4de5 1715 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1716
cd28ab6a 1717 return NETDEV_TX_OK;
454e6cb6
SH
1718
1719mapping_unwind:
9b289c33 1720 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, TX_RING_SIZE)) {
454e6cb6
SH
1721 le = sky2->tx_le + i;
1722 re = sky2->tx_ring + i;
1723
1724 switch(le->opcode & ~HW_OWNER) {
1725 case OP_LARGESEND:
1726 case OP_PACKET:
1727 pci_unmap_single(hw->pdev,
1728 pci_unmap_addr(re, mapaddr),
1729 pci_unmap_len(re, maplen),
1730 PCI_DMA_TODEVICE);
1731 break;
1732 case OP_BUFFER:
1733 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1734 pci_unmap_len(re, maplen),
1735 PCI_DMA_TODEVICE);
1736 break;
1737 }
1738 }
1739
454e6cb6
SH
1740mapping_error:
1741 if (net_ratelimit())
1742 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1743 dev_kfree_skb(skb);
1744 return NETDEV_TX_OK;
cd28ab6a
SH
1745}
1746
cd28ab6a 1747/*
793b883e
SH
1748 * Free ring elements from starting at tx_cons until "done"
1749 *
481cea4a
SH
1750 * NB:
1751 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1752 * buffers so make sure not to free skb to early.
481cea4a
SH
1753 * 2. This may run in parallel start_xmit because the it only
1754 * looks at the tail of the queue of FIFO (tx_cons), not
1755 * the head (tx_prod)
cd28ab6a 1756 */
d11c13e7 1757static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1758{
d11c13e7 1759 struct net_device *dev = sky2->netdev;
af2a58ac 1760 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1761 unsigned idx;
cd28ab6a 1762
0e3ff6aa 1763 BUG_ON(done >= TX_RING_SIZE);
2224795d 1764
291ea614
SH
1765 for (idx = sky2->tx_cons; idx != done;
1766 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1767 struct sky2_tx_le *le = sky2->tx_le + idx;
1768 struct tx_ring_info *re = sky2->tx_ring + idx;
1769
1770 switch(le->opcode & ~HW_OWNER) {
1771 case OP_LARGESEND:
1772 case OP_PACKET:
1773 pci_unmap_single(pdev,
1774 pci_unmap_addr(re, mapaddr),
1775 pci_unmap_len(re, maplen),
1776 PCI_DMA_TODEVICE);
af2a58ac 1777 break;
291ea614
SH
1778 case OP_BUFFER:
1779 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1780 pci_unmap_len(re, maplen),
734d1868 1781 PCI_DMA_TODEVICE);
291ea614
SH
1782 break;
1783 }
1784
1785 if (le->ctrl & EOP) {
bd1c6869
SH
1786 struct sk_buff *skb = re->skb;
1787
291ea614
SH
1788 if (unlikely(netif_msg_tx_done(sky2)))
1789 printk(KERN_DEBUG "%s: tx done %u\n",
1790 dev->name, idx);
3cf26753 1791
7138a0f5 1792 dev->stats.tx_packets++;
bd1c6869
SH
1793 dev->stats.tx_bytes += skb->len;
1794
1795 if (skb_queue_len(&sky2->rx_recycle) < sky2->rx_pending
1796 && skb_recycle_check(skb, sky2->rx_data_size
1797 + sky2_rx_pad(sky2->hw)))
1798 __skb_queue_head(&sky2->rx_recycle, skb);
1799 else
1800 dev_kfree_skb_any(skb);
2bf56fe2 1801
3cf26753 1802 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1803 }
793b883e 1804 }
793b883e 1805
291ea614 1806 sky2->tx_cons = idx;
50432cb5
SH
1807 smp_mb();
1808
22e11703 1809 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1810 netif_wake_queue(dev);
cd28ab6a
SH
1811}
1812
264bb4fa 1813static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1814{
a510996b
MM
1815 /* Disable Force Sync bit and Enable Alloc bit */
1816 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1817 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1818
1819 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1820 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1821 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1822
1823 /* Reset the PCI FIFO of the async Tx queue */
1824 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1825 BMU_RST_SET | BMU_FIFO_RST);
1826
1827 /* Reset the Tx prefetch units */
1828 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1829 PREF_UNIT_RST_SET);
1830
1831 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1832 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1833}
1834
cd28ab6a
SH
1835/* Network shutdown */
1836static int sky2_down(struct net_device *dev)
1837{
1838 struct sky2_port *sky2 = netdev_priv(dev);
1839 struct sky2_hw *hw = sky2->hw;
1840 unsigned port = sky2->port;
1841 u16 ctrl;
e07b1aa8 1842 u32 imask;
cd28ab6a 1843
1b537565
SH
1844 /* Never really got started! */
1845 if (!sky2->tx_le)
1846 return 0;
1847
cd28ab6a
SH
1848 if (netif_msg_ifdown(sky2))
1849 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1850
d104acaf
SH
1851 /* Force flow control off */
1852 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1853
cd28ab6a
SH
1854 /* Stop transmitter */
1855 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1856 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1857
1858 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1859 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH
1860
1861 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1862 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH
1863 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1864
1865 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1866
1867 /* Workaround shared GMAC reset */
793b883e
SH
1868 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1869 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH
1870 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1871
cd28ab6a 1872 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1873
6c83504f
SH
1874 /* Force any delayed status interrrupt and NAPI */
1875 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1876 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1877 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1878 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1879
a947a39d
MM
1880 sky2_rx_stop(sky2);
1881
1882 /* Disable port IRQ */
1883 imask = sky2_read32(hw, B0_IMSK);
1884 imask &= ~portirq_msk[port];
1885 sky2_write32(hw, B0_IMSK, imask);
1886 sky2_read32(hw, B0_IMSK);
1887
6c83504f
SH
1888 synchronize_irq(hw->pdev->irq);
1889 napi_synchronize(&hw->napi);
1890
0da6d7b3 1891 spin_lock_bh(&sky2->phy_lock);
b96936da 1892 sky2_phy_power_down(hw, port);
0da6d7b3 1893 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1894
d571b694 1895 /* turn off LED's */
cd28ab6a
SH
1896 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1897
264bb4fa
MM
1898 sky2_tx_reset(hw, port);
1899
481cea4a
SH
1900 /* Free any pending frames stuck in HW queue */
1901 sky2_tx_complete(sky2, sky2->tx_prod);
1902
cd28ab6a
SH
1903 sky2_rx_clean(sky2);
1904
1905 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1906 sky2->rx_le, sky2->rx_le_map);
1907 kfree(sky2->rx_ring);
1908
1909 pci_free_consistent(hw->pdev,
1910 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1911 sky2->tx_le, sky2->tx_le_map);
1912 kfree(sky2->tx_ring);
1913
1b537565
SH
1914 sky2->tx_le = NULL;
1915 sky2->rx_le = NULL;
1916
1917 sky2->rx_ring = NULL;
1918 sky2->tx_ring = NULL;
1919
cd28ab6a
SH
1920 return 0;
1921}
1922
1923static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1924{
ea76e635 1925 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH
1926 return SPEED_1000;
1927
05745c4a
SH
1928 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1929 if (aux & PHY_M_PS_SPEED_100)
1930 return SPEED_100;
1931 else
1932 return SPEED_10;
1933 }
cd28ab6a
SH
1934
1935 switch (aux & PHY_M_PS_SPEED_MSK) {
1936 case PHY_M_PS_SPEED_1000:
1937 return SPEED_1000;
1938 case PHY_M_PS_SPEED_100:
1939 return SPEED_100;
1940 default:
1941 return SPEED_10;
1942 }
1943}
1944
1945static void sky2_link_up(struct sky2_port *sky2)
1946{
1947 struct sky2_hw *hw = sky2->hw;
1948 unsigned port = sky2->port;
1949 u16 reg;
16ad91e1
SH
1950 static const char *fc_name[] = {
1951 [FC_NONE] = "none",
1952 [FC_TX] = "tx",
1953 [FC_RX] = "rx",
1954 [FC_BOTH] = "both",
1955 };
cd28ab6a 1956
cd28ab6a 1957 /* enable Rx/Tx */
2eaba1a2 1958 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH
1959 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1960 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH
1961
1962 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1963
1964 netif_carrier_on(sky2->netdev);
cd28ab6a 1965
75e80683 1966 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1967
cd28ab6a 1968 /* Turn on link LED */
793b883e 1969 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH
1970 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1971
1972 if (netif_msg_link(sky2))
1973 printk(KERN_INFO PFX
d571b694 1974 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH
1975 sky2->netdev->name, sky2->speed,
1976 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1977 fc_name[sky2->flow_status]);
cd28ab6a
SH
1978}
1979
1980static void sky2_link_down(struct sky2_port *sky2)
1981{
1982 struct sky2_hw *hw = sky2->hw;
1983 unsigned port = sky2->port;
1984 u16 reg;
1985
1986 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1987
1988 reg = gma_read16(hw, port, GM_GP_CTRL);
1989 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1990 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1991
cd28ab6a 1992 netif_carrier_off(sky2->netdev);
cd28ab6a
SH
1993
1994 /* Turn on link LED */
1995 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1996
1997 if (netif_msg_link(sky2))
1998 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1999
cd28ab6a
SH
2000 sky2_phy_init(hw, port);
2001}
2002
16ad91e1
SH
2003static enum flow_control sky2_flow(int rx, int tx)
2004{
2005 if (rx)
2006 return tx ? FC_BOTH : FC_RX;
2007 else
2008 return tx ? FC_TX : FC_NONE;
2009}
2010
793b883e
SH
2011static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2012{
2013 struct sky2_hw *hw = sky2->hw;
2014 unsigned port = sky2->port;
da4c1ff4 2015 u16 advert, lpa;
793b883e 2016
da4c1ff4 2017 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2018 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH
2019 if (lpa & PHY_M_AN_RF) {
2020 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2021 return -1;
2022 }
2023
793b883e
SH
2024 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2025 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2026 sky2->netdev->name);
2027 return -1;
2028 }
2029
793b883e 2030 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2031 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2032
da4c1ff4
SH
2033 /* Since the pause result bits seem to in different positions on
2034 * different chips. look at registers.
2035 */
ea76e635 2036 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH
2037 /* Shift for bits in fiber PHY */
2038 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2039 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2040
2041 if (advert & ADVERTISE_1000XPAUSE)
2042 advert |= ADVERTISE_PAUSE_CAP;
2043 if (advert & ADVERTISE_1000XPSE_ASYM)
2044 advert |= ADVERTISE_PAUSE_ASYM;
2045 if (lpa & LPA_1000XPAUSE)
2046 lpa |= LPA_PAUSE_CAP;
2047 if (lpa & LPA_1000XPAUSE_ASYM)
2048 lpa |= LPA_PAUSE_ASYM;
2049 }
793b883e 2050
da4c1ff4
SH
2051 sky2->flow_status = FC_NONE;
2052 if (advert & ADVERTISE_PAUSE_CAP) {
2053 if (lpa & LPA_PAUSE_CAP)
2054 sky2->flow_status = FC_BOTH;
2055 else if (advert & ADVERTISE_PAUSE_ASYM)
2056 sky2->flow_status = FC_RX;
2057 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2058 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2059 sky2->flow_status = FC_TX;
2060 }
793b883e 2061
16ad91e1 2062 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2063 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2064 sky2->flow_status = FC_NONE;
2eaba1a2 2065
da4c1ff4 2066 if (sky2->flow_status & FC_TX)
793b883e
SH
2067 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2068 else
2069 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2070
2071 return 0;
2072}
cd28ab6a 2073
e07b1aa8
SH
2074/* Interrupt from PHY */
2075static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2076{
e07b1aa8
SH
2077 struct net_device *dev = hw->dev[port];
2078 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH
2079 u16 istatus, phystat;
2080
ebc646f6
SH
2081 if (!netif_running(dev))
2082 return;
2083
e07b1aa8
SH
2084 spin_lock(&sky2->phy_lock);
2085 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2086 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2087
cd28ab6a
SH
2088 if (netif_msg_intr(sky2))
2089 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2090 sky2->netdev->name, istatus, phystat);
2091
0ea065e5 2092 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH
2093 if (sky2_autoneg_done(sky2, phystat) == 0)
2094 sky2_link_up(sky2);
2095 goto out;
2096 }
cd28ab6a 2097
793b883e
SH
2098 if (istatus & PHY_M_IS_LSP_CHANGE)
2099 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2100
793b883e
SH
2101 if (istatus & PHY_M_IS_DUP_CHANGE)
2102 sky2->duplex =
2103 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2104
793b883e
SH
2105 if (istatus & PHY_M_IS_LST_CHANGE) {
2106 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2107 sky2_link_up(sky2);
793b883e
SH
2108 else
2109 sky2_link_down(sky2);
cd28ab6a 2110 }
793b883e 2111out:
e07b1aa8 2112 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH
2113}
2114
62335ab0 2115/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH
2116 * and tx queue is full (stopped).
2117 */
cd28ab6a
SH
2118static void sky2_tx_timeout(struct net_device *dev)
2119{
2120 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2121 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH
2122
2123 if (netif_msg_timer(sky2))
2124 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2125
8f24664d 2126 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH
2127 dev->name, sky2->tx_cons, sky2->tx_prod,
2128 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2129 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2130
81906791
SH
2131 /* can't restart safely under softirq */
2132 schedule_work(&hw->restart_work);
cd28ab6a
SH
2133}
2134
2135static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2136{
6b1a3aef 2137 struct sky2_port *sky2 = netdev_priv(dev);
2138 struct sky2_hw *hw = sky2->hw;
b628ed98 2139 unsigned port = sky2->port;
6b1a3aef 2140 int err;
2141 u16 ctl, mode;
e07b1aa8 2142 u32 imask;
cd28ab6a
SH
2143
2144 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2145 return -EINVAL;
2146
05745c4a
SH
2147 if (new_mtu > ETH_DATA_LEN &&
2148 (hw->chip_id == CHIP_ID_YUKON_FE ||
2149 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH
2150 return -EINVAL;
2151
6b1a3aef 2152 if (!netif_running(dev)) {
2153 dev->mtu = new_mtu;
2154 return 0;
2155 }
2156
e07b1aa8 2157 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2158 sky2_write32(hw, B0_IMSK, 0);
2159
018d1c66 2160 dev->trans_start = jiffies; /* prevent tx timeout */
2161 netif_stop_queue(dev);
bea3348e 2162 napi_disable(&hw->napi);
018d1c66 2163
e07b1aa8
SH
2164 synchronize_irq(hw->pdev->irq);
2165
39dbd958 2166 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2167 sky2_set_tx_stfwd(hw, port);
b628ed98
SH
2168
2169 ctl = gma_read16(hw, port, GM_GP_CTRL);
2170 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2171 sky2_rx_stop(sky2);
2172 sky2_rx_clean(sky2);
cd28ab6a
SH
2173
2174 dev->mtu = new_mtu;
14d0263f 2175
6b1a3aef 2176 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2177 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2178
2179 if (dev->mtu > ETH_DATA_LEN)
2180 mode |= GM_SMOD_JUMBO_ENA;
2181
b628ed98 2182 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2183
b628ed98 2184 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2185
6b1a3aef 2186 err = sky2_rx_start(sky2);
e07b1aa8 2187 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2188
d1d08d12 2189 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH
2190 napi_enable(&hw->napi);
2191
1b537565
SH
2192 if (err)
2193 dev_close(dev);
2194 else {
b628ed98 2195 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2196
1b537565
SH
2197 netif_wake_queue(dev);
2198 }
2199
cd28ab6a
SH
2200 return err;
2201}
2202
14d0263f
SH
2203/* For small just reuse existing skb for next receive */
2204static struct sk_buff *receive_copy(struct sky2_port *sky2,
2205 const struct rx_ring_info *re,
2206 unsigned length)
2207{
2208 struct sk_buff *skb;
2209
2210 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2211 if (likely(skb)) {
2212 skb_reserve(skb, 2);
2213 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2214 length, PCI_DMA_FROMDEVICE);
d626f62b 2215 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH
2216 skb->ip_summed = re->skb->ip_summed;
2217 skb->csum = re->skb->csum;
2218 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2219 length, PCI_DMA_FROMDEVICE);
2220 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2221 skb_put(skb, length);
14d0263f
SH
2222 }
2223 return skb;
2224}
2225
2226/* Adjust length of skb with fragments to match received data */
2227static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2228 unsigned int length)
2229{
2230 int i, num_frags;
2231 unsigned int size;
2232
2233 /* put header into skb */
2234 size = min(length, hdr_space);
2235 skb->tail += size;
2236 skb->len += size;
2237 length -= size;
2238
2239 num_frags = skb_shinfo(skb)->nr_frags;
2240 for (i = 0; i < num_frags; i++) {
2241 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2242
2243 if (length == 0) {
2244 /* don't need this page */
2245 __free_page(frag->page);
2246 --skb_shinfo(skb)->nr_frags;
2247 } else {
2248 size = min(length, (unsigned) PAGE_SIZE);
2249
2250 frag->size = size;
2251 skb->data_len += size;
2252 skb->truesize += size;
2253 skb->len += size;
2254 length -= size;
2255 }
2256 }
2257}
2258
2259/* Normal packet - take skb from ring element and put in a new one */
2260static struct sk_buff *receive_new(struct sky2_port *sky2,
2261 struct rx_ring_info *re,
2262 unsigned int length)
2263{
2264 struct sk_buff *skb, *nskb;
2265 unsigned hdr_space = sky2->rx_data_size;
2266
14d0263f
SH
2267 /* Don't be tricky about reusing pages (yet) */
2268 nskb = sky2_rx_alloc(sky2);
2269 if (unlikely(!nskb))
2270 return NULL;
2271
2272 skb = re->skb;
2273 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2274
2275 prefetch(skb->data);
2276 re->skb = nskb;
454e6cb6
SH
2277 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2278 dev_kfree_skb(nskb);
2279 re->skb = skb;
2280 return NULL;
2281 }
14d0263f
SH
2282
2283 if (skb_shinfo(skb)->nr_frags)
2284 skb_put_frags(skb, hdr_space, length);
2285 else
489b10c1 2286 skb_put(skb, length);
14d0263f
SH
2287 return skb;
2288}
2289
cd28ab6a
SH
2290/*
2291 * Receive one packet.
d571b694 2292 * For larger packets, get new buffer.
cd28ab6a 2293 */
497d7c86 2294static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH
2295 u16 length, u32 status)
2296{
497d7c86 2297 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2298 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2299 struct sk_buff *skb = NULL;
d6532232
SH
2300 u16 count = (status & GMR_FS_LEN) >> 16;
2301
2302#ifdef SKY2_VLAN_TAG_USED
2303 /* Account for vlan tag */
2304 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2305 count -= VLAN_HLEN;
2306#endif
cd28ab6a
SH
2307
2308 if (unlikely(netif_msg_rx_status(sky2)))
2309 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2310 dev->name, sky2->rx_next, status, length);
cd28ab6a 2311
793b883e 2312 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2313 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2314
3b12e014
SH
2315 /* This chip has hardware problems that generates bogus status.
2316 * So do only marginal checking and expect higher level protocols
2317 * to handle crap frames.
2318 */
2319 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2320 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2321 length != count)
2322 goto okay;
2323
42eeea01 2324 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH
2325 goto error;
2326
42eeea01 2327 if (!(status & GMR_FS_RX_OK))
2328 goto resubmit;
2329
d6532232
SH
2330 /* if length reported by DMA does not match PHY, packet was truncated */
2331 if (length != count)
3b12e014 2332 goto len_error;
71749531 2333
3b12e014 2334okay:
14d0263f
SH
2335 if (length < copybreak)
2336 skb = receive_copy(sky2, re, length);
2337 else
2338 skb = receive_new(sky2, re, length);
793b883e 2339resubmit:
14d0263f 2340 sky2_rx_submit(sky2, re);
79e57d32 2341
cd28ab6a
SH
2342 return skb;
2343
3b12e014 2344len_error:
71749531
SH
2345 /* Truncation of overlength packets
2346 causes PHY length to not match MAC length */
7138a0f5 2347 ++dev->stats.rx_length_errors;
d6532232 2348 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH
2349 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2350 dev->name, status, length);
d6532232 2351 goto resubmit;
71749531 2352
cd28ab6a 2353error:
7138a0f5 2354 ++dev->stats.rx_errors;
b6d77734 2355 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2356 dev->stats.rx_over_errors++;
b6d77734
SH
2357 goto resubmit;
2358 }
6e15b712 2359
3be92a70 2360 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2361 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2362 dev->name, status, length);
793b883e
SH
2363
2364 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2365 dev->stats.rx_length_errors++;
cd28ab6a 2366 if (status & GMR_FS_FRAGMENT)
7138a0f5 2367 dev->stats.rx_frame_errors++;
cd28ab6a 2368 if (status & GMR_FS_CRC_ERR)
7138a0f5 2369 dev->stats.rx_crc_errors++;
79e57d32 2370
793b883e 2371 goto resubmit;
cd28ab6a
SH
2372}
2373
e07b1aa8
SH
2374/* Transmit complete */
2375static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2376{
e07b1aa8 2377 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2378
49d4b8ba 2379 if (netif_running(dev))
e07b1aa8 2380 sky2_tx_complete(sky2, last);
cd28ab6a
SH
2381}
2382
37e5a243
SH
2383static inline void sky2_skb_rx(const struct sky2_port *sky2,
2384 u32 status, struct sk_buff *skb)
2385{
2386#ifdef SKY2_VLAN_TAG_USED
2387 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2388 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2389 if (skb->ip_summed == CHECKSUM_NONE)
2390 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2391 else
2392 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2393 vlan_tag, skb);
2394 return;
2395 }
2396#endif
2397 if (skb->ip_summed == CHECKSUM_NONE)
2398 netif_receive_skb(skb);
2399 else
2400 napi_gro_receive(&sky2->hw->napi, skb);
2401}
2402
bf15fe99
SH
2403static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2404 unsigned packets, unsigned bytes)
2405{
2406 if (packets) {
2407 struct net_device *dev = hw->dev[port];
2408
2409 dev->stats.rx_packets += packets;
2410 dev->stats.rx_bytes += bytes;
2411 dev->last_rx = jiffies;
2412 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2413 }
2414}
2415
e07b1aa8 2416/* Process status response ring */
26691830 2417static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2418{
e07b1aa8 2419 int work_done = 0;
bf15fe99
SH
2420 unsigned int total_bytes[2] = { 0 };
2421 unsigned int total_packets[2] = { 0 };
a8fd6266 2422
af2a58ac 2423 rmb();
26691830 2424 do {
55c9dd35 2425 struct sky2_port *sky2;
13210ce5 2426 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2427 unsigned port;
13210ce5 2428 struct net_device *dev;
cd28ab6a 2429 struct sk_buff *skb;
cd28ab6a
SH
2430 u32 status;
2431 u16 length;
ab5adecb
SH
2432 u8 opcode = le->opcode;
2433
2434 if (!(opcode & HW_OWNER))
2435 break;
cd28ab6a 2436
cb5d9547 2437 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2438
ab5adecb 2439 port = le->css & CSS_LINK_BIT;
69161611 2440 dev = hw->dev[port];
13210ce5 2441 sky2 = netdev_priv(dev);
f65b138c
SH
2442 length = le16_to_cpu(le->length);
2443 status = le32_to_cpu(le->status);
cd28ab6a 2444
ab5adecb
SH
2445 le->opcode = 0;
2446 switch (opcode & ~HW_OWNER) {
cd28ab6a 2447 case OP_RXSTAT:
bf15fe99
SH
2448 total_packets[port]++;
2449 total_bytes[port] += length;
497d7c86 2450 skb = sky2_receive(dev, length, status);
3225b919 2451 if (unlikely(!skb)) {
7138a0f5 2452 dev->stats.rx_dropped++;
55c9dd35 2453 break;
3225b919 2454 }
13210ce5 2455
69161611 2456 /* This chip reports checksum status differently */
05745c4a 2457 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2458 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH
2459 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2460 (le->css & CSS_TCPUDPCSOK))
2461 skb->ip_summed = CHECKSUM_UNNECESSARY;
2462 else
2463 skb->ip_summed = CHECKSUM_NONE;
2464 }
2465
13210ce5 2466 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2467
37e5a243 2468 sky2_skb_rx(sky2, status, skb);
13210ce5 2469
22e11703 2470 /* Stop after net poll weight */
13210ce5 2471 if (++work_done >= to_do)
2472 goto exit_loop;
cd28ab6a
SH
2473 break;
2474
d1f13708 2475#ifdef SKY2_VLAN_TAG_USED
2476 case OP_RXVLAN:
2477 sky2->rx_tag = length;
2478 break;
2479
2480 case OP_RXCHKSVLAN:
2481 sky2->rx_tag = length;
2482 /* fall through */
2483#endif
cd28ab6a 2484 case OP_RXCHKS:
0ea065e5 2485 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
87418307
SH
2486 break;
2487
05745c4a
SH
2488 /* If this happens then driver assuming wrong format */
2489 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2490 if (net_ratelimit())
2491 printk(KERN_NOTICE "%s: unexpected"
2492 " checksum status\n",
2493 dev->name);
69161611 2494 break;
05745c4a 2495 }
69161611 2496
87418307
SH
2497 /* Both checksum counters are programmed to start at
2498 * the same offset, so unless there is a problem they
2499 * should match. This failure is an early indication that
2500 * hardware receive checksumming won't work.
2501 */
2502 if (likely(status >> 16 == (status & 0xffff))) {
2503 skb = sky2->rx_ring[sky2->rx_next].skb;
2504 skb->ip_summed = CHECKSUM_COMPLETE;
b9389796 2505 skb->csum = le16_to_cpu(status);
87418307
SH
2506 } else {
2507 printk(KERN_NOTICE PFX "%s: hardware receive "
2508 "checksum problem (status = %#x)\n",
2509 dev->name, status);
0ea065e5
SH
2510 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2511
87418307 2512 sky2_write32(sky2->hw,
69161611 2513 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH
2514 BMU_DIS_RX_CHKSUM);
2515 }
cd28ab6a
SH
2516 break;
2517
2518 case OP_TXINDEXLE:
13b97b74 2519 /* TX index reports status for both ports */
f55925d7
SH
2520 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2521 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH
2522 if (hw->dev[1])
2523 sky2_tx_done(hw->dev[1],
2524 ((status >> 24) & 0xff)
2525 | (u16)(length & 0xf) << 8);
cd28ab6a
SH
2526 break;
2527
cd28ab6a
SH
2528 default:
2529 if (net_ratelimit())
793b883e 2530 printk(KERN_WARNING PFX
ab5adecb 2531 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2532 }
26691830 2533 } while (hw->st_idx != idx);
cd28ab6a 2534
fe2a24df
SH
2535 /* Fully processed status ring so clear irq */
2536 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2537
13210ce5 2538exit_loop:
bf15fe99
SH
2539 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2540 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2541
e07b1aa8 2542 return work_done;
cd28ab6a
SH
2543}
2544
2545static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2546{
2547 struct net_device *dev = hw->dev[port];
2548
3be92a70
SH
2549 if (net_ratelimit())
2550 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2551 dev->name, status);
cd28ab6a
SH
2552
2553 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH
2554 if (net_ratelimit())
2555 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2556 dev->name);
cd28ab6a
SH
2557 /* Clear IRQ */
2558 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2559 }
2560
2561 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH
2562 if (net_ratelimit())
2563 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2564 dev->name);
cd28ab6a
SH
2565
2566 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2567 }
2568
2569 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH
2570 if (net_ratelimit())
2571 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH
2572 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2573 }
2574
2575 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH
2576 if (net_ratelimit())
2577 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH
2578 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2579 }
2580
2581 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH
2582 if (net_ratelimit())
2583 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2584 dev->name);
cd28ab6a
SH
2585 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2586 }
2587}
2588
2589static void sky2_hw_intr(struct sky2_hw *hw)
2590{
555382cb 2591 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2592 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH
2593 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2594
2595 status &= hwmsk;
cd28ab6a 2596
793b883e 2597 if (status & Y2_IS_TIST_OV)
cd28ab6a 2598 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH
2599
2600 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH
2601 u16 pci_err;
2602
82637e80 2603 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2604 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2605 if (net_ratelimit())
555382cb 2606 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2607 pci_err);
cd28ab6a 2608
b32f40c4 2609 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2610 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2611 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH
2612 }
2613
2614 if (status & Y2_IS_PCI_EXP) {
d571b694 2615 /* PCI-Express uncorrectable Error occurred */
555382cb 2616 u32 err;
cd28ab6a 2617
82637e80 2618 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH
2619 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2620 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2621 0xfffffffful);
3be92a70 2622 if (net_ratelimit())
555382cb 2623 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2624
7782c8c4 2625 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2626 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH
2627 }
2628
2629 if (status & Y2_HWE_L1_MASK)
2630 sky2_hw_error(hw, 0, status);
2631 status >>= 8;
2632 if (status & Y2_HWE_L1_MASK)
2633 sky2_hw_error(hw, 1, status);
2634}
2635
2636static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2637{
2638 struct net_device *dev = hw->dev[port];
2639 struct sky2_port *sky2 = netdev_priv(dev);
2640 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2641
2642 if (netif_msg_intr(sky2))
2643 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2644 dev->name, status);
2645
a3caeada
SH
2646 if (status & GM_IS_RX_CO_OV)
2647 gma_read16(hw, port, GM_RX_IRQ_SRC);
2648
2649 if (status & GM_IS_TX_CO_OV)
2650 gma_read16(hw, port, GM_TX_IRQ_SRC);
2651
cd28ab6a 2652 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2653 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH
2654 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2655 }
2656
2657 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2658 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH
2659 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2660 }
cd28ab6a
SH
2661}
2662
40b01727 2663/* This should never happen it is a bug. */
c119731d 2664static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH
2665{
2666 struct net_device *dev = hw->dev[port];
c119731d 2667 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2668
c119731d
SH
2669 dev_err(&hw->pdev->dev, PFX
2670 "%s: descriptor error q=%#x get=%u put=%u\n",
2671 dev->name, (unsigned) q, (unsigned) idx,
2672 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2673
40b01727 2674 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2675}
cd28ab6a 2676
75e80683
SH
2677static int sky2_rx_hung(struct net_device *dev)
2678{
2679 struct sky2_port *sky2 = netdev_priv(dev);
2680 struct sky2_hw *hw = sky2->hw;
2681 unsigned port = sky2->port;
2682 unsigned rxq = rxqaddr[port];
2683 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2684 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2685 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2686 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2687
2688 /* If idle and MAC or PCI is stuck */
2689 if (sky2->check.last == dev->last_rx &&
2690 ((mac_rp == sky2->check.mac_rp &&
2691 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2692 /* Check if the PCI RX hang */
2693 (fifo_rp == sky2->check.fifo_rp &&
2694 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2695 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2696 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2697 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2698 return 1;
2699 } else {
2700 sky2->check.last = dev->last_rx;
2701 sky2->check.mac_rp = mac_rp;
2702 sky2->check.mac_lev = mac_lev;
2703 sky2->check.fifo_rp = fifo_rp;
2704 sky2->check.fifo_lev = fifo_lev;
2705 return 0;
2706 }
2707}
2708
32c2c300 2709static void sky2_watchdog(unsigned long arg)
d27ed387 2710{
01bd7564 2711 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2712
75e80683 2713 /* Check for lost IRQ once a second */
32c2c300 2714 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2715 napi_schedule(&hw->napi);
75e80683
SH
2716 } else {
2717 int i, active = 0;
2718
2719 for (i = 0; i < hw->ports; i++) {
bea3348e 2720 struct net_device *dev = hw->dev[i];
75e80683
SH
2721 if (!netif_running(dev))
2722 continue;
2723 ++active;
2724
2725 /* For chips with Rx FIFO, check if stuck */
39dbd958 2726 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH
2727 sky2_rx_hung(dev)) {
2728 pr_info(PFX "%s: receiver hang detected\n",
2729 dev->name);
2730 schedule_work(&hw->restart_work);
2731 return;
2732 }
2733 }
2734
2735 if (active == 0)
2736 return;
32c2c300 2737 }
01bd7564 2738
75e80683 2739 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH
2740}
2741
40b01727
SH
2742/* Hardware/software error handling */
2743static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2744{
40b01727
SH
2745 if (net_ratelimit())
2746 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2747
1e5f1283
SH
2748 if (status & Y2_IS_HW_ERR)
2749 sky2_hw_intr(hw);
d257924e 2750
1e5f1283
SH
2751 if (status & Y2_IS_IRQ_MAC1)
2752 sky2_mac_intr(hw, 0);
cd28ab6a 2753
1e5f1283
SH
2754 if (status & Y2_IS_IRQ_MAC2)
2755 sky2_mac_intr(hw, 1);
cd28ab6a 2756
1e5f1283 2757 if (status & Y2_IS_CHK_RX1)
c119731d 2758 sky2_le_error(hw, 0, Q_R1);
d257924e 2759
1e5f1283 2760 if (status & Y2_IS_CHK_RX2)
c119731d 2761 sky2_le_error(hw, 1, Q_R2);
d257924e 2762
1e5f1283 2763 if (status & Y2_IS_CHK_TXA1)
c119731d 2764 sky2_le_error(hw, 0, Q_XA1);
d257924e 2765
1e5f1283 2766 if (status & Y2_IS_CHK_TXA2)
c119731d 2767 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH
2768}
2769
bea3348e 2770static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2771{
bea3348e 2772 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2773 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2774 int work_done = 0;
26691830 2775 u16 idx;
40b01727
SH
2776
2777 if (unlikely(status & Y2_IS_ERROR))
2778 sky2_err_intr(hw, status);
2779
2780 if (status & Y2_IS_IRQ_PHY1)
2781 sky2_phy_intr(hw, 0);
2782
2783 if (status & Y2_IS_IRQ_PHY2)
2784 sky2_phy_intr(hw, 1);
cd28ab6a 2785
26691830
SH
2786 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2787 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM
2788
2789 if (work_done >= work_limit)
26691830
SH
2790 goto done;
2791 }
6f535763 2792
26691830
SH
2793 napi_complete(napi);
2794 sky2_read32(hw, B0_Y2_SP_LISR);
2795done:
6f535763 2796
bea3348e 2797 return work_done;
e07b1aa8
SH
2798}
2799
7d12e780 2800static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH
2801{
2802 struct sky2_hw *hw = dev_id;
e07b1aa8
SH
2803 u32 status;
2804
2805 /* Reading this mask interrupts as side effect */
2806 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2807 if (status == 0 || status == ~0)
2808 return IRQ_NONE;
793b883e 2809
e07b1aa8 2810 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH
2811
2812 napi_schedule(&hw->napi);
793b883e 2813
cd28ab6a
SH
2814 return IRQ_HANDLED;
2815}
2816
2817#ifdef CONFIG_NET_POLL_CONTROLLER
2818static void sky2_netpoll(struct net_device *dev)
2819{
2820 struct sky2_port *sky2 = netdev_priv(dev);
2821
bea3348e 2822 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH
2823}
2824#endif
2825
2826/* Chip internal frequency for clock calculations */
05745c4a 2827static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2828{
793b883e 2829 switch (hw->chip_id) {
cd28ab6a 2830 case CHIP_ID_YUKON_EC:
5a5b1ea0 2831 case CHIP_ID_YUKON_EC_U:
93745494 2832 case CHIP_ID_YUKON_EX:
ed4d4161 2833 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2834 case CHIP_ID_YUKON_UL_2:
05745c4a
SH
2835 return 125;
2836
cd28ab6a 2837 case CHIP_ID_YUKON_FE:
05745c4a
SH
2838 return 100;
2839
2840 case CHIP_ID_YUKON_FE_P:
2841 return 50;
2842
2843 case CHIP_ID_YUKON_XL:
2844 return 156;
2845
2846 default:
2847 BUG();
cd28ab6a
SH
2848 }
2849}
2850
fb17358f 2851static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2852{
fb17358f 2853 return sky2_mhz(hw) * us;
cd28ab6a
SH
2854}
2855
fb17358f 2856static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2857{
fb17358f 2858 return clk / sky2_mhz(hw);
cd28ab6a
SH
2859}
2860
fb17358f 2861
e3173832 2862static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2863{
b89165f2 2864 u8 t8;
cd28ab6a 2865
167f53d0 2866 /* Enable all clocks and check for bad PCI access */
b32f40c4 2867 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2868
cd28ab6a 2869 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2870
cd28ab6a 2871 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH
2872 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2873
2874 switch(hw->chip_id) {
2875 case CHIP_ID_YUKON_XL:
39dbd958 2876 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH
2877 break;
2878
2879 case CHIP_ID_YUKON_EC_U:
2880 hw->flags = SKY2_HW_GIGABIT
2881 | SKY2_HW_NEWER_PHY
2882 | SKY2_HW_ADV_POWER_CTL;
2883 break;
2884
2885 case CHIP_ID_YUKON_EX:
2886 hw->flags = SKY2_HW_GIGABIT
2887 | SKY2_HW_NEWER_PHY
2888 | SKY2_HW_NEW_LE
2889 | SKY2_HW_ADV_POWER_CTL;
2890
2891 /* New transmit checksum */
2892 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2893 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2894 break;
2895
2896 case CHIP_ID_YUKON_EC:
2897 /* This rev is really old, and requires untested workarounds */
2898 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2899 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2900 return -EOPNOTSUPP;
2901 }
39dbd958 2902 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH
2903 break;
2904
2905 case CHIP_ID_YUKON_FE:
ea76e635
SH
2906 break;
2907
05745c4a
SH
2908 case CHIP_ID_YUKON_FE_P:
2909 hw->flags = SKY2_HW_NEWER_PHY
2910 | SKY2_HW_NEW_LE
2911 | SKY2_HW_AUTO_TX_SUM
2912 | SKY2_HW_ADV_POWER_CTL;
2913 break;
ed4d4161
SH
2914
2915 case CHIP_ID_YUKON_SUPR:
2916 hw->flags = SKY2_HW_GIGABIT
2917 | SKY2_HW_NEWER_PHY
2918 | SKY2_HW_NEW_LE
2919 | SKY2_HW_AUTO_TX_SUM
2920 | SKY2_HW_ADV_POWER_CTL;
2921 break;
2922
0ce8b98d
SH
2923 case CHIP_ID_YUKON_UL_2:
2924 hw->flags = SKY2_HW_GIGABIT
2925 | SKY2_HW_ADV_POWER_CTL;
2926 break;
2927
ea76e635 2928 default:
b02a9258
SH
2929 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2930 hw->chip_id);
cd28ab6a
SH
2931 return -EOPNOTSUPP;
2932 }
2933
ea76e635
SH
2934 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2935 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2936 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2937
e3173832
SH
2938 hw->ports = 1;
2939 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2940 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2941 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2942 ++hw->ports;
2943 }
2944
2945 return 0;
2946}
2947
2948static void sky2_reset(struct sky2_hw *hw)
2949{
555382cb 2950 struct pci_dev *pdev = hw->pdev;
e3173832 2951 u16 status;
555382cb
SH
2952 int i, cap;
2953 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2954
cd28ab6a 2955 /* disable ASF */
4f44d8ba
SH
2956 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2957 status = sky2_read16(hw, HCU_CCSR);
2958 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2959 HCU_CCSR_UC_STATE_MSK);
2960 sky2_write16(hw, HCU_CCSR, status);
2961 } else
2962 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2963 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH
2964
2965 /* do a SW reset */
2966 sky2_write8(hw, B0_CTST, CS_RST_SET);
2967 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2968
ac93a394
SH
2969 /* allow writes to PCI config */
2970 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2971
cd28ab6a 2972 /* clear PCI errors, if any */
b32f40c4 2973 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2974 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2975 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH
2976
2977 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2978
555382cb
SH
2979 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2980 if (cap) {
7782c8c4
SH
2981 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2982 0xfffffffful);
555382cb
SH
2983
2984 /* If error bit is stuck on ignore it */
2985 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2986 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2987 else
555382cb
SH
2988 hwe_mask |= Y2_IS_PCI_EXP;
2989 }
cd28ab6a 2990
ae306cca 2991 sky2_power_on(hw);
82637e80 2992 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH
2993
2994 for (i = 0; i < hw->ports; i++) {
2995 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2996 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2997
ed4d4161
SH
2998 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2999 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH
3000 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3001 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3002 | GMC_BYP_RETR_ON);
cd28ab6a
SH
3003 }
3004
793b883e
SH
3005 /* Clear I2C IRQ noise */
3006 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH
3007
3008 /* turn off hardware timer (unused) */
3009 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3010 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3011
cd28ab6a
SH
3012 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
3013
69634ee7
SH
3014 /* Turn off descriptor polling */
3015 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH
3016
3017 /* Turn off receive timestamp */
3018 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3019 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH
3020
3021 /* enable the Tx Arbiters */
3022 for (i = 0; i < hw->ports; i++)
3023 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3024
3025 /* Initialize ram interface */
3026 for (i = 0; i < hw->ports; i++) {
793b883e 3027 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH
3028
3029 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3030 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3031 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3032 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3033 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3034 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3035 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3036 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3037 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3038 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3039 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3040 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3041 }
3042
555382cb 3043 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3044
cd28ab6a 3045 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3046 sky2_gmac_reset(hw, i);
cd28ab6a 3047
cd28ab6a
SH
3048 memset(hw->st_le, 0, STATUS_LE_BYTES);
3049 hw->st_idx = 0;
3050
3051 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3052 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3053
3054 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3055 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH
3056
3057 /* Set the list last index */
793b883e 3058 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3059
290d4de5
SH
3060 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3061 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3062
290d4de5
SH
3063 /* set Status-FIFO ISR watermark */
3064 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3065 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3066 else
3067 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3068
290d4de5 3069 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH
3070 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3071 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3072
793b883e 3073 /* enable status unit */
cd28ab6a
SH
3074 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3075
3076 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3077 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3078 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH
3079}
3080
af18d8b8
SH
3081/* Take device down (offline).
3082 * Equivalent to doing dev_stop() but this does not
3083 * inform upper layers of the transistion.
3084 */
3085static void sky2_detach(struct net_device *dev)
3086{
3087 if (netif_running(dev)) {
3088 netif_device_detach(dev); /* stop txq */
3089 sky2_down(dev);
3090 }
3091}
3092
3093/* Bring device back after doing sky2_detach */
3094static int sky2_reattach(struct net_device *dev)
3095{
3096 int err = 0;
3097
3098 if (netif_running(dev)) {
3099 err = sky2_up(dev);
3100 if (err) {
3101 printk(KERN_INFO PFX "%s: could not restart %d\n",
3102 dev->name, err);
3103 dev_close(dev);
3104 } else {
3105 netif_device_attach(dev);
3106 sky2_set_multicast(dev);
3107 }
3108 }
3109
3110 return err;
3111}
3112
81906791
SH
3113static void sky2_restart(struct work_struct *work)
3114{
3115 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3116 int i;
81906791 3117
81906791 3118 rtnl_lock();
af18d8b8
SH
3119 for (i = 0; i < hw->ports; i++)
3120 sky2_detach(hw->dev[i]);
81906791 3121
8cfcbe99
SH
3122 napi_disable(&hw->napi);
3123 sky2_write32(hw, B0_IMSK, 0);
81906791
SH
3124 sky2_reset(hw);
3125 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3126 napi_enable(&hw->napi);
81906791 3127
af18d8b8
SH
3128 for (i = 0; i < hw->ports; i++)
3129 sky2_reattach(hw->dev[i]);
81906791 3130
81906791
SH
3131 rtnl_unlock();
3132}
3133
e3173832
SH
3134static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3135{
3136 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3137}
3138
3139static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3140{
3141 const struct sky2_port *sky2 = netdev_priv(dev);
3142
3143 wol->supported = sky2_wol_supported(sky2->hw);
3144 wol->wolopts = sky2->wol;
3145}
3146
3147static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3148{
3149 struct sky2_port *sky2 = netdev_priv(dev);
3150 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3151
9d731d77
RW
3152 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3153 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH
3154 return -EOPNOTSUPP;
3155
3156 sky2->wol = wol->wolopts;
3157
05745c4a
SH
3158 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3159 hw->chip_id == CHIP_ID_YUKON_EX ||
3160 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH
3161 sky2_write32(hw, B0_CTST, sky2->wol
3162 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3163
9d731d77
RW
3164 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3165
e3173832
SH
3166 if (!netif_running(dev))
3167 sky2_wol_init(sky2);
cd28ab6a
SH
3168 return 0;
3169}
3170
28bd181a 3171static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3172{
b89165f2
SH
3173 if (sky2_is_copper(hw)) {
3174 u32 modes = SUPPORTED_10baseT_Half
3175 | SUPPORTED_10baseT_Full
3176 | SUPPORTED_100baseT_Half
3177 | SUPPORTED_100baseT_Full
3178 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3179
ea76e635 3180 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3181 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH
3182 | SUPPORTED_1000baseT_Full;
3183 return modes;
cd28ab6a 3184 } else
b89165f2
SH
3185 return SUPPORTED_1000baseT_Half
3186 | SUPPORTED_1000baseT_Full
3187 | SUPPORTED_Autoneg
3188 | SUPPORTED_FIBRE;
cd28ab6a
SH
3189}
3190
793b883e 3191static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH
3192{
3193 struct sky2_port *sky2 = netdev_priv(dev);
3194 struct sky2_hw *hw = sky2->hw;
3195
3196 ecmd->transceiver = XCVR_INTERNAL;
3197 ecmd->supported = sky2_supported_modes(hw);
3198 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3199 if (sky2_is_copper(hw)) {
cd28ab6a 3200 ecmd->port = PORT_TP;
b89165f2
SH
3201 ecmd->speed = sky2->speed;
3202 } else {
3203 ecmd->speed = SPEED_1000;
cd28ab6a 3204 ecmd->port = PORT_FIBRE;
b89165f2 3205 }
cd28ab6a
SH
3206
3207 ecmd->advertising = sky2->advertising;
0ea065e5
SH
3208 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3209 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH
3210 ecmd->duplex = sky2->duplex;
3211 return 0;
3212}
3213
3214static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3215{
3216 struct sky2_port *sky2 = netdev_priv(dev);
3217 const struct sky2_hw *hw = sky2->hw;
3218 u32 supported = sky2_supported_modes(hw);
3219
3220 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3221 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH
3222 ecmd->advertising = supported;
3223 sky2->duplex = -1;
3224 sky2->speed = -1;
3225 } else {
3226 u32 setting;
3227
793b883e 3228 switch (ecmd->speed) {
cd28ab6a
SH
3229 case SPEED_1000:
3230 if (ecmd->duplex == DUPLEX_FULL)
3231 setting = SUPPORTED_1000baseT_Full;
3232 else if (ecmd->duplex == DUPLEX_HALF)
3233 setting = SUPPORTED_1000baseT_Half;
3234 else
3235 return -EINVAL;
3236 break;
3237 case SPEED_100:
3238 if (ecmd->duplex == DUPLEX_FULL)
3239 setting = SUPPORTED_100baseT_Full;
3240 else if (ecmd->duplex == DUPLEX_HALF)
3241 setting = SUPPORTED_100baseT_Half;
3242 else
3243 return -EINVAL;
3244 break;
3245
3246 case SPEED_10:
3247 if (ecmd->duplex == DUPLEX_FULL)
3248 setting = SUPPORTED_10baseT_Full;
3249 else if (ecmd->duplex == DUPLEX_HALF)
3250 setting = SUPPORTED_10baseT_Half;
3251 else
3252 return -EINVAL;
3253 break;
3254 default:
3255 return -EINVAL;
3256 }
3257
3258 if ((setting & supported) == 0)
3259 return -EINVAL;
3260
3261 sky2->speed = ecmd->speed;
3262 sky2->duplex = ecmd->duplex;
0ea065e5 3263 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH
3264 }
3265
cd28ab6a
SH
3266 sky2->advertising = ecmd->advertising;
3267
d1b139c0 3268 if (netif_running(dev)) {
1b537565 3269 sky2_phy_reinit(sky2);
d1b139c0
SH
3270 sky2_set_multicast(dev);
3271 }
cd28ab6a
SH
3272
3273 return 0;
3274}
3275
3276static void sky2_get_drvinfo(struct net_device *dev,
3277 struct ethtool_drvinfo *info)
3278{
3279 struct sky2_port *sky2 = netdev_priv(dev);
3280
3281 strcpy(info->driver, DRV_NAME);
3282 strcpy(info->version, DRV_VERSION);
3283 strcpy(info->fw_version, "N/A");
3284 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3285}
3286
3287static const struct sky2_stat {
793b883e
SH
3288 char name[ETH_GSTRING_LEN];
3289 u16 offset;
cd28ab6a
SH
3290} sky2_stats[] = {
3291 { "tx_bytes", GM_TXO_OK_HI },
3292 { "rx_bytes", GM_RXO_OK_HI },
3293 { "tx_broadcast", GM_TXF_BC_OK },
3294 { "rx_broadcast", GM_RXF_BC_OK },
3295 { "tx_multicast", GM_TXF_MC_OK },
3296 { "rx_multicast", GM_RXF_MC_OK },
3297 { "tx_unicast", GM_TXF_UC_OK },
3298 { "rx_unicast", GM_RXF_UC_OK },
3299 { "tx_mac_pause", GM_TXF_MPAUSE },
3300 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3301 { "collisions", GM_TXF_COL },
cd28ab6a
SH
3302 { "late_collision",GM_TXF_LAT_COL },
3303 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3304 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3305 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3306
d2604540 3307 { "rx_short", GM_RXF_SHT },
cd28ab6a 3308 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH
3309 { "rx_64_byte_packets", GM_RXF_64B },
3310 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3311 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3312 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3313 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3314 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3315 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3316 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH
3317 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3318 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3319 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH
3320
3321 { "tx_64_byte_packets", GM_TXF_64B },
3322 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3323 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3324 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3325 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3326 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3327 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3328 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH
3329};
3330
cd28ab6a
SH
3331static u32 sky2_get_rx_csum(struct net_device *dev)
3332{
3333 struct sky2_port *sky2 = netdev_priv(dev);
3334
0ea065e5 3335 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH
3336}
3337
3338static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3339{
3340 struct sky2_port *sky2 = netdev_priv(dev);
3341
0ea065e5
SH
3342 if (data)
3343 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3344 else
3345 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3346
cd28ab6a
SH
3347 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3348 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3349
3350 return 0;
3351}
3352
3353static u32 sky2_get_msglevel(struct net_device *netdev)
3354{
3355 struct sky2_port *sky2 = netdev_priv(netdev);
3356 return sky2->msg_enable;
3357}
3358
9a7ae0a9
SH
3359static int sky2_nway_reset(struct net_device *dev)
3360{
3361 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3362
0ea065e5 3363 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH
3364 return -EINVAL;
3365
1b537565 3366 sky2_phy_reinit(sky2);
d1b139c0 3367 sky2_set_multicast(dev);
9a7ae0a9
SH
3368
3369 return 0;
3370}
3371
793b883e 3372static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH
3373{
3374 struct sky2_hw *hw = sky2->hw;
3375 unsigned port = sky2->port;
3376 int i;
3377
3378 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3379 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3380 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3381 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3382
793b883e 3383 for (i = 2; i < count; i++)
cd28ab6a
SH
3384 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3385}
3386
cd28ab6a
SH
3387static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3388{
3389 struct sky2_port *sky2 = netdev_priv(netdev);
3390 sky2->msg_enable = value;
3391}
3392
b9f2c044 3393static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3394{
b9f2c044
JG
3395 switch (sset) {
3396 case ETH_SS_STATS:
3397 return ARRAY_SIZE(sky2_stats);
3398 default:
3399 return -EOPNOTSUPP;
3400 }
cd28ab6a
SH
3401}
3402
3403static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3404 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH
3405{
3406 struct sky2_port *sky2 = netdev_priv(dev);
3407
793b883e 3408 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH
3409}
3410
793b883e 3411static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH
3412{
3413 int i;
3414
3415 switch (stringset) {
3416 case ETH_SS_STATS:
3417 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3418 memcpy(data + i * ETH_GSTRING_LEN,
3419 sky2_stats[i].name, ETH_GSTRING_LEN);
3420 break;
3421 }
3422}
3423
cd28ab6a
SH
3424static int sky2_set_mac_address(struct net_device *dev, void *p)
3425{
3426 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH
3427 struct sky2_hw *hw = sky2->hw;
3428 unsigned port = sky2->port;
3429 const struct sockaddr *addr = p;
cd28ab6a
SH
3430
3431 if (!is_valid_ether_addr(addr->sa_data))
3432 return -EADDRNOTAVAIL;
3433
cd28ab6a 3434 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3435 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3436 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3437 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3438 dev->dev_addr, ETH_ALEN);
1b537565 3439
a8ab1ec0
SH
3440 /* virtual address for data */
3441 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3442
3443 /* physical address: used for pause frames */
3444 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH
3445
3446 return 0;
cd28ab6a
SH
3447}
3448
a052b52f
SH
3449static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3450{
3451 u32 bit;
3452
3453 bit = ether_crc(ETH_ALEN, addr) & 63;
3454 filter[bit >> 3] |= 1 << (bit & 7);
3455}
3456
cd28ab6a
SH
3457static void sky2_set_multicast(struct net_device *dev)
3458{
3459 struct sky2_port *sky2 = netdev_priv(dev);
3460 struct sky2_hw *hw = sky2->hw;
3461 unsigned port = sky2->port;
3462 struct dev_mc_list *list = dev->mc_list;
3463 u16 reg;
3464 u8 filter[8];
a052b52f
SH
3465 int rx_pause;
3466 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3467
a052b52f 3468 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH
3469 memset(filter, 0, sizeof(filter));
3470
3471 reg = gma_read16(hw, port, GM_RX_CTRL);
3472 reg |= GM_RXCR_UCF_ENA;
3473
d571b694 3474 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3475 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3476 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3477 memset(filter, 0xff, sizeof(filter));
a052b52f 3478 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH
3479 reg &= ~GM_RXCR_MCF_ENA;
3480 else {
3481 int i;
3482 reg |= GM_RXCR_MCF_ENA;
3483
a052b52f
SH
3484 if (rx_pause)
3485 sky2_add_filter(filter, pause_mc_addr);
3486
3487 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3488 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH
3489 }
3490
cd28ab6a 3491 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3492 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3493 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3494 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3495 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3496 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3497 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3498 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH
3499
3500 gma_write16(hw, port, GM_RX_CTRL, reg);
3501}
3502
3503/* Can have one global because blinking is controlled by
3504 * ethtool and that is always under RTNL mutex
3505 */
a84d0a3d 3506static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3507{
a84d0a3d
SH
3508 struct sky2_hw *hw = sky2->hw;
3509 unsigned port = sky2->port;
793b883e 3510
a84d0a3d
SH
3511 spin_lock_bh(&sky2->phy_lock);
3512 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3513 hw->chip_id == CHIP_ID_YUKON_EX ||
3514 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3515 u16 pg;
793b883e
SH
3516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3517 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3518
a84d0a3d
SH
3519 switch (mode) {
3520 case MO_LED_OFF:
3521 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3522 PHY_M_LEDC_LOS_CTRL(8) |
3523 PHY_M_LEDC_INIT_CTRL(8) |
3524 PHY_M_LEDC_STA1_CTRL(8) |
3525 PHY_M_LEDC_STA0_CTRL(8));
3526 break;
3527 case MO_LED_ON:
3528 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3529 PHY_M_LEDC_LOS_CTRL(9) |
3530 PHY_M_LEDC_INIT_CTRL(9) |
3531 PHY_M_LEDC_STA1_CTRL(9) |
3532 PHY_M_LEDC_STA0_CTRL(9));
3533 break;
3534 case MO_LED_BLINK:
3535 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3536 PHY_M_LEDC_LOS_CTRL(0xa) |
3537 PHY_M_LEDC_INIT_CTRL(0xa) |
3538 PHY_M_LEDC_STA1_CTRL(0xa) |
3539 PHY_M_LEDC_STA0_CTRL(0xa));
3540 break;
3541 case MO_LED_NORM:
3542 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3543 PHY_M_LEDC_LOS_CTRL(1) |
3544 PHY_M_LEDC_INIT_CTRL(8) |
3545 PHY_M_LEDC_STA1_CTRL(7) |
3546 PHY_M_LEDC_STA0_CTRL(7));
3547 }
793b883e 3548
a84d0a3d
SH
3549 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3550 } else
7d2e3cb7 3551 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH
3552 PHY_M_LED_MO_DUP(mode) |
3553 PHY_M_LED_MO_10(mode) |
3554 PHY_M_LED_MO_100(mode) |
3555 PHY_M_LED_MO_1000(mode) |
3556 PHY_M_LED_MO_RX(mode) |
3557 PHY_M_LED_MO_TX(mode));
3558
3559 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH
3560}
3561
3562/* blink LED's for finding board */
3563static int sky2_phys_id(struct net_device *dev, u32 data)
3564{
3565 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3566 unsigned int i;
cd28ab6a 3567
a84d0a3d
SH
3568 if (data == 0)
3569 data = UINT_MAX;
cd28ab6a 3570
a84d0a3d
SH
3571 for (i = 0; i < data; i++) {
3572 sky2_led(sky2, MO_LED_ON);
3573 if (msleep_interruptible(500))
3574 break;
3575 sky2_led(sky2, MO_LED_OFF);
3576 if (msleep_interruptible(500))
3577 break;
793b883e 3578 }
a84d0a3d 3579 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH
3580
3581 return 0;
3582}
3583
3584static void sky2_get_pauseparam(struct net_device *dev,
3585 struct ethtool_pauseparam *ecmd)
3586{
3587 struct sky2_port *sky2 = netdev_priv(dev);
3588
16ad91e1
SH
3589 switch (sky2->flow_mode) {
3590 case FC_NONE:
3591 ecmd->tx_pause = ecmd->rx_pause = 0;
3592 break;
3593 case FC_TX:
3594 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3595 break;
3596 case FC_RX:
3597 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3598 break;
3599 case FC_BOTH:
3600 ecmd->tx_pause = ecmd->rx_pause = 1;
3601 }
3602
0ea065e5
SH
3603 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3604 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH
3605}
3606
3607static int sky2_set_pauseparam(struct net_device *dev,
3608 struct ethtool_pauseparam *ecmd)
3609{
3610 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3611
0ea065e5
SH
3612 if (ecmd->autoneg == AUTONEG_ENABLE)
3613 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3614 else
3615 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3616
16ad91e1 3617 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3618
16ad91e1
SH
3619 if (netif_running(dev))
3620 sky2_phy_reinit(sky2);
cd28ab6a 3621
2eaba1a2 3622 return 0;
cd28ab6a
SH
3623}
3624
fb17358f
SH
3625static int sky2_get_coalesce(struct net_device *dev,
3626 struct ethtool_coalesce *ecmd)
3627{
3628 struct sky2_port *sky2 = netdev_priv(dev);
3629 struct sky2_hw *hw = sky2->hw;
3630
3631 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3632 ecmd->tx_coalesce_usecs = 0;
3633 else {
3634 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3635 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3636 }
3637 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3638
3639 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3640 ecmd->rx_coalesce_usecs = 0;
3641 else {
3642 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3643 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3644 }
3645 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3646
3647 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3648 ecmd->rx_coalesce_usecs_irq = 0;
3649 else {
3650 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3651 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3652 }
3653
3654 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3655
3656 return 0;
3657}
3658
3659/* Note: this affect both ports */
3660static int sky2_set_coalesce(struct net_device *dev,
3661 struct ethtool_coalesce *ecmd)
3662{
3663 struct sky2_port *sky2 = netdev_priv(dev);
3664 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3665 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3666
77b3d6a2
SH
3667 if (ecmd->tx_coalesce_usecs > tmax ||
3668 ecmd->rx_coalesce_usecs > tmax ||
3669 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH
3670 return -EINVAL;
3671
ff81fbbe 3672 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3673 return -EINVAL;
ff81fbbe 3674 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3675 return -EINVAL;
ff81fbbe 3676 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH
3677 return -EINVAL;
3678
3679 if (ecmd->tx_coalesce_usecs == 0)
3680 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3681 else {
3682 sky2_write32(hw, STAT_TX_TIMER_INI,
3683 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3684 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3685 }
3686 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3687
3688 if (ecmd->rx_coalesce_usecs == 0)
3689 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3690 else {
3691 sky2_write32(hw, STAT_LEV_TIMER_INI,
3692 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3693 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3694 }
3695 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3696
3697 if (ecmd->rx_coalesce_usecs_irq == 0)
3698 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3699 else {
d28d4870 3700 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH
3701 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3702 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3703 }
3704 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3705 return 0;
3706}
3707
793b883e
SH
3708static void sky2_get_ringparam(struct net_device *dev,
3709 struct ethtool_ringparam *ering)
3710{
3711 struct sky2_port *sky2 = netdev_priv(dev);
3712
3713 ering->rx_max_pending = RX_MAX_PENDING;
3714 ering->rx_mini_max_pending = 0;
3715 ering->rx_jumbo_max_pending = 0;
3716 ering->tx_max_pending = TX_RING_SIZE - 1;
3717
3718 ering->rx_pending = sky2->rx_pending;
3719 ering->rx_mini_pending = 0;
3720 ering->rx_jumbo_pending = 0;
3721 ering->tx_pending = sky2->tx_pending;
3722}
3723
3724static int sky2_set_ringparam(struct net_device *dev,
3725 struct ethtool_ringparam *ering)
3726{
3727 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH
3728
3729 if (ering->rx_pending > RX_MAX_PENDING ||
3730 ering->rx_pending < 8 ||
3731 ering->tx_pending < MAX_SKB_TX_LE ||
3732 ering->tx_pending > TX_RING_SIZE - 1)
3733 return -EINVAL;
3734
af18d8b8 3735 sky2_detach(dev);
793b883e
SH
3736
3737 sky2->rx_pending = ering->rx_pending;
3738 sky2->tx_pending = ering->tx_pending;
3739
af18d8b8 3740 return sky2_reattach(dev);
793b883e
SH
3741}
3742
793b883e
SH
3743static int sky2_get_regs_len(struct net_device *dev)
3744{
6e4cbb34 3745 return 0x4000;
793b883e
SH
3746}
3747
3748/*
3749 * Returns copy of control register region
3ead5db7 3750 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH
3751 */
3752static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3753 void *p)
3754{
3755 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3756 const void __iomem *io = sky2->hw->regs;
295b54c4 3757 unsigned int b;
793b883e
SH
3758
3759 regs->version = 1;
793b883e 3760
295b54c4
SH
3761 for (b = 0; b < 128; b++) {
3762 /* This complicated switch statement is to make sure and
3763 * only access regions that are unreserved.
3764 * Some blocks are only valid on dual port cards.
3765 * and block 3 has some special diagnostic registers that
3766 * are poison.
3767 */
3768 switch (b) {
3769 case 3:
3770 /* skip diagnostic ram region */
3771 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3772 break;
3ead5db7 3773
295b54c4
SH
3774 /* dual port cards only */
3775 case 5: /* Tx Arbiter 2 */
3776 case 9: /* RX2 */
3777 case 14 ... 15: /* TX2 */
3778 case 17: case 19: /* Ram Buffer 2 */
3779 case 22 ... 23: /* Tx Ram Buffer 2 */
3780 case 25: /* Rx MAC Fifo 1 */
3781 case 27: /* Tx MAC Fifo 2 */
3782 case 31: /* GPHY 2 */
3783 case 40 ... 47: /* Pattern Ram 2 */
3784 case 52: case 54: /* TCP Segmentation 2 */
3785 case 112 ... 116: /* GMAC 2 */
3786 if (sky2->hw->ports == 1)
3787 goto reserved;
3788 /* fall through */
3789 case 0: /* Control */
3790 case 2: /* Mac address */
3791 case 4: /* Tx Arbiter 1 */
3792 case 7: /* PCI express reg */
3793 case 8: /* RX1 */
3794 case 12 ... 13: /* TX1 */
3795 case 16: case 18:/* Rx Ram Buffer 1 */
3796 case 20 ... 21: /* Tx Ram Buffer 1 */
3797 case 24: /* Rx MAC Fifo 1 */
3798 case 26: /* Tx MAC Fifo 1 */
3799 case 28 ... 29: /* Descriptor and status unit */
3800 case 30: /* GPHY 1*/
3801 case 32 ... 39: /* Pattern Ram 1 */
3802 case 48: case 50: /* TCP Segmentation 1 */
3803 case 56 ... 60: /* PCI space */
3804 case 80 ... 84: /* GMAC 1 */
3805 memcpy_fromio(p, io, 128);
3806 break;
3807 default:
3808reserved:
3809 memset(p, 0, 128);
3810 }
3ead5db7 3811
295b54c4
SH
3812 p += 128;
3813 io += 128;
3814 }
793b883e 3815}
cd28ab6a 3816
b628ed98
SH
3817/* In order to do Jumbo packets on these chips, need to turn off the
3818 * transmit store/forward. Therefore checksum offload won't work.
3819 */
3820static int no_tx_offload(struct net_device *dev)
3821{
3822 const struct sky2_port *sky2 = netdev_priv(dev);
3823 const struct sky2_hw *hw = sky2->hw;
3824
69161611 3825 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH
3826}
3827
3828static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3829{
3830 if (data && no_tx_offload(dev))
3831 return -EINVAL;
3832
3833 return ethtool_op_set_tx_csum(dev, data);
3834}
3835
3836
3837static int sky2_set_tso(struct net_device *dev, u32 data)
3838{
3839 if (data && no_tx_offload(dev))
3840 return -EINVAL;
3841
3842 return ethtool_op_set_tso(dev, data);
3843}
3844
f4331a6d
SH
3845static int sky2_get_eeprom_len(struct net_device *dev)
3846{
3847 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3848 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH
3849 u16 reg2;
3850
b32f40c4 3851 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH
3852 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3853}
3854
1413235c 3855static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3856{
1413235c 3857 unsigned long start = jiffies;
f4331a6d 3858
1413235c
SH
3859 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3860 /* Can take up to 10.6 ms for write */
3861 if (time_after(jiffies, start + HZ/4)) {
3862 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3863 return -ETIMEDOUT;
3864 }
3865 mdelay(1);
3866 }
167f53d0 3867
1413235c
SH
3868 return 0;
3869}
167f53d0 3870
1413235c
SH
3871static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3872 u16 offset, size_t length)
3873{
3874 int rc = 0;
3875
3876 while (length > 0) {
3877 u32 val;
3878
3879 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3880 rc = sky2_vpd_wait(hw, cap, 0);
3881 if (rc)
3882 break;
3883
3884 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3885
3886 memcpy(data, &val, min(sizeof(val), length));
3887 offset += sizeof(u32);
3888 data += sizeof(u32);
3889 length -= sizeof(u32);
3890 }
3891
3892 return rc;
f4331a6d
SH
3893}
3894
1413235c
SH
3895static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3896 u16 offset, unsigned int length)
f4331a6d 3897{
1413235c
SH
3898 unsigned int i;
3899 int rc = 0;
3900
3901 for (i = 0; i < length; i += sizeof(u32)) {
3902 u32 val = *(u32 *)(data + i);
3903
3904 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3905 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3906
3907 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3908 if (rc)
3909 break;
3910 }
3911 return rc;
f4331a6d
SH
3912}
3913
3914static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3915 u8 *data)
3916{
3917 struct sky2_port *sky2 = netdev_priv(dev);
3918 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH
3919
3920 if (!cap)
3921 return -EINVAL;
3922
3923 eeprom->magic = SKY2_EEPROM_MAGIC;
3924
1413235c 3925 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH
3926}
3927
3928static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3929 u8 *data)
3930{
3931 struct sky2_port *sky2 = netdev_priv(dev);
3932 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH
3933
3934 if (!cap)
3935 return -EINVAL;
3936
3937 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3938 return -EINVAL;
3939
1413235c
SH
3940 /* Partial writes not supported */
3941 if ((eeprom->offset & 3) || (eeprom->len & 3))
3942 return -EINVAL;
f4331a6d 3943
1413235c 3944 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH
3945}
3946
3947
7282d491 3948static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH
3949 .get_settings = sky2_get_settings,
3950 .set_settings = sky2_set_settings,
3951 .get_drvinfo = sky2_get_drvinfo,
3952 .get_wol = sky2_get_wol,
3953 .set_wol = sky2_set_wol,
3954 .get_msglevel = sky2_get_msglevel,
3955 .set_msglevel = sky2_set_msglevel,
3956 .nway_reset = sky2_nway_reset,
3957 .get_regs_len = sky2_get_regs_len,
3958 .get_regs = sky2_get_regs,
3959 .get_link = ethtool_op_get_link,
3960 .get_eeprom_len = sky2_get_eeprom_len,
3961 .get_eeprom = sky2_get_eeprom,
3962 .set_eeprom = sky2_set_eeprom,
f4331a6d 3963 .set_sg = ethtool_op_set_sg,
f4331a6d 3964 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH
3965 .set_tso = sky2_set_tso,
3966 .get_rx_csum = sky2_get_rx_csum,
3967 .set_rx_csum = sky2_set_rx_csum,
3968 .get_strings = sky2_get_strings,
3969 .get_coalesce = sky2_get_coalesce,
3970 .set_coalesce = sky2_set_coalesce,
3971 .get_ringparam = sky2_get_ringparam,
3972 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH
3973 .get_pauseparam = sky2_get_pauseparam,
3974 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3975 .phys_id = sky2_phys_id,
b9f2c044 3976 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH
3977 .get_ethtool_stats = sky2_get_ethtool_stats,
3978};
3979
3cf26753
SH
3980#ifdef CONFIG_SKY2_DEBUG
3981
3982static struct dentry *sky2_debug;
3983
e4c2abe2
SH
3984
3985/*
3986 * Read and parse the first part of Vital Product Data
3987 */
3988#define VPD_SIZE 128
3989#define VPD_MAGIC 0x82
3990
3991static const struct vpd_tag {
3992 char tag[2];
3993 char *label;
3994} vpd_tags[] = {
3995 { "PN", "Part Number" },
3996 { "EC", "Engineering Level" },
3997 { "MN", "Manufacturer" },
3998 { "SN", "Serial Number" },
3999 { "YA", "Asset Tag" },
4000 { "VL", "First Error Log Message" },
4001 { "VF", "Second Error Log Message" },
4002 { "VB", "Boot Agent ROM Configuration" },
4003 { "VE", "EFI UNDI Configuration" },
4004};
4005
4006static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4007{
4008 size_t vpd_size;
4009 loff_t offs;
4010 u8 len;
4011 unsigned char *buf;
4012 u16 reg2;
4013
4014 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4015 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4016
4017 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4018 buf = kmalloc(vpd_size, GFP_KERNEL);
4019 if (!buf) {
4020 seq_puts(seq, "no memory!\n");
4021 return;
4022 }
4023
4024 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4025 seq_puts(seq, "VPD read failed\n");
4026 goto out;
4027 }
4028
4029 if (buf[0] != VPD_MAGIC) {
4030 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4031 goto out;
4032 }
4033 len = buf[1];
4034 if (len == 0 || len > vpd_size - 4) {
4035 seq_printf(seq, "Invalid id length: %d\n", len);
4036 goto out;
4037 }
4038
4039 seq_printf(seq, "%.*s\n", len, buf + 3);
4040 offs = len + 3;
4041
4042 while (offs < vpd_size - 4) {
4043 int i;
4044
4045 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4046 break;
4047 len = buf[offs + 2];
4048 if (offs + len + 3 >= vpd_size)
4049 break;
4050
4051 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4052 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4053 seq_printf(seq, " %s: %.*s\n",
4054 vpd_tags[i].label, len, buf + offs + 3);
4055 break;
4056 }
4057 }
4058 offs += len + 3;
4059 }
4060out:
4061 kfree(buf);
4062}
4063
3cf26753
SH
4064static int sky2_debug_show(struct seq_file *seq, void *v)
4065{
4066 struct net_device *dev = seq->private;
4067 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4068 struct sky2_hw *hw = sky2->hw;
3cf26753
SH
4069 unsigned port = sky2->port;
4070 unsigned idx, last;
4071 int sop;
4072
e4c2abe2 4073 sky2_show_vpd(seq, hw);
3cf26753 4074
e4c2abe2 4075 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH
4076 sky2_read32(hw, B0_ISRC),
4077 sky2_read32(hw, B0_IMSK),
4078 sky2_read32(hw, B0_Y2_SP_ICR));
4079
e4c2abe2
SH
4080 if (!netif_running(dev)) {
4081 seq_printf(seq, "network not running\n");
4082 return 0;
4083 }
4084
bea3348e 4085 napi_disable(&hw->napi);
3cf26753
SH
4086 last = sky2_read16(hw, STAT_PUT_IDX);
4087
4088 if (hw->st_idx == last)
4089 seq_puts(seq, "Status ring (empty)\n");
4090 else {
4091 seq_puts(seq, "Status ring\n");
4092 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4093 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4094 const struct sky2_status_le *le = hw->st_le + idx;
4095 seq_printf(seq, "[%d] %#x %d %#x\n",
4096 idx, le->opcode, le->length, le->status);
4097 }
4098 seq_puts(seq, "\n");
4099 }
4100
4101 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4102 sky2->tx_cons, sky2->tx_prod,
4103 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4104 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4105
4106 /* Dump contents of tx ring */
4107 sop = 1;
4108 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4109 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4110 const struct sky2_tx_le *le = sky2->tx_le + idx;
4111 u32 a = le32_to_cpu(le->addr);
4112
4113 if (sop)
4114 seq_printf(seq, "%u:", idx);
4115 sop = 0;
4116
4117 switch(le->opcode & ~HW_OWNER) {
4118 case OP_ADDR64:
4119 seq_printf(seq, " %#x:", a);
4120 break;
4121 case OP_LRGLEN:
4122 seq_printf(seq, " mtu=%d", a);
4123 break;
4124 case OP_VLAN:
4125 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4126 break;
4127 case OP_TCPLISW:
4128 seq_printf(seq, " csum=%#x", a);
4129 break;
4130 case OP_LARGESEND:
4131 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4132 break;
4133 case OP_PACKET:
4134 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4135 break;
4136 case OP_BUFFER:
4137 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4138 break;
4139 default:
4140 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4141 a, le16_to_cpu(le->length));
4142 }
4143
4144 if (le->ctrl & EOP) {
4145 seq_putc(seq, '\n');
4146 sop = 1;
4147 }
4148 }
4149
4150 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4151 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4152 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH
4153 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4154
d1d08d12 4155 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4156 napi_enable(&hw->napi);
3cf26753
SH
4157 return 0;
4158}
4159
4160static int sky2_debug_open(struct inode *inode, struct file *file)
4161{
4162 return single_open(file, sky2_debug_show, inode->i_private);
4163}
4164
4165static const struct file_operations sky2_debug_fops = {
4166 .owner = THIS_MODULE,
4167 .open = sky2_debug_open,
4168 .read = seq_read,
4169 .llseek = seq_lseek,
4170 .release = single_release,
4171};
4172
4173/*
4174 * Use network device events to create/remove/rename
4175 * debugfs file entries
4176 */
4177static int sky2_device_event(struct notifier_block *unused,
4178 unsigned long event, void *ptr)
4179{
4180 struct net_device *dev = ptr;
5b296bc9 4181 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4182
1436b301 4183 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4184 return NOTIFY_DONE;
3cf26753 4185
5b296bc9
SH
4186 switch(event) {
4187 case NETDEV_CHANGENAME:
4188 if (sky2->debugfs) {
4189 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4190 sky2_debug, dev->name);
4191 }
4192 break;
3cf26753 4193
5b296bc9
SH
4194 case NETDEV_GOING_DOWN:
4195 if (sky2->debugfs) {
4196 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4197 dev->name);
4198 debugfs_remove(sky2->debugfs);
4199 sky2->debugfs = NULL;
3cf26753 4200 }
5b296bc9
SH
4201 break;
4202
4203 case NETDEV_UP:
4204 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4205 sky2_debug, dev,
4206 &sky2_debug_fops);
4207 if (IS_ERR(sky2->debugfs))
4208 sky2->debugfs = NULL;
3cf26753
SH
4209 }
4210
4211 return NOTIFY_DONE;
4212}
4213
4214static struct notifier_block sky2_notifier = {
4215 .notifier_call = sky2_device_event,
4216};
4217
4218
4219static __init void sky2_debug_init(void)
4220{
4221 struct dentry *ent;
4222
4223 ent = debugfs_create_dir("sky2", NULL);
4224 if (!ent || IS_ERR(ent))
4225 return;
4226
4227 sky2_debug = ent;
4228 register_netdevice_notifier(&sky2_notifier);
4229}
4230
4231static __exit void sky2_debug_cleanup(void)
4232{
4233 if (sky2_debug) {
4234 unregister_netdevice_notifier(&sky2_notifier);
4235 debugfs_remove(sky2_debug);
4236 sky2_debug = NULL;
4237 }
4238}
4239
4240#else
4241#define sky2_debug_init()
4242#define sky2_debug_cleanup()
4243#endif
4244
1436b301
SH
4245/* Two copies of network device operations to handle special case of
4246 not allowing netpoll on second port */
4247static const struct net_device_ops sky2_netdev_ops[2] = {
4248 {
4249 .ndo_open = sky2_up,
4250 .ndo_stop = sky2_down,
00829823 4251 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH
4252 .ndo_do_ioctl = sky2_ioctl,
4253 .ndo_validate_addr = eth_validate_addr,
4254 .ndo_set_mac_address = sky2_set_mac_address,
4255 .ndo_set_multicast_list = sky2_set_multicast,
4256 .ndo_change_mtu = sky2_change_mtu,
4257 .ndo_tx_timeout = sky2_tx_timeout,
4258#ifdef SKY2_VLAN_TAG_USED
4259 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4260#endif
4261#ifdef CONFIG_NET_POLL_CONTROLLER
4262 .ndo_poll_controller = sky2_netpoll,
4263#endif
4264 },
4265 {
4266 .ndo_open = sky2_up,
4267 .ndo_stop = sky2_down,
00829823 4268 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH
4269 .ndo_do_ioctl = sky2_ioctl,
4270 .ndo_validate_addr = eth_validate_addr,
4271 .ndo_set_mac_address = sky2_set_mac_address,
4272 .ndo_set_multicast_list = sky2_set_multicast,
4273 .ndo_change_mtu = sky2_change_mtu,
4274 .ndo_tx_timeout = sky2_tx_timeout,
4275#ifdef SKY2_VLAN_TAG_USED
4276 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4277#endif
4278 },
4279};
3cf26753 4280
cd28ab6a
SH
4281/* Initialize network device */
4282static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4283 unsigned port,
be63a21c 4284 int highmem, int wol)
cd28ab6a
SH
4285{
4286 struct sky2_port *sky2;
4287 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4288
4289 if (!dev) {
898eb71c 4290 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH
4291 return NULL;
4292 }
4293
cd28ab6a 4294 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4295 dev->irq = hw->pdev->irq;
cd28ab6a 4296 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4297 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4298 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH
4299
4300 sky2 = netdev_priv(dev);
4301 sky2->netdev = dev;
4302 sky2->hw = hw;
4303 sky2->msg_enable = netif_msg_init(debug, default_msg);
4304
cd28ab6a 4305 /* Auto speed and flow control */
0ea065e5
SH
4306 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4307 if (hw->chip_id != CHIP_ID_YUKON_XL)
4308 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4309
16ad91e1
SH
4310 sky2->flow_mode = FC_BOTH;
4311
cd28ab6a
SH
4312 sky2->duplex = -1;
4313 sky2->speed = -1;
4314 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4315 sky2->wol = wol;
75d070c5 4316
e07b1aa8 4317 spin_lock_init(&sky2->phy_lock);
793b883e 4318 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4319 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH
4320
4321 hw->dev[port] = dev;
4322
4323 sky2->port = port;
4324
4a50a876 4325 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH
4326 if (highmem)
4327 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4328
d1f13708 4329#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH
4330 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4331 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4332 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4333 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4334 }
d1f13708 4335#endif
4336
cd28ab6a 4337 /* read the mac address */
793b883e 4338 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4339 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4340
cd28ab6a
SH
4341 return dev;
4342}
4343
28bd181a 4344static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH
4345{
4346 const struct sky2_port *sky2 = netdev_priv(dev);
4347
4348 if (netif_msg_probe(sky2))
e174961c
JB
4349 printk(KERN_INFO PFX "%s: addr %pM\n",
4350 dev->name, dev->dev_addr);
cd28ab6a
SH
4351}
4352
fb2690a9 4353/* Handle software interrupt used during MSI test */
7d12e780 4354static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH
4355{
4356 struct sky2_hw *hw = dev_id;
4357 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4358
4359 if (status == 0)
4360 return IRQ_NONE;
4361
4362 if (status & Y2_IS_IRQ_SW) {
ea76e635 4363 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH
4364 wake_up(&hw->msi_wait);
4365 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4366 }
4367 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4368
4369 return IRQ_HANDLED;
4370}
4371
4372/* Test interrupt path by forcing a a software IRQ */
4373static int __devinit sky2_test_msi(struct sky2_hw *hw)
4374{
4375 struct pci_dev *pdev = hw->pdev;
4376 int err;
4377
bb507fe1 4378 init_waitqueue_head (&hw->msi_wait);
4379
fb2690a9
SH
4380 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4381
b0a20ded 4382 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4383 if (err) {
b02a9258 4384 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH
4385 return err;
4386 }
4387
fb2690a9 4388 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4389 sky2_read8(hw, B0_CTST);
fb2690a9 4390
ea76e635 4391 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4392
ea76e635 4393 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4394 /* MSI test failed, go back to INTx mode */
b02a9258
SH
4395 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4396 "switching to INTx mode.\n");
fb2690a9
SH
4397
4398 err = -EOPNOTSUPP;
4399 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4400 }
4401
4402 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4403 sky2_read32(hw, B0_IMSK);
fb2690a9
SH
4404
4405 free_irq(pdev->irq, hw);
4406
4407 return err;
4408}
4409
c7127a34
SH
4410/* This driver supports yukon2 chipset only */
4411static const char *sky2_name(u8 chipid, char *buf, int sz)
4412{
4413 const char *name[] = {
4414 "XL", /* 0xb3 */
4415 "EC Ultra", /* 0xb4 */
4416 "Extreme", /* 0xb5 */
4417 "EC", /* 0xb6 */
4418 "FE", /* 0xb7 */
4419 "FE+", /* 0xb8 */
4420 "Supreme", /* 0xb9 */
0ce8b98d 4421 "UL 2", /* 0xba */
c7127a34
SH
4422 };
4423
0ce8b98d 4424 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH
4425 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4426 else
4427 snprintf(buf, sz, "(chip %#x)", chipid);
4428 return buf;
4429}
4430
cd28ab6a
SH
4431static int __devinit sky2_probe(struct pci_dev *pdev,
4432 const struct pci_device_id *ent)
4433{
7f60c64b 4434 struct net_device *dev;
cd28ab6a 4435 struct sky2_hw *hw;
be63a21c 4436 int err, using_dac = 0, wol_default;
3834507d 4437 u32 reg;
c7127a34 4438 char buf1[16];
cd28ab6a 4439
793b883e
SH
4440 err = pci_enable_device(pdev);
4441 if (err) {
b02a9258 4442 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH
4443 goto err_out;
4444 }
4445
6cc90a5a
SH
4446 /* Get configuration information
4447 * Note: only regular PCI config access once to test for HW issues
4448 * other PCI access through shared memory for speed and to
4449 * avoid MMCONFIG problems.
4450 */
4451 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4452 if (err) {
4453 dev_err(&pdev->dev, "PCI read config failed\n");
4454 goto err_out;
4455 }
4456
4457 if (~reg == 0) {
4458 dev_err(&pdev->dev, "PCI configuration read error\n");
4459 goto err_out;
4460 }
4461
793b883e
SH
4462 err = pci_request_regions(pdev, DRV_NAME);
4463 if (err) {
b02a9258 4464 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4465 goto err_out_disable;
cd28ab6a
SH
4466 }
4467
4468 pci_set_master(pdev);
4469
d1f3d4dd 4470 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4471 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4472 using_dac = 1;
6a35528a 4473 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4474 if (err < 0) {
b02a9258
SH
4475 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4476 "for consistent allocations\n");
d1f3d4dd
SH
4477 goto err_out_free_regions;
4478 }
d1f3d4dd 4479 } else {
284901a9 4480 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4481 if (err) {
b02a9258 4482 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH
4483 goto err_out_free_regions;
4484 }
4485 }
d1f3d4dd 4486
3834507d
SH
4487
4488#ifdef __BIG_ENDIAN
4489 /* The sk98lin vendor driver uses hardware byte swapping but
4490 * this driver uses software swapping.
4491 */
4492 reg &= ~PCI_REV_DESC;
4493 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4494 if (err) {
4495 dev_err(&pdev->dev, "PCI write config failed\n");
4496 goto err_out_free_regions;
4497 }
4498#endif
4499
9d731d77 4500 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4501
cd28ab6a 4502 err = -ENOMEM;
6aad85d6 4503 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4504 if (!hw) {
b02a9258 4505 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH
4506 goto err_out_free_regions;
4507 }
4508
cd28ab6a 4509 hw->pdev = pdev;
cd28ab6a
SH
4510
4511 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4512 if (!hw->regs) {
b02a9258 4513 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH
4514 goto err_out_free_hw;
4515 }
4516
08c06d8a 4517 /* ring for status responses */
167f53d0 4518 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH
4519 if (!hw->st_le)
4520 goto err_out_iounmap;
4521
e3173832 4522 err = sky2_init(hw);
cd28ab6a 4523 if (err)
793b883e 4524 goto err_out_iounmap;
cd28ab6a 4525
c844d483
SH
4526 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4527 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4528
e3173832
SH
4529 sky2_reset(hw);
4530
be63a21c 4531 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4532 if (!dev) {
4533 err = -ENOMEM;
cd28ab6a 4534 goto err_out_free_pci;
7f60c64b 4535 }
cd28ab6a 4536
9fa1b1f3
SH
4537 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4538 err = sky2_test_msi(hw);
4539 if (err == -EOPNOTSUPP)
4540 pci_disable_msi(pdev);
4541 else if (err)
4542 goto err_out_free_netdev;
4543 }
4544
793b883e
SH
4545 err = register_netdev(dev);
4546 if (err) {
b02a9258 4547 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH
4548 goto err_out_free_netdev;
4549 }
4550
6de16237
SH
4551 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4552
ea76e635
SH
4553 err = request_irq(pdev->irq, sky2_intr,
4554 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4555 dev->name, hw);
9fa1b1f3 4556 if (err) {
b02a9258 4557 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH
4558 goto err_out_unregister;
4559 }
4560 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4561 napi_enable(&hw->napi);
9fa1b1f3 4562
cd28ab6a
SH
4563 sky2_show_addr(dev);
4564
7f60c64b 4565 if (hw->ports > 1) {
4566 struct net_device *dev1;
4567
be63a21c 4568 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH
4569 if (!dev1)
4570 dev_warn(&pdev->dev, "allocation for second device failed\n");
4571 else if ((err = register_netdev(dev1))) {
4572 dev_warn(&pdev->dev,
4573 "register of second port failed (%d)\n", err);
cd28ab6a
SH
4574 hw->dev[1] = NULL;
4575 free_netdev(dev1);
b02a9258
SH
4576 } else
4577 sky2_show_addr(dev1);
cd28ab6a
SH
4578 }
4579
32c2c300 4580 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH
4581 INIT_WORK(&hw->restart_work, sky2_restart);
4582
793b883e
SH
4583 pci_set_drvdata(pdev, hw);
4584
cd28ab6a
SH
4585 return 0;
4586
793b883e 4587err_out_unregister:
ea76e635 4588 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4589 pci_disable_msi(pdev);
793b883e 4590 unregister_netdev(dev);
cd28ab6a
SH
4591err_out_free_netdev:
4592 free_netdev(dev);
cd28ab6a 4593err_out_free_pci:
793b883e 4594 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4595 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH
4596err_out_iounmap:
4597 iounmap(hw->regs);
4598err_out_free_hw:
4599 kfree(hw);
4600err_out_free_regions:
4601 pci_release_regions(pdev);
44a1d2e5 4602err_out_disable:
cd28ab6a 4603 pci_disable_device(pdev);
cd28ab6a 4604err_out:
549a68c3 4605 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH
4606 return err;
4607}
4608
4609static void __devexit sky2_remove(struct pci_dev *pdev)
4610{
793b883e 4611 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4612 int i;
cd28ab6a 4613
793b883e 4614 if (!hw)
cd28ab6a
SH
4615 return;
4616
32c2c300 4617 del_timer_sync(&hw->watchdog_timer);
6de16237 4618 cancel_work_sync(&hw->restart_work);
d27ed387 4619
b877fe28 4620 for (i = hw->ports-1; i >= 0; --i)
6de16237 4621 unregister_netdev(hw->dev[i]);
81906791 4622
d27ed387 4623 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4624
ae306cca
SH
4625 sky2_power_aux(hw);
4626
cd28ab6a 4627 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4628 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4629 sky2_read8(hw, B0_CTST);
cd28ab6a
SH
4630
4631 free_irq(pdev->irq, hw);
ea76e635 4632 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4633 pci_disable_msi(pdev);
793b883e 4634 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH
4635 pci_release_regions(pdev);
4636 pci_disable_device(pdev);
793b883e 4637
b877fe28 4638 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH
4639 free_netdev(hw->dev[i]);
4640
cd28ab6a
SH
4641 iounmap(hw->regs);
4642 kfree(hw);
5afa0a9c 4643
cd28ab6a
SH
4644 pci_set_drvdata(pdev, NULL);
4645}
4646
4647#ifdef CONFIG_PM
4648static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4649{
793b883e 4650 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4651 int i, wol = 0;
cd28ab6a 4652
549a68c3
SH
4653 if (!hw)
4654 return 0;
4655
063a0b38
SH
4656 del_timer_sync(&hw->watchdog_timer);
4657 cancel_work_sync(&hw->restart_work);
4658
19720737 4659 rtnl_lock();
f05267e7 4660 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4661 struct net_device *dev = hw->dev[i];
e3173832 4662 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4663
af18d8b8 4664 sky2_detach(dev);
e3173832
SH
4665
4666 if (sky2->wol)
4667 sky2_wol_init(sky2);
4668
4669 wol |= sky2->wol;
cd28ab6a
SH
4670 }
4671
8ab8fca2 4672 sky2_write32(hw, B0_IMSK, 0);
6de16237 4673 napi_disable(&hw->napi);
ae306cca 4674 sky2_power_aux(hw);
19720737 4675 rtnl_unlock();
e3173832 4676
d374c1c1 4677 pci_save_state(pdev);
e3173832 4678 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4679 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4680
2ccc99b7 4681 return 0;
cd28ab6a
SH
4682}
4683
4684static int sky2_resume(struct pci_dev *pdev)
4685{
793b883e 4686 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4687 int i, err;
cd28ab6a 4688
549a68c3
SH
4689 if (!hw)
4690 return 0;
4691
f71eb1a2
SH
4692 err = pci_set_power_state(pdev, PCI_D0);
4693 if (err)
4694 goto out;
ae306cca
SH
4695
4696 err = pci_restore_state(pdev);
4697 if (err)
4698 goto out;
4699
cd28ab6a 4700 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH
4701
4702 /* Re-enable all clocks */
05745c4a
SH
4703 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4704 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4705 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4706 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4707
e3173832 4708 sky2_reset(hw);
8ab8fca2 4709 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4710 napi_enable(&hw->napi);
8ab8fca2 4711
af18d8b8 4712 rtnl_lock();
f05267e7 4713 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH
4714 err = sky2_reattach(hw->dev[i]);
4715 if (err)
4716 goto out;
cd28ab6a 4717 }
af18d8b8 4718 rtnl_unlock();
eb35cf60 4719
ae306cca 4720 return 0;
08c06d8a 4721out:
af18d8b8
SH
4722 rtnl_unlock();
4723
b02a9258 4724 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4725 pci_disable_device(pdev);
08c06d8a 4726 return err;
cd28ab6a
SH
4727}
4728#endif
4729
e3173832
SH
4730static void sky2_shutdown(struct pci_dev *pdev)
4731{
4732 struct sky2_hw *hw = pci_get_drvdata(pdev);
4733 int i, wol = 0;
4734
549a68c3
SH
4735 if (!hw)
4736 return;
4737
19720737 4738 rtnl_lock();
5c0d6b34 4739 del_timer_sync(&hw->watchdog_timer);
e3173832
SH
4740
4741 for (i = 0; i < hw->ports; i++) {
4742 struct net_device *dev = hw->dev[i];
4743 struct sky2_port *sky2 = netdev_priv(dev);
4744
4745 if (sky2->wol) {
4746 wol = 1;
4747 sky2_wol_init(sky2);
4748 }
4749 }
4750
4751 if (wol)
4752 sky2_power_aux(hw);
19720737 4753 rtnl_unlock();
e3173832
SH
4754
4755 pci_enable_wake(pdev, PCI_D3hot, wol);
4756 pci_enable_wake(pdev, PCI_D3cold, wol);
4757
4758 pci_disable_device(pdev);
f71eb1a2 4759 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH
4760}
4761
cd28ab6a 4762static struct pci_driver sky2_driver = {
793b883e
SH
4763 .name = DRV_NAME,
4764 .id_table = sky2_id_table,
4765 .probe = sky2_probe,
4766 .remove = __devexit_p(sky2_remove),
cd28ab6a 4767#ifdef CONFIG_PM
793b883e
SH
4768 .suspend = sky2_suspend,
4769 .resume = sky2_resume,
cd28ab6a 4770#endif
e3173832 4771 .shutdown = sky2_shutdown,
cd28ab6a
SH
4772};
4773
4774static int __init sky2_init_module(void)
4775{
c844d483
SH
4776 pr_info(PFX "driver version " DRV_VERSION "\n");
4777
3cf26753 4778 sky2_debug_init();
50241c4c 4779 return pci_register_driver(&sky2_driver);
cd28ab6a
SH
4780}
4781
4782static void __exit sky2_cleanup_module(void)
4783{
4784 pci_unregister_driver(&sky2_driver);
3cf26753 4785 sky2_debug_cleanup();
cd28ab6a
SH
4786}
4787
4788module_init(sky2_init_module);
4789module_exit(sky2_cleanup_module);
4790
4791MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4792MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4793MODULE_LICENSE("GPL");
5f4f9dc1 4794MODULE_VERSION(DRV_VERSION);