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sky2: revert to access PCI config via device space
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
555382cb 34#include <linux/aer.h>
cd28ab6a 35#include <linux/ip.h>
c9bdd4b5 36#include <net/ip.h>
cd28ab6a
SH		 37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
3cf26753 43#include <linux/debugfs.h>
ef743d33 44#include <linux/mii.h>
cd28ab6a
SH		 45
46#include <asm/irq.h>
47
d1f13708 48#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49#define SKY2_VLAN_TAG_USED 1
50#endif
51
cd28ab6a
SH		 52#include "sky2.h"
53
54#define DRV_NAME "sky2"
1e354787 55#define DRV_VERSION "1.20"
cd28ab6a
SH		 56#define PFX DRV_NAME " "
57
58/*
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
14d0263f 61 * similar to Tigon3.
cd28ab6a
SH		 62 */
63
14d0263f 64#define RX_LE_SIZE 1024
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 66#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 68#define RX_SKB_ALIGN 8
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 77#define TX_WATCHDOG (5 * HZ)
78#define NAPI_WEIGHT 64
79#define PHY_RETRIES 1000
80
f4331a6d
SH		 81#define SKY2_EEPROM_MAGIC 0x9955aabb
82
83
cb5d9547
SH		 84#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85
cd28ab6a 86static const u32 default_msg =
793b883e
SH		 87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 90
793b883e 91static int debug = -1; /* defaults above */
cd28ab6a
SH		 92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
14d0263f 95static int copybreak __read_mostly = 128;
bdb5c58e
SH		 96module_param(copybreak, int, 0);
97MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98
fb2690a9
SH		 99static int disable_msi = 0;
100module_param(disable_msi, int, 0);
101MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
cd28ab6a
SH		 139 { 0 }
140};
793b883e 141
cd28ab6a
SH		 142MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144/* Avoid conditionals by using array */
145static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 147static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 148
92f965e8
SH		 149/* This driver supports yukon2 chipset only */
150static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
93745494 153 "Extreme", /* 0xb5 */
92f965e8
SH		 154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
05745c4a 156 "FE+", /* 0xb8 */
793b883e
SH		 157};
158
d1b139c0
SH		 159static void sky2_set_multicast(struct net_device *dev);
160
af043aa5 161/* Access to PHY via serial interconnect */
ef743d33 162static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 163{
164 int i;
165
166 gma_write16(hw, port, GM_SMI_DATA, val);
167 gma_write16(hw, port, GM_SMI_CTRL,
168 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
169
170 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 171 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
172 if (ctrl == 0xffff)
173 goto io_error;
174
175 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 176 return 0;
af043aa5
SH		 177
178 udelay(10);
cd28ab6a 179 }
ef743d33 180
af043aa5 181 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 182 return -ETIMEDOUT;
af043aa5
SH		 183
184io_error:
185 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
186 return -EIO;
cd28ab6a
SH		 187}
188
ef743d33 189static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 190{
191 int i;
192
793b883e 193 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 194 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
195
196 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 197 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
198 if (ctrl == 0xffff)
199 goto io_error;
200
201 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 202 *val = gma_read16(hw, port, GM_SMI_DATA);
203 return 0;
204 }
205
af043aa5 206 udelay(10);
cd28ab6a
SH		 207 }
208
af043aa5 209 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 210 return -ETIMEDOUT;
af043aa5
SH		 211io_error:
212 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
213 return -EIO;
ef743d33 214}
215
af043aa5 216static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 217{
218 u16 v;
af043aa5 219 __gm_phy_read(hw, port, reg, &v);
ef743d33 220 return v;
cd28ab6a
SH		 221}
222
5afa0a9c 223
ae306cca
SH		 224static void sky2_power_on(struct sky2_hw *hw)
225{
226 /* switch power to VCC (WA for VAUX problem) */
227 sky2_write8(hw, B0_POWER_CTRL,
228 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 229
ae306cca
SH		 230 /* disable Core Clock Division, */
231 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 232
ae306cca
SH		 233 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239 else
240 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 241
ea76e635 242 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 243 u32 reg;
5afa0a9c 244
b32f40c4 245 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 246
b32f40c4 247 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 248 /* set all bits to 0 except bits 15..12 and 8 */
249 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 250 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 251
b32f40c4 252 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 253 /* set all bits to 0 except bits 28 & 27 */
254 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 255 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 256
b32f40c4 257 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 258
259 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
260 reg = sky2_read32(hw, B2_GP_IO);
261 reg |= GLB_GPIO_STAT_RACE_DIS;
262 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 263
264 sky2_read32(hw, B2_GP_IO);
5afa0a9c 265 }
ae306cca 266}
5afa0a9c 267
ae306cca
SH		 268static void sky2_power_aux(struct sky2_hw *hw)
269{
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
272 else
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
278
279 /* switch power to VAUX */
280 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
281 sky2_write8(hw, B0_POWER_CTRL,
282 (PC_VAUX_ENA | PC_VCC_ENA |
283 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 284}
285
d3bcfbeb 286static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 287{
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 292
cd28ab6a
SH		 293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301}
302
16ad91e1
SH		 303/* flow control to advertise bits */
304static const u16 copper_fc_adv[] = {
305 [FC_NONE] = 0,
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
309};
310
311/* flow control to advertise bits when using 1000BaseX */
312static const u16 fiber_fc_adv[] = {
df3fe1f3 313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 317};
318
319/* flow control to GMA disable bits */
320static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
324 [FC_BOTH] = 0,
325};
326
327
cd28ab6a
SH		 328static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
329{
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 332
ea76e635
SH		 333 if (sky2->autoneg == AUTONEG_ENABLE &&
334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
336
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 338 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
340
53419c68 341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 342 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 343 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
345 else
53419c68
SH		 346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 348
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 353 if (sky2_is_copper(hw)) {
05745c4a 354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 357
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
360 u16 spec;
361
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
366 }
cd28ab6a
SH		 367 } else {
368 /* disable energy detect */
369 ctrl &= ~PHY_M_PC_EN_DET_MSK;
370
371 /* enable automatic crossover */
372 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
373
53419c68 374 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 375 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 376 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 377 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 378 ctrl &= ~PHY_M_PC_DSC_MSK;
379 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
380 }
381 }
cd28ab6a
SH		 382 } else {
383 /* workaround for deviation #4.88 (CRC errors) */
384 /* disable Automatic Crossover */
385
386 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 387 }
cd28ab6a 388
b89165f2
SH		 389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
390
391 /* special setup for PHY 88E1112 Fiber */
ea76e635 392 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 393 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 394
b89165f2
SH		 395 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
397 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
398 ctrl &= ~PHY_M_MAC_MD_MSK;
399 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401
402 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 403 /* select page 1 to access Fiber registers */
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 405
406 /* for SFP-module set SIGDET polarity to low */
407 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
408 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 410 }
b89165f2
SH		 411
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 413 }
414
7800fddc 415 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 416 ct1000 = 0;
417 adv = PHY_AN_CSMA;
2eaba1a2 418 reg = 0;
cd28ab6a
SH		 419
420 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 421 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 422 if (sky2->advertising & ADVERTISED_1000baseT_Full)
423 ct1000 |= PHY_M_1000C_AFD;
424 if (sky2->advertising & ADVERTISED_1000baseT_Half)
425 ct1000 |= PHY_M_1000C_AHD;
426 if (sky2->advertising & ADVERTISED_100baseT_Full)
427 adv |= PHY_M_AN_100_FD;
428 if (sky2->advertising & ADVERTISED_100baseT_Half)
429 adv |= PHY_M_AN_100_HD;
430 if (sky2->advertising & ADVERTISED_10baseT_Full)
431 adv |= PHY_M_AN_10_FD;
432 if (sky2->advertising & ADVERTISED_10baseT_Half)
433 adv |= PHY_M_AN_10_HD;
709c6e7b 434
16ad91e1 435 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 436 } else { /* special defines for FIBER (88E1040S only) */
437 if (sky2->advertising & ADVERTISED_1000baseT_Full)
438 adv |= PHY_M_AN_1000X_AFD;
439 if (sky2->advertising & ADVERTISED_1000baseT_Half)
440 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 441
16ad91e1 442 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 443 }
cd28ab6a
SH		 444
445 /* Restart Auto-negotiation */
446 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 } else {
448 /* forced speed/duplex settings */
449 ct1000 = PHY_M_1000C_MSE;
450
2eaba1a2
SH		 451 /* Disable auto update for duplex flow control and speed */
452 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 453
454 switch (sky2->speed) {
455 case SPEED_1000:
456 ctrl |= PHY_CT_SP1000;
2eaba1a2 457 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 458 break;
459 case SPEED_100:
460 ctrl |= PHY_CT_SP100;
2eaba1a2 461 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 462 break;
463 }
464
2eaba1a2
SH		 465 if (sky2->duplex == DUPLEX_FULL) {
466 reg |= GM_GPCR_DUP_FULL;
467 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 468 } else if (sky2->speed < SPEED_1000)
469 sky2->flow_mode = FC_NONE;
2eaba1a2 470
2eaba1a2 471
16ad91e1 472 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 473
474 /* Forward pause packets to GMAC? */
16ad91e1 475 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 476 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
477 else
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 479 }
480
2eaba1a2
SH		 481 gma_write16(hw, port, GM_GP_CTRL, reg);
482
05745c4a 483 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 484 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
485
486 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
487 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
488
489 /* Setup Phy LED's */
490 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
491 ledover = 0;
492
493 switch (hw->chip_id) {
494 case CHIP_ID_YUKON_FE:
495 /* on 88E3082 these bits are at 11..9 (shifted left) */
496 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
497
498 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
499
500 /* delete ACT LED control bits */
501 ctrl &= ~PHY_M_FELP_LED1_MSK;
502 /* change ACT LED control to blink mode */
503 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
504 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
505 break;
506
05745c4a
SH		 507 case CHIP_ID_YUKON_FE_P:
508 /* Enable Link Partner Next Page */
509 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
510 ctrl |= PHY_M_PC_ENA_LIP_NP;
511
512 /* disable Energy Detect and enable scrambler */
513 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
514 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
515
516 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
517 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
518 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
519 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
520
521 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
522 break;
523
cd28ab6a 524 case CHIP_ID_YUKON_XL:
793b883e 525 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 526
527 /* select page 3 to access LED control register */
528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
529
530 /* set LED Function Control register */
ed6d32c7
SH		 531 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
532 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
533 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
534 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
535 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 536
537 /* set Polarity Control register */
538 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 539 (PHY_M_POLC_LS1_P_MIX(4) |
540 PHY_M_POLC_IS0_P_MIX(4) |
541 PHY_M_POLC_LOS_CTRL(2) |
542 PHY_M_POLC_INIT_CTRL(2) |
543 PHY_M_POLC_STA1_CTRL(2) |
544 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 545
546 /* restore page register */
793b883e 547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 548 break;
93745494 549
ed6d32c7 550 case CHIP_ID_YUKON_EC_U:
93745494 551 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 552 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
553
554 /* select page 3 to access LED control register */
555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
556
557 /* set LED Function Control register */
558 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
559 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
560 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
561 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
562 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
563
564 /* set Blink Rate in LED Timer Control Register */
565 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
566 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
567 /* restore page register */
568 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
569 break;
cd28ab6a
SH		 570
571 default:
572 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
573 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
574 /* turn off the Rx LED (LED_RX) */
0efdf262 575 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 576 }
577
9467a8fc
SH		 578 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
579 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 580 /* apply fixes in PHY AFE */
ed6d32c7
SH		 581 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
582
977bdf06 583 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 584 gm_phy_write(hw, port, 0x18, 0xaa99);
585 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 586
977bdf06 587 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 588 gm_phy_write(hw, port, 0x18, 0xa204);
589 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 590
591 /* set page register to 0 */
9467a8fc 592 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 593 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
594 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
595 /* apply workaround for integrated resistors calibration */
596 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
597 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 598 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 599 /* no effect on Yukon-XL */
977bdf06 600 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 601
977bdf06
SH		 602 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
603 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 604 ledover |= PHY_M_LED_MO_100;
977bdf06 605 }
cd28ab6a 606
977bdf06
SH		 607 if (ledover)
608 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
609
610 }
2eaba1a2 611
d571b694 612 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 613 if (sky2->autoneg == AUTONEG_ENABLE)
614 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
615 else
616 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
617}
618
d3bcfbeb 619static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
620{
621 u32 reg1;
ff35164e
SH		 622 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
623 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
d3bcfbeb 624
b32f40c4 625 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
ff35164e 626 /* Turn on/off phy power saving */
d3bcfbeb 627 if (onoff)
d3bcfbeb 628 reg1 &= ~phy_power[port];
629 else
630 reg1 |= phy_power[port];
631
ff35164e
SH		 632 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
633 reg1 |= coma_mode[port];
634
b32f40c4
SH		 635 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
636 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
167f53d0 637
d3bcfbeb 638 udelay(100);
639}
640
1b537565
SH		 641/* Force a renegotiation */
642static void sky2_phy_reinit(struct sky2_port *sky2)
643{
e07b1aa8 644 spin_lock_bh(&sky2->phy_lock);
1b537565 645 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 646 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 647}
648
e3173832
SH		 649/* Put device in state to listen for Wake On Lan */
650static void sky2_wol_init(struct sky2_port *sky2)
651{
652 struct sky2_hw *hw = sky2->hw;
653 unsigned port = sky2->port;
654 enum flow_control save_mode;
655 u16 ctrl;
656 u32 reg1;
657
658 /* Bring hardware out of reset */
659 sky2_write16(hw, B0_CTST, CS_RST_CLR);
660 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
661
662 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
663 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
664
665 /* Force to 10/100
666 * sky2_reset will re-enable on resume
667 */
668 save_mode = sky2->flow_mode;
669 ctrl = sky2->advertising;
670
671 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
672 sky2->flow_mode = FC_NONE;
673 sky2_phy_power(hw, port, 1);
674 sky2_phy_reinit(sky2);
675
676 sky2->flow_mode = save_mode;
677 sky2->advertising = ctrl;
678
679 /* Set GMAC to no flow control and auto update for speed/duplex */
680 gma_write16(hw, port, GM_GP_CTRL,
681 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
682 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
683
684 /* Set WOL address */
685 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
686 sky2->netdev->dev_addr, ETH_ALEN);
687
688 /* Turn on appropriate WOL control bits */
689 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
690 ctrl = 0;
691 if (sky2->wol & WAKE_PHY)
692 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
693 else
694 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
695
696 if (sky2->wol & WAKE_MAGIC)
697 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
698 else
699 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
700
701 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
702 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
703
704 /* Turn on legacy PCI-Express PME mode */
b32f40c4 705 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 706 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 707 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 708
709 /* block receiver */
710 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
711
712}
713
69161611
SH		 714static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
715{
05745c4a
SH		 716 struct net_device *dev = hw->dev[port];
717
718 if (dev->mtu <= ETH_DATA_LEN)
69161611 719 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
05745c4a
SH		 720 TX_JUMBO_DIS | TX_STFW_ENA);
721
722 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
723 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
724 TX_STFW_ENA | TX_JUMBO_ENA);
725 else {
726 /* set Tx GMAC FIFO Almost Empty Threshold */
727 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
728 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 729
05745c4a
SH		 730 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
731 TX_JUMBO_ENA | TX_STFW_DIS);
69161611 732
05745c4a
SH		 733 /* Can't do offload because of lack of store/forward */
734 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
69161611
SH		 735 }
736}
737
cd28ab6a
SH		 738static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
739{
740 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
741 u16 reg;
25cccecc 742 u32 rx_reg;
cd28ab6a
SH		 743 int i;
744 const u8 *addr = hw->dev[port]->dev_addr;
745
f350339c
SH		 746 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
747 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 748
749 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
750
793b883e 751 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 752 /* WA DEV_472 -- looks like crossed wires on port 2 */
753 /* clear GMAC 1 Control reset */
754 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
755 do {
756 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
757 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
758 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
759 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
760 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
761 }
762
793b883e 763 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 764
2eaba1a2
SH		 765 /* Enable Transmit FIFO Underrun */
766 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
767
e07b1aa8 768 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 769 sky2_phy_init(hw, port);
e07b1aa8 770 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 771
772 /* MIB clear */
773 reg = gma_read16(hw, port, GM_PHY_ADDR);
774 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
775
43f2f104
SH		 776 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
777 gma_read16(hw, port, i);
cd28ab6a
SH		 778 gma_write16(hw, port, GM_PHY_ADDR, reg);
779
780 /* transmit control */
781 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
782
783 /* receive control reg: unicast + multicast + no FCS */
784 gma_write16(hw, port, GM_RX_CTRL,
793b883e 785 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 786
787 /* transmit flow control */
788 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
789
790 /* transmit parameter */
791 gma_write16(hw, port, GM_TX_PARAM,
792 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
793 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
794 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
795 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
796
797 /* serial mode register */
798 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 799 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 800
6b1a3aef 801 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 802 reg |= GM_SMOD_JUMBO_ENA;
803
804 gma_write16(hw, port, GM_SERIAL_MODE, reg);
805
cd28ab6a
SH		 806 /* virtual address for data */
807 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
808
793b883e
SH		 809 /* physical address: used for pause frames */
810 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
811
812 /* ignore counter overflows */
cd28ab6a
SH		 813 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
814 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
815 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
816
817 /* Configure Rx MAC FIFO */
818 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 819 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 820 if (hw->chip_id == CHIP_ID_YUKON_EX ||
821 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 822 rx_reg |= GMF_RX_OVER_ON;
69161611 823
25cccecc 824 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 825
d571b694 826 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 827 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 828
8df9a876 829 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 830 reg = RX_GMF_FL_THR_DEF + 1;
831 /* Another magic mystery workaround from sk98lin */
832 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
833 hw->chip_rev == CHIP_REV_YU_FE2_A0)
834 reg = 0x178;
835 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 836
837 /* Configure Tx MAC FIFO */
838 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
839 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 840
e0c28116
SH		 841 /* On chips without ram buffer, pause is controled by MAC level */
842 if (sky2_read8(hw, B2_E_0) == 0) {
8df9a876 843 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 844 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 845
69161611 846 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 847 }
848
cd28ab6a
SH		 849}
850
67712901
SH		 851/* Assign Ram Buffer allocation to queue */
852static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 853{
67712901
SH		 854 u32 end;
855
856 /* convert from K bytes to qwords used for hw register */
857 start *= 1024/8;
858 space *= 1024/8;
859 end = start + space - 1;
793b883e 860
cd28ab6a
SH		 861 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
862 sky2_write32(hw, RB_ADDR(q, RB_START), start);
863 sky2_write32(hw, RB_ADDR(q, RB_END), end);
864 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
865 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
866
867 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 868 u32 tp = space - space/4;
793b883e 869
1c28f6ba
SH		 870 /* On receive queue's set the thresholds
871 * give receiver priority when > 3/4 full
872 * send pause when down to 2K
873 */
874 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
875 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 876
1c28f6ba
SH		 877 tp = space - 2048/8;
878 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
879 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 880 } else {
881 /* Enable store & forward on Tx queue's because
882 * Tx FIFO is only 1K on Yukon
883 */
884 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
885 }
886
887 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 888 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 889}
890
cd28ab6a 891/* Setup Bus Memory Interface */
af4ed7e6 892static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 893{
894 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
895 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
896 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 897 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 898}
899
cd28ab6a
SH		 900/* Setup prefetch unit registers. This is the interface between
901 * hardware and driver list elements
902 */
8cc048e3 903static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 904 u64 addr, u32 last)
905{
cd28ab6a
SH		 906 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
907 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
908 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
909 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
910 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
911 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 912
913 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 914}
915
793b883e
SH		 916static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
917{
918 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
919
cb5d9547 920 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 921 le->ctrl = 0;
793b883e
SH		 922 return le;
923}
cd28ab6a 924
88f5f0ca
SH		 925static void tx_init(struct sky2_port *sky2)
926{
927 struct sky2_tx_le *le;
928
929 sky2->tx_prod = sky2->tx_cons = 0;
930 sky2->tx_tcpsum = 0;
931 sky2->tx_last_mss = 0;
932
933 le = get_tx_le(sky2);
934 le->addr = 0;
935 le->opcode = OP_ADDR64 | HW_OWNER;
936 sky2->tx_addr64 = 0;
937}
938
291ea614
SH		 939static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
940 struct sky2_tx_le *le)
941{
942 return sky2->tx_ring + (le - sky2->tx_le);
943}
944
290d4de5
SH		 945/* Update chip's next pointer */
946static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 947{
50432cb5 948 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 949 wmb();
50432cb5
SH		 950 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
951
952 /* Synchronize I/O on since next processor may write to tail */
953 mmiowb();
cd28ab6a
SH		 954}
955
793b883e 956
cd28ab6a
SH		 957static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
958{
959 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 960 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 961 le->ctrl = 0;
cd28ab6a
SH		 962 return le;
963}
964
14d0263f
SH		 965/* Build description to hardware for one receive segment */
966static void sky2_rx_add(struct sky2_port *sky2, u8 op,
967 dma_addr_t map, unsigned len)
cd28ab6a
SH		 968{
969 struct sky2_rx_le *le;
36eb0c71 970 u32 hi = upper_32_bits(map);
cd28ab6a 971
793b883e 972 if (sky2->rx_addr64 != hi) {
cd28ab6a 973 le = sky2_next_rx(sky2);
793b883e 974 le->addr = cpu_to_le32(hi);
cd28ab6a 975 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 976 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 977 }
793b883e 978
cd28ab6a 979 le = sky2_next_rx(sky2);
734d1868
SH		 980 le->addr = cpu_to_le32((u32) map);
981 le->length = cpu_to_le16(len);
14d0263f 982 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 983}
984
14d0263f
SH		 985/* Build description to hardware for one possibly fragmented skb */
986static void sky2_rx_submit(struct sky2_port *sky2,
987 const struct rx_ring_info *re)
988{
989 int i;
990
991 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
992
993 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
994 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
995}
996
997
998static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
999 unsigned size)
1000{
1001 struct sk_buff *skb = re->skb;
1002 int i;
1003
1004 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1005 pci_unmap_len_set(re, data_size, size);
1006
1007 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1008 re->frag_addr[i] = pci_map_page(pdev,
1009 skb_shinfo(skb)->frags[i].page,
1010 skb_shinfo(skb)->frags[i].page_offset,
1011 skb_shinfo(skb)->frags[i].size,
1012 PCI_DMA_FROMDEVICE);
1013}
1014
1015static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1016{
1017 struct sk_buff *skb = re->skb;
1018 int i;
1019
1020 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1021 PCI_DMA_FROMDEVICE);
1022
1023 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1024 pci_unmap_page(pdev, re->frag_addr[i],
1025 skb_shinfo(skb)->frags[i].size,
1026 PCI_DMA_FROMDEVICE);
1027}
793b883e 1028
cd28ab6a
SH		 1029/* Tell chip where to start receive checksum.
1030 * Actually has two checksums, but set both same to avoid possible byte
1031 * order problems.
1032 */
793b883e 1033static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1034{
ea76e635 1035 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1036
ea76e635
SH		 1037 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1038 le->ctrl = 0;
1039 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1040
ea76e635
SH		 1041 sky2_write32(sky2->hw,
1042 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1043 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1044}
1045
6b1a3aef 1046/*
1047 * The RX Stop command will not work for Yukon-2 if the BMU does not
1048 * reach the end of packet and since we can't make sure that we have
1049 * incoming data, we must reset the BMU while it is not doing a DMA
1050 * transfer. Since it is possible that the RX path is still active,
1051 * the RX RAM buffer will be stopped first, so any possible incoming
1052 * data will not trigger a DMA. After the RAM buffer is stopped, the
1053 * BMU is polled until any DMA in progress is ended and only then it
1054 * will be reset.
1055 */
1056static void sky2_rx_stop(struct sky2_port *sky2)
1057{
1058 struct sky2_hw *hw = sky2->hw;
1059 unsigned rxq = rxqaddr[sky2->port];
1060 int i;
1061
1062 /* disable the RAM Buffer receive queue */
1063 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1064
1065 for (i = 0; i < 0xffff; i++)
1066 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1067 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1068 goto stopped;
1069
1070 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1071 sky2->netdev->name);
1072stopped:
1073 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1074
1075 /* reset the Rx prefetch unit */
1076 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1077 mmiowb();
6b1a3aef 1078}
793b883e 1079
d571b694 1080/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1081static void sky2_rx_clean(struct sky2_port *sky2)
1082{
1083 unsigned i;
1084
1085 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1086 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1087 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1088
1089 if (re->skb) {
14d0263f 1090 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1091 kfree_skb(re->skb);
1092 re->skb = NULL;
1093 }
1094 }
1095}
1096
ef743d33 1097/* Basic MII support */
1098static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1099{
1100 struct mii_ioctl_data *data = if_mii(ifr);
1101 struct sky2_port *sky2 = netdev_priv(dev);
1102 struct sky2_hw *hw = sky2->hw;
1103 int err = -EOPNOTSUPP;
1104
1105 if (!netif_running(dev))
1106 return -ENODEV; /* Phy still in reset */
1107
d89e1343 1108 switch (cmd) {
ef743d33 1109 case SIOCGMIIPHY:
1110 data->phy_id = PHY_ADDR_MARV;
1111
1112 /* fallthru */
1113 case SIOCGMIIREG: {
1114 u16 val = 0;
91c86df5 1115
e07b1aa8 1116 spin_lock_bh(&sky2->phy_lock);
ef743d33 1117 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1118 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1119
ef743d33 1120 data->val_out = val;
1121 break;
1122 }
1123
1124 case SIOCSMIIREG:
1125 if (!capable(CAP_NET_ADMIN))
1126 return -EPERM;
1127
e07b1aa8 1128 spin_lock_bh(&sky2->phy_lock);
ef743d33 1129 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1130 data->val_in);
e07b1aa8 1131 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1132 break;
1133 }
1134 return err;
1135}
1136
d1f13708 1137#ifdef SKY2_VLAN_TAG_USED
1138static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1139{
1140 struct sky2_port *sky2 = netdev_priv(dev);
1141 struct sky2_hw *hw = sky2->hw;
1142 u16 port = sky2->port;
d1f13708 1143
2bb8c262 1144 netif_tx_lock_bh(dev);
bea3348e 1145 napi_disable(&hw->napi);
d1f13708 1146
d1f13708 1147 sky2->vlgrp = grp;
3d4e66f5
SH		 1148 if (grp) {
1149 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1150 RX_VLAN_STRIP_ON);
1151 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1152 TX_VLAN_TAG_ON);
1153 } else {
1154 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1155 RX_VLAN_STRIP_OFF);
1156 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1157 TX_VLAN_TAG_OFF);
1158 }
d1f13708 1159
bea3348e 1160 napi_enable(&hw->napi);
2bb8c262 1161 netif_tx_unlock_bh(dev);
d1f13708 1162}
1163#endif
1164
82788c7a 1165/*
14d0263f
SH		 1166 * Allocate an skb for receiving. If the MTU is large enough
1167 * make the skb non-linear with a fragment list of pages.
1168 *
82788c7a
SH		 1169 * It appears the hardware has a bug in the FIFO logic that
1170 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1171 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1172 * aligned except if slab debugging is enabled.
82788c7a 1173 */
14d0263f 1174static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1175{
1176 struct sk_buff *skb;
14d0263f
SH		 1177 unsigned long p;
1178 int i;
82788c7a 1179
14d0263f
SH		 1180 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1181 if (!skb)
1182 goto nomem;
1183
1184 p = (unsigned long) skb->data;
1185 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1186
1187 for (i = 0; i < sky2->rx_nfrags; i++) {
1188 struct page *page = alloc_page(GFP_ATOMIC);
1189
1190 if (!page)
1191 goto free_partial;
1192 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1193 }
1194
1195 return skb;
14d0263f
SH		 1196free_partial:
1197 kfree_skb(skb);
1198nomem:
1199 return NULL;
82788c7a
SH		 1200}
1201
55c9dd35
SH		 1202static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1203{
1204 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1205}
1206
cd28ab6a
SH		 1207/*
1208 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1209 * Normal case this ends up creating one list element for skb
1210 * in the receive ring. Worst case if using large MTU and each
1211 * allocation falls on a different 64 bit region, that results
1212 * in 6 list elements per ring entry.
1213 * One element is used for checksum enable/disable, and one
1214 * extra to avoid wrap.
cd28ab6a 1215 */
6b1a3aef 1216static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1217{
6b1a3aef 1218 struct sky2_hw *hw = sky2->hw;
14d0263f 1219 struct rx_ring_info *re;
6b1a3aef 1220 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1221 unsigned i, size, space, thresh;
cd28ab6a 1222
6b1a3aef 1223 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1224 sky2_qset(hw, rxq);
977bdf06 1225
c3905bc4
SH		 1226 /* On PCI express lowering the watermark gives better performance */
1227 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1228 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1229
1230 /* These chips have no ram buffer?
1231 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1232 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1233 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1234 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1235 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1236
6b1a3aef 1237 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1238
ea76e635
SH		 1239 if (!(hw->flags & SKY2_HW_NEW_LE))
1240 rx_set_checksum(sky2);
14d0263f
SH		 1241
1242 /* Space needed for frame data + headers rounded up */
f957da2a 1243 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1244
1245 /* Stopping point for hardware truncation */
1246 thresh = (size - 8) / sizeof(u32);
1247
1248 /* Account for overhead of skb - to avoid order > 0 allocation */
1249 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1250 + sizeof(struct skb_shared_info);
1251
1252 sky2->rx_nfrags = space >> PAGE_SHIFT;
1253 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1254
1255 if (sky2->rx_nfrags != 0) {
1256 /* Compute residue after pages */
1257 space = sky2->rx_nfrags << PAGE_SHIFT;
1258
1259 if (space < size)
1260 size -= space;
1261 else
1262 size = 0;
1263
1264 /* Optimize to handle small packets and headers */
1265 if (size < copybreak)
1266 size = copybreak;
1267 if (size < ETH_HLEN)
1268 size = ETH_HLEN;
1269 }
1270 sky2->rx_data_size = size;
1271
1272 /* Fill Rx ring */
793b883e 1273 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1274 re = sky2->rx_ring + i;
cd28ab6a 1275
14d0263f 1276 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1277 if (!re->skb)
1278 goto nomem;
1279
14d0263f
SH		 1280 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1281 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1282 }
1283
a1433ac4
SH		 1284 /*
1285 * The receiver hangs if it receives frames larger than the
1286 * packet buffer. As a workaround, truncate oversize frames, but
1287 * the register is limited to 9 bits, so if you do frames > 2052
1288 * you better get the MTU right!
1289 */
a1433ac4
SH		 1290 if (thresh > 0x1ff)
1291 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1292 else {
1293 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1294 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1295 }
1296
6b1a3aef 1297 /* Tell chip about available buffers */
55c9dd35 1298 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1299 return 0;
1300nomem:
1301 sky2_rx_clean(sky2);
1302 return -ENOMEM;
1303}
1304
1305/* Bring up network interface. */
1306static int sky2_up(struct net_device *dev)
1307{
1308 struct sky2_port *sky2 = netdev_priv(dev);
1309 struct sky2_hw *hw = sky2->hw;
1310 unsigned port = sky2->port;
e0c28116 1311 u32 imask, ramsize;
ee7abb04 1312 int cap, err = -ENOMEM;
843a46f4 1313 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1314
ee7abb04
SH		 1315 /*
1316 * On dual port PCI-X card, there is an problem where status
1317 * can be received out of order due to split transactions
843a46f4 1318 */
ee7abb04
SH		 1319 if (otherdev && netif_running(otherdev) &&
1320 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1321 u16 cmd;
1322
b32f40c4 1323 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1324 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1325 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1326
ee7abb04 1327 }
843a46f4 1328
cd28ab6a
SH		 1329 if (netif_msg_ifup(sky2))
1330 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1331
55d7b4e6
SH		 1332 netif_carrier_off(dev);
1333
cd28ab6a
SH		 1334 /* must be power of 2 */
1335 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1336 TX_RING_SIZE *
1337 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1338 &sky2->tx_le_map);
1339 if (!sky2->tx_le)
1340 goto err_out;
1341
6cdbbdf3 1342 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1343 GFP_KERNEL);
1344 if (!sky2->tx_ring)
1345 goto err_out;
88f5f0ca
SH		 1346
1347 tx_init(sky2);
cd28ab6a
SH		 1348
1349 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1350 &sky2->rx_le_map);
1351 if (!sky2->rx_le)
1352 goto err_out;
1353 memset(sky2->rx_le, 0, RX_LE_BYTES);
1354
291ea614 1355 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1356 GFP_KERNEL);
1357 if (!sky2->rx_ring)
1358 goto err_out;
1359
d3bcfbeb 1360 sky2_phy_power(hw, port, 1);
1361
cd28ab6a
SH		 1362 sky2_mac_init(hw, port);
1363
e0c28116
SH		 1364 /* Register is number of 4K blocks on internal RAM buffer. */
1365 ramsize = sky2_read8(hw, B2_E_0) * 4;
1366 if (ramsize > 0) {
67712901 1367 u32 rxspace;
cd28ab6a 1368
e0c28116 1369 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1370 if (ramsize < 16)
1371 rxspace = ramsize / 2;
1372 else
1373 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1374
67712901
SH		 1375 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1376 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1377
1378 /* Make sure SyncQ is disabled */
1379 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1380 RB_RST_SET);
1381 }
793b883e 1382
af4ed7e6 1383 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1384
69161611
SH		 1385 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1386 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1387 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1388
977bdf06 1389 /* Set almost empty threshold */
c2716fb4
SH		 1390 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1391 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1392 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1393
6b1a3aef 1394 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1395 TX_RING_SIZE - 1);
cd28ab6a 1396
6b1a3aef 1397 err = sky2_rx_start(sky2);
6de16237 1398 if (err)
cd28ab6a
SH		 1399 goto err_out;
1400
cd28ab6a 1401 /* Enable interrupts from phy/mac for port */
e07b1aa8 1402 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1403 imask |= portirq_msk[port];
e07b1aa8
SH		 1404 sky2_write32(hw, B0_IMSK, imask);
1405
cd28ab6a
SH		 1406 return 0;
1407
1408err_out:
1b537565 1409 if (sky2->rx_le) {
cd28ab6a
SH		 1410 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1411 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1412 sky2->rx_le = NULL;
1413 }
1414 if (sky2->tx_le) {
cd28ab6a
SH		 1415 pci_free_consistent(hw->pdev,
1416 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1417 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1418 sky2->tx_le = NULL;
1419 }
1420 kfree(sky2->tx_ring);
1421 kfree(sky2->rx_ring);
cd28ab6a 1422
1b537565
SH		 1423 sky2->tx_ring = NULL;
1424 sky2->rx_ring = NULL;
cd28ab6a
SH		 1425 return err;
1426}
1427
793b883e
SH		 1428/* Modular subtraction in ring */
1429static inline int tx_dist(unsigned tail, unsigned head)
1430{
cb5d9547 1431 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1432}
cd28ab6a 1433
793b883e
SH		 1434/* Number of list elements available for next tx */
1435static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1436{
793b883e 1437 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1438}
1439
793b883e 1440/* Estimate of number of transmit list elements required */
28bd181a 1441static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1442{
793b883e
SH		 1443 unsigned count;
1444
1445 count = sizeof(dma_addr_t) / sizeof(u32);
1446 count += skb_shinfo(skb)->nr_frags * count;
1447
89114afd 1448 if (skb_is_gso(skb))
793b883e
SH		 1449 ++count;
1450
84fa7933 1451 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1452 ++count;
1453
1454 return count;
cd28ab6a
SH		 1455}
1456
793b883e
SH		 1457/*
1458 * Put one packet in ring for transmit.
1459 * A single packet can generate multiple list elements, and
1460 * the number of ring elements will probably be less than the number
1461 * of list elements used.
1462 */
cd28ab6a
SH		 1463static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1464{
1465 struct sky2_port *sky2 = netdev_priv(dev);
1466 struct sky2_hw *hw = sky2->hw;
d1f13708 1467 struct sky2_tx_le *le = NULL;
6cdbbdf3 1468 struct tx_ring_info *re;
cd28ab6a
SH		 1469 unsigned i, len;
1470 dma_addr_t mapping;
1471 u32 addr64;
1472 u16 mss;
1473 u8 ctrl;
1474
2bb8c262
SH		 1475 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1476 return NETDEV_TX_BUSY;
cd28ab6a 1477
793b883e 1478 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1479 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1480 dev->name, sky2->tx_prod, skb->len);
1481
cd28ab6a
SH		 1482 len = skb_headlen(skb);
1483 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1484 addr64 = upper_32_bits(mapping);
793b883e 1485
a018e330 1486 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1487 if (addr64 != sky2->tx_addr64 ||
1488 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1489 le = get_tx_le(sky2);
f65b138c 1490 le->addr = cpu_to_le32(addr64);
793b883e 1491 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1492 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1493 }
cd28ab6a
SH		 1494
1495 /* Check for TCP Segmentation Offload */
7967168c 1496 mss = skb_shinfo(skb)->gso_size;
793b883e 1497 if (mss != 0) {
ea76e635
SH		 1498
1499 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1500 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1501
1502 if (mss != sky2->tx_last_mss) {
1503 le = get_tx_le(sky2);
1504 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1505
1506 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1507 le->opcode = OP_MSS | HW_OWNER;
1508 else
1509 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1510 sky2->tx_last_mss = mss;
1511 }
cd28ab6a
SH		 1512 }
1513
cd28ab6a 1514 ctrl = 0;
d1f13708 1515#ifdef SKY2_VLAN_TAG_USED
1516 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1517 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1518 if (!le) {
1519 le = get_tx_le(sky2);
f65b138c 1520 le->addr = 0;
d1f13708 1521 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1522 } else
1523 le->opcode |= OP_VLAN;
1524 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1525 ctrl |= INS_VLAN;
1526 }
1527#endif
1528
1529 /* Handle TCP checksum offload */
84fa7933 1530 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1531 /* On Yukon EX (some versions) encoding change. */
ea76e635 1532 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1533 ctrl |= CALSUM; /* auto checksum */
1534 else {
1535 const unsigned offset = skb_transport_offset(skb);
1536 u32 tcpsum;
1537
1538 tcpsum = offset << 16; /* sum start */
1539 tcpsum |= offset + skb->csum_offset; /* sum write */
1540
1541 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1542 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1543 ctrl |= UDPTCP;
1544
1545 if (tcpsum != sky2->tx_tcpsum) {
1546 sky2->tx_tcpsum = tcpsum;
1547
1548 le = get_tx_le(sky2);
1549 le->addr = cpu_to_le32(tcpsum);
1550 le->length = 0; /* initial checksum value */
1551 le->ctrl = 1; /* one packet */
1552 le->opcode = OP_TCPLISW | HW_OWNER;
1553 }
1d179332 1554 }
cd28ab6a
SH		 1555 }
1556
1557 le = get_tx_le(sky2);
f65b138c 1558 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1559 le->length = cpu_to_le16(len);
1560 le->ctrl = ctrl;
793b883e 1561 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1562
291ea614 1563 re = tx_le_re(sky2, le);
cd28ab6a 1564 re->skb = skb;
6cdbbdf3 1565 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1566 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1567
1568 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1569 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1570
1571 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1572 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1573 addr64 = upper_32_bits(mapping);
793b883e
SH		 1574 if (addr64 != sky2->tx_addr64) {
1575 le = get_tx_le(sky2);
f65b138c 1576 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1577 le->ctrl = 0;
1578 le->opcode = OP_ADDR64 | HW_OWNER;
1579 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1580 }
1581
1582 le = get_tx_le(sky2);
f65b138c 1583 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1584 le->length = cpu_to_le16(frag->size);
1585 le->ctrl = ctrl;
793b883e 1586 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1587
291ea614
SH		 1588 re = tx_le_re(sky2, le);
1589 re->skb = skb;
1590 pci_unmap_addr_set(re, mapaddr, mapping);
1591 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1592 }
6cdbbdf3 1593
cd28ab6a
SH		 1594 le->ctrl |= EOP;
1595
97bda706 1596 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1597 netif_stop_queue(dev);
b19666d9 1598
290d4de5 1599 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1600
cd28ab6a
SH		 1601 dev->trans_start = jiffies;
1602 return NETDEV_TX_OK;
1603}
1604
cd28ab6a 1605/*
793b883e
SH		 1606 * Free ring elements from starting at tx_cons until "done"
1607 *
1608 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1609 * buffers so make sure not to free skb to early.
cd28ab6a 1610 */
d11c13e7 1611static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1612{
d11c13e7 1613 struct net_device *dev = sky2->netdev;
af2a58ac 1614 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1615 unsigned idx;
cd28ab6a 1616
0e3ff6aa 1617 BUG_ON(done >= TX_RING_SIZE);
2224795d 1618
291ea614
SH		 1619 for (idx = sky2->tx_cons; idx != done;
1620 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1621 struct sky2_tx_le *le = sky2->tx_le + idx;
1622 struct tx_ring_info *re = sky2->tx_ring + idx;
1623
1624 switch(le->opcode & ~HW_OWNER) {
1625 case OP_LARGESEND:
1626 case OP_PACKET:
1627 pci_unmap_single(pdev,
1628 pci_unmap_addr(re, mapaddr),
1629 pci_unmap_len(re, maplen),
1630 PCI_DMA_TODEVICE);
af2a58ac 1631 break;
291ea614
SH		 1632 case OP_BUFFER:
1633 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1634 pci_unmap_len(re, maplen),
734d1868 1635 PCI_DMA_TODEVICE);
291ea614
SH		 1636 break;
1637 }
1638
1639 if (le->ctrl & EOP) {
1640 if (unlikely(netif_msg_tx_done(sky2)))
1641 printk(KERN_DEBUG "%s: tx done %u\n",
1642 dev->name, idx);
3cf26753 1643
7138a0f5
SH		 1644 dev->stats.tx_packets++;
1645 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1646
794b2bd2 1647 dev_kfree_skb_any(re->skb);
3cf26753 1648 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1649 }
793b883e 1650 }
793b883e 1651
291ea614 1652 sky2->tx_cons = idx;
50432cb5
SH		 1653 smp_mb();
1654
22e11703 1655 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1656 netif_wake_queue(dev);
cd28ab6a
SH		 1657}
1658
1659/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1660static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1661{
2bb8c262
SH		 1662 struct sky2_port *sky2 = netdev_priv(dev);
1663
1664 netif_tx_lock_bh(dev);
d11c13e7 1665 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1666 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1667}
1668
1669/* Network shutdown */
1670static int sky2_down(struct net_device *dev)
1671{
1672 struct sky2_port *sky2 = netdev_priv(dev);
1673 struct sky2_hw *hw = sky2->hw;
1674 unsigned port = sky2->port;
1675 u16 ctrl;
e07b1aa8 1676 u32 imask;
cd28ab6a 1677
1b537565
SH		 1678 /* Never really got started! */
1679 if (!sky2->tx_le)
1680 return 0;
1681
cd28ab6a
SH		 1682 if (netif_msg_ifdown(sky2))
1683 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1684
018d1c66 1685 /* Stop more packets from being queued */
cd28ab6a
SH		 1686 netif_stop_queue(dev);
1687
ebc646f6
SH		 1688 /* Disable port IRQ */
1689 imask = sky2_read32(hw, B0_IMSK);
1690 imask &= ~portirq_msk[port];
1691 sky2_write32(hw, B0_IMSK, imask);
1692
6de16237
SH		 1693 synchronize_irq(hw->pdev->irq);
1694
d3bcfbeb 1695 sky2_gmac_reset(hw, port);
793b883e 1696
cd28ab6a
SH		 1697 /* Stop transmitter */
1698 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1699 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1700
1701 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1702 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1703
1704 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1705 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1706 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1707
6de16237
SH		 1708 /* Make sure no packets are pending */
1709 napi_synchronize(&hw->napi);
1710
cd28ab6a
SH		 1711 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1712
1713 /* Workaround shared GMAC reset */
793b883e
SH		 1714 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1715 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1716 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1717
1718 /* Disable Force Sync bit and Enable Alloc bit */
1719 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1720 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1721
1722 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1723 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1724 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1725
1726 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1727 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1728 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1729
1730 /* Reset the Tx prefetch units */
1731 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1732 PREF_UNIT_RST_SET);
1733
1734 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1735
6b1a3aef 1736 sky2_rx_stop(sky2);
cd28ab6a
SH		 1737
1738 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1739 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1740
d3bcfbeb 1741 sky2_phy_power(hw, port, 0);
1742
55d7b4e6
SH		 1743 netif_carrier_off(dev);
1744
d571b694 1745 /* turn off LED's */
cd28ab6a
SH		 1746 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1747
2bb8c262 1748 sky2_tx_clean(dev);
cd28ab6a
SH		 1749 sky2_rx_clean(sky2);
1750
1751 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1752 sky2->rx_le, sky2->rx_le_map);
1753 kfree(sky2->rx_ring);
1754
1755 pci_free_consistent(hw->pdev,
1756 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1757 sky2->tx_le, sky2->tx_le_map);
1758 kfree(sky2->tx_ring);
1759
1b537565
SH		 1760 sky2->tx_le = NULL;
1761 sky2->rx_le = NULL;
1762
1763 sky2->rx_ring = NULL;
1764 sky2->tx_ring = NULL;
1765
cd28ab6a
SH		 1766 return 0;
1767}
1768
1769static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1770{
ea76e635 1771 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1772 return SPEED_1000;
1773
05745c4a
SH		 1774 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1775 if (aux & PHY_M_PS_SPEED_100)
1776 return SPEED_100;
1777 else
1778 return SPEED_10;
1779 }
cd28ab6a
SH		 1780
1781 switch (aux & PHY_M_PS_SPEED_MSK) {
1782 case PHY_M_PS_SPEED_1000:
1783 return SPEED_1000;
1784 case PHY_M_PS_SPEED_100:
1785 return SPEED_100;
1786 default:
1787 return SPEED_10;
1788 }
1789}
1790
1791static void sky2_link_up(struct sky2_port *sky2)
1792{
1793 struct sky2_hw *hw = sky2->hw;
1794 unsigned port = sky2->port;
1795 u16 reg;
16ad91e1
SH		 1796 static const char *fc_name[] = {
1797 [FC_NONE] = "none",
1798 [FC_TX] = "tx",
1799 [FC_RX] = "rx",
1800 [FC_BOTH] = "both",
1801 };
cd28ab6a 1802
cd28ab6a 1803 /* enable Rx/Tx */
2eaba1a2 1804 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1805 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1806 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1807
1808 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1809
1810 netif_carrier_on(sky2->netdev);
cd28ab6a 1811
75e80683 1812 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1813
cd28ab6a 1814 /* Turn on link LED */
793b883e 1815 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1816 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1817
1818 if (netif_msg_link(sky2))
1819 printk(KERN_INFO PFX
d571b694 1820 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1821 sky2->netdev->name, sky2->speed,
1822 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1823 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1824}
1825
1826static void sky2_link_down(struct sky2_port *sky2)
1827{
1828 struct sky2_hw *hw = sky2->hw;
1829 unsigned port = sky2->port;
1830 u16 reg;
1831
1832 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1833
1834 reg = gma_read16(hw, port, GM_GP_CTRL);
1835 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1836 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1837
cd28ab6a 1838 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1839
1840 /* Turn on link LED */
1841 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1842
1843 if (netif_msg_link(sky2))
1844 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1845
cd28ab6a
SH		 1846 sky2_phy_init(hw, port);
1847}
1848
16ad91e1
SH		 1849static enum flow_control sky2_flow(int rx, int tx)
1850{
1851 if (rx)
1852 return tx ? FC_BOTH : FC_RX;
1853 else
1854 return tx ? FC_TX : FC_NONE;
1855}
1856
793b883e
SH		 1857static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1858{
1859 struct sky2_hw *hw = sky2->hw;
1860 unsigned port = sky2->port;
da4c1ff4 1861 u16 advert, lpa;
793b883e 1862
da4c1ff4 1863 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1864 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1865 if (lpa & PHY_M_AN_RF) {
1866 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1867 return -1;
1868 }
1869
793b883e
SH		 1870 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1871 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1872 sky2->netdev->name);
1873 return -1;
1874 }
1875
793b883e 1876 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1877 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1878
da4c1ff4
SH		 1879 /* Since the pause result bits seem to in different positions on
1880 * different chips. look at registers.
1881 */
ea76e635 1882 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1883 /* Shift for bits in fiber PHY */
1884 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1885 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1886
1887 if (advert & ADVERTISE_1000XPAUSE)
1888 advert |= ADVERTISE_PAUSE_CAP;
1889 if (advert & ADVERTISE_1000XPSE_ASYM)
1890 advert |= ADVERTISE_PAUSE_ASYM;
1891 if (lpa & LPA_1000XPAUSE)
1892 lpa |= LPA_PAUSE_CAP;
1893 if (lpa & LPA_1000XPAUSE_ASYM)
1894 lpa |= LPA_PAUSE_ASYM;
1895 }
793b883e 1896
da4c1ff4
SH		 1897 sky2->flow_status = FC_NONE;
1898 if (advert & ADVERTISE_PAUSE_CAP) {
1899 if (lpa & LPA_PAUSE_CAP)
1900 sky2->flow_status = FC_BOTH;
1901 else if (advert & ADVERTISE_PAUSE_ASYM)
1902 sky2->flow_status = FC_RX;
1903 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1904 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1905 sky2->flow_status = FC_TX;
1906 }
793b883e 1907
16ad91e1 1908 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1909 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1910 sky2->flow_status = FC_NONE;
2eaba1a2 1911
da4c1ff4 1912 if (sky2->flow_status & FC_TX)
793b883e
SH		 1913 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1914 else
1915 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1916
1917 return 0;
1918}
cd28ab6a 1919
e07b1aa8
SH		 1920/* Interrupt from PHY */
1921static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1922{
e07b1aa8
SH		 1923 struct net_device *dev = hw->dev[port];
1924 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1925 u16 istatus, phystat;
1926
ebc646f6
SH		 1927 if (!netif_running(dev))
1928 return;
1929
e07b1aa8
SH		 1930 spin_lock(&sky2->phy_lock);
1931 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1932 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1933
cd28ab6a
SH		 1934 if (netif_msg_intr(sky2))
1935 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1936 sky2->netdev->name, istatus, phystat);
1937
2eaba1a2 1938 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1939 if (sky2_autoneg_done(sky2, phystat) == 0)
1940 sky2_link_up(sky2);
1941 goto out;
1942 }
cd28ab6a 1943
793b883e
SH		 1944 if (istatus & PHY_M_IS_LSP_CHANGE)
1945 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1946
793b883e
SH		 1947 if (istatus & PHY_M_IS_DUP_CHANGE)
1948 sky2->duplex =
1949 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1950
793b883e
SH		 1951 if (istatus & PHY_M_IS_LST_CHANGE) {
1952 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1953 sky2_link_up(sky2);
793b883e
SH		 1954 else
1955 sky2_link_down(sky2);
cd28ab6a 1956 }
793b883e 1957out:
e07b1aa8 1958 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1959}
1960
62335ab0 1961/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1962 * and tx queue is full (stopped).
1963 */
cd28ab6a
SH		 1964static void sky2_tx_timeout(struct net_device *dev)
1965{
1966 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1967 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1968
1969 if (netif_msg_timer(sky2))
1970 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1971
8f24664d 1972 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1973 dev->name, sky2->tx_cons, sky2->tx_prod,
1974 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1975 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1976
81906791
SH		 1977 /* can't restart safely under softirq */
1978 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1979}
1980
1981static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1982{
6b1a3aef 1983 struct sky2_port *sky2 = netdev_priv(dev);
1984 struct sky2_hw *hw = sky2->hw;
b628ed98 1985 unsigned port = sky2->port;
6b1a3aef 1986 int err;
1987 u16 ctl, mode;
e07b1aa8 1988 u32 imask;
cd28ab6a
SH		 1989
1990 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1991 return -EINVAL;
1992
05745c4a
SH		 1993 if (new_mtu > ETH_DATA_LEN &&
1994 (hw->chip_id == CHIP_ID_YUKON_FE ||
1995 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 1996 return -EINVAL;
1997
6b1a3aef 1998 if (!netif_running(dev)) {
1999 dev->mtu = new_mtu;
2000 return 0;
2001 }
2002
e07b1aa8 2003 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2004 sky2_write32(hw, B0_IMSK, 0);
2005
018d1c66 2006 dev->trans_start = jiffies; /* prevent tx timeout */
2007 netif_stop_queue(dev);
bea3348e 2008 napi_disable(&hw->napi);
018d1c66 2009
e07b1aa8
SH		 2010 synchronize_irq(hw->pdev->irq);
2011
e0c28116 2012 if (sky2_read8(hw, B2_E_0) == 0)
69161611 2013 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2014
2015 ctl = gma_read16(hw, port, GM_GP_CTRL);
2016 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2017 sky2_rx_stop(sky2);
2018 sky2_rx_clean(sky2);
cd28ab6a
SH		 2019
2020 dev->mtu = new_mtu;
14d0263f 2021
6b1a3aef 2022 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2023 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2024
2025 if (dev->mtu > ETH_DATA_LEN)
2026 mode |= GM_SMOD_JUMBO_ENA;
2027
b628ed98 2028 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2029
b628ed98 2030 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2031
6b1a3aef 2032 err = sky2_rx_start(sky2);
e07b1aa8 2033 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2034
bea3348e
SH		 2035 napi_enable(&hw->napi);
2036
1b537565
SH		 2037 if (err)
2038 dev_close(dev);
2039 else {
b628ed98 2040 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2041
1b537565
SH		 2042 netif_wake_queue(dev);
2043 }
2044
cd28ab6a
SH		 2045 return err;
2046}
2047
14d0263f
SH		 2048/* For small just reuse existing skb for next receive */
2049static struct sk_buff *receive_copy(struct sky2_port *sky2,
2050 const struct rx_ring_info *re,
2051 unsigned length)
2052{
2053 struct sk_buff *skb;
2054
2055 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2056 if (likely(skb)) {
2057 skb_reserve(skb, 2);
2058 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2059 length, PCI_DMA_FROMDEVICE);
d626f62b 2060 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2061 skb->ip_summed = re->skb->ip_summed;
2062 skb->csum = re->skb->csum;
2063 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2064 length, PCI_DMA_FROMDEVICE);
2065 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2066 skb_put(skb, length);
14d0263f
SH		 2067 }
2068 return skb;
2069}
2070
2071/* Adjust length of skb with fragments to match received data */
2072static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2073 unsigned int length)
2074{
2075 int i, num_frags;
2076 unsigned int size;
2077
2078 /* put header into skb */
2079 size = min(length, hdr_space);
2080 skb->tail += size;
2081 skb->len += size;
2082 length -= size;
2083
2084 num_frags = skb_shinfo(skb)->nr_frags;
2085 for (i = 0; i < num_frags; i++) {
2086 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2087
2088 if (length == 0) {
2089 /* don't need this page */
2090 __free_page(frag->page);
2091 --skb_shinfo(skb)->nr_frags;
2092 } else {
2093 size = min(length, (unsigned) PAGE_SIZE);
2094
2095 frag->size = size;
2096 skb->data_len += size;
2097 skb->truesize += size;
2098 skb->len += size;
2099 length -= size;
2100 }
2101 }
2102}
2103
2104/* Normal packet - take skb from ring element and put in a new one */
2105static struct sk_buff *receive_new(struct sky2_port *sky2,
2106 struct rx_ring_info *re,
2107 unsigned int length)
2108{
2109 struct sk_buff *skb, *nskb;
2110 unsigned hdr_space = sky2->rx_data_size;
2111
14d0263f
SH		 2112 /* Don't be tricky about reusing pages (yet) */
2113 nskb = sky2_rx_alloc(sky2);
2114 if (unlikely(!nskb))
2115 return NULL;
2116
2117 skb = re->skb;
2118 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2119
2120 prefetch(skb->data);
2121 re->skb = nskb;
2122 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2123
2124 if (skb_shinfo(skb)->nr_frags)
2125 skb_put_frags(skb, hdr_space, length);
2126 else
489b10c1 2127 skb_put(skb, length);
14d0263f
SH		 2128 return skb;
2129}
2130
cd28ab6a
SH		 2131/*
2132 * Receive one packet.
d571b694 2133 * For larger packets, get new buffer.
cd28ab6a 2134 */
497d7c86 2135static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2136 u16 length, u32 status)
2137{
497d7c86 2138 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2139 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2140 struct sk_buff *skb = NULL;
d6532232
SH		 2141 u16 count = (status & GMR_FS_LEN) >> 16;
2142
2143#ifdef SKY2_VLAN_TAG_USED
2144 /* Account for vlan tag */
2145 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2146 count -= VLAN_HLEN;
2147#endif
cd28ab6a
SH		 2148
2149 if (unlikely(netif_msg_rx_status(sky2)))
2150 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2151 dev->name, sky2->rx_next, status, length);
cd28ab6a 2152
793b883e 2153 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2154 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2155
3b12e014
SH		 2156 /* This chip has hardware problems that generates bogus status.
2157 * So do only marginal checking and expect higher level protocols
2158 * to handle crap frames.
2159 */
2160 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2161 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2162 length != count)
2163 goto okay;
2164
42eeea01 2165 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2166 goto error;
2167
42eeea01 2168 if (!(status & GMR_FS_RX_OK))
2169 goto resubmit;
2170
d6532232
SH		 2171 /* if length reported by DMA does not match PHY, packet was truncated */
2172 if (length != count)
3b12e014 2173 goto len_error;
71749531 2174
3b12e014 2175okay:
14d0263f
SH		 2176 if (length < copybreak)
2177 skb = receive_copy(sky2, re, length);
2178 else
2179 skb = receive_new(sky2, re, length);
793b883e 2180resubmit:
14d0263f 2181 sky2_rx_submit(sky2, re);
79e57d32 2182
cd28ab6a
SH		 2183 return skb;
2184
3b12e014 2185len_error:
71749531
SH		 2186 /* Truncation of overlength packets
2187 causes PHY length to not match MAC length */
7138a0f5 2188 ++dev->stats.rx_length_errors;
d6532232 2189 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2190 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2191 dev->name, status, length);
d6532232 2192 goto resubmit;
71749531 2193
cd28ab6a 2194error:
7138a0f5 2195 ++dev->stats.rx_errors;
b6d77734 2196 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2197 dev->stats.rx_over_errors++;
b6d77734
SH		 2198 goto resubmit;
2199 }
6e15b712 2200
3be92a70 2201 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2202 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2203 dev->name, status, length);
793b883e
SH		 2204
2205 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2206 dev->stats.rx_length_errors++;
cd28ab6a 2207 if (status & GMR_FS_FRAGMENT)
7138a0f5 2208 dev->stats.rx_frame_errors++;
cd28ab6a 2209 if (status & GMR_FS_CRC_ERR)
7138a0f5 2210 dev->stats.rx_crc_errors++;
79e57d32 2211
793b883e 2212 goto resubmit;
cd28ab6a
SH		 2213}
2214
e07b1aa8
SH		 2215/* Transmit complete */
2216static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2217{
e07b1aa8 2218 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2219
e07b1aa8 2220 if (netif_running(dev)) {
2bb8c262 2221 netif_tx_lock(dev);
e07b1aa8 2222 sky2_tx_complete(sky2, last);
2bb8c262 2223 netif_tx_unlock(dev);
2224795d 2224 }
cd28ab6a
SH		 2225}
2226
e07b1aa8 2227/* Process status response ring */
26691830 2228static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2229{
e07b1aa8 2230 int work_done = 0;
55c9dd35 2231 unsigned rx[2] = { 0, 0 };
a8fd6266 2232
af2a58ac 2233 rmb();
26691830 2234 do {
55c9dd35 2235 struct sky2_port *sky2;
13210ce5 2236 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2237 unsigned port;
13210ce5 2238 struct net_device *dev;
cd28ab6a 2239 struct sk_buff *skb;
cd28ab6a
SH		 2240 u32 status;
2241 u16 length;
ab5adecb
SH		 2242 u8 opcode = le->opcode;
2243
2244 if (!(opcode & HW_OWNER))
2245 break;
cd28ab6a 2246
cb5d9547 2247 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2248
ab5adecb 2249 port = le->css & CSS_LINK_BIT;
69161611 2250 dev = hw->dev[port];
13210ce5 2251 sky2 = netdev_priv(dev);
f65b138c
SH		 2252 length = le16_to_cpu(le->length);
2253 status = le32_to_cpu(le->status);
cd28ab6a 2254
ab5adecb
SH		 2255 le->opcode = 0;
2256 switch (opcode & ~HW_OWNER) {
cd28ab6a 2257 case OP_RXSTAT:
55c9dd35 2258 ++rx[port];
497d7c86 2259 skb = sky2_receive(dev, length, status);
3225b919 2260 if (unlikely(!skb)) {
7138a0f5 2261 dev->stats.rx_dropped++;
55c9dd35 2262 break;
3225b919 2263 }
13210ce5 2264
69161611 2265 /* This chip reports checksum status differently */
05745c4a 2266 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2267 if (sky2->rx_csum &&
2268 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2269 (le->css & CSS_TCPUDPCSOK))
2270 skb->ip_summed = CHECKSUM_UNNECESSARY;
2271 else
2272 skb->ip_summed = CHECKSUM_NONE;
2273 }
2274
13210ce5 2275 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2276 dev->stats.rx_packets++;
2277 dev->stats.rx_bytes += skb->len;
13210ce5 2278 dev->last_rx = jiffies;
2279
d1f13708 2280#ifdef SKY2_VLAN_TAG_USED
2281 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2282 vlan_hwaccel_receive_skb(skb,
2283 sky2->vlgrp,
2284 be16_to_cpu(sky2->rx_tag));
2285 } else
2286#endif
cd28ab6a 2287 netif_receive_skb(skb);
13210ce5 2288
22e11703 2289 /* Stop after net poll weight */
13210ce5 2290 if (++work_done >= to_do)
2291 goto exit_loop;
cd28ab6a
SH		 2292 break;
2293
d1f13708 2294#ifdef SKY2_VLAN_TAG_USED
2295 case OP_RXVLAN:
2296 sky2->rx_tag = length;
2297 break;
2298
2299 case OP_RXCHKSVLAN:
2300 sky2->rx_tag = length;
2301 /* fall through */
2302#endif
cd28ab6a 2303 case OP_RXCHKS:
87418307
SH		 2304 if (!sky2->rx_csum)
2305 break;
2306
05745c4a
SH		 2307 /* If this happens then driver assuming wrong format */
2308 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2309 if (net_ratelimit())
2310 printk(KERN_NOTICE "%s: unexpected"
2311 " checksum status\n",
2312 dev->name);
69161611 2313 break;
05745c4a 2314 }
69161611 2315
87418307
SH		 2316 /* Both checksum counters are programmed to start at
2317 * the same offset, so unless there is a problem they
2318 * should match. This failure is an early indication that
2319 * hardware receive checksumming won't work.
2320 */
2321 if (likely(status >> 16 == (status & 0xffff))) {
2322 skb = sky2->rx_ring[sky2->rx_next].skb;
2323 skb->ip_summed = CHECKSUM_COMPLETE;
2324 skb->csum = status & 0xffff;
2325 } else {
2326 printk(KERN_NOTICE PFX "%s: hardware receive "
2327 "checksum problem (status = %#x)\n",
2328 dev->name, status);
2329 sky2->rx_csum = 0;
2330 sky2_write32(sky2->hw,
69161611 2331 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2332 BMU_DIS_RX_CHKSUM);
2333 }
cd28ab6a
SH		 2334 break;
2335
2336 case OP_TXINDEXLE:
13b97b74 2337 /* TX index reports status for both ports */
f55925d7
SH		 2338 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2339 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2340 if (hw->dev[1])
2341 sky2_tx_done(hw->dev[1],
2342 ((status >> 24) & 0xff)
2343 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2344 break;
2345
cd28ab6a
SH		 2346 default:
2347 if (net_ratelimit())
793b883e 2348 printk(KERN_WARNING PFX
ab5adecb 2349 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2350 }
26691830 2351 } while (hw->st_idx != idx);
cd28ab6a 2352
fe2a24df
SH		 2353 /* Fully processed status ring so clear irq */
2354 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2355
13210ce5 2356exit_loop:
55c9dd35
SH		 2357 if (rx[0])
2358 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2359
55c9dd35
SH		 2360 if (rx[1])
2361 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2362
e07b1aa8 2363 return work_done;
cd28ab6a
SH		 2364}
2365
2366static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2367{
2368 struct net_device *dev = hw->dev[port];
2369
3be92a70
SH		 2370 if (net_ratelimit())
2371 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2372 dev->name, status);
cd28ab6a
SH		 2373
2374 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2375 if (net_ratelimit())
2376 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2377 dev->name);
cd28ab6a
SH		 2378 /* Clear IRQ */
2379 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2380 }
2381
2382 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2383 if (net_ratelimit())
2384 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2385 dev->name);
cd28ab6a
SH		 2386
2387 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2388 }
2389
2390 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2391 if (net_ratelimit())
2392 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2393 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2394 }
2395
2396 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2397 if (net_ratelimit())
2398 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2399 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2400 }
2401
2402 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2403 if (net_ratelimit())
2404 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2405 dev->name);
cd28ab6a
SH		 2406 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2407 }
2408}
2409
2410static void sky2_hw_intr(struct sky2_hw *hw)
2411{
555382cb 2412 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2413 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2414 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2415
2416 status &= hwmsk;
cd28ab6a 2417
793b883e 2418 if (status & Y2_IS_TIST_OV)
cd28ab6a 2419 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2420
2421 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2422 u16 pci_err;
2423
b32f40c4 2424 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2425 if (net_ratelimit())
555382cb 2426 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2427 pci_err);
cd28ab6a 2428
b32f40c4 2429 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2430 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2431 }
2432
2433 if (status & Y2_IS_PCI_EXP) {
d571b694 2434 /* PCI-Express uncorrectable Error occurred */
cf06ffb4 2435 int aer = pci_find_aer_capability(hw->pdev);
555382cb 2436 u32 err;
cd28ab6a 2437
cf06ffb4
SH		 2438 if (aer) {
2439 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS,
2440 &err);
2441 pci_cleanup_aer_uncorrect_error_status(pdev);
2442 } else {
2443 /* Either AER not configured, or not working
2444 * because of bad MMCONFIG, so just do recover
2445 * manually.
2446 */
2447 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2448 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2449 0xfffffffful);
2450 }
2451
3be92a70 2452 if (net_ratelimit())
555382cb 2453 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2454
cd28ab6a
SH		 2455 }
2456
2457 if (status & Y2_HWE_L1_MASK)
2458 sky2_hw_error(hw, 0, status);
2459 status >>= 8;
2460 if (status & Y2_HWE_L1_MASK)
2461 sky2_hw_error(hw, 1, status);
2462}
2463
2464static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2465{
2466 struct net_device *dev = hw->dev[port];
2467 struct sky2_port *sky2 = netdev_priv(dev);
2468 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2469
2470 if (netif_msg_intr(sky2))
2471 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2472 dev->name, status);
2473
a3caeada
SH		 2474 if (status & GM_IS_RX_CO_OV)
2475 gma_read16(hw, port, GM_RX_IRQ_SRC);
2476
2477 if (status & GM_IS_TX_CO_OV)
2478 gma_read16(hw, port, GM_TX_IRQ_SRC);
2479
cd28ab6a 2480 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2481 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2482 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2483 }
2484
2485 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2486 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2487 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2488 }
cd28ab6a
SH		 2489}
2490
40b01727
SH		 2491/* This should never happen it is a bug. */
2492static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2493 u16 q, unsigned ring_size)
d257924e
SH		 2494{
2495 struct net_device *dev = hw->dev[port];
2496 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2497 unsigned idx;
2498 const u64 *le = (q == Q_R1 || q == Q_R2)
2499 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2500
40b01727
SH		 2501 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2502 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2503 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2504 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2505
40b01727 2506 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2507}
cd28ab6a 2508
75e80683
SH		 2509static int sky2_rx_hung(struct net_device *dev)
2510{
2511 struct sky2_port *sky2 = netdev_priv(dev);
2512 struct sky2_hw *hw = sky2->hw;
2513 unsigned port = sky2->port;
2514 unsigned rxq = rxqaddr[port];
2515 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2516 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2517 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2518 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2519
2520 /* If idle and MAC or PCI is stuck */
2521 if (sky2->check.last == dev->last_rx &&
2522 ((mac_rp == sky2->check.mac_rp &&
2523 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2524 /* Check if the PCI RX hang */
2525 (fifo_rp == sky2->check.fifo_rp &&
2526 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2527 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2528 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2529 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2530 return 1;
2531 } else {
2532 sky2->check.last = dev->last_rx;
2533 sky2->check.mac_rp = mac_rp;
2534 sky2->check.mac_lev = mac_lev;
2535 sky2->check.fifo_rp = fifo_rp;
2536 sky2->check.fifo_lev = fifo_lev;
2537 return 0;
2538 }
2539}
2540
32c2c300 2541static void sky2_watchdog(unsigned long arg)
d27ed387 2542{
01bd7564 2543 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2544
75e80683 2545 /* Check for lost IRQ once a second */
32c2c300 2546 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2547 napi_schedule(&hw->napi);
75e80683
SH		 2548 } else {
2549 int i, active = 0;
2550
2551 for (i = 0; i < hw->ports; i++) {
bea3348e 2552 struct net_device *dev = hw->dev[i];
75e80683
SH		 2553 if (!netif_running(dev))
2554 continue;
2555 ++active;
2556
2557 /* For chips with Rx FIFO, check if stuck */
e0c28116 2558 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
75e80683
SH		 2559 sky2_rx_hung(dev)) {
2560 pr_info(PFX "%s: receiver hang detected\n",
2561 dev->name);
2562 schedule_work(&hw->restart_work);
2563 return;
2564 }
2565 }
2566
2567 if (active == 0)
2568 return;
32c2c300 2569 }
01bd7564 2570
75e80683 2571 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2572}
2573
40b01727
SH		 2574/* Hardware/software error handling */
2575static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2576{
40b01727
SH		 2577 if (net_ratelimit())
2578 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2579
1e5f1283
SH		 2580 if (status & Y2_IS_HW_ERR)
2581 sky2_hw_intr(hw);
d257924e 2582
1e5f1283
SH		 2583 if (status & Y2_IS_IRQ_MAC1)
2584 sky2_mac_intr(hw, 0);
cd28ab6a 2585
1e5f1283
SH		 2586 if (status & Y2_IS_IRQ_MAC2)
2587 sky2_mac_intr(hw, 1);
cd28ab6a 2588
1e5f1283 2589 if (status & Y2_IS_CHK_RX1)
40b01727 2590 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2591
1e5f1283 2592 if (status & Y2_IS_CHK_RX2)
40b01727 2593 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2594
1e5f1283 2595 if (status & Y2_IS_CHK_TXA1)
40b01727 2596 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2597
1e5f1283 2598 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2599 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2600}
2601
bea3348e 2602static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2603{
bea3348e 2604 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2605 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2606 int work_done = 0;
26691830 2607 u16 idx;
40b01727
SH		 2608
2609 if (unlikely(status & Y2_IS_ERROR))
2610 sky2_err_intr(hw, status);
2611
2612 if (status & Y2_IS_IRQ_PHY1)
2613 sky2_phy_intr(hw, 0);
2614
2615 if (status & Y2_IS_IRQ_PHY2)
2616 sky2_phy_intr(hw, 1);
cd28ab6a 2617
26691830
SH		 2618 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2619 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2620
2621 if (work_done >= work_limit)
26691830
SH		 2622 goto done;
2623 }
6f535763 2624
26691830
SH		 2625 /* Bug/Errata workaround?
2626 * Need to kick the TX irq moderation timer.
2627 */
2628 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2629 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2630 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2631 }
26691830
SH		 2632 napi_complete(napi);
2633 sky2_read32(hw, B0_Y2_SP_LISR);
2634done:
6f535763 2635
bea3348e 2636 return work_done;
e07b1aa8
SH		 2637}
2638
7d12e780 2639static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2640{
2641 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2642 u32 status;
2643
2644 /* Reading this mask interrupts as side effect */
2645 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2646 if (status == 0 || status == ~0)
2647 return IRQ_NONE;
793b883e 2648
e07b1aa8 2649 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2650
2651 napi_schedule(&hw->napi);
793b883e 2652
cd28ab6a
SH		 2653 return IRQ_HANDLED;
2654}
2655
2656#ifdef CONFIG_NET_POLL_CONTROLLER
2657static void sky2_netpoll(struct net_device *dev)
2658{
2659 struct sky2_port *sky2 = netdev_priv(dev);
2660
bea3348e 2661 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2662}
2663#endif
2664
2665/* Chip internal frequency for clock calculations */
05745c4a 2666static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2667{
793b883e 2668 switch (hw->chip_id) {
cd28ab6a 2669 case CHIP_ID_YUKON_EC:
5a5b1ea0 2670 case CHIP_ID_YUKON_EC_U:
93745494 2671 case CHIP_ID_YUKON_EX:
05745c4a
SH		 2672 return 125;
2673
cd28ab6a 2674 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2675 return 100;
2676
2677 case CHIP_ID_YUKON_FE_P:
2678 return 50;
2679
2680 case CHIP_ID_YUKON_XL:
2681 return 156;
2682
2683 default:
2684 BUG();
cd28ab6a
SH		 2685 }
2686}
2687
fb17358f 2688static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2689{
fb17358f 2690 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2691}
2692
fb17358f 2693static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2694{
fb17358f 2695 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2696}
2697
fb17358f 2698
e3173832 2699static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2700{
b89165f2 2701 u8 t8;
cd28ab6a 2702
167f53d0 2703 /* Enable all clocks and check for bad PCI access */
b32f40c4 2704 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2705
cd28ab6a 2706 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2707
cd28ab6a 2708 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2709 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2710
2711 switch(hw->chip_id) {
2712 case CHIP_ID_YUKON_XL:
2713 hw->flags = SKY2_HW_GIGABIT
e0c28116
SH		 2714 | SKY2_HW_NEWER_PHY;
2715 if (hw->chip_rev < 3)
2716 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2717
ea76e635
SH		 2718 break;
2719
2720 case CHIP_ID_YUKON_EC_U:
2721 hw->flags = SKY2_HW_GIGABIT
2722 | SKY2_HW_NEWER_PHY
2723 | SKY2_HW_ADV_POWER_CTL;
2724 break;
2725
2726 case CHIP_ID_YUKON_EX:
2727 hw->flags = SKY2_HW_GIGABIT
2728 | SKY2_HW_NEWER_PHY
2729 | SKY2_HW_NEW_LE
2730 | SKY2_HW_ADV_POWER_CTL;
2731
2732 /* New transmit checksum */
2733 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2734 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2735 break;
2736
2737 case CHIP_ID_YUKON_EC:
2738 /* This rev is really old, and requires untested workarounds */
2739 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2740 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2741 return -EOPNOTSUPP;
2742 }
e0c28116 2743 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
ea76e635
SH		 2744 break;
2745
2746 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2747 break;
2748
05745c4a
SH		 2749 case CHIP_ID_YUKON_FE_P:
2750 hw->flags = SKY2_HW_NEWER_PHY
2751 | SKY2_HW_NEW_LE
2752 | SKY2_HW_AUTO_TX_SUM
2753 | SKY2_HW_ADV_POWER_CTL;
2754 break;
ea76e635 2755 default:
b02a9258
SH		 2756 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2757 hw->chip_id);
cd28ab6a
SH		 2758 return -EOPNOTSUPP;
2759 }
2760
ea76e635
SH		 2761 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2762 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2763 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2764
290d4de5 2765
e3173832
SH		 2766 hw->ports = 1;
2767 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2768 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2769 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2770 ++hw->ports;
2771 }
2772
2773 return 0;
2774}
2775
2776static void sky2_reset(struct sky2_hw *hw)
2777{
555382cb 2778 struct pci_dev *pdev = hw->pdev;
e3173832 2779 u16 status;
555382cb
SH		 2780 int i, cap;
2781 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2782
cd28ab6a 2783 /* disable ASF */
4f44d8ba
SH		 2784 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2785 status = sky2_read16(hw, HCU_CCSR);
2786 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2787 HCU_CCSR_UC_STATE_MSK);
2788 sky2_write16(hw, HCU_CCSR, status);
2789 } else
2790 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2791 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2792
2793 /* do a SW reset */
2794 sky2_write8(hw, B0_CTST, CS_RST_SET);
2795 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2796
ac93a394
SH		 2797 /* allow writes to PCI config */
2798 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2799
cd28ab6a 2800 /* clear PCI errors, if any */
b32f40c4 2801 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2802 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2803 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2804
2805 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2806
555382cb
SH		 2807 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2808 if (cap) {
cf06ffb4
SH		 2809 if (pci_find_aer_capability(pdev)) {
2810 /* Check for advanced error reporting */
2811 pci_cleanup_aer_uncorrect_error_status(pdev);
2812 pci_cleanup_aer_correct_error_status(pdev);
2813 } else {
2814 dev_warn(&pdev->dev,
2815 "PCI Express Advanced Error Reporting"
2816 " not configured or MMCONFIG problem?\n");
2817
2818 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2819 0xfffffffful);
2820 }
555382cb
SH		 2821
2822 /* If error bit is stuck on ignore it */
2823 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2824 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7bd656d1 2825
555382cb
SH		 2826 else if (pci_enable_pcie_error_reporting(pdev))
2827 hwe_mask |= Y2_IS_PCI_EXP;
2828 }
cd28ab6a 2829
ae306cca 2830 sky2_power_on(hw);
cd28ab6a
SH		 2831
2832 for (i = 0; i < hw->ports; i++) {
2833 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2834 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2835
2836 if (hw->chip_id == CHIP_ID_YUKON_EX)
2837 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2838 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2839 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2840 }
2841
793b883e
SH		 2842 /* Clear I2C IRQ noise */
2843 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2844
2845 /* turn off hardware timer (unused) */
2846 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2847 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2848
cd28ab6a
SH		 2849 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2850
69634ee7
SH		 2851 /* Turn off descriptor polling */
2852 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2853
2854 /* Turn off receive timestamp */
2855 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2856 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2857
2858 /* enable the Tx Arbiters */
2859 for (i = 0; i < hw->ports; i++)
2860 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2861
2862 /* Initialize ram interface */
2863 for (i = 0; i < hw->ports; i++) {
793b883e 2864 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2865
2866 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2867 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2868 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2869 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2870 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2871 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2872 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2873 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2874 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2875 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2876 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2877 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2878 }
2879
555382cb 2880 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2881
cd28ab6a 2882 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2883 sky2_gmac_reset(hw, i);
cd28ab6a 2884
cd28ab6a
SH		 2885 memset(hw->st_le, 0, STATUS_LE_BYTES);
2886 hw->st_idx = 0;
2887
2888 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2889 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2890
2891 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2892 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2893
2894 /* Set the list last index */
793b883e 2895 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2896
290d4de5
SH		 2897 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2898 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2899
290d4de5
SH		 2900 /* set Status-FIFO ISR watermark */
2901 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2902 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2903 else
2904 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2905
290d4de5 2906 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2907 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2908 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2909
793b883e 2910 /* enable status unit */
cd28ab6a
SH		 2911 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2912
2913 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2914 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2915 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2916}
2917
81906791
SH		 2918static void sky2_restart(struct work_struct *work)
2919{
2920 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2921 struct net_device *dev;
2922 int i, err;
2923
81906791
SH		 2924 rtnl_lock();
2925 sky2_write32(hw, B0_IMSK, 0);
2926 sky2_read32(hw, B0_IMSK);
6de16237 2927 napi_disable(&hw->napi);
81906791 2928
81906791
SH		 2929 for (i = 0; i < hw->ports; i++) {
2930 dev = hw->dev[i];
2931 if (netif_running(dev))
2932 sky2_down(dev);
2933 }
2934
2935 sky2_reset(hw);
2936 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2937 napi_enable(&hw->napi);
81906791
SH		 2938
2939 for (i = 0; i < hw->ports; i++) {
2940 dev = hw->dev[i];
2941 if (netif_running(dev)) {
2942 err = sky2_up(dev);
2943 if (err) {
2944 printk(KERN_INFO PFX "%s: could not restart %d\n",
2945 dev->name, err);
2946 dev_close(dev);
2947 }
2948 }
2949 }
2950
81906791
SH		 2951 rtnl_unlock();
2952}
2953
e3173832
SH		 2954static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2955{
2956 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2957}
2958
2959static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2960{
2961 const struct sky2_port *sky2 = netdev_priv(dev);
2962
2963 wol->supported = sky2_wol_supported(sky2->hw);
2964 wol->wolopts = sky2->wol;
2965}
2966
2967static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2968{
2969 struct sky2_port *sky2 = netdev_priv(dev);
2970 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2971
e3173832
SH		 2972 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2973 return -EOPNOTSUPP;
2974
2975 sky2->wol = wol->wolopts;
2976
05745c4a
SH		 2977 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2978 hw->chip_id == CHIP_ID_YUKON_EX ||
2979 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2980 sky2_write32(hw, B0_CTST, sky2->wol
2981 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2982
2983 if (!netif_running(dev))
2984 sky2_wol_init(sky2);
cd28ab6a
SH		 2985 return 0;
2986}
2987
28bd181a 2988static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2989{
b89165f2
SH		 2990 if (sky2_is_copper(hw)) {
2991 u32 modes = SUPPORTED_10baseT_Half
2992 | SUPPORTED_10baseT_Full
2993 | SUPPORTED_100baseT_Half
2994 | SUPPORTED_100baseT_Full
2995 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2996
ea76e635 2997 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 2998 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2999 | SUPPORTED_1000baseT_Full;
3000 return modes;
cd28ab6a 3001 } else
b89165f2
SH		 3002 return SUPPORTED_1000baseT_Half
3003 | SUPPORTED_1000baseT_Full
3004 | SUPPORTED_Autoneg
3005 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3006}
3007
793b883e 3008static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3009{
3010 struct sky2_port *sky2 = netdev_priv(dev);
3011 struct sky2_hw *hw = sky2->hw;
3012
3013 ecmd->transceiver = XCVR_INTERNAL;
3014 ecmd->supported = sky2_supported_modes(hw);
3015 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3016 if (sky2_is_copper(hw)) {
cd28ab6a 3017 ecmd->port = PORT_TP;
b89165f2
SH		 3018 ecmd->speed = sky2->speed;
3019 } else {
3020 ecmd->speed = SPEED_1000;
cd28ab6a 3021 ecmd->port = PORT_FIBRE;
b89165f2 3022 }
cd28ab6a
SH		 3023
3024 ecmd->advertising = sky2->advertising;
3025 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3026 ecmd->duplex = sky2->duplex;
3027 return 0;
3028}
3029
3030static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3031{
3032 struct sky2_port *sky2 = netdev_priv(dev);
3033 const struct sky2_hw *hw = sky2->hw;
3034 u32 supported = sky2_supported_modes(hw);
3035
3036 if (ecmd->autoneg == AUTONEG_ENABLE) {
3037 ecmd->advertising = supported;
3038 sky2->duplex = -1;
3039 sky2->speed = -1;
3040 } else {
3041 u32 setting;
3042
793b883e 3043 switch (ecmd->speed) {
cd28ab6a
SH		 3044 case SPEED_1000:
3045 if (ecmd->duplex == DUPLEX_FULL)
3046 setting = SUPPORTED_1000baseT_Full;
3047 else if (ecmd->duplex == DUPLEX_HALF)
3048 setting = SUPPORTED_1000baseT_Half;
3049 else
3050 return -EINVAL;
3051 break;
3052 case SPEED_100:
3053 if (ecmd->duplex == DUPLEX_FULL)
3054 setting = SUPPORTED_100baseT_Full;
3055 else if (ecmd->duplex == DUPLEX_HALF)
3056 setting = SUPPORTED_100baseT_Half;
3057 else
3058 return -EINVAL;
3059 break;
3060
3061 case SPEED_10:
3062 if (ecmd->duplex == DUPLEX_FULL)
3063 setting = SUPPORTED_10baseT_Full;
3064 else if (ecmd->duplex == DUPLEX_HALF)
3065 setting = SUPPORTED_10baseT_Half;
3066 else
3067 return -EINVAL;
3068 break;
3069 default:
3070 return -EINVAL;
3071 }
3072
3073 if ((setting & supported) == 0)
3074 return -EINVAL;
3075
3076 sky2->speed = ecmd->speed;
3077 sky2->duplex = ecmd->duplex;
3078 }
3079
3080 sky2->autoneg = ecmd->autoneg;
3081 sky2->advertising = ecmd->advertising;
3082
d1b139c0 3083 if (netif_running(dev)) {
1b537565 3084 sky2_phy_reinit(sky2);
d1b139c0
SH		 3085 sky2_set_multicast(dev);
3086 }
cd28ab6a
SH		 3087
3088 return 0;
3089}
3090
3091static void sky2_get_drvinfo(struct net_device *dev,
3092 struct ethtool_drvinfo *info)
3093{
3094 struct sky2_port *sky2 = netdev_priv(dev);
3095
3096 strcpy(info->driver, DRV_NAME);
3097 strcpy(info->version, DRV_VERSION);
3098 strcpy(info->fw_version, "N/A");
3099 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3100}
3101
3102static const struct sky2_stat {
793b883e
SH		 3103 char name[ETH_GSTRING_LEN];
3104 u16 offset;
cd28ab6a
SH		 3105} sky2_stats[] = {
3106 { "tx_bytes", GM_TXO_OK_HI },
3107 { "rx_bytes", GM_RXO_OK_HI },
3108 { "tx_broadcast", GM_TXF_BC_OK },
3109 { "rx_broadcast", GM_RXF_BC_OK },
3110 { "tx_multicast", GM_TXF_MC_OK },
3111 { "rx_multicast", GM_RXF_MC_OK },
3112 { "tx_unicast", GM_TXF_UC_OK },
3113 { "rx_unicast", GM_RXF_UC_OK },
3114 { "tx_mac_pause", GM_TXF_MPAUSE },
3115 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3116 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3117 { "late_collision",GM_TXF_LAT_COL },
3118 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3119 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3120 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3121
d2604540 3122 { "rx_short", GM_RXF_SHT },
cd28ab6a 3123 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3124 { "rx_64_byte_packets", GM_RXF_64B },
3125 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3126 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3127 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3128 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3129 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3130 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3131 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3132 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3133 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3134 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3135
3136 { "tx_64_byte_packets", GM_TXF_64B },
3137 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3138 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3139 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3140 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3141 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3142 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3143 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3144};
3145
cd28ab6a
SH		 3146static u32 sky2_get_rx_csum(struct net_device *dev)
3147{
3148 struct sky2_port *sky2 = netdev_priv(dev);
3149
3150 return sky2->rx_csum;
3151}
3152
3153static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3154{
3155 struct sky2_port *sky2 = netdev_priv(dev);
3156
3157 sky2->rx_csum = data;
793b883e 3158
cd28ab6a
SH		 3159 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3160 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3161
3162 return 0;
3163}
3164
3165static u32 sky2_get_msglevel(struct net_device *netdev)
3166{
3167 struct sky2_port *sky2 = netdev_priv(netdev);
3168 return sky2->msg_enable;
3169}
3170
9a7ae0a9
SH		 3171static int sky2_nway_reset(struct net_device *dev)
3172{
3173 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3174
16ad91e1 3175 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3176 return -EINVAL;
3177
1b537565 3178 sky2_phy_reinit(sky2);
d1b139c0 3179 sky2_set_multicast(dev);
9a7ae0a9
SH		 3180
3181 return 0;
3182}
3183
793b883e 3184static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3185{
3186 struct sky2_hw *hw = sky2->hw;
3187 unsigned port = sky2->port;
3188 int i;
3189
3190 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3191 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3192 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3193 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3194
793b883e 3195 for (i = 2; i < count; i++)
cd28ab6a
SH		 3196 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3197}
3198
cd28ab6a
SH		 3199static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3200{
3201 struct sky2_port *sky2 = netdev_priv(netdev);
3202 sky2->msg_enable = value;
3203}
3204
b9f2c044 3205static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3206{
b9f2c044
JG		 3207 switch (sset) {
3208 case ETH_SS_STATS:
3209 return ARRAY_SIZE(sky2_stats);
3210 default:
3211 return -EOPNOTSUPP;
3212 }
cd28ab6a
SH		 3213}
3214
3215static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3216 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3217{
3218 struct sky2_port *sky2 = netdev_priv(dev);
3219
793b883e 3220 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3221}
3222
793b883e 3223static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3224{
3225 int i;
3226
3227 switch (stringset) {
3228 case ETH_SS_STATS:
3229 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3230 memcpy(data + i * ETH_GSTRING_LEN,
3231 sky2_stats[i].name, ETH_GSTRING_LEN);
3232 break;
3233 }
3234}
3235
cd28ab6a
SH		 3236static int sky2_set_mac_address(struct net_device *dev, void *p)
3237{
3238 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3239 struct sky2_hw *hw = sky2->hw;
3240 unsigned port = sky2->port;
3241 const struct sockaddr *addr = p;
cd28ab6a
SH		 3242
3243 if (!is_valid_ether_addr(addr->sa_data))
3244 return -EADDRNOTAVAIL;
3245
cd28ab6a 3246 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3247 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3248 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3249 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3250 dev->dev_addr, ETH_ALEN);
1b537565 3251
a8ab1ec0
SH		 3252 /* virtual address for data */
3253 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3254
3255 /* physical address: used for pause frames */
3256 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3257
3258 return 0;
cd28ab6a
SH		 3259}
3260
a052b52f
SH		 3261static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3262{
3263 u32 bit;
3264
3265 bit = ether_crc(ETH_ALEN, addr) & 63;
3266 filter[bit >> 3] |= 1 << (bit & 7);
3267}
3268
cd28ab6a
SH		 3269static void sky2_set_multicast(struct net_device *dev)
3270{
3271 struct sky2_port *sky2 = netdev_priv(dev);
3272 struct sky2_hw *hw = sky2->hw;
3273 unsigned port = sky2->port;
3274 struct dev_mc_list *list = dev->mc_list;
3275 u16 reg;
3276 u8 filter[8];
a052b52f
SH		 3277 int rx_pause;
3278 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3279
a052b52f 3280 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3281 memset(filter, 0, sizeof(filter));
3282
3283 reg = gma_read16(hw, port, GM_RX_CTRL);
3284 reg |= GM_RXCR_UCF_ENA;
3285
d571b694 3286 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3287 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3288 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3289 memset(filter, 0xff, sizeof(filter));
a052b52f 3290 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3291 reg &= ~GM_RXCR_MCF_ENA;
3292 else {
3293 int i;
3294 reg |= GM_RXCR_MCF_ENA;
3295
a052b52f
SH		 3296 if (rx_pause)
3297 sky2_add_filter(filter, pause_mc_addr);
3298
3299 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3300 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3301 }
3302
cd28ab6a 3303 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3304 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3305 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3306 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3307 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3308 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3309 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3310 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3311
3312 gma_write16(hw, port, GM_RX_CTRL, reg);
3313}
3314
3315/* Can have one global because blinking is controlled by
3316 * ethtool and that is always under RTNL mutex
3317 */
91c86df5 3318static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3319{
793b883e
SH		 3320 u16 pg;
3321
793b883e
SH		 3322 switch (hw->chip_id) {
3323 case CHIP_ID_YUKON_XL:
3324 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3325 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3326 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3327 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3328 PHY_M_LEDC_INIT_CTRL(7) |
3329 PHY_M_LEDC_STA1_CTRL(7) |
3330 PHY_M_LEDC_STA0_CTRL(7))
3331 : 0);
3332
3333 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3334 break;
3335
3336 default:
3337 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3338 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3339 on ? PHY_M_LED_ALL : 0);
793b883e 3340 }
cd28ab6a
SH		 3341}
3342
3343/* blink LED's for finding board */
3344static int sky2_phys_id(struct net_device *dev, u32 data)
3345{
3346 struct sky2_port *sky2 = netdev_priv(dev);
3347 struct sky2_hw *hw = sky2->hw;
3348 unsigned port = sky2->port;
793b883e 3349 u16 ledctrl, ledover = 0;
cd28ab6a 3350 long ms;
91c86df5 3351 int interrupted;
cd28ab6a
SH		 3352 int onoff = 1;
3353
793b883e 3354 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3355 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3356 else
3357 ms = data * 1000;
3358
3359 /* save initial values */
e07b1aa8 3360 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3361 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3362 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3363 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3364 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3366 } else {
3367 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3368 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3369 }
cd28ab6a 3370
91c86df5
SH		 3371 interrupted = 0;
3372 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3373 sky2_led(hw, port, onoff);
3374 onoff = !onoff;
3375
e07b1aa8 3376 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3377 interrupted = msleep_interruptible(250);
e07b1aa8 3378 spin_lock_bh(&sky2->phy_lock);
91c86df5 3379
cd28ab6a
SH		 3380 ms -= 250;
3381 }
3382
3383 /* resume regularly scheduled programming */
793b883e
SH		 3384 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3385 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3386 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3387 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3388 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3389 } else {
3390 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3391 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3392 }
e07b1aa8 3393 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3394
3395 return 0;
3396}
3397
3398static void sky2_get_pauseparam(struct net_device *dev,
3399 struct ethtool_pauseparam *ecmd)
3400{
3401 struct sky2_port *sky2 = netdev_priv(dev);
3402
16ad91e1
SH		 3403 switch (sky2->flow_mode) {
3404 case FC_NONE:
3405 ecmd->tx_pause = ecmd->rx_pause = 0;
3406 break;
3407 case FC_TX:
3408 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3409 break;
3410 case FC_RX:
3411 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3412 break;
3413 case FC_BOTH:
3414 ecmd->tx_pause = ecmd->rx_pause = 1;
3415 }
3416
cd28ab6a
SH		 3417 ecmd->autoneg = sky2->autoneg;
3418}
3419
3420static int sky2_set_pauseparam(struct net_device *dev,
3421 struct ethtool_pauseparam *ecmd)
3422{
3423 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3424
3425 sky2->autoneg = ecmd->autoneg;
16ad91e1 3426 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3427
16ad91e1
SH		 3428 if (netif_running(dev))
3429 sky2_phy_reinit(sky2);
cd28ab6a 3430
2eaba1a2 3431 return 0;
cd28ab6a
SH		 3432}
3433
fb17358f
SH		 3434static int sky2_get_coalesce(struct net_device *dev,
3435 struct ethtool_coalesce *ecmd)
3436{
3437 struct sky2_port *sky2 = netdev_priv(dev);
3438 struct sky2_hw *hw = sky2->hw;
3439
3440 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3441 ecmd->tx_coalesce_usecs = 0;
3442 else {
3443 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3444 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3445 }
3446 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3447
3448 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3449 ecmd->rx_coalesce_usecs = 0;
3450 else {
3451 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3452 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3453 }
3454 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3455
3456 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3457 ecmd->rx_coalesce_usecs_irq = 0;
3458 else {
3459 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3460 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3461 }
3462
3463 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3464
3465 return 0;
3466}
3467
3468/* Note: this affect both ports */
3469static int sky2_set_coalesce(struct net_device *dev,
3470 struct ethtool_coalesce *ecmd)
3471{
3472 struct sky2_port *sky2 = netdev_priv(dev);
3473 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3474 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3475
77b3d6a2
SH		 3476 if (ecmd->tx_coalesce_usecs > tmax ||
3477 ecmd->rx_coalesce_usecs > tmax ||
3478 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3479 return -EINVAL;
3480
ff81fbbe 3481 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3482 return -EINVAL;
ff81fbbe 3483 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3484 return -EINVAL;
ff81fbbe 3485 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3486 return -EINVAL;
3487
3488 if (ecmd->tx_coalesce_usecs == 0)
3489 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3490 else {
3491 sky2_write32(hw, STAT_TX_TIMER_INI,
3492 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3493 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3494 }
3495 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3496
3497 if (ecmd->rx_coalesce_usecs == 0)
3498 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3499 else {
3500 sky2_write32(hw, STAT_LEV_TIMER_INI,
3501 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3502 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3503 }
3504 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3505
3506 if (ecmd->rx_coalesce_usecs_irq == 0)
3507 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3508 else {
d28d4870 3509 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3510 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3511 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3512 }
3513 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3514 return 0;
3515}
3516
793b883e
SH		 3517static void sky2_get_ringparam(struct net_device *dev,
3518 struct ethtool_ringparam *ering)
3519{
3520 struct sky2_port *sky2 = netdev_priv(dev);
3521
3522 ering->rx_max_pending = RX_MAX_PENDING;
3523 ering->rx_mini_max_pending = 0;
3524 ering->rx_jumbo_max_pending = 0;
3525 ering->tx_max_pending = TX_RING_SIZE - 1;
3526
3527 ering->rx_pending = sky2->rx_pending;
3528 ering->rx_mini_pending = 0;
3529 ering->rx_jumbo_pending = 0;
3530 ering->tx_pending = sky2->tx_pending;
3531}
3532
3533static int sky2_set_ringparam(struct net_device *dev,
3534 struct ethtool_ringparam *ering)
3535{
3536 struct sky2_port *sky2 = netdev_priv(dev);
3537 int err = 0;
3538
3539 if (ering->rx_pending > RX_MAX_PENDING ||
3540 ering->rx_pending < 8 ||
3541 ering->tx_pending < MAX_SKB_TX_LE ||
3542 ering->tx_pending > TX_RING_SIZE - 1)
3543 return -EINVAL;
3544
3545 if (netif_running(dev))
3546 sky2_down(dev);
3547
3548 sky2->rx_pending = ering->rx_pending;
3549 sky2->tx_pending = ering->tx_pending;
3550
1b537565 3551 if (netif_running(dev)) {
793b883e 3552 err = sky2_up(dev);
1b537565
SH		 3553 if (err)
3554 dev_close(dev);
6ed995bb
SH		 3555 else
3556 sky2_set_multicast(dev);
1b537565 3557 }
793b883e
SH		 3558
3559 return err;
3560}
3561
793b883e
SH		 3562static int sky2_get_regs_len(struct net_device *dev)
3563{
6e4cbb34 3564 return 0x4000;
793b883e
SH		 3565}
3566
3567/*
3568 * Returns copy of control register region
3ead5db7 3569 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3570 */
3571static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3572 void *p)
3573{
3574 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3575 const void __iomem *io = sky2->hw->regs;
295b54c4 3576 unsigned int b;
793b883e
SH		 3577
3578 regs->version = 1;
793b883e 3579
295b54c4
SH		 3580 for (b = 0; b < 128; b++) {
3581 /* This complicated switch statement is to make sure and
3582 * only access regions that are unreserved.
3583 * Some blocks are only valid on dual port cards.
3584 * and block 3 has some special diagnostic registers that
3585 * are poison.
3586 */
3587 switch (b) {
3588 case 3:
3589 /* skip diagnostic ram region */
3590 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3591 break;
3ead5db7 3592
295b54c4
SH		 3593 /* dual port cards only */
3594 case 5: /* Tx Arbiter 2 */
3595 case 9: /* RX2 */
3596 case 14 ... 15: /* TX2 */
3597 case 17: case 19: /* Ram Buffer 2 */
3598 case 22 ... 23: /* Tx Ram Buffer 2 */
3599 case 25: /* Rx MAC Fifo 1 */
3600 case 27: /* Tx MAC Fifo 2 */
3601 case 31: /* GPHY 2 */
3602 case 40 ... 47: /* Pattern Ram 2 */
3603 case 52: case 54: /* TCP Segmentation 2 */
3604 case 112 ... 116: /* GMAC 2 */
3605 if (sky2->hw->ports == 1)
3606 goto reserved;
3607 /* fall through */
3608 case 0: /* Control */
3609 case 2: /* Mac address */
3610 case 4: /* Tx Arbiter 1 */
3611 case 7: /* PCI express reg */
3612 case 8: /* RX1 */
3613 case 12 ... 13: /* TX1 */
3614 case 16: case 18:/* Rx Ram Buffer 1 */
3615 case 20 ... 21: /* Tx Ram Buffer 1 */
3616 case 24: /* Rx MAC Fifo 1 */
3617 case 26: /* Tx MAC Fifo 1 */
3618 case 28 ... 29: /* Descriptor and status unit */
3619 case 30: /* GPHY 1*/
3620 case 32 ... 39: /* Pattern Ram 1 */
3621 case 48: case 50: /* TCP Segmentation 1 */
3622 case 56 ... 60: /* PCI space */
3623 case 80 ... 84: /* GMAC 1 */
3624 memcpy_fromio(p, io, 128);
3625 break;
3626 default:
3627reserved:
3628 memset(p, 0, 128);
3629 }
3ead5db7 3630
295b54c4
SH		 3631 p += 128;
3632 io += 128;
3633 }
793b883e 3634}
cd28ab6a 3635
b628ed98
SH		 3636/* In order to do Jumbo packets on these chips, need to turn off the
3637 * transmit store/forward. Therefore checksum offload won't work.
3638 */
3639static int no_tx_offload(struct net_device *dev)
3640{
3641 const struct sky2_port *sky2 = netdev_priv(dev);
3642 const struct sky2_hw *hw = sky2->hw;
3643
69161611 3644 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3645}
3646
3647static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3648{
3649 if (data && no_tx_offload(dev))
3650 return -EINVAL;
3651
3652 return ethtool_op_set_tx_csum(dev, data);
3653}
3654
3655
3656static int sky2_set_tso(struct net_device *dev, u32 data)
3657{
3658 if (data && no_tx_offload(dev))
3659 return -EINVAL;
3660
3661 return ethtool_op_set_tso(dev, data);
3662}
3663
f4331a6d
SH		 3664static int sky2_get_eeprom_len(struct net_device *dev)
3665{
3666 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3667 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3668 u16 reg2;
3669
b32f40c4 3670 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3671 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3672}
3673
b32f40c4 3674static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3675{
167f53d0 3676 u32 val;
f4331a6d 3677
b32f40c4 3678 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3679
3680 do {
b32f40c4 3681 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3682 } while (!(offset & PCI_VPD_ADDR_F));
3683
b32f40c4 3684 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3685 return val;
f4331a6d
SH		 3686}
3687
b32f40c4 3688static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3689{
b32f40c4
SH		 3690 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3691 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3692 do {
b32f40c4 3693 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3694 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3695}
3696
3697static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3698 u8 *data)
3699{
3700 struct sky2_port *sky2 = netdev_priv(dev);
3701 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3702 int length = eeprom->len;
3703 u16 offset = eeprom->offset;
3704
3705 if (!cap)
3706 return -EINVAL;
3707
3708 eeprom->magic = SKY2_EEPROM_MAGIC;
3709
3710 while (length > 0) {
b32f40c4 3711 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3712 int n = min_t(int, length, sizeof(val));
3713
3714 memcpy(data, &val, n);
3715 length -= n;
3716 data += n;
3717 offset += n;
3718 }
3719 return 0;
3720}
3721
3722static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3723 u8 *data)
3724{
3725 struct sky2_port *sky2 = netdev_priv(dev);
3726 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3727 int length = eeprom->len;
3728 u16 offset = eeprom->offset;
3729
3730 if (!cap)
3731 return -EINVAL;
3732
3733 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3734 return -EINVAL;
3735
3736 while (length > 0) {
3737 u32 val;
3738 int n = min_t(int, length, sizeof(val));
3739
3740 if (n < sizeof(val))
b32f40c4 3741 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3742 memcpy(&val, data, n);
3743
b32f40c4 3744 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3745
3746 length -= n;
3747 data += n;
3748 offset += n;
3749 }
3750 return 0;
3751}
3752
3753
7282d491 3754static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3755 .get_settings = sky2_get_settings,
3756 .set_settings = sky2_set_settings,
3757 .get_drvinfo = sky2_get_drvinfo,
3758 .get_wol = sky2_get_wol,
3759 .set_wol = sky2_set_wol,
3760 .get_msglevel = sky2_get_msglevel,
3761 .set_msglevel = sky2_set_msglevel,
3762 .nway_reset = sky2_nway_reset,
3763 .get_regs_len = sky2_get_regs_len,
3764 .get_regs = sky2_get_regs,
3765 .get_link = ethtool_op_get_link,
3766 .get_eeprom_len = sky2_get_eeprom_len,
3767 .get_eeprom = sky2_get_eeprom,
3768 .set_eeprom = sky2_set_eeprom,
f4331a6d 3769 .set_sg = ethtool_op_set_sg,
f4331a6d 3770 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3771 .set_tso = sky2_set_tso,
3772 .get_rx_csum = sky2_get_rx_csum,
3773 .set_rx_csum = sky2_set_rx_csum,
3774 .get_strings = sky2_get_strings,
3775 .get_coalesce = sky2_get_coalesce,
3776 .set_coalesce = sky2_set_coalesce,
3777 .get_ringparam = sky2_get_ringparam,
3778 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3779 .get_pauseparam = sky2_get_pauseparam,
3780 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3781 .phys_id = sky2_phys_id,
b9f2c044 3782 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3783 .get_ethtool_stats = sky2_get_ethtool_stats,
3784};
3785
3cf26753
SH		 3786#ifdef CONFIG_SKY2_DEBUG
3787
3788static struct dentry *sky2_debug;
3789
3790static int sky2_debug_show(struct seq_file *seq, void *v)
3791{
3792 struct net_device *dev = seq->private;
3793 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3794 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3795 unsigned port = sky2->port;
3796 unsigned idx, last;
3797 int sop;
3798
3799 if (!netif_running(dev))
3800 return -ENETDOWN;
3801
3802 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3803 sky2_read32(hw, B0_ISRC),
3804 sky2_read32(hw, B0_IMSK),
3805 sky2_read32(hw, B0_Y2_SP_ICR));
3806
bea3348e 3807 napi_disable(&hw->napi);
3cf26753
SH		 3808 last = sky2_read16(hw, STAT_PUT_IDX);
3809
3810 if (hw->st_idx == last)
3811 seq_puts(seq, "Status ring (empty)\n");
3812 else {
3813 seq_puts(seq, "Status ring\n");
3814 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3815 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3816 const struct sky2_status_le *le = hw->st_le + idx;
3817 seq_printf(seq, "[%d] %#x %d %#x\n",
3818 idx, le->opcode, le->length, le->status);
3819 }
3820 seq_puts(seq, "\n");
3821 }
3822
3823 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3824 sky2->tx_cons, sky2->tx_prod,
3825 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3826 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3827
3828 /* Dump contents of tx ring */
3829 sop = 1;
3830 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3831 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3832 const struct sky2_tx_le *le = sky2->tx_le + idx;
3833 u32 a = le32_to_cpu(le->addr);
3834
3835 if (sop)
3836 seq_printf(seq, "%u:", idx);
3837 sop = 0;
3838
3839 switch(le->opcode & ~HW_OWNER) {
3840 case OP_ADDR64:
3841 seq_printf(seq, " %#x:", a);
3842 break;
3843 case OP_LRGLEN:
3844 seq_printf(seq, " mtu=%d", a);
3845 break;
3846 case OP_VLAN:
3847 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3848 break;
3849 case OP_TCPLISW:
3850 seq_printf(seq, " csum=%#x", a);
3851 break;
3852 case OP_LARGESEND:
3853 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3854 break;
3855 case OP_PACKET:
3856 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3857 break;
3858 case OP_BUFFER:
3859 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3860 break;
3861 default:
3862 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3863 a, le16_to_cpu(le->length));
3864 }
3865
3866 if (le->ctrl & EOP) {
3867 seq_putc(seq, '\n');
3868 sop = 1;
3869 }
3870 }
3871
3872 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3873 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3874 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3875 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3876
bea3348e 3877 napi_enable(&hw->napi);
3cf26753
SH		 3878 return 0;
3879}
3880
3881static int sky2_debug_open(struct inode *inode, struct file *file)
3882{
3883 return single_open(file, sky2_debug_show, inode->i_private);
3884}
3885
3886static const struct file_operations sky2_debug_fops = {
3887 .owner = THIS_MODULE,
3888 .open = sky2_debug_open,
3889 .read = seq_read,
3890 .llseek = seq_lseek,
3891 .release = single_release,
3892};
3893
3894/*
3895 * Use network device events to create/remove/rename
3896 * debugfs file entries
3897 */
3898static int sky2_device_event(struct notifier_block *unused,
3899 unsigned long event, void *ptr)
3900{
3901 struct net_device *dev = ptr;
5b296bc9 3902 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3903
5b296bc9
SH		 3904 if (dev->open != sky2_up || !sky2_debug)
3905 return NOTIFY_DONE;
3cf26753 3906
5b296bc9
SH		 3907 switch(event) {
3908 case NETDEV_CHANGENAME:
3909 if (sky2->debugfs) {
3910 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3911 sky2_debug, dev->name);
3912 }
3913 break;
3cf26753 3914
5b296bc9
SH		 3915 case NETDEV_GOING_DOWN:
3916 if (sky2->debugfs) {
3917 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3918 dev->name);
3919 debugfs_remove(sky2->debugfs);
3920 sky2->debugfs = NULL;
3cf26753 3921 }
5b296bc9
SH		 3922 break;
3923
3924 case NETDEV_UP:
3925 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3926 sky2_debug, dev,
3927 &sky2_debug_fops);
3928 if (IS_ERR(sky2->debugfs))
3929 sky2->debugfs = NULL;
3cf26753
SH		 3930 }
3931
3932 return NOTIFY_DONE;
3933}
3934
3935static struct notifier_block sky2_notifier = {
3936 .notifier_call = sky2_device_event,
3937};
3938
3939
3940static __init void sky2_debug_init(void)
3941{
3942 struct dentry *ent;
3943
3944 ent = debugfs_create_dir("sky2", NULL);
3945 if (!ent || IS_ERR(ent))
3946 return;
3947
3948 sky2_debug = ent;
3949 register_netdevice_notifier(&sky2_notifier);
3950}
3951
3952static __exit void sky2_debug_cleanup(void)
3953{
3954 if (sky2_debug) {
3955 unregister_netdevice_notifier(&sky2_notifier);
3956 debugfs_remove(sky2_debug);
3957 sky2_debug = NULL;
3958 }
3959}
3960
3961#else
3962#define sky2_debug_init()
3963#define sky2_debug_cleanup()
3964#endif
3965
3966
cd28ab6a
SH		 3967/* Initialize network device */
3968static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3969 unsigned port,
3970 int highmem, int wol)
cd28ab6a
SH		 3971{
3972 struct sky2_port *sky2;
3973 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3974
3975 if (!dev) {
898eb71c 3976 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 3977 return NULL;
3978 }
3979
cd28ab6a 3980 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3981 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3982 dev->open = sky2_up;
3983 dev->stop = sky2_down;
ef743d33 3984 dev->do_ioctl = sky2_ioctl;
cd28ab6a 3985 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 3986 dev->set_multicast_list = sky2_set_multicast;
3987 dev->set_mac_address = sky2_set_mac_address;
3988 dev->change_mtu = sky2_change_mtu;
3989 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3990 dev->tx_timeout = sky2_tx_timeout;
3991 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 3992#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 3993 if (port == 0)
3994 dev->poll_controller = sky2_netpoll;
cd28ab6a 3995#endif
cd28ab6a
SH		 3996
3997 sky2 = netdev_priv(dev);
3998 sky2->netdev = dev;
3999 sky2->hw = hw;
4000 sky2->msg_enable = netif_msg_init(debug, default_msg);
4001
cd28ab6a
SH		 4002 /* Auto speed and flow control */
4003 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4004 sky2->flow_mode = FC_BOTH;
4005
cd28ab6a
SH		 4006 sky2->duplex = -1;
4007 sky2->speed = -1;
4008 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4009 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
e3173832 4010 sky2->wol = wol;
75d070c5 4011
e07b1aa8 4012 spin_lock_init(&sky2->phy_lock);
793b883e 4013 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4014 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4015
4016 hw->dev[port] = dev;
4017
4018 sky2->port = port;
4019
4a50a876 4020 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4021 if (highmem)
4022 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4023
d1f13708 4024#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4025 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4026 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4027 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4028 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4029 dev->vlan_rx_register = sky2_vlan_rx_register;
4030 }
d1f13708 4031#endif
4032
cd28ab6a 4033 /* read the mac address */
793b883e 4034 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4035 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4036
cd28ab6a
SH		 4037 return dev;
4038}
4039
28bd181a 4040static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4041{
4042 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4043 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4044
4045 if (netif_msg_probe(sky2))
0795af57
JP		 4046 printk(KERN_INFO PFX "%s: addr %s\n",
4047 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4048}
4049
fb2690a9 4050/* Handle software interrupt used during MSI test */
7d12e780 4051static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4052{
4053 struct sky2_hw *hw = dev_id;
4054 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4055
4056 if (status == 0)
4057 return IRQ_NONE;
4058
4059 if (status & Y2_IS_IRQ_SW) {
ea76e635 4060 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4061 wake_up(&hw->msi_wait);
4062 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4063 }
4064 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4065
4066 return IRQ_HANDLED;
4067}
4068
4069/* Test interrupt path by forcing a a software IRQ */
4070static int __devinit sky2_test_msi(struct sky2_hw *hw)
4071{
4072 struct pci_dev *pdev = hw->pdev;
4073 int err;
4074
bb507fe1 4075 init_waitqueue_head (&hw->msi_wait);
4076
fb2690a9
SH		 4077 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4078
b0a20ded 4079 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4080 if (err) {
b02a9258 4081 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4082 return err;
4083 }
4084
fb2690a9 4085 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4086 sky2_read8(hw, B0_CTST);
fb2690a9 4087
ea76e635 4088 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4089
ea76e635 4090 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4091 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4092 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4093 "switching to INTx mode.\n");
fb2690a9
SH		 4094
4095 err = -EOPNOTSUPP;
4096 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4097 }
4098
4099 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4100 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4101
4102 free_irq(pdev->irq, hw);
4103
4104 return err;
4105}
4106
e3173832
SH		 4107static int __devinit pci_wake_enabled(struct pci_dev *dev)
4108{
4109 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4110 u16 value;
4111
4112 if (!pm)
4113 return 0;
4114 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4115 return 0;
4116 return value & PCI_PM_CTRL_PME_ENABLE;
4117}
4118
cd28ab6a
SH		 4119static int __devinit sky2_probe(struct pci_dev *pdev,
4120 const struct pci_device_id *ent)
4121{
7f60c64b 4122 struct net_device *dev;
cd28ab6a 4123 struct sky2_hw *hw;
e3173832 4124 int err, using_dac = 0, wol_default;
cd28ab6a 4125
793b883e
SH		 4126 err = pci_enable_device(pdev);
4127 if (err) {
b02a9258 4128 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4129 goto err_out;
4130 }
4131
793b883e
SH		 4132 err = pci_request_regions(pdev, DRV_NAME);
4133 if (err) {
b02a9258 4134 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4135 goto err_out_disable;
cd28ab6a
SH		 4136 }
4137
4138 pci_set_master(pdev);
4139
d1f3d4dd
SH		 4140 if (sizeof(dma_addr_t) > sizeof(u32) &&
4141 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4142 using_dac = 1;
4143 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4144 if (err < 0) {
b02a9258
SH		 4145 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4146 "for consistent allocations\n");
d1f3d4dd
SH		 4147 goto err_out_free_regions;
4148 }
d1f3d4dd 4149 } else {
cd28ab6a
SH		 4150 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4151 if (err) {
b02a9258 4152 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4153 goto err_out_free_regions;
4154 }
4155 }
d1f3d4dd 4156
e3173832
SH		 4157 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4158
cd28ab6a 4159 err = -ENOMEM;
6aad85d6 4160 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4161 if (!hw) {
b02a9258 4162 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4163 goto err_out_free_regions;
4164 }
4165
cd28ab6a 4166 hw->pdev = pdev;
cd28ab6a
SH		 4167
4168 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4169 if (!hw->regs) {
b02a9258 4170 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4171 goto err_out_free_hw;
4172 }
4173
56a645cc 4174#ifdef __BIG_ENDIAN
f65b138c
SH		 4175 /* The sk98lin vendor driver uses hardware byte swapping but
4176 * this driver uses software swapping.
4177 */
56a645cc
SH		 4178 {
4179 u32 reg;
b32f40c4 4180 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4181 reg &= ~PCI_REV_DESC;
b32f40c4 4182 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4183 }
4184#endif
4185
08c06d8a 4186 /* ring for status responses */
167f53d0 4187 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4188 if (!hw->st_le)
4189 goto err_out_iounmap;
4190
e3173832 4191 err = sky2_init(hw);
cd28ab6a 4192 if (err)
793b883e 4193 goto err_out_iounmap;
cd28ab6a 4194
b02a9258 4195 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4196 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4197 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4198 hw->chip_id, hw->chip_rev);
cd28ab6a 4199
e3173832
SH		 4200 sky2_reset(hw);
4201
4202 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4203 if (!dev) {
4204 err = -ENOMEM;
cd28ab6a 4205 goto err_out_free_pci;
7f60c64b 4206 }
cd28ab6a 4207
9fa1b1f3
SH		 4208 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4209 err = sky2_test_msi(hw);
4210 if (err == -EOPNOTSUPP)
4211 pci_disable_msi(pdev);
4212 else if (err)
4213 goto err_out_free_netdev;
4214 }
4215
793b883e
SH		 4216 err = register_netdev(dev);
4217 if (err) {
b02a9258 4218 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4219 goto err_out_free_netdev;
4220 }
4221
6de16237
SH		 4222 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4223
ea76e635
SH		 4224 err = request_irq(pdev->irq, sky2_intr,
4225 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4226 dev->name, hw);
9fa1b1f3 4227 if (err) {
b02a9258 4228 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4229 goto err_out_unregister;
4230 }
4231 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4232 napi_enable(&hw->napi);
9fa1b1f3 4233
cd28ab6a
SH		 4234 sky2_show_addr(dev);
4235
7f60c64b 4236 if (hw->ports > 1) {
4237 struct net_device *dev1;
4238
e3173832 4239 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4240 if (!dev1)
4241 dev_warn(&pdev->dev, "allocation for second device failed\n");
4242 else if ((err = register_netdev(dev1))) {
4243 dev_warn(&pdev->dev,
4244 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4245 hw->dev[1] = NULL;
4246 free_netdev(dev1);
b02a9258
SH		 4247 } else
4248 sky2_show_addr(dev1);
cd28ab6a
SH		 4249 }
4250
32c2c300 4251 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4252 INIT_WORK(&hw->restart_work, sky2_restart);
4253
793b883e
SH		 4254 pci_set_drvdata(pdev, hw);
4255
cd28ab6a
SH		 4256 return 0;
4257
793b883e 4258err_out_unregister:
ea76e635 4259 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4260 pci_disable_msi(pdev);
793b883e 4261 unregister_netdev(dev);
cd28ab6a
SH		 4262err_out_free_netdev:
4263 free_netdev(dev);
cd28ab6a 4264err_out_free_pci:
793b883e 4265 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4266 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4267err_out_iounmap:
4268 iounmap(hw->regs);
4269err_out_free_hw:
4270 kfree(hw);
4271err_out_free_regions:
4272 pci_release_regions(pdev);
44a1d2e5 4273err_out_disable:
cd28ab6a 4274 pci_disable_device(pdev);
cd28ab6a 4275err_out:
549a68c3 4276 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4277 return err;
4278}
4279
4280static void __devexit sky2_remove(struct pci_dev *pdev)
4281{
793b883e 4282 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4283 int i;
cd28ab6a 4284
793b883e 4285 if (!hw)
cd28ab6a
SH		 4286 return;
4287
32c2c300 4288 del_timer_sync(&hw->watchdog_timer);
6de16237 4289 cancel_work_sync(&hw->restart_work);
d27ed387 4290
b877fe28 4291 for (i = hw->ports-1; i >= 0; --i)
6de16237 4292 unregister_netdev(hw->dev[i]);
81906791 4293
d27ed387 4294 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4295
ae306cca
SH		 4296 sky2_power_aux(hw);
4297
cd28ab6a 4298 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4299 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4300 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4301
4302 free_irq(pdev->irq, hw);
ea76e635 4303 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4304 pci_disable_msi(pdev);
793b883e 4305 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4306 pci_release_regions(pdev);
4307 pci_disable_device(pdev);
793b883e 4308
b877fe28 4309 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4310 free_netdev(hw->dev[i]);
4311
cd28ab6a
SH		 4312 iounmap(hw->regs);
4313 kfree(hw);
5afa0a9c 4314
cd28ab6a
SH		 4315 pci_set_drvdata(pdev, NULL);
4316}
4317
4318#ifdef CONFIG_PM
4319static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4320{
793b883e 4321 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4322 int i, wol = 0;
cd28ab6a 4323
549a68c3
SH		 4324 if (!hw)
4325 return 0;
4326
f05267e7 4327 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4328 struct net_device *dev = hw->dev[i];
e3173832 4329 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4330
e3173832 4331 if (netif_running(dev))
5afa0a9c 4332 sky2_down(dev);
e3173832
SH		 4333
4334 if (sky2->wol)
4335 sky2_wol_init(sky2);
4336
4337 wol |= sky2->wol;
cd28ab6a
SH		 4338 }
4339
8ab8fca2 4340 sky2_write32(hw, B0_IMSK, 0);
6de16237 4341 napi_disable(&hw->napi);
ae306cca 4342 sky2_power_aux(hw);
e3173832 4343
d374c1c1 4344 pci_save_state(pdev);
e3173832 4345 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4346 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4347
2ccc99b7 4348 return 0;
cd28ab6a
SH		 4349}
4350
4351static int sky2_resume(struct pci_dev *pdev)
4352{
793b883e 4353 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4354 int i, err;
cd28ab6a 4355
549a68c3
SH		 4356 if (!hw)
4357 return 0;
4358
ae306cca
SH		 4359 err = pci_set_power_state(pdev, PCI_D0);
4360 if (err)
4361 goto out;
4362
4363 err = pci_restore_state(pdev);
4364 if (err)
4365 goto out;
4366
cd28ab6a 4367 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4368
4369 /* Re-enable all clocks */
05745c4a
SH		 4370 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4371 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4372 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4373 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4374
e3173832 4375 sky2_reset(hw);
8ab8fca2 4376 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4377 napi_enable(&hw->napi);
8ab8fca2 4378
f05267e7 4379 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4380 struct net_device *dev = hw->dev[i];
6a5706b9 4381 if (netif_running(dev)) {
08c06d8a
SH		 4382 err = sky2_up(dev);
4383 if (err) {
4384 printk(KERN_ERR PFX "%s: could not up: %d\n",
4385 dev->name, err);
4386 dev_close(dev);
eb35cf60 4387 goto out;
5afa0a9c 4388 }
d1b139c0
SH		 4389
4390 sky2_set_multicast(dev);
cd28ab6a
SH		 4391 }
4392 }
eb35cf60 4393
ae306cca 4394 return 0;
08c06d8a 4395out:
b02a9258 4396 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4397 pci_disable_device(pdev);
08c06d8a 4398 return err;
cd28ab6a
SH		 4399}
4400#endif
4401
e3173832
SH		 4402static void sky2_shutdown(struct pci_dev *pdev)
4403{
4404 struct sky2_hw *hw = pci_get_drvdata(pdev);
4405 int i, wol = 0;
4406
549a68c3
SH		 4407 if (!hw)
4408 return;
4409
5c0d6b34 4410 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4411
4412 for (i = 0; i < hw->ports; i++) {
4413 struct net_device *dev = hw->dev[i];
4414 struct sky2_port *sky2 = netdev_priv(dev);
4415
4416 if (sky2->wol) {
4417 wol = 1;
4418 sky2_wol_init(sky2);
4419 }
4420 }
4421
4422 if (wol)
4423 sky2_power_aux(hw);
4424
4425 pci_enable_wake(pdev, PCI_D3hot, wol);
4426 pci_enable_wake(pdev, PCI_D3cold, wol);
4427
4428 pci_disable_device(pdev);
4429 pci_set_power_state(pdev, PCI_D3hot);
4430
4431}
4432
cd28ab6a 4433static struct pci_driver sky2_driver = {
793b883e
SH		 4434 .name = DRV_NAME,
4435 .id_table = sky2_id_table,
4436 .probe = sky2_probe,
4437 .remove = __devexit_p(sky2_remove),
cd28ab6a 4438#ifdef CONFIG_PM
793b883e
SH		 4439 .suspend = sky2_suspend,
4440 .resume = sky2_resume,
cd28ab6a 4441#endif
e3173832 4442 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4443};
4444
4445static int __init sky2_init_module(void)
4446{
3cf26753 4447 sky2_debug_init();
50241c4c 4448 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4449}
4450
4451static void __exit sky2_cleanup_module(void)
4452{
4453 pci_unregister_driver(&sky2_driver);
3cf26753 4454 sky2_debug_cleanup();
cd28ab6a
SH		 4455}
4456
4457module_init(sky2_init_module);
4458module_exit(sky2_cleanup_module);
4459
4460MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4461MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4462MODULE_LICENSE("GPL");
5f4f9dc1 4463MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)