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drivers/net/mlx4: Adjust constant
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
e4f1482e 53#define DRV_VERSION "1.23"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 66
67#define TX_RING_SIZE 512
e9c1be80 68#define TX_DEF_PENDING 128
b19666d9 69#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
cd28ab6a 71
793b883e 72#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 73#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 74#define TX_WATCHDOG (5 * HZ)
75#define NAPI_WEIGHT 64
76#define PHY_RETRIES 1000
77
f4331a6d
SH		 78#define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
cb5d9547
SH		 81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH		 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH		 89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
14d0263f 92static int copybreak __read_mostly = 128;
bdb5c58e
SH		 93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH		 96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
e6cac9ba 100static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0
SH		 150static void sky2_set_multicast(struct net_device *dev);
151
af043aa5 152/* Access to PHY via serial interconnect */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
af043aa5
SH		 168
169 udelay(10);
cd28ab6a 170 }
ef743d33 171
af043aa5 172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 173 return -ETIMEDOUT;
af043aa5
SH		 174
175io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
cd28ab6a
SH		 178}
179
ef743d33 180static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 181{
182 int i;
183
793b883e 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
af043aa5 197 udelay(10);
cd28ab6a
SH		 198 }
199
af043aa5 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 201 return -ETIMEDOUT;
af043aa5
SH		 202io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
ef743d33 205}
206
af043aa5 207static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 208{
209 u16 v;
af043aa5 210 __gm_phy_read(hw, port, reg, &v);
ef743d33 211 return v;
cd28ab6a
SH		 212}
213
5afa0a9c 214
ae306cca
SH		 215static void sky2_power_on(struct sky2_hw *hw)
216{
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 220
ae306cca
SH		 221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 223
ae306cca
SH		 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 232
ea76e635 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 234 u32 reg;
5afa0a9c 235
b32f40c4 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 237
b32f40c4 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 247
b32f40c4 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 254
255 sky2_read32(hw, B2_GP_IO);
5afa0a9c 256 }
ae306cca 257}
5afa0a9c 258
ae306cca
SH		 259static void sky2_power_aux(struct sky2_hw *hw)
260{
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 275}
276
d3bcfbeb 277static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
16ad91e1
SH		 294/* flow control to advertise bits */
295static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300};
301
302/* flow control to advertise bits when using 1000BaseX */
303static const u16 fiber_fc_adv[] = {
df3fe1f3 304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 308};
309
310/* flow control to GMA disable bits */
311static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316};
317
318
cd28ab6a
SH		 319static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320{
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 323
ea76e635
SH		 324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 329 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
53419c68 332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 333 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 334 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
53419c68
SH		 337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 344 if (sky2_is_copper(hw)) {
05745c4a 345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
cd28ab6a
SH		 358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
53419c68 365 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 366 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 368 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
cd28ab6a
SH		 373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 378 }
cd28ab6a 379
b89165f2
SH		 380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
ea76e635 383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 385
b89165f2
SH		 386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 401 }
b89165f2
SH		 402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 404 }
405
7800fddc 406 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
2eaba1a2 409 reg = 0;
cd28ab6a
SH		 410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 412 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
709c6e7b 425
16ad91e1 426 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 432
16ad91e1 433 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 434 }
cd28ab6a
SH		 435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
2eaba1a2
SH		 442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
2eaba1a2 448 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
2eaba1a2 452 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 453 break;
454 }
455
2eaba1a2
SH		 456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
2eaba1a2 461
2eaba1a2 462
16ad91e1 463 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 464
465 /* Forward pause packets to GMAC? */
16ad91e1 466 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 470 }
471
2eaba1a2
SH		 472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
05745c4a 474 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
05745c4a
SH		 498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
cd28ab6a 515 case CHIP_ID_YUKON_XL:
793b883e 516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
ed6d32c7
SH		 522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 536
537 /* restore page register */
793b883e 538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 539 break;
93745494 540
ed6d32c7 541 case CHIP_ID_YUKON_EC_U:
93745494 542 case CHIP_ID_YUKON_EX:
ed4d4161 543 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
cd28ab6a
SH		 562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 566
cd28ab6a 567 /* turn off the Rx LED (LED_RX) */
a84d0a3d 568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 569 }
570
0ce8b98d 571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 572 /* apply fixes in PHY AFE */
ed6d32c7
SH		 573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
977bdf06 575 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 578
0ce8b98d
SH		 579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
977bdf06
SH		 584
585 /* set page register to 0 */
9467a8fc 586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 594 /* no effect on Yukon-XL */
977bdf06 595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 596
977bdf06
SH		 597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 600 }
cd28ab6a 601
977bdf06
SH		 602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
2eaba1a2 606
d571b694 607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612}
613
b96936da
SH		 614static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 618{
619 u32 reg1;
d3bcfbeb 620
82637e80 621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 623 reg1 &= ~phy_power[port];
d3bcfbeb 624
b96936da 625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 626 reg1 |= coma_mode[port];
627
b32f40c4 628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 636}
167f53d0 637
b96936da
SH		 638static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639{
640 u32 reg1;
db99b988
SH		 641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 670
e484d5f5 671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
b96936da
SH		 683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 689}
690
1b537565
SH		 691/* Force a renegotiation */
692static void sky2_phy_reinit(struct sky2_port *sky2)
693{
e07b1aa8 694 spin_lock_bh(&sky2->phy_lock);
1b537565 695 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 696 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 697}
698
e3173832
SH		 699/* Put device in state to listen for Wake On Lan */
700static void sky2_wol_init(struct sky2_port *sky2)
701{
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
b96936da
SH		 723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
b32f40c4 758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 759 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765}
766
69161611
SH		 767static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768{
05745c4a
SH		 769 struct net_device *dev = hw->dev[port];
770
ed4d4161
SH		 771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
05745c4a 777
ed4d4161
SH		 778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 781
ed4d4161
SH		 782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 792
ed4d4161
SH		 793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
69161611
SH		 798 }
799}
800
cd28ab6a
SH		 801static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802{
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
25cccecc 805 u32 rx_reg;
cd28ab6a
SH		 806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
f350339c
SH		 809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
793b883e 814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
793b883e 826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 827
2eaba1a2
SH		 828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
e07b1aa8 831 spin_lock_bh(&sky2->phy_lock);
b96936da 832 sky2_phy_power_up(hw, port);
cd28ab6a 833 sky2_phy_init(hw, port);
e07b1aa8 834 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
43f2f104
SH		 840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
cd28ab6a
SH		 842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
793b883e 849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 864
6b1a3aef 865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
cd28ab6a
SH		 870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
793b883e
SH		 873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
cd28ab6a
SH		 877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 886 rx_reg |= GMF_RX_OVER_ON;
69161611 887
25cccecc 888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 889
798fdd07
SH		 890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
cd28ab6a 897
8df9a876 898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 909
e0c28116 910 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 914
69161611 915 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 916 }
917
e970d1f8
SH		 918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
cd28ab6a
SH		 925}
926
67712901
SH		 927/* Assign Ram Buffer allocation to queue */
928static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 929{
67712901
SH		 930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
793b883e 936
cd28ab6a
SH		 937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 944 u32 tp = space - space/4;
793b883e 945
1c28f6ba
SH		 946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 952
1c28f6ba
SH		 953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 965}
966
cd28ab6a 967/* Setup Bus Memory Interface */
af4ed7e6 968static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 969{
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 974}
975
cd28ab6a
SH		 976/* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
8cc048e3 979static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 980 u64 addr, u32 last)
981{
cd28ab6a
SH		 982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 990}
991
793b883e
SH		 992static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
993{
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
995
cb5d9547 996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 997 le->ctrl = 0;
793b883e
SH		 998 return le;
999}
cd28ab6a 1000
88f5f0ca
SH		 1001static void tx_init(struct sky2_port *sky2)
1002{
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
1009 le = get_tx_le(sky2);
1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1012}
1013
291ea614
SH		 1014static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016{
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018}
1019
290d4de5
SH		 1020/* Update chip's next pointer */
1021static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1022{
50432cb5 1023 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1024 wmb();
50432cb5
SH		 1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
cd28ab6a
SH		 1029}
1030
793b883e 1031
cd28ab6a
SH		 1032static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033{
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1036 le->ctrl = 0;
cd28ab6a
SH		 1037 return le;
1038}
1039
14d0263f
SH		 1040/* Build description to hardware for one receive segment */
1041static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1043{
1044 struct sky2_rx_le *le;
1045
86c6887e 1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1047 le = sky2_next_rx(sky2);
86c6887e 1048 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
793b883e 1051
cd28ab6a 1052 le = sky2_next_rx(sky2);
734d1868
SH		 1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
14d0263f 1055 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1056}
1057
14d0263f
SH		 1058/* Build description to hardware for one possibly fragmented skb */
1059static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061{
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068}
1069
1070
454e6cb6 1071static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1072 unsigned size)
1073{
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1079 return -EIO;
1080
14d0263f
SH		 1081 pci_unmap_len_set(re, data_size, size);
1082
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
454e6cb6 1089 return 0;
14d0263f
SH		 1090}
1091
1092static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1093{
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1099
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1104}
793b883e 1105
cd28ab6a
SH		 1106/* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1108 * order problems.
1109 */
793b883e 1110static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1111{
ea76e635 1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1113
ea76e635
SH		 1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1115 le->ctrl = 0;
1116 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1117
ea76e635
SH		 1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1121}
1122
6b1a3aef 1123/*
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1131 * will be reset.
1132 */
1133static void sky2_rx_stop(struct sky2_port *sky2)
1134{
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1137 int i;
1138
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1141
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1145 goto stopped;
1146
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1149stopped:
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1151
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1154 mmiowb();
6b1a3aef 1155}
793b883e 1156
d571b694 1157/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1158static void sky2_rx_clean(struct sky2_port *sky2)
1159{
1160 unsigned i;
1161
1162 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1163 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1164 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1165
1166 if (re->skb) {
14d0263f 1167 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1168 kfree_skb(re->skb);
1169 re->skb = NULL;
1170 }
1171 }
bd1c6869 1172 skb_queue_purge(&sky2->rx_recycle);
cd28ab6a
SH		 1173}
1174
ef743d33 1175/* Basic MII support */
1176static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1177{
1178 struct mii_ioctl_data *data = if_mii(ifr);
1179 struct sky2_port *sky2 = netdev_priv(dev);
1180 struct sky2_hw *hw = sky2->hw;
1181 int err = -EOPNOTSUPP;
1182
1183 if (!netif_running(dev))
1184 return -ENODEV; /* Phy still in reset */
1185
d89e1343 1186 switch (cmd) {
ef743d33 1187 case SIOCGMIIPHY:
1188 data->phy_id = PHY_ADDR_MARV;
1189
1190 /* fallthru */
1191 case SIOCGMIIREG: {
1192 u16 val = 0;
91c86df5 1193
e07b1aa8 1194 spin_lock_bh(&sky2->phy_lock);
ef743d33 1195 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1196 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1197
ef743d33 1198 data->val_out = val;
1199 break;
1200 }
1201
1202 case SIOCSMIIREG:
1203 if (!capable(CAP_NET_ADMIN))
1204 return -EPERM;
1205
e07b1aa8 1206 spin_lock_bh(&sky2->phy_lock);
ef743d33 1207 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1208 data->val_in);
e07b1aa8 1209 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1210 break;
1211 }
1212 return err;
1213}
1214
d1f13708 1215#ifdef SKY2_VLAN_TAG_USED
d494eacd 1216static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1217{
d494eacd 1218 if (onoff) {
3d4e66f5
SH		 1219 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1220 RX_VLAN_STRIP_ON);
1221 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1222 TX_VLAN_TAG_ON);
1223 } else {
1224 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1225 RX_VLAN_STRIP_OFF);
1226 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1227 TX_VLAN_TAG_OFF);
1228 }
d494eacd
SH		 1229}
1230
1231static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1232{
1233 struct sky2_port *sky2 = netdev_priv(dev);
1234 struct sky2_hw *hw = sky2->hw;
1235 u16 port = sky2->port;
1236
1237 netif_tx_lock_bh(dev);
1238 napi_disable(&hw->napi);
1239
1240 sky2->vlgrp = grp;
1241 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1242
d1d08d12 1243 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1244 napi_enable(&hw->napi);
2bb8c262 1245 netif_tx_unlock_bh(dev);
d1f13708 1246}
1247#endif
1248
bd1c6869
SH		 1249/* Amount of required worst case padding in rx buffer */
1250static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1251{
1252 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1253}
1254
82788c7a 1255/*
14d0263f
SH		 1256 * Allocate an skb for receiving. If the MTU is large enough
1257 * make the skb non-linear with a fragment list of pages.
82788c7a 1258 */
14d0263f 1259static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1260{
1261 struct sk_buff *skb;
14d0263f 1262 int i;
82788c7a 1263
bd1c6869
SH		 1264 skb = __skb_dequeue(&sky2->rx_recycle);
1265 if (!skb)
1266 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size
1267 + sky2_rx_pad(sky2->hw));
1268 if (!skb)
1269 goto nomem;
1270
39dbd958 1271 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1272 unsigned char *start;
1273 /*
1274 * Workaround for a bug in FIFO that cause hang
1275 * if the FIFO if the receive buffer is not 64 byte aligned.
1276 * The buffer returned from netdev_alloc_skb is
1277 * aligned except if slab debugging is enabled.
1278 */
f03b8654
SH		 1279 start = PTR_ALIGN(skb->data, 8);
1280 skb_reserve(skb, start - skb->data);
bd1c6869 1281 } else
f03b8654 1282 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1283
1284 for (i = 0; i < sky2->rx_nfrags; i++) {
1285 struct page *page = alloc_page(GFP_ATOMIC);
1286
1287 if (!page)
1288 goto free_partial;
1289 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1290 }
1291
1292 return skb;
14d0263f
SH		 1293free_partial:
1294 kfree_skb(skb);
1295nomem:
1296 return NULL;
82788c7a
SH		 1297}
1298
55c9dd35
SH		 1299static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1300{
1301 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1302}
1303
cd28ab6a
SH		 1304/*
1305 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1306 * Normal case this ends up creating one list element for skb
1307 * in the receive ring. Worst case if using large MTU and each
1308 * allocation falls on a different 64 bit region, that results
1309 * in 6 list elements per ring entry.
1310 * One element is used for checksum enable/disable, and one
1311 * extra to avoid wrap.
cd28ab6a 1312 */
6b1a3aef 1313static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1314{
6b1a3aef 1315 struct sky2_hw *hw = sky2->hw;
14d0263f 1316 struct rx_ring_info *re;
6b1a3aef 1317 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1318 unsigned i, size, thresh;
cd28ab6a 1319
6b1a3aef 1320 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1321 sky2_qset(hw, rxq);
977bdf06 1322
c3905bc4
SH		 1323 /* On PCI express lowering the watermark gives better performance */
1324 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1325 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1326
1327 /* These chips have no ram buffer?
1328 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1329 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1330 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1331 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1332 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1333
6b1a3aef 1334 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1335
ea76e635
SH		 1336 if (!(hw->flags & SKY2_HW_NEW_LE))
1337 rx_set_checksum(sky2);
14d0263f
SH		 1338
1339 /* Space needed for frame data + headers rounded up */
f957da2a 1340 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1341
1342 /* Stopping point for hardware truncation */
1343 thresh = (size - 8) / sizeof(u32);
1344
5f06eba4 1345 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1346 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1347
5f06eba4
SH		 1348 /* Compute residue after pages */
1349 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1350
5f06eba4
SH		 1351 /* Optimize to handle small packets and headers */
1352 if (size < copybreak)
1353 size = copybreak;
1354 if (size < ETH_HLEN)
1355 size = ETH_HLEN;
14d0263f 1356
14d0263f
SH		 1357 sky2->rx_data_size = size;
1358
bd1c6869
SH		 1359 skb_queue_head_init(&sky2->rx_recycle);
1360
14d0263f 1361 /* Fill Rx ring */
793b883e 1362 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1363 re = sky2->rx_ring + i;
cd28ab6a 1364
14d0263f 1365 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1366 if (!re->skb)
1367 goto nomem;
1368
454e6cb6
SH		 1369 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1370 dev_kfree_skb(re->skb);
1371 re->skb = NULL;
1372 goto nomem;
1373 }
1374
14d0263f 1375 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1376 }
1377
a1433ac4
SH		 1378 /*
1379 * The receiver hangs if it receives frames larger than the
1380 * packet buffer. As a workaround, truncate oversize frames, but
1381 * the register is limited to 9 bits, so if you do frames > 2052
1382 * you better get the MTU right!
1383 */
a1433ac4
SH		 1384 if (thresh > 0x1ff)
1385 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1386 else {
1387 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1388 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1389 }
1390
6b1a3aef 1391 /* Tell chip about available buffers */
55c9dd35 1392 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1393 return 0;
1394nomem:
1395 sky2_rx_clean(sky2);
1396 return -ENOMEM;
1397}
1398
1399/* Bring up network interface. */
1400static int sky2_up(struct net_device *dev)
1401{
1402 struct sky2_port *sky2 = netdev_priv(dev);
1403 struct sky2_hw *hw = sky2->hw;
1404 unsigned port = sky2->port;
e0c28116 1405 u32 imask, ramsize;
ee7abb04 1406 int cap, err = -ENOMEM;
843a46f4 1407 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1408
ee7abb04
SH		 1409 /*
1410 * On dual port PCI-X card, there is an problem where status
1411 * can be received out of order due to split transactions
843a46f4 1412 */
ee7abb04
SH		 1413 if (otherdev && netif_running(otherdev) &&
1414 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1415 u16 cmd;
1416
b32f40c4 1417 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1418 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1419 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1420
ee7abb04 1421 }
843a46f4 1422
55d7b4e6
SH		 1423 netif_carrier_off(dev);
1424
cd28ab6a
SH		 1425 /* must be power of 2 */
1426 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1427 TX_RING_SIZE *
1428 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1429 &sky2->tx_le_map);
1430 if (!sky2->tx_le)
1431 goto err_out;
1432
6cdbbdf3 1433 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1434 GFP_KERNEL);
1435 if (!sky2->tx_ring)
1436 goto err_out;
88f5f0ca
SH		 1437
1438 tx_init(sky2);
cd28ab6a
SH		 1439
1440 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1441 &sky2->rx_le_map);
1442 if (!sky2->rx_le)
1443 goto err_out;
1444 memset(sky2->rx_le, 0, RX_LE_BYTES);
1445
291ea614 1446 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1447 GFP_KERNEL);
1448 if (!sky2->rx_ring)
1449 goto err_out;
1450
1451 sky2_mac_init(hw, port);
1452
e0c28116
SH		 1453 /* Register is number of 4K blocks on internal RAM buffer. */
1454 ramsize = sky2_read8(hw, B2_E_0) * 4;
1455 if (ramsize > 0) {
67712901 1456 u32 rxspace;
cd28ab6a 1457
39dbd958 1458 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1459 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1460 if (ramsize < 16)
1461 rxspace = ramsize / 2;
1462 else
1463 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1464
67712901
SH		 1465 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1466 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1467
1468 /* Make sure SyncQ is disabled */
1469 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1470 RB_RST_SET);
1471 }
793b883e 1472
af4ed7e6 1473 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1474
69161611
SH		 1475 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1476 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1477 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1478
977bdf06 1479 /* Set almost empty threshold */
c2716fb4
SH		 1480 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1481 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1482 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1483
6b1a3aef 1484 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1485 TX_RING_SIZE - 1);
cd28ab6a 1486
d494eacd
SH		 1487#ifdef SKY2_VLAN_TAG_USED
1488 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1489#endif
1490
6b1a3aef 1491 err = sky2_rx_start(sky2);
6de16237 1492 if (err)
cd28ab6a
SH		 1493 goto err_out;
1494
cd28ab6a 1495 /* Enable interrupts from phy/mac for port */
e07b1aa8 1496 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1497 imask |= portirq_msk[port];
e07b1aa8 1498 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1499 sky2_read32(hw, B0_IMSK);
e07b1aa8 1500
a7bffe72 1501 sky2_set_multicast(dev);
a11da890
AD		 1502
1503 if (netif_msg_ifup(sky2))
1504 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
cd28ab6a
SH		 1505 return 0;
1506
1507err_out:
1b537565 1508 if (sky2->rx_le) {
cd28ab6a
SH		 1509 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1510 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1511 sky2->rx_le = NULL;
1512 }
1513 if (sky2->tx_le) {
cd28ab6a
SH		 1514 pci_free_consistent(hw->pdev,
1515 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1516 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1517 sky2->tx_le = NULL;
1518 }
1519 kfree(sky2->tx_ring);
1520 kfree(sky2->rx_ring);
cd28ab6a 1521
1b537565
SH		 1522 sky2->tx_ring = NULL;
1523 sky2->rx_ring = NULL;
cd28ab6a
SH		 1524 return err;
1525}
1526
793b883e
SH		 1527/* Modular subtraction in ring */
1528static inline int tx_dist(unsigned tail, unsigned head)
1529{
cb5d9547 1530 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1531}
cd28ab6a 1532
793b883e
SH		 1533/* Number of list elements available for next tx */
1534static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1535{
793b883e 1536 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1537}
1538
793b883e 1539/* Estimate of number of transmit list elements required */
28bd181a 1540static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1541{
793b883e
SH		 1542 unsigned count;
1543
1544 count = sizeof(dma_addr_t) / sizeof(u32);
1545 count += skb_shinfo(skb)->nr_frags * count;
1546
89114afd 1547 if (skb_is_gso(skb))
793b883e
SH		 1548 ++count;
1549
84fa7933 1550 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1551 ++count;
1552
1553 return count;
cd28ab6a
SH		 1554}
1555
793b883e
SH		 1556/*
1557 * Put one packet in ring for transmit.
1558 * A single packet can generate multiple list elements, and
1559 * the number of ring elements will probably be less than the number
1560 * of list elements used.
1561 */
cd28ab6a
SH		 1562static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1563{
1564 struct sky2_port *sky2 = netdev_priv(dev);
1565 struct sky2_hw *hw = sky2->hw;
d1f13708 1566 struct sky2_tx_le *le = NULL;
6cdbbdf3 1567 struct tx_ring_info *re;
454e6cb6 1568 unsigned i, len, first_slot;
cd28ab6a 1569 dma_addr_t mapping;
cd28ab6a
SH		 1570 u16 mss;
1571 u8 ctrl;
1572
2bb8c262
SH		 1573 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1574 return NETDEV_TX_BUSY;
cd28ab6a 1575
cd28ab6a
SH		 1576 len = skb_headlen(skb);
1577 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1578
454e6cb6
SH		 1579 if (pci_dma_mapping_error(hw->pdev, mapping))
1580 goto mapping_error;
1581
1582 first_slot = sky2->tx_prod;
1583 if (unlikely(netif_msg_tx_queued(sky2)))
1584 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1585 dev->name, first_slot, skb->len);
1586
86c6887e
SH		 1587 /* Send high bits if needed */
1588 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1589 le = get_tx_le(sky2);
86c6887e 1590 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1591 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1592 }
cd28ab6a
SH		 1593
1594 /* Check for TCP Segmentation Offload */
7967168c 1595 mss = skb_shinfo(skb)->gso_size;
793b883e 1596 if (mss != 0) {
ea76e635
SH		 1597
1598 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1599 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1600
1601 if (mss != sky2->tx_last_mss) {
1602 le = get_tx_le(sky2);
1603 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1604
1605 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1606 le->opcode = OP_MSS | HW_OWNER;
1607 else
1608 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1609 sky2->tx_last_mss = mss;
1610 }
cd28ab6a
SH		 1611 }
1612
cd28ab6a 1613 ctrl = 0;
d1f13708 1614#ifdef SKY2_VLAN_TAG_USED
1615 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1616 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1617 if (!le) {
1618 le = get_tx_le(sky2);
f65b138c 1619 le->addr = 0;
d1f13708 1620 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1621 } else
1622 le->opcode |= OP_VLAN;
1623 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1624 ctrl |= INS_VLAN;
1625 }
1626#endif
1627
1628 /* Handle TCP checksum offload */
84fa7933 1629 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1630 /* On Yukon EX (some versions) encoding change. */
ea76e635 1631 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1632 ctrl |= CALSUM; /* auto checksum */
1633 else {
1634 const unsigned offset = skb_transport_offset(skb);
1635 u32 tcpsum;
1636
1637 tcpsum = offset << 16; /* sum start */
1638 tcpsum |= offset + skb->csum_offset; /* sum write */
1639
1640 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1641 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1642 ctrl |= UDPTCP;
1643
1644 if (tcpsum != sky2->tx_tcpsum) {
1645 sky2->tx_tcpsum = tcpsum;
1646
1647 le = get_tx_le(sky2);
1648 le->addr = cpu_to_le32(tcpsum);
1649 le->length = 0; /* initial checksum value */
1650 le->ctrl = 1; /* one packet */
1651 le->opcode = OP_TCPLISW | HW_OWNER;
1652 }
1d179332 1653 }
cd28ab6a
SH		 1654 }
1655
1656 le = get_tx_le(sky2);
f65b138c 1657 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1658 le->length = cpu_to_le16(len);
1659 le->ctrl = ctrl;
793b883e 1660 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1661
291ea614 1662 re = tx_le_re(sky2, le);
cd28ab6a 1663 re->skb = skb;
6cdbbdf3 1664 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1665 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1666
1667 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1668 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1669
1670 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1671 frag->size, PCI_DMA_TODEVICE);
86c6887e 1672
454e6cb6
SH		 1673 if (pci_dma_mapping_error(hw->pdev, mapping))
1674 goto mapping_unwind;
1675
86c6887e 1676 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1677 le = get_tx_le(sky2);
86c6887e 1678 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1679 le->ctrl = 0;
1680 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1681 }
1682
1683 le = get_tx_le(sky2);
f65b138c 1684 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1685 le->length = cpu_to_le16(frag->size);
1686 le->ctrl = ctrl;
793b883e 1687 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1688
291ea614
SH		 1689 re = tx_le_re(sky2, le);
1690 re->skb = skb;
1691 pci_unmap_addr_set(re, mapaddr, mapping);
1692 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1693 }
6cdbbdf3 1694
cd28ab6a
SH		 1695 le->ctrl |= EOP;
1696
97bda706 1697 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1698 netif_stop_queue(dev);
b19666d9 1699
290d4de5 1700 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1701
cd28ab6a 1702 return NETDEV_TX_OK;
454e6cb6
SH		 1703
1704mapping_unwind:
1705 for (i = first_slot; i != sky2->tx_prod; i = RING_NEXT(i, TX_RING_SIZE)) {
1706 le = sky2->tx_le + i;
1707 re = sky2->tx_ring + i;
1708
1709 switch(le->opcode & ~HW_OWNER) {
1710 case OP_LARGESEND:
1711 case OP_PACKET:
1712 pci_unmap_single(hw->pdev,
1713 pci_unmap_addr(re, mapaddr),
1714 pci_unmap_len(re, maplen),
1715 PCI_DMA_TODEVICE);
1716 break;
1717 case OP_BUFFER:
1718 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1719 pci_unmap_len(re, maplen),
1720 PCI_DMA_TODEVICE);
1721 break;
1722 }
1723 }
1724
1725 sky2->tx_prod = first_slot;
1726mapping_error:
1727 if (net_ratelimit())
1728 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1729 dev_kfree_skb(skb);
1730 return NETDEV_TX_OK;
cd28ab6a
SH		 1731}
1732
cd28ab6a 1733/*
793b883e
SH		 1734 * Free ring elements from starting at tx_cons until "done"
1735 *
1736 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1737 * buffers so make sure not to free skb to early.
cd28ab6a 1738 */
d11c13e7 1739static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1740{
d11c13e7 1741 struct net_device *dev = sky2->netdev;
af2a58ac 1742 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1743 unsigned idx;
cd28ab6a 1744
0e3ff6aa 1745 BUG_ON(done >= TX_RING_SIZE);
2224795d 1746
291ea614
SH		 1747 for (idx = sky2->tx_cons; idx != done;
1748 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1749 struct sky2_tx_le *le = sky2->tx_le + idx;
1750 struct tx_ring_info *re = sky2->tx_ring + idx;
1751
1752 switch(le->opcode & ~HW_OWNER) {
1753 case OP_LARGESEND:
1754 case OP_PACKET:
1755 pci_unmap_single(pdev,
1756 pci_unmap_addr(re, mapaddr),
1757 pci_unmap_len(re, maplen),
1758 PCI_DMA_TODEVICE);
af2a58ac 1759 break;
291ea614
SH		 1760 case OP_BUFFER:
1761 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1762 pci_unmap_len(re, maplen),
734d1868 1763 PCI_DMA_TODEVICE);
291ea614
SH		 1764 break;
1765 }
1766
1767 if (le->ctrl & EOP) {
bd1c6869
SH		 1768 struct sk_buff *skb = re->skb;
1769
291ea614
SH		 1770 if (unlikely(netif_msg_tx_done(sky2)))
1771 printk(KERN_DEBUG "%s: tx done %u\n",
1772 dev->name, idx);
3cf26753 1773
7138a0f5 1774 dev->stats.tx_packets++;
bd1c6869
SH		 1775 dev->stats.tx_bytes += skb->len;
1776
1777 if (skb_queue_len(&sky2->rx_recycle) < sky2->rx_pending
1778 && skb_recycle_check(skb, sky2->rx_data_size
1779 + sky2_rx_pad(sky2->hw)))
1780 __skb_queue_head(&sky2->rx_recycle, skb);
1781 else
1782 dev_kfree_skb_any(skb);
2bf56fe2 1783
3cf26753 1784 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1785 }
793b883e 1786 }
793b883e 1787
291ea614 1788 sky2->tx_cons = idx;
50432cb5
SH		 1789 smp_mb();
1790
22e11703 1791 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1792 netif_wake_queue(dev);
cd28ab6a
SH		 1793}
1794
1795/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1796static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1797{
2bb8c262
SH		 1798 struct sky2_port *sky2 = netdev_priv(dev);
1799
1800 netif_tx_lock_bh(dev);
d11c13e7 1801 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1802 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1803}
1804
1805/* Network shutdown */
1806static int sky2_down(struct net_device *dev)
1807{
1808 struct sky2_port *sky2 = netdev_priv(dev);
1809 struct sky2_hw *hw = sky2->hw;
1810 unsigned port = sky2->port;
1811 u16 ctrl;
e07b1aa8 1812 u32 imask;
cd28ab6a 1813
1b537565
SH		 1814 /* Never really got started! */
1815 if (!sky2->tx_le)
1816 return 0;
1817
cd28ab6a
SH		 1818 if (netif_msg_ifdown(sky2))
1819 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1820
ebc646f6
SH		 1821 /* Disable port IRQ */
1822 imask = sky2_read32(hw, B0_IMSK);
1823 imask &= ~portirq_msk[port];
1824 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1825 sky2_read32(hw, B0_IMSK);
ebc646f6 1826
d104acaf
SH		 1827 /* Force flow control off */
1828 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1829
cd28ab6a
SH		 1830 /* Stop transmitter */
1831 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1832 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1833
1834 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1835 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1836
1837 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1838 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1839 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1840
1841 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1842
1843 /* Workaround shared GMAC reset */
793b883e
SH		 1844 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1845 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1846 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1847
1848 /* Disable Force Sync bit and Enable Alloc bit */
1849 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1850 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1851
1852 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1853 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1854 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1855
1856 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1857 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1858 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1859
1860 /* Reset the Tx prefetch units */
1861 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1862 PREF_UNIT_RST_SET);
1863
1864 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1865
6b1a3aef 1866 sky2_rx_stop(sky2);
cd28ab6a
SH		 1867
1868 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1869 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1870
6c83504f
SH		 1871 /* Force any delayed status interrrupt and NAPI */
1872 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1873 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1874 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1875 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1876
1877 synchronize_irq(hw->pdev->irq);
1878 napi_synchronize(&hw->napi);
1879
b96936da 1880 sky2_phy_power_down(hw, port);
d3bcfbeb 1881
d571b694 1882 /* turn off LED's */
cd28ab6a
SH		 1883 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1884
2bb8c262 1885 sky2_tx_clean(dev);
cd28ab6a
SH		 1886 sky2_rx_clean(sky2);
1887
1888 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1889 sky2->rx_le, sky2->rx_le_map);
1890 kfree(sky2->rx_ring);
1891
1892 pci_free_consistent(hw->pdev,
1893 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1894 sky2->tx_le, sky2->tx_le_map);
1895 kfree(sky2->tx_ring);
1896
1b537565
SH		 1897 sky2->tx_le = NULL;
1898 sky2->rx_le = NULL;
1899
1900 sky2->rx_ring = NULL;
1901 sky2->tx_ring = NULL;
1902
cd28ab6a
SH		 1903 return 0;
1904}
1905
1906static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1907{
ea76e635 1908 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1909 return SPEED_1000;
1910
05745c4a
SH		 1911 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1912 if (aux & PHY_M_PS_SPEED_100)
1913 return SPEED_100;
1914 else
1915 return SPEED_10;
1916 }
cd28ab6a
SH		 1917
1918 switch (aux & PHY_M_PS_SPEED_MSK) {
1919 case PHY_M_PS_SPEED_1000:
1920 return SPEED_1000;
1921 case PHY_M_PS_SPEED_100:
1922 return SPEED_100;
1923 default:
1924 return SPEED_10;
1925 }
1926}
1927
1928static void sky2_link_up(struct sky2_port *sky2)
1929{
1930 struct sky2_hw *hw = sky2->hw;
1931 unsigned port = sky2->port;
1932 u16 reg;
16ad91e1
SH		 1933 static const char *fc_name[] = {
1934 [FC_NONE] = "none",
1935 [FC_TX] = "tx",
1936 [FC_RX] = "rx",
1937 [FC_BOTH] = "both",
1938 };
cd28ab6a 1939
cd28ab6a 1940 /* enable Rx/Tx */
2eaba1a2 1941 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1942 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1943 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1944
1945 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1946
1947 netif_carrier_on(sky2->netdev);
cd28ab6a 1948
75e80683 1949 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1950
cd28ab6a 1951 /* Turn on link LED */
793b883e 1952 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1953 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1954
1955 if (netif_msg_link(sky2))
1956 printk(KERN_INFO PFX
d571b694 1957 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1958 sky2->netdev->name, sky2->speed,
1959 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1960 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1961}
1962
1963static void sky2_link_down(struct sky2_port *sky2)
1964{
1965 struct sky2_hw *hw = sky2->hw;
1966 unsigned port = sky2->port;
1967 u16 reg;
1968
1969 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1970
1971 reg = gma_read16(hw, port, GM_GP_CTRL);
1972 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1973 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1974
cd28ab6a 1975 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1976
1977 /* Turn on link LED */
1978 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1979
1980 if (netif_msg_link(sky2))
1981 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1982
cd28ab6a
SH		 1983 sky2_phy_init(hw, port);
1984}
1985
16ad91e1
SH		 1986static enum flow_control sky2_flow(int rx, int tx)
1987{
1988 if (rx)
1989 return tx ? FC_BOTH : FC_RX;
1990 else
1991 return tx ? FC_TX : FC_NONE;
1992}
1993
793b883e
SH		 1994static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1995{
1996 struct sky2_hw *hw = sky2->hw;
1997 unsigned port = sky2->port;
da4c1ff4 1998 u16 advert, lpa;
793b883e 1999
da4c1ff4 2000 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2001 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2002 if (lpa & PHY_M_AN_RF) {
2003 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2004 return -1;
2005 }
2006
793b883e
SH		 2007 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2008 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2009 sky2->netdev->name);
2010 return -1;
2011 }
2012
793b883e 2013 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2014 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2015
da4c1ff4
SH		 2016 /* Since the pause result bits seem to in different positions on
2017 * different chips. look at registers.
2018 */
ea76e635 2019 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2020 /* Shift for bits in fiber PHY */
2021 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2022 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2023
2024 if (advert & ADVERTISE_1000XPAUSE)
2025 advert |= ADVERTISE_PAUSE_CAP;
2026 if (advert & ADVERTISE_1000XPSE_ASYM)
2027 advert |= ADVERTISE_PAUSE_ASYM;
2028 if (lpa & LPA_1000XPAUSE)
2029 lpa |= LPA_PAUSE_CAP;
2030 if (lpa & LPA_1000XPAUSE_ASYM)
2031 lpa |= LPA_PAUSE_ASYM;
2032 }
793b883e 2033
da4c1ff4
SH		 2034 sky2->flow_status = FC_NONE;
2035 if (advert & ADVERTISE_PAUSE_CAP) {
2036 if (lpa & LPA_PAUSE_CAP)
2037 sky2->flow_status = FC_BOTH;
2038 else if (advert & ADVERTISE_PAUSE_ASYM)
2039 sky2->flow_status = FC_RX;
2040 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2041 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2042 sky2->flow_status = FC_TX;
2043 }
793b883e 2044
16ad91e1 2045 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2046 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2047 sky2->flow_status = FC_NONE;
2eaba1a2 2048
da4c1ff4 2049 if (sky2->flow_status & FC_TX)
793b883e
SH		 2050 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2051 else
2052 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2053
2054 return 0;
2055}
cd28ab6a 2056
e07b1aa8
SH		 2057/* Interrupt from PHY */
2058static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2059{
e07b1aa8
SH		 2060 struct net_device *dev = hw->dev[port];
2061 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2062 u16 istatus, phystat;
2063
ebc646f6
SH		 2064 if (!netif_running(dev))
2065 return;
2066
e07b1aa8
SH		 2067 spin_lock(&sky2->phy_lock);
2068 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2069 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2070
cd28ab6a
SH		 2071 if (netif_msg_intr(sky2))
2072 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2073 sky2->netdev->name, istatus, phystat);
2074
2eaba1a2 2075 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 2076 if (sky2_autoneg_done(sky2, phystat) == 0)
2077 sky2_link_up(sky2);
2078 goto out;
2079 }
cd28ab6a 2080
793b883e
SH		 2081 if (istatus & PHY_M_IS_LSP_CHANGE)
2082 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2083
793b883e
SH		 2084 if (istatus & PHY_M_IS_DUP_CHANGE)
2085 sky2->duplex =
2086 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2087
793b883e
SH		 2088 if (istatus & PHY_M_IS_LST_CHANGE) {
2089 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2090 sky2_link_up(sky2);
793b883e
SH		 2091 else
2092 sky2_link_down(sky2);
cd28ab6a 2093 }
793b883e 2094out:
e07b1aa8 2095 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2096}
2097
62335ab0 2098/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2099 * and tx queue is full (stopped).
2100 */
cd28ab6a
SH		 2101static void sky2_tx_timeout(struct net_device *dev)
2102{
2103 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2104 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2105
2106 if (netif_msg_timer(sky2))
2107 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2108
8f24664d 2109 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2110 dev->name, sky2->tx_cons, sky2->tx_prod,
2111 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2112 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2113
81906791
SH		 2114 /* can't restart safely under softirq */
2115 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2116}
2117
2118static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2119{
6b1a3aef 2120 struct sky2_port *sky2 = netdev_priv(dev);
2121 struct sky2_hw *hw = sky2->hw;
b628ed98 2122 unsigned port = sky2->port;
6b1a3aef 2123 int err;
2124 u16 ctl, mode;
e07b1aa8 2125 u32 imask;
cd28ab6a
SH		 2126
2127 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2128 return -EINVAL;
2129
05745c4a
SH		 2130 if (new_mtu > ETH_DATA_LEN &&
2131 (hw->chip_id == CHIP_ID_YUKON_FE ||
2132 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2133 return -EINVAL;
2134
6b1a3aef 2135 if (!netif_running(dev)) {
2136 dev->mtu = new_mtu;
2137 return 0;
2138 }
2139
e07b1aa8 2140 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2141 sky2_write32(hw, B0_IMSK, 0);
2142
018d1c66 2143 dev->trans_start = jiffies; /* prevent tx timeout */
2144 netif_stop_queue(dev);
bea3348e 2145 napi_disable(&hw->napi);
018d1c66 2146
e07b1aa8
SH		 2147 synchronize_irq(hw->pdev->irq);
2148
39dbd958 2149 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2150 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2151
2152 ctl = gma_read16(hw, port, GM_GP_CTRL);
2153 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2154 sky2_rx_stop(sky2);
2155 sky2_rx_clean(sky2);
cd28ab6a
SH		 2156
2157 dev->mtu = new_mtu;
14d0263f 2158
6b1a3aef 2159 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2160 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2161
2162 if (dev->mtu > ETH_DATA_LEN)
2163 mode |= GM_SMOD_JUMBO_ENA;
2164
b628ed98 2165 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2166
b628ed98 2167 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2168
6b1a3aef 2169 err = sky2_rx_start(sky2);
e07b1aa8 2170 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2171
d1d08d12 2172 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2173 napi_enable(&hw->napi);
2174
1b537565
SH		 2175 if (err)
2176 dev_close(dev);
2177 else {
b628ed98 2178 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2179
1b537565
SH		 2180 netif_wake_queue(dev);
2181 }
2182
cd28ab6a
SH		 2183 return err;
2184}
2185
14d0263f
SH		 2186/* For small just reuse existing skb for next receive */
2187static struct sk_buff *receive_copy(struct sky2_port *sky2,
2188 const struct rx_ring_info *re,
2189 unsigned length)
2190{
2191 struct sk_buff *skb;
2192
2193 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2194 if (likely(skb)) {
2195 skb_reserve(skb, 2);
2196 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2197 length, PCI_DMA_FROMDEVICE);
d626f62b 2198 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2199 skb->ip_summed = re->skb->ip_summed;
2200 skb->csum = re->skb->csum;
2201 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2202 length, PCI_DMA_FROMDEVICE);
2203 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2204 skb_put(skb, length);
14d0263f
SH		 2205 }
2206 return skb;
2207}
2208
2209/* Adjust length of skb with fragments to match received data */
2210static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2211 unsigned int length)
2212{
2213 int i, num_frags;
2214 unsigned int size;
2215
2216 /* put header into skb */
2217 size = min(length, hdr_space);
2218 skb->tail += size;
2219 skb->len += size;
2220 length -= size;
2221
2222 num_frags = skb_shinfo(skb)->nr_frags;
2223 for (i = 0; i < num_frags; i++) {
2224 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2225
2226 if (length == 0) {
2227 /* don't need this page */
2228 __free_page(frag->page);
2229 --skb_shinfo(skb)->nr_frags;
2230 } else {
2231 size = min(length, (unsigned) PAGE_SIZE);
2232
2233 frag->size = size;
2234 skb->data_len += size;
2235 skb->truesize += size;
2236 skb->len += size;
2237 length -= size;
2238 }
2239 }
2240}
2241
2242/* Normal packet - take skb from ring element and put in a new one */
2243static struct sk_buff *receive_new(struct sky2_port *sky2,
2244 struct rx_ring_info *re,
2245 unsigned int length)
2246{
2247 struct sk_buff *skb, *nskb;
2248 unsigned hdr_space = sky2->rx_data_size;
2249
14d0263f
SH		 2250 /* Don't be tricky about reusing pages (yet) */
2251 nskb = sky2_rx_alloc(sky2);
2252 if (unlikely(!nskb))
2253 return NULL;
2254
2255 skb = re->skb;
2256 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2257
2258 prefetch(skb->data);
2259 re->skb = nskb;
454e6cb6
SH		 2260 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2261 dev_kfree_skb(nskb);
2262 re->skb = skb;
2263 return NULL;
2264 }
14d0263f
SH		 2265
2266 if (skb_shinfo(skb)->nr_frags)
2267 skb_put_frags(skb, hdr_space, length);
2268 else
489b10c1 2269 skb_put(skb, length);
14d0263f
SH		 2270 return skb;
2271}
2272
cd28ab6a
SH		 2273/*
2274 * Receive one packet.
d571b694 2275 * For larger packets, get new buffer.
cd28ab6a 2276 */
497d7c86 2277static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2278 u16 length, u32 status)
2279{
497d7c86 2280 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2281 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2282 struct sk_buff *skb = NULL;
d6532232
SH		 2283 u16 count = (status & GMR_FS_LEN) >> 16;
2284
2285#ifdef SKY2_VLAN_TAG_USED
2286 /* Account for vlan tag */
2287 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2288 count -= VLAN_HLEN;
2289#endif
cd28ab6a
SH		 2290
2291 if (unlikely(netif_msg_rx_status(sky2)))
2292 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2293 dev->name, sky2->rx_next, status, length);
cd28ab6a 2294
793b883e 2295 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2296 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2297
3b12e014
SH		 2298 /* This chip has hardware problems that generates bogus status.
2299 * So do only marginal checking and expect higher level protocols
2300 * to handle crap frames.
2301 */
2302 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2303 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2304 length != count)
2305 goto okay;
2306
42eeea01 2307 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2308 goto error;
2309
42eeea01 2310 if (!(status & GMR_FS_RX_OK))
2311 goto resubmit;
2312
d6532232
SH		 2313 /* if length reported by DMA does not match PHY, packet was truncated */
2314 if (length != count)
3b12e014 2315 goto len_error;
71749531 2316
3b12e014 2317okay:
14d0263f
SH		 2318 if (length < copybreak)
2319 skb = receive_copy(sky2, re, length);
2320 else
2321 skb = receive_new(sky2, re, length);
793b883e 2322resubmit:
14d0263f 2323 sky2_rx_submit(sky2, re);
79e57d32 2324
cd28ab6a
SH		 2325 return skb;
2326
3b12e014 2327len_error:
71749531
SH		 2328 /* Truncation of overlength packets
2329 causes PHY length to not match MAC length */
7138a0f5 2330 ++dev->stats.rx_length_errors;
d6532232 2331 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2332 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2333 dev->name, status, length);
d6532232 2334 goto resubmit;
71749531 2335
cd28ab6a 2336error:
7138a0f5 2337 ++dev->stats.rx_errors;
b6d77734 2338 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2339 dev->stats.rx_over_errors++;
b6d77734
SH		 2340 goto resubmit;
2341 }
6e15b712 2342
3be92a70 2343 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2344 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2345 dev->name, status, length);
793b883e
SH		 2346
2347 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2348 dev->stats.rx_length_errors++;
cd28ab6a 2349 if (status & GMR_FS_FRAGMENT)
7138a0f5 2350 dev->stats.rx_frame_errors++;
cd28ab6a 2351 if (status & GMR_FS_CRC_ERR)
7138a0f5 2352 dev->stats.rx_crc_errors++;
79e57d32 2353
793b883e 2354 goto resubmit;
cd28ab6a
SH		 2355}
2356
e07b1aa8
SH		 2357/* Transmit complete */
2358static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2359{
e07b1aa8 2360 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2361
e07b1aa8 2362 if (netif_running(dev)) {
2bb8c262 2363 netif_tx_lock(dev);
e07b1aa8 2364 sky2_tx_complete(sky2, last);
2bb8c262 2365 netif_tx_unlock(dev);
2224795d 2366 }
cd28ab6a
SH		 2367}
2368
37e5a243
SH		 2369static inline void sky2_skb_rx(const struct sky2_port *sky2,
2370 u32 status, struct sk_buff *skb)
2371{
2372#ifdef SKY2_VLAN_TAG_USED
2373 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2374 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2375 if (skb->ip_summed == CHECKSUM_NONE)
2376 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2377 else
2378 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2379 vlan_tag, skb);
2380 return;
2381 }
2382#endif
2383 if (skb->ip_summed == CHECKSUM_NONE)
2384 netif_receive_skb(skb);
2385 else
2386 napi_gro_receive(&sky2->hw->napi, skb);
2387}
2388
bf15fe99
SH		 2389static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2390 unsigned packets, unsigned bytes)
2391{
2392 if (packets) {
2393 struct net_device *dev = hw->dev[port];
2394
2395 dev->stats.rx_packets += packets;
2396 dev->stats.rx_bytes += bytes;
2397 dev->last_rx = jiffies;
2398 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2399 }
2400}
2401
e07b1aa8 2402/* Process status response ring */
26691830 2403static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2404{
e07b1aa8 2405 int work_done = 0;
bf15fe99
SH		 2406 unsigned int total_bytes[2] = { 0 };
2407 unsigned int total_packets[2] = { 0 };
a8fd6266 2408
af2a58ac 2409 rmb();
26691830 2410 do {
55c9dd35 2411 struct sky2_port *sky2;
13210ce5 2412 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2413 unsigned port;
13210ce5 2414 struct net_device *dev;
cd28ab6a 2415 struct sk_buff *skb;
cd28ab6a
SH		 2416 u32 status;
2417 u16 length;
ab5adecb
SH		 2418 u8 opcode = le->opcode;
2419
2420 if (!(opcode & HW_OWNER))
2421 break;
cd28ab6a 2422
cb5d9547 2423 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2424
ab5adecb 2425 port = le->css & CSS_LINK_BIT;
69161611 2426 dev = hw->dev[port];
13210ce5 2427 sky2 = netdev_priv(dev);
f65b138c
SH		 2428 length = le16_to_cpu(le->length);
2429 status = le32_to_cpu(le->status);
cd28ab6a 2430
ab5adecb
SH		 2431 le->opcode = 0;
2432 switch (opcode & ~HW_OWNER) {
cd28ab6a 2433 case OP_RXSTAT:
bf15fe99
SH		 2434 total_packets[port]++;
2435 total_bytes[port] += length;
497d7c86 2436 skb = sky2_receive(dev, length, status);
3225b919 2437 if (unlikely(!skb)) {
7138a0f5 2438 dev->stats.rx_dropped++;
55c9dd35 2439 break;
3225b919 2440 }
13210ce5 2441
69161611 2442 /* This chip reports checksum status differently */
05745c4a 2443 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2444 if (sky2->rx_csum &&
2445 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2446 (le->css & CSS_TCPUDPCSOK))
2447 skb->ip_summed = CHECKSUM_UNNECESSARY;
2448 else
2449 skb->ip_summed = CHECKSUM_NONE;
2450 }
2451
13210ce5 2452 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2453
37e5a243 2454 sky2_skb_rx(sky2, status, skb);
13210ce5 2455
22e11703 2456 /* Stop after net poll weight */
13210ce5 2457 if (++work_done >= to_do)
2458 goto exit_loop;
cd28ab6a
SH		 2459 break;
2460
d1f13708 2461#ifdef SKY2_VLAN_TAG_USED
2462 case OP_RXVLAN:
2463 sky2->rx_tag = length;
2464 break;
2465
2466 case OP_RXCHKSVLAN:
2467 sky2->rx_tag = length;
2468 /* fall through */
2469#endif
cd28ab6a 2470 case OP_RXCHKS:
87418307
SH		 2471 if (!sky2->rx_csum)
2472 break;
2473
05745c4a
SH		 2474 /* If this happens then driver assuming wrong format */
2475 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2476 if (net_ratelimit())
2477 printk(KERN_NOTICE "%s: unexpected"
2478 " checksum status\n",
2479 dev->name);
69161611 2480 break;
05745c4a 2481 }
69161611 2482
87418307
SH		 2483 /* Both checksum counters are programmed to start at
2484 * the same offset, so unless there is a problem they
2485 * should match. This failure is an early indication that
2486 * hardware receive checksumming won't work.
2487 */
2488 if (likely(status >> 16 == (status & 0xffff))) {
2489 skb = sky2->rx_ring[sky2->rx_next].skb;
2490 skb->ip_summed = CHECKSUM_COMPLETE;
b9389796 2491 skb->csum = le16_to_cpu(status);
87418307
SH		 2492 } else {
2493 printk(KERN_NOTICE PFX "%s: hardware receive "
2494 "checksum problem (status = %#x)\n",
2495 dev->name, status);
2496 sky2->rx_csum = 0;
2497 sky2_write32(sky2->hw,
69161611 2498 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2499 BMU_DIS_RX_CHKSUM);
2500 }
cd28ab6a
SH		 2501 break;
2502
2503 case OP_TXINDEXLE:
13b97b74 2504 /* TX index reports status for both ports */
f55925d7
SH		 2505 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2506 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2507 if (hw->dev[1])
2508 sky2_tx_done(hw->dev[1],
2509 ((status >> 24) & 0xff)
2510 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2511 break;
2512
cd28ab6a
SH		 2513 default:
2514 if (net_ratelimit())
793b883e 2515 printk(KERN_WARNING PFX
ab5adecb 2516 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2517 }
26691830 2518 } while (hw->st_idx != idx);
cd28ab6a 2519
fe2a24df
SH		 2520 /* Fully processed status ring so clear irq */
2521 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2522
13210ce5 2523exit_loop:
bf15fe99
SH		 2524 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2525 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2526
e07b1aa8 2527 return work_done;
cd28ab6a
SH		 2528}
2529
2530static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2531{
2532 struct net_device *dev = hw->dev[port];
2533
3be92a70
SH		 2534 if (net_ratelimit())
2535 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2536 dev->name, status);
cd28ab6a
SH		 2537
2538 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2539 if (net_ratelimit())
2540 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2541 dev->name);
cd28ab6a
SH		 2542 /* Clear IRQ */
2543 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2544 }
2545
2546 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2547 if (net_ratelimit())
2548 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2549 dev->name);
cd28ab6a
SH		 2550
2551 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2552 }
2553
2554 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2555 if (net_ratelimit())
2556 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2557 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2558 }
2559
2560 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2561 if (net_ratelimit())
2562 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2563 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2564 }
2565
2566 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2567 if (net_ratelimit())
2568 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2569 dev->name);
cd28ab6a
SH		 2570 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2571 }
2572}
2573
2574static void sky2_hw_intr(struct sky2_hw *hw)
2575{
555382cb 2576 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2577 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2578 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2579
2580 status &= hwmsk;
cd28ab6a 2581
793b883e 2582 if (status & Y2_IS_TIST_OV)
cd28ab6a 2583 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2584
2585 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2586 u16 pci_err;
2587
82637e80 2588 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2589 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2590 if (net_ratelimit())
555382cb 2591 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2592 pci_err);
cd28ab6a 2593
b32f40c4 2594 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2595 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2596 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2597 }
2598
2599 if (status & Y2_IS_PCI_EXP) {
d571b694 2600 /* PCI-Express uncorrectable Error occurred */
555382cb 2601 u32 err;
cd28ab6a 2602
82637e80 2603 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2604 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2605 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2606 0xfffffffful);
3be92a70 2607 if (net_ratelimit())
555382cb 2608 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2609
7782c8c4 2610 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2611 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2612 }
2613
2614 if (status & Y2_HWE_L1_MASK)
2615 sky2_hw_error(hw, 0, status);
2616 status >>= 8;
2617 if (status & Y2_HWE_L1_MASK)
2618 sky2_hw_error(hw, 1, status);
2619}
2620
2621static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2622{
2623 struct net_device *dev = hw->dev[port];
2624 struct sky2_port *sky2 = netdev_priv(dev);
2625 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2626
2627 if (netif_msg_intr(sky2))
2628 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2629 dev->name, status);
2630
a3caeada
SH		 2631 if (status & GM_IS_RX_CO_OV)
2632 gma_read16(hw, port, GM_RX_IRQ_SRC);
2633
2634 if (status & GM_IS_TX_CO_OV)
2635 gma_read16(hw, port, GM_TX_IRQ_SRC);
2636
cd28ab6a 2637 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2638 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2639 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2640 }
2641
2642 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2643 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2644 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2645 }
cd28ab6a
SH		 2646}
2647
40b01727
SH		 2648/* This should never happen it is a bug. */
2649static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2650 u16 q, unsigned ring_size)
d257924e
SH		 2651{
2652 struct net_device *dev = hw->dev[port];
2653 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2654 unsigned idx;
2655 const u64 *le = (q == Q_R1 || q == Q_R2)
2656 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2657
40b01727
SH		 2658 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2659 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2660 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2661 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2662
40b01727 2663 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2664}
cd28ab6a 2665
75e80683
SH		 2666static int sky2_rx_hung(struct net_device *dev)
2667{
2668 struct sky2_port *sky2 = netdev_priv(dev);
2669 struct sky2_hw *hw = sky2->hw;
2670 unsigned port = sky2->port;
2671 unsigned rxq = rxqaddr[port];
2672 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2673 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2674 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2675 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2676
2677 /* If idle and MAC or PCI is stuck */
2678 if (sky2->check.last == dev->last_rx &&
2679 ((mac_rp == sky2->check.mac_rp &&
2680 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2681 /* Check if the PCI RX hang */
2682 (fifo_rp == sky2->check.fifo_rp &&
2683 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2684 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2685 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2686 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2687 return 1;
2688 } else {
2689 sky2->check.last = dev->last_rx;
2690 sky2->check.mac_rp = mac_rp;
2691 sky2->check.mac_lev = mac_lev;
2692 sky2->check.fifo_rp = fifo_rp;
2693 sky2->check.fifo_lev = fifo_lev;
2694 return 0;
2695 }
2696}
2697
32c2c300 2698static void sky2_watchdog(unsigned long arg)
d27ed387 2699{
01bd7564 2700 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2701
75e80683 2702 /* Check for lost IRQ once a second */
32c2c300 2703 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2704 napi_schedule(&hw->napi);
75e80683
SH		 2705 } else {
2706 int i, active = 0;
2707
2708 for (i = 0; i < hw->ports; i++) {
bea3348e 2709 struct net_device *dev = hw->dev[i];
75e80683
SH		 2710 if (!netif_running(dev))
2711 continue;
2712 ++active;
2713
2714 /* For chips with Rx FIFO, check if stuck */
39dbd958 2715 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2716 sky2_rx_hung(dev)) {
2717 pr_info(PFX "%s: receiver hang detected\n",
2718 dev->name);
2719 schedule_work(&hw->restart_work);
2720 return;
2721 }
2722 }
2723
2724 if (active == 0)
2725 return;
32c2c300 2726 }
01bd7564 2727
75e80683 2728 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2729}
2730
40b01727
SH		 2731/* Hardware/software error handling */
2732static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2733{
40b01727
SH		 2734 if (net_ratelimit())
2735 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2736
1e5f1283
SH		 2737 if (status & Y2_IS_HW_ERR)
2738 sky2_hw_intr(hw);
d257924e 2739
1e5f1283
SH		 2740 if (status & Y2_IS_IRQ_MAC1)
2741 sky2_mac_intr(hw, 0);
cd28ab6a 2742
1e5f1283
SH		 2743 if (status & Y2_IS_IRQ_MAC2)
2744 sky2_mac_intr(hw, 1);
cd28ab6a 2745
1e5f1283 2746 if (status & Y2_IS_CHK_RX1)
40b01727 2747 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2748
1e5f1283 2749 if (status & Y2_IS_CHK_RX2)
40b01727 2750 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2751
1e5f1283 2752 if (status & Y2_IS_CHK_TXA1)
40b01727 2753 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2754
1e5f1283 2755 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2756 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2757}
2758
bea3348e 2759static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2760{
bea3348e 2761 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2762 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2763 int work_done = 0;
26691830 2764 u16 idx;
40b01727
SH		 2765
2766 if (unlikely(status & Y2_IS_ERROR))
2767 sky2_err_intr(hw, status);
2768
2769 if (status & Y2_IS_IRQ_PHY1)
2770 sky2_phy_intr(hw, 0);
2771
2772 if (status & Y2_IS_IRQ_PHY2)
2773 sky2_phy_intr(hw, 1);
cd28ab6a 2774
26691830
SH		 2775 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2776 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2777
2778 if (work_done >= work_limit)
26691830
SH		 2779 goto done;
2780 }
6f535763 2781
26691830
SH		 2782 napi_complete(napi);
2783 sky2_read32(hw, B0_Y2_SP_LISR);
2784done:
6f535763 2785
bea3348e 2786 return work_done;
e07b1aa8
SH		 2787}
2788
7d12e780 2789static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2790{
2791 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2792 u32 status;
2793
2794 /* Reading this mask interrupts as side effect */
2795 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2796 if (status == 0 || status == ~0)
2797 return IRQ_NONE;
793b883e 2798
e07b1aa8 2799 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2800
2801 napi_schedule(&hw->napi);
793b883e 2802
cd28ab6a
SH		 2803 return IRQ_HANDLED;
2804}
2805
2806#ifdef CONFIG_NET_POLL_CONTROLLER
2807static void sky2_netpoll(struct net_device *dev)
2808{
2809 struct sky2_port *sky2 = netdev_priv(dev);
2810
bea3348e 2811 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2812}
2813#endif
2814
2815/* Chip internal frequency for clock calculations */
05745c4a 2816static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2817{
793b883e 2818 switch (hw->chip_id) {
cd28ab6a 2819 case CHIP_ID_YUKON_EC:
5a5b1ea0 2820 case CHIP_ID_YUKON_EC_U:
93745494 2821 case CHIP_ID_YUKON_EX:
ed4d4161 2822 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2823 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2824 return 125;
2825
cd28ab6a 2826 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2827 return 100;
2828
2829 case CHIP_ID_YUKON_FE_P:
2830 return 50;
2831
2832 case CHIP_ID_YUKON_XL:
2833 return 156;
2834
2835 default:
2836 BUG();
cd28ab6a
SH		 2837 }
2838}
2839
fb17358f 2840static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2841{
fb17358f 2842 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2843}
2844
fb17358f 2845static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2846{
fb17358f 2847 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2848}
2849
fb17358f 2850
e3173832 2851static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2852{
b89165f2 2853 u8 t8;
cd28ab6a 2854
167f53d0 2855 /* Enable all clocks and check for bad PCI access */
b32f40c4 2856 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2857
cd28ab6a 2858 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2859
cd28ab6a 2860 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2861 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2862
2863 switch(hw->chip_id) {
2864 case CHIP_ID_YUKON_XL:
39dbd958 2865 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2866 break;
2867
2868 case CHIP_ID_YUKON_EC_U:
2869 hw->flags = SKY2_HW_GIGABIT
2870 | SKY2_HW_NEWER_PHY
2871 | SKY2_HW_ADV_POWER_CTL;
2872 break;
2873
2874 case CHIP_ID_YUKON_EX:
2875 hw->flags = SKY2_HW_GIGABIT
2876 | SKY2_HW_NEWER_PHY
2877 | SKY2_HW_NEW_LE
2878 | SKY2_HW_ADV_POWER_CTL;
2879
2880 /* New transmit checksum */
2881 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2882 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2883 break;
2884
2885 case CHIP_ID_YUKON_EC:
2886 /* This rev is really old, and requires untested workarounds */
2887 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2888 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2889 return -EOPNOTSUPP;
2890 }
39dbd958 2891 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2892 break;
2893
2894 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2895 break;
2896
05745c4a
SH		 2897 case CHIP_ID_YUKON_FE_P:
2898 hw->flags = SKY2_HW_NEWER_PHY
2899 | SKY2_HW_NEW_LE
2900 | SKY2_HW_AUTO_TX_SUM
2901 | SKY2_HW_ADV_POWER_CTL;
2902 break;
ed4d4161
SH		 2903
2904 case CHIP_ID_YUKON_SUPR:
2905 hw->flags = SKY2_HW_GIGABIT
2906 | SKY2_HW_NEWER_PHY
2907 | SKY2_HW_NEW_LE
2908 | SKY2_HW_AUTO_TX_SUM
2909 | SKY2_HW_ADV_POWER_CTL;
2910 break;
2911
0ce8b98d
SH		 2912 case CHIP_ID_YUKON_UL_2:
2913 hw->flags = SKY2_HW_GIGABIT
2914 | SKY2_HW_ADV_POWER_CTL;
2915 break;
2916
ea76e635 2917 default:
b02a9258
SH		 2918 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2919 hw->chip_id);
cd28ab6a
SH		 2920 return -EOPNOTSUPP;
2921 }
2922
ea76e635
SH		 2923 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2924 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2925 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2926
e3173832
SH		 2927 hw->ports = 1;
2928 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2929 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2930 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2931 ++hw->ports;
2932 }
2933
2934 return 0;
2935}
2936
2937static void sky2_reset(struct sky2_hw *hw)
2938{
555382cb 2939 struct pci_dev *pdev = hw->pdev;
e3173832 2940 u16 status;
555382cb
SH		 2941 int i, cap;
2942 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2943
cd28ab6a 2944 /* disable ASF */
4f44d8ba
SH		 2945 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2946 status = sky2_read16(hw, HCU_CCSR);
2947 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2948 HCU_CCSR_UC_STATE_MSK);
2949 sky2_write16(hw, HCU_CCSR, status);
2950 } else
2951 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2952 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2953
2954 /* do a SW reset */
2955 sky2_write8(hw, B0_CTST, CS_RST_SET);
2956 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2957
ac93a394
SH		 2958 /* allow writes to PCI config */
2959 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2960
cd28ab6a 2961 /* clear PCI errors, if any */
b32f40c4 2962 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2963 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2964 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2965
2966 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2967
555382cb
SH		 2968 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2969 if (cap) {
7782c8c4
SH		 2970 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2971 0xfffffffful);
555382cb
SH		 2972
2973 /* If error bit is stuck on ignore it */
2974 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2975 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2976 else
555382cb
SH		 2977 hwe_mask |= Y2_IS_PCI_EXP;
2978 }
cd28ab6a 2979
ae306cca 2980 sky2_power_on(hw);
82637e80 2981 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2982
2983 for (i = 0; i < hw->ports; i++) {
2984 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2985 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2986
ed4d4161
SH		 2987 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2988 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2989 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2990 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2991 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2992 }
2993
793b883e
SH		 2994 /* Clear I2C IRQ noise */
2995 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2996
2997 /* turn off hardware timer (unused) */
2998 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2999 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3000
cd28ab6a
SH		 3001 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
3002
69634ee7
SH		 3003 /* Turn off descriptor polling */
3004 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3005
3006 /* Turn off receive timestamp */
3007 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3008 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3009
3010 /* enable the Tx Arbiters */
3011 for (i = 0; i < hw->ports; i++)
3012 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3013
3014 /* Initialize ram interface */
3015 for (i = 0; i < hw->ports; i++) {
793b883e 3016 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3017
3018 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3019 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3020 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3021 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3022 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3023 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3024 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3025 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3026 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3027 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3028 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3029 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3030 }
3031
555382cb 3032 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3033
cd28ab6a 3034 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3035 sky2_gmac_reset(hw, i);
cd28ab6a 3036
cd28ab6a
SH		 3037 memset(hw->st_le, 0, STATUS_LE_BYTES);
3038 hw->st_idx = 0;
3039
3040 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3041 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3042
3043 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3044 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3045
3046 /* Set the list last index */
793b883e 3047 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3048
290d4de5
SH		 3049 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3050 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3051
290d4de5
SH		 3052 /* set Status-FIFO ISR watermark */
3053 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3054 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3055 else
3056 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3057
290d4de5 3058 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3059 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3060 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3061
793b883e 3062 /* enable status unit */
cd28ab6a
SH		 3063 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3064
3065 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3066 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3067 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3068}
3069
81906791
SH		 3070static void sky2_restart(struct work_struct *work)
3071{
3072 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3073 struct net_device *dev;
3074 int i, err;
3075
81906791 3076 rtnl_lock();
81906791
SH		 3077 for (i = 0; i < hw->ports; i++) {
3078 dev = hw->dev[i];
3079 if (netif_running(dev))
3080 sky2_down(dev);
3081 }
3082
8cfcbe99
SH		 3083 napi_disable(&hw->napi);
3084 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3085 sky2_reset(hw);
3086 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3087 napi_enable(&hw->napi);
81906791
SH		 3088
3089 for (i = 0; i < hw->ports; i++) {
3090 dev = hw->dev[i];
3091 if (netif_running(dev)) {
3092 err = sky2_up(dev);
3093 if (err) {
3094 printk(KERN_INFO PFX "%s: could not restart %d\n",
3095 dev->name, err);
3096 dev_close(dev);
3097 }
3098 }
3099 }
3100
81906791
SH		 3101 rtnl_unlock();
3102}
3103
e3173832
SH		 3104static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3105{
3106 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3107}
3108
3109static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3110{
3111 const struct sky2_port *sky2 = netdev_priv(dev);
3112
3113 wol->supported = sky2_wol_supported(sky2->hw);
3114 wol->wolopts = sky2->wol;
3115}
3116
3117static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3118{
3119 struct sky2_port *sky2 = netdev_priv(dev);
3120 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3121
9d731d77
RW		 3122 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3123 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3124 return -EOPNOTSUPP;
3125
3126 sky2->wol = wol->wolopts;
3127
05745c4a
SH		 3128 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3129 hw->chip_id == CHIP_ID_YUKON_EX ||
3130 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3131 sky2_write32(hw, B0_CTST, sky2->wol
3132 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3133
9d731d77
RW		 3134 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3135
e3173832
SH		 3136 if (!netif_running(dev))
3137 sky2_wol_init(sky2);
cd28ab6a
SH		 3138 return 0;
3139}
3140
28bd181a 3141static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3142{
b89165f2
SH		 3143 if (sky2_is_copper(hw)) {
3144 u32 modes = SUPPORTED_10baseT_Half
3145 | SUPPORTED_10baseT_Full
3146 | SUPPORTED_100baseT_Half
3147 | SUPPORTED_100baseT_Full
3148 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3149
ea76e635 3150 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3151 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3152 | SUPPORTED_1000baseT_Full;
3153 return modes;
cd28ab6a 3154 } else
b89165f2
SH		 3155 return SUPPORTED_1000baseT_Half
3156 | SUPPORTED_1000baseT_Full
3157 | SUPPORTED_Autoneg
3158 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3159}
3160
793b883e 3161static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3162{
3163 struct sky2_port *sky2 = netdev_priv(dev);
3164 struct sky2_hw *hw = sky2->hw;
3165
3166 ecmd->transceiver = XCVR_INTERNAL;
3167 ecmd->supported = sky2_supported_modes(hw);
3168 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3169 if (sky2_is_copper(hw)) {
cd28ab6a 3170 ecmd->port = PORT_TP;
b89165f2
SH		 3171 ecmd->speed = sky2->speed;
3172 } else {
3173 ecmd->speed = SPEED_1000;
cd28ab6a 3174 ecmd->port = PORT_FIBRE;
b89165f2 3175 }
cd28ab6a
SH		 3176
3177 ecmd->advertising = sky2->advertising;
3178 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3179 ecmd->duplex = sky2->duplex;
3180 return 0;
3181}
3182
3183static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3184{
3185 struct sky2_port *sky2 = netdev_priv(dev);
3186 const struct sky2_hw *hw = sky2->hw;
3187 u32 supported = sky2_supported_modes(hw);
3188
3189 if (ecmd->autoneg == AUTONEG_ENABLE) {
3190 ecmd->advertising = supported;
3191 sky2->duplex = -1;
3192 sky2->speed = -1;
3193 } else {
3194 u32 setting;
3195
793b883e 3196 switch (ecmd->speed) {
cd28ab6a
SH		 3197 case SPEED_1000:
3198 if (ecmd->duplex == DUPLEX_FULL)
3199 setting = SUPPORTED_1000baseT_Full;
3200 else if (ecmd->duplex == DUPLEX_HALF)
3201 setting = SUPPORTED_1000baseT_Half;
3202 else
3203 return -EINVAL;
3204 break;
3205 case SPEED_100:
3206 if (ecmd->duplex == DUPLEX_FULL)
3207 setting = SUPPORTED_100baseT_Full;
3208 else if (ecmd->duplex == DUPLEX_HALF)
3209 setting = SUPPORTED_100baseT_Half;
3210 else
3211 return -EINVAL;
3212 break;
3213
3214 case SPEED_10:
3215 if (ecmd->duplex == DUPLEX_FULL)
3216 setting = SUPPORTED_10baseT_Full;
3217 else if (ecmd->duplex == DUPLEX_HALF)
3218 setting = SUPPORTED_10baseT_Half;
3219 else
3220 return -EINVAL;
3221 break;
3222 default:
3223 return -EINVAL;
3224 }
3225
3226 if ((setting & supported) == 0)
3227 return -EINVAL;
3228
3229 sky2->speed = ecmd->speed;
3230 sky2->duplex = ecmd->duplex;
3231 }
3232
3233 sky2->autoneg = ecmd->autoneg;
3234 sky2->advertising = ecmd->advertising;
3235
d1b139c0 3236 if (netif_running(dev)) {
1b537565 3237 sky2_phy_reinit(sky2);
d1b139c0
SH		 3238 sky2_set_multicast(dev);
3239 }
cd28ab6a
SH		 3240
3241 return 0;
3242}
3243
3244static void sky2_get_drvinfo(struct net_device *dev,
3245 struct ethtool_drvinfo *info)
3246{
3247 struct sky2_port *sky2 = netdev_priv(dev);
3248
3249 strcpy(info->driver, DRV_NAME);
3250 strcpy(info->version, DRV_VERSION);
3251 strcpy(info->fw_version, "N/A");
3252 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3253}
3254
3255static const struct sky2_stat {
793b883e
SH		 3256 char name[ETH_GSTRING_LEN];
3257 u16 offset;
cd28ab6a
SH		 3258} sky2_stats[] = {
3259 { "tx_bytes", GM_TXO_OK_HI },
3260 { "rx_bytes", GM_RXO_OK_HI },
3261 { "tx_broadcast", GM_TXF_BC_OK },
3262 { "rx_broadcast", GM_RXF_BC_OK },
3263 { "tx_multicast", GM_TXF_MC_OK },
3264 { "rx_multicast", GM_RXF_MC_OK },
3265 { "tx_unicast", GM_TXF_UC_OK },
3266 { "rx_unicast", GM_RXF_UC_OK },
3267 { "tx_mac_pause", GM_TXF_MPAUSE },
3268 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3269 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3270 { "late_collision",GM_TXF_LAT_COL },
3271 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3272 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3273 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3274
d2604540 3275 { "rx_short", GM_RXF_SHT },
cd28ab6a 3276 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3277 { "rx_64_byte_packets", GM_RXF_64B },
3278 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3279 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3280 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3281 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3282 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3283 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3284 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3285 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3286 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3287 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3288
3289 { "tx_64_byte_packets", GM_TXF_64B },
3290 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3291 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3292 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3293 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3294 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3295 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3296 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3297};
3298
cd28ab6a
SH		 3299static u32 sky2_get_rx_csum(struct net_device *dev)
3300{
3301 struct sky2_port *sky2 = netdev_priv(dev);
3302
3303 return sky2->rx_csum;
3304}
3305
3306static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3307{
3308 struct sky2_port *sky2 = netdev_priv(dev);
3309
3310 sky2->rx_csum = data;
793b883e 3311
cd28ab6a
SH		 3312 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3313 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3314
3315 return 0;
3316}
3317
3318static u32 sky2_get_msglevel(struct net_device *netdev)
3319{
3320 struct sky2_port *sky2 = netdev_priv(netdev);
3321 return sky2->msg_enable;
3322}
3323
9a7ae0a9
SH		 3324static int sky2_nway_reset(struct net_device *dev)
3325{
3326 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3327
16ad91e1 3328 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3329 return -EINVAL;
3330
1b537565 3331 sky2_phy_reinit(sky2);
d1b139c0 3332 sky2_set_multicast(dev);
9a7ae0a9
SH		 3333
3334 return 0;
3335}
3336
793b883e 3337static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3338{
3339 struct sky2_hw *hw = sky2->hw;
3340 unsigned port = sky2->port;
3341 int i;
3342
3343 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3344 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3345 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3346 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3347
793b883e 3348 for (i = 2; i < count; i++)
cd28ab6a
SH		 3349 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3350}
3351
cd28ab6a
SH		 3352static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3353{
3354 struct sky2_port *sky2 = netdev_priv(netdev);
3355 sky2->msg_enable = value;
3356}
3357
b9f2c044 3358static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3359{
b9f2c044
JG		 3360 switch (sset) {
3361 case ETH_SS_STATS:
3362 return ARRAY_SIZE(sky2_stats);
3363 default:
3364 return -EOPNOTSUPP;
3365 }
cd28ab6a
SH		 3366}
3367
3368static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3369 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3370{
3371 struct sky2_port *sky2 = netdev_priv(dev);
3372
793b883e 3373 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3374}
3375
793b883e 3376static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3377{
3378 int i;
3379
3380 switch (stringset) {
3381 case ETH_SS_STATS:
3382 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3383 memcpy(data + i * ETH_GSTRING_LEN,
3384 sky2_stats[i].name, ETH_GSTRING_LEN);
3385 break;
3386 }
3387}
3388
cd28ab6a
SH		 3389static int sky2_set_mac_address(struct net_device *dev, void *p)
3390{
3391 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3392 struct sky2_hw *hw = sky2->hw;
3393 unsigned port = sky2->port;
3394 const struct sockaddr *addr = p;
cd28ab6a
SH		 3395
3396 if (!is_valid_ether_addr(addr->sa_data))
3397 return -EADDRNOTAVAIL;
3398
cd28ab6a 3399 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3400 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3401 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3402 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3403 dev->dev_addr, ETH_ALEN);
1b537565 3404
a8ab1ec0
SH		 3405 /* virtual address for data */
3406 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3407
3408 /* physical address: used for pause frames */
3409 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3410
3411 return 0;
cd28ab6a
SH		 3412}
3413
a052b52f
SH		 3414static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3415{
3416 u32 bit;
3417
3418 bit = ether_crc(ETH_ALEN, addr) & 63;
3419 filter[bit >> 3] |= 1 << (bit & 7);
3420}
3421
cd28ab6a
SH		 3422static void sky2_set_multicast(struct net_device *dev)
3423{
3424 struct sky2_port *sky2 = netdev_priv(dev);
3425 struct sky2_hw *hw = sky2->hw;
3426 unsigned port = sky2->port;
3427 struct dev_mc_list *list = dev->mc_list;
3428 u16 reg;
3429 u8 filter[8];
a052b52f
SH		 3430 int rx_pause;
3431 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3432
a052b52f 3433 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3434 memset(filter, 0, sizeof(filter));
3435
3436 reg = gma_read16(hw, port, GM_RX_CTRL);
3437 reg |= GM_RXCR_UCF_ENA;
3438
d571b694 3439 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3440 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3441 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3442 memset(filter, 0xff, sizeof(filter));
a052b52f 3443 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3444 reg &= ~GM_RXCR_MCF_ENA;
3445 else {
3446 int i;
3447 reg |= GM_RXCR_MCF_ENA;
3448
a052b52f
SH		 3449 if (rx_pause)
3450 sky2_add_filter(filter, pause_mc_addr);
3451
3452 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3453 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3454 }
3455
cd28ab6a 3456 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3457 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3458 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3459 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3460 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3461 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3462 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3463 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3464
3465 gma_write16(hw, port, GM_RX_CTRL, reg);
3466}
3467
3468/* Can have one global because blinking is controlled by
3469 * ethtool and that is always under RTNL mutex
3470 */
a84d0a3d 3471static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3472{
a84d0a3d
SH		 3473 struct sky2_hw *hw = sky2->hw;
3474 unsigned port = sky2->port;
793b883e 3475
a84d0a3d
SH		 3476 spin_lock_bh(&sky2->phy_lock);
3477 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3478 hw->chip_id == CHIP_ID_YUKON_EX ||
3479 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3480 u16 pg;
793b883e
SH		 3481 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3482 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3483
a84d0a3d
SH		 3484 switch (mode) {
3485 case MO_LED_OFF:
3486 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3487 PHY_M_LEDC_LOS_CTRL(8) |
3488 PHY_M_LEDC_INIT_CTRL(8) |
3489 PHY_M_LEDC_STA1_CTRL(8) |
3490 PHY_M_LEDC_STA0_CTRL(8));
3491 break;
3492 case MO_LED_ON:
3493 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3494 PHY_M_LEDC_LOS_CTRL(9) |
3495 PHY_M_LEDC_INIT_CTRL(9) |
3496 PHY_M_LEDC_STA1_CTRL(9) |
3497 PHY_M_LEDC_STA0_CTRL(9));
3498 break;
3499 case MO_LED_BLINK:
3500 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3501 PHY_M_LEDC_LOS_CTRL(0xa) |
3502 PHY_M_LEDC_INIT_CTRL(0xa) |
3503 PHY_M_LEDC_STA1_CTRL(0xa) |
3504 PHY_M_LEDC_STA0_CTRL(0xa));
3505 break;
3506 case MO_LED_NORM:
3507 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3508 PHY_M_LEDC_LOS_CTRL(1) |
3509 PHY_M_LEDC_INIT_CTRL(8) |
3510 PHY_M_LEDC_STA1_CTRL(7) |
3511 PHY_M_LEDC_STA0_CTRL(7));
3512 }
793b883e 3513
a84d0a3d
SH		 3514 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3515 } else
7d2e3cb7 3516 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3517 PHY_M_LED_MO_DUP(mode) |
3518 PHY_M_LED_MO_10(mode) |
3519 PHY_M_LED_MO_100(mode) |
3520 PHY_M_LED_MO_1000(mode) |
3521 PHY_M_LED_MO_RX(mode) |
3522 PHY_M_LED_MO_TX(mode));
3523
3524 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3525}
3526
3527/* blink LED's for finding board */
3528static int sky2_phys_id(struct net_device *dev, u32 data)
3529{
3530 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3531 unsigned int i;
cd28ab6a 3532
a84d0a3d
SH		 3533 if (data == 0)
3534 data = UINT_MAX;
cd28ab6a 3535
a84d0a3d
SH		 3536 for (i = 0; i < data; i++) {
3537 sky2_led(sky2, MO_LED_ON);
3538 if (msleep_interruptible(500))
3539 break;
3540 sky2_led(sky2, MO_LED_OFF);
3541 if (msleep_interruptible(500))
3542 break;
793b883e 3543 }
a84d0a3d 3544 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3545
3546 return 0;
3547}
3548
3549static void sky2_get_pauseparam(struct net_device *dev,
3550 struct ethtool_pauseparam *ecmd)
3551{
3552 struct sky2_port *sky2 = netdev_priv(dev);
3553
16ad91e1
SH		 3554 switch (sky2->flow_mode) {
3555 case FC_NONE:
3556 ecmd->tx_pause = ecmd->rx_pause = 0;
3557 break;
3558 case FC_TX:
3559 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3560 break;
3561 case FC_RX:
3562 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3563 break;
3564 case FC_BOTH:
3565 ecmd->tx_pause = ecmd->rx_pause = 1;
3566 }
3567
cd28ab6a
SH		 3568 ecmd->autoneg = sky2->autoneg;
3569}
3570
3571static int sky2_set_pauseparam(struct net_device *dev,
3572 struct ethtool_pauseparam *ecmd)
3573{
3574 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3575
3576 sky2->autoneg = ecmd->autoneg;
16ad91e1 3577 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3578
16ad91e1
SH		 3579 if (netif_running(dev))
3580 sky2_phy_reinit(sky2);
cd28ab6a 3581
2eaba1a2 3582 return 0;
cd28ab6a
SH		 3583}
3584
fb17358f
SH		 3585static int sky2_get_coalesce(struct net_device *dev,
3586 struct ethtool_coalesce *ecmd)
3587{
3588 struct sky2_port *sky2 = netdev_priv(dev);
3589 struct sky2_hw *hw = sky2->hw;
3590
3591 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3592 ecmd->tx_coalesce_usecs = 0;
3593 else {
3594 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3595 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3596 }
3597 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3598
3599 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3600 ecmd->rx_coalesce_usecs = 0;
3601 else {
3602 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3603 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3604 }
3605 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3606
3607 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3608 ecmd->rx_coalesce_usecs_irq = 0;
3609 else {
3610 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3611 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3612 }
3613
3614 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3615
3616 return 0;
3617}
3618
3619/* Note: this affect both ports */
3620static int sky2_set_coalesce(struct net_device *dev,
3621 struct ethtool_coalesce *ecmd)
3622{
3623 struct sky2_port *sky2 = netdev_priv(dev);
3624 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3625 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3626
77b3d6a2
SH		 3627 if (ecmd->tx_coalesce_usecs > tmax ||
3628 ecmd->rx_coalesce_usecs > tmax ||
3629 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3630 return -EINVAL;
3631
ff81fbbe 3632 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3633 return -EINVAL;
ff81fbbe 3634 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3635 return -EINVAL;
ff81fbbe 3636 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3637 return -EINVAL;
3638
3639 if (ecmd->tx_coalesce_usecs == 0)
3640 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3641 else {
3642 sky2_write32(hw, STAT_TX_TIMER_INI,
3643 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3644 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3645 }
3646 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3647
3648 if (ecmd->rx_coalesce_usecs == 0)
3649 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3650 else {
3651 sky2_write32(hw, STAT_LEV_TIMER_INI,
3652 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3653 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3654 }
3655 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3656
3657 if (ecmd->rx_coalesce_usecs_irq == 0)
3658 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3659 else {
d28d4870 3660 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3661 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3662 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3663 }
3664 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3665 return 0;
3666}
3667
793b883e
SH		 3668static void sky2_get_ringparam(struct net_device *dev,
3669 struct ethtool_ringparam *ering)
3670{
3671 struct sky2_port *sky2 = netdev_priv(dev);
3672
3673 ering->rx_max_pending = RX_MAX_PENDING;
3674 ering->rx_mini_max_pending = 0;
3675 ering->rx_jumbo_max_pending = 0;
3676 ering->tx_max_pending = TX_RING_SIZE - 1;
3677
3678 ering->rx_pending = sky2->rx_pending;
3679 ering->rx_mini_pending = 0;
3680 ering->rx_jumbo_pending = 0;
3681 ering->tx_pending = sky2->tx_pending;
3682}
3683
3684static int sky2_set_ringparam(struct net_device *dev,
3685 struct ethtool_ringparam *ering)
3686{
3687 struct sky2_port *sky2 = netdev_priv(dev);
3688 int err = 0;
3689
3690 if (ering->rx_pending > RX_MAX_PENDING ||
3691 ering->rx_pending < 8 ||
3692 ering->tx_pending < MAX_SKB_TX_LE ||
3693 ering->tx_pending > TX_RING_SIZE - 1)
3694 return -EINVAL;
3695
3696 if (netif_running(dev))
3697 sky2_down(dev);
3698
3699 sky2->rx_pending = ering->rx_pending;
3700 sky2->tx_pending = ering->tx_pending;
3701
1b537565 3702 if (netif_running(dev)) {
793b883e 3703 err = sky2_up(dev);
1b537565
SH		 3704 if (err)
3705 dev_close(dev);
3706 }
793b883e
SH		 3707
3708 return err;
3709}
3710
793b883e
SH		 3711static int sky2_get_regs_len(struct net_device *dev)
3712{
6e4cbb34 3713 return 0x4000;
793b883e
SH		 3714}
3715
3716/*
3717 * Returns copy of control register region
3ead5db7 3718 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3719 */
3720static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3721 void *p)
3722{
3723 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3724 const void __iomem *io = sky2->hw->regs;
295b54c4 3725 unsigned int b;
793b883e
SH		 3726
3727 regs->version = 1;
793b883e 3728
295b54c4
SH		 3729 for (b = 0; b < 128; b++) {
3730 /* This complicated switch statement is to make sure and
3731 * only access regions that are unreserved.
3732 * Some blocks are only valid on dual port cards.
3733 * and block 3 has some special diagnostic registers that
3734 * are poison.
3735 */
3736 switch (b) {
3737 case 3:
3738 /* skip diagnostic ram region */
3739 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3740 break;
3ead5db7 3741
295b54c4
SH		 3742 /* dual port cards only */
3743 case 5: /* Tx Arbiter 2 */
3744 case 9: /* RX2 */
3745 case 14 ... 15: /* TX2 */
3746 case 17: case 19: /* Ram Buffer 2 */
3747 case 22 ... 23: /* Tx Ram Buffer 2 */
3748 case 25: /* Rx MAC Fifo 1 */
3749 case 27: /* Tx MAC Fifo 2 */
3750 case 31: /* GPHY 2 */
3751 case 40 ... 47: /* Pattern Ram 2 */
3752 case 52: case 54: /* TCP Segmentation 2 */
3753 case 112 ... 116: /* GMAC 2 */
3754 if (sky2->hw->ports == 1)
3755 goto reserved;
3756 /* fall through */
3757 case 0: /* Control */
3758 case 2: /* Mac address */
3759 case 4: /* Tx Arbiter 1 */
3760 case 7: /* PCI express reg */
3761 case 8: /* RX1 */
3762 case 12 ... 13: /* TX1 */
3763 case 16: case 18:/* Rx Ram Buffer 1 */
3764 case 20 ... 21: /* Tx Ram Buffer 1 */
3765 case 24: /* Rx MAC Fifo 1 */
3766 case 26: /* Tx MAC Fifo 1 */
3767 case 28 ... 29: /* Descriptor and status unit */
3768 case 30: /* GPHY 1*/
3769 case 32 ... 39: /* Pattern Ram 1 */
3770 case 48: case 50: /* TCP Segmentation 1 */
3771 case 56 ... 60: /* PCI space */
3772 case 80 ... 84: /* GMAC 1 */
3773 memcpy_fromio(p, io, 128);
3774 break;
3775 default:
3776reserved:
3777 memset(p, 0, 128);
3778 }
3ead5db7 3779
295b54c4
SH		 3780 p += 128;
3781 io += 128;
3782 }
793b883e 3783}
cd28ab6a 3784
b628ed98
SH		 3785/* In order to do Jumbo packets on these chips, need to turn off the
3786 * transmit store/forward. Therefore checksum offload won't work.
3787 */
3788static int no_tx_offload(struct net_device *dev)
3789{
3790 const struct sky2_port *sky2 = netdev_priv(dev);
3791 const struct sky2_hw *hw = sky2->hw;
3792
69161611 3793 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3794}
3795
3796static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3797{
3798 if (data && no_tx_offload(dev))
3799 return -EINVAL;
3800
3801 return ethtool_op_set_tx_csum(dev, data);
3802}
3803
3804
3805static int sky2_set_tso(struct net_device *dev, u32 data)
3806{
3807 if (data && no_tx_offload(dev))
3808 return -EINVAL;
3809
3810 return ethtool_op_set_tso(dev, data);
3811}
3812
f4331a6d
SH		 3813static int sky2_get_eeprom_len(struct net_device *dev)
3814{
3815 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3816 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3817 u16 reg2;
3818
b32f40c4 3819 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3820 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3821}
3822
1413235c 3823static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3824{
1413235c 3825 unsigned long start = jiffies;
f4331a6d 3826
1413235c
SH		 3827 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3828 /* Can take up to 10.6 ms for write */
3829 if (time_after(jiffies, start + HZ/4)) {
3830 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3831 return -ETIMEDOUT;
3832 }
3833 mdelay(1);
3834 }
167f53d0 3835
1413235c
SH		 3836 return 0;
3837}
167f53d0 3838
1413235c
SH		 3839static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3840 u16 offset, size_t length)
3841{
3842 int rc = 0;
3843
3844 while (length > 0) {
3845 u32 val;
3846
3847 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3848 rc = sky2_vpd_wait(hw, cap, 0);
3849 if (rc)
3850 break;
3851
3852 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3853
3854 memcpy(data, &val, min(sizeof(val), length));
3855 offset += sizeof(u32);
3856 data += sizeof(u32);
3857 length -= sizeof(u32);
3858 }
3859
3860 return rc;
f4331a6d
SH		 3861}
3862
1413235c
SH		 3863static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3864 u16 offset, unsigned int length)
f4331a6d 3865{
1413235c
SH		 3866 unsigned int i;
3867 int rc = 0;
3868
3869 for (i = 0; i < length; i += sizeof(u32)) {
3870 u32 val = *(u32 *)(data + i);
3871
3872 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3873 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3874
3875 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3876 if (rc)
3877 break;
3878 }
3879 return rc;
f4331a6d
SH		 3880}
3881
3882static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3883 u8 *data)
3884{
3885 struct sky2_port *sky2 = netdev_priv(dev);
3886 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3887
3888 if (!cap)
3889 return -EINVAL;
3890
3891 eeprom->magic = SKY2_EEPROM_MAGIC;
3892
1413235c 3893 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3894}
3895
3896static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3897 u8 *data)
3898{
3899 struct sky2_port *sky2 = netdev_priv(dev);
3900 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3901
3902 if (!cap)
3903 return -EINVAL;
3904
3905 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3906 return -EINVAL;
3907
1413235c
SH		 3908 /* Partial writes not supported */
3909 if ((eeprom->offset & 3) || (eeprom->len & 3))
3910 return -EINVAL;
f4331a6d 3911
1413235c 3912 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3913}
3914
3915
7282d491 3916static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3917 .get_settings = sky2_get_settings,
3918 .set_settings = sky2_set_settings,
3919 .get_drvinfo = sky2_get_drvinfo,
3920 .get_wol = sky2_get_wol,
3921 .set_wol = sky2_set_wol,
3922 .get_msglevel = sky2_get_msglevel,
3923 .set_msglevel = sky2_set_msglevel,
3924 .nway_reset = sky2_nway_reset,
3925 .get_regs_len = sky2_get_regs_len,
3926 .get_regs = sky2_get_regs,
3927 .get_link = ethtool_op_get_link,
3928 .get_eeprom_len = sky2_get_eeprom_len,
3929 .get_eeprom = sky2_get_eeprom,
3930 .set_eeprom = sky2_set_eeprom,
f4331a6d 3931 .set_sg = ethtool_op_set_sg,
f4331a6d 3932 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3933 .set_tso = sky2_set_tso,
3934 .get_rx_csum = sky2_get_rx_csum,
3935 .set_rx_csum = sky2_set_rx_csum,
3936 .get_strings = sky2_get_strings,
3937 .get_coalesce = sky2_get_coalesce,
3938 .set_coalesce = sky2_set_coalesce,
3939 .get_ringparam = sky2_get_ringparam,
3940 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3941 .get_pauseparam = sky2_get_pauseparam,
3942 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3943 .phys_id = sky2_phys_id,
b9f2c044 3944 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3945 .get_ethtool_stats = sky2_get_ethtool_stats,
3946};
3947
3cf26753
SH		 3948#ifdef CONFIG_SKY2_DEBUG
3949
3950static struct dentry *sky2_debug;
3951
e4c2abe2
SH		 3952
3953/*
3954 * Read and parse the first part of Vital Product Data
3955 */
3956#define VPD_SIZE 128
3957#define VPD_MAGIC 0x82
3958
3959static const struct vpd_tag {
3960 char tag[2];
3961 char *label;
3962} vpd_tags[] = {
3963 { "PN", "Part Number" },
3964 { "EC", "Engineering Level" },
3965 { "MN", "Manufacturer" },
3966 { "SN", "Serial Number" },
3967 { "YA", "Asset Tag" },
3968 { "VL", "First Error Log Message" },
3969 { "VF", "Second Error Log Message" },
3970 { "VB", "Boot Agent ROM Configuration" },
3971 { "VE", "EFI UNDI Configuration" },
3972};
3973
3974static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3975{
3976 size_t vpd_size;
3977 loff_t offs;
3978 u8 len;
3979 unsigned char *buf;
3980 u16 reg2;
3981
3982 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3983 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3984
3985 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3986 buf = kmalloc(vpd_size, GFP_KERNEL);
3987 if (!buf) {
3988 seq_puts(seq, "no memory!\n");
3989 return;
3990 }
3991
3992 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
3993 seq_puts(seq, "VPD read failed\n");
3994 goto out;
3995 }
3996
3997 if (buf[0] != VPD_MAGIC) {
3998 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
3999 goto out;
4000 }
4001 len = buf[1];
4002 if (len == 0 || len > vpd_size - 4) {
4003 seq_printf(seq, "Invalid id length: %d\n", len);
4004 goto out;
4005 }
4006
4007 seq_printf(seq, "%.*s\n", len, buf + 3);
4008 offs = len + 3;
4009
4010 while (offs < vpd_size - 4) {
4011 int i;
4012
4013 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4014 break;
4015 len = buf[offs + 2];
4016 if (offs + len + 3 >= vpd_size)
4017 break;
4018
4019 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4020 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4021 seq_printf(seq, " %s: %.*s\n",
4022 vpd_tags[i].label, len, buf + offs + 3);
4023 break;
4024 }
4025 }
4026 offs += len + 3;
4027 }
4028out:
4029 kfree(buf);
4030}
4031
3cf26753
SH		 4032static int sky2_debug_show(struct seq_file *seq, void *v)
4033{
4034 struct net_device *dev = seq->private;
4035 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4036 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4037 unsigned port = sky2->port;
4038 unsigned idx, last;
4039 int sop;
4040
e4c2abe2 4041 sky2_show_vpd(seq, hw);
3cf26753 4042
e4c2abe2 4043 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4044 sky2_read32(hw, B0_ISRC),
4045 sky2_read32(hw, B0_IMSK),
4046 sky2_read32(hw, B0_Y2_SP_ICR));
4047
e4c2abe2
SH		 4048 if (!netif_running(dev)) {
4049 seq_printf(seq, "network not running\n");
4050 return 0;
4051 }
4052
bea3348e 4053 napi_disable(&hw->napi);
3cf26753
SH		 4054 last = sky2_read16(hw, STAT_PUT_IDX);
4055
4056 if (hw->st_idx == last)
4057 seq_puts(seq, "Status ring (empty)\n");
4058 else {
4059 seq_puts(seq, "Status ring\n");
4060 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4061 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4062 const struct sky2_status_le *le = hw->st_le + idx;
4063 seq_printf(seq, "[%d] %#x %d %#x\n",
4064 idx, le->opcode, le->length, le->status);
4065 }
4066 seq_puts(seq, "\n");
4067 }
4068
4069 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4070 sky2->tx_cons, sky2->tx_prod,
4071 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4072 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4073
4074 /* Dump contents of tx ring */
4075 sop = 1;
4076 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4077 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4078 const struct sky2_tx_le *le = sky2->tx_le + idx;
4079 u32 a = le32_to_cpu(le->addr);
4080
4081 if (sop)
4082 seq_printf(seq, "%u:", idx);
4083 sop = 0;
4084
4085 switch(le->opcode & ~HW_OWNER) {
4086 case OP_ADDR64:
4087 seq_printf(seq, " %#x:", a);
4088 break;
4089 case OP_LRGLEN:
4090 seq_printf(seq, " mtu=%d", a);
4091 break;
4092 case OP_VLAN:
4093 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4094 break;
4095 case OP_TCPLISW:
4096 seq_printf(seq, " csum=%#x", a);
4097 break;
4098 case OP_LARGESEND:
4099 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4100 break;
4101 case OP_PACKET:
4102 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4103 break;
4104 case OP_BUFFER:
4105 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4106 break;
4107 default:
4108 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4109 a, le16_to_cpu(le->length));
4110 }
4111
4112 if (le->ctrl & EOP) {
4113 seq_putc(seq, '\n');
4114 sop = 1;
4115 }
4116 }
4117
4118 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4119 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4120 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4121 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4122
d1d08d12 4123 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4124 napi_enable(&hw->napi);
3cf26753
SH		 4125 return 0;
4126}
4127
4128static int sky2_debug_open(struct inode *inode, struct file *file)
4129{
4130 return single_open(file, sky2_debug_show, inode->i_private);
4131}
4132
4133static const struct file_operations sky2_debug_fops = {
4134 .owner = THIS_MODULE,
4135 .open = sky2_debug_open,
4136 .read = seq_read,
4137 .llseek = seq_lseek,
4138 .release = single_release,
4139};
4140
4141/*
4142 * Use network device events to create/remove/rename
4143 * debugfs file entries
4144 */
4145static int sky2_device_event(struct notifier_block *unused,
4146 unsigned long event, void *ptr)
4147{
4148 struct net_device *dev = ptr;
5b296bc9 4149 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4150
1436b301 4151 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4152 return NOTIFY_DONE;
3cf26753 4153
5b296bc9
SH		 4154 switch(event) {
4155 case NETDEV_CHANGENAME:
4156 if (sky2->debugfs) {
4157 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4158 sky2_debug, dev->name);
4159 }
4160 break;
3cf26753 4161
5b296bc9
SH		 4162 case NETDEV_GOING_DOWN:
4163 if (sky2->debugfs) {
4164 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4165 dev->name);
4166 debugfs_remove(sky2->debugfs);
4167 sky2->debugfs = NULL;
3cf26753 4168 }
5b296bc9
SH		 4169 break;
4170
4171 case NETDEV_UP:
4172 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4173 sky2_debug, dev,
4174 &sky2_debug_fops);
4175 if (IS_ERR(sky2->debugfs))
4176 sky2->debugfs = NULL;
3cf26753
SH		 4177 }
4178
4179 return NOTIFY_DONE;
4180}
4181
4182static struct notifier_block sky2_notifier = {
4183 .notifier_call = sky2_device_event,
4184};
4185
4186
4187static __init void sky2_debug_init(void)
4188{
4189 struct dentry *ent;
4190
4191 ent = debugfs_create_dir("sky2", NULL);
4192 if (!ent || IS_ERR(ent))
4193 return;
4194
4195 sky2_debug = ent;
4196 register_netdevice_notifier(&sky2_notifier);
4197}
4198
4199static __exit void sky2_debug_cleanup(void)
4200{
4201 if (sky2_debug) {
4202 unregister_netdevice_notifier(&sky2_notifier);
4203 debugfs_remove(sky2_debug);
4204 sky2_debug = NULL;
4205 }
4206}
4207
4208#else
4209#define sky2_debug_init()
4210#define sky2_debug_cleanup()
4211#endif
4212
1436b301
SH		 4213/* Two copies of network device operations to handle special case of
4214 not allowing netpoll on second port */
4215static const struct net_device_ops sky2_netdev_ops[2] = {
4216 {
4217 .ndo_open = sky2_up,
4218 .ndo_stop = sky2_down,
00829823 4219 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4220 .ndo_do_ioctl = sky2_ioctl,
4221 .ndo_validate_addr = eth_validate_addr,
4222 .ndo_set_mac_address = sky2_set_mac_address,
4223 .ndo_set_multicast_list = sky2_set_multicast,
4224 .ndo_change_mtu = sky2_change_mtu,
4225 .ndo_tx_timeout = sky2_tx_timeout,
4226#ifdef SKY2_VLAN_TAG_USED
4227 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4228#endif
4229#ifdef CONFIG_NET_POLL_CONTROLLER
4230 .ndo_poll_controller = sky2_netpoll,
4231#endif
4232 },
4233 {
4234 .ndo_open = sky2_up,
4235 .ndo_stop = sky2_down,
00829823 4236 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4237 .ndo_do_ioctl = sky2_ioctl,
4238 .ndo_validate_addr = eth_validate_addr,
4239 .ndo_set_mac_address = sky2_set_mac_address,
4240 .ndo_set_multicast_list = sky2_set_multicast,
4241 .ndo_change_mtu = sky2_change_mtu,
4242 .ndo_tx_timeout = sky2_tx_timeout,
4243#ifdef SKY2_VLAN_TAG_USED
4244 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4245#endif
4246 },
4247};
3cf26753 4248
cd28ab6a
SH		 4249/* Initialize network device */
4250static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4251 unsigned port,
be63a21c 4252 int highmem, int wol)
cd28ab6a
SH		 4253{
4254 struct sky2_port *sky2;
4255 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4256
4257 if (!dev) {
898eb71c 4258 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4259 return NULL;
4260 }
4261
cd28ab6a 4262 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4263 dev->irq = hw->pdev->irq;
cd28ab6a 4264 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4265 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4266 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4267
4268 sky2 = netdev_priv(dev);
4269 sky2->netdev = dev;
4270 sky2->hw = hw;
4271 sky2->msg_enable = netif_msg_init(debug, default_msg);
4272
cd28ab6a
SH		 4273 /* Auto speed and flow control */
4274 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4275 sky2->flow_mode = FC_BOTH;
4276
cd28ab6a
SH		 4277 sky2->duplex = -1;
4278 sky2->speed = -1;
4279 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4280 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4281 sky2->wol = wol;
75d070c5 4282
e07b1aa8 4283 spin_lock_init(&sky2->phy_lock);
793b883e 4284 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4285 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4286
4287 hw->dev[port] = dev;
4288
4289 sky2->port = port;
4290
4a50a876 4291 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4292 if (highmem)
4293 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4294
d1f13708 4295#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4296 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4297 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4298 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4299 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4300 }
d1f13708 4301#endif
4302
cd28ab6a 4303 /* read the mac address */
793b883e 4304 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4305 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4306
cd28ab6a
SH		 4307 return dev;
4308}
4309
28bd181a 4310static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4311{
4312 const struct sky2_port *sky2 = netdev_priv(dev);
4313
4314 if (netif_msg_probe(sky2))
e174961c
JB		 4315 printk(KERN_INFO PFX "%s: addr %pM\n",
4316 dev->name, dev->dev_addr);
cd28ab6a
SH		 4317}
4318
fb2690a9 4319/* Handle software interrupt used during MSI test */
7d12e780 4320static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4321{
4322 struct sky2_hw *hw = dev_id;
4323 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4324
4325 if (status == 0)
4326 return IRQ_NONE;
4327
4328 if (status & Y2_IS_IRQ_SW) {
ea76e635 4329 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4330 wake_up(&hw->msi_wait);
4331 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4332 }
4333 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4334
4335 return IRQ_HANDLED;
4336}
4337
4338/* Test interrupt path by forcing a a software IRQ */
4339static int __devinit sky2_test_msi(struct sky2_hw *hw)
4340{
4341 struct pci_dev *pdev = hw->pdev;
4342 int err;
4343
bb507fe1 4344 init_waitqueue_head (&hw->msi_wait);
4345
fb2690a9
SH		 4346 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4347
b0a20ded 4348 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4349 if (err) {
b02a9258 4350 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4351 return err;
4352 }
4353
fb2690a9 4354 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4355 sky2_read8(hw, B0_CTST);
fb2690a9 4356
ea76e635 4357 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4358
ea76e635 4359 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4360 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4361 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4362 "switching to INTx mode.\n");
fb2690a9
SH		 4363
4364 err = -EOPNOTSUPP;
4365 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4366 }
4367
4368 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4369 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4370
4371 free_irq(pdev->irq, hw);
4372
4373 return err;
4374}
4375
c7127a34
SH		 4376/* This driver supports yukon2 chipset only */
4377static const char *sky2_name(u8 chipid, char *buf, int sz)
4378{
4379 const char *name[] = {
4380 "XL", /* 0xb3 */
4381 "EC Ultra", /* 0xb4 */
4382 "Extreme", /* 0xb5 */
4383 "EC", /* 0xb6 */
4384 "FE", /* 0xb7 */
4385 "FE+", /* 0xb8 */
4386 "Supreme", /* 0xb9 */
0ce8b98d 4387 "UL 2", /* 0xba */
c7127a34
SH		 4388 };
4389
0ce8b98d 4390 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4391 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4392 else
4393 snprintf(buf, sz, "(chip %#x)", chipid);
4394 return buf;
4395}
4396
cd28ab6a
SH		 4397static int __devinit sky2_probe(struct pci_dev *pdev,
4398 const struct pci_device_id *ent)
4399{
7f60c64b 4400 struct net_device *dev;
cd28ab6a 4401 struct sky2_hw *hw;
be63a21c 4402 int err, using_dac = 0, wol_default;
3834507d 4403 u32 reg;
c7127a34 4404 char buf1[16];
cd28ab6a 4405
793b883e
SH		 4406 err = pci_enable_device(pdev);
4407 if (err) {
b02a9258 4408 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4409 goto err_out;
4410 }
4411
6cc90a5a
SH		 4412 /* Get configuration information
4413 * Note: only regular PCI config access once to test for HW issues
4414 * other PCI access through shared memory for speed and to
4415 * avoid MMCONFIG problems.
4416 */
4417 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4418 if (err) {
4419 dev_err(&pdev->dev, "PCI read config failed\n");
4420 goto err_out;
4421 }
4422
4423 if (~reg == 0) {
4424 dev_err(&pdev->dev, "PCI configuration read error\n");
4425 goto err_out;
4426 }
4427
793b883e
SH		 4428 err = pci_request_regions(pdev, DRV_NAME);
4429 if (err) {
b02a9258 4430 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4431 goto err_out_disable;
cd28ab6a
SH		 4432 }
4433
4434 pci_set_master(pdev);
4435
d1f3d4dd 4436 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4437 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4438 using_dac = 1;
6a35528a 4439 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4440 if (err < 0) {
b02a9258
SH		 4441 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4442 "for consistent allocations\n");
d1f3d4dd
SH		 4443 goto err_out_free_regions;
4444 }
d1f3d4dd 4445 } else {
284901a9 4446 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4447 if (err) {
b02a9258 4448 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4449 goto err_out_free_regions;
4450 }
4451 }
d1f3d4dd 4452
3834507d
SH		 4453
4454#ifdef __BIG_ENDIAN
4455 /* The sk98lin vendor driver uses hardware byte swapping but
4456 * this driver uses software swapping.
4457 */
4458 reg &= ~PCI_REV_DESC;
4459 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4460 if (err) {
4461 dev_err(&pdev->dev, "PCI write config failed\n");
4462 goto err_out_free_regions;
4463 }
4464#endif
4465
9d731d77 4466 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4467
cd28ab6a 4468 err = -ENOMEM;
6aad85d6 4469 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4470 if (!hw) {
b02a9258 4471 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4472 goto err_out_free_regions;
4473 }
4474
cd28ab6a 4475 hw->pdev = pdev;
cd28ab6a
SH		 4476
4477 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4478 if (!hw->regs) {
b02a9258 4479 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4480 goto err_out_free_hw;
4481 }
4482
08c06d8a 4483 /* ring for status responses */
167f53d0 4484 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4485 if (!hw->st_le)
4486 goto err_out_iounmap;
4487
e3173832 4488 err = sky2_init(hw);
cd28ab6a 4489 if (err)
793b883e 4490 goto err_out_iounmap;
cd28ab6a 4491
c844d483
SH		 4492 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4493 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4494
e3173832
SH		 4495 sky2_reset(hw);
4496
be63a21c 4497 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4498 if (!dev) {
4499 err = -ENOMEM;
cd28ab6a 4500 goto err_out_free_pci;
7f60c64b 4501 }
cd28ab6a 4502
9fa1b1f3
SH		 4503 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4504 err = sky2_test_msi(hw);
4505 if (err == -EOPNOTSUPP)
4506 pci_disable_msi(pdev);
4507 else if (err)
4508 goto err_out_free_netdev;
4509 }
4510
793b883e
SH		 4511 err = register_netdev(dev);
4512 if (err) {
b02a9258 4513 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4514 goto err_out_free_netdev;
4515 }
4516
6de16237
SH		 4517 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4518
ea76e635
SH		 4519 err = request_irq(pdev->irq, sky2_intr,
4520 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4521 dev->name, hw);
9fa1b1f3 4522 if (err) {
b02a9258 4523 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4524 goto err_out_unregister;
4525 }
4526 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4527 napi_enable(&hw->napi);
9fa1b1f3 4528
cd28ab6a
SH		 4529 sky2_show_addr(dev);
4530
7f60c64b 4531 if (hw->ports > 1) {
4532 struct net_device *dev1;
4533
be63a21c 4534 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4535 if (!dev1)
4536 dev_warn(&pdev->dev, "allocation for second device failed\n");
4537 else if ((err = register_netdev(dev1))) {
4538 dev_warn(&pdev->dev,
4539 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4540 hw->dev[1] = NULL;
4541 free_netdev(dev1);
b02a9258
SH		 4542 } else
4543 sky2_show_addr(dev1);
cd28ab6a
SH		 4544 }
4545
32c2c300 4546 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4547 INIT_WORK(&hw->restart_work, sky2_restart);
4548
793b883e
SH		 4549 pci_set_drvdata(pdev, hw);
4550
cd28ab6a
SH		 4551 return 0;
4552
793b883e 4553err_out_unregister:
ea76e635 4554 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4555 pci_disable_msi(pdev);
793b883e 4556 unregister_netdev(dev);
cd28ab6a
SH		 4557err_out_free_netdev:
4558 free_netdev(dev);
cd28ab6a 4559err_out_free_pci:
793b883e 4560 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4561 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4562err_out_iounmap:
4563 iounmap(hw->regs);
4564err_out_free_hw:
4565 kfree(hw);
4566err_out_free_regions:
4567 pci_release_regions(pdev);
44a1d2e5 4568err_out_disable:
cd28ab6a 4569 pci_disable_device(pdev);
cd28ab6a 4570err_out:
549a68c3 4571 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4572 return err;
4573}
4574
4575static void __devexit sky2_remove(struct pci_dev *pdev)
4576{
793b883e 4577 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4578 int i;
cd28ab6a 4579
793b883e 4580 if (!hw)
cd28ab6a
SH		 4581 return;
4582
32c2c300 4583 del_timer_sync(&hw->watchdog_timer);
6de16237 4584 cancel_work_sync(&hw->restart_work);
d27ed387 4585
b877fe28 4586 for (i = hw->ports-1; i >= 0; --i)
6de16237 4587 unregister_netdev(hw->dev[i]);
81906791 4588
d27ed387 4589 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4590
ae306cca
SH		 4591 sky2_power_aux(hw);
4592
cd28ab6a 4593 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4594 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4595 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4596
4597 free_irq(pdev->irq, hw);
ea76e635 4598 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4599 pci_disable_msi(pdev);
793b883e 4600 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4601 pci_release_regions(pdev);
4602 pci_disable_device(pdev);
793b883e 4603
b877fe28 4604 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4605 free_netdev(hw->dev[i]);
4606
cd28ab6a
SH		 4607 iounmap(hw->regs);
4608 kfree(hw);
5afa0a9c 4609
cd28ab6a
SH		 4610 pci_set_drvdata(pdev, NULL);
4611}
4612
4613#ifdef CONFIG_PM
4614static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4615{
793b883e 4616 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4617 int i, wol = 0;
cd28ab6a 4618
549a68c3
SH		 4619 if (!hw)
4620 return 0;
4621
063a0b38
SH		 4622 del_timer_sync(&hw->watchdog_timer);
4623 cancel_work_sync(&hw->restart_work);
4624
f05267e7 4625 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4626 struct net_device *dev = hw->dev[i];
e3173832 4627 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4628
063a0b38 4629 netif_device_detach(dev);
e3173832 4630 if (netif_running(dev))
5afa0a9c 4631 sky2_down(dev);
e3173832
SH		 4632
4633 if (sky2->wol)
4634 sky2_wol_init(sky2);
4635
4636 wol |= sky2->wol;
cd28ab6a
SH		 4637 }
4638
8ab8fca2 4639 sky2_write32(hw, B0_IMSK, 0);
6de16237 4640 napi_disable(&hw->napi);
ae306cca 4641 sky2_power_aux(hw);
e3173832 4642
d374c1c1 4643 pci_save_state(pdev);
e3173832 4644 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4645 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4646
2ccc99b7 4647 return 0;
cd28ab6a
SH		 4648}
4649
4650static int sky2_resume(struct pci_dev *pdev)
4651{
793b883e 4652 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4653 int i, err;
cd28ab6a 4654
549a68c3
SH		 4655 if (!hw)
4656 return 0;
4657
f71eb1a2
SH		 4658 err = pci_set_power_state(pdev, PCI_D0);
4659 if (err)
4660 goto out;
ae306cca
SH		 4661
4662 err = pci_restore_state(pdev);
4663 if (err)
4664 goto out;
4665
cd28ab6a 4666 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4667
4668 /* Re-enable all clocks */
05745c4a
SH		 4669 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4670 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4671 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4672 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4673
e3173832 4674 sky2_reset(hw);
8ab8fca2 4675 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4676 napi_enable(&hw->napi);
8ab8fca2 4677
f05267e7 4678 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4679 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4680
4681 netif_device_attach(dev);
6a5706b9 4682 if (netif_running(dev)) {
08c06d8a
SH		 4683 err = sky2_up(dev);
4684 if (err) {
4685 printk(KERN_ERR PFX "%s: could not up: %d\n",
4686 dev->name, err);
68c28898 4687 rtnl_lock();
08c06d8a 4688 dev_close(dev);
68c28898 4689 rtnl_unlock();
eb35cf60 4690 goto out;
5afa0a9c 4691 }
cd28ab6a
SH		 4692 }
4693 }
eb35cf60 4694
ae306cca 4695 return 0;
08c06d8a 4696out:
b02a9258 4697 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4698 pci_disable_device(pdev);
08c06d8a 4699 return err;
cd28ab6a
SH		 4700}
4701#endif
4702
e3173832
SH		 4703static void sky2_shutdown(struct pci_dev *pdev)
4704{
4705 struct sky2_hw *hw = pci_get_drvdata(pdev);
4706 int i, wol = 0;
4707
549a68c3
SH		 4708 if (!hw)
4709 return;
4710
5c0d6b34 4711 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4712
4713 for (i = 0; i < hw->ports; i++) {
4714 struct net_device *dev = hw->dev[i];
4715 struct sky2_port *sky2 = netdev_priv(dev);
4716
4717 if (sky2->wol) {
4718 wol = 1;
4719 sky2_wol_init(sky2);
4720 }
4721 }
4722
4723 if (wol)
4724 sky2_power_aux(hw);
4725
4726 pci_enable_wake(pdev, PCI_D3hot, wol);
4727 pci_enable_wake(pdev, PCI_D3cold, wol);
4728
4729 pci_disable_device(pdev);
f71eb1a2 4730 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4731}
4732
cd28ab6a 4733static struct pci_driver sky2_driver = {
793b883e
SH		 4734 .name = DRV_NAME,
4735 .id_table = sky2_id_table,
4736 .probe = sky2_probe,
4737 .remove = __devexit_p(sky2_remove),
cd28ab6a 4738#ifdef CONFIG_PM
793b883e
SH		 4739 .suspend = sky2_suspend,
4740 .resume = sky2_resume,
cd28ab6a 4741#endif
e3173832 4742 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4743};
4744
4745static int __init sky2_init_module(void)
4746{
c844d483
SH		 4747 pr_info(PFX "driver version " DRV_VERSION "\n");
4748
3cf26753 4749 sky2_debug_init();
50241c4c 4750 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4751}
4752
4753static void __exit sky2_cleanup_module(void)
4754{
4755 pci_unregister_driver(&sky2_driver);
3cf26753 4756 sky2_debug_cleanup();
cd28ab6a
SH		 4757}
4758
4759module_init(sky2_init_module);
4760module_exit(sky2_cleanup_module);
4761
4762MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4763MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4764MODULE_LICENSE("GPL");
5f4f9dc1 4765MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)