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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
a73b629b 53#define DRV_VERSION "1.15"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 66#define RX_SKB_ALIGN 8
22e11703 67#define RX_BUF_WRITE 16
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
cb5d9547
SH		 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
cd28ab6a 82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
14d0263f 91static int copybreak __read_mostly = 128;
bdb5c58e
SH		 92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
e561a83b 99static int idle_timeout = 0;
01bd7564 100module_param(idle_timeout, int, 0);
e561a83b 101MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 134 { 0 }
135};
793b883e 136
cd28ab6a
SH		 137MODULE_DEVICE_TABLE(pci, sky2_id_table);
138
139/* Avoid conditionals by using array */
140static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
141static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 142static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 143
92f965e8
SH		 144/* This driver supports yukon2 chipset only */
145static const char *yukon2_name[] = {
146 "XL", /* 0xb3 */
147 "EC Ultra", /* 0xb4 */
93745494 148 "Extreme", /* 0xb5 */
92f965e8
SH		 149 "EC", /* 0xb6 */
150 "FE", /* 0xb7 */
793b883e
SH		 151};
152
793b883e 153/* Access to external PHY */
ef743d33 154static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 155{
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 163 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 164 return 0;
793b883e 165 udelay(1);
cd28ab6a 166 }
ef743d33 167
793b883e 168 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 169 return -ETIMEDOUT;
cd28ab6a
SH		 170}
171
ef743d33 172static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 173{
174 int i;
175
793b883e 176 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 177 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
178
179 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 180 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
181 *val = gma_read16(hw, port, GM_SMI_DATA);
182 return 0;
183 }
184
793b883e 185 udelay(1);
cd28ab6a
SH		 186 }
187
ef743d33 188 return -ETIMEDOUT;
189}
190
191static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
192{
193 u16 v;
194
195 if (__gm_phy_read(hw, port, reg, &v) != 0)
196 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
197 return v;
cd28ab6a
SH		 198}
199
5afa0a9c 200
ae306cca
SH		 201static void sky2_power_on(struct sky2_hw *hw)
202{
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw, B0_POWER_CTRL,
205 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 206
ae306cca
SH		 207 /* disable Core Clock Division, */
208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 209
ae306cca
SH		 210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
211 /* enable bits are inverted */
212 sky2_write8(hw, B2_Y2_CLK_GATE,
213 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
214 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
215 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
216 else
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 218
93745494 219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
fc99fe06 220 u32 reg;
5afa0a9c 221
fc99fe06
SH		 222 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
223 /* set all bits to 0 except bits 15..12 and 8 */
224 reg &= P_ASPM_CONTROL_MSK;
225 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
226
227 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
228 /* set all bits to 0 except bits 28 & 27 */
229 reg &= P_CTL_TIM_VMAIN_AV_MSK;
230 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
231
232 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 233
234 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
235 reg = sky2_read32(hw, B2_GP_IO);
236 reg |= GLB_GPIO_STAT_RACE_DIS;
237 sky2_write32(hw, B2_GP_IO, reg);
5afa0a9c 238 }
ae306cca 239}
5afa0a9c 240
ae306cca
SH		 241static void sky2_power_aux(struct sky2_hw *hw)
242{
243 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
244 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
245 else
246 /* enable bits are inverted */
247 sky2_write8(hw, B2_Y2_CLK_GATE,
248 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
249 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
250 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
251
252 /* switch power to VAUX */
253 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
254 sky2_write8(hw, B0_POWER_CTRL,
255 (PC_VAUX_ENA | PC_VCC_ENA |
256 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 257}
258
d3bcfbeb 259static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 260{
261 u16 reg;
262
263 /* disable all GMAC IRQ's */
264 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
265 /* disable PHY IRQs */
266 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 267
cd28ab6a
SH		 268 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
269 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
270 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
271 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
272
273 reg = gma_read16(hw, port, GM_RX_CTRL);
274 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
275 gma_write16(hw, port, GM_RX_CTRL, reg);
276}
277
16ad91e1
SH		 278/* flow control to advertise bits */
279static const u16 copper_fc_adv[] = {
280 [FC_NONE] = 0,
281 [FC_TX] = PHY_M_AN_ASP,
282 [FC_RX] = PHY_M_AN_PC,
283 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
284};
285
286/* flow control to advertise bits when using 1000BaseX */
287static const u16 fiber_fc_adv[] = {
288 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
289 [FC_TX] = PHY_M_P_ASYM_MD_X,
290 [FC_RX] = PHY_M_P_SYM_MD_X,
291 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
292};
293
294/* flow control to GMA disable bits */
295static const u16 gm_fc_disable[] = {
296 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
297 [FC_TX] = GM_GPCR_FC_RX_DIS,
298 [FC_RX] = GM_GPCR_FC_TX_DIS,
299 [FC_BOTH] = 0,
300};
301
302
cd28ab6a
SH		 303static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
304{
305 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 306 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 307
93745494
SH		 308 if (sky2->autoneg == AUTONEG_ENABLE
309 && !(hw->chip_id == CHIP_ID_YUKON_XL
310 || hw->chip_id == CHIP_ID_YUKON_EC_U
311 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 312 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
313
314 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 315 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 316 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
317
53419c68 318 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 319 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 320 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 321 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
322 else
53419c68
SH		 323 /* set master & slave downshift counter to 1x */
324 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 325
326 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
327 }
328
329 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 330 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 331 if (hw->chip_id == CHIP_ID_YUKON_FE) {
332 /* enable automatic crossover */
333 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
334 } else {
335 /* disable energy detect */
336 ctrl &= ~PHY_M_PC_EN_DET_MSK;
337
338 /* enable automatic crossover */
339 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
340
53419c68 341 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 342 if (sky2->autoneg == AUTONEG_ENABLE
343 && (hw->chip_id == CHIP_ID_YUKON_XL
344 || hw->chip_id == CHIP_ID_YUKON_EC_U
345 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 346 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 347 ctrl &= ~PHY_M_PC_DSC_MSK;
348 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
349 }
350 }
cd28ab6a
SH		 351 } else {
352 /* workaround for deviation #4.88 (CRC errors) */
353 /* disable Automatic Crossover */
354
355 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 356 }
cd28ab6a 357
b89165f2
SH		 358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 /* special setup for PHY 88E1112 Fiber */
361 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
362 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 363
b89165f2
SH		 364 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
366 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
367 ctrl &= ~PHY_M_MAC_MD_MSK;
368 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
369 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
370
371 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 372 /* select page 1 to access Fiber registers */
373 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 374
375 /* for SFP-module set SIGDET polarity to low */
376 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
377 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 378 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 379 }
b89165f2
SH		 380
381 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 382 }
383
7800fddc 384 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 385 ct1000 = 0;
386 adv = PHY_AN_CSMA;
2eaba1a2 387 reg = 0;
cd28ab6a
SH		 388
389 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 390 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 391 if (sky2->advertising & ADVERTISED_1000baseT_Full)
392 ct1000 |= PHY_M_1000C_AFD;
393 if (sky2->advertising & ADVERTISED_1000baseT_Half)
394 ct1000 |= PHY_M_1000C_AHD;
395 if (sky2->advertising & ADVERTISED_100baseT_Full)
396 adv |= PHY_M_AN_100_FD;
397 if (sky2->advertising & ADVERTISED_100baseT_Half)
398 adv |= PHY_M_AN_100_HD;
399 if (sky2->advertising & ADVERTISED_10baseT_Full)
400 adv |= PHY_M_AN_10_FD;
401 if (sky2->advertising & ADVERTISED_10baseT_Half)
402 adv |= PHY_M_AN_10_HD;
709c6e7b 403
16ad91e1 404 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 405 } else { /* special defines for FIBER (88E1040S only) */
406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
407 adv |= PHY_M_AN_1000X_AFD;
408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
409 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 410
16ad91e1 411 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 412 }
cd28ab6a
SH		 413
414 /* Restart Auto-negotiation */
415 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
416 } else {
417 /* forced speed/duplex settings */
418 ct1000 = PHY_M_1000C_MSE;
419
2eaba1a2
SH		 420 /* Disable auto update for duplex flow control and speed */
421 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 422
423 switch (sky2->speed) {
424 case SPEED_1000:
425 ctrl |= PHY_CT_SP1000;
2eaba1a2 426 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 427 break;
428 case SPEED_100:
429 ctrl |= PHY_CT_SP100;
2eaba1a2 430 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 431 break;
432 }
433
2eaba1a2
SH		 434 if (sky2->duplex == DUPLEX_FULL) {
435 reg |= GM_GPCR_DUP_FULL;
436 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 437 } else if (sky2->speed < SPEED_1000)
438 sky2->flow_mode = FC_NONE;
2eaba1a2 439
2eaba1a2 440
16ad91e1 441 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 442
443 /* Forward pause packets to GMAC? */
16ad91e1 444 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 445 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
446 else
447 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 448 }
449
2eaba1a2
SH		 450 gma_write16(hw, port, GM_GP_CTRL, reg);
451
cd28ab6a
SH		 452 if (hw->chip_id != CHIP_ID_YUKON_FE)
453 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
454
455 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
456 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
457
458 /* Setup Phy LED's */
459 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
460 ledover = 0;
461
462 switch (hw->chip_id) {
463 case CHIP_ID_YUKON_FE:
464 /* on 88E3082 these bits are at 11..9 (shifted left) */
465 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
466
467 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
468
469 /* delete ACT LED control bits */
470 ctrl &= ~PHY_M_FELP_LED1_MSK;
471 /* change ACT LED control to blink mode */
472 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
473 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
474 break;
475
476 case CHIP_ID_YUKON_XL:
793b883e 477 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 478
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
481
482 /* set LED Function Control register */
ed6d32c7
SH		 483 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 488
489 /* set Polarity Control register */
490 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 491 (PHY_M_POLC_LS1_P_MIX(4) |
492 PHY_M_POLC_IS0_P_MIX(4) |
493 PHY_M_POLC_LOS_CTRL(2) |
494 PHY_M_POLC_INIT_CTRL(2) |
495 PHY_M_POLC_STA1_CTRL(2) |
496 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 497
498 /* restore page register */
793b883e 499 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 500 break;
93745494 501
ed6d32c7 502 case CHIP_ID_YUKON_EC_U:
93745494 503 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 504 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
505
506 /* select page 3 to access LED control register */
507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
508
509 /* set LED Function Control register */
510 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
511 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
512 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
513 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
514 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
515
516 /* set Blink Rate in LED Timer Control Register */
517 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
518 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
519 /* restore page register */
520 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
521 break;
cd28ab6a
SH		 522
523 default:
524 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
525 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
526 /* turn off the Rx LED (LED_RX) */
0efdf262 527 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 528 }
529
9467a8fc
SH		 530 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
531 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 532 /* apply fixes in PHY AFE */
ed6d32c7
SH		 533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
534
977bdf06 535 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 536 gm_phy_write(hw, port, 0x18, 0xaa99);
537 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 538
977bdf06 539 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 540 gm_phy_write(hw, port, 0x18, 0xa204);
541 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 542
543 /* set page register to 0 */
9467a8fc 544 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 545 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 546 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 547
977bdf06
SH		 548 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
549 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 550 ledover |= PHY_M_LED_MO_100;
977bdf06 551 }
cd28ab6a 552
977bdf06
SH		 553 if (ledover)
554 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
555
556 }
2eaba1a2 557
d571b694 558 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 559 if (sky2->autoneg == AUTONEG_ENABLE)
560 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
561 else
562 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
563}
564
d3bcfbeb 565static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
566{
567 u32 reg1;
568 static const u32 phy_power[]
569 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
570
571 /* looks like this XL is back asswards .. */
572 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
573 onoff = !onoff;
574
aed2cec4 575 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 576 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 577 if (onoff)
578 /* Turn off phy power saving */
579 reg1 &= ~phy_power[port];
580 else
581 reg1 |= phy_power[port];
582
583 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 584 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 585 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 586 udelay(100);
587}
588
1b537565
SH		 589/* Force a renegotiation */
590static void sky2_phy_reinit(struct sky2_port *sky2)
591{
e07b1aa8 592 spin_lock_bh(&sky2->phy_lock);
1b537565 593 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 594 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 595}
596
e3173832
SH		 597/* Put device in state to listen for Wake On Lan */
598static void sky2_wol_init(struct sky2_port *sky2)
599{
600 struct sky2_hw *hw = sky2->hw;
601 unsigned port = sky2->port;
602 enum flow_control save_mode;
603 u16 ctrl;
604 u32 reg1;
605
606 /* Bring hardware out of reset */
607 sky2_write16(hw, B0_CTST, CS_RST_CLR);
608 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
609
610 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
611 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
612
613 /* Force to 10/100
614 * sky2_reset will re-enable on resume
615 */
616 save_mode = sky2->flow_mode;
617 ctrl = sky2->advertising;
618
619 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
620 sky2->flow_mode = FC_NONE;
621 sky2_phy_power(hw, port, 1);
622 sky2_phy_reinit(sky2);
623
624 sky2->flow_mode = save_mode;
625 sky2->advertising = ctrl;
626
627 /* Set GMAC to no flow control and auto update for speed/duplex */
628 gma_write16(hw, port, GM_GP_CTRL,
629 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
630 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
631
632 /* Set WOL address */
633 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
634 sky2->netdev->dev_addr, ETH_ALEN);
635
636 /* Turn on appropriate WOL control bits */
637 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
638 ctrl = 0;
639 if (sky2->wol & WAKE_PHY)
640 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
641 else
642 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
643
644 if (sky2->wol & WAKE_MAGIC)
645 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
646 else
647 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
648
649 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
650 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
651
652 /* Turn on legacy PCI-Express PME mode */
653 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
654 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
655 reg1 |= PCI_Y2_PME_LEGACY;
656 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
657 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
658
659 /* block receiver */
660 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
661
662}
663
69161611
SH		 664static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
665{
666 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
667 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
668 TX_STFW_ENA |
669 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
670 } else {
671 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
672 /* set Tx GMAC FIFO Almost Empty Threshold */
673 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
674 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
675
676 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
677 TX_JUMBO_ENA | TX_STFW_DIS);
678
679 /* Can't do offload because of lack of store/forward */
680 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
681 | NETIF_F_ALL_CSUM);
682 } else
683 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
684 TX_JUMBO_DIS | TX_STFW_ENA);
685 }
686}
687
cd28ab6a
SH		 688static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
689{
690 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
691 u16 reg;
692 int i;
693 const u8 *addr = hw->dev[port]->dev_addr;
694
42eeea01 695 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
b4ed372b 696 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 697
698 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
699
793b883e 700 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 701 /* WA DEV_472 -- looks like crossed wires on port 2 */
702 /* clear GMAC 1 Control reset */
703 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
704 do {
705 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
706 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
707 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
708 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
709 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
710 }
711
793b883e 712 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 713
2eaba1a2
SH		 714 /* Enable Transmit FIFO Underrun */
715 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
716
e07b1aa8 717 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 718 sky2_phy_init(hw, port);
e07b1aa8 719 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 720
721 /* MIB clear */
722 reg = gma_read16(hw, port, GM_PHY_ADDR);
723 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
724
43f2f104
SH		 725 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
726 gma_read16(hw, port, i);
cd28ab6a
SH		 727 gma_write16(hw, port, GM_PHY_ADDR, reg);
728
729 /* transmit control */
730 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
731
732 /* receive control reg: unicast + multicast + no FCS */
733 gma_write16(hw, port, GM_RX_CTRL,
793b883e 734 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 735
736 /* transmit flow control */
737 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
738
739 /* transmit parameter */
740 gma_write16(hw, port, GM_TX_PARAM,
741 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
742 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
743 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
744 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
745
746 /* serial mode register */
747 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 748 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 749
6b1a3aef 750 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 751 reg |= GM_SMOD_JUMBO_ENA;
752
753 gma_write16(hw, port, GM_SERIAL_MODE, reg);
754
cd28ab6a
SH		 755 /* virtual address for data */
756 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
757
793b883e
SH		 758 /* physical address: used for pause frames */
759 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
760
761 /* ignore counter overflows */
cd28ab6a
SH		 762 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
763 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
764 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
765
766 /* Configure Rx MAC FIFO */
767 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
69161611
SH		 768 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
769 if (hw->chip_id == CHIP_ID_YUKON_EX)
770 reg |= GMF_RX_OVER_ON;
771
772 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
cd28ab6a 773
d571b694 774 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 775 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 776
8df9a876
SH		 777 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
778 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 779
780 /* Configure Tx MAC FIFO */
781 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
782 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 783
93745494 784 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 785 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 786 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 787
69161611 788 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 789 }
790
cd28ab6a
SH		 791}
792
67712901
SH		 793/* Assign Ram Buffer allocation to queue */
794static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 795{
67712901
SH		 796 u32 end;
797
798 /* convert from K bytes to qwords used for hw register */
799 start *= 1024/8;
800 space *= 1024/8;
801 end = start + space - 1;
793b883e 802
cd28ab6a
SH		 803 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
804 sky2_write32(hw, RB_ADDR(q, RB_START), start);
805 sky2_write32(hw, RB_ADDR(q, RB_END), end);
806 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
807 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
808
809 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 810 u32 tp = space - space/4;
793b883e 811
1c28f6ba
SH		 812 /* On receive queue's set the thresholds
813 * give receiver priority when > 3/4 full
814 * send pause when down to 2K
815 */
816 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
817 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 818
1c28f6ba
SH		 819 tp = space - 2048/8;
820 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
821 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 822 } else {
823 /* Enable store & forward on Tx queue's because
824 * Tx FIFO is only 1K on Yukon
825 */
826 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
827 }
828
829 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 830 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 831}
832
cd28ab6a 833/* Setup Bus Memory Interface */
af4ed7e6 834static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 835{
836 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
837 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
838 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 839 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 840}
841
cd28ab6a
SH		 842/* Setup prefetch unit registers. This is the interface between
843 * hardware and driver list elements
844 */
8cc048e3 845static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 846 u64 addr, u32 last)
847{
cd28ab6a
SH		 848 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
849 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
850 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
851 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
852 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
853 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 854
855 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 856}
857
793b883e
SH		 858static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
859{
860 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
861
cb5d9547 862 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 863 le->ctrl = 0;
793b883e
SH		 864 return le;
865}
cd28ab6a 866
291ea614
SH		 867static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
868 struct sky2_tx_le *le)
869{
870 return sky2->tx_ring + (le - sky2->tx_le);
871}
872
290d4de5
SH		 873/* Update chip's next pointer */
874static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 875{
50432cb5 876 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 877 wmb();
50432cb5
SH		 878 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
879
880 /* Synchronize I/O on since next processor may write to tail */
881 mmiowb();
cd28ab6a
SH		 882}
883
793b883e 884
cd28ab6a
SH		 885static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
886{
887 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 888 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 889 le->ctrl = 0;
cd28ab6a
SH		 890 return le;
891}
892
a018e330 893/* Return high part of DMA address (could be 32 or 64 bit) */
894static inline u32 high32(dma_addr_t a)
895{
a036119f 896 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 897}
898
14d0263f
SH		 899/* Build description to hardware for one receive segment */
900static void sky2_rx_add(struct sky2_port *sky2, u8 op,
901 dma_addr_t map, unsigned len)
cd28ab6a
SH		 902{
903 struct sky2_rx_le *le;
734d1868 904 u32 hi = high32(map);
cd28ab6a 905
793b883e 906 if (sky2->rx_addr64 != hi) {
cd28ab6a 907 le = sky2_next_rx(sky2);
793b883e 908 le->addr = cpu_to_le32(hi);
cd28ab6a 909 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 910 sky2->rx_addr64 = high32(map + len);
cd28ab6a 911 }
793b883e 912
cd28ab6a 913 le = sky2_next_rx(sky2);
734d1868
SH		 914 le->addr = cpu_to_le32((u32) map);
915 le->length = cpu_to_le16(len);
14d0263f 916 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 917}
918
14d0263f
SH		 919/* Build description to hardware for one possibly fragmented skb */
920static void sky2_rx_submit(struct sky2_port *sky2,
921 const struct rx_ring_info *re)
922{
923 int i;
924
925 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
926
927 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
928 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
929}
930
931
932static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
933 unsigned size)
934{
935 struct sk_buff *skb = re->skb;
936 int i;
937
938 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
939 pci_unmap_len_set(re, data_size, size);
940
941 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
942 re->frag_addr[i] = pci_map_page(pdev,
943 skb_shinfo(skb)->frags[i].page,
944 skb_shinfo(skb)->frags[i].page_offset,
945 skb_shinfo(skb)->frags[i].size,
946 PCI_DMA_FROMDEVICE);
947}
948
949static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
950{
951 struct sk_buff *skb = re->skb;
952 int i;
953
954 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
955 PCI_DMA_FROMDEVICE);
956
957 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
958 pci_unmap_page(pdev, re->frag_addr[i],
959 skb_shinfo(skb)->frags[i].size,
960 PCI_DMA_FROMDEVICE);
961}
793b883e 962
cd28ab6a
SH		 963/* Tell chip where to start receive checksum.
964 * Actually has two checksums, but set both same to avoid possible byte
965 * order problems.
966 */
793b883e 967static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 968{
969 struct sky2_rx_le *le;
970
69161611
SH		 971 if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
972 le = sky2_next_rx(sky2);
973 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
974 le->ctrl = 0;
975 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 976
69161611
SH		 977 sky2_write32(sky2->hw,
978 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
979 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
980 }
cd28ab6a
SH		 981
982}
983
6b1a3aef 984/*
985 * The RX Stop command will not work for Yukon-2 if the BMU does not
986 * reach the end of packet and since we can't make sure that we have
987 * incoming data, we must reset the BMU while it is not doing a DMA
988 * transfer. Since it is possible that the RX path is still active,
989 * the RX RAM buffer will be stopped first, so any possible incoming
990 * data will not trigger a DMA. After the RAM buffer is stopped, the
991 * BMU is polled until any DMA in progress is ended and only then it
992 * will be reset.
993 */
994static void sky2_rx_stop(struct sky2_port *sky2)
995{
996 struct sky2_hw *hw = sky2->hw;
997 unsigned rxq = rxqaddr[sky2->port];
998 int i;
999
1000 /* disable the RAM Buffer receive queue */
1001 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1002
1003 for (i = 0; i < 0xffff; i++)
1004 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1005 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1006 goto stopped;
1007
1008 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1009 sky2->netdev->name);
1010stopped:
1011 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1012
1013 /* reset the Rx prefetch unit */
1014 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1015 mmiowb();
6b1a3aef 1016}
793b883e 1017
d571b694 1018/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1019static void sky2_rx_clean(struct sky2_port *sky2)
1020{
1021 unsigned i;
1022
1023 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1024 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1025 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1026
1027 if (re->skb) {
14d0263f 1028 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1029 kfree_skb(re->skb);
1030 re->skb = NULL;
1031 }
1032 }
1033}
1034
ef743d33 1035/* Basic MII support */
1036static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1037{
1038 struct mii_ioctl_data *data = if_mii(ifr);
1039 struct sky2_port *sky2 = netdev_priv(dev);
1040 struct sky2_hw *hw = sky2->hw;
1041 int err = -EOPNOTSUPP;
1042
1043 if (!netif_running(dev))
1044 return -ENODEV; /* Phy still in reset */
1045
d89e1343 1046 switch (cmd) {
ef743d33 1047 case SIOCGMIIPHY:
1048 data->phy_id = PHY_ADDR_MARV;
1049
1050 /* fallthru */
1051 case SIOCGMIIREG: {
1052 u16 val = 0;
91c86df5 1053
e07b1aa8 1054 spin_lock_bh(&sky2->phy_lock);
ef743d33 1055 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1056 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1057
ef743d33 1058 data->val_out = val;
1059 break;
1060 }
1061
1062 case SIOCSMIIREG:
1063 if (!capable(CAP_NET_ADMIN))
1064 return -EPERM;
1065
e07b1aa8 1066 spin_lock_bh(&sky2->phy_lock);
ef743d33 1067 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1068 data->val_in);
e07b1aa8 1069 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1070 break;
1071 }
1072 return err;
1073}
1074
d1f13708 1075#ifdef SKY2_VLAN_TAG_USED
1076static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1077{
1078 struct sky2_port *sky2 = netdev_priv(dev);
1079 struct sky2_hw *hw = sky2->hw;
1080 u16 port = sky2->port;
d1f13708 1081
2bb8c262 1082 netif_tx_lock_bh(dev);
3d4e66f5 1083 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1084
d1f13708 1085 sky2->vlgrp = grp;
3d4e66f5
SH		 1086 if (grp) {
1087 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1088 RX_VLAN_STRIP_ON);
1089 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1090 TX_VLAN_TAG_ON);
1091 } else {
1092 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1093 RX_VLAN_STRIP_OFF);
1094 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1095 TX_VLAN_TAG_OFF);
1096 }
d1f13708 1097
3d4e66f5 1098 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1099 netif_tx_unlock_bh(dev);
d1f13708 1100}
1101#endif
1102
82788c7a 1103/*
14d0263f
SH		 1104 * Allocate an skb for receiving. If the MTU is large enough
1105 * make the skb non-linear with a fragment list of pages.
1106 *
82788c7a
SH		 1107 * It appears the hardware has a bug in the FIFO logic that
1108 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1109 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1110 * aligned except if slab debugging is enabled.
82788c7a 1111 */
14d0263f 1112static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1113{
1114 struct sk_buff *skb;
14d0263f
SH		 1115 unsigned long p;
1116 int i;
82788c7a 1117
14d0263f
SH		 1118 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1119 if (!skb)
1120 goto nomem;
1121
1122 p = (unsigned long) skb->data;
1123 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1124
1125 for (i = 0; i < sky2->rx_nfrags; i++) {
1126 struct page *page = alloc_page(GFP_ATOMIC);
1127
1128 if (!page)
1129 goto free_partial;
1130 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1131 }
1132
1133 return skb;
14d0263f
SH		 1134free_partial:
1135 kfree_skb(skb);
1136nomem:
1137 return NULL;
82788c7a
SH		 1138}
1139
cd28ab6a
SH		 1140/*
1141 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1142 * Normal case this ends up creating one list element for skb
1143 * in the receive ring. Worst case if using large MTU and each
1144 * allocation falls on a different 64 bit region, that results
1145 * in 6 list elements per ring entry.
1146 * One element is used for checksum enable/disable, and one
1147 * extra to avoid wrap.
cd28ab6a 1148 */
6b1a3aef 1149static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1150{
6b1a3aef 1151 struct sky2_hw *hw = sky2->hw;
14d0263f 1152 struct rx_ring_info *re;
6b1a3aef 1153 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1154 unsigned i, size, space, thresh;
cd28ab6a 1155
6b1a3aef 1156 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1157 sky2_qset(hw, rxq);
977bdf06 1158
c3905bc4
SH		 1159 /* On PCI express lowering the watermark gives better performance */
1160 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1161 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1162
1163 /* These chips have no ram buffer?
1164 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1165 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1166 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1167 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1168 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1169
6b1a3aef 1170 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1171
1172 rx_set_checksum(sky2);
14d0263f
SH		 1173
1174 /* Space needed for frame data + headers rounded up */
1175 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1176 + 8;
1177
1178 /* Stopping point for hardware truncation */
1179 thresh = (size - 8) / sizeof(u32);
1180
1181 /* Account for overhead of skb - to avoid order > 0 allocation */
1182 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1183 + sizeof(struct skb_shared_info);
1184
1185 sky2->rx_nfrags = space >> PAGE_SHIFT;
1186 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1187
1188 if (sky2->rx_nfrags != 0) {
1189 /* Compute residue after pages */
1190 space = sky2->rx_nfrags << PAGE_SHIFT;
1191
1192 if (space < size)
1193 size -= space;
1194 else
1195 size = 0;
1196
1197 /* Optimize to handle small packets and headers */
1198 if (size < copybreak)
1199 size = copybreak;
1200 if (size < ETH_HLEN)
1201 size = ETH_HLEN;
1202 }
1203 sky2->rx_data_size = size;
1204
1205 /* Fill Rx ring */
793b883e 1206 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1207 re = sky2->rx_ring + i;
cd28ab6a 1208
14d0263f 1209 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1210 if (!re->skb)
1211 goto nomem;
1212
14d0263f
SH		 1213 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1214 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1215 }
1216
a1433ac4
SH		 1217 /*
1218 * The receiver hangs if it receives frames larger than the
1219 * packet buffer. As a workaround, truncate oversize frames, but
1220 * the register is limited to 9 bits, so if you do frames > 2052
1221 * you better get the MTU right!
1222 */
a1433ac4
SH		 1223 if (thresh > 0x1ff)
1224 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1225 else {
1226 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1227 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1228 }
1229
6b1a3aef 1230 /* Tell chip about available buffers */
50432cb5 1231 sky2_put_idx(hw, rxq, sky2->rx_put);
cd28ab6a
SH		 1232 return 0;
1233nomem:
1234 sky2_rx_clean(sky2);
1235 return -ENOMEM;
1236}
1237
1238/* Bring up network interface. */
1239static int sky2_up(struct net_device *dev)
1240{
1241 struct sky2_port *sky2 = netdev_priv(dev);
1242 struct sky2_hw *hw = sky2->hw;
1243 unsigned port = sky2->port;
67712901 1244 u32 ramsize, imask;
ee7abb04 1245 int cap, err = -ENOMEM;
843a46f4 1246 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1247
ee7abb04
SH		 1248 /*
1249 * On dual port PCI-X card, there is an problem where status
1250 * can be received out of order due to split transactions
843a46f4 1251 */
ee7abb04
SH		 1252 if (otherdev && netif_running(otherdev) &&
1253 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1254 struct sky2_port *osky2 = netdev_priv(otherdev);
1255 u16 cmd;
1256
1257 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1258 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1259 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1260
1261 sky2->rx_csum = 0;
1262 osky2->rx_csum = 0;
1263 }
843a46f4 1264
cd28ab6a
SH		 1265 if (netif_msg_ifup(sky2))
1266 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1267
1268 /* must be power of 2 */
1269 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1270 TX_RING_SIZE *
1271 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1272 &sky2->tx_le_map);
1273 if (!sky2->tx_le)
1274 goto err_out;
1275
6cdbbdf3 1276 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1277 GFP_KERNEL);
1278 if (!sky2->tx_ring)
1279 goto err_out;
1280 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1281
1282 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1283 &sky2->rx_le_map);
1284 if (!sky2->rx_le)
1285 goto err_out;
1286 memset(sky2->rx_le, 0, RX_LE_BYTES);
1287
291ea614 1288 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1289 GFP_KERNEL);
1290 if (!sky2->rx_ring)
1291 goto err_out;
1292
d3bcfbeb 1293 sky2_phy_power(hw, port, 1);
1294
cd28ab6a
SH		 1295 sky2_mac_init(hw, port);
1296
67712901
SH		 1297 /* Register is number of 4K blocks on internal RAM buffer. */
1298 ramsize = sky2_read8(hw, B2_E_0) * 4;
1299 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1300
67712901
SH		 1301 if (ramsize > 0) {
1302 u32 rxspace;
cd28ab6a 1303
67712901
SH		 1304 if (ramsize < 16)
1305 rxspace = ramsize / 2;
1306 else
1307 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1308
67712901
SH		 1309 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1310 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1311
1312 /* Make sure SyncQ is disabled */
1313 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1314 RB_RST_SET);
1315 }
793b883e 1316
af4ed7e6 1317 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1318
69161611
SH		 1319 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1320 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1321 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1322
977bdf06 1323 /* Set almost empty threshold */
c2716fb4
SH		 1324 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1325 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1326 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1327
6b1a3aef 1328 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1329 TX_RING_SIZE - 1);
cd28ab6a 1330
6b1a3aef 1331 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1332 if (err)
1333 goto err_out;
1334
cd28ab6a 1335 /* Enable interrupts from phy/mac for port */
e07b1aa8 1336 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1337 imask |= portirq_msk[port];
e07b1aa8
SH		 1338 sky2_write32(hw, B0_IMSK, imask);
1339
cd28ab6a
SH		 1340 return 0;
1341
1342err_out:
1b537565 1343 if (sky2->rx_le) {
cd28ab6a
SH		 1344 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1345 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1346 sky2->rx_le = NULL;
1347 }
1348 if (sky2->tx_le) {
cd28ab6a
SH		 1349 pci_free_consistent(hw->pdev,
1350 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1351 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1352 sky2->tx_le = NULL;
1353 }
1354 kfree(sky2->tx_ring);
1355 kfree(sky2->rx_ring);
cd28ab6a 1356
1b537565
SH		 1357 sky2->tx_ring = NULL;
1358 sky2->rx_ring = NULL;
cd28ab6a
SH		 1359 return err;
1360}
1361
793b883e
SH		 1362/* Modular subtraction in ring */
1363static inline int tx_dist(unsigned tail, unsigned head)
1364{
cb5d9547 1365 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1366}
cd28ab6a 1367
793b883e
SH		 1368/* Number of list elements available for next tx */
1369static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1370{
793b883e 1371 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1372}
1373
793b883e 1374/* Estimate of number of transmit list elements required */
28bd181a 1375static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1376{
793b883e
SH		 1377 unsigned count;
1378
1379 count = sizeof(dma_addr_t) / sizeof(u32);
1380 count += skb_shinfo(skb)->nr_frags * count;
1381
89114afd 1382 if (skb_is_gso(skb))
793b883e
SH		 1383 ++count;
1384
84fa7933 1385 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1386 ++count;
1387
1388 return count;
cd28ab6a
SH		 1389}
1390
793b883e
SH		 1391/*
1392 * Put one packet in ring for transmit.
1393 * A single packet can generate multiple list elements, and
1394 * the number of ring elements will probably be less than the number
1395 * of list elements used.
1396 */
cd28ab6a
SH		 1397static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1398{
1399 struct sky2_port *sky2 = netdev_priv(dev);
1400 struct sky2_hw *hw = sky2->hw;
d1f13708 1401 struct sky2_tx_le *le = NULL;
6cdbbdf3 1402 struct tx_ring_info *re;
cd28ab6a
SH		 1403 unsigned i, len;
1404 dma_addr_t mapping;
1405 u32 addr64;
1406 u16 mss;
1407 u8 ctrl;
1408
2bb8c262
SH		 1409 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1410 return NETDEV_TX_BUSY;
cd28ab6a 1411
793b883e 1412 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1413 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1414 dev->name, sky2->tx_prod, skb->len);
1415
cd28ab6a
SH		 1416 len = skb_headlen(skb);
1417 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1418 addr64 = high32(mapping);
793b883e 1419
a018e330 1420 /* Send high bits if changed or crosses boundary */
1421 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1422 le = get_tx_le(sky2);
f65b138c 1423 le->addr = cpu_to_le32(addr64);
793b883e 1424 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1425 sky2->tx_addr64 = high32(mapping + len);
793b883e 1426 }
cd28ab6a
SH		 1427
1428 /* Check for TCP Segmentation Offload */
7967168c 1429 mss = skb_shinfo(skb)->gso_size;
793b883e 1430 if (mss != 0) {
69161611
SH		 1431 if (hw->chip_id != CHIP_ID_YUKON_EX)
1432 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1433
1434 if (mss != sky2->tx_last_mss) {
1435 le = get_tx_le(sky2);
1436 le->addr = cpu_to_le32(mss);
1437 if (hw->chip_id == CHIP_ID_YUKON_EX)
1438 le->opcode = OP_MSS | HW_OWNER;
1439 else
1440 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1441 sky2->tx_last_mss = mss;
1442 }
cd28ab6a
SH		 1443 }
1444
cd28ab6a 1445 ctrl = 0;
d1f13708 1446#ifdef SKY2_VLAN_TAG_USED
1447 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1448 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1449 if (!le) {
1450 le = get_tx_le(sky2);
f65b138c 1451 le->addr = 0;
d1f13708 1452 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1453 } else
1454 le->opcode |= OP_VLAN;
1455 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1456 ctrl |= INS_VLAN;
1457 }
1458#endif
1459
1460 /* Handle TCP checksum offload */
84fa7933 1461 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611
SH		 1462 /* On Yukon EX (some versions) encoding change. */
1463 if (hw->chip_id == CHIP_ID_YUKON_EX
1464 && hw->chip_rev != CHIP_REV_YU_EX_B0)
1465 ctrl |= CALSUM; /* auto checksum */
1466 else {
1467 const unsigned offset = skb_transport_offset(skb);
1468 u32 tcpsum;
1469
1470 tcpsum = offset << 16; /* sum start */
1471 tcpsum |= offset + skb->csum_offset; /* sum write */
1472
1473 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1474 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1475 ctrl |= UDPTCP;
1476
1477 if (tcpsum != sky2->tx_tcpsum) {
1478 sky2->tx_tcpsum = tcpsum;
1479
1480 le = get_tx_le(sky2);
1481 le->addr = cpu_to_le32(tcpsum);
1482 le->length = 0; /* initial checksum value */
1483 le->ctrl = 1; /* one packet */
1484 le->opcode = OP_TCPLISW | HW_OWNER;
1485 }
1d179332 1486 }
cd28ab6a
SH		 1487 }
1488
1489 le = get_tx_le(sky2);
f65b138c 1490 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1491 le->length = cpu_to_le16(len);
1492 le->ctrl = ctrl;
793b883e 1493 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1494
291ea614 1495 re = tx_le_re(sky2, le);
cd28ab6a 1496 re->skb = skb;
6cdbbdf3 1497 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1498 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1499
1500 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1501 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1502
1503 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1504 frag->size, PCI_DMA_TODEVICE);
a036119f 1505 addr64 = high32(mapping);
793b883e
SH		 1506 if (addr64 != sky2->tx_addr64) {
1507 le = get_tx_le(sky2);
f65b138c 1508 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1509 le->ctrl = 0;
1510 le->opcode = OP_ADDR64 | HW_OWNER;
1511 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1512 }
1513
1514 le = get_tx_le(sky2);
f65b138c 1515 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1516 le->length = cpu_to_le16(frag->size);
1517 le->ctrl = ctrl;
793b883e 1518 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1519
291ea614
SH		 1520 re = tx_le_re(sky2, le);
1521 re->skb = skb;
1522 pci_unmap_addr_set(re, mapaddr, mapping);
1523 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1524 }
6cdbbdf3 1525
cd28ab6a
SH		 1526 le->ctrl |= EOP;
1527
97bda706 1528 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1529 netif_stop_queue(dev);
b19666d9 1530
290d4de5 1531 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1532
cd28ab6a
SH		 1533 dev->trans_start = jiffies;
1534 return NETDEV_TX_OK;
1535}
1536
cd28ab6a 1537/*
793b883e
SH		 1538 * Free ring elements from starting at tx_cons until "done"
1539 *
1540 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1541 * buffers so make sure not to free skb to early.
cd28ab6a 1542 */
d11c13e7 1543static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1544{
d11c13e7 1545 struct net_device *dev = sky2->netdev;
af2a58ac 1546 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1547 unsigned idx;
cd28ab6a 1548
0e3ff6aa 1549 BUG_ON(done >= TX_RING_SIZE);
2224795d 1550
291ea614
SH		 1551 for (idx = sky2->tx_cons; idx != done;
1552 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1553 struct sky2_tx_le *le = sky2->tx_le + idx;
1554 struct tx_ring_info *re = sky2->tx_ring + idx;
1555
1556 switch(le->opcode & ~HW_OWNER) {
1557 case OP_LARGESEND:
1558 case OP_PACKET:
1559 pci_unmap_single(pdev,
1560 pci_unmap_addr(re, mapaddr),
1561 pci_unmap_len(re, maplen),
1562 PCI_DMA_TODEVICE);
af2a58ac 1563 break;
291ea614
SH		 1564 case OP_BUFFER:
1565 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1566 pci_unmap_len(re, maplen),
734d1868 1567 PCI_DMA_TODEVICE);
291ea614
SH		 1568 break;
1569 }
1570
1571 if (le->ctrl & EOP) {
1572 if (unlikely(netif_msg_tx_done(sky2)))
1573 printk(KERN_DEBUG "%s: tx done %u\n",
1574 dev->name, idx);
2bf56fe2 1575 sky2->net_stats.tx_packets++;
1576 sky2->net_stats.tx_bytes += re->skb->len;
1577
794b2bd2 1578 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1579 }
1580
291ea614 1581 le->opcode = 0; /* paranoia */
793b883e 1582 }
793b883e 1583
291ea614 1584 sky2->tx_cons = idx;
50432cb5
SH		 1585 smp_mb();
1586
22e11703 1587 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1588 netif_wake_queue(dev);
cd28ab6a
SH		 1589}
1590
1591/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1592static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1593{
2bb8c262
SH		 1594 struct sky2_port *sky2 = netdev_priv(dev);
1595
1596 netif_tx_lock_bh(dev);
d11c13e7 1597 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1598 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1599}
1600
1601/* Network shutdown */
1602static int sky2_down(struct net_device *dev)
1603{
1604 struct sky2_port *sky2 = netdev_priv(dev);
1605 struct sky2_hw *hw = sky2->hw;
1606 unsigned port = sky2->port;
1607 u16 ctrl;
e07b1aa8 1608 u32 imask;
cd28ab6a 1609
1b537565
SH		 1610 /* Never really got started! */
1611 if (!sky2->tx_le)
1612 return 0;
1613
cd28ab6a
SH		 1614 if (netif_msg_ifdown(sky2))
1615 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1616
018d1c66 1617 /* Stop more packets from being queued */
cd28ab6a 1618 netif_stop_queue(dev);
9a87240c 1619 netif_carrier_off(dev);
cd28ab6a 1620
ebc646f6
SH		 1621 /* Disable port IRQ */
1622 imask = sky2_read32(hw, B0_IMSK);
1623 imask &= ~portirq_msk[port];
1624 sky2_write32(hw, B0_IMSK, imask);
1625
d3bcfbeb 1626 sky2_gmac_reset(hw, port);
793b883e 1627
cd28ab6a
SH		 1628 /* Stop transmitter */
1629 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1630 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1631
1632 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1633 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1634
1635 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1636 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1637 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1638
1639 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1640
1641 /* Workaround shared GMAC reset */
793b883e
SH		 1642 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1643 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1644 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1645
1646 /* Disable Force Sync bit and Enable Alloc bit */
1647 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1648 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1649
1650 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1651 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1652 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1653
1654 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1655 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1656 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1657
1658 /* Reset the Tx prefetch units */
1659 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1660 PREF_UNIT_RST_SET);
1661
1662 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1663
6b1a3aef 1664 sky2_rx_stop(sky2);
cd28ab6a
SH		 1665
1666 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1667 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1668
d3bcfbeb 1669 sky2_phy_power(hw, port, 0);
1670
d571b694 1671 /* turn off LED's */
cd28ab6a
SH		 1672 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1673
018d1c66 1674 synchronize_irq(hw->pdev->irq);
1675
2bb8c262 1676 sky2_tx_clean(dev);
cd28ab6a
SH		 1677 sky2_rx_clean(sky2);
1678
1679 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1680 sky2->rx_le, sky2->rx_le_map);
1681 kfree(sky2->rx_ring);
1682
1683 pci_free_consistent(hw->pdev,
1684 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1685 sky2->tx_le, sky2->tx_le_map);
1686 kfree(sky2->tx_ring);
1687
1b537565
SH		 1688 sky2->tx_le = NULL;
1689 sky2->rx_le = NULL;
1690
1691 sky2->rx_ring = NULL;
1692 sky2->tx_ring = NULL;
1693
cd28ab6a
SH		 1694 return 0;
1695}
1696
1697static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1698{
b89165f2 1699 if (!sky2_is_copper(hw))
793b883e
SH		 1700 return SPEED_1000;
1701
cd28ab6a
SH		 1702 if (hw->chip_id == CHIP_ID_YUKON_FE)
1703 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1704
1705 switch (aux & PHY_M_PS_SPEED_MSK) {
1706 case PHY_M_PS_SPEED_1000:
1707 return SPEED_1000;
1708 case PHY_M_PS_SPEED_100:
1709 return SPEED_100;
1710 default:
1711 return SPEED_10;
1712 }
1713}
1714
1715static void sky2_link_up(struct sky2_port *sky2)
1716{
1717 struct sky2_hw *hw = sky2->hw;
1718 unsigned port = sky2->port;
1719 u16 reg;
16ad91e1
SH		 1720 static const char *fc_name[] = {
1721 [FC_NONE] = "none",
1722 [FC_TX] = "tx",
1723 [FC_RX] = "rx",
1724 [FC_BOTH] = "both",
1725 };
cd28ab6a 1726
cd28ab6a 1727 /* enable Rx/Tx */
2eaba1a2 1728 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1729 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1730 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1731
1732 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1733
1734 netif_carrier_on(sky2->netdev);
1735 netif_wake_queue(sky2->netdev);
1736
1737 /* Turn on link LED */
793b883e 1738 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1739 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1740
93745494
SH		 1741 if (hw->chip_id == CHIP_ID_YUKON_XL
1742 || hw->chip_id == CHIP_ID_YUKON_EC_U
1743 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1744 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1745 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1746
1747 switch(sky2->speed) {
1748 case SPEED_10:
1749 led |= PHY_M_LEDC_INIT_CTRL(7);
1750 break;
1751
1752 case SPEED_100:
1753 led |= PHY_M_LEDC_STA1_CTRL(7);
1754 break;
1755
1756 case SPEED_1000:
1757 led |= PHY_M_LEDC_STA0_CTRL(7);
1758 break;
1759 }
793b883e
SH		 1760
1761 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1762 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1763 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1764 }
1765
cd28ab6a
SH		 1766 if (netif_msg_link(sky2))
1767 printk(KERN_INFO PFX
d571b694 1768 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1769 sky2->netdev->name, sky2->speed,
1770 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1771 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1772}
1773
1774static void sky2_link_down(struct sky2_port *sky2)
1775{
1776 struct sky2_hw *hw = sky2->hw;
1777 unsigned port = sky2->port;
1778 u16 reg;
1779
1780 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1781
1782 reg = gma_read16(hw, port, GM_GP_CTRL);
1783 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1784 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1785
cd28ab6a
SH		 1786 netif_carrier_off(sky2->netdev);
1787 netif_stop_queue(sky2->netdev);
1788
1789 /* Turn on link LED */
1790 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1791
1792 if (netif_msg_link(sky2))
1793 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1794
cd28ab6a
SH		 1795 sky2_phy_init(hw, port);
1796}
1797
16ad91e1
SH		 1798static enum flow_control sky2_flow(int rx, int tx)
1799{
1800 if (rx)
1801 return tx ? FC_BOTH : FC_RX;
1802 else
1803 return tx ? FC_TX : FC_NONE;
1804}
1805
793b883e
SH		 1806static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1807{
1808 struct sky2_hw *hw = sky2->hw;
1809 unsigned port = sky2->port;
da4c1ff4 1810 u16 advert, lpa;
793b883e 1811
da4c1ff4 1812 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1813 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1814 if (lpa & PHY_M_AN_RF) {
1815 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1816 return -1;
1817 }
1818
793b883e
SH		 1819 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1820 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1821 sky2->netdev->name);
1822 return -1;
1823 }
1824
793b883e 1825 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1826 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1827
da4c1ff4
SH		 1828 /* Since the pause result bits seem to in different positions on
1829 * different chips. look at registers.
1830 */
1831 if (!sky2_is_copper(hw)) {
1832 /* Shift for bits in fiber PHY */
1833 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1834 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1835
1836 if (advert & ADVERTISE_1000XPAUSE)
1837 advert |= ADVERTISE_PAUSE_CAP;
1838 if (advert & ADVERTISE_1000XPSE_ASYM)
1839 advert |= ADVERTISE_PAUSE_ASYM;
1840 if (lpa & LPA_1000XPAUSE)
1841 lpa |= LPA_PAUSE_CAP;
1842 if (lpa & LPA_1000XPAUSE_ASYM)
1843 lpa |= LPA_PAUSE_ASYM;
1844 }
793b883e 1845
da4c1ff4
SH		 1846 sky2->flow_status = FC_NONE;
1847 if (advert & ADVERTISE_PAUSE_CAP) {
1848 if (lpa & LPA_PAUSE_CAP)
1849 sky2->flow_status = FC_BOTH;
1850 else if (advert & ADVERTISE_PAUSE_ASYM)
1851 sky2->flow_status = FC_RX;
1852 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1853 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1854 sky2->flow_status = FC_TX;
1855 }
793b883e 1856
16ad91e1 1857 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1858 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1859 sky2->flow_status = FC_NONE;
2eaba1a2 1860
da4c1ff4 1861 if (sky2->flow_status & FC_TX)
793b883e
SH		 1862 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1863 else
1864 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1865
1866 return 0;
1867}
cd28ab6a 1868
e07b1aa8
SH		 1869/* Interrupt from PHY */
1870static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1871{
e07b1aa8
SH		 1872 struct net_device *dev = hw->dev[port];
1873 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1874 u16 istatus, phystat;
1875
ebc646f6
SH		 1876 if (!netif_running(dev))
1877 return;
1878
e07b1aa8
SH		 1879 spin_lock(&sky2->phy_lock);
1880 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1881 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1882
cd28ab6a
SH		 1883 if (netif_msg_intr(sky2))
1884 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1885 sky2->netdev->name, istatus, phystat);
1886
2eaba1a2 1887 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1888 if (sky2_autoneg_done(sky2, phystat) == 0)
1889 sky2_link_up(sky2);
1890 goto out;
1891 }
cd28ab6a 1892
793b883e
SH		 1893 if (istatus & PHY_M_IS_LSP_CHANGE)
1894 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1895
793b883e
SH		 1896 if (istatus & PHY_M_IS_DUP_CHANGE)
1897 sky2->duplex =
1898 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1899
793b883e
SH		 1900 if (istatus & PHY_M_IS_LST_CHANGE) {
1901 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1902 sky2_link_up(sky2);
793b883e
SH		 1903 else
1904 sky2_link_down(sky2);
cd28ab6a 1905 }
793b883e 1906out:
e07b1aa8 1907 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1908}
1909
62335ab0 1910/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1911 * and tx queue is full (stopped).
1912 */
cd28ab6a
SH		 1913static void sky2_tx_timeout(struct net_device *dev)
1914{
1915 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1916 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1917
1918 if (netif_msg_timer(sky2))
1919 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1920
8f24664d 1921 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1922 dev->name, sky2->tx_cons, sky2->tx_prod,
1923 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1924 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1925
81906791
SH		 1926 /* can't restart safely under softirq */
1927 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1928}
1929
1930static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1931{
6b1a3aef 1932 struct sky2_port *sky2 = netdev_priv(dev);
1933 struct sky2_hw *hw = sky2->hw;
b628ed98 1934 unsigned port = sky2->port;
6b1a3aef 1935 int err;
1936 u16 ctl, mode;
e07b1aa8 1937 u32 imask;
cd28ab6a
SH		 1938
1939 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1940 return -EINVAL;
1941
d2adf4f6
SH		 1942 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1943 return -EINVAL;
1944
6b1a3aef 1945 if (!netif_running(dev)) {
1946 dev->mtu = new_mtu;
1947 return 0;
1948 }
1949
e07b1aa8 1950 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1951 sky2_write32(hw, B0_IMSK, 0);
1952
018d1c66 1953 dev->trans_start = jiffies; /* prevent tx timeout */
1954 netif_stop_queue(dev);
1955 netif_poll_disable(hw->dev[0]);
1956
e07b1aa8
SH		 1957 synchronize_irq(hw->pdev->irq);
1958
69161611
SH		 1959 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1960 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 1961
1962 ctl = gma_read16(hw, port, GM_GP_CTRL);
1963 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 1964 sky2_rx_stop(sky2);
1965 sky2_rx_clean(sky2);
cd28ab6a
SH		 1966
1967 dev->mtu = new_mtu;
14d0263f 1968
6b1a3aef 1969 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1970 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1971
1972 if (dev->mtu > ETH_DATA_LEN)
1973 mode |= GM_SMOD_JUMBO_ENA;
1974
b628ed98 1975 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1976
b628ed98 1977 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1978
6b1a3aef 1979 err = sky2_rx_start(sky2);
e07b1aa8 1980 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1981
1b537565
SH		 1982 if (err)
1983 dev_close(dev);
1984 else {
b628ed98 1985 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1986
1987 netif_poll_enable(hw->dev[0]);
1988 netif_wake_queue(dev);
1989 }
1990
cd28ab6a
SH		 1991 return err;
1992}
1993
14d0263f
SH		 1994/* For small just reuse existing skb for next receive */
1995static struct sk_buff *receive_copy(struct sky2_port *sky2,
1996 const struct rx_ring_info *re,
1997 unsigned length)
1998{
1999 struct sk_buff *skb;
2000
2001 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2002 if (likely(skb)) {
2003 skb_reserve(skb, 2);
2004 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2005 length, PCI_DMA_FROMDEVICE);
d626f62b 2006 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2007 skb->ip_summed = re->skb->ip_summed;
2008 skb->csum = re->skb->csum;
2009 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2010 length, PCI_DMA_FROMDEVICE);
2011 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2012 skb_put(skb, length);
14d0263f
SH		 2013 }
2014 return skb;
2015}
2016
2017/* Adjust length of skb with fragments to match received data */
2018static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2019 unsigned int length)
2020{
2021 int i, num_frags;
2022 unsigned int size;
2023
2024 /* put header into skb */
2025 size = min(length, hdr_space);
2026 skb->tail += size;
2027 skb->len += size;
2028 length -= size;
2029
2030 num_frags = skb_shinfo(skb)->nr_frags;
2031 for (i = 0; i < num_frags; i++) {
2032 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2033
2034 if (length == 0) {
2035 /* don't need this page */
2036 __free_page(frag->page);
2037 --skb_shinfo(skb)->nr_frags;
2038 } else {
2039 size = min(length, (unsigned) PAGE_SIZE);
2040
2041 frag->size = size;
2042 skb->data_len += size;
2043 skb->truesize += size;
2044 skb->len += size;
2045 length -= size;
2046 }
2047 }
2048}
2049
2050/* Normal packet - take skb from ring element and put in a new one */
2051static struct sk_buff *receive_new(struct sky2_port *sky2,
2052 struct rx_ring_info *re,
2053 unsigned int length)
2054{
2055 struct sk_buff *skb, *nskb;
2056 unsigned hdr_space = sky2->rx_data_size;
2057
2058 pr_debug(PFX "receive new length=%d\n", length);
2059
2060 /* Don't be tricky about reusing pages (yet) */
2061 nskb = sky2_rx_alloc(sky2);
2062 if (unlikely(!nskb))
2063 return NULL;
2064
2065 skb = re->skb;
2066 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2067
2068 prefetch(skb->data);
2069 re->skb = nskb;
2070 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2071
2072 if (skb_shinfo(skb)->nr_frags)
2073 skb_put_frags(skb, hdr_space, length);
2074 else
489b10c1 2075 skb_put(skb, length);
14d0263f
SH		 2076 return skb;
2077}
2078
cd28ab6a
SH		 2079/*
2080 * Receive one packet.
d571b694 2081 * For larger packets, get new buffer.
cd28ab6a 2082 */
497d7c86 2083static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2084 u16 length, u32 status)
2085{
497d7c86 2086 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2087 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2088 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2089
2090 if (unlikely(netif_msg_rx_status(sky2)))
2091 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2092 dev->name, sky2->rx_next, status, length);
cd28ab6a 2093
793b883e 2094 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2095 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2096
42eeea01 2097 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2098 goto error;
2099
42eeea01 2100 if (!(status & GMR_FS_RX_OK))
2101 goto resubmit;
2102
14d0263f
SH		 2103 if (length < copybreak)
2104 skb = receive_copy(sky2, re, length);
2105 else
2106 skb = receive_new(sky2, re, length);
793b883e 2107resubmit:
14d0263f 2108 sky2_rx_submit(sky2, re);
79e57d32 2109
cd28ab6a
SH		 2110 return skb;
2111
2112error:
6e15b712 2113 ++sky2->net_stats.rx_errors;
b6d77734 2114 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2115 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2116 goto resubmit;
2117 }
6e15b712 2118
3be92a70 2119 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2120 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2121 dev->name, status, length);
793b883e
SH		 2122
2123 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2124 sky2->net_stats.rx_length_errors++;
2125 if (status & GMR_FS_FRAGMENT)
2126 sky2->net_stats.rx_frame_errors++;
2127 if (status & GMR_FS_CRC_ERR)
2128 sky2->net_stats.rx_crc_errors++;
79e57d32 2129
793b883e 2130 goto resubmit;
cd28ab6a
SH		 2131}
2132
e07b1aa8
SH		 2133/* Transmit complete */
2134static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2135{
e07b1aa8 2136 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2137
e07b1aa8 2138 if (netif_running(dev)) {
2bb8c262 2139 netif_tx_lock(dev);
e07b1aa8 2140 sky2_tx_complete(sky2, last);
2bb8c262 2141 netif_tx_unlock(dev);
2224795d 2142 }
cd28ab6a
SH		 2143}
2144
e07b1aa8
SH		 2145/* Process status response ring */
2146static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2147{
22e11703 2148 struct sky2_port *sky2;
e07b1aa8 2149 int work_done = 0;
22e11703 2150 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2151 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2152
af2a58ac 2153 rmb();
bea86103 2154
e71ebd73 2155 while (hw->st_idx != hwidx) {
13210ce5 2156 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2157 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2158 struct net_device *dev;
cd28ab6a 2159 struct sk_buff *skb;
cd28ab6a
SH		 2160 u32 status;
2161 u16 length;
2162
cb5d9547 2163 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2164
69161611 2165 dev = hw->dev[port];
13210ce5 2166 sky2 = netdev_priv(dev);
f65b138c
SH		 2167 length = le16_to_cpu(le->length);
2168 status = le32_to_cpu(le->status);
cd28ab6a 2169
e71ebd73 2170 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2171 case OP_RXSTAT:
497d7c86 2172 skb = sky2_receive(dev, length, status);
3225b919
SH		 2173 if (unlikely(!skb)) {
2174 sky2->net_stats.rx_dropped++;
5df79111 2175 goto force_update;
3225b919 2176 }
13210ce5 2177
69161611
SH		 2178 /* This chip reports checksum status differently */
2179 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2180 if (sky2->rx_csum &&
2181 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2182 (le->css & CSS_TCPUDPCSOK))
2183 skb->ip_summed = CHECKSUM_UNNECESSARY;
2184 else
2185 skb->ip_summed = CHECKSUM_NONE;
2186 }
2187
13210ce5 2188 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2189 sky2->net_stats.rx_packets++;
2190 sky2->net_stats.rx_bytes += skb->len;
13210ce5 2191 dev->last_rx = jiffies;
2192
d1f13708 2193#ifdef SKY2_VLAN_TAG_USED
2194 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2195 vlan_hwaccel_receive_skb(skb,
2196 sky2->vlgrp,
2197 be16_to_cpu(sky2->rx_tag));
2198 } else
2199#endif
cd28ab6a 2200 netif_receive_skb(skb);
13210ce5 2201
22e11703 2202 /* Update receiver after 16 frames */
69161611 2203 if (++buf_write[port] == RX_BUF_WRITE) {
5df79111 2204force_update:
69161611
SH		 2205 sky2_put_idx(hw, rxqaddr[port], sky2->rx_put);
2206 buf_write[port] = 0;
22e11703
SH		 2207 }
2208
2209 /* Stop after net poll weight */
13210ce5 2210 if (++work_done >= to_do)
2211 goto exit_loop;
cd28ab6a
SH		 2212 break;
2213
d1f13708 2214#ifdef SKY2_VLAN_TAG_USED
2215 case OP_RXVLAN:
2216 sky2->rx_tag = length;
2217 break;
2218
2219 case OP_RXCHKSVLAN:
2220 sky2->rx_tag = length;
2221 /* fall through */
2222#endif
cd28ab6a 2223 case OP_RXCHKS:
87418307
SH		 2224 if (!sky2->rx_csum)
2225 break;
2226
69161611
SH		 2227 if (hw->chip_id == CHIP_ID_YUKON_EX)
2228 break;
2229
87418307
SH		 2230 /* Both checksum counters are programmed to start at
2231 * the same offset, so unless there is a problem they
2232 * should match. This failure is an early indication that
2233 * hardware receive checksumming won't work.
2234 */
2235 if (likely(status >> 16 == (status & 0xffff))) {
2236 skb = sky2->rx_ring[sky2->rx_next].skb;
2237 skb->ip_summed = CHECKSUM_COMPLETE;
2238 skb->csum = status & 0xffff;
2239 } else {
2240 printk(KERN_NOTICE PFX "%s: hardware receive "
2241 "checksum problem (status = %#x)\n",
2242 dev->name, status);
2243 sky2->rx_csum = 0;
2244 sky2_write32(sky2->hw,
69161611 2245 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2246 BMU_DIS_RX_CHKSUM);
2247 }
cd28ab6a
SH		 2248 break;
2249
2250 case OP_TXINDEXLE:
13b97b74 2251 /* TX index reports status for both ports */
f55925d7
SH		 2252 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2253 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2254 if (hw->dev[1])
2255 sky2_tx_done(hw->dev[1],
2256 ((status >> 24) & 0xff)
2257 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2258 break;
2259
cd28ab6a
SH		 2260 default:
2261 if (net_ratelimit())
793b883e 2262 printk(KERN_WARNING PFX
e71ebd73
SH		 2263 "unknown status opcode 0x%x\n", le->opcode);
2264 goto exit_loop;
cd28ab6a 2265 }
13210ce5 2266 }
cd28ab6a 2267
fe2a24df
SH		 2268 /* Fully processed status ring so clear irq */
2269 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
50432cb5 2270 mmiowb();
fe2a24df 2271
13210ce5 2272exit_loop:
22e11703
SH		 2273 if (buf_write[0]) {
2274 sky2 = netdev_priv(hw->dev[0]);
2275 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2276 }
2277
2278 if (buf_write[1]) {
2279 sky2 = netdev_priv(hw->dev[1]);
2280 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2281 }
2282
e07b1aa8 2283 return work_done;
cd28ab6a
SH		 2284}
2285
2286static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2287{
2288 struct net_device *dev = hw->dev[port];
2289
3be92a70
SH		 2290 if (net_ratelimit())
2291 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2292 dev->name, status);
cd28ab6a
SH		 2293
2294 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2295 if (net_ratelimit())
2296 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2297 dev->name);
cd28ab6a
SH		 2298 /* Clear IRQ */
2299 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2300 }
2301
2302 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2303 if (net_ratelimit())
2304 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2305 dev->name);
cd28ab6a
SH		 2306
2307 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2308 }
2309
2310 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2311 if (net_ratelimit())
2312 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2313 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2314 }
2315
2316 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2317 if (net_ratelimit())
2318 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2319 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2320 }
2321
2322 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2323 if (net_ratelimit())
2324 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2325 dev->name);
cd28ab6a
SH		 2326 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2327 }
2328}
2329
2330static void sky2_hw_intr(struct sky2_hw *hw)
2331{
2332 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2333
793b883e 2334 if (status & Y2_IS_TIST_OV)
cd28ab6a 2335 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2336
2337 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2338 u16 pci_err;
2339
56a645cc 2340 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2341 if (net_ratelimit())
b02a9258
SH		 2342 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2343 pci_err);
cd28ab6a
SH		 2344
2345 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2346 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2347 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2348 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2349 }
2350
2351 if (status & Y2_IS_PCI_EXP) {
d571b694 2352 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2353 u32 pex_err;
2354
7bd656d1 2355 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2356
3be92a70 2357 if (net_ratelimit())
b02a9258
SH		 2358 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2359 pex_err);
cd28ab6a
SH		 2360
2361 /* clear the interrupt */
2362 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2363 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2364 0xffffffffUL);
cd28ab6a
SH		 2365 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2366
7bd656d1 2367 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2368 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2369 hwmsk &= ~Y2_IS_PCI_EXP;
2370 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2371 }
2372 }
2373
2374 if (status & Y2_HWE_L1_MASK)
2375 sky2_hw_error(hw, 0, status);
2376 status >>= 8;
2377 if (status & Y2_HWE_L1_MASK)
2378 sky2_hw_error(hw, 1, status);
2379}
2380
2381static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2382{
2383 struct net_device *dev = hw->dev[port];
2384 struct sky2_port *sky2 = netdev_priv(dev);
2385 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2386
2387 if (netif_msg_intr(sky2))
2388 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2389 dev->name, status);
2390
a3caeada
SH		 2391 if (status & GM_IS_RX_CO_OV)
2392 gma_read16(hw, port, GM_RX_IRQ_SRC);
2393
2394 if (status & GM_IS_TX_CO_OV)
2395 gma_read16(hw, port, GM_TX_IRQ_SRC);
2396
cd28ab6a
SH		 2397 if (status & GM_IS_RX_FF_OR) {
2398 ++sky2->net_stats.rx_fifo_errors;
2399 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2400 }
2401
2402 if (status & GM_IS_TX_FF_UR) {
2403 ++sky2->net_stats.tx_fifo_errors;
2404 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2405 }
cd28ab6a
SH		 2406}
2407
40b01727
SH		 2408/* This should never happen it is a bug. */
2409static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2410 u16 q, unsigned ring_size)
d257924e
SH		 2411{
2412 struct net_device *dev = hw->dev[port];
2413 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2414 unsigned idx;
2415 const u64 *le = (q == Q_R1 || q == Q_R2)
2416 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2417
40b01727
SH		 2418 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2419 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2420 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2421 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2422
40b01727 2423 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2424}
cd28ab6a 2425
d27ed387
SH		 2426/* If idle then force a fake soft NAPI poll once a second
2427 * to work around cases where sharing an edge triggered interrupt.
2428 */
eb35cf60
SH		 2429static inline void sky2_idle_start(struct sky2_hw *hw)
2430{
2431 if (idle_timeout > 0)
2432 mod_timer(&hw->idle_timer,
2433 jiffies + msecs_to_jiffies(idle_timeout));
2434}
2435
d27ed387
SH		 2436static void sky2_idle(unsigned long arg)
2437{
01bd7564
SH		 2438 struct sky2_hw *hw = (struct sky2_hw *) arg;
2439 struct net_device *dev = hw->dev[0];
d27ed387 2440
d27ed387
SH		 2441 if (__netif_rx_schedule_prep(dev))
2442 __netif_rx_schedule(dev);
01bd7564
SH		 2443
2444 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2445}
2446
40b01727
SH		 2447/* Hardware/software error handling */
2448static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2449{
40b01727
SH		 2450 if (net_ratelimit())
2451 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2452
1e5f1283
SH		 2453 if (status & Y2_IS_HW_ERR)
2454 sky2_hw_intr(hw);
d257924e 2455
1e5f1283
SH		 2456 if (status & Y2_IS_IRQ_MAC1)
2457 sky2_mac_intr(hw, 0);
cd28ab6a 2458
1e5f1283
SH		 2459 if (status & Y2_IS_IRQ_MAC2)
2460 sky2_mac_intr(hw, 1);
cd28ab6a 2461
1e5f1283 2462 if (status & Y2_IS_CHK_RX1)
40b01727 2463 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2464
1e5f1283 2465 if (status & Y2_IS_CHK_RX2)
40b01727 2466 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2467
1e5f1283 2468 if (status & Y2_IS_CHK_TXA1)
40b01727 2469 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2470
1e5f1283 2471 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2472 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2473}
2474
2475static int sky2_poll(struct net_device *dev0, int *budget)
2476{
2477 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2478 int work_limit = min(dev0->quota, *budget);
2479 int work_done = 0;
2480 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2481
2482 if (unlikely(status & Y2_IS_ERROR))
2483 sky2_err_intr(hw, status);
2484
2485 if (status & Y2_IS_IRQ_PHY1)
2486 sky2_phy_intr(hw, 0);
2487
2488 if (status & Y2_IS_IRQ_PHY2)
2489 sky2_phy_intr(hw, 1);
cd28ab6a 2490
1e5f1283 2491 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2492 if (work_done < work_limit) {
2493 netif_rx_complete(dev0);
86fba634 2494
50432cb5 2495 /* end of interrupt, re-enables also acts as I/O synchronization */
fe2a24df
SH		 2496 sky2_read32(hw, B0_Y2_SP_LISR);
2497 return 0;
2498 } else {
2499 *budget -= work_done;
2500 dev0->quota -= work_done;
1e5f1283 2501 return 1;
fe2a24df 2502 }
e07b1aa8
SH		 2503}
2504
7d12e780 2505static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2506{
2507 struct sky2_hw *hw = dev_id;
2508 struct net_device *dev0 = hw->dev[0];
2509 u32 status;
2510
2511 /* Reading this mask interrupts as side effect */
2512 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2513 if (status == 0 || status == ~0)
2514 return IRQ_NONE;
793b883e 2515
e07b1aa8
SH		 2516 prefetch(&hw->st_le[hw->st_idx]);
2517 if (likely(__netif_rx_schedule_prep(dev0)))
2518 __netif_rx_schedule(dev0);
793b883e 2519
cd28ab6a
SH		 2520 return IRQ_HANDLED;
2521}
2522
2523#ifdef CONFIG_NET_POLL_CONTROLLER
2524static void sky2_netpoll(struct net_device *dev)
2525{
2526 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2527 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2528
88d11360
SH		 2529 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2530 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2531}
2532#endif
2533
2534/* Chip internal frequency for clock calculations */
fb17358f 2535static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2536{
793b883e 2537 switch (hw->chip_id) {
cd28ab6a 2538 case CHIP_ID_YUKON_EC:
5a5b1ea0 2539 case CHIP_ID_YUKON_EC_U:
93745494 2540 case CHIP_ID_YUKON_EX:
fb17358f 2541 return 125; /* 125 Mhz */
cd28ab6a 2542 case CHIP_ID_YUKON_FE:
fb17358f 2543 return 100; /* 100 Mhz */
793b883e 2544 default: /* YUKON_XL */
fb17358f 2545 return 156; /* 156 Mhz */
cd28ab6a
SH		 2546 }
2547}
2548
fb17358f 2549static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2550{
fb17358f 2551 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2552}
2553
fb17358f 2554static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2555{
fb17358f 2556 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2557}
2558
fb17358f 2559
e3173832 2560static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2561{
b89165f2 2562 u8 t8;
cd28ab6a 2563
451af335
SH		 2564 /* Enable all clocks */
2565 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2566
cd28ab6a 2567 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2568
cd28ab6a
SH		 2569 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2570 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2571 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2572 hw->chip_id);
cd28ab6a
SH		 2573 return -EOPNOTSUPP;
2574 }
2575
290d4de5
SH		 2576 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2577
2578 /* This rev is really old, and requires untested workarounds */
2579 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2580 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2581 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2582 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2583 return -EOPNOTSUPP;
2584 }
2585
e3173832
SH		 2586 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2587 hw->ports = 1;
2588 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2589 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2590 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2591 ++hw->ports;
2592 }
2593
2594 return 0;
2595}
2596
2597static void sky2_reset(struct sky2_hw *hw)
2598{
2599 u16 status;
2600 int i;
2601
cd28ab6a 2602 /* disable ASF */
4f44d8ba
SH		 2603 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2604 status = sky2_read16(hw, HCU_CCSR);
2605 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2606 HCU_CCSR_UC_STATE_MSK);
2607 sky2_write16(hw, HCU_CCSR, status);
2608 } else
2609 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2610 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2611
2612 /* do a SW reset */
2613 sky2_write8(hw, B0_CTST, CS_RST_SET);
2614 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2615
2616 /* clear PCI errors, if any */
56a645cc 2617 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2618
cd28ab6a 2619 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2620 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2621
cd28ab6a
SH		 2622
2623 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2624
2625 /* clear any PEX errors */
7bd656d1
SH		 2626 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2627 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2628
cd28ab6a 2629
ae306cca 2630 sky2_power_on(hw);
cd28ab6a
SH		 2631
2632 for (i = 0; i < hw->ports; i++) {
2633 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2634 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2635
2636 if (hw->chip_id == CHIP_ID_YUKON_EX)
2637 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2638 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2639 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2640 }
2641
2642 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2643
793b883e
SH		 2644 /* Clear I2C IRQ noise */
2645 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2646
2647 /* turn off hardware timer (unused) */
2648 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2649 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2650
cd28ab6a
SH		 2651 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2652
69634ee7
SH		 2653 /* Turn off descriptor polling */
2654 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2655
2656 /* Turn off receive timestamp */
2657 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2658 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2659
2660 /* enable the Tx Arbiters */
2661 for (i = 0; i < hw->ports; i++)
2662 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2663
2664 /* Initialize ram interface */
2665 for (i = 0; i < hw->ports; i++) {
793b883e 2666 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2667
2668 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2669 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2670 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2671 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2672 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2673 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2674 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2675 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2676 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2677 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2678 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2679 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2680 }
2681
7bd656d1 2682 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2683
cd28ab6a 2684 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2685 sky2_gmac_reset(hw, i);
cd28ab6a 2686
cd28ab6a
SH		 2687 memset(hw->st_le, 0, STATUS_LE_BYTES);
2688 hw->st_idx = 0;
2689
2690 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2691 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2692
2693 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2694 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2695
2696 /* Set the list last index */
793b883e 2697 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2698
290d4de5
SH		 2699 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2700 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2701
290d4de5
SH		 2702 /* set Status-FIFO ISR watermark */
2703 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2704 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2705 else
2706 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2707
290d4de5 2708 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2709 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2710 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2711
793b883e 2712 /* enable status unit */
cd28ab6a
SH		 2713 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2714
2715 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2716 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2717 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2718}
2719
81906791
SH		 2720static void sky2_restart(struct work_struct *work)
2721{
2722 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2723 struct net_device *dev;
2724 int i, err;
2725
2726 dev_dbg(&hw->pdev->dev, "restarting\n");
2727
2728 del_timer_sync(&hw->idle_timer);
2729
2730 rtnl_lock();
2731 sky2_write32(hw, B0_IMSK, 0);
2732 sky2_read32(hw, B0_IMSK);
2733
2734 netif_poll_disable(hw->dev[0]);
2735
2736 for (i = 0; i < hw->ports; i++) {
2737 dev = hw->dev[i];
2738 if (netif_running(dev))
2739 sky2_down(dev);
2740 }
2741
2742 sky2_reset(hw);
2743 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2744 netif_poll_enable(hw->dev[0]);
2745
2746 for (i = 0; i < hw->ports; i++) {
2747 dev = hw->dev[i];
2748 if (netif_running(dev)) {
2749 err = sky2_up(dev);
2750 if (err) {
2751 printk(KERN_INFO PFX "%s: could not restart %d\n",
2752 dev->name, err);
2753 dev_close(dev);
2754 }
2755 }
2756 }
2757
2758 sky2_idle_start(hw);
2759
2760 rtnl_unlock();
2761}
2762
e3173832
SH		 2763static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2764{
2765 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2766}
2767
2768static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2769{
2770 const struct sky2_port *sky2 = netdev_priv(dev);
2771
2772 wol->supported = sky2_wol_supported(sky2->hw);
2773 wol->wolopts = sky2->wol;
2774}
2775
2776static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2777{
2778 struct sky2_port *sky2 = netdev_priv(dev);
2779 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2780
e3173832
SH		 2781 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2782 return -EOPNOTSUPP;
2783
2784 sky2->wol = wol->wolopts;
2785
69161611 2786 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
e3173832
SH		 2787 sky2_write32(hw, B0_CTST, sky2->wol
2788 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2789
2790 if (!netif_running(dev))
2791 sky2_wol_init(sky2);
cd28ab6a
SH		 2792 return 0;
2793}
2794
28bd181a 2795static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2796{
b89165f2
SH		 2797 if (sky2_is_copper(hw)) {
2798 u32 modes = SUPPORTED_10baseT_Half
2799 | SUPPORTED_10baseT_Full
2800 | SUPPORTED_100baseT_Half
2801 | SUPPORTED_100baseT_Full
2802 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2803
2804 if (hw->chip_id != CHIP_ID_YUKON_FE)
2805 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2806 | SUPPORTED_1000baseT_Full;
2807 return modes;
cd28ab6a 2808 } else
b89165f2
SH		 2809 return SUPPORTED_1000baseT_Half
2810 | SUPPORTED_1000baseT_Full
2811 | SUPPORTED_Autoneg
2812 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2813}
2814
793b883e 2815static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2816{
2817 struct sky2_port *sky2 = netdev_priv(dev);
2818 struct sky2_hw *hw = sky2->hw;
2819
2820 ecmd->transceiver = XCVR_INTERNAL;
2821 ecmd->supported = sky2_supported_modes(hw);
2822 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2823 if (sky2_is_copper(hw)) {
cd28ab6a 2824 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2825 | SUPPORTED_10baseT_Full
2826 | SUPPORTED_100baseT_Half
2827 | SUPPORTED_100baseT_Full
2828 | SUPPORTED_1000baseT_Half
2829 | SUPPORTED_1000baseT_Full
2830 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2831 ecmd->port = PORT_TP;
b89165f2
SH		 2832 ecmd->speed = sky2->speed;
2833 } else {
2834 ecmd->speed = SPEED_1000;
cd28ab6a 2835 ecmd->port = PORT_FIBRE;
b89165f2 2836 }
cd28ab6a
SH		 2837
2838 ecmd->advertising = sky2->advertising;
2839 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2840 ecmd->duplex = sky2->duplex;
2841 return 0;
2842}
2843
2844static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2845{
2846 struct sky2_port *sky2 = netdev_priv(dev);
2847 const struct sky2_hw *hw = sky2->hw;
2848 u32 supported = sky2_supported_modes(hw);
2849
2850 if (ecmd->autoneg == AUTONEG_ENABLE) {
2851 ecmd->advertising = supported;
2852 sky2->duplex = -1;
2853 sky2->speed = -1;
2854 } else {
2855 u32 setting;
2856
793b883e 2857 switch (ecmd->speed) {
cd28ab6a
SH		 2858 case SPEED_1000:
2859 if (ecmd->duplex == DUPLEX_FULL)
2860 setting = SUPPORTED_1000baseT_Full;
2861 else if (ecmd->duplex == DUPLEX_HALF)
2862 setting = SUPPORTED_1000baseT_Half;
2863 else
2864 return -EINVAL;
2865 break;
2866 case SPEED_100:
2867 if (ecmd->duplex == DUPLEX_FULL)
2868 setting = SUPPORTED_100baseT_Full;
2869 else if (ecmd->duplex == DUPLEX_HALF)
2870 setting = SUPPORTED_100baseT_Half;
2871 else
2872 return -EINVAL;
2873 break;
2874
2875 case SPEED_10:
2876 if (ecmd->duplex == DUPLEX_FULL)
2877 setting = SUPPORTED_10baseT_Full;
2878 else if (ecmd->duplex == DUPLEX_HALF)
2879 setting = SUPPORTED_10baseT_Half;
2880 else
2881 return -EINVAL;
2882 break;
2883 default:
2884 return -EINVAL;
2885 }
2886
2887 if ((setting & supported) == 0)
2888 return -EINVAL;
2889
2890 sky2->speed = ecmd->speed;
2891 sky2->duplex = ecmd->duplex;
2892 }
2893
2894 sky2->autoneg = ecmd->autoneg;
2895 sky2->advertising = ecmd->advertising;
2896
1b537565
SH		 2897 if (netif_running(dev))
2898 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2899
2900 return 0;
2901}
2902
2903static void sky2_get_drvinfo(struct net_device *dev,
2904 struct ethtool_drvinfo *info)
2905{
2906 struct sky2_port *sky2 = netdev_priv(dev);
2907
2908 strcpy(info->driver, DRV_NAME);
2909 strcpy(info->version, DRV_VERSION);
2910 strcpy(info->fw_version, "N/A");
2911 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2912}
2913
2914static const struct sky2_stat {
793b883e
SH		 2915 char name[ETH_GSTRING_LEN];
2916 u16 offset;
cd28ab6a
SH		 2917} sky2_stats[] = {
2918 { "tx_bytes", GM_TXO_OK_HI },
2919 { "rx_bytes", GM_RXO_OK_HI },
2920 { "tx_broadcast", GM_TXF_BC_OK },
2921 { "rx_broadcast", GM_RXF_BC_OK },
2922 { "tx_multicast", GM_TXF_MC_OK },
2923 { "rx_multicast", GM_RXF_MC_OK },
2924 { "tx_unicast", GM_TXF_UC_OK },
2925 { "rx_unicast", GM_RXF_UC_OK },
2926 { "tx_mac_pause", GM_TXF_MPAUSE },
2927 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2928 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2929 { "late_collision",GM_TXF_LAT_COL },
2930 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2931 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2932 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2933
d2604540 2934 { "rx_short", GM_RXF_SHT },
cd28ab6a 2935 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2936 { "rx_64_byte_packets", GM_RXF_64B },
2937 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2938 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2939 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2940 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2941 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2942 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2943 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2944 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2945 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2946 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2947
2948 { "tx_64_byte_packets", GM_TXF_64B },
2949 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2950 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2951 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2952 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2953 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2954 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2955 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2956};
2957
cd28ab6a
SH		 2958static u32 sky2_get_rx_csum(struct net_device *dev)
2959{
2960 struct sky2_port *sky2 = netdev_priv(dev);
2961
2962 return sky2->rx_csum;
2963}
2964
2965static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2966{
2967 struct sky2_port *sky2 = netdev_priv(dev);
2968
2969 sky2->rx_csum = data;
793b883e 2970
cd28ab6a
SH		 2971 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2972 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2973
2974 return 0;
2975}
2976
2977static u32 sky2_get_msglevel(struct net_device *netdev)
2978{
2979 struct sky2_port *sky2 = netdev_priv(netdev);
2980 return sky2->msg_enable;
2981}
2982
9a7ae0a9
SH		 2983static int sky2_nway_reset(struct net_device *dev)
2984{
2985 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2986
16ad91e1 2987 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2988 return -EINVAL;
2989
1b537565 2990 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2991
2992 return 0;
2993}
2994
793b883e 2995static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2996{
2997 struct sky2_hw *hw = sky2->hw;
2998 unsigned port = sky2->port;
2999 int i;
3000
3001 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3002 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3003 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3004 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3005
793b883e 3006 for (i = 2; i < count; i++)
cd28ab6a
SH		 3007 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3008}
3009
cd28ab6a
SH		 3010static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3011{
3012 struct sky2_port *sky2 = netdev_priv(netdev);
3013 sky2->msg_enable = value;
3014}
3015
3016static int sky2_get_stats_count(struct net_device *dev)
3017{
3018 return ARRAY_SIZE(sky2_stats);
3019}
3020
3021static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3022 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3023{
3024 struct sky2_port *sky2 = netdev_priv(dev);
3025
793b883e 3026 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3027}
3028
793b883e 3029static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3030{
3031 int i;
3032
3033 switch (stringset) {
3034 case ETH_SS_STATS:
3035 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3036 memcpy(data + i * ETH_GSTRING_LEN,
3037 sky2_stats[i].name, ETH_GSTRING_LEN);
3038 break;
3039 }
3040}
3041
cd28ab6a
SH		 3042static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3043{
3044 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3045 return &sky2->net_stats;
3046}
3047
3048static int sky2_set_mac_address(struct net_device *dev, void *p)
3049{
3050 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3051 struct sky2_hw *hw = sky2->hw;
3052 unsigned port = sky2->port;
3053 const struct sockaddr *addr = p;
cd28ab6a
SH		 3054
3055 if (!is_valid_ether_addr(addr->sa_data))
3056 return -EADDRNOTAVAIL;
3057
cd28ab6a 3058 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3059 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3060 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3061 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3062 dev->dev_addr, ETH_ALEN);
1b537565 3063
a8ab1ec0
SH		 3064 /* virtual address for data */
3065 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3066
3067 /* physical address: used for pause frames */
3068 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3069
3070 return 0;
cd28ab6a
SH		 3071}
3072
a052b52f
SH		 3073static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3074{
3075 u32 bit;
3076
3077 bit = ether_crc(ETH_ALEN, addr) & 63;
3078 filter[bit >> 3] |= 1 << (bit & 7);
3079}
3080
cd28ab6a
SH		 3081static void sky2_set_multicast(struct net_device *dev)
3082{
3083 struct sky2_port *sky2 = netdev_priv(dev);
3084 struct sky2_hw *hw = sky2->hw;
3085 unsigned port = sky2->port;
3086 struct dev_mc_list *list = dev->mc_list;
3087 u16 reg;
3088 u8 filter[8];
a052b52f
SH		 3089 int rx_pause;
3090 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3091
a052b52f 3092 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3093 memset(filter, 0, sizeof(filter));
3094
3095 reg = gma_read16(hw, port, GM_RX_CTRL);
3096 reg |= GM_RXCR_UCF_ENA;
3097
d571b694 3098 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3099 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3100 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3101 memset(filter, 0xff, sizeof(filter));
a052b52f 3102 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3103 reg &= ~GM_RXCR_MCF_ENA;
3104 else {
3105 int i;
3106 reg |= GM_RXCR_MCF_ENA;
3107
a052b52f
SH		 3108 if (rx_pause)
3109 sky2_add_filter(filter, pause_mc_addr);
3110
3111 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3112 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3113 }
3114
cd28ab6a 3115 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3116 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3117 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3118 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3119 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3120 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3121 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3122 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3123
3124 gma_write16(hw, port, GM_RX_CTRL, reg);
3125}
3126
3127/* Can have one global because blinking is controlled by
3128 * ethtool and that is always under RTNL mutex
3129 */
91c86df5 3130static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3131{
793b883e
SH		 3132 u16 pg;
3133
793b883e
SH		 3134 switch (hw->chip_id) {
3135 case CHIP_ID_YUKON_XL:
3136 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3137 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3138 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3139 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3140 PHY_M_LEDC_INIT_CTRL(7) |
3141 PHY_M_LEDC_STA1_CTRL(7) |
3142 PHY_M_LEDC_STA0_CTRL(7))
3143 : 0);
3144
3145 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3146 break;
3147
3148 default:
3149 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3150 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3151 on ? PHY_M_LED_ALL : 0);
793b883e 3152 }
cd28ab6a
SH		 3153}
3154
3155/* blink LED's for finding board */
3156static int sky2_phys_id(struct net_device *dev, u32 data)
3157{
3158 struct sky2_port *sky2 = netdev_priv(dev);
3159 struct sky2_hw *hw = sky2->hw;
3160 unsigned port = sky2->port;
793b883e 3161 u16 ledctrl, ledover = 0;
cd28ab6a 3162 long ms;
91c86df5 3163 int interrupted;
cd28ab6a
SH		 3164 int onoff = 1;
3165
793b883e 3166 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3167 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3168 else
3169 ms = data * 1000;
3170
3171 /* save initial values */
e07b1aa8 3172 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3173 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3174 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3175 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3176 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3177 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3178 } else {
3179 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3180 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3181 }
cd28ab6a 3182
91c86df5
SH		 3183 interrupted = 0;
3184 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3185 sky2_led(hw, port, onoff);
3186 onoff = !onoff;
3187
e07b1aa8 3188 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3189 interrupted = msleep_interruptible(250);
e07b1aa8 3190 spin_lock_bh(&sky2->phy_lock);
91c86df5 3191
cd28ab6a
SH		 3192 ms -= 250;
3193 }
3194
3195 /* resume regularly scheduled programming */
793b883e
SH		 3196 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3197 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3198 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3199 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3200 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3201 } else {
3202 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3203 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3204 }
e07b1aa8 3205 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3206
3207 return 0;
3208}
3209
3210static void sky2_get_pauseparam(struct net_device *dev,
3211 struct ethtool_pauseparam *ecmd)
3212{
3213 struct sky2_port *sky2 = netdev_priv(dev);
3214
16ad91e1
SH		 3215 switch (sky2->flow_mode) {
3216 case FC_NONE:
3217 ecmd->tx_pause = ecmd->rx_pause = 0;
3218 break;
3219 case FC_TX:
3220 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3221 break;
3222 case FC_RX:
3223 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3224 break;
3225 case FC_BOTH:
3226 ecmd->tx_pause = ecmd->rx_pause = 1;
3227 }
3228
cd28ab6a
SH		 3229 ecmd->autoneg = sky2->autoneg;
3230}
3231
3232static int sky2_set_pauseparam(struct net_device *dev,
3233 struct ethtool_pauseparam *ecmd)
3234{
3235 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3236
3237 sky2->autoneg = ecmd->autoneg;
16ad91e1 3238 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3239
16ad91e1
SH		 3240 if (netif_running(dev))
3241 sky2_phy_reinit(sky2);
cd28ab6a 3242
2eaba1a2 3243 return 0;
cd28ab6a
SH		 3244}
3245
fb17358f
SH		 3246static int sky2_get_coalesce(struct net_device *dev,
3247 struct ethtool_coalesce *ecmd)
3248{
3249 struct sky2_port *sky2 = netdev_priv(dev);
3250 struct sky2_hw *hw = sky2->hw;
3251
3252 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3253 ecmd->tx_coalesce_usecs = 0;
3254 else {
3255 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3256 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3257 }
3258 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3259
3260 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3261 ecmd->rx_coalesce_usecs = 0;
3262 else {
3263 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3264 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3265 }
3266 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3267
3268 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3269 ecmd->rx_coalesce_usecs_irq = 0;
3270 else {
3271 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3272 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3273 }
3274
3275 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3276
3277 return 0;
3278}
3279
3280/* Note: this affect both ports */
3281static int sky2_set_coalesce(struct net_device *dev,
3282 struct ethtool_coalesce *ecmd)
3283{
3284 struct sky2_port *sky2 = netdev_priv(dev);
3285 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3286 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3287
77b3d6a2
SH		 3288 if (ecmd->tx_coalesce_usecs > tmax ||
3289 ecmd->rx_coalesce_usecs > tmax ||
3290 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3291 return -EINVAL;
3292
ff81fbbe 3293 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3294 return -EINVAL;
ff81fbbe 3295 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3296 return -EINVAL;
ff81fbbe 3297 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3298 return -EINVAL;
3299
3300 if (ecmd->tx_coalesce_usecs == 0)
3301 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3302 else {
3303 sky2_write32(hw, STAT_TX_TIMER_INI,
3304 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3305 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3306 }
3307 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3308
3309 if (ecmd->rx_coalesce_usecs == 0)
3310 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3311 else {
3312 sky2_write32(hw, STAT_LEV_TIMER_INI,
3313 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3314 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3315 }
3316 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3317
3318 if (ecmd->rx_coalesce_usecs_irq == 0)
3319 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3320 else {
d28d4870 3321 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3322 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3323 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3324 }
3325 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3326 return 0;
3327}
3328
793b883e
SH		 3329static void sky2_get_ringparam(struct net_device *dev,
3330 struct ethtool_ringparam *ering)
3331{
3332 struct sky2_port *sky2 = netdev_priv(dev);
3333
3334 ering->rx_max_pending = RX_MAX_PENDING;
3335 ering->rx_mini_max_pending = 0;
3336 ering->rx_jumbo_max_pending = 0;
3337 ering->tx_max_pending = TX_RING_SIZE - 1;
3338
3339 ering->rx_pending = sky2->rx_pending;
3340 ering->rx_mini_pending = 0;
3341 ering->rx_jumbo_pending = 0;
3342 ering->tx_pending = sky2->tx_pending;
3343}
3344
3345static int sky2_set_ringparam(struct net_device *dev,
3346 struct ethtool_ringparam *ering)
3347{
3348 struct sky2_port *sky2 = netdev_priv(dev);
3349 int err = 0;
3350
3351 if (ering->rx_pending > RX_MAX_PENDING ||
3352 ering->rx_pending < 8 ||
3353 ering->tx_pending < MAX_SKB_TX_LE ||
3354 ering->tx_pending > TX_RING_SIZE - 1)
3355 return -EINVAL;
3356
3357 if (netif_running(dev))
3358 sky2_down(dev);
3359
3360 sky2->rx_pending = ering->rx_pending;
3361 sky2->tx_pending = ering->tx_pending;
3362
1b537565 3363 if (netif_running(dev)) {
793b883e 3364 err = sky2_up(dev);
1b537565
SH		 3365 if (err)
3366 dev_close(dev);
6ed995bb
SH		 3367 else
3368 sky2_set_multicast(dev);
1b537565 3369 }
793b883e
SH		 3370
3371 return err;
3372}
3373
793b883e
SH		 3374static int sky2_get_regs_len(struct net_device *dev)
3375{
6e4cbb34 3376 return 0x4000;
793b883e
SH		 3377}
3378
3379/*
3380 * Returns copy of control register region
3ead5db7 3381 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3382 */
3383static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3384 void *p)
3385{
3386 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3387 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3388
3389 regs->version = 1;
6e4cbb34 3390 memset(p, 0, regs->len);
793b883e 3391
6e4cbb34
SH		 3392 memcpy_fromio(p, io, B3_RAM_ADDR);
3393
3ead5db7
SH		 3394 /* skip diagnostic ram region */
3395 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3396
3397 /* copy GMAC registers */
3398 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3399 if (sky2->hw->ports > 1)
3400 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3401
793b883e 3402}
cd28ab6a 3403
b628ed98
SH		 3404/* In order to do Jumbo packets on these chips, need to turn off the
3405 * transmit store/forward. Therefore checksum offload won't work.
3406 */
3407static int no_tx_offload(struct net_device *dev)
3408{
3409 const struct sky2_port *sky2 = netdev_priv(dev);
3410 const struct sky2_hw *hw = sky2->hw;
3411
69161611 3412 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3413}
3414
3415static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3416{
3417 if (data && no_tx_offload(dev))
3418 return -EINVAL;
3419
3420 return ethtool_op_set_tx_csum(dev, data);
3421}
3422
3423
3424static int sky2_set_tso(struct net_device *dev, u32 data)
3425{
3426 if (data && no_tx_offload(dev))
3427 return -EINVAL;
3428
3429 return ethtool_op_set_tso(dev, data);
3430}
3431
7282d491 3432static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3433 .get_settings = sky2_get_settings,
3434 .set_settings = sky2_set_settings,
e3173832
SH		 3435 .get_drvinfo = sky2_get_drvinfo,
3436 .get_wol = sky2_get_wol,
3437 .set_wol = sky2_set_wol,
793b883e
SH		 3438 .get_msglevel = sky2_get_msglevel,
3439 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3440 .nway_reset = sky2_nway_reset,
793b883e
SH		 3441 .get_regs_len = sky2_get_regs_len,
3442 .get_regs = sky2_get_regs,
3443 .get_link = ethtool_op_get_link,
3444 .get_sg = ethtool_op_get_sg,
3445 .set_sg = ethtool_op_set_sg,
3446 .get_tx_csum = ethtool_op_get_tx_csum,
b628ed98 3447 .set_tx_csum = sky2_set_tx_csum,
793b883e 3448 .get_tso = ethtool_op_get_tso,
b628ed98 3449 .set_tso = sky2_set_tso,
793b883e
SH		 3450 .get_rx_csum = sky2_get_rx_csum,
3451 .set_rx_csum = sky2_set_rx_csum,
3452 .get_strings = sky2_get_strings,
fb17358f
SH		 3453 .get_coalesce = sky2_get_coalesce,
3454 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3455 .get_ringparam = sky2_get_ringparam,
3456 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3457 .get_pauseparam = sky2_get_pauseparam,
3458 .set_pauseparam = sky2_set_pauseparam,
793b883e 3459 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3460 .get_stats_count = sky2_get_stats_count,
3461 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3462 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3463};
3464
3465/* Initialize network device */
3466static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3467 unsigned port,
3468 int highmem, int wol)
cd28ab6a
SH		 3469{
3470 struct sky2_port *sky2;
3471 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3472
3473 if (!dev) {
b02a9258 3474 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3475 return NULL;
3476 }
3477
3478 SET_MODULE_OWNER(dev);
3479 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3480 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3481 dev->open = sky2_up;
3482 dev->stop = sky2_down;
ef743d33 3483 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3484 dev->hard_start_xmit = sky2_xmit_frame;
3485 dev->get_stats = sky2_get_stats;
3486 dev->set_multicast_list = sky2_set_multicast;
3487 dev->set_mac_address = sky2_set_mac_address;
3488 dev->change_mtu = sky2_change_mtu;
3489 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3490 dev->tx_timeout = sky2_tx_timeout;
3491 dev->watchdog_timeo = TX_WATCHDOG;
3492 if (port == 0)
3493 dev->poll = sky2_poll;
3494 dev->weight = NAPI_WEIGHT;
3495#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3496 /* Network console (only works on port 0)
3497 * because netpoll makes assumptions about NAPI
3498 */
3499 if (port == 0)
3500 dev->poll_controller = sky2_netpoll;
cd28ab6a 3501#endif
cd28ab6a
SH		 3502
3503 sky2 = netdev_priv(dev);
3504 sky2->netdev = dev;
3505 sky2->hw = hw;
3506 sky2->msg_enable = netif_msg_init(debug, default_msg);
3507
cd28ab6a
SH		 3508 /* Auto speed and flow control */
3509 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3510 sky2->flow_mode = FC_BOTH;
3511
cd28ab6a
SH		 3512 sky2->duplex = -1;
3513 sky2->speed = -1;
3514 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3515 sky2->rx_csum = 1;
e3173832 3516 sky2->wol = wol;
75d070c5 3517
e07b1aa8 3518 spin_lock_init(&sky2->phy_lock);
793b883e 3519 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3520 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3521
3522 hw->dev[port] = dev;
3523
3524 sky2->port = port;
3525
4a50a876 3526 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3527 if (highmem)
3528 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3529
d1f13708 3530#ifdef SKY2_VLAN_TAG_USED
3531 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3532 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708 3533#endif
3534
cd28ab6a 3535 /* read the mac address */
793b883e 3536 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3537 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3538
3539 /* device is off until link detection */
3540 netif_carrier_off(dev);
3541 netif_stop_queue(dev);
3542
3543 return dev;
3544}
3545
28bd181a 3546static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3547{
3548 const struct sky2_port *sky2 = netdev_priv(dev);
3549
3550 if (netif_msg_probe(sky2))
3551 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3552 dev->name,
3553 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3554 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3555}
3556
fb2690a9 3557/* Handle software interrupt used during MSI test */
7d12e780 3558static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3559{
3560 struct sky2_hw *hw = dev_id;
3561 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3562
3563 if (status == 0)
3564 return IRQ_NONE;
3565
3566 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3567 hw->msi = 1;
fb2690a9
SH		 3568 wake_up(&hw->msi_wait);
3569 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3570 }
3571 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3572
3573 return IRQ_HANDLED;
3574}
3575
3576/* Test interrupt path by forcing a a software IRQ */
3577static int __devinit sky2_test_msi(struct sky2_hw *hw)
3578{
3579 struct pci_dev *pdev = hw->pdev;
3580 int err;
3581
bb507fe1 3582 init_waitqueue_head (&hw->msi_wait);
3583
fb2690a9
SH		 3584 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3585
b0a20ded 3586 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3587 if (err) {
b02a9258 3588 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3589 return err;
3590 }
3591
fb2690a9 3592 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3593 sky2_read8(hw, B0_CTST);
fb2690a9 3594
b0a20ded 3595 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3596
b0a20ded 3597 if (!hw->msi) {
fb2690a9 3598 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3599 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3600 "switching to INTx mode.\n");
fb2690a9
SH		 3601
3602 err = -EOPNOTSUPP;
3603 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3604 }
3605
3606 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3607 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3608
3609 free_irq(pdev->irq, hw);
3610
3611 return err;
3612}
3613
e3173832
SH		 3614static int __devinit pci_wake_enabled(struct pci_dev *dev)
3615{
3616 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3617 u16 value;
3618
3619 if (!pm)
3620 return 0;
3621 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3622 return 0;
3623 return value & PCI_PM_CTRL_PME_ENABLE;
3624}
3625
cd28ab6a
SH		 3626static int __devinit sky2_probe(struct pci_dev *pdev,
3627 const struct pci_device_id *ent)
3628{
7f60c64b 3629 struct net_device *dev;
cd28ab6a 3630 struct sky2_hw *hw;
e3173832 3631 int err, using_dac = 0, wol_default;
cd28ab6a 3632
793b883e
SH		 3633 err = pci_enable_device(pdev);
3634 if (err) {
b02a9258 3635 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3636 goto err_out;
3637 }
3638
793b883e
SH		 3639 err = pci_request_regions(pdev, DRV_NAME);
3640 if (err) {
b02a9258 3641 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3642 goto err_out_disable;
cd28ab6a
SH		 3643 }
3644
3645 pci_set_master(pdev);
3646
d1f3d4dd
SH		 3647 if (sizeof(dma_addr_t) > sizeof(u32) &&
3648 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3649 using_dac = 1;
3650 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3651 if (err < 0) {
b02a9258
SH		 3652 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3653 "for consistent allocations\n");
d1f3d4dd
SH		 3654 goto err_out_free_regions;
3655 }
d1f3d4dd 3656 } else {
cd28ab6a
SH		 3657 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3658 if (err) {
b02a9258 3659 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3660 goto err_out_free_regions;
3661 }
3662 }
d1f3d4dd 3663
e3173832
SH		 3664 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3665
cd28ab6a 3666 err = -ENOMEM;
6aad85d6 3667 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3668 if (!hw) {
b02a9258 3669 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3670 goto err_out_free_regions;
3671 }
3672
cd28ab6a 3673 hw->pdev = pdev;
cd28ab6a
SH		 3674
3675 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3676 if (!hw->regs) {
b02a9258 3677 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3678 goto err_out_free_hw;
3679 }
3680
56a645cc 3681#ifdef __BIG_ENDIAN
f65b138c
SH		 3682 /* The sk98lin vendor driver uses hardware byte swapping but
3683 * this driver uses software swapping.
3684 */
56a645cc
SH		 3685 {
3686 u32 reg;
56a645cc 3687 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3688 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3689 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3690 }
3691#endif
3692
08c06d8a
SH		 3693 /* ring for status responses */
3694 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3695 &hw->st_dma);
3696 if (!hw->st_le)
3697 goto err_out_iounmap;
3698
e3173832 3699 err = sky2_init(hw);
cd28ab6a 3700 if (err)
793b883e 3701 goto err_out_iounmap;
cd28ab6a 3702
b02a9258 3703 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3704 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3705 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3706 hw->chip_id, hw->chip_rev);
cd28ab6a 3707
e3173832
SH		 3708 sky2_reset(hw);
3709
3710 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3711 if (!dev) {
3712 err = -ENOMEM;
cd28ab6a 3713 goto err_out_free_pci;
7f60c64b 3714 }
cd28ab6a 3715
9fa1b1f3
SH		 3716 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3717 err = sky2_test_msi(hw);
3718 if (err == -EOPNOTSUPP)
3719 pci_disable_msi(pdev);
3720 else if (err)
3721 goto err_out_free_netdev;
3722 }
3723
793b883e
SH		 3724 err = register_netdev(dev);
3725 if (err) {
b02a9258 3726 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3727 goto err_out_free_netdev;
3728 }
3729
b0a20ded
SH		 3730 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3731 dev->name, hw);
9fa1b1f3 3732 if (err) {
b02a9258 3733 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3734 goto err_out_unregister;
3735 }
3736 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3737
cd28ab6a
SH		 3738 sky2_show_addr(dev);
3739
7f60c64b 3740 if (hw->ports > 1) {
3741 struct net_device *dev1;
3742
e3173832 3743 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3744 if (!dev1)
3745 dev_warn(&pdev->dev, "allocation for second device failed\n");
3746 else if ((err = register_netdev(dev1))) {
3747 dev_warn(&pdev->dev,
3748 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3749 hw->dev[1] = NULL;
3750 free_netdev(dev1);
b02a9258
SH		 3751 } else
3752 sky2_show_addr(dev1);
cd28ab6a
SH		 3753 }
3754
01bd7564 3755 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 3756 INIT_WORK(&hw->restart_work, sky2_restart);
3757
eb35cf60 3758 sky2_idle_start(hw);
d27ed387 3759
793b883e
SH		 3760 pci_set_drvdata(pdev, hw);
3761
cd28ab6a
SH		 3762 return 0;
3763
793b883e 3764err_out_unregister:
b0a20ded
SH		 3765 if (hw->msi)
3766 pci_disable_msi(pdev);
793b883e 3767 unregister_netdev(dev);
cd28ab6a
SH		 3768err_out_free_netdev:
3769 free_netdev(dev);
cd28ab6a 3770err_out_free_pci:
793b883e 3771 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3772 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3773err_out_iounmap:
3774 iounmap(hw->regs);
3775err_out_free_hw:
3776 kfree(hw);
3777err_out_free_regions:
3778 pci_release_regions(pdev);
44a1d2e5 3779err_out_disable:
cd28ab6a 3780 pci_disable_device(pdev);
cd28ab6a 3781err_out:
549a68c3 3782 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 3783 return err;
3784}
3785
3786static void __devexit sky2_remove(struct pci_dev *pdev)
3787{
793b883e 3788 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3789 struct net_device *dev0, *dev1;
3790
793b883e 3791 if (!hw)
cd28ab6a
SH		 3792 return;
3793
d27ed387
SH		 3794 del_timer_sync(&hw->idle_timer);
3795
81906791
SH		 3796 flush_scheduled_work();
3797
d27ed387 3798 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3799 synchronize_irq(hw->pdev->irq);
3800
cd28ab6a 3801 dev0 = hw->dev[0];
793b883e
SH		 3802 dev1 = hw->dev[1];
3803 if (dev1)
3804 unregister_netdev(dev1);
cd28ab6a
SH		 3805 unregister_netdev(dev0);
3806
ae306cca
SH		 3807 sky2_power_aux(hw);
3808
cd28ab6a 3809 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3810 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3811 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3812
3813 free_irq(pdev->irq, hw);
b0a20ded
SH		 3814 if (hw->msi)
3815 pci_disable_msi(pdev);
793b883e 3816 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3817 pci_release_regions(pdev);
3818 pci_disable_device(pdev);
793b883e 3819
cd28ab6a
SH		 3820 if (dev1)
3821 free_netdev(dev1);
3822 free_netdev(dev0);
3823 iounmap(hw->regs);
3824 kfree(hw);
5afa0a9c 3825
cd28ab6a
SH		 3826 pci_set_drvdata(pdev, NULL);
3827}
3828
3829#ifdef CONFIG_PM
3830static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3831{
793b883e 3832 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3833 int i, wol = 0;
cd28ab6a 3834
549a68c3
SH		 3835 if (!hw)
3836 return 0;
3837
eb35cf60 3838 del_timer_sync(&hw->idle_timer);
6a5706b9 3839 netif_poll_disable(hw->dev[0]);
eb35cf60 3840
f05267e7 3841 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3842 struct net_device *dev = hw->dev[i];
e3173832 3843 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3844
e3173832 3845 if (netif_running(dev))
5afa0a9c 3846 sky2_down(dev);
e3173832
SH		 3847
3848 if (sky2->wol)
3849 sky2_wol_init(sky2);
3850
3851 wol |= sky2->wol;
cd28ab6a
SH		 3852 }
3853
8ab8fca2 3854 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3855 sky2_power_aux(hw);
e3173832 3856
d374c1c1 3857 pci_save_state(pdev);
e3173832 3858 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3859 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3860
2ccc99b7 3861 return 0;
cd28ab6a
SH		 3862}
3863
3864static int sky2_resume(struct pci_dev *pdev)
3865{
793b883e 3866 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3867 int i, err;
cd28ab6a 3868
549a68c3
SH		 3869 if (!hw)
3870 return 0;
3871
ae306cca
SH		 3872 err = pci_set_power_state(pdev, PCI_D0);
3873 if (err)
3874 goto out;
3875
3876 err = pci_restore_state(pdev);
3877 if (err)
3878 goto out;
3879
cd28ab6a 3880 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 3881
3882 /* Re-enable all clocks */
3883 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3884 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3885
e3173832 3886 sky2_reset(hw);
cd28ab6a 3887
8ab8fca2
SH		 3888 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3889
f05267e7 3890 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3891 struct net_device *dev = hw->dev[i];
6a5706b9 3892 if (netif_running(dev)) {
08c06d8a
SH		 3893 err = sky2_up(dev);
3894 if (err) {
3895 printk(KERN_ERR PFX "%s: could not up: %d\n",
3896 dev->name, err);
3897 dev_close(dev);
eb35cf60 3898 goto out;
5afa0a9c 3899 }
cd28ab6a
SH		 3900 }
3901 }
eb35cf60 3902
6a5706b9 3903 netif_poll_enable(hw->dev[0]);
eb35cf60 3904 sky2_idle_start(hw);
ae306cca 3905 return 0;
08c06d8a 3906out:
b02a9258 3907 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3908 pci_disable_device(pdev);
08c06d8a 3909 return err;
cd28ab6a
SH		 3910}
3911#endif
3912
e3173832
SH		 3913static void sky2_shutdown(struct pci_dev *pdev)
3914{
3915 struct sky2_hw *hw = pci_get_drvdata(pdev);
3916 int i, wol = 0;
3917
549a68c3
SH		 3918 if (!hw)
3919 return;
3920
e3173832
SH		 3921 del_timer_sync(&hw->idle_timer);
3922 netif_poll_disable(hw->dev[0]);
3923
3924 for (i = 0; i < hw->ports; i++) {
3925 struct net_device *dev = hw->dev[i];
3926 struct sky2_port *sky2 = netdev_priv(dev);
3927
3928 if (sky2->wol) {
3929 wol = 1;
3930 sky2_wol_init(sky2);
3931 }
3932 }
3933
3934 if (wol)
3935 sky2_power_aux(hw);
3936
3937 pci_enable_wake(pdev, PCI_D3hot, wol);
3938 pci_enable_wake(pdev, PCI_D3cold, wol);
3939
3940 pci_disable_device(pdev);
3941 pci_set_power_state(pdev, PCI_D3hot);
3942
3943}
3944
cd28ab6a 3945static struct pci_driver sky2_driver = {
793b883e
SH		 3946 .name = DRV_NAME,
3947 .id_table = sky2_id_table,
3948 .probe = sky2_probe,
3949 .remove = __devexit_p(sky2_remove),
cd28ab6a 3950#ifdef CONFIG_PM
793b883e
SH		 3951 .suspend = sky2_suspend,
3952 .resume = sky2_resume,
cd28ab6a 3953#endif
e3173832 3954 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3955};
3956
3957static int __init sky2_init_module(void)
3958{
50241c4c 3959 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3960}
3961
3962static void __exit sky2_cleanup_module(void)
3963{
3964 pci_unregister_driver(&sky2_driver);
3965}
3966
3967module_init(sky2_init_module);
3968module_exit(sky2_cleanup_module);
3969
3970MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3971MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3972MODULE_LICENSE("GPL");
5f4f9dc1 3973MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)