projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[NET]: Fix NAPI completion handling in some drivers.
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
555382cb 34#include <linux/aer.h>
cd28ab6a 35#include <linux/ip.h>
c9bdd4b5 36#include <net/ip.h>
cd28ab6a
SH		 37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
3cf26753 43#include <linux/debugfs.h>
ef743d33 44#include <linux/mii.h>
cd28ab6a
SH		 45
46#include <asm/irq.h>
47
d1f13708 48#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49#define SKY2_VLAN_TAG_USED 1
50#endif
51
cd28ab6a
SH		 52#include "sky2.h"
53
54#define DRV_NAME "sky2"
faf60e72 55#define DRV_VERSION "1.18"
cd28ab6a
SH		 56#define PFX DRV_NAME " "
57
58/*
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
14d0263f 61 * similar to Tigon3.
cd28ab6a
SH		 62 */
63
14d0263f 64#define RX_LE_SIZE 1024
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 66#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 68#define RX_SKB_ALIGN 8
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 77#define TX_WATCHDOG (5 * HZ)
78#define NAPI_WEIGHT 64
79#define PHY_RETRIES 1000
80
f4331a6d
SH		 81#define SKY2_EEPROM_MAGIC 0x9955aabb
82
83
cb5d9547
SH		 84#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85
cd28ab6a 86static const u32 default_msg =
793b883e
SH		 87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 90
793b883e 91static int debug = -1; /* defaults above */
cd28ab6a
SH		 92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
14d0263f 95static int copybreak __read_mostly = 128;
bdb5c58e
SH		 96module_param(copybreak, int, 0);
97MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98
fb2690a9
SH		 99static int disable_msi = 0;
100module_param(disable_msi, int, 0);
101MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
05745c4a 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 137 { 0 }
138};
793b883e 139
cd28ab6a
SH		 140MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142/* Avoid conditionals by using array */
143static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 145static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 146
92f965e8
SH		 147/* This driver supports yukon2 chipset only */
148static const char *yukon2_name[] = {
149 "XL", /* 0xb3 */
150 "EC Ultra", /* 0xb4 */
93745494 151 "Extreme", /* 0xb5 */
92f965e8
SH		 152 "EC", /* 0xb6 */
153 "FE", /* 0xb7 */
05745c4a 154 "FE+", /* 0xb8 */
793b883e
SH		 155};
156
d1b139c0
SH		 157static void sky2_set_multicast(struct net_device *dev);
158
793b883e 159/* Access to external PHY */
ef743d33 160static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 161{
162 int i;
163
164 gma_write16(hw, port, GM_SMI_DATA, val);
165 gma_write16(hw, port, GM_SMI_CTRL,
166 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
167
168 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 169 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 170 return 0;
793b883e 171 udelay(1);
cd28ab6a 172 }
ef743d33 173
793b883e 174 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 175 return -ETIMEDOUT;
cd28ab6a
SH		 176}
177
ef743d33 178static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 179{
180 int i;
181
793b883e 182 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 183 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
184
185 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 186 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
187 *val = gma_read16(hw, port, GM_SMI_DATA);
188 return 0;
189 }
190
793b883e 191 udelay(1);
cd28ab6a
SH		 192 }
193
ef743d33 194 return -ETIMEDOUT;
195}
196
197static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
198{
199 u16 v;
200
201 if (__gm_phy_read(hw, port, reg, &v) != 0)
202 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
203 return v;
cd28ab6a
SH		 204}
205
5afa0a9c 206
ae306cca
SH		 207static void sky2_power_on(struct sky2_hw *hw)
208{
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 212
ae306cca
SH		 213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 215
ae306cca
SH		 216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 else
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 224
ea76e635 225 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
167f53d0 226 struct pci_dev *pdev = hw->pdev;
fc99fe06 227 u32 reg;
5afa0a9c 228
167f53d0 229 pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
b2345773 230
167f53d0 231 pci_read_config_dword(pdev, PCI_DEV_REG4, &reg);
fc99fe06
SH		 232 /* set all bits to 0 except bits 15..12 and 8 */
233 reg &= P_ASPM_CONTROL_MSK;
167f53d0 234 pci_write_config_dword(pdev, PCI_DEV_REG4, reg);
fc99fe06 235
167f53d0 236 pci_read_config_dword(pdev, PCI_DEV_REG5, &reg);
fc99fe06
SH		 237 /* set all bits to 0 except bits 28 & 27 */
238 reg &= P_CTL_TIM_VMAIN_AV_MSK;
167f53d0 239 pci_write_config_dword(pdev, PCI_DEV_REG5, reg);
fc99fe06 240
167f53d0 241 pci_write_config_dword(pdev, PCI_CFG_REG_1, 0);
8f70920f
SH		 242
243 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
244 reg = sky2_read32(hw, B2_GP_IO);
245 reg |= GLB_GPIO_STAT_RACE_DIS;
246 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 247
248 sky2_read32(hw, B2_GP_IO);
5afa0a9c 249 }
ae306cca 250}
5afa0a9c 251
ae306cca
SH		 252static void sky2_power_aux(struct sky2_hw *hw)
253{
254 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
255 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
256 else
257 /* enable bits are inverted */
258 sky2_write8(hw, B2_Y2_CLK_GATE,
259 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
260 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
261 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
262
263 /* switch power to VAUX */
264 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
265 sky2_write8(hw, B0_POWER_CTRL,
266 (PC_VAUX_ENA | PC_VCC_ENA |
267 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 268}
269
d3bcfbeb 270static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 271{
272 u16 reg;
273
274 /* disable all GMAC IRQ's */
275 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
276 /* disable PHY IRQs */
277 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 278
cd28ab6a
SH		 279 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
280 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
281 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
282 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
283
284 reg = gma_read16(hw, port, GM_RX_CTRL);
285 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
286 gma_write16(hw, port, GM_RX_CTRL, reg);
287}
288
16ad91e1
SH		 289/* flow control to advertise bits */
290static const u16 copper_fc_adv[] = {
291 [FC_NONE] = 0,
292 [FC_TX] = PHY_M_AN_ASP,
293 [FC_RX] = PHY_M_AN_PC,
294 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
295};
296
297/* flow control to advertise bits when using 1000BaseX */
298static const u16 fiber_fc_adv[] = {
299 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
300 [FC_TX] = PHY_M_P_ASYM_MD_X,
301 [FC_RX] = PHY_M_P_SYM_MD_X,
302 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
303};
304
305/* flow control to GMA disable bits */
306static const u16 gm_fc_disable[] = {
307 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
308 [FC_TX] = GM_GPCR_FC_RX_DIS,
309 [FC_RX] = GM_GPCR_FC_TX_DIS,
310 [FC_BOTH] = 0,
311};
312
313
cd28ab6a
SH		 314static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
315{
316 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 317 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 318
ea76e635
SH		 319 if (sky2->autoneg == AUTONEG_ENABLE &&
320 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 321 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
322
323 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 324 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 325 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
326
53419c68 327 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 328 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 329 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 330 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
331 else
53419c68
SH		 332 /* set master & slave downshift counter to 1x */
333 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 334
335 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
336 }
337
338 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 339 if (sky2_is_copper(hw)) {
05745c4a 340 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 343
344 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
345 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
346 u16 spec;
347
348 /* Enable Class A driver for FE+ A0 */
349 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
350 spec |= PHY_M_FESC_SEL_CL_A;
351 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
352 }
cd28ab6a
SH		 353 } else {
354 /* disable energy detect */
355 ctrl &= ~PHY_M_PC_EN_DET_MSK;
356
357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
359
53419c68 360 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 361 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 362 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 363 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 364 ctrl &= ~PHY_M_PC_DSC_MSK;
365 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
366 }
367 }
cd28ab6a
SH		 368 } else {
369 /* workaround for deviation #4.88 (CRC errors) */
370 /* disable Automatic Crossover */
371
372 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 373 }
cd28ab6a 374
b89165f2
SH		 375 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
376
377 /* special setup for PHY 88E1112 Fiber */
ea76e635 378 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 379 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 380
b89165f2
SH		 381 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
382 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
383 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
384 ctrl &= ~PHY_M_MAC_MD_MSK;
385 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
386 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
387
388 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 389 /* select page 1 to access Fiber registers */
390 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 391
392 /* for SFP-module set SIGDET polarity to low */
393 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
394 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 395 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 396 }
b89165f2
SH		 397
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 399 }
400
7800fddc 401 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 402 ct1000 = 0;
403 adv = PHY_AN_CSMA;
2eaba1a2 404 reg = 0;
cd28ab6a
SH		 405
406 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 407 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 408 if (sky2->advertising & ADVERTISED_1000baseT_Full)
409 ct1000 |= PHY_M_1000C_AFD;
410 if (sky2->advertising & ADVERTISED_1000baseT_Half)
411 ct1000 |= PHY_M_1000C_AHD;
412 if (sky2->advertising & ADVERTISED_100baseT_Full)
413 adv |= PHY_M_AN_100_FD;
414 if (sky2->advertising & ADVERTISED_100baseT_Half)
415 adv |= PHY_M_AN_100_HD;
416 if (sky2->advertising & ADVERTISED_10baseT_Full)
417 adv |= PHY_M_AN_10_FD;
418 if (sky2->advertising & ADVERTISED_10baseT_Half)
419 adv |= PHY_M_AN_10_HD;
709c6e7b 420
16ad91e1 421 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 422 } else { /* special defines for FIBER (88E1040S only) */
423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 adv |= PHY_M_AN_1000X_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 427
16ad91e1 428 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 429 }
cd28ab6a
SH		 430
431 /* Restart Auto-negotiation */
432 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
433 } else {
434 /* forced speed/duplex settings */
435 ct1000 = PHY_M_1000C_MSE;
436
2eaba1a2
SH		 437 /* Disable auto update for duplex flow control and speed */
438 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 439
440 switch (sky2->speed) {
441 case SPEED_1000:
442 ctrl |= PHY_CT_SP1000;
2eaba1a2 443 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 444 break;
445 case SPEED_100:
446 ctrl |= PHY_CT_SP100;
2eaba1a2 447 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 448 break;
449 }
450
2eaba1a2
SH		 451 if (sky2->duplex == DUPLEX_FULL) {
452 reg |= GM_GPCR_DUP_FULL;
453 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 454 } else if (sky2->speed < SPEED_1000)
455 sky2->flow_mode = FC_NONE;
2eaba1a2 456
2eaba1a2 457
16ad91e1 458 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 459
460 /* Forward pause packets to GMAC? */
16ad91e1 461 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 462 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
463 else
464 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 465 }
466
2eaba1a2
SH		 467 gma_write16(hw, port, GM_GP_CTRL, reg);
468
05745c4a 469 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 470 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
471
472 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
473 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
474
475 /* Setup Phy LED's */
476 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
477 ledover = 0;
478
479 switch (hw->chip_id) {
480 case CHIP_ID_YUKON_FE:
481 /* on 88E3082 these bits are at 11..9 (shifted left) */
482 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
483
484 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
485
486 /* delete ACT LED control bits */
487 ctrl &= ~PHY_M_FELP_LED1_MSK;
488 /* change ACT LED control to blink mode */
489 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
490 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
491 break;
492
05745c4a
SH		 493 case CHIP_ID_YUKON_FE_P:
494 /* Enable Link Partner Next Page */
495 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
496 ctrl |= PHY_M_PC_ENA_LIP_NP;
497
498 /* disable Energy Detect and enable scrambler */
499 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
500 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
501
502 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
503 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
504 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
505 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
506
507 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
508 break;
509
cd28ab6a 510 case CHIP_ID_YUKON_XL:
793b883e 511 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 512
513 /* select page 3 to access LED control register */
514 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
515
516 /* set LED Function Control register */
ed6d32c7
SH		 517 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
518 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
519 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
520 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
521 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 522
523 /* set Polarity Control register */
524 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 525 (PHY_M_POLC_LS1_P_MIX(4) |
526 PHY_M_POLC_IS0_P_MIX(4) |
527 PHY_M_POLC_LOS_CTRL(2) |
528 PHY_M_POLC_INIT_CTRL(2) |
529 PHY_M_POLC_STA1_CTRL(2) |
530 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 531
532 /* restore page register */
793b883e 533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 534 break;
93745494 535
ed6d32c7 536 case CHIP_ID_YUKON_EC_U:
93745494 537 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 538 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
539
540 /* select page 3 to access LED control register */
541 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
542
543 /* set LED Function Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
545 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
546 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
547 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
548 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
549
550 /* set Blink Rate in LED Timer Control Register */
551 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
552 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
553 /* restore page register */
554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
555 break;
cd28ab6a
SH		 556
557 default:
558 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
559 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
560 /* turn off the Rx LED (LED_RX) */
0efdf262 561 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 562 }
563
9467a8fc
SH		 564 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
565 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 566 /* apply fixes in PHY AFE */
ed6d32c7
SH		 567 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
568
977bdf06 569 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 570 gm_phy_write(hw, port, 0x18, 0xaa99);
571 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 572
977bdf06 573 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 574 gm_phy_write(hw, port, 0x18, 0xa204);
575 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 576
577 /* set page register to 0 */
9467a8fc 578 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 579 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
580 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
581 /* apply workaround for integrated resistors calibration */
582 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
583 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 584 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 585 /* no effect on Yukon-XL */
977bdf06 586 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 587
977bdf06
SH		 588 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
589 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 590 ledover |= PHY_M_LED_MO_100;
977bdf06 591 }
cd28ab6a 592
977bdf06
SH		 593 if (ledover)
594 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
595
596 }
2eaba1a2 597
d571b694 598 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 599 if (sky2->autoneg == AUTONEG_ENABLE)
600 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
601 else
602 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
603}
604
d3bcfbeb 605static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
606{
167f53d0 607 struct pci_dev *pdev = hw->pdev;
d3bcfbeb 608 u32 reg1;
609 static const u32 phy_power[]
610 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
611
612 /* looks like this XL is back asswards .. */
613 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
614 onoff = !onoff;
615
167f53d0 616 pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);
d3bcfbeb 617 if (onoff)
618 /* Turn off phy power saving */
619 reg1 &= ~phy_power[port];
620 else
621 reg1 |= phy_power[port];
622
167f53d0
SH		 623 pci_write_config_dword(pdev, PCI_DEV_REG1, reg1);
624 pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);
625
d3bcfbeb 626 udelay(100);
627}
628
1b537565
SH		 629/* Force a renegotiation */
630static void sky2_phy_reinit(struct sky2_port *sky2)
631{
e07b1aa8 632 spin_lock_bh(&sky2->phy_lock);
1b537565 633 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 634 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 635}
636
e3173832
SH		 637/* Put device in state to listen for Wake On Lan */
638static void sky2_wol_init(struct sky2_port *sky2)
639{
640 struct sky2_hw *hw = sky2->hw;
641 unsigned port = sky2->port;
642 enum flow_control save_mode;
643 u16 ctrl;
644 u32 reg1;
645
646 /* Bring hardware out of reset */
647 sky2_write16(hw, B0_CTST, CS_RST_CLR);
648 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
649
650 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
651 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
652
653 /* Force to 10/100
654 * sky2_reset will re-enable on resume
655 */
656 save_mode = sky2->flow_mode;
657 ctrl = sky2->advertising;
658
659 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
660 sky2->flow_mode = FC_NONE;
661 sky2_phy_power(hw, port, 1);
662 sky2_phy_reinit(sky2);
663
664 sky2->flow_mode = save_mode;
665 sky2->advertising = ctrl;
666
667 /* Set GMAC to no flow control and auto update for speed/duplex */
668 gma_write16(hw, port, GM_GP_CTRL,
669 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
670 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
671
672 /* Set WOL address */
673 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
674 sky2->netdev->dev_addr, ETH_ALEN);
675
676 /* Turn on appropriate WOL control bits */
677 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
678 ctrl = 0;
679 if (sky2->wol & WAKE_PHY)
680 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
681 else
682 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
683
684 if (sky2->wol & WAKE_MAGIC)
685 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
686 else
687 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
688
689 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
690 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
691
692 /* Turn on legacy PCI-Express PME mode */
167f53d0 693 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
e3173832 694 reg1 |= PCI_Y2_PME_LEGACY;
167f53d0 695 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
e3173832
SH		 696
697 /* block receiver */
698 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
699
700}
701
69161611
SH		 702static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
703{
05745c4a
SH		 704 struct net_device *dev = hw->dev[port];
705
706 if (dev->mtu <= ETH_DATA_LEN)
69161611 707 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
05745c4a
SH		 708 TX_JUMBO_DIS | TX_STFW_ENA);
709
710 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
711 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
712 TX_STFW_ENA | TX_JUMBO_ENA);
713 else {
714 /* set Tx GMAC FIFO Almost Empty Threshold */
715 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
716 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 717
05745c4a
SH		 718 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
719 TX_JUMBO_ENA | TX_STFW_DIS);
69161611 720
05745c4a
SH		 721 /* Can't do offload because of lack of store/forward */
722 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
69161611
SH		 723 }
724}
725
cd28ab6a
SH		 726static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
727{
728 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
729 u16 reg;
25cccecc 730 u32 rx_reg;
cd28ab6a
SH		 731 int i;
732 const u8 *addr = hw->dev[port]->dev_addr;
733
f350339c
SH		 734 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
735 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 736
737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
738
793b883e 739 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 740 /* WA DEV_472 -- looks like crossed wires on port 2 */
741 /* clear GMAC 1 Control reset */
742 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
743 do {
744 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
745 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
746 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
747 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
748 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
749 }
750
793b883e 751 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 752
2eaba1a2
SH		 753 /* Enable Transmit FIFO Underrun */
754 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
755
e07b1aa8 756 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 757 sky2_phy_init(hw, port);
e07b1aa8 758 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 759
760 /* MIB clear */
761 reg = gma_read16(hw, port, GM_PHY_ADDR);
762 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
763
43f2f104
SH		 764 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
765 gma_read16(hw, port, i);
cd28ab6a
SH		 766 gma_write16(hw, port, GM_PHY_ADDR, reg);
767
768 /* transmit control */
769 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
770
771 /* receive control reg: unicast + multicast + no FCS */
772 gma_write16(hw, port, GM_RX_CTRL,
793b883e 773 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 774
775 /* transmit flow control */
776 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
777
778 /* transmit parameter */
779 gma_write16(hw, port, GM_TX_PARAM,
780 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
781 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
782 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
783 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
784
785 /* serial mode register */
786 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 787 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 788
6b1a3aef 789 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 790 reg |= GM_SMOD_JUMBO_ENA;
791
792 gma_write16(hw, port, GM_SERIAL_MODE, reg);
793
cd28ab6a
SH		 794 /* virtual address for data */
795 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
796
793b883e
SH		 797 /* physical address: used for pause frames */
798 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
799
800 /* ignore counter overflows */
cd28ab6a
SH		 801 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
802 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
803 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
804
805 /* Configure Rx MAC FIFO */
806 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 807 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 808 if (hw->chip_id == CHIP_ID_YUKON_EX ||
809 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 810 rx_reg |= GMF_RX_OVER_ON;
69161611 811
25cccecc 812 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 813
d571b694 814 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 815 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 816
8df9a876 817 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 818 reg = RX_GMF_FL_THR_DEF + 1;
819 /* Another magic mystery workaround from sk98lin */
820 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
821 hw->chip_rev == CHIP_REV_YU_FE2_A0)
822 reg = 0x178;
823 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 824
825 /* Configure Tx MAC FIFO */
826 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
827 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 828
e0c28116
SH		 829 /* On chips without ram buffer, pause is controled by MAC level */
830 if (sky2_read8(hw, B2_E_0) == 0) {
8df9a876 831 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 832 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 833
69161611 834 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 835 }
836
cd28ab6a
SH		 837}
838
67712901
SH		 839/* Assign Ram Buffer allocation to queue */
840static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 841{
67712901
SH		 842 u32 end;
843
844 /* convert from K bytes to qwords used for hw register */
845 start *= 1024/8;
846 space *= 1024/8;
847 end = start + space - 1;
793b883e 848
cd28ab6a
SH		 849 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
850 sky2_write32(hw, RB_ADDR(q, RB_START), start);
851 sky2_write32(hw, RB_ADDR(q, RB_END), end);
852 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
853 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
854
855 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 856 u32 tp = space - space/4;
793b883e 857
1c28f6ba
SH		 858 /* On receive queue's set the thresholds
859 * give receiver priority when > 3/4 full
860 * send pause when down to 2K
861 */
862 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
863 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 864
1c28f6ba
SH		 865 tp = space - 2048/8;
866 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
867 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 868 } else {
869 /* Enable store & forward on Tx queue's because
870 * Tx FIFO is only 1K on Yukon
871 */
872 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
873 }
874
875 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 876 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 877}
878
cd28ab6a 879/* Setup Bus Memory Interface */
af4ed7e6 880static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 881{
882 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
883 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
884 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 885 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 886}
887
cd28ab6a
SH		 888/* Setup prefetch unit registers. This is the interface between
889 * hardware and driver list elements
890 */
8cc048e3 891static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 892 u64 addr, u32 last)
893{
cd28ab6a
SH		 894 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
895 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
896 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
897 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
898 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
899 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 900
901 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 902}
903
793b883e
SH		 904static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
905{
906 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
907
cb5d9547 908 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 909 le->ctrl = 0;
793b883e
SH		 910 return le;
911}
cd28ab6a 912
88f5f0ca
SH		 913static void tx_init(struct sky2_port *sky2)
914{
915 struct sky2_tx_le *le;
916
917 sky2->tx_prod = sky2->tx_cons = 0;
918 sky2->tx_tcpsum = 0;
919 sky2->tx_last_mss = 0;
920
921 le = get_tx_le(sky2);
922 le->addr = 0;
923 le->opcode = OP_ADDR64 | HW_OWNER;
924 sky2->tx_addr64 = 0;
925}
926
291ea614
SH		 927static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
928 struct sky2_tx_le *le)
929{
930 return sky2->tx_ring + (le - sky2->tx_le);
931}
932
290d4de5
SH		 933/* Update chip's next pointer */
934static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 935{
50432cb5 936 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 937 wmb();
50432cb5
SH		 938 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
939
940 /* Synchronize I/O on since next processor may write to tail */
941 mmiowb();
cd28ab6a
SH		 942}
943
793b883e 944
cd28ab6a
SH		 945static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
946{
947 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 948 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 949 le->ctrl = 0;
cd28ab6a
SH		 950 return le;
951}
952
14d0263f
SH		 953/* Build description to hardware for one receive segment */
954static void sky2_rx_add(struct sky2_port *sky2, u8 op,
955 dma_addr_t map, unsigned len)
cd28ab6a
SH		 956{
957 struct sky2_rx_le *le;
36eb0c71 958 u32 hi = upper_32_bits(map);
cd28ab6a 959
793b883e 960 if (sky2->rx_addr64 != hi) {
cd28ab6a 961 le = sky2_next_rx(sky2);
793b883e 962 le->addr = cpu_to_le32(hi);
cd28ab6a 963 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 964 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 965 }
793b883e 966
cd28ab6a 967 le = sky2_next_rx(sky2);
734d1868
SH		 968 le->addr = cpu_to_le32((u32) map);
969 le->length = cpu_to_le16(len);
14d0263f 970 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 971}
972
14d0263f
SH		 973/* Build description to hardware for one possibly fragmented skb */
974static void sky2_rx_submit(struct sky2_port *sky2,
975 const struct rx_ring_info *re)
976{
977 int i;
978
979 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
980
981 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
982 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
983}
984
985
986static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
987 unsigned size)
988{
989 struct sk_buff *skb = re->skb;
990 int i;
991
992 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
993 pci_unmap_len_set(re, data_size, size);
994
995 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
996 re->frag_addr[i] = pci_map_page(pdev,
997 skb_shinfo(skb)->frags[i].page,
998 skb_shinfo(skb)->frags[i].page_offset,
999 skb_shinfo(skb)->frags[i].size,
1000 PCI_DMA_FROMDEVICE);
1001}
1002
1003static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1004{
1005 struct sk_buff *skb = re->skb;
1006 int i;
1007
1008 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1009 PCI_DMA_FROMDEVICE);
1010
1011 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1012 pci_unmap_page(pdev, re->frag_addr[i],
1013 skb_shinfo(skb)->frags[i].size,
1014 PCI_DMA_FROMDEVICE);
1015}
793b883e 1016
cd28ab6a
SH		 1017/* Tell chip where to start receive checksum.
1018 * Actually has two checksums, but set both same to avoid possible byte
1019 * order problems.
1020 */
793b883e 1021static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1022{
ea76e635 1023 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1024
ea76e635
SH		 1025 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1026 le->ctrl = 0;
1027 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1028
ea76e635
SH		 1029 sky2_write32(sky2->hw,
1030 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1031 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1032}
1033
6b1a3aef 1034/*
1035 * The RX Stop command will not work for Yukon-2 if the BMU does not
1036 * reach the end of packet and since we can't make sure that we have
1037 * incoming data, we must reset the BMU while it is not doing a DMA
1038 * transfer. Since it is possible that the RX path is still active,
1039 * the RX RAM buffer will be stopped first, so any possible incoming
1040 * data will not trigger a DMA. After the RAM buffer is stopped, the
1041 * BMU is polled until any DMA in progress is ended and only then it
1042 * will be reset.
1043 */
1044static void sky2_rx_stop(struct sky2_port *sky2)
1045{
1046 struct sky2_hw *hw = sky2->hw;
1047 unsigned rxq = rxqaddr[sky2->port];
1048 int i;
1049
1050 /* disable the RAM Buffer receive queue */
1051 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1052
1053 for (i = 0; i < 0xffff; i++)
1054 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1055 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1056 goto stopped;
1057
1058 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1059 sky2->netdev->name);
1060stopped:
1061 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1062
1063 /* reset the Rx prefetch unit */
1064 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1065 mmiowb();
6b1a3aef 1066}
793b883e 1067
d571b694 1068/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1069static void sky2_rx_clean(struct sky2_port *sky2)
1070{
1071 unsigned i;
1072
1073 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1074 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1075 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1076
1077 if (re->skb) {
14d0263f 1078 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1079 kfree_skb(re->skb);
1080 re->skb = NULL;
1081 }
1082 }
1083}
1084
ef743d33 1085/* Basic MII support */
1086static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1087{
1088 struct mii_ioctl_data *data = if_mii(ifr);
1089 struct sky2_port *sky2 = netdev_priv(dev);
1090 struct sky2_hw *hw = sky2->hw;
1091 int err = -EOPNOTSUPP;
1092
1093 if (!netif_running(dev))
1094 return -ENODEV; /* Phy still in reset */
1095
d89e1343 1096 switch (cmd) {
ef743d33 1097 case SIOCGMIIPHY:
1098 data->phy_id = PHY_ADDR_MARV;
1099
1100 /* fallthru */
1101 case SIOCGMIIREG: {
1102 u16 val = 0;
91c86df5 1103
e07b1aa8 1104 spin_lock_bh(&sky2->phy_lock);
ef743d33 1105 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1106 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1107
ef743d33 1108 data->val_out = val;
1109 break;
1110 }
1111
1112 case SIOCSMIIREG:
1113 if (!capable(CAP_NET_ADMIN))
1114 return -EPERM;
1115
e07b1aa8 1116 spin_lock_bh(&sky2->phy_lock);
ef743d33 1117 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1118 data->val_in);
e07b1aa8 1119 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1120 break;
1121 }
1122 return err;
1123}
1124
d1f13708 1125#ifdef SKY2_VLAN_TAG_USED
1126static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1127{
1128 struct sky2_port *sky2 = netdev_priv(dev);
1129 struct sky2_hw *hw = sky2->hw;
1130 u16 port = sky2->port;
d1f13708 1131
2bb8c262 1132 netif_tx_lock_bh(dev);
bea3348e 1133 napi_disable(&hw->napi);
d1f13708 1134
d1f13708 1135 sky2->vlgrp = grp;
3d4e66f5
SH		 1136 if (grp) {
1137 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1138 RX_VLAN_STRIP_ON);
1139 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1140 TX_VLAN_TAG_ON);
1141 } else {
1142 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1143 RX_VLAN_STRIP_OFF);
1144 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1145 TX_VLAN_TAG_OFF);
1146 }
d1f13708 1147
bea3348e 1148 napi_enable(&hw->napi);
2bb8c262 1149 netif_tx_unlock_bh(dev);
d1f13708 1150}
1151#endif
1152
82788c7a 1153/*
14d0263f
SH		 1154 * Allocate an skb for receiving. If the MTU is large enough
1155 * make the skb non-linear with a fragment list of pages.
1156 *
82788c7a
SH		 1157 * It appears the hardware has a bug in the FIFO logic that
1158 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1159 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1160 * aligned except if slab debugging is enabled.
82788c7a 1161 */
14d0263f 1162static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1163{
1164 struct sk_buff *skb;
14d0263f
SH		 1165 unsigned long p;
1166 int i;
82788c7a 1167
14d0263f
SH		 1168 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1169 if (!skb)
1170 goto nomem;
1171
1172 p = (unsigned long) skb->data;
1173 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1174
1175 for (i = 0; i < sky2->rx_nfrags; i++) {
1176 struct page *page = alloc_page(GFP_ATOMIC);
1177
1178 if (!page)
1179 goto free_partial;
1180 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1181 }
1182
1183 return skb;
14d0263f
SH		 1184free_partial:
1185 kfree_skb(skb);
1186nomem:
1187 return NULL;
82788c7a
SH		 1188}
1189
55c9dd35
SH		 1190static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1191{
1192 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1193}
1194
cd28ab6a
SH		 1195/*
1196 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1197 * Normal case this ends up creating one list element for skb
1198 * in the receive ring. Worst case if using large MTU and each
1199 * allocation falls on a different 64 bit region, that results
1200 * in 6 list elements per ring entry.
1201 * One element is used for checksum enable/disable, and one
1202 * extra to avoid wrap.
cd28ab6a 1203 */
6b1a3aef 1204static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1205{
6b1a3aef 1206 struct sky2_hw *hw = sky2->hw;
14d0263f 1207 struct rx_ring_info *re;
6b1a3aef 1208 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1209 unsigned i, size, space, thresh;
cd28ab6a 1210
6b1a3aef 1211 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1212 sky2_qset(hw, rxq);
977bdf06 1213
c3905bc4
SH		 1214 /* On PCI express lowering the watermark gives better performance */
1215 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1216 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1217
1218 /* These chips have no ram buffer?
1219 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1220 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1221 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1222 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1223 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1224
6b1a3aef 1225 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1226
ea76e635
SH		 1227 if (!(hw->flags & SKY2_HW_NEW_LE))
1228 rx_set_checksum(sky2);
14d0263f
SH		 1229
1230 /* Space needed for frame data + headers rounded up */
f957da2a 1231 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1232
1233 /* Stopping point for hardware truncation */
1234 thresh = (size - 8) / sizeof(u32);
1235
1236 /* Account for overhead of skb - to avoid order > 0 allocation */
1237 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1238 + sizeof(struct skb_shared_info);
1239
1240 sky2->rx_nfrags = space >> PAGE_SHIFT;
1241 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1242
1243 if (sky2->rx_nfrags != 0) {
1244 /* Compute residue after pages */
1245 space = sky2->rx_nfrags << PAGE_SHIFT;
1246
1247 if (space < size)
1248 size -= space;
1249 else
1250 size = 0;
1251
1252 /* Optimize to handle small packets and headers */
1253 if (size < copybreak)
1254 size = copybreak;
1255 if (size < ETH_HLEN)
1256 size = ETH_HLEN;
1257 }
1258 sky2->rx_data_size = size;
1259
1260 /* Fill Rx ring */
793b883e 1261 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1262 re = sky2->rx_ring + i;
cd28ab6a 1263
14d0263f 1264 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1265 if (!re->skb)
1266 goto nomem;
1267
14d0263f
SH		 1268 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1269 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1270 }
1271
a1433ac4
SH		 1272 /*
1273 * The receiver hangs if it receives frames larger than the
1274 * packet buffer. As a workaround, truncate oversize frames, but
1275 * the register is limited to 9 bits, so if you do frames > 2052
1276 * you better get the MTU right!
1277 */
a1433ac4
SH		 1278 if (thresh > 0x1ff)
1279 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1280 else {
1281 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1282 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1283 }
1284
6b1a3aef 1285 /* Tell chip about available buffers */
55c9dd35 1286 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1287 return 0;
1288nomem:
1289 sky2_rx_clean(sky2);
1290 return -ENOMEM;
1291}
1292
1293/* Bring up network interface. */
1294static int sky2_up(struct net_device *dev)
1295{
1296 struct sky2_port *sky2 = netdev_priv(dev);
1297 struct sky2_hw *hw = sky2->hw;
1298 unsigned port = sky2->port;
e0c28116 1299 u32 imask, ramsize;
ee7abb04 1300 int cap, err = -ENOMEM;
843a46f4 1301 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1302
ee7abb04
SH		 1303 /*
1304 * On dual port PCI-X card, there is an problem where status
1305 * can be received out of order due to split transactions
843a46f4 1306 */
ee7abb04
SH		 1307 if (otherdev && netif_running(otherdev) &&
1308 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1309 struct sky2_port *osky2 = netdev_priv(otherdev);
1310 u16 cmd;
1311
167f53d0 1312 pci_read_config_word(hw->pdev, cap + PCI_X_CMD, &cmd);
ee7abb04 1313 cmd &= ~PCI_X_CMD_MAX_SPLIT;
167f53d0 1314 pci_write_config_word(hw->pdev, cap + PCI_X_CMD, cmd);
ee7abb04
SH		 1315
1316 sky2->rx_csum = 0;
1317 osky2->rx_csum = 0;
1318 }
843a46f4 1319
cd28ab6a
SH		 1320 if (netif_msg_ifup(sky2))
1321 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1322
55d7b4e6
SH		 1323 netif_carrier_off(dev);
1324
cd28ab6a
SH		 1325 /* must be power of 2 */
1326 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1327 TX_RING_SIZE *
1328 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1329 &sky2->tx_le_map);
1330 if (!sky2->tx_le)
1331 goto err_out;
1332
6cdbbdf3 1333 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1334 GFP_KERNEL);
1335 if (!sky2->tx_ring)
1336 goto err_out;
88f5f0ca
SH		 1337
1338 tx_init(sky2);
cd28ab6a
SH		 1339
1340 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1341 &sky2->rx_le_map);
1342 if (!sky2->rx_le)
1343 goto err_out;
1344 memset(sky2->rx_le, 0, RX_LE_BYTES);
1345
291ea614 1346 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1347 GFP_KERNEL);
1348 if (!sky2->rx_ring)
1349 goto err_out;
1350
d3bcfbeb 1351 sky2_phy_power(hw, port, 1);
1352
cd28ab6a
SH		 1353 sky2_mac_init(hw, port);
1354
e0c28116
SH		 1355 /* Register is number of 4K blocks on internal RAM buffer. */
1356 ramsize = sky2_read8(hw, B2_E_0) * 4;
1357 if (ramsize > 0) {
67712901 1358 u32 rxspace;
cd28ab6a 1359
e0c28116 1360 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1361 if (ramsize < 16)
1362 rxspace = ramsize / 2;
1363 else
1364 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1365
67712901
SH		 1366 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1367 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1368
1369 /* Make sure SyncQ is disabled */
1370 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1371 RB_RST_SET);
1372 }
793b883e 1373
af4ed7e6 1374 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1375
69161611
SH		 1376 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1377 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1378 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1379
977bdf06 1380 /* Set almost empty threshold */
c2716fb4
SH		 1381 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1382 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1383 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1384
6b1a3aef 1385 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1386 TX_RING_SIZE - 1);
cd28ab6a 1387
bea3348e
SH		 1388 napi_enable(&hw->napi);
1389
6b1a3aef 1390 err = sky2_rx_start(sky2);
bea3348e
SH		 1391 if (err) {
1392 napi_disable(&hw->napi);
cd28ab6a 1393 goto err_out;
bea3348e 1394 }
cd28ab6a 1395
cd28ab6a 1396 /* Enable interrupts from phy/mac for port */
e07b1aa8 1397 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1398 imask |= portirq_msk[port];
e07b1aa8
SH		 1399 sky2_write32(hw, B0_IMSK, imask);
1400
cd28ab6a
SH		 1401 return 0;
1402
1403err_out:
1b537565 1404 if (sky2->rx_le) {
cd28ab6a
SH		 1405 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1406 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1407 sky2->rx_le = NULL;
1408 }
1409 if (sky2->tx_le) {
cd28ab6a
SH		 1410 pci_free_consistent(hw->pdev,
1411 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1412 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1413 sky2->tx_le = NULL;
1414 }
1415 kfree(sky2->tx_ring);
1416 kfree(sky2->rx_ring);
cd28ab6a 1417
1b537565
SH		 1418 sky2->tx_ring = NULL;
1419 sky2->rx_ring = NULL;
cd28ab6a
SH		 1420 return err;
1421}
1422
793b883e
SH		 1423/* Modular subtraction in ring */
1424static inline int tx_dist(unsigned tail, unsigned head)
1425{
cb5d9547 1426 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1427}
cd28ab6a 1428
793b883e
SH		 1429/* Number of list elements available for next tx */
1430static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1431{
793b883e 1432 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1433}
1434
793b883e 1435/* Estimate of number of transmit list elements required */
28bd181a 1436static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1437{
793b883e
SH		 1438 unsigned count;
1439
1440 count = sizeof(dma_addr_t) / sizeof(u32);
1441 count += skb_shinfo(skb)->nr_frags * count;
1442
89114afd 1443 if (skb_is_gso(skb))
793b883e
SH		 1444 ++count;
1445
84fa7933 1446 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1447 ++count;
1448
1449 return count;
cd28ab6a
SH		 1450}
1451
793b883e
SH		 1452/*
1453 * Put one packet in ring for transmit.
1454 * A single packet can generate multiple list elements, and
1455 * the number of ring elements will probably be less than the number
1456 * of list elements used.
1457 */
cd28ab6a
SH		 1458static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1459{
1460 struct sky2_port *sky2 = netdev_priv(dev);
1461 struct sky2_hw *hw = sky2->hw;
d1f13708 1462 struct sky2_tx_le *le = NULL;
6cdbbdf3 1463 struct tx_ring_info *re;
cd28ab6a
SH		 1464 unsigned i, len;
1465 dma_addr_t mapping;
1466 u32 addr64;
1467 u16 mss;
1468 u8 ctrl;
1469
2bb8c262
SH		 1470 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1471 return NETDEV_TX_BUSY;
cd28ab6a 1472
793b883e 1473 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1474 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1475 dev->name, sky2->tx_prod, skb->len);
1476
cd28ab6a
SH		 1477 len = skb_headlen(skb);
1478 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1479 addr64 = upper_32_bits(mapping);
793b883e 1480
a018e330 1481 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1482 if (addr64 != sky2->tx_addr64 ||
1483 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1484 le = get_tx_le(sky2);
f65b138c 1485 le->addr = cpu_to_le32(addr64);
793b883e 1486 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1487 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1488 }
cd28ab6a
SH		 1489
1490 /* Check for TCP Segmentation Offload */
7967168c 1491 mss = skb_shinfo(skb)->gso_size;
793b883e 1492 if (mss != 0) {
ea76e635
SH		 1493
1494 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1495 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1496
1497 if (mss != sky2->tx_last_mss) {
1498 le = get_tx_le(sky2);
1499 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1500
1501 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1502 le->opcode = OP_MSS | HW_OWNER;
1503 else
1504 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1505 sky2->tx_last_mss = mss;
1506 }
cd28ab6a
SH		 1507 }
1508
cd28ab6a 1509 ctrl = 0;
d1f13708 1510#ifdef SKY2_VLAN_TAG_USED
1511 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1512 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1513 if (!le) {
1514 le = get_tx_le(sky2);
f65b138c 1515 le->addr = 0;
d1f13708 1516 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1517 } else
1518 le->opcode |= OP_VLAN;
1519 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1520 ctrl |= INS_VLAN;
1521 }
1522#endif
1523
1524 /* Handle TCP checksum offload */
84fa7933 1525 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1526 /* On Yukon EX (some versions) encoding change. */
ea76e635 1527 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1528 ctrl |= CALSUM; /* auto checksum */
1529 else {
1530 const unsigned offset = skb_transport_offset(skb);
1531 u32 tcpsum;
1532
1533 tcpsum = offset << 16; /* sum start */
1534 tcpsum |= offset + skb->csum_offset; /* sum write */
1535
1536 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1537 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1538 ctrl |= UDPTCP;
1539
1540 if (tcpsum != sky2->tx_tcpsum) {
1541 sky2->tx_tcpsum = tcpsum;
1542
1543 le = get_tx_le(sky2);
1544 le->addr = cpu_to_le32(tcpsum);
1545 le->length = 0; /* initial checksum value */
1546 le->ctrl = 1; /* one packet */
1547 le->opcode = OP_TCPLISW | HW_OWNER;
1548 }
1d179332 1549 }
cd28ab6a
SH		 1550 }
1551
1552 le = get_tx_le(sky2);
f65b138c 1553 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1554 le->length = cpu_to_le16(len);
1555 le->ctrl = ctrl;
793b883e 1556 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1557
291ea614 1558 re = tx_le_re(sky2, le);
cd28ab6a 1559 re->skb = skb;
6cdbbdf3 1560 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1561 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1562
1563 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1564 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1565
1566 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1567 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1568 addr64 = upper_32_bits(mapping);
793b883e
SH		 1569 if (addr64 != sky2->tx_addr64) {
1570 le = get_tx_le(sky2);
f65b138c 1571 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1572 le->ctrl = 0;
1573 le->opcode = OP_ADDR64 | HW_OWNER;
1574 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1575 }
1576
1577 le = get_tx_le(sky2);
f65b138c 1578 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1579 le->length = cpu_to_le16(frag->size);
1580 le->ctrl = ctrl;
793b883e 1581 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1582
291ea614
SH		 1583 re = tx_le_re(sky2, le);
1584 re->skb = skb;
1585 pci_unmap_addr_set(re, mapaddr, mapping);
1586 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1587 }
6cdbbdf3 1588
cd28ab6a
SH		 1589 le->ctrl |= EOP;
1590
97bda706 1591 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1592 netif_stop_queue(dev);
b19666d9 1593
290d4de5 1594 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1595
cd28ab6a
SH		 1596 dev->trans_start = jiffies;
1597 return NETDEV_TX_OK;
1598}
1599
cd28ab6a 1600/*
793b883e
SH		 1601 * Free ring elements from starting at tx_cons until "done"
1602 *
1603 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1604 * buffers so make sure not to free skb to early.
cd28ab6a 1605 */
d11c13e7 1606static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1607{
d11c13e7 1608 struct net_device *dev = sky2->netdev;
af2a58ac 1609 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1610 unsigned idx;
cd28ab6a 1611
0e3ff6aa 1612 BUG_ON(done >= TX_RING_SIZE);
2224795d 1613
291ea614
SH		 1614 for (idx = sky2->tx_cons; idx != done;
1615 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1616 struct sky2_tx_le *le = sky2->tx_le + idx;
1617 struct tx_ring_info *re = sky2->tx_ring + idx;
1618
1619 switch(le->opcode & ~HW_OWNER) {
1620 case OP_LARGESEND:
1621 case OP_PACKET:
1622 pci_unmap_single(pdev,
1623 pci_unmap_addr(re, mapaddr),
1624 pci_unmap_len(re, maplen),
1625 PCI_DMA_TODEVICE);
af2a58ac 1626 break;
291ea614
SH		 1627 case OP_BUFFER:
1628 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1629 pci_unmap_len(re, maplen),
734d1868 1630 PCI_DMA_TODEVICE);
291ea614
SH		 1631 break;
1632 }
1633
1634 if (le->ctrl & EOP) {
1635 if (unlikely(netif_msg_tx_done(sky2)))
1636 printk(KERN_DEBUG "%s: tx done %u\n",
1637 dev->name, idx);
3cf26753 1638
2bf56fe2 1639 sky2->net_stats.tx_packets++;
1640 sky2->net_stats.tx_bytes += re->skb->len;
1641
794b2bd2 1642 dev_kfree_skb_any(re->skb);
3cf26753 1643 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1644 }
793b883e 1645 }
793b883e 1646
291ea614 1647 sky2->tx_cons = idx;
50432cb5
SH		 1648 smp_mb();
1649
22e11703 1650 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1651 netif_wake_queue(dev);
cd28ab6a
SH		 1652}
1653
1654/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1655static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1656{
2bb8c262
SH		 1657 struct sky2_port *sky2 = netdev_priv(dev);
1658
1659 netif_tx_lock_bh(dev);
d11c13e7 1660 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1661 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1662}
1663
1664/* Network shutdown */
1665static int sky2_down(struct net_device *dev)
1666{
1667 struct sky2_port *sky2 = netdev_priv(dev);
1668 struct sky2_hw *hw = sky2->hw;
1669 unsigned port = sky2->port;
1670 u16 ctrl;
e07b1aa8 1671 u32 imask;
cd28ab6a 1672
1b537565
SH		 1673 /* Never really got started! */
1674 if (!sky2->tx_le)
1675 return 0;
1676
cd28ab6a
SH		 1677 if (netif_msg_ifdown(sky2))
1678 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1679
018d1c66 1680 /* Stop more packets from being queued */
cd28ab6a
SH		 1681 netif_stop_queue(dev);
1682
bea3348e
SH		 1683 napi_disable(&hw->napi);
1684
ebc646f6
SH		 1685 /* Disable port IRQ */
1686 imask = sky2_read32(hw, B0_IMSK);
1687 imask &= ~portirq_msk[port];
1688 sky2_write32(hw, B0_IMSK, imask);
1689
d3bcfbeb 1690 sky2_gmac_reset(hw, port);
793b883e 1691
cd28ab6a
SH		 1692 /* Stop transmitter */
1693 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1694 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1695
1696 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1697 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1698
1699 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1700 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1701 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1702
1703 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1704
1705 /* Workaround shared GMAC reset */
793b883e
SH		 1706 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1707 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1708 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1709
1710 /* Disable Force Sync bit and Enable Alloc bit */
1711 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1712 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1713
1714 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1715 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1716 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1717
1718 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1719 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1720 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1721
1722 /* Reset the Tx prefetch units */
1723 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1724 PREF_UNIT_RST_SET);
1725
1726 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1727
6b1a3aef 1728 sky2_rx_stop(sky2);
cd28ab6a
SH		 1729
1730 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1731 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1732
d3bcfbeb 1733 sky2_phy_power(hw, port, 0);
1734
55d7b4e6
SH		 1735 netif_carrier_off(dev);
1736
d571b694 1737 /* turn off LED's */
cd28ab6a
SH		 1738 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1739
018d1c66 1740 synchronize_irq(hw->pdev->irq);
1741
2bb8c262 1742 sky2_tx_clean(dev);
cd28ab6a
SH		 1743 sky2_rx_clean(sky2);
1744
1745 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1746 sky2->rx_le, sky2->rx_le_map);
1747 kfree(sky2->rx_ring);
1748
1749 pci_free_consistent(hw->pdev,
1750 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1751 sky2->tx_le, sky2->tx_le_map);
1752 kfree(sky2->tx_ring);
1753
1b537565
SH		 1754 sky2->tx_le = NULL;
1755 sky2->rx_le = NULL;
1756
1757 sky2->rx_ring = NULL;
1758 sky2->tx_ring = NULL;
1759
cd28ab6a
SH		 1760 return 0;
1761}
1762
1763static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1764{
ea76e635 1765 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1766 return SPEED_1000;
1767
05745c4a
SH		 1768 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1769 if (aux & PHY_M_PS_SPEED_100)
1770 return SPEED_100;
1771 else
1772 return SPEED_10;
1773 }
cd28ab6a
SH		 1774
1775 switch (aux & PHY_M_PS_SPEED_MSK) {
1776 case PHY_M_PS_SPEED_1000:
1777 return SPEED_1000;
1778 case PHY_M_PS_SPEED_100:
1779 return SPEED_100;
1780 default:
1781 return SPEED_10;
1782 }
1783}
1784
1785static void sky2_link_up(struct sky2_port *sky2)
1786{
1787 struct sky2_hw *hw = sky2->hw;
1788 unsigned port = sky2->port;
1789 u16 reg;
16ad91e1
SH		 1790 static const char *fc_name[] = {
1791 [FC_NONE] = "none",
1792 [FC_TX] = "tx",
1793 [FC_RX] = "rx",
1794 [FC_BOTH] = "both",
1795 };
cd28ab6a 1796
cd28ab6a 1797 /* enable Rx/Tx */
2eaba1a2 1798 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1799 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1800 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1801
1802 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1803
1804 netif_carrier_on(sky2->netdev);
cd28ab6a 1805
75e80683 1806 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1807
cd28ab6a 1808 /* Turn on link LED */
793b883e 1809 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1810 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1811
ea76e635 1812 if (hw->flags & SKY2_HW_NEWER_PHY) {
793b883e 1813 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1814 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1815
1816 switch(sky2->speed) {
1817 case SPEED_10:
1818 led |= PHY_M_LEDC_INIT_CTRL(7);
1819 break;
1820
1821 case SPEED_100:
1822 led |= PHY_M_LEDC_STA1_CTRL(7);
1823 break;
1824
1825 case SPEED_1000:
1826 led |= PHY_M_LEDC_STA0_CTRL(7);
1827 break;
1828 }
793b883e
SH		 1829
1830 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1831 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1832 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1833 }
1834
cd28ab6a
SH		 1835 if (netif_msg_link(sky2))
1836 printk(KERN_INFO PFX
d571b694 1837 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1838 sky2->netdev->name, sky2->speed,
1839 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1840 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1841}
1842
1843static void sky2_link_down(struct sky2_port *sky2)
1844{
1845 struct sky2_hw *hw = sky2->hw;
1846 unsigned port = sky2->port;
1847 u16 reg;
1848
1849 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1850
1851 reg = gma_read16(hw, port, GM_GP_CTRL);
1852 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1853 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1854
cd28ab6a 1855 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1856
1857 /* Turn on link LED */
1858 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1859
1860 if (netif_msg_link(sky2))
1861 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1862
cd28ab6a
SH		 1863 sky2_phy_init(hw, port);
1864}
1865
16ad91e1
SH		 1866static enum flow_control sky2_flow(int rx, int tx)
1867{
1868 if (rx)
1869 return tx ? FC_BOTH : FC_RX;
1870 else
1871 return tx ? FC_TX : FC_NONE;
1872}
1873
793b883e
SH		 1874static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1875{
1876 struct sky2_hw *hw = sky2->hw;
1877 unsigned port = sky2->port;
da4c1ff4 1878 u16 advert, lpa;
793b883e 1879
da4c1ff4 1880 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1881 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1882 if (lpa & PHY_M_AN_RF) {
1883 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1884 return -1;
1885 }
1886
793b883e
SH		 1887 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1888 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1889 sky2->netdev->name);
1890 return -1;
1891 }
1892
793b883e 1893 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1894 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1895
da4c1ff4
SH		 1896 /* Since the pause result bits seem to in different positions on
1897 * different chips. look at registers.
1898 */
ea76e635 1899 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1900 /* Shift for bits in fiber PHY */
1901 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1902 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1903
1904 if (advert & ADVERTISE_1000XPAUSE)
1905 advert |= ADVERTISE_PAUSE_CAP;
1906 if (advert & ADVERTISE_1000XPSE_ASYM)
1907 advert |= ADVERTISE_PAUSE_ASYM;
1908 if (lpa & LPA_1000XPAUSE)
1909 lpa |= LPA_PAUSE_CAP;
1910 if (lpa & LPA_1000XPAUSE_ASYM)
1911 lpa |= LPA_PAUSE_ASYM;
1912 }
793b883e 1913
da4c1ff4
SH		 1914 sky2->flow_status = FC_NONE;
1915 if (advert & ADVERTISE_PAUSE_CAP) {
1916 if (lpa & LPA_PAUSE_CAP)
1917 sky2->flow_status = FC_BOTH;
1918 else if (advert & ADVERTISE_PAUSE_ASYM)
1919 sky2->flow_status = FC_RX;
1920 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1921 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1922 sky2->flow_status = FC_TX;
1923 }
793b883e 1924
16ad91e1 1925 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1926 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1927 sky2->flow_status = FC_NONE;
2eaba1a2 1928
da4c1ff4 1929 if (sky2->flow_status & FC_TX)
793b883e
SH		 1930 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1931 else
1932 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1933
1934 return 0;
1935}
cd28ab6a 1936
e07b1aa8
SH		 1937/* Interrupt from PHY */
1938static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1939{
e07b1aa8
SH		 1940 struct net_device *dev = hw->dev[port];
1941 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1942 u16 istatus, phystat;
1943
ebc646f6
SH		 1944 if (!netif_running(dev))
1945 return;
1946
e07b1aa8
SH		 1947 spin_lock(&sky2->phy_lock);
1948 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1949 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1950
cd28ab6a
SH		 1951 if (netif_msg_intr(sky2))
1952 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1953 sky2->netdev->name, istatus, phystat);
1954
2eaba1a2 1955 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1956 if (sky2_autoneg_done(sky2, phystat) == 0)
1957 sky2_link_up(sky2);
1958 goto out;
1959 }
cd28ab6a 1960
793b883e
SH		 1961 if (istatus & PHY_M_IS_LSP_CHANGE)
1962 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1963
793b883e
SH		 1964 if (istatus & PHY_M_IS_DUP_CHANGE)
1965 sky2->duplex =
1966 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1967
793b883e
SH		 1968 if (istatus & PHY_M_IS_LST_CHANGE) {
1969 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1970 sky2_link_up(sky2);
793b883e
SH		 1971 else
1972 sky2_link_down(sky2);
cd28ab6a 1973 }
793b883e 1974out:
e07b1aa8 1975 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1976}
1977
62335ab0 1978/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1979 * and tx queue is full (stopped).
1980 */
cd28ab6a
SH		 1981static void sky2_tx_timeout(struct net_device *dev)
1982{
1983 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1984 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1985
1986 if (netif_msg_timer(sky2))
1987 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1988
8f24664d 1989 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1990 dev->name, sky2->tx_cons, sky2->tx_prod,
1991 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1992 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1993
81906791
SH		 1994 /* can't restart safely under softirq */
1995 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1996}
1997
1998static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1999{
6b1a3aef 2000 struct sky2_port *sky2 = netdev_priv(dev);
2001 struct sky2_hw *hw = sky2->hw;
b628ed98 2002 unsigned port = sky2->port;
6b1a3aef 2003 int err;
2004 u16 ctl, mode;
e07b1aa8 2005 u32 imask;
cd28ab6a
SH		 2006
2007 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2008 return -EINVAL;
2009
05745c4a
SH		 2010 if (new_mtu > ETH_DATA_LEN &&
2011 (hw->chip_id == CHIP_ID_YUKON_FE ||
2012 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2013 return -EINVAL;
2014
6b1a3aef 2015 if (!netif_running(dev)) {
2016 dev->mtu = new_mtu;
2017 return 0;
2018 }
2019
e07b1aa8 2020 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2021 sky2_write32(hw, B0_IMSK, 0);
2022
018d1c66 2023 dev->trans_start = jiffies; /* prevent tx timeout */
2024 netif_stop_queue(dev);
bea3348e 2025 napi_disable(&hw->napi);
018d1c66 2026
e07b1aa8
SH		 2027 synchronize_irq(hw->pdev->irq);
2028
e0c28116 2029 if (sky2_read8(hw, B2_E_0) == 0)
69161611 2030 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2031
2032 ctl = gma_read16(hw, port, GM_GP_CTRL);
2033 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2034 sky2_rx_stop(sky2);
2035 sky2_rx_clean(sky2);
cd28ab6a
SH		 2036
2037 dev->mtu = new_mtu;
14d0263f 2038
6b1a3aef 2039 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2040 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2041
2042 if (dev->mtu > ETH_DATA_LEN)
2043 mode |= GM_SMOD_JUMBO_ENA;
2044
b628ed98 2045 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2046
b628ed98 2047 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2048
6b1a3aef 2049 err = sky2_rx_start(sky2);
e07b1aa8 2050 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2051
bea3348e
SH		 2052 /* Unconditionally re-enable NAPI because even if we
2053 * call dev_close() that will do a napi_disable().
2054 */
2055 napi_enable(&hw->napi);
2056
1b537565
SH		 2057 if (err)
2058 dev_close(dev);
2059 else {
b628ed98 2060 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2061
1b537565
SH		 2062 netif_wake_queue(dev);
2063 }
2064
cd28ab6a
SH		 2065 return err;
2066}
2067
14d0263f
SH		 2068/* For small just reuse existing skb for next receive */
2069static struct sk_buff *receive_copy(struct sky2_port *sky2,
2070 const struct rx_ring_info *re,
2071 unsigned length)
2072{
2073 struct sk_buff *skb;
2074
2075 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2076 if (likely(skb)) {
2077 skb_reserve(skb, 2);
2078 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2079 length, PCI_DMA_FROMDEVICE);
d626f62b 2080 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2081 skb->ip_summed = re->skb->ip_summed;
2082 skb->csum = re->skb->csum;
2083 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2084 length, PCI_DMA_FROMDEVICE);
2085 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2086 skb_put(skb, length);
14d0263f
SH		 2087 }
2088 return skb;
2089}
2090
2091/* Adjust length of skb with fragments to match received data */
2092static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2093 unsigned int length)
2094{
2095 int i, num_frags;
2096 unsigned int size;
2097
2098 /* put header into skb */
2099 size = min(length, hdr_space);
2100 skb->tail += size;
2101 skb->len += size;
2102 length -= size;
2103
2104 num_frags = skb_shinfo(skb)->nr_frags;
2105 for (i = 0; i < num_frags; i++) {
2106 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2107
2108 if (length == 0) {
2109 /* don't need this page */
2110 __free_page(frag->page);
2111 --skb_shinfo(skb)->nr_frags;
2112 } else {
2113 size = min(length, (unsigned) PAGE_SIZE);
2114
2115 frag->size = size;
2116 skb->data_len += size;
2117 skb->truesize += size;
2118 skb->len += size;
2119 length -= size;
2120 }
2121 }
2122}
2123
2124/* Normal packet - take skb from ring element and put in a new one */
2125static struct sk_buff *receive_new(struct sky2_port *sky2,
2126 struct rx_ring_info *re,
2127 unsigned int length)
2128{
2129 struct sk_buff *skb, *nskb;
2130 unsigned hdr_space = sky2->rx_data_size;
2131
14d0263f
SH		 2132 /* Don't be tricky about reusing pages (yet) */
2133 nskb = sky2_rx_alloc(sky2);
2134 if (unlikely(!nskb))
2135 return NULL;
2136
2137 skb = re->skb;
2138 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2139
2140 prefetch(skb->data);
2141 re->skb = nskb;
2142 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2143
2144 if (skb_shinfo(skb)->nr_frags)
2145 skb_put_frags(skb, hdr_space, length);
2146 else
489b10c1 2147 skb_put(skb, length);
14d0263f
SH		 2148 return skb;
2149}
2150
cd28ab6a
SH		 2151/*
2152 * Receive one packet.
d571b694 2153 * For larger packets, get new buffer.
cd28ab6a 2154 */
497d7c86 2155static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2156 u16 length, u32 status)
2157{
497d7c86 2158 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2159 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2160 struct sk_buff *skb = NULL;
d6532232
SH		 2161 u16 count = (status & GMR_FS_LEN) >> 16;
2162
2163#ifdef SKY2_VLAN_TAG_USED
2164 /* Account for vlan tag */
2165 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2166 count -= VLAN_HLEN;
2167#endif
cd28ab6a
SH		 2168
2169 if (unlikely(netif_msg_rx_status(sky2)))
2170 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2171 dev->name, sky2->rx_next, status, length);
cd28ab6a 2172
793b883e 2173 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2174 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2175
3b12e014
SH		 2176 /* This chip has hardware problems that generates bogus status.
2177 * So do only marginal checking and expect higher level protocols
2178 * to handle crap frames.
2179 */
2180 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2181 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2182 length != count)
2183 goto okay;
2184
42eeea01 2185 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2186 goto error;
2187
42eeea01 2188 if (!(status & GMR_FS_RX_OK))
2189 goto resubmit;
2190
d6532232
SH		 2191 /* if length reported by DMA does not match PHY, packet was truncated */
2192 if (length != count)
3b12e014 2193 goto len_error;
71749531 2194
3b12e014 2195okay:
14d0263f
SH		 2196 if (length < copybreak)
2197 skb = receive_copy(sky2, re, length);
2198 else
2199 skb = receive_new(sky2, re, length);
793b883e 2200resubmit:
14d0263f 2201 sky2_rx_submit(sky2, re);
79e57d32 2202
cd28ab6a
SH		 2203 return skb;
2204
3b12e014 2205len_error:
71749531
SH		 2206 /* Truncation of overlength packets
2207 causes PHY length to not match MAC length */
2208 ++sky2->net_stats.rx_length_errors;
d6532232 2209 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2210 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2211 dev->name, status, length);
d6532232 2212 goto resubmit;
71749531 2213
cd28ab6a 2214error:
6e15b712 2215 ++sky2->net_stats.rx_errors;
b6d77734 2216 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2217 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2218 goto resubmit;
2219 }
6e15b712 2220
3be92a70 2221 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2222 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2223 dev->name, status, length);
793b883e
SH		 2224
2225 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2226 sky2->net_stats.rx_length_errors++;
2227 if (status & GMR_FS_FRAGMENT)
2228 sky2->net_stats.rx_frame_errors++;
2229 if (status & GMR_FS_CRC_ERR)
2230 sky2->net_stats.rx_crc_errors++;
79e57d32 2231
793b883e 2232 goto resubmit;
cd28ab6a
SH		 2233}
2234
e07b1aa8
SH		 2235/* Transmit complete */
2236static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2237{
e07b1aa8 2238 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2239
e07b1aa8 2240 if (netif_running(dev)) {
2bb8c262 2241 netif_tx_lock(dev);
e07b1aa8 2242 sky2_tx_complete(sky2, last);
2bb8c262 2243 netif_tx_unlock(dev);
2224795d 2244 }
cd28ab6a
SH		 2245}
2246
e07b1aa8
SH		 2247/* Process status response ring */
2248static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2249{
e07b1aa8 2250 int work_done = 0;
55c9dd35 2251 unsigned rx[2] = { 0, 0 };
e71ebd73 2252 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2253
af2a58ac 2254 rmb();
bea86103 2255
e71ebd73 2256 while (hw->st_idx != hwidx) {
55c9dd35 2257 struct sky2_port *sky2;
13210ce5 2258 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2259 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2260 struct net_device *dev;
cd28ab6a 2261 struct sk_buff *skb;
cd28ab6a
SH		 2262 u32 status;
2263 u16 length;
2264
cb5d9547 2265 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2266
69161611 2267 dev = hw->dev[port];
13210ce5 2268 sky2 = netdev_priv(dev);
f65b138c
SH		 2269 length = le16_to_cpu(le->length);
2270 status = le32_to_cpu(le->status);
cd28ab6a 2271
e71ebd73 2272 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2273 case OP_RXSTAT:
55c9dd35 2274 ++rx[port];
497d7c86 2275 skb = sky2_receive(dev, length, status);
3225b919
SH		 2276 if (unlikely(!skb)) {
2277 sky2->net_stats.rx_dropped++;
55c9dd35 2278 break;
3225b919 2279 }
13210ce5 2280
69161611 2281 /* This chip reports checksum status differently */
05745c4a 2282 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2283 if (sky2->rx_csum &&
2284 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2285 (le->css & CSS_TCPUDPCSOK))
2286 skb->ip_summed = CHECKSUM_UNNECESSARY;
2287 else
2288 skb->ip_summed = CHECKSUM_NONE;
2289 }
2290
13210ce5 2291 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2292 sky2->net_stats.rx_packets++;
2293 sky2->net_stats.rx_bytes += skb->len;
13210ce5 2294 dev->last_rx = jiffies;
2295
d1f13708 2296#ifdef SKY2_VLAN_TAG_USED
2297 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2298 vlan_hwaccel_receive_skb(skb,
2299 sky2->vlgrp,
2300 be16_to_cpu(sky2->rx_tag));
2301 } else
2302#endif
cd28ab6a 2303 netif_receive_skb(skb);
13210ce5 2304
22e11703 2305 /* Stop after net poll weight */
13210ce5 2306 if (++work_done >= to_do)
2307 goto exit_loop;
cd28ab6a
SH		 2308 break;
2309
d1f13708 2310#ifdef SKY2_VLAN_TAG_USED
2311 case OP_RXVLAN:
2312 sky2->rx_tag = length;
2313 break;
2314
2315 case OP_RXCHKSVLAN:
2316 sky2->rx_tag = length;
2317 /* fall through */
2318#endif
cd28ab6a 2319 case OP_RXCHKS:
87418307
SH		 2320 if (!sky2->rx_csum)
2321 break;
2322
05745c4a
SH		 2323 /* If this happens then driver assuming wrong format */
2324 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2325 if (net_ratelimit())
2326 printk(KERN_NOTICE "%s: unexpected"
2327 " checksum status\n",
2328 dev->name);
69161611 2329 break;
05745c4a 2330 }
69161611 2331
87418307
SH		 2332 /* Both checksum counters are programmed to start at
2333 * the same offset, so unless there is a problem they
2334 * should match. This failure is an early indication that
2335 * hardware receive checksumming won't work.
2336 */
2337 if (likely(status >> 16 == (status & 0xffff))) {
2338 skb = sky2->rx_ring[sky2->rx_next].skb;
2339 skb->ip_summed = CHECKSUM_COMPLETE;
2340 skb->csum = status & 0xffff;
2341 } else {
2342 printk(KERN_NOTICE PFX "%s: hardware receive "
2343 "checksum problem (status = %#x)\n",
2344 dev->name, status);
2345 sky2->rx_csum = 0;
2346 sky2_write32(sky2->hw,
69161611 2347 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2348 BMU_DIS_RX_CHKSUM);
2349 }
cd28ab6a
SH		 2350 break;
2351
2352 case OP_TXINDEXLE:
13b97b74 2353 /* TX index reports status for both ports */
f55925d7
SH		 2354 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2355 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2356 if (hw->dev[1])
2357 sky2_tx_done(hw->dev[1],
2358 ((status >> 24) & 0xff)
2359 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2360 break;
2361
cd28ab6a
SH		 2362 default:
2363 if (net_ratelimit())
793b883e 2364 printk(KERN_WARNING PFX
e71ebd73 2365 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a 2366 }
13210ce5 2367 }
cd28ab6a 2368
fe2a24df
SH		 2369 /* Fully processed status ring so clear irq */
2370 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2371
13210ce5 2372exit_loop:
55c9dd35
SH		 2373 if (rx[0])
2374 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2375
55c9dd35
SH		 2376 if (rx[1])
2377 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2378
e07b1aa8 2379 return work_done;
cd28ab6a
SH		 2380}
2381
2382static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2383{
2384 struct net_device *dev = hw->dev[port];
2385
3be92a70
SH		 2386 if (net_ratelimit())
2387 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2388 dev->name, status);
cd28ab6a
SH		 2389
2390 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2391 if (net_ratelimit())
2392 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2393 dev->name);
cd28ab6a
SH		 2394 /* Clear IRQ */
2395 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2396 }
2397
2398 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2399 if (net_ratelimit())
2400 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2401 dev->name);
cd28ab6a
SH		 2402
2403 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2404 }
2405
2406 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2407 if (net_ratelimit())
2408 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2409 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2410 }
2411
2412 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2413 if (net_ratelimit())
2414 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2415 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2416 }
2417
2418 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2419 if (net_ratelimit())
2420 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2421 dev->name);
cd28ab6a
SH		 2422 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2423 }
2424}
2425
2426static void sky2_hw_intr(struct sky2_hw *hw)
2427{
555382cb 2428 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2429 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2430 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2431
2432 status &= hwmsk;
cd28ab6a 2433
793b883e 2434 if (status & Y2_IS_TIST_OV)
cd28ab6a 2435 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2436
2437 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2438 u16 pci_err;
2439
167f53d0 2440 pci_read_config_word(pdev, PCI_STATUS, &pci_err);
3be92a70 2441 if (net_ratelimit())
555382cb 2442 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2443 pci_err);
cd28ab6a 2444
167f53d0
SH		 2445 pci_write_config_word(pdev, PCI_STATUS,
2446 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2447 }
2448
2449 if (status & Y2_IS_PCI_EXP) {
d571b694 2450 /* PCI-Express uncorrectable Error occurred */
555382cb
SH		 2451 int pos = pci_find_aer_capability(hw->pdev);
2452 u32 err;
cd28ab6a 2453
555382cb 2454 pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_STATUS, &err);
3be92a70 2455 if (net_ratelimit())
555382cb
SH		 2456 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2457 pci_cleanup_aer_uncorrect_error_status(pdev);
cd28ab6a
SH		 2458 }
2459
2460 if (status & Y2_HWE_L1_MASK)
2461 sky2_hw_error(hw, 0, status);
2462 status >>= 8;
2463 if (status & Y2_HWE_L1_MASK)
2464 sky2_hw_error(hw, 1, status);
2465}
2466
2467static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2468{
2469 struct net_device *dev = hw->dev[port];
2470 struct sky2_port *sky2 = netdev_priv(dev);
2471 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2472
2473 if (netif_msg_intr(sky2))
2474 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2475 dev->name, status);
2476
a3caeada
SH		 2477 if (status & GM_IS_RX_CO_OV)
2478 gma_read16(hw, port, GM_RX_IRQ_SRC);
2479
2480 if (status & GM_IS_TX_CO_OV)
2481 gma_read16(hw, port, GM_TX_IRQ_SRC);
2482
cd28ab6a
SH		 2483 if (status & GM_IS_RX_FF_OR) {
2484 ++sky2->net_stats.rx_fifo_errors;
2485 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2486 }
2487
2488 if (status & GM_IS_TX_FF_UR) {
2489 ++sky2->net_stats.tx_fifo_errors;
2490 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2491 }
cd28ab6a
SH		 2492}
2493
40b01727
SH		 2494/* This should never happen it is a bug. */
2495static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2496 u16 q, unsigned ring_size)
d257924e
SH		 2497{
2498 struct net_device *dev = hw->dev[port];
2499 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2500 unsigned idx;
2501 const u64 *le = (q == Q_R1 || q == Q_R2)
2502 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2503
40b01727
SH		 2504 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2505 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2506 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2507 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2508
40b01727 2509 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2510}
cd28ab6a 2511
75e80683
SH		 2512static int sky2_rx_hung(struct net_device *dev)
2513{
2514 struct sky2_port *sky2 = netdev_priv(dev);
2515 struct sky2_hw *hw = sky2->hw;
2516 unsigned port = sky2->port;
2517 unsigned rxq = rxqaddr[port];
2518 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2519 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2520 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2521 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2522
2523 /* If idle and MAC or PCI is stuck */
2524 if (sky2->check.last == dev->last_rx &&
2525 ((mac_rp == sky2->check.mac_rp &&
2526 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2527 /* Check if the PCI RX hang */
2528 (fifo_rp == sky2->check.fifo_rp &&
2529 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2530 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2531 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2532 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2533 return 1;
2534 } else {
2535 sky2->check.last = dev->last_rx;
2536 sky2->check.mac_rp = mac_rp;
2537 sky2->check.mac_lev = mac_lev;
2538 sky2->check.fifo_rp = fifo_rp;
2539 sky2->check.fifo_lev = fifo_lev;
2540 return 0;
2541 }
2542}
2543
32c2c300 2544static void sky2_watchdog(unsigned long arg)
d27ed387 2545{
01bd7564 2546 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2547
75e80683 2548 /* Check for lost IRQ once a second */
32c2c300 2549 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2550 napi_schedule(&hw->napi);
75e80683
SH		 2551 } else {
2552 int i, active = 0;
2553
2554 for (i = 0; i < hw->ports; i++) {
bea3348e 2555 struct net_device *dev = hw->dev[i];
75e80683
SH		 2556 if (!netif_running(dev))
2557 continue;
2558 ++active;
2559
2560 /* For chips with Rx FIFO, check if stuck */
e0c28116 2561 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
75e80683
SH		 2562 sky2_rx_hung(dev)) {
2563 pr_info(PFX "%s: receiver hang detected\n",
2564 dev->name);
2565 schedule_work(&hw->restart_work);
2566 return;
2567 }
2568 }
2569
2570 if (active == 0)
2571 return;
32c2c300 2572 }
01bd7564 2573
75e80683 2574 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2575}
2576
40b01727
SH		 2577/* Hardware/software error handling */
2578static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2579{
40b01727
SH		 2580 if (net_ratelimit())
2581 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2582
1e5f1283
SH		 2583 if (status & Y2_IS_HW_ERR)
2584 sky2_hw_intr(hw);
d257924e 2585
1e5f1283
SH		 2586 if (status & Y2_IS_IRQ_MAC1)
2587 sky2_mac_intr(hw, 0);
cd28ab6a 2588
1e5f1283
SH		 2589 if (status & Y2_IS_IRQ_MAC2)
2590 sky2_mac_intr(hw, 1);
cd28ab6a 2591
1e5f1283 2592 if (status & Y2_IS_CHK_RX1)
40b01727 2593 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2594
1e5f1283 2595 if (status & Y2_IS_CHK_RX2)
40b01727 2596 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2597
1e5f1283 2598 if (status & Y2_IS_CHK_TXA1)
40b01727 2599 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2600
1e5f1283 2601 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2602 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2603}
2604
bea3348e 2605static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2606{
bea3348e 2607 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2608 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2609 int work_done = 0;
40b01727
SH		 2610
2611 if (unlikely(status & Y2_IS_ERROR))
2612 sky2_err_intr(hw, status);
2613
2614 if (status & Y2_IS_IRQ_PHY1)
2615 sky2_phy_intr(hw, 0);
2616
2617 if (status & Y2_IS_IRQ_PHY2)
2618 sky2_phy_intr(hw, 1);
cd28ab6a 2619
6f535763
DM		 2620 for(;;) {
2621 work_done += sky2_status_intr(hw, work_limit);
2622
2623 if (work_done >= work_limit)
2624 break;
2625
2626 /* More work? */
2627 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
2628 continue;
86fba634 2629
bea3348e
SH		 2630 /* Bug/Errata workaround?
2631 * Need to kick the TX irq moderation timer.
2632 */
2633 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2634 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2635 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2636 }
5c11ce70 2637
bea3348e
SH		 2638 napi_complete(napi);
2639 sky2_read32(hw, B0_Y2_SP_LISR);
6f535763
DM		 2640 break;
2641
fe2a24df 2642 }
6f535763 2643
bea3348e 2644 return work_done;
e07b1aa8
SH		 2645}
2646
7d12e780 2647static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2648{
2649 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2650 u32 status;
2651
2652 /* Reading this mask interrupts as side effect */
2653 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2654 if (status == 0 || status == ~0)
2655 return IRQ_NONE;
793b883e 2656
e07b1aa8 2657 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2658
2659 napi_schedule(&hw->napi);
793b883e 2660
cd28ab6a
SH		 2661 return IRQ_HANDLED;
2662}
2663
2664#ifdef CONFIG_NET_POLL_CONTROLLER
2665static void sky2_netpoll(struct net_device *dev)
2666{
2667 struct sky2_port *sky2 = netdev_priv(dev);
2668
bea3348e 2669 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2670}
2671#endif
2672
2673/* Chip internal frequency for clock calculations */
05745c4a 2674static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2675{
793b883e 2676 switch (hw->chip_id) {
cd28ab6a 2677 case CHIP_ID_YUKON_EC:
5a5b1ea0 2678 case CHIP_ID_YUKON_EC_U:
93745494 2679 case CHIP_ID_YUKON_EX:
05745c4a
SH		 2680 return 125;
2681
cd28ab6a 2682 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2683 return 100;
2684
2685 case CHIP_ID_YUKON_FE_P:
2686 return 50;
2687
2688 case CHIP_ID_YUKON_XL:
2689 return 156;
2690
2691 default:
2692 BUG();
cd28ab6a
SH		 2693 }
2694}
2695
fb17358f 2696static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2697{
fb17358f 2698 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2699}
2700
fb17358f 2701static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2702{
fb17358f 2703 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2704}
2705
fb17358f 2706
e3173832 2707static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2708{
167f53d0 2709 int rc;
b89165f2 2710 u8 t8;
cd28ab6a 2711
167f53d0
SH		 2712 /* Enable all clocks and check for bad PCI access */
2713 rc = pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
2714 if (rc)
2715 return rc;
451af335 2716
cd28ab6a 2717 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2718
cd28ab6a 2719 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2720 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2721
2722 switch(hw->chip_id) {
2723 case CHIP_ID_YUKON_XL:
2724 hw->flags = SKY2_HW_GIGABIT
e0c28116
SH		 2725 | SKY2_HW_NEWER_PHY;
2726 if (hw->chip_rev < 3)
2727 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2728
ea76e635
SH		 2729 break;
2730
2731 case CHIP_ID_YUKON_EC_U:
2732 hw->flags = SKY2_HW_GIGABIT
2733 | SKY2_HW_NEWER_PHY
2734 | SKY2_HW_ADV_POWER_CTL;
2735 break;
2736
2737 case CHIP_ID_YUKON_EX:
2738 hw->flags = SKY2_HW_GIGABIT
2739 | SKY2_HW_NEWER_PHY
2740 | SKY2_HW_NEW_LE
2741 | SKY2_HW_ADV_POWER_CTL;
2742
2743 /* New transmit checksum */
2744 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2745 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2746 break;
2747
2748 case CHIP_ID_YUKON_EC:
2749 /* This rev is really old, and requires untested workarounds */
2750 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2751 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2752 return -EOPNOTSUPP;
2753 }
e0c28116 2754 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
ea76e635
SH		 2755 break;
2756
2757 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2758 break;
2759
05745c4a
SH		 2760 case CHIP_ID_YUKON_FE_P:
2761 hw->flags = SKY2_HW_NEWER_PHY
2762 | SKY2_HW_NEW_LE
2763 | SKY2_HW_AUTO_TX_SUM
2764 | SKY2_HW_ADV_POWER_CTL;
2765 break;
ea76e635 2766 default:
b02a9258
SH		 2767 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2768 hw->chip_id);
cd28ab6a
SH		 2769 return -EOPNOTSUPP;
2770 }
2771
ea76e635
SH		 2772 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2773 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2774 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2775
290d4de5 2776
e3173832
SH		 2777 hw->ports = 1;
2778 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2779 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2780 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2781 ++hw->ports;
2782 }
2783
2784 return 0;
2785}
2786
2787static void sky2_reset(struct sky2_hw *hw)
2788{
555382cb 2789 struct pci_dev *pdev = hw->pdev;
e3173832 2790 u16 status;
555382cb
SH		 2791 int i, cap;
2792 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2793
cd28ab6a 2794 /* disable ASF */
4f44d8ba
SH		 2795 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2796 status = sky2_read16(hw, HCU_CCSR);
2797 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2798 HCU_CCSR_UC_STATE_MSK);
2799 sky2_write16(hw, HCU_CCSR, status);
2800 } else
2801 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2802 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2803
2804 /* do a SW reset */
2805 sky2_write8(hw, B0_CTST, CS_RST_SET);
2806 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2807
2808 /* clear PCI errors, if any */
167f53d0
SH		 2809 pci_read_config_word(pdev, PCI_STATUS, &status);
2810 status |= PCI_STATUS_ERROR_BITS;
2811 pci_write_config_word(pdev, PCI_STATUS, status);
cd28ab6a
SH		 2812
2813 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2814
555382cb
SH		 2815 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2816 if (cap) {
2817 /* Check for advanced error reporting */
2818 pci_cleanup_aer_uncorrect_error_status(pdev);
2819 pci_cleanup_aer_correct_error_status(pdev);
2820
2821 /* If error bit is stuck on ignore it */
2822 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2823 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7bd656d1 2824
555382cb
SH		 2825 else if (pci_enable_pcie_error_reporting(pdev))
2826 hwe_mask |= Y2_IS_PCI_EXP;
2827 }
cd28ab6a 2828
ae306cca 2829 sky2_power_on(hw);
cd28ab6a
SH		 2830
2831 for (i = 0; i < hw->ports; i++) {
2832 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2833 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2834
2835 if (hw->chip_id == CHIP_ID_YUKON_EX)
2836 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2837 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2838 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2839 }
2840
793b883e
SH		 2841 /* Clear I2C IRQ noise */
2842 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2843
2844 /* turn off hardware timer (unused) */
2845 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2846 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2847
cd28ab6a
SH		 2848 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2849
69634ee7
SH		 2850 /* Turn off descriptor polling */
2851 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2852
2853 /* Turn off receive timestamp */
2854 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2855 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2856
2857 /* enable the Tx Arbiters */
2858 for (i = 0; i < hw->ports; i++)
2859 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2860
2861 /* Initialize ram interface */
2862 for (i = 0; i < hw->ports; i++) {
793b883e 2863 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2864
2865 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2866 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2867 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2868 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2869 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2870 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2871 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2872 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2873 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2874 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2875 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2876 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2877 }
2878
555382cb 2879 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2880
cd28ab6a 2881 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2882 sky2_gmac_reset(hw, i);
cd28ab6a 2883
cd28ab6a
SH		 2884 memset(hw->st_le, 0, STATUS_LE_BYTES);
2885 hw->st_idx = 0;
2886
2887 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2888 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2889
2890 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2891 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2892
2893 /* Set the list last index */
793b883e 2894 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2895
290d4de5
SH		 2896 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2897 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2898
290d4de5
SH		 2899 /* set Status-FIFO ISR watermark */
2900 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2901 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2902 else
2903 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2904
290d4de5 2905 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2906 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2907 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2908
793b883e 2909 /* enable status unit */
cd28ab6a
SH		 2910 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2911
2912 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2913 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2914 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2915}
2916
81906791
SH		 2917static void sky2_restart(struct work_struct *work)
2918{
2919 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2920 struct net_device *dev;
2921 int i, err;
2922
81906791
SH		 2923 rtnl_lock();
2924 sky2_write32(hw, B0_IMSK, 0);
2925 sky2_read32(hw, B0_IMSK);
2926
81906791
SH		 2927 for (i = 0; i < hw->ports; i++) {
2928 dev = hw->dev[i];
2929 if (netif_running(dev))
2930 sky2_down(dev);
2931 }
2932
2933 sky2_reset(hw);
2934 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
81906791
SH		 2935
2936 for (i = 0; i < hw->ports; i++) {
2937 dev = hw->dev[i];
2938 if (netif_running(dev)) {
2939 err = sky2_up(dev);
2940 if (err) {
2941 printk(KERN_INFO PFX "%s: could not restart %d\n",
2942 dev->name, err);
2943 dev_close(dev);
2944 }
2945 }
2946 }
2947
81906791
SH		 2948 rtnl_unlock();
2949}
2950
e3173832
SH		 2951static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2952{
2953 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2954}
2955
2956static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2957{
2958 const struct sky2_port *sky2 = netdev_priv(dev);
2959
2960 wol->supported = sky2_wol_supported(sky2->hw);
2961 wol->wolopts = sky2->wol;
2962}
2963
2964static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2965{
2966 struct sky2_port *sky2 = netdev_priv(dev);
2967 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2968
e3173832
SH		 2969 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2970 return -EOPNOTSUPP;
2971
2972 sky2->wol = wol->wolopts;
2973
05745c4a
SH		 2974 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2975 hw->chip_id == CHIP_ID_YUKON_EX ||
2976 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2977 sky2_write32(hw, B0_CTST, sky2->wol
2978 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2979
2980 if (!netif_running(dev))
2981 sky2_wol_init(sky2);
cd28ab6a
SH		 2982 return 0;
2983}
2984
28bd181a 2985static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2986{
b89165f2
SH		 2987 if (sky2_is_copper(hw)) {
2988 u32 modes = SUPPORTED_10baseT_Half
2989 | SUPPORTED_10baseT_Full
2990 | SUPPORTED_100baseT_Half
2991 | SUPPORTED_100baseT_Full
2992 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2993
ea76e635 2994 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 2995 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2996 | SUPPORTED_1000baseT_Full;
2997 return modes;
cd28ab6a 2998 } else
b89165f2
SH		 2999 return SUPPORTED_1000baseT_Half
3000 | SUPPORTED_1000baseT_Full
3001 | SUPPORTED_Autoneg
3002 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3003}
3004
793b883e 3005static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3006{
3007 struct sky2_port *sky2 = netdev_priv(dev);
3008 struct sky2_hw *hw = sky2->hw;
3009
3010 ecmd->transceiver = XCVR_INTERNAL;
3011 ecmd->supported = sky2_supported_modes(hw);
3012 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3013 if (sky2_is_copper(hw)) {
cd28ab6a 3014 ecmd->port = PORT_TP;
b89165f2
SH		 3015 ecmd->speed = sky2->speed;
3016 } else {
3017 ecmd->speed = SPEED_1000;
cd28ab6a 3018 ecmd->port = PORT_FIBRE;
b89165f2 3019 }
cd28ab6a
SH		 3020
3021 ecmd->advertising = sky2->advertising;
3022 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3023 ecmd->duplex = sky2->duplex;
3024 return 0;
3025}
3026
3027static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3028{
3029 struct sky2_port *sky2 = netdev_priv(dev);
3030 const struct sky2_hw *hw = sky2->hw;
3031 u32 supported = sky2_supported_modes(hw);
3032
3033 if (ecmd->autoneg == AUTONEG_ENABLE) {
3034 ecmd->advertising = supported;
3035 sky2->duplex = -1;
3036 sky2->speed = -1;
3037 } else {
3038 u32 setting;
3039
793b883e 3040 switch (ecmd->speed) {
cd28ab6a
SH		 3041 case SPEED_1000:
3042 if (ecmd->duplex == DUPLEX_FULL)
3043 setting = SUPPORTED_1000baseT_Full;
3044 else if (ecmd->duplex == DUPLEX_HALF)
3045 setting = SUPPORTED_1000baseT_Half;
3046 else
3047 return -EINVAL;
3048 break;
3049 case SPEED_100:
3050 if (ecmd->duplex == DUPLEX_FULL)
3051 setting = SUPPORTED_100baseT_Full;
3052 else if (ecmd->duplex == DUPLEX_HALF)
3053 setting = SUPPORTED_100baseT_Half;
3054 else
3055 return -EINVAL;
3056 break;
3057
3058 case SPEED_10:
3059 if (ecmd->duplex == DUPLEX_FULL)
3060 setting = SUPPORTED_10baseT_Full;
3061 else if (ecmd->duplex == DUPLEX_HALF)
3062 setting = SUPPORTED_10baseT_Half;
3063 else
3064 return -EINVAL;
3065 break;
3066 default:
3067 return -EINVAL;
3068 }
3069
3070 if ((setting & supported) == 0)
3071 return -EINVAL;
3072
3073 sky2->speed = ecmd->speed;
3074 sky2->duplex = ecmd->duplex;
3075 }
3076
3077 sky2->autoneg = ecmd->autoneg;
3078 sky2->advertising = ecmd->advertising;
3079
d1b139c0 3080 if (netif_running(dev)) {
1b537565 3081 sky2_phy_reinit(sky2);
d1b139c0
SH		 3082 sky2_set_multicast(dev);
3083 }
cd28ab6a
SH		 3084
3085 return 0;
3086}
3087
3088static void sky2_get_drvinfo(struct net_device *dev,
3089 struct ethtool_drvinfo *info)
3090{
3091 struct sky2_port *sky2 = netdev_priv(dev);
3092
3093 strcpy(info->driver, DRV_NAME);
3094 strcpy(info->version, DRV_VERSION);
3095 strcpy(info->fw_version, "N/A");
3096 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3097}
3098
3099static const struct sky2_stat {
793b883e
SH		 3100 char name[ETH_GSTRING_LEN];
3101 u16 offset;
cd28ab6a
SH		 3102} sky2_stats[] = {
3103 { "tx_bytes", GM_TXO_OK_HI },
3104 { "rx_bytes", GM_RXO_OK_HI },
3105 { "tx_broadcast", GM_TXF_BC_OK },
3106 { "rx_broadcast", GM_RXF_BC_OK },
3107 { "tx_multicast", GM_TXF_MC_OK },
3108 { "rx_multicast", GM_RXF_MC_OK },
3109 { "tx_unicast", GM_TXF_UC_OK },
3110 { "rx_unicast", GM_RXF_UC_OK },
3111 { "tx_mac_pause", GM_TXF_MPAUSE },
3112 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3113 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3114 { "late_collision",GM_TXF_LAT_COL },
3115 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3116 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3117 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3118
d2604540 3119 { "rx_short", GM_RXF_SHT },
cd28ab6a 3120 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3121 { "rx_64_byte_packets", GM_RXF_64B },
3122 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3123 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3124 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3125 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3126 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3127 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3128 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3129 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3130 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3131 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3132
3133 { "tx_64_byte_packets", GM_TXF_64B },
3134 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3135 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3136 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3137 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3138 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3139 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3140 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3141};
3142
cd28ab6a
SH		 3143static u32 sky2_get_rx_csum(struct net_device *dev)
3144{
3145 struct sky2_port *sky2 = netdev_priv(dev);
3146
3147 return sky2->rx_csum;
3148}
3149
3150static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3151{
3152 struct sky2_port *sky2 = netdev_priv(dev);
3153
3154 sky2->rx_csum = data;
793b883e 3155
cd28ab6a
SH		 3156 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3157 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3158
3159 return 0;
3160}
3161
3162static u32 sky2_get_msglevel(struct net_device *netdev)
3163{
3164 struct sky2_port *sky2 = netdev_priv(netdev);
3165 return sky2->msg_enable;
3166}
3167
9a7ae0a9
SH		 3168static int sky2_nway_reset(struct net_device *dev)
3169{
3170 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3171
16ad91e1 3172 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3173 return -EINVAL;
3174
1b537565 3175 sky2_phy_reinit(sky2);
d1b139c0 3176 sky2_set_multicast(dev);
9a7ae0a9
SH		 3177
3178 return 0;
3179}
3180
793b883e 3181static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3182{
3183 struct sky2_hw *hw = sky2->hw;
3184 unsigned port = sky2->port;
3185 int i;
3186
3187 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3188 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3189 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3190 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3191
793b883e 3192 for (i = 2; i < count; i++)
cd28ab6a
SH		 3193 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3194}
3195
cd28ab6a
SH		 3196static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3197{
3198 struct sky2_port *sky2 = netdev_priv(netdev);
3199 sky2->msg_enable = value;
3200}
3201
b9f2c044 3202static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3203{
b9f2c044
JG		 3204 switch (sset) {
3205 case ETH_SS_STATS:
3206 return ARRAY_SIZE(sky2_stats);
3207 default:
3208 return -EOPNOTSUPP;
3209 }
cd28ab6a
SH		 3210}
3211
3212static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3213 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3214{
3215 struct sky2_port *sky2 = netdev_priv(dev);
3216
793b883e 3217 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3218}
3219
793b883e 3220static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3221{
3222 int i;
3223
3224 switch (stringset) {
3225 case ETH_SS_STATS:
3226 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3227 memcpy(data + i * ETH_GSTRING_LEN,
3228 sky2_stats[i].name, ETH_GSTRING_LEN);
3229 break;
3230 }
3231}
3232
cd28ab6a
SH		 3233static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3234{
3235 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3236 return &sky2->net_stats;
3237}
3238
3239static int sky2_set_mac_address(struct net_device *dev, void *p)
3240{
3241 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3242 struct sky2_hw *hw = sky2->hw;
3243 unsigned port = sky2->port;
3244 const struct sockaddr *addr = p;
cd28ab6a
SH		 3245
3246 if (!is_valid_ether_addr(addr->sa_data))
3247 return -EADDRNOTAVAIL;
3248
cd28ab6a 3249 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3250 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3251 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3252 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3253 dev->dev_addr, ETH_ALEN);
1b537565 3254
a8ab1ec0
SH		 3255 /* virtual address for data */
3256 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3257
3258 /* physical address: used for pause frames */
3259 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3260
3261 return 0;
cd28ab6a
SH		 3262}
3263
a052b52f
SH		 3264static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3265{
3266 u32 bit;
3267
3268 bit = ether_crc(ETH_ALEN, addr) & 63;
3269 filter[bit >> 3] |= 1 << (bit & 7);
3270}
3271
cd28ab6a
SH		 3272static void sky2_set_multicast(struct net_device *dev)
3273{
3274 struct sky2_port *sky2 = netdev_priv(dev);
3275 struct sky2_hw *hw = sky2->hw;
3276 unsigned port = sky2->port;
3277 struct dev_mc_list *list = dev->mc_list;
3278 u16 reg;
3279 u8 filter[8];
a052b52f
SH		 3280 int rx_pause;
3281 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3282
a052b52f 3283 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3284 memset(filter, 0, sizeof(filter));
3285
3286 reg = gma_read16(hw, port, GM_RX_CTRL);
3287 reg |= GM_RXCR_UCF_ENA;
3288
d571b694 3289 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3290 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3291 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3292 memset(filter, 0xff, sizeof(filter));
a052b52f 3293 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3294 reg &= ~GM_RXCR_MCF_ENA;
3295 else {
3296 int i;
3297 reg |= GM_RXCR_MCF_ENA;
3298
a052b52f
SH		 3299 if (rx_pause)
3300 sky2_add_filter(filter, pause_mc_addr);
3301
3302 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3303 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3304 }
3305
cd28ab6a 3306 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3307 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3308 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3309 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3310 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3311 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3312 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3313 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3314
3315 gma_write16(hw, port, GM_RX_CTRL, reg);
3316}
3317
3318/* Can have one global because blinking is controlled by
3319 * ethtool and that is always under RTNL mutex
3320 */
91c86df5 3321static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3322{
793b883e
SH		 3323 u16 pg;
3324
793b883e
SH		 3325 switch (hw->chip_id) {
3326 case CHIP_ID_YUKON_XL:
3327 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3328 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3329 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3330 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3331 PHY_M_LEDC_INIT_CTRL(7) |
3332 PHY_M_LEDC_STA1_CTRL(7) |
3333 PHY_M_LEDC_STA0_CTRL(7))
3334 : 0);
3335
3336 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3337 break;
3338
3339 default:
3340 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3341 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3342 on ? PHY_M_LED_ALL : 0);
793b883e 3343 }
cd28ab6a
SH		 3344}
3345
3346/* blink LED's for finding board */
3347static int sky2_phys_id(struct net_device *dev, u32 data)
3348{
3349 struct sky2_port *sky2 = netdev_priv(dev);
3350 struct sky2_hw *hw = sky2->hw;
3351 unsigned port = sky2->port;
793b883e 3352 u16 ledctrl, ledover = 0;
cd28ab6a 3353 long ms;
91c86df5 3354 int interrupted;
cd28ab6a
SH		 3355 int onoff = 1;
3356
793b883e 3357 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3358 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3359 else
3360 ms = data * 1000;
3361
3362 /* save initial values */
e07b1aa8 3363 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3364 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3365 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3366 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3367 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3368 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3369 } else {
3370 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3371 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3372 }
cd28ab6a 3373
91c86df5
SH		 3374 interrupted = 0;
3375 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3376 sky2_led(hw, port, onoff);
3377 onoff = !onoff;
3378
e07b1aa8 3379 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3380 interrupted = msleep_interruptible(250);
e07b1aa8 3381 spin_lock_bh(&sky2->phy_lock);
91c86df5 3382
cd28ab6a
SH		 3383 ms -= 250;
3384 }
3385
3386 /* resume regularly scheduled programming */
793b883e
SH		 3387 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3388 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3389 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3391 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3392 } else {
3393 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3394 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3395 }
e07b1aa8 3396 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3397
3398 return 0;
3399}
3400
3401static void sky2_get_pauseparam(struct net_device *dev,
3402 struct ethtool_pauseparam *ecmd)
3403{
3404 struct sky2_port *sky2 = netdev_priv(dev);
3405
16ad91e1
SH		 3406 switch (sky2->flow_mode) {
3407 case FC_NONE:
3408 ecmd->tx_pause = ecmd->rx_pause = 0;
3409 break;
3410 case FC_TX:
3411 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3412 break;
3413 case FC_RX:
3414 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3415 break;
3416 case FC_BOTH:
3417 ecmd->tx_pause = ecmd->rx_pause = 1;
3418 }
3419
cd28ab6a
SH		 3420 ecmd->autoneg = sky2->autoneg;
3421}
3422
3423static int sky2_set_pauseparam(struct net_device *dev,
3424 struct ethtool_pauseparam *ecmd)
3425{
3426 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3427
3428 sky2->autoneg = ecmd->autoneg;
16ad91e1 3429 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3430
16ad91e1
SH		 3431 if (netif_running(dev))
3432 sky2_phy_reinit(sky2);
cd28ab6a 3433
2eaba1a2 3434 return 0;
cd28ab6a
SH		 3435}
3436
fb17358f
SH		 3437static int sky2_get_coalesce(struct net_device *dev,
3438 struct ethtool_coalesce *ecmd)
3439{
3440 struct sky2_port *sky2 = netdev_priv(dev);
3441 struct sky2_hw *hw = sky2->hw;
3442
3443 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3444 ecmd->tx_coalesce_usecs = 0;
3445 else {
3446 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3447 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3448 }
3449 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3450
3451 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3452 ecmd->rx_coalesce_usecs = 0;
3453 else {
3454 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3455 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3456 }
3457 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3458
3459 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3460 ecmd->rx_coalesce_usecs_irq = 0;
3461 else {
3462 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3463 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3464 }
3465
3466 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3467
3468 return 0;
3469}
3470
3471/* Note: this affect both ports */
3472static int sky2_set_coalesce(struct net_device *dev,
3473 struct ethtool_coalesce *ecmd)
3474{
3475 struct sky2_port *sky2 = netdev_priv(dev);
3476 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3477 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3478
77b3d6a2
SH		 3479 if (ecmd->tx_coalesce_usecs > tmax ||
3480 ecmd->rx_coalesce_usecs > tmax ||
3481 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3482 return -EINVAL;
3483
ff81fbbe 3484 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3485 return -EINVAL;
ff81fbbe 3486 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3487 return -EINVAL;
ff81fbbe 3488 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3489 return -EINVAL;
3490
3491 if (ecmd->tx_coalesce_usecs == 0)
3492 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3493 else {
3494 sky2_write32(hw, STAT_TX_TIMER_INI,
3495 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3496 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3497 }
3498 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3499
3500 if (ecmd->rx_coalesce_usecs == 0)
3501 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3502 else {
3503 sky2_write32(hw, STAT_LEV_TIMER_INI,
3504 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3505 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3506 }
3507 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3508
3509 if (ecmd->rx_coalesce_usecs_irq == 0)
3510 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3511 else {
d28d4870 3512 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3513 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3514 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3515 }
3516 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3517 return 0;
3518}
3519
793b883e
SH		 3520static void sky2_get_ringparam(struct net_device *dev,
3521 struct ethtool_ringparam *ering)
3522{
3523 struct sky2_port *sky2 = netdev_priv(dev);
3524
3525 ering->rx_max_pending = RX_MAX_PENDING;
3526 ering->rx_mini_max_pending = 0;
3527 ering->rx_jumbo_max_pending = 0;
3528 ering->tx_max_pending = TX_RING_SIZE - 1;
3529
3530 ering->rx_pending = sky2->rx_pending;
3531 ering->rx_mini_pending = 0;
3532 ering->rx_jumbo_pending = 0;
3533 ering->tx_pending = sky2->tx_pending;
3534}
3535
3536static int sky2_set_ringparam(struct net_device *dev,
3537 struct ethtool_ringparam *ering)
3538{
3539 struct sky2_port *sky2 = netdev_priv(dev);
3540 int err = 0;
3541
3542 if (ering->rx_pending > RX_MAX_PENDING ||
3543 ering->rx_pending < 8 ||
3544 ering->tx_pending < MAX_SKB_TX_LE ||
3545 ering->tx_pending > TX_RING_SIZE - 1)
3546 return -EINVAL;
3547
3548 if (netif_running(dev))
3549 sky2_down(dev);
3550
3551 sky2->rx_pending = ering->rx_pending;
3552 sky2->tx_pending = ering->tx_pending;
3553
1b537565 3554 if (netif_running(dev)) {
793b883e 3555 err = sky2_up(dev);
1b537565
SH		 3556 if (err)
3557 dev_close(dev);
6ed995bb
SH		 3558 else
3559 sky2_set_multicast(dev);
1b537565 3560 }
793b883e
SH		 3561
3562 return err;
3563}
3564
793b883e
SH		 3565static int sky2_get_regs_len(struct net_device *dev)
3566{
6e4cbb34 3567 return 0x4000;
793b883e
SH		 3568}
3569
3570/*
3571 * Returns copy of control register region
3ead5db7 3572 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3573 */
3574static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3575 void *p)
3576{
3577 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3578 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3579
3580 regs->version = 1;
6e4cbb34 3581 memset(p, 0, regs->len);
793b883e 3582
6e4cbb34
SH		 3583 memcpy_fromio(p, io, B3_RAM_ADDR);
3584
3ead5db7
SH		 3585 /* skip diagnostic ram region */
3586 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3587
3588 /* copy GMAC registers */
3589 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3590 if (sky2->hw->ports > 1)
3591 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3592
793b883e 3593}
cd28ab6a 3594
b628ed98
SH		 3595/* In order to do Jumbo packets on these chips, need to turn off the
3596 * transmit store/forward. Therefore checksum offload won't work.
3597 */
3598static int no_tx_offload(struct net_device *dev)
3599{
3600 const struct sky2_port *sky2 = netdev_priv(dev);
3601 const struct sky2_hw *hw = sky2->hw;
3602
69161611 3603 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3604}
3605
3606static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3607{
3608 if (data && no_tx_offload(dev))
3609 return -EINVAL;
3610
3611 return ethtool_op_set_tx_csum(dev, data);
3612}
3613
3614
3615static int sky2_set_tso(struct net_device *dev, u32 data)
3616{
3617 if (data && no_tx_offload(dev))
3618 return -EINVAL;
3619
3620 return ethtool_op_set_tso(dev, data);
3621}
3622
f4331a6d
SH		 3623static int sky2_get_eeprom_len(struct net_device *dev)
3624{
3625 struct sky2_port *sky2 = netdev_priv(dev);
3626 u16 reg2;
3627
167f53d0 3628 pci_read_config_word(sky2->hw->pdev, PCI_DEV_REG2, &reg2);
f4331a6d
SH		 3629 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3630}
3631
167f53d0 3632static u32 sky2_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
f4331a6d 3633{
167f53d0 3634 u32 val;
f4331a6d 3635
167f53d0
SH		 3636 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
3637
3638 do {
3639 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3640 } while (!(offset & PCI_VPD_ADDR_F));
3641
3642 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
3643 return val;
f4331a6d
SH		 3644}
3645
167f53d0 3646static void sky2_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
f4331a6d 3647{
167f53d0
SH		 3648 pci_write_config_word(pdev, cap + PCI_VPD_DATA, val);
3649 pci_write_config_dword(pdev, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3650 do {
167f53d0
SH		 3651 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3652 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3653}
3654
3655static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3656 u8 *data)
3657{
3658 struct sky2_port *sky2 = netdev_priv(dev);
3659 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3660 int length = eeprom->len;
3661 u16 offset = eeprom->offset;
3662
3663 if (!cap)
3664 return -EINVAL;
3665
3666 eeprom->magic = SKY2_EEPROM_MAGIC;
3667
3668 while (length > 0) {
167f53d0 3669 u32 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
f4331a6d
SH		 3670 int n = min_t(int, length, sizeof(val));
3671
3672 memcpy(data, &val, n);
3673 length -= n;
3674 data += n;
3675 offset += n;
3676 }
3677 return 0;
3678}
3679
3680static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3681 u8 *data)
3682{
3683 struct sky2_port *sky2 = netdev_priv(dev);
3684 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3685 int length = eeprom->len;
3686 u16 offset = eeprom->offset;
3687
3688 if (!cap)
3689 return -EINVAL;
3690
3691 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3692 return -EINVAL;
3693
3694 while (length > 0) {
3695 u32 val;
3696 int n = min_t(int, length, sizeof(val));
3697
3698 if (n < sizeof(val))
167f53d0 3699 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
f4331a6d
SH		 3700 memcpy(&val, data, n);
3701
167f53d0 3702 sky2_vpd_write(sky2->hw->pdev, cap, offset, val);
f4331a6d
SH		 3703
3704 length -= n;
3705 data += n;
3706 offset += n;
3707 }
3708 return 0;
3709}
3710
3711
7282d491 3712static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3713 .get_settings = sky2_get_settings,
3714 .set_settings = sky2_set_settings,
3715 .get_drvinfo = sky2_get_drvinfo,
3716 .get_wol = sky2_get_wol,
3717 .set_wol = sky2_set_wol,
3718 .get_msglevel = sky2_get_msglevel,
3719 .set_msglevel = sky2_set_msglevel,
3720 .nway_reset = sky2_nway_reset,
3721 .get_regs_len = sky2_get_regs_len,
3722 .get_regs = sky2_get_regs,
3723 .get_link = ethtool_op_get_link,
3724 .get_eeprom_len = sky2_get_eeprom_len,
3725 .get_eeprom = sky2_get_eeprom,
3726 .set_eeprom = sky2_set_eeprom,
f4331a6d 3727 .set_sg = ethtool_op_set_sg,
f4331a6d 3728 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3729 .set_tso = sky2_set_tso,
3730 .get_rx_csum = sky2_get_rx_csum,
3731 .set_rx_csum = sky2_set_rx_csum,
3732 .get_strings = sky2_get_strings,
3733 .get_coalesce = sky2_get_coalesce,
3734 .set_coalesce = sky2_set_coalesce,
3735 .get_ringparam = sky2_get_ringparam,
3736 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3737 .get_pauseparam = sky2_get_pauseparam,
3738 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3739 .phys_id = sky2_phys_id,
b9f2c044 3740 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3741 .get_ethtool_stats = sky2_get_ethtool_stats,
3742};
3743
3cf26753
SH		 3744#ifdef CONFIG_SKY2_DEBUG
3745
3746static struct dentry *sky2_debug;
3747
3748static int sky2_debug_show(struct seq_file *seq, void *v)
3749{
3750 struct net_device *dev = seq->private;
3751 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3752 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3753 unsigned port = sky2->port;
3754 unsigned idx, last;
3755 int sop;
3756
3757 if (!netif_running(dev))
3758 return -ENETDOWN;
3759
3760 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3761 sky2_read32(hw, B0_ISRC),
3762 sky2_read32(hw, B0_IMSK),
3763 sky2_read32(hw, B0_Y2_SP_ICR));
3764
bea3348e 3765 napi_disable(&hw->napi);
3cf26753
SH		 3766 last = sky2_read16(hw, STAT_PUT_IDX);
3767
3768 if (hw->st_idx == last)
3769 seq_puts(seq, "Status ring (empty)\n");
3770 else {
3771 seq_puts(seq, "Status ring\n");
3772 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3773 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3774 const struct sky2_status_le *le = hw->st_le + idx;
3775 seq_printf(seq, "[%d] %#x %d %#x\n",
3776 idx, le->opcode, le->length, le->status);
3777 }
3778 seq_puts(seq, "\n");
3779 }
3780
3781 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3782 sky2->tx_cons, sky2->tx_prod,
3783 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3784 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3785
3786 /* Dump contents of tx ring */
3787 sop = 1;
3788 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3789 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3790 const struct sky2_tx_le *le = sky2->tx_le + idx;
3791 u32 a = le32_to_cpu(le->addr);
3792
3793 if (sop)
3794 seq_printf(seq, "%u:", idx);
3795 sop = 0;
3796
3797 switch(le->opcode & ~HW_OWNER) {
3798 case OP_ADDR64:
3799 seq_printf(seq, " %#x:", a);
3800 break;
3801 case OP_LRGLEN:
3802 seq_printf(seq, " mtu=%d", a);
3803 break;
3804 case OP_VLAN:
3805 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3806 break;
3807 case OP_TCPLISW:
3808 seq_printf(seq, " csum=%#x", a);
3809 break;
3810 case OP_LARGESEND:
3811 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3812 break;
3813 case OP_PACKET:
3814 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3815 break;
3816 case OP_BUFFER:
3817 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3818 break;
3819 default:
3820 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3821 a, le16_to_cpu(le->length));
3822 }
3823
3824 if (le->ctrl & EOP) {
3825 seq_putc(seq, '\n');
3826 sop = 1;
3827 }
3828 }
3829
3830 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3831 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3832 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3833 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3834
bea3348e 3835 napi_enable(&hw->napi);
3cf26753
SH		 3836 return 0;
3837}
3838
3839static int sky2_debug_open(struct inode *inode, struct file *file)
3840{
3841 return single_open(file, sky2_debug_show, inode->i_private);
3842}
3843
3844static const struct file_operations sky2_debug_fops = {
3845 .owner = THIS_MODULE,
3846 .open = sky2_debug_open,
3847 .read = seq_read,
3848 .llseek = seq_lseek,
3849 .release = single_release,
3850};
3851
3852/*
3853 * Use network device events to create/remove/rename
3854 * debugfs file entries
3855 */
3856static int sky2_device_event(struct notifier_block *unused,
3857 unsigned long event, void *ptr)
3858{
3859 struct net_device *dev = ptr;
5b296bc9 3860 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3861
5b296bc9
SH		 3862 if (dev->open != sky2_up || !sky2_debug)
3863 return NOTIFY_DONE;
3cf26753 3864
5b296bc9
SH		 3865 switch(event) {
3866 case NETDEV_CHANGENAME:
3867 if (sky2->debugfs) {
3868 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3869 sky2_debug, dev->name);
3870 }
3871 break;
3cf26753 3872
5b296bc9
SH		 3873 case NETDEV_GOING_DOWN:
3874 if (sky2->debugfs) {
3875 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3876 dev->name);
3877 debugfs_remove(sky2->debugfs);
3878 sky2->debugfs = NULL;
3cf26753 3879 }
5b296bc9
SH		 3880 break;
3881
3882 case NETDEV_UP:
3883 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3884 sky2_debug, dev,
3885 &sky2_debug_fops);
3886 if (IS_ERR(sky2->debugfs))
3887 sky2->debugfs = NULL;
3cf26753
SH		 3888 }
3889
3890 return NOTIFY_DONE;
3891}
3892
3893static struct notifier_block sky2_notifier = {
3894 .notifier_call = sky2_device_event,
3895};
3896
3897
3898static __init void sky2_debug_init(void)
3899{
3900 struct dentry *ent;
3901
3902 ent = debugfs_create_dir("sky2", NULL);
3903 if (!ent || IS_ERR(ent))
3904 return;
3905
3906 sky2_debug = ent;
3907 register_netdevice_notifier(&sky2_notifier);
3908}
3909
3910static __exit void sky2_debug_cleanup(void)
3911{
3912 if (sky2_debug) {
3913 unregister_netdevice_notifier(&sky2_notifier);
3914 debugfs_remove(sky2_debug);
3915 sky2_debug = NULL;
3916 }
3917}
3918
3919#else
3920#define sky2_debug_init()
3921#define sky2_debug_cleanup()
3922#endif
3923
3924
cd28ab6a
SH		 3925/* Initialize network device */
3926static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3927 unsigned port,
3928 int highmem, int wol)
cd28ab6a
SH		 3929{
3930 struct sky2_port *sky2;
3931 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3932
3933 if (!dev) {
b02a9258 3934 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3935 return NULL;
3936 }
3937
cd28ab6a 3938 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3939 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3940 dev->open = sky2_up;
3941 dev->stop = sky2_down;
ef743d33 3942 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3943 dev->hard_start_xmit = sky2_xmit_frame;
3944 dev->get_stats = sky2_get_stats;
3945 dev->set_multicast_list = sky2_set_multicast;
3946 dev->set_mac_address = sky2_set_mac_address;
3947 dev->change_mtu = sky2_change_mtu;
3948 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3949 dev->tx_timeout = sky2_tx_timeout;
3950 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 3951#ifdef CONFIG_NET_POLL_CONTROLLER
bea3348e 3952 dev->poll_controller = sky2_netpoll;
cd28ab6a 3953#endif
cd28ab6a
SH		 3954
3955 sky2 = netdev_priv(dev);
3956 sky2->netdev = dev;
3957 sky2->hw = hw;
3958 sky2->msg_enable = netif_msg_init(debug, default_msg);
3959
cd28ab6a
SH		 3960 /* Auto speed and flow control */
3961 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3962 sky2->flow_mode = FC_BOTH;
3963
cd28ab6a
SH		 3964 sky2->duplex = -1;
3965 sky2->speed = -1;
3966 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3967 sky2->rx_csum = 1;
e3173832 3968 sky2->wol = wol;
75d070c5 3969
e07b1aa8 3970 spin_lock_init(&sky2->phy_lock);
793b883e 3971 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3972 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3973
3974 hw->dev[port] = dev;
3975
3976 sky2->port = port;
3977
4a50a876 3978 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3979 if (highmem)
3980 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3981
d1f13708 3982#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 3983 /* The workaround for FE+ status conflicts with VLAN tag detection. */
3984 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
3985 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
3986 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3987 dev->vlan_rx_register = sky2_vlan_rx_register;
3988 }
d1f13708 3989#endif
3990
cd28ab6a 3991 /* read the mac address */
793b883e 3992 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3993 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3994
cd28ab6a
SH		 3995 return dev;
3996}
3997
28bd181a 3998static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3999{
4000 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4001 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4002
4003 if (netif_msg_probe(sky2))
0795af57
JP		 4004 printk(KERN_INFO PFX "%s: addr %s\n",
4005 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4006}
4007
fb2690a9 4008/* Handle software interrupt used during MSI test */
7d12e780 4009static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4010{
4011 struct sky2_hw *hw = dev_id;
4012 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4013
4014 if (status == 0)
4015 return IRQ_NONE;
4016
4017 if (status & Y2_IS_IRQ_SW) {
ea76e635 4018 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4019 wake_up(&hw->msi_wait);
4020 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4021 }
4022 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4023
4024 return IRQ_HANDLED;
4025}
4026
4027/* Test interrupt path by forcing a a software IRQ */
4028static int __devinit sky2_test_msi(struct sky2_hw *hw)
4029{
4030 struct pci_dev *pdev = hw->pdev;
4031 int err;
4032
bb507fe1 4033 init_waitqueue_head (&hw->msi_wait);
4034
fb2690a9
SH		 4035 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4036
b0a20ded 4037 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4038 if (err) {
b02a9258 4039 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4040 return err;
4041 }
4042
fb2690a9 4043 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4044 sky2_read8(hw, B0_CTST);
fb2690a9 4045
ea76e635 4046 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4047
ea76e635 4048 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4049 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4050 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4051 "switching to INTx mode.\n");
fb2690a9
SH		 4052
4053 err = -EOPNOTSUPP;
4054 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4055 }
4056
4057 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4058 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4059
4060 free_irq(pdev->irq, hw);
4061
4062 return err;
4063}
4064
e3173832
SH		 4065static int __devinit pci_wake_enabled(struct pci_dev *dev)
4066{
4067 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4068 u16 value;
4069
4070 if (!pm)
4071 return 0;
4072 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4073 return 0;
4074 return value & PCI_PM_CTRL_PME_ENABLE;
4075}
4076
cd28ab6a
SH		 4077static int __devinit sky2_probe(struct pci_dev *pdev,
4078 const struct pci_device_id *ent)
4079{
7f60c64b 4080 struct net_device *dev;
cd28ab6a 4081 struct sky2_hw *hw;
e3173832 4082 int err, using_dac = 0, wol_default;
cd28ab6a 4083
793b883e
SH		 4084 err = pci_enable_device(pdev);
4085 if (err) {
b02a9258 4086 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4087 goto err_out;
4088 }
4089
793b883e
SH		 4090 err = pci_request_regions(pdev, DRV_NAME);
4091 if (err) {
b02a9258 4092 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4093 goto err_out_disable;
cd28ab6a
SH		 4094 }
4095
4096 pci_set_master(pdev);
4097
d1f3d4dd
SH		 4098 if (sizeof(dma_addr_t) > sizeof(u32) &&
4099 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4100 using_dac = 1;
4101 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4102 if (err < 0) {
b02a9258
SH		 4103 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4104 "for consistent allocations\n");
d1f3d4dd
SH		 4105 goto err_out_free_regions;
4106 }
d1f3d4dd 4107 } else {
cd28ab6a
SH		 4108 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4109 if (err) {
b02a9258 4110 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4111 goto err_out_free_regions;
4112 }
4113 }
d1f3d4dd 4114
e3173832
SH		 4115 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4116
cd28ab6a 4117 err = -ENOMEM;
6aad85d6 4118 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4119 if (!hw) {
b02a9258 4120 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4121 goto err_out_free_regions;
4122 }
4123
cd28ab6a 4124 hw->pdev = pdev;
cd28ab6a
SH		 4125
4126 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4127 if (!hw->regs) {
b02a9258 4128 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4129 goto err_out_free_hw;
4130 }
4131
56a645cc 4132#ifdef __BIG_ENDIAN
f65b138c
SH		 4133 /* The sk98lin vendor driver uses hardware byte swapping but
4134 * this driver uses software swapping.
4135 */
56a645cc
SH		 4136 {
4137 u32 reg;
167f53d0 4138 pci_read_config_dword(pdev,PCI_DEV_REG2, &reg);
f65b138c 4139 reg &= ~PCI_REV_DESC;
167f53d0 4140 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
56a645cc
SH		 4141 }
4142#endif
4143
08c06d8a 4144 /* ring for status responses */
167f53d0 4145 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4146 if (!hw->st_le)
4147 goto err_out_iounmap;
4148
e3173832 4149 err = sky2_init(hw);
cd28ab6a 4150 if (err)
793b883e 4151 goto err_out_iounmap;
cd28ab6a 4152
b02a9258 4153 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4154 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4155 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4156 hw->chip_id, hw->chip_rev);
cd28ab6a 4157
e3173832
SH		 4158 sky2_reset(hw);
4159
4160 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4161 if (!dev) {
4162 err = -ENOMEM;
cd28ab6a 4163 goto err_out_free_pci;
7f60c64b 4164 }
bea3348e 4165 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
cd28ab6a 4166
9fa1b1f3
SH		 4167 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4168 err = sky2_test_msi(hw);
4169 if (err == -EOPNOTSUPP)
4170 pci_disable_msi(pdev);
4171 else if (err)
4172 goto err_out_free_netdev;
4173 }
4174
793b883e
SH		 4175 err = register_netdev(dev);
4176 if (err) {
b02a9258 4177 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4178 goto err_out_free_netdev;
4179 }
4180
ea76e635
SH		 4181 err = request_irq(pdev->irq, sky2_intr,
4182 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4183 dev->name, hw);
9fa1b1f3 4184 if (err) {
b02a9258 4185 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4186 goto err_out_unregister;
4187 }
4188 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4189
cd28ab6a
SH		 4190 sky2_show_addr(dev);
4191
7f60c64b 4192 if (hw->ports > 1) {
4193 struct net_device *dev1;
4194
e3173832 4195 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4196 if (!dev1)
4197 dev_warn(&pdev->dev, "allocation for second device failed\n");
4198 else if ((err = register_netdev(dev1))) {
4199 dev_warn(&pdev->dev,
4200 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4201 hw->dev[1] = NULL;
4202 free_netdev(dev1);
b02a9258
SH		 4203 } else
4204 sky2_show_addr(dev1);
cd28ab6a
SH		 4205 }
4206
32c2c300 4207 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4208 INIT_WORK(&hw->restart_work, sky2_restart);
4209
793b883e
SH		 4210 pci_set_drvdata(pdev, hw);
4211
cd28ab6a
SH		 4212 return 0;
4213
793b883e 4214err_out_unregister:
ea76e635 4215 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4216 pci_disable_msi(pdev);
793b883e 4217 unregister_netdev(dev);
cd28ab6a
SH		 4218err_out_free_netdev:
4219 free_netdev(dev);
cd28ab6a 4220err_out_free_pci:
793b883e 4221 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4222 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4223err_out_iounmap:
4224 iounmap(hw->regs);
4225err_out_free_hw:
4226 kfree(hw);
4227err_out_free_regions:
4228 pci_release_regions(pdev);
44a1d2e5 4229err_out_disable:
cd28ab6a 4230 pci_disable_device(pdev);
cd28ab6a 4231err_out:
549a68c3 4232 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4233 return err;
4234}
4235
4236static void __devexit sky2_remove(struct pci_dev *pdev)
4237{
793b883e 4238 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 4239 struct net_device *dev0, *dev1;
4240
793b883e 4241 if (!hw)
cd28ab6a
SH		 4242 return;
4243
32c2c300 4244 del_timer_sync(&hw->watchdog_timer);
d27ed387 4245
81906791
SH		 4246 flush_scheduled_work();
4247
d27ed387 4248 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 4249 synchronize_irq(hw->pdev->irq);
4250
cd28ab6a 4251 dev0 = hw->dev[0];
793b883e
SH		 4252 dev1 = hw->dev[1];
4253 if (dev1)
4254 unregister_netdev(dev1);
cd28ab6a
SH		 4255 unregister_netdev(dev0);
4256
ae306cca
SH		 4257 sky2_power_aux(hw);
4258
cd28ab6a 4259 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4260 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4261 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4262
4263 free_irq(pdev->irq, hw);
ea76e635 4264 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4265 pci_disable_msi(pdev);
793b883e 4266 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4267 pci_release_regions(pdev);
4268 pci_disable_device(pdev);
793b883e 4269
cd28ab6a
SH		 4270 if (dev1)
4271 free_netdev(dev1);
4272 free_netdev(dev0);
4273 iounmap(hw->regs);
4274 kfree(hw);
5afa0a9c 4275
cd28ab6a
SH		 4276 pci_set_drvdata(pdev, NULL);
4277}
4278
4279#ifdef CONFIG_PM
4280static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4281{
793b883e 4282 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4283 int i, wol = 0;
cd28ab6a 4284
549a68c3
SH		 4285 if (!hw)
4286 return 0;
4287
f05267e7 4288 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4289 struct net_device *dev = hw->dev[i];
e3173832 4290 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4291
e3173832 4292 if (netif_running(dev))
5afa0a9c 4293 sky2_down(dev);
e3173832
SH		 4294
4295 if (sky2->wol)
4296 sky2_wol_init(sky2);
4297
4298 wol |= sky2->wol;
cd28ab6a
SH		 4299 }
4300
8ab8fca2 4301 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4302 sky2_power_aux(hw);
e3173832 4303
d374c1c1 4304 pci_save_state(pdev);
e3173832 4305 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4306 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4307
2ccc99b7 4308 return 0;
cd28ab6a
SH		 4309}
4310
4311static int sky2_resume(struct pci_dev *pdev)
4312{
793b883e 4313 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4314 int i, err;
cd28ab6a 4315
549a68c3
SH		 4316 if (!hw)
4317 return 0;
4318
ae306cca
SH		 4319 err = pci_set_power_state(pdev, PCI_D0);
4320 if (err)
4321 goto out;
4322
4323 err = pci_restore_state(pdev);
4324 if (err)
4325 goto out;
4326
cd28ab6a 4327 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4328
4329 /* Re-enable all clocks */
05745c4a
SH		 4330 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4331 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4332 hw->chip_id == CHIP_ID_YUKON_FE_P)
167f53d0 4333 pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
1ad5b4a5 4334
e3173832 4335 sky2_reset(hw);
cd28ab6a 4336
8ab8fca2
SH		 4337 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4338
f05267e7 4339 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4340 struct net_device *dev = hw->dev[i];
6a5706b9 4341 if (netif_running(dev)) {
08c06d8a
SH		 4342 err = sky2_up(dev);
4343 if (err) {
4344 printk(KERN_ERR PFX "%s: could not up: %d\n",
4345 dev->name, err);
4346 dev_close(dev);
eb35cf60 4347 goto out;
5afa0a9c 4348 }
d1b139c0
SH		 4349
4350 sky2_set_multicast(dev);
cd28ab6a
SH		 4351 }
4352 }
eb35cf60 4353
ae306cca 4354 return 0;
08c06d8a 4355out:
b02a9258 4356 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4357 pci_disable_device(pdev);
08c06d8a 4358 return err;
cd28ab6a
SH		 4359}
4360#endif
4361
e3173832
SH		 4362static void sky2_shutdown(struct pci_dev *pdev)
4363{
4364 struct sky2_hw *hw = pci_get_drvdata(pdev);
4365 int i, wol = 0;
4366
549a68c3
SH		 4367 if (!hw)
4368 return;
4369
bea3348e 4370 napi_disable(&hw->napi);
e3173832
SH		 4371
4372 for (i = 0; i < hw->ports; i++) {
4373 struct net_device *dev = hw->dev[i];
4374 struct sky2_port *sky2 = netdev_priv(dev);
4375
4376 if (sky2->wol) {
4377 wol = 1;
4378 sky2_wol_init(sky2);
4379 }
4380 }
4381
4382 if (wol)
4383 sky2_power_aux(hw);
4384
4385 pci_enable_wake(pdev, PCI_D3hot, wol);
4386 pci_enable_wake(pdev, PCI_D3cold, wol);
4387
4388 pci_disable_device(pdev);
4389 pci_set_power_state(pdev, PCI_D3hot);
4390
4391}
4392
cd28ab6a 4393static struct pci_driver sky2_driver = {
793b883e
SH		 4394 .name = DRV_NAME,
4395 .id_table = sky2_id_table,
4396 .probe = sky2_probe,
4397 .remove = __devexit_p(sky2_remove),
cd28ab6a 4398#ifdef CONFIG_PM
793b883e
SH		 4399 .suspend = sky2_suspend,
4400 .resume = sky2_resume,
cd28ab6a 4401#endif
e3173832 4402 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4403};
4404
4405static int __init sky2_init_module(void)
4406{
3cf26753 4407 sky2_debug_init();
50241c4c 4408 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4409}
4410
4411static void __exit sky2_cleanup_module(void)
4412{
4413 pci_unregister_driver(&sky2_driver);
3cf26753 4414 sky2_debug_cleanup();
cd28ab6a
SH		 4415}
4416
4417module_init(sky2_init_module);
4418module_exit(sky2_cleanup_module);
4419
4420MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4421MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4422MODULE_LICENSE("GPL");
5f4f9dc1 4423MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)