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sky2: jumbo packet changes
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
ac958154 53#define DRV_VERSION "1.26"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 66
ee5f68fe 67/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 71#define TX_MAX_PENDING 4096
72#define TX_DEF_PENDING 127
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 144 { 0 }
145};
793b883e 146
cd28ab6a
SH		 147MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149/* Avoid conditionals by using array */
150static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 152static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 153
d1b139c0
SH		 154static void sky2_set_multicast(struct net_device *dev);
155
af043aa5 156/* Access to PHY via serial interconnect */
ef743d33 157static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 158{
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
167 if (ctrl == 0xffff)
168 goto io_error;
169
170 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 171 return 0;
af043aa5
SH		 172
173 udelay(10);
cd28ab6a 174 }
ef743d33 175
af043aa5 176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 177 return -ETIMEDOUT;
af043aa5
SH		 178
179io_error:
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
181 return -EIO;
cd28ab6a
SH		 182}
183
ef743d33 184static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 185{
186 int i;
187
793b883e 188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
190
191 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
193 if (ctrl == 0xffff)
194 goto io_error;
195
196 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 197 *val = gma_read16(hw, port, GM_SMI_DATA);
198 return 0;
199 }
200
af043aa5 201 udelay(10);
cd28ab6a
SH		 202 }
203
af043aa5 204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 205 return -ETIMEDOUT;
af043aa5
SH		 206io_error:
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
208 return -EIO;
ef743d33 209}
210
af043aa5 211static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 212{
213 u16 v;
af043aa5 214 __gm_phy_read(hw, port, reg, &v);
ef743d33 215 return v;
cd28ab6a
SH		 216}
217
5afa0a9c 218
ae306cca
SH		 219static void sky2_power_on(struct sky2_hw *hw)
220{
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 224
ae306cca
SH		 225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 227
ae306cca
SH		 228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
234 else
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 236
ea76e635 237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 238 u32 reg;
5afa0a9c 239
b32f40c4 240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 241
b32f40c4 242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 246
b32f40c4 247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 251
b32f40c4 252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 253
5f8ae5c5 254 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
255
8f70920f
SH		 256 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
257 reg = sky2_read32(hw, B2_GP_IO);
258 reg |= GLB_GPIO_STAT_RACE_DIS;
259 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 260
261 sky2_read32(hw, B2_GP_IO);
5afa0a9c 262 }
10547ae2
SH		 263
264 /* Turn on "driver loaded" LED */
265 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 266}
5afa0a9c 267
ae306cca
SH		 268static void sky2_power_aux(struct sky2_hw *hw)
269{
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
272 else
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
278
c23ddf8f
SH		 279 /* switch power to VAUX if supported and PME from D3cold */
280 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
281 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 285
286 /* turn off "driver loaded LED" */
287 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c 288}
289
d3bcfbeb 290static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 291{
292 u16 reg;
293
294 /* disable all GMAC IRQ's */
295 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 296
cd28ab6a
SH		 297 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
298 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
301
302 reg = gma_read16(hw, port, GM_RX_CTRL);
303 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
304 gma_write16(hw, port, GM_RX_CTRL, reg);
305}
306
16ad91e1
SH		 307/* flow control to advertise bits */
308static const u16 copper_fc_adv[] = {
309 [FC_NONE] = 0,
310 [FC_TX] = PHY_M_AN_ASP,
311 [FC_RX] = PHY_M_AN_PC,
312 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
313};
314
315/* flow control to advertise bits when using 1000BaseX */
316static const u16 fiber_fc_adv[] = {
df3fe1f3 317 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 318 [FC_TX] = PHY_M_P_ASYM_MD_X,
319 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 320 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 321};
322
323/* flow control to GMA disable bits */
324static const u16 gm_fc_disable[] = {
325 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
326 [FC_TX] = GM_GPCR_FC_RX_DIS,
327 [FC_RX] = GM_GPCR_FC_TX_DIS,
328 [FC_BOTH] = 0,
329};
330
331
cd28ab6a
SH		 332static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
333{
334 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 335 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 336
0ea065e5 337 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 338 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 339 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
340
341 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 342 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 343 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
344
53419c68 345 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 346 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 347 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 348 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
349 else
53419c68
SH		 350 /* set master & slave downshift counter to 1x */
351 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 352
353 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
354 }
355
356 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 357 if (sky2_is_copper(hw)) {
05745c4a 358 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 359 /* enable automatic crossover */
360 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 361
362 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
363 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
364 u16 spec;
365
366 /* Enable Class A driver for FE+ A0 */
367 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
368 spec |= PHY_M_FESC_SEL_CL_A;
369 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
370 }
cd28ab6a
SH		 371 } else {
372 /* disable energy detect */
373 ctrl &= ~PHY_M_PC_EN_DET_MSK;
374
375 /* enable automatic crossover */
376 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
377
53419c68 378 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 379 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
380 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 381 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 382 ctrl &= ~PHY_M_PC_DSC_MSK;
383 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
384 }
385 }
cd28ab6a
SH		 386 } else {
387 /* workaround for deviation #4.88 (CRC errors) */
388 /* disable Automatic Crossover */
389
390 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 391 }
cd28ab6a 392
b89165f2
SH		 393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
394
395 /* special setup for PHY 88E1112 Fiber */
ea76e635 396 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 397 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 398
b89165f2
SH		 399 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
400 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
401 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
402 ctrl &= ~PHY_M_MAC_MD_MSK;
403 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
404 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
405
406 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 407 /* select page 1 to access Fiber registers */
408 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 409
410 /* for SFP-module set SIGDET polarity to low */
411 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
412 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 413 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 414 }
b89165f2
SH		 415
416 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 417 }
418
7800fddc 419 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 420 ct1000 = 0;
421 adv = PHY_AN_CSMA;
2eaba1a2 422 reg = 0;
cd28ab6a 423
0ea065e5 424 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 425 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 426 if (sky2->advertising & ADVERTISED_1000baseT_Full)
427 ct1000 |= PHY_M_1000C_AFD;
428 if (sky2->advertising & ADVERTISED_1000baseT_Half)
429 ct1000 |= PHY_M_1000C_AHD;
430 if (sky2->advertising & ADVERTISED_100baseT_Full)
431 adv |= PHY_M_AN_100_FD;
432 if (sky2->advertising & ADVERTISED_100baseT_Half)
433 adv |= PHY_M_AN_100_HD;
434 if (sky2->advertising & ADVERTISED_10baseT_Full)
435 adv |= PHY_M_AN_10_FD;
436 if (sky2->advertising & ADVERTISED_10baseT_Half)
437 adv |= PHY_M_AN_10_HD;
709c6e7b 438
b89165f2
SH		 439 } else { /* special defines for FIBER (88E1040S only) */
440 if (sky2->advertising & ADVERTISED_1000baseT_Full)
441 adv |= PHY_M_AN_1000X_AFD;
442 if (sky2->advertising & ADVERTISED_1000baseT_Half)
443 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 444 }
cd28ab6a
SH		 445
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
448 } else {
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
451
0ea065e5
SH		 452 /* Disable auto update for duplex flow control and duplex */
453 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 454
455 switch (sky2->speed) {
456 case SPEED_1000:
457 ctrl |= PHY_CT_SP1000;
2eaba1a2 458 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 459 break;
460 case SPEED_100:
461 ctrl |= PHY_CT_SP100;
2eaba1a2 462 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 463 break;
464 }
465
2eaba1a2
SH		 466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
0ea065e5 471 }
2eaba1a2 472
0ea065e5
SH		 473 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
474 if (sky2_is_copper(hw))
475 adv |= copper_fc_adv[sky2->flow_mode];
476 else
477 adv |= fiber_fc_adv[sky2->flow_mode];
478 } else {
479 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 480 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 481
482 /* Forward pause packets to GMAC? */
16ad91e1 483 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
485 else
486 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 487 }
488
2eaba1a2
SH		 489 gma_write16(hw, port, GM_GP_CTRL, reg);
490
05745c4a 491 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 492 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
493
494 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
495 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
496
497 /* Setup Phy LED's */
498 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
499 ledover = 0;
500
501 switch (hw->chip_id) {
502 case CHIP_ID_YUKON_FE:
503 /* on 88E3082 these bits are at 11..9 (shifted left) */
504 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
505
506 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
507
508 /* delete ACT LED control bits */
509 ctrl &= ~PHY_M_FELP_LED1_MSK;
510 /* change ACT LED control to blink mode */
511 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
05745c4a
SH		 515 case CHIP_ID_YUKON_FE_P:
516 /* Enable Link Partner Next Page */
517 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
518 ctrl |= PHY_M_PC_ENA_LIP_NP;
519
520 /* disable Energy Detect and enable scrambler */
521 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
523
524 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
525 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
526 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
527 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
528
529 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
530 break;
531
cd28ab6a 532 case CHIP_ID_YUKON_XL:
793b883e 533 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 534
535 /* select page 3 to access LED control register */
536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
537
538 /* set LED Function Control register */
ed6d32c7
SH		 539 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
540 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
541 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
542 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
543 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 544
545 /* set Polarity Control register */
546 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 547 (PHY_M_POLC_LS1_P_MIX(4) |
548 PHY_M_POLC_IS0_P_MIX(4) |
549 PHY_M_POLC_LOS_CTRL(2) |
550 PHY_M_POLC_INIT_CTRL(2) |
551 PHY_M_POLC_STA1_CTRL(2) |
552 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 553
554 /* restore page register */
793b883e 555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 556 break;
93745494 557
ed6d32c7 558 case CHIP_ID_YUKON_EC_U:
93745494 559 case CHIP_ID_YUKON_EX:
ed4d4161 560 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 561 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
562
563 /* select page 3 to access LED control register */
564 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
565
566 /* set LED Function Control register */
567 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
568 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
569 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
570 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
571 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
572
573 /* set Blink Rate in LED Timer Control Register */
574 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
575 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
576 /* restore page register */
577 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
578 break;
cd28ab6a
SH		 579
580 default:
581 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
582 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 583
cd28ab6a 584 /* turn off the Rx LED (LED_RX) */
a84d0a3d 585 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 586 }
587
0ce8b98d 588 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 589 /* apply fixes in PHY AFE */
ed6d32c7
SH		 590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
591
977bdf06 592 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 593 gm_phy_write(hw, port, 0x18, 0xaa99);
594 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 595
0ce8b98d
SH		 596 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
597 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
598 gm_phy_write(hw, port, 0x18, 0xa204);
599 gm_phy_write(hw, port, 0x17, 0x2002);
600 }
977bdf06
SH		 601
602 /* set page register to 0 */
9467a8fc 603 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 604 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
605 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
606 /* apply workaround for integrated resistors calibration */
607 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
608 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 609 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
610 /* apply fixes in PHY AFE */
611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
612
613 /* apply RDAC termination workaround */
614 gm_phy_write(hw, port, 24, 0x2800);
615 gm_phy_write(hw, port, 23, 0x2001);
616
617 /* set page register back to 0 */
618 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 619 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
620 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 621 /* no effect on Yukon-XL */
977bdf06 622 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 623
8e95a202
JP		 624 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
625 sky2->speed == SPEED_100) {
977bdf06 626 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 627 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 628 }
cd28ab6a 629
977bdf06
SH		 630 if (ledover)
631 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
632
633 }
2eaba1a2 634
d571b694 635 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 636 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
638 else
639 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
640}
641
b96936da
SH		 642static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
643static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
644
645static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 646{
647 u32 reg1;
d3bcfbeb 648
a40ccc68 649 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 650 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 651 reg1 &= ~phy_power[port];
d3bcfbeb 652
b96936da 653 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 654 reg1 |= coma_mode[port];
655
b32f40c4 656 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 657 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 658 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 659
660 if (hw->chip_id == CHIP_ID_YUKON_FE)
661 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
662 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
663 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 664}
167f53d0 665
b96936da
SH		 666static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
667{
668 u32 reg1;
db99b988
SH		 669 u16 ctrl;
670
671 /* release GPHY Control reset */
672 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
673
674 /* release GMAC reset */
675 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
676
677 if (hw->flags & SKY2_HW_NEWER_PHY) {
678 /* select page 2 to access MAC control register */
679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
680
681 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
682 /* allow GMII Power Down */
683 ctrl &= ~PHY_M_MAC_GMIF_PUP;
684 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
685
686 /* set page register back to 0 */
687 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
688 }
689
690 /* setup General Purpose Control Register */
691 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 692 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
693 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
694 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 695
696 if (hw->chip_id != CHIP_ID_YUKON_EC) {
697 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 698 /* select page 2 to access MAC control register */
699 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 700
e484d5f5 701 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 702 /* enable Power Down */
703 ctrl |= PHY_M_PC_POW_D_ENA;
704 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 705
706 /* set page register back to 0 */
707 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 708 }
709
710 /* set IEEE compatible Power Down Mode (dev. #4.99) */
711 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
712 }
b96936da 713
a40ccc68 714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 715 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 716 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 719}
720
1b537565
SH		 721/* Force a renegotiation */
722static void sky2_phy_reinit(struct sky2_port *sky2)
723{
e07b1aa8 724 spin_lock_bh(&sky2->phy_lock);
1b537565 725 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 726 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 727}
728
e3173832
SH		 729/* Put device in state to listen for Wake On Lan */
730static void sky2_wol_init(struct sky2_port *sky2)
731{
732 struct sky2_hw *hw = sky2->hw;
733 unsigned port = sky2->port;
734 enum flow_control save_mode;
735 u16 ctrl;
e3173832
SH		 736
737 /* Bring hardware out of reset */
738 sky2_write16(hw, B0_CTST, CS_RST_CLR);
739 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
740
741 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
742 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
743
744 /* Force to 10/100
745 * sky2_reset will re-enable on resume
746 */
747 save_mode = sky2->flow_mode;
748 ctrl = sky2->advertising;
749
750 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
751 sky2->flow_mode = FC_NONE;
b96936da
SH		 752
753 spin_lock_bh(&sky2->phy_lock);
754 sky2_phy_power_up(hw, port);
755 sky2_phy_init(hw, port);
756 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 757
758 sky2->flow_mode = save_mode;
759 sky2->advertising = ctrl;
760
761 /* Set GMAC to no flow control and auto update for speed/duplex */
762 gma_write16(hw, port, GM_GP_CTRL,
763 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
764 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
765
766 /* Set WOL address */
767 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
768 sky2->netdev->dev_addr, ETH_ALEN);
769
770 /* Turn on appropriate WOL control bits */
771 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
772 ctrl = 0;
773 if (sky2->wol & WAKE_PHY)
774 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
775 else
776 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
777
778 if (sky2->wol & WAKE_MAGIC)
779 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
780 else
a419aef8 781 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 782
783 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
784 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
785
5f8ae5c5 786 /* Disable PiG firmware */
787 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
788
e3173832
SH		 789 /* block receiver */
790 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 791}
792
69161611
SH		 793static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
794{
05745c4a
SH		 795 struct net_device *dev = hw->dev[port];
796
ed4d4161
SH		 797 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
798 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 799 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 800 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 801 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
802 } else if (dev->mtu > ETH_DATA_LEN) {
803 /* set Tx GMAC FIFO Almost Empty Threshold */
804 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
805 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 806
44dde56d 807 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
808 } else
809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 810}
811
cd28ab6a
SH		 812static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
813{
814 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
815 u16 reg;
25cccecc 816 u32 rx_reg;
cd28ab6a
SH		 817 int i;
818 const u8 *addr = hw->dev[port]->dev_addr;
819
f350339c
SH		 820 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
821 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 822
823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
824
793b883e 825 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 826 /* WA DEV_472 -- looks like crossed wires on port 2 */
827 /* clear GMAC 1 Control reset */
828 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
829 do {
830 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
831 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
832 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
833 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
834 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
835 }
836
793b883e 837 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 838
2eaba1a2
SH		 839 /* Enable Transmit FIFO Underrun */
840 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
841
e07b1aa8 842 spin_lock_bh(&sky2->phy_lock);
b96936da 843 sky2_phy_power_up(hw, port);
cd28ab6a 844 sky2_phy_init(hw, port);
e07b1aa8 845 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 846
847 /* MIB clear */
848 reg = gma_read16(hw, port, GM_PHY_ADDR);
849 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
850
43f2f104
SH		 851 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
852 gma_read16(hw, port, i);
cd28ab6a
SH		 853 gma_write16(hw, port, GM_PHY_ADDR, reg);
854
855 /* transmit control */
856 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
857
858 /* receive control reg: unicast + multicast + no FCS */
859 gma_write16(hw, port, GM_RX_CTRL,
793b883e 860 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 861
862 /* transmit flow control */
863 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
864
865 /* transmit parameter */
866 gma_write16(hw, port, GM_TX_PARAM,
867 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
868 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
869 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
870 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
871
872 /* serial mode register */
873 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 874 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 875
6b1a3aef 876 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 877 reg |= GM_SMOD_JUMBO_ENA;
878
879 gma_write16(hw, port, GM_SERIAL_MODE, reg);
880
cd28ab6a
SH		 881 /* virtual address for data */
882 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
883
793b883e
SH		 884 /* physical address: used for pause frames */
885 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
886
887 /* ignore counter overflows */
cd28ab6a
SH		 888 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
889 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
890 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
891
892 /* Configure Rx MAC FIFO */
893 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 894 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 895 if (hw->chip_id == CHIP_ID_YUKON_EX ||
896 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 897 rx_reg |= GMF_RX_OVER_ON;
69161611 898
25cccecc 899 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 900
798fdd07
SH		 901 if (hw->chip_id == CHIP_ID_YUKON_XL) {
902 /* Hardware errata - clear flush mask */
903 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
904 } else {
905 /* Flush Rx MAC FIFO on any flow control or error */
906 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
907 }
cd28ab6a 908
8df9a876 909 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 910 reg = RX_GMF_FL_THR_DEF + 1;
911 /* Another magic mystery workaround from sk98lin */
912 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
913 hw->chip_rev == CHIP_REV_YU_FE2_A0)
914 reg = 0x178;
915 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 916
917 /* Configure Tx MAC FIFO */
918 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
919 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 920
e0c28116 921 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 922 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 923 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 924 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
925 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 926 reg = 1568 / 8;
927 else
928 reg = 1024 / 8;
929 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
930 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 931
69161611 932 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 933 }
934
e970d1f8
SH		 935 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
936 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
937 /* disable dynamic watermark */
938 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
939 reg &= ~TX_DYN_WM_ENA;
940 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
941 }
cd28ab6a
SH		 942}
943
67712901
SH		 944/* Assign Ram Buffer allocation to queue */
945static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 946{
67712901
SH		 947 u32 end;
948
949 /* convert from K bytes to qwords used for hw register */
950 start *= 1024/8;
951 space *= 1024/8;
952 end = start + space - 1;
793b883e 953
cd28ab6a
SH		 954 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
955 sky2_write32(hw, RB_ADDR(q, RB_START), start);
956 sky2_write32(hw, RB_ADDR(q, RB_END), end);
957 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
958 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
959
960 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 961 u32 tp = space - space/4;
793b883e 962
1c28f6ba
SH		 963 /* On receive queue's set the thresholds
964 * give receiver priority when > 3/4 full
965 * send pause when down to 2K
966 */
967 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
968 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 969
1c28f6ba
SH		 970 tp = space - 2048/8;
971 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
972 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 973 } else {
974 /* Enable store & forward on Tx queue's because
975 * Tx FIFO is only 1K on Yukon
976 */
977 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
978 }
979
980 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 981 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 982}
983
cd28ab6a 984/* Setup Bus Memory Interface */
af4ed7e6 985static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 986{
987 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
988 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
989 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 990 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 991}
992
cd28ab6a
SH		 993/* Setup prefetch unit registers. This is the interface between
994 * hardware and driver list elements
995 */
8cc048e3 996static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 997 dma_addr_t addr, u32 last)
cd28ab6a 998{
cd28ab6a
SH		 999 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1000 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1001 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1002 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1003 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1004 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1005
1006 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1007}
1008
9b289c33 1009static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1010{
9b289c33 1011 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1012
ee5f68fe 1013 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1014 le->ctrl = 0;
793b883e
SH		 1015 return le;
1016}
cd28ab6a 1017
88f5f0ca
SH		 1018static void tx_init(struct sky2_port *sky2)
1019{
1020 struct sky2_tx_le *le;
1021
1022 sky2->tx_prod = sky2->tx_cons = 0;
1023 sky2->tx_tcpsum = 0;
1024 sky2->tx_last_mss = 0;
1025
9b289c33 1026 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1027 le->addr = 0;
1028 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1029 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1030}
1031
290d4de5
SH		 1032/* Update chip's next pointer */
1033static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1034{
50432cb5 1035 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1036 wmb();
50432cb5
SH		 1037 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1038
1039 /* Synchronize I/O on since next processor may write to tail */
1040 mmiowb();
cd28ab6a
SH		 1041}
1042
793b883e 1043
cd28ab6a
SH		 1044static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1045{
1046 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1047 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1048 le->ctrl = 0;
cd28ab6a
SH		 1049 return le;
1050}
1051
14d0263f
SH		 1052/* Build description to hardware for one receive segment */
1053static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1054 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1055{
1056 struct sky2_rx_le *le;
1057
86c6887e 1058 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1059 le = sky2_next_rx(sky2);
86c6887e 1060 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1061 le->opcode = OP_ADDR64 | HW_OWNER;
1062 }
793b883e 1063
cd28ab6a 1064 le = sky2_next_rx(sky2);
d6e74b6b 1065 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1066 le->length = cpu_to_le16(len);
14d0263f 1067 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1068}
1069
14d0263f
SH		 1070/* Build description to hardware for one possibly fragmented skb */
1071static void sky2_rx_submit(struct sky2_port *sky2,
1072 const struct rx_ring_info *re)
1073{
1074 int i;
1075
1076 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1077
1078 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1079 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1080}
1081
1082
454e6cb6 1083static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1084 unsigned size)
1085{
1086 struct sk_buff *skb = re->skb;
1087 int i;
1088
1089 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1090 if (pci_dma_mapping_error(pdev, re->data_addr))
1091 goto mapping_error;
454e6cb6 1092
14d0263f
SH		 1093 pci_unmap_len_set(re, data_size, size);
1094
3fbd9187 1095 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1096 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1097
1098 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1099 frag->page_offset,
1100 frag->size,
14d0263f 1101 PCI_DMA_FROMDEVICE);
3fbd9187 1102
1103 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1104 goto map_page_error;
1105 }
454e6cb6 1106 return 0;
3fbd9187 1107
1108map_page_error:
1109 while (--i >= 0) {
1110 pci_unmap_page(pdev, re->frag_addr[i],
1111 skb_shinfo(skb)->frags[i].size,
1112 PCI_DMA_FROMDEVICE);
1113 }
1114
1115 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1116 PCI_DMA_FROMDEVICE);
1117
1118mapping_error:
1119 if (net_ratelimit())
1120 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1121 skb->dev->name);
1122 return -EIO;
14d0263f
SH		 1123}
1124
1125static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1126{
1127 struct sk_buff *skb = re->skb;
1128 int i;
1129
1130 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1131 PCI_DMA_FROMDEVICE);
1132
1133 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1134 pci_unmap_page(pdev, re->frag_addr[i],
1135 skb_shinfo(skb)->frags[i].size,
1136 PCI_DMA_FROMDEVICE);
1137}
793b883e 1138
cd28ab6a
SH		 1139/* Tell chip where to start receive checksum.
1140 * Actually has two checksums, but set both same to avoid possible byte
1141 * order problems.
1142 */
793b883e 1143static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1144{
ea76e635 1145 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1146
ea76e635
SH		 1147 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1148 le->ctrl = 0;
1149 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1150
ea76e635
SH		 1151 sky2_write32(sky2->hw,
1152 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1153 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1154 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1155}
1156
6b1a3aef 1157/*
1158 * The RX Stop command will not work for Yukon-2 if the BMU does not
1159 * reach the end of packet and since we can't make sure that we have
1160 * incoming data, we must reset the BMU while it is not doing a DMA
1161 * transfer. Since it is possible that the RX path is still active,
1162 * the RX RAM buffer will be stopped first, so any possible incoming
1163 * data will not trigger a DMA. After the RAM buffer is stopped, the
1164 * BMU is polled until any DMA in progress is ended and only then it
1165 * will be reset.
1166 */
1167static void sky2_rx_stop(struct sky2_port *sky2)
1168{
1169 struct sky2_hw *hw = sky2->hw;
1170 unsigned rxq = rxqaddr[sky2->port];
1171 int i;
1172
1173 /* disable the RAM Buffer receive queue */
1174 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1175
1176 for (i = 0; i < 0xffff; i++)
1177 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1178 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1179 goto stopped;
1180
1181 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1182 sky2->netdev->name);
1183stopped:
1184 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1185
1186 /* reset the Rx prefetch unit */
1187 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1188 mmiowb();
6b1a3aef 1189}
793b883e 1190
d571b694 1191/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1192static void sky2_rx_clean(struct sky2_port *sky2)
1193{
1194 unsigned i;
1195
1196 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1197 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1198 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1199
1200 if (re->skb) {
14d0263f 1201 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1202 kfree_skb(re->skb);
1203 re->skb = NULL;
1204 }
1205 }
1206}
1207
ef743d33 1208/* Basic MII support */
1209static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1210{
1211 struct mii_ioctl_data *data = if_mii(ifr);
1212 struct sky2_port *sky2 = netdev_priv(dev);
1213 struct sky2_hw *hw = sky2->hw;
1214 int err = -EOPNOTSUPP;
1215
1216 if (!netif_running(dev))
1217 return -ENODEV; /* Phy still in reset */
1218
d89e1343 1219 switch (cmd) {
ef743d33 1220 case SIOCGMIIPHY:
1221 data->phy_id = PHY_ADDR_MARV;
1222
1223 /* fallthru */
1224 case SIOCGMIIREG: {
1225 u16 val = 0;
91c86df5 1226
e07b1aa8 1227 spin_lock_bh(&sky2->phy_lock);
ef743d33 1228 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1229 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1230
ef743d33 1231 data->val_out = val;
1232 break;
1233 }
1234
1235 case SIOCSMIIREG:
e07b1aa8 1236 spin_lock_bh(&sky2->phy_lock);
ef743d33 1237 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1238 data->val_in);
e07b1aa8 1239 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1240 break;
1241 }
1242 return err;
1243}
1244
d1f13708 1245#ifdef SKY2_VLAN_TAG_USED
d494eacd 1246static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1247{
d494eacd 1248 if (onoff) {
3d4e66f5
SH		 1249 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1250 RX_VLAN_STRIP_ON);
1251 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1252 TX_VLAN_TAG_ON);
1253 } else {
1254 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1255 RX_VLAN_STRIP_OFF);
1256 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1257 TX_VLAN_TAG_OFF);
1258 }
d494eacd
SH		 1259}
1260
1261static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1262{
1263 struct sky2_port *sky2 = netdev_priv(dev);
1264 struct sky2_hw *hw = sky2->hw;
1265 u16 port = sky2->port;
1266
1267 netif_tx_lock_bh(dev);
1268 napi_disable(&hw->napi);
1269
1270 sky2->vlgrp = grp;
1271 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1272
d1d08d12 1273 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1274 napi_enable(&hw->napi);
2bb8c262 1275 netif_tx_unlock_bh(dev);
d1f13708 1276}
1277#endif
1278
bd1c6869
SH		 1279/* Amount of required worst case padding in rx buffer */
1280static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1281{
1282 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1283}
1284
82788c7a 1285/*
14d0263f
SH		 1286 * Allocate an skb for receiving. If the MTU is large enough
1287 * make the skb non-linear with a fragment list of pages.
82788c7a 1288 */
14d0263f 1289static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1290{
1291 struct sk_buff *skb;
14d0263f 1292 int i;
82788c7a 1293
724b6942
SH		 1294 skb = netdev_alloc_skb(sky2->netdev,
1295 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1296 if (!skb)
1297 goto nomem;
1298
39dbd958 1299 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1300 unsigned char *start;
1301 /*
1302 * Workaround for a bug in FIFO that cause hang
1303 * if the FIFO if the receive buffer is not 64 byte aligned.
1304 * The buffer returned from netdev_alloc_skb is
1305 * aligned except if slab debugging is enabled.
1306 */
f03b8654
SH		 1307 start = PTR_ALIGN(skb->data, 8);
1308 skb_reserve(skb, start - skb->data);
bd1c6869 1309 } else
f03b8654 1310 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1311
1312 for (i = 0; i < sky2->rx_nfrags; i++) {
1313 struct page *page = alloc_page(GFP_ATOMIC);
1314
1315 if (!page)
1316 goto free_partial;
1317 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1318 }
1319
1320 return skb;
14d0263f
SH		 1321free_partial:
1322 kfree_skb(skb);
1323nomem:
1324 return NULL;
82788c7a
SH		 1325}
1326
55c9dd35
SH		 1327static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1328{
1329 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1330}
1331
cd28ab6a
SH		 1332/*
1333 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1334 * Normal case this ends up creating one list element for skb
1335 * in the receive ring. Worst case if using large MTU and each
1336 * allocation falls on a different 64 bit region, that results
1337 * in 6 list elements per ring entry.
1338 * One element is used for checksum enable/disable, and one
1339 * extra to avoid wrap.
cd28ab6a 1340 */
6b1a3aef 1341static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1342{
6b1a3aef 1343 struct sky2_hw *hw = sky2->hw;
14d0263f 1344 struct rx_ring_info *re;
6b1a3aef 1345 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1346 unsigned i, size, thresh;
cd28ab6a 1347
6b1a3aef 1348 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1349 sky2_qset(hw, rxq);
977bdf06 1350
c3905bc4
SH		 1351 /* On PCI express lowering the watermark gives better performance */
1352 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1353 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1354
1355 /* These chips have no ram buffer?
1356 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1357 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
8e95a202
JP		 1358 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1359 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1360 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1361
6b1a3aef 1362 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1363
ea76e635
SH		 1364 if (!(hw->flags & SKY2_HW_NEW_LE))
1365 rx_set_checksum(sky2);
14d0263f
SH		 1366
1367 /* Space needed for frame data + headers rounded up */
f957da2a 1368 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1369
1370 /* Stopping point for hardware truncation */
1371 thresh = (size - 8) / sizeof(u32);
1372
5f06eba4 1373 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1374 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1375
5f06eba4
SH		 1376 /* Compute residue after pages */
1377 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1378
5f06eba4
SH		 1379 /* Optimize to handle small packets and headers */
1380 if (size < copybreak)
1381 size = copybreak;
1382 if (size < ETH_HLEN)
1383 size = ETH_HLEN;
14d0263f 1384
14d0263f
SH		 1385 sky2->rx_data_size = size;
1386
1387 /* Fill Rx ring */
793b883e 1388 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1389 re = sky2->rx_ring + i;
cd28ab6a 1390
14d0263f 1391 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1392 if (!re->skb)
1393 goto nomem;
1394
454e6cb6
SH		 1395 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1396 dev_kfree_skb(re->skb);
1397 re->skb = NULL;
1398 goto nomem;
1399 }
1400
14d0263f 1401 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1402 }
1403
a1433ac4
SH		 1404 /*
1405 * The receiver hangs if it receives frames larger than the
1406 * packet buffer. As a workaround, truncate oversize frames, but
1407 * the register is limited to 9 bits, so if you do frames > 2052
1408 * you better get the MTU right!
1409 */
a1433ac4
SH		 1410 if (thresh > 0x1ff)
1411 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1412 else {
1413 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1414 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1415 }
1416
6b1a3aef 1417 /* Tell chip about available buffers */
55c9dd35 1418 sky2_rx_update(sky2, rxq);
877c8570
SH		 1419
1420 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1421 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1422 /*
1423 * Disable flushing of non ASF packets;
1424 * must be done after initializing the BMUs;
1425 * drivers without ASF support should do this too, otherwise
1426 * it may happen that they cannot run on ASF devices;
1427 * remember that the MAC FIFO isn't reset during initialization.
1428 */
1429 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1430 }
1431
1432 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1433 /* Enable RX Home Address & Routing Header checksum fix */
1434 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1435 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1436
1437 /* Enable TX Home Address & Routing Header checksum fix */
1438 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1439 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1440 }
1441
1442
1443
cd28ab6a
SH		 1444 return 0;
1445nomem:
1446 sky2_rx_clean(sky2);
1447 return -ENOMEM;
1448}
1449
90bbebb4
MM		 1450static int sky2_alloc_buffers(struct sky2_port *sky2)
1451{
1452 struct sky2_hw *hw = sky2->hw;
1453
1454 /* must be power of 2 */
1455 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1456 sky2->tx_ring_size *
1457 sizeof(struct sky2_tx_le),
1458 &sky2->tx_le_map);
1459 if (!sky2->tx_le)
1460 goto nomem;
1461
1462 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1463 GFP_KERNEL);
1464 if (!sky2->tx_ring)
1465 goto nomem;
1466
1467 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1468 &sky2->rx_le_map);
1469 if (!sky2->rx_le)
1470 goto nomem;
1471 memset(sky2->rx_le, 0, RX_LE_BYTES);
1472
1473 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1474 GFP_KERNEL);
1475 if (!sky2->rx_ring)
1476 goto nomem;
1477
1478 return 0;
1479nomem:
1480 return -ENOMEM;
1481}
1482
1483static void sky2_free_buffers(struct sky2_port *sky2)
1484{
1485 struct sky2_hw *hw = sky2->hw;
1486
1487 if (sky2->rx_le) {
1488 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1489 sky2->rx_le, sky2->rx_le_map);
1490 sky2->rx_le = NULL;
1491 }
1492 if (sky2->tx_le) {
1493 pci_free_consistent(hw->pdev,
1494 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1495 sky2->tx_le, sky2->tx_le_map);
1496 sky2->tx_le = NULL;
1497 }
1498 kfree(sky2->tx_ring);
1499 kfree(sky2->rx_ring);
1500
1501 sky2->tx_ring = NULL;
1502 sky2->rx_ring = NULL;
1503}
1504
cd28ab6a
SH		 1505/* Bring up network interface. */
1506static int sky2_up(struct net_device *dev)
1507{
1508 struct sky2_port *sky2 = netdev_priv(dev);
1509 struct sky2_hw *hw = sky2->hw;
1510 unsigned port = sky2->port;
e0c28116 1511 u32 imask, ramsize;
90bbebb4 1512 int cap, err;
843a46f4 1513 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1514
ee7abb04
SH		 1515 /*
1516 * On dual port PCI-X card, there is an problem where status
1517 * can be received out of order due to split transactions
843a46f4 1518 */
ee7abb04
SH		 1519 if (otherdev && netif_running(otherdev) &&
1520 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1521 u16 cmd;
1522
b32f40c4 1523 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1524 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1525 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1526
ee7abb04 1527 }
843a46f4 1528
55d7b4e6
SH		 1529 netif_carrier_off(dev);
1530
90bbebb4
MM		 1531 err = sky2_alloc_buffers(sky2);
1532 if (err)
cd28ab6a 1533 goto err_out;
88f5f0ca
SH		 1534
1535 tx_init(sky2);
cd28ab6a 1536
cd28ab6a
SH		 1537 sky2_mac_init(hw, port);
1538
e0c28116
SH		 1539 /* Register is number of 4K blocks on internal RAM buffer. */
1540 ramsize = sky2_read8(hw, B2_E_0) * 4;
1541 if (ramsize > 0) {
67712901 1542 u32 rxspace;
cd28ab6a 1543
e0c28116 1544 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1545 if (ramsize < 16)
1546 rxspace = ramsize / 2;
1547 else
1548 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1549
67712901
SH		 1550 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1551 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1552
1553 /* Make sure SyncQ is disabled */
1554 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1555 RB_RST_SET);
1556 }
793b883e 1557
af4ed7e6 1558 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1559
69161611
SH		 1560 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1561 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1562 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1563
977bdf06 1564 /* Set almost empty threshold */
8e95a202
JP		 1565 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1566 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1567 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1568
6b1a3aef 1569 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1570 sky2->tx_ring_size - 1);
cd28ab6a 1571
d494eacd
SH		 1572#ifdef SKY2_VLAN_TAG_USED
1573 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1574#endif
1575
6b1a3aef 1576 err = sky2_rx_start(sky2);
6de16237 1577 if (err)
cd28ab6a
SH		 1578 goto err_out;
1579
cd28ab6a 1580 /* Enable interrupts from phy/mac for port */
e07b1aa8 1581 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1582 imask |= portirq_msk[port];
e07b1aa8 1583 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1584 sky2_read32(hw, B0_IMSK);
e07b1aa8 1585
a11da890
AD		 1586 if (netif_msg_ifup(sky2))
1587 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1588
cd28ab6a
SH		 1589 return 0;
1590
1591err_out:
90bbebb4 1592 sky2_free_buffers(sky2);
cd28ab6a
SH		 1593 return err;
1594}
1595
793b883e 1596/* Modular subtraction in ring */
ee5f68fe 1597static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1598{
ee5f68fe 1599 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1600}
cd28ab6a 1601
793b883e
SH		 1602/* Number of list elements available for next tx */
1603static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1604{
ee5f68fe 1605 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1606}
1607
793b883e 1608/* Estimate of number of transmit list elements required */
28bd181a 1609static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1610{
793b883e
SH		 1611 unsigned count;
1612
07e31637
SH		 1613 count = (skb_shinfo(skb)->nr_frags + 1)
1614 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1615
89114afd 1616 if (skb_is_gso(skb))
793b883e 1617 ++count;
07e31637
SH		 1618 else if (sizeof(dma_addr_t) == sizeof(u32))
1619 ++count; /* possible vlan */
793b883e 1620
84fa7933 1621 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1622 ++count;
1623
1624 return count;
cd28ab6a
SH		 1625}
1626
f6815077 1627static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1628{
1629 if (re->flags & TX_MAP_SINGLE)
1630 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1631 pci_unmap_len(re, maplen),
1632 PCI_DMA_TODEVICE);
1633 else if (re->flags & TX_MAP_PAGE)
1634 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1635 pci_unmap_len(re, maplen),
1636 PCI_DMA_TODEVICE);
f6815077 1637 re->flags = 0;
6b84daca
SH		 1638}
1639
793b883e
SH		 1640/*
1641 * Put one packet in ring for transmit.
1642 * A single packet can generate multiple list elements, and
1643 * the number of ring elements will probably be less than the number
1644 * of list elements used.
1645 */
61357325
SH		 1646static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1647 struct net_device *dev)
cd28ab6a
SH		 1648{
1649 struct sky2_port *sky2 = netdev_priv(dev);
1650 struct sky2_hw *hw = sky2->hw;
d1f13708 1651 struct sky2_tx_le *le = NULL;
6cdbbdf3 1652 struct tx_ring_info *re;
9b289c33 1653 unsigned i, len;
cd28ab6a 1654 dma_addr_t mapping;
5dce95e5
SH		 1655 u32 upper;
1656 u16 slot;
cd28ab6a
SH		 1657 u16 mss;
1658 u8 ctrl;
1659
2bb8c262
SH		 1660 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1661 return NETDEV_TX_BUSY;
cd28ab6a 1662
cd28ab6a
SH		 1663 len = skb_headlen(skb);
1664 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1665
454e6cb6
SH		 1666 if (pci_dma_mapping_error(hw->pdev, mapping))
1667 goto mapping_error;
1668
9b289c33 1669 slot = sky2->tx_prod;
454e6cb6
SH		 1670 if (unlikely(netif_msg_tx_queued(sky2)))
1671 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1672 dev->name, slot, skb->len);
454e6cb6 1673
86c6887e 1674 /* Send high bits if needed */
5dce95e5
SH		 1675 upper = upper_32_bits(mapping);
1676 if (upper != sky2->tx_last_upper) {
9b289c33 1677 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1678 le->addr = cpu_to_le32(upper);
1679 sky2->tx_last_upper = upper;
793b883e 1680 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1681 }
cd28ab6a
SH		 1682
1683 /* Check for TCP Segmentation Offload */
7967168c 1684 mss = skb_shinfo(skb)->gso_size;
793b883e 1685 if (mss != 0) {
ea76e635
SH		 1686
1687 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1688 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1689
1690 if (mss != sky2->tx_last_mss) {
9b289c33 1691 le = get_tx_le(sky2, &slot);
69161611 1692 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1693
1694 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1695 le->opcode = OP_MSS | HW_OWNER;
1696 else
1697 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1698 sky2->tx_last_mss = mss;
1699 }
cd28ab6a
SH		 1700 }
1701
cd28ab6a 1702 ctrl = 0;
d1f13708 1703#ifdef SKY2_VLAN_TAG_USED
1704 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1705 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1706 if (!le) {
9b289c33 1707 le = get_tx_le(sky2, &slot);
f65b138c 1708 le->addr = 0;
d1f13708 1709 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1710 } else
1711 le->opcode |= OP_VLAN;
1712 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1713 ctrl |= INS_VLAN;
1714 }
1715#endif
1716
1717 /* Handle TCP checksum offload */
84fa7933 1718 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1719 /* On Yukon EX (some versions) encoding change. */
ea76e635 1720 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1721 ctrl |= CALSUM; /* auto checksum */
1722 else {
1723 const unsigned offset = skb_transport_offset(skb);
1724 u32 tcpsum;
1725
1726 tcpsum = offset << 16; /* sum start */
1727 tcpsum |= offset + skb->csum_offset; /* sum write */
1728
1729 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1730 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1731 ctrl |= UDPTCP;
1732
1733 if (tcpsum != sky2->tx_tcpsum) {
1734 sky2->tx_tcpsum = tcpsum;
1735
9b289c33 1736 le = get_tx_le(sky2, &slot);
69161611
SH		 1737 le->addr = cpu_to_le32(tcpsum);
1738 le->length = 0; /* initial checksum value */
1739 le->ctrl = 1; /* one packet */
1740 le->opcode = OP_TCPLISW | HW_OWNER;
1741 }
1d179332 1742 }
cd28ab6a
SH		 1743 }
1744
6b84daca
SH		 1745 re = sky2->tx_ring + slot;
1746 re->flags = TX_MAP_SINGLE;
1747 pci_unmap_addr_set(re, mapaddr, mapping);
1748 pci_unmap_len_set(re, maplen, len);
1749
9b289c33 1750 le = get_tx_le(sky2, &slot);
d6e74b6b 1751 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1752 le->length = cpu_to_le16(len);
1753 le->ctrl = ctrl;
793b883e 1754 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1755
cd28ab6a
SH		 1756
1757 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1758 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1759
1760 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1761 frag->size, PCI_DMA_TODEVICE);
86c6887e 1762
454e6cb6
SH		 1763 if (pci_dma_mapping_error(hw->pdev, mapping))
1764 goto mapping_unwind;
1765
5dce95e5
SH		 1766 upper = upper_32_bits(mapping);
1767 if (upper != sky2->tx_last_upper) {
9b289c33 1768 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1769 le->addr = cpu_to_le32(upper);
1770 sky2->tx_last_upper = upper;
793b883e 1771 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1772 }
1773
6b84daca
SH		 1774 re = sky2->tx_ring + slot;
1775 re->flags = TX_MAP_PAGE;
1776 pci_unmap_addr_set(re, mapaddr, mapping);
1777 pci_unmap_len_set(re, maplen, frag->size);
1778
9b289c33 1779 le = get_tx_le(sky2, &slot);
d6e74b6b 1780 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1781 le->length = cpu_to_le16(frag->size);
1782 le->ctrl = ctrl;
793b883e 1783 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1784 }
6cdbbdf3 1785
6b84daca 1786 re->skb = skb;
cd28ab6a
SH		 1787 le->ctrl |= EOP;
1788
9b289c33
MM		 1789 sky2->tx_prod = slot;
1790
97bda706 1791 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1792 netif_stop_queue(dev);
b19666d9 1793
290d4de5 1794 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1795
cd28ab6a 1796 return NETDEV_TX_OK;
454e6cb6
SH		 1797
1798mapping_unwind:
ee5f68fe 1799 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1800 re = sky2->tx_ring + i;
1801
6b84daca 1802 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1803 }
1804
454e6cb6
SH		 1805mapping_error:
1806 if (net_ratelimit())
1807 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1808 dev_kfree_skb(skb);
1809 return NETDEV_TX_OK;
cd28ab6a
SH		 1810}
1811
cd28ab6a 1812/*
793b883e
SH		 1813 * Free ring elements from starting at tx_cons until "done"
1814 *
481cea4a
SH		 1815 * NB:
1816 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1817 * buffers so make sure not to free skb to early.
481cea4a
SH		 1818 * 2. This may run in parallel start_xmit because the it only
1819 * looks at the tail of the queue of FIFO (tx_cons), not
1820 * the head (tx_prod)
cd28ab6a 1821 */
d11c13e7 1822static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1823{
d11c13e7 1824 struct net_device *dev = sky2->netdev;
291ea614 1825 unsigned idx;
cd28ab6a 1826
ee5f68fe 1827 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1828
291ea614 1829 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1830 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1831 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1832 struct sk_buff *skb = re->skb;
291ea614 1833
6b84daca 1834 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1835
6b84daca 1836 if (skb) {
291ea614
SH		 1837 if (unlikely(netif_msg_tx_done(sky2)))
1838 printk(KERN_DEBUG "%s: tx done %u\n",
1839 dev->name, idx);
3cf26753 1840
7138a0f5 1841 dev->stats.tx_packets++;
bd1c6869
SH		 1842 dev->stats.tx_bytes += skb->len;
1843
f6815077 1844 re->skb = NULL;
724b6942 1845 dev_kfree_skb_any(skb);
2bf56fe2 1846
ee5f68fe 1847 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1848 }
793b883e 1849 }
793b883e 1850
291ea614 1851 sky2->tx_cons = idx;
50432cb5
SH		 1852 smp_mb();
1853
9db2f1be
JP		 1854 /* Wake unless it's detached, and called e.g. from sky2_down() */
1855 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
cd28ab6a 1856 netif_wake_queue(dev);
cd28ab6a
SH		 1857}
1858
264bb4fa 1859static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1860{
a510996b
MM		 1861 /* Disable Force Sync bit and Enable Alloc bit */
1862 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1863 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1864
1865 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1866 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1867 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1868
1869 /* Reset the PCI FIFO of the async Tx queue */
1870 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1871 BMU_RST_SET | BMU_FIFO_RST);
1872
1873 /* Reset the Tx prefetch units */
1874 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1875 PREF_UNIT_RST_SET);
1876
1877 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1878 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1879}
1880
cd28ab6a
SH		 1881/* Network shutdown */
1882static int sky2_down(struct net_device *dev)
1883{
1884 struct sky2_port *sky2 = netdev_priv(dev);
1885 struct sky2_hw *hw = sky2->hw;
1886 unsigned port = sky2->port;
1887 u16 ctrl;
e07b1aa8 1888 u32 imask;
cd28ab6a 1889
1b537565
SH		 1890 /* Never really got started! */
1891 if (!sky2->tx_le)
1892 return 0;
1893
cd28ab6a
SH		 1894 if (netif_msg_ifdown(sky2))
1895 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1896
d104acaf
SH		 1897 /* Force flow control off */
1898 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1899
cd28ab6a
SH		 1900 /* Stop transmitter */
1901 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1902 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1903
1904 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1905 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1906
1907 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1908 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1909 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1910
1911 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1912
1913 /* Workaround shared GMAC reset */
8e95a202
JP		 1914 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1915 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1916 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1917
cd28ab6a 1918 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1919
6c83504f
SH		 1920 /* Force any delayed status interrrupt and NAPI */
1921 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1922 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1923 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1924 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1925
a947a39d
MM		 1926 sky2_rx_stop(sky2);
1927
1928 /* Disable port IRQ */
1929 imask = sky2_read32(hw, B0_IMSK);
1930 imask &= ~portirq_msk[port];
1931 sky2_write32(hw, B0_IMSK, imask);
1932 sky2_read32(hw, B0_IMSK);
1933
6c83504f
SH		 1934 synchronize_irq(hw->pdev->irq);
1935 napi_synchronize(&hw->napi);
1936
0da6d7b3 1937 spin_lock_bh(&sky2->phy_lock);
b96936da 1938 sky2_phy_power_down(hw, port);
0da6d7b3 1939 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1940
264bb4fa
MM		 1941 sky2_tx_reset(hw, port);
1942
481cea4a
SH		 1943 /* Free any pending frames stuck in HW queue */
1944 sky2_tx_complete(sky2, sky2->tx_prod);
1945
cd28ab6a
SH		 1946 sky2_rx_clean(sky2);
1947
90bbebb4 1948 sky2_free_buffers(sky2);
1b537565 1949
cd28ab6a
SH		 1950 return 0;
1951}
1952
1953static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1954{
ea76e635 1955 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1956 return SPEED_1000;
1957
05745c4a
SH		 1958 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1959 if (aux & PHY_M_PS_SPEED_100)
1960 return SPEED_100;
1961 else
1962 return SPEED_10;
1963 }
cd28ab6a
SH		 1964
1965 switch (aux & PHY_M_PS_SPEED_MSK) {
1966 case PHY_M_PS_SPEED_1000:
1967 return SPEED_1000;
1968 case PHY_M_PS_SPEED_100:
1969 return SPEED_100;
1970 default:
1971 return SPEED_10;
1972 }
1973}
1974
1975static void sky2_link_up(struct sky2_port *sky2)
1976{
1977 struct sky2_hw *hw = sky2->hw;
1978 unsigned port = sky2->port;
1979 u16 reg;
16ad91e1
SH		 1980 static const char *fc_name[] = {
1981 [FC_NONE] = "none",
1982 [FC_TX] = "tx",
1983 [FC_RX] = "rx",
1984 [FC_BOTH] = "both",
1985 };
cd28ab6a 1986
cd28ab6a 1987 /* enable Rx/Tx */
2eaba1a2 1988 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1989 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1990 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1991
1992 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1993
1994 netif_carrier_on(sky2->netdev);
cd28ab6a 1995
75e80683 1996 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1997
cd28ab6a 1998 /* Turn on link LED */
793b883e 1999 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2000 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2001
2002 if (netif_msg_link(sky2))
2003 printk(KERN_INFO PFX
d571b694 2004 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 2005 sky2->netdev->name, sky2->speed,
2006 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 2007 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2008}
2009
2010static void sky2_link_down(struct sky2_port *sky2)
2011{
2012 struct sky2_hw *hw = sky2->hw;
2013 unsigned port = sky2->port;
2014 u16 reg;
2015
2016 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2017
2018 reg = gma_read16(hw, port, GM_GP_CTRL);
2019 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2020 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2021
cd28ab6a 2022 netif_carrier_off(sky2->netdev);
cd28ab6a 2023
809aaaae 2024 /* Turn off link LED */
cd28ab6a
SH		 2025 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2026
2027 if (netif_msg_link(sky2))
2028 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 2029
cd28ab6a
SH		 2030 sky2_phy_init(hw, port);
2031}
2032
16ad91e1
SH		 2033static enum flow_control sky2_flow(int rx, int tx)
2034{
2035 if (rx)
2036 return tx ? FC_BOTH : FC_RX;
2037 else
2038 return tx ? FC_TX : FC_NONE;
2039}
2040
793b883e
SH		 2041static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2042{
2043 struct sky2_hw *hw = sky2->hw;
2044 unsigned port = sky2->port;
da4c1ff4 2045 u16 advert, lpa;
793b883e 2046
da4c1ff4 2047 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2048 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2049 if (lpa & PHY_M_AN_RF) {
2050 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2051 return -1;
2052 }
2053
793b883e
SH		 2054 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2055 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2056 sky2->netdev->name);
2057 return -1;
2058 }
2059
793b883e 2060 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2061 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2062
da4c1ff4
SH		 2063 /* Since the pause result bits seem to in different positions on
2064 * different chips. look at registers.
2065 */
ea76e635 2066 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2067 /* Shift for bits in fiber PHY */
2068 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2069 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2070
2071 if (advert & ADVERTISE_1000XPAUSE)
2072 advert |= ADVERTISE_PAUSE_CAP;
2073 if (advert & ADVERTISE_1000XPSE_ASYM)
2074 advert |= ADVERTISE_PAUSE_ASYM;
2075 if (lpa & LPA_1000XPAUSE)
2076 lpa |= LPA_PAUSE_CAP;
2077 if (lpa & LPA_1000XPAUSE_ASYM)
2078 lpa |= LPA_PAUSE_ASYM;
2079 }
793b883e 2080
da4c1ff4
SH		 2081 sky2->flow_status = FC_NONE;
2082 if (advert & ADVERTISE_PAUSE_CAP) {
2083 if (lpa & LPA_PAUSE_CAP)
2084 sky2->flow_status = FC_BOTH;
2085 else if (advert & ADVERTISE_PAUSE_ASYM)
2086 sky2->flow_status = FC_RX;
2087 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2088 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2089 sky2->flow_status = FC_TX;
2090 }
793b883e 2091
8e95a202
JP		 2092 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2093 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2094 sky2->flow_status = FC_NONE;
2eaba1a2 2095
da4c1ff4 2096 if (sky2->flow_status & FC_TX)
793b883e
SH		 2097 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2098 else
2099 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2100
2101 return 0;
2102}
cd28ab6a 2103
e07b1aa8
SH		 2104/* Interrupt from PHY */
2105static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2106{
e07b1aa8
SH		 2107 struct net_device *dev = hw->dev[port];
2108 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2109 u16 istatus, phystat;
2110
ebc646f6
SH		 2111 if (!netif_running(dev))
2112 return;
2113
e07b1aa8
SH		 2114 spin_lock(&sky2->phy_lock);
2115 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2116 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2117
cd28ab6a
SH		 2118 if (netif_msg_intr(sky2))
2119 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2120 sky2->netdev->name, istatus, phystat);
2121
0ea065e5 2122 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2123 if (sky2_autoneg_done(sky2, phystat) == 0)
2124 sky2_link_up(sky2);
2125 goto out;
2126 }
cd28ab6a 2127
793b883e
SH		 2128 if (istatus & PHY_M_IS_LSP_CHANGE)
2129 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2130
793b883e
SH		 2131 if (istatus & PHY_M_IS_DUP_CHANGE)
2132 sky2->duplex =
2133 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2134
793b883e
SH		 2135 if (istatus & PHY_M_IS_LST_CHANGE) {
2136 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2137 sky2_link_up(sky2);
793b883e
SH		 2138 else
2139 sky2_link_down(sky2);
cd28ab6a 2140 }
793b883e 2141out:
e07b1aa8 2142 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2143}
2144
0f5aac70
SH		 2145/* Special quick link interrupt (Yukon-2 Optima only) */
2146static void sky2_qlink_intr(struct sky2_hw *hw)
2147{
2148 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2149 u32 imask;
2150 u16 phy;
2151
2152 /* disable irq */
2153 imask = sky2_read32(hw, B0_IMSK);
2154 imask &= ~Y2_IS_PHY_QLNK;
2155 sky2_write32(hw, B0_IMSK, imask);
2156
2157 /* reset PHY Link Detect */
2158 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2159 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2160 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2161 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2162
2163 sky2_link_up(sky2);
2164}
2165
62335ab0 2166/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2167 * and tx queue is full (stopped).
2168 */
cd28ab6a
SH		 2169static void sky2_tx_timeout(struct net_device *dev)
2170{
2171 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2172 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2173
2174 if (netif_msg_timer(sky2))
2175 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2176
8f24664d 2177 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2178 dev->name, sky2->tx_cons, sky2->tx_prod,
2179 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2180 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2181
81906791
SH		 2182 /* can't restart safely under softirq */
2183 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2184}
2185
2186static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2187{
6b1a3aef 2188 struct sky2_port *sky2 = netdev_priv(dev);
2189 struct sky2_hw *hw = sky2->hw;
b628ed98 2190 unsigned port = sky2->port;
6b1a3aef 2191 int err;
2192 u16 ctl, mode;
e07b1aa8 2193 u32 imask;
cd28ab6a 2194
44dde56d 2195 /* MTU size outside the spec */
cd28ab6a
SH		 2196 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2197 return -EINVAL;
2198
44dde56d 2199 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2200 if (new_mtu > ETH_DATA_LEN &&
2201 (hw->chip_id == CHIP_ID_YUKON_FE ||
2202 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2203 return -EINVAL;
2204
44dde56d 2205 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2206 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2207 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2208
6b1a3aef 2209 if (!netif_running(dev)) {
2210 dev->mtu = new_mtu;
2211 return 0;
2212 }
2213
e07b1aa8 2214 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2215 sky2_write32(hw, B0_IMSK, 0);
2216
018d1c66 2217 dev->trans_start = jiffies; /* prevent tx timeout */
2218 netif_stop_queue(dev);
bea3348e 2219 napi_disable(&hw->napi);
018d1c66 2220
e07b1aa8
SH		 2221 synchronize_irq(hw->pdev->irq);
2222
39dbd958 2223 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2224 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2225
2226 ctl = gma_read16(hw, port, GM_GP_CTRL);
2227 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2228 sky2_rx_stop(sky2);
2229 sky2_rx_clean(sky2);
cd28ab6a
SH		 2230
2231 dev->mtu = new_mtu;
14d0263f 2232
6b1a3aef 2233 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2234 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2235
2236 if (dev->mtu > ETH_DATA_LEN)
2237 mode |= GM_SMOD_JUMBO_ENA;
2238
b628ed98 2239 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2240
b628ed98 2241 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2242
6b1a3aef 2243 err = sky2_rx_start(sky2);
e07b1aa8 2244 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2245
d1d08d12 2246 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2247 napi_enable(&hw->napi);
2248
1b537565
SH		 2249 if (err)
2250 dev_close(dev);
2251 else {
b628ed98 2252 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2253
1b537565
SH		 2254 netif_wake_queue(dev);
2255 }
2256
cd28ab6a
SH		 2257 return err;
2258}
2259
14d0263f
SH		 2260/* For small just reuse existing skb for next receive */
2261static struct sk_buff *receive_copy(struct sky2_port *sky2,
2262 const struct rx_ring_info *re,
2263 unsigned length)
2264{
2265 struct sk_buff *skb;
2266
89d71a66 2267 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2268 if (likely(skb)) {
14d0263f
SH		 2269 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2270 length, PCI_DMA_FROMDEVICE);
d626f62b 2271 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2272 skb->ip_summed = re->skb->ip_summed;
2273 skb->csum = re->skb->csum;
2274 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2275 length, PCI_DMA_FROMDEVICE);
2276 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2277 skb_put(skb, length);
14d0263f
SH		 2278 }
2279 return skb;
2280}
2281
2282/* Adjust length of skb with fragments to match received data */
2283static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2284 unsigned int length)
2285{
2286 int i, num_frags;
2287 unsigned int size;
2288
2289 /* put header into skb */
2290 size = min(length, hdr_space);
2291 skb->tail += size;
2292 skb->len += size;
2293 length -= size;
2294
2295 num_frags = skb_shinfo(skb)->nr_frags;
2296 for (i = 0; i < num_frags; i++) {
2297 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2298
2299 if (length == 0) {
2300 /* don't need this page */
2301 __free_page(frag->page);
2302 --skb_shinfo(skb)->nr_frags;
2303 } else {
2304 size = min(length, (unsigned) PAGE_SIZE);
2305
2306 frag->size = size;
2307 skb->data_len += size;
2308 skb->truesize += size;
2309 skb->len += size;
2310 length -= size;
2311 }
2312 }
2313}
2314
2315/* Normal packet - take skb from ring element and put in a new one */
2316static struct sk_buff *receive_new(struct sky2_port *sky2,
2317 struct rx_ring_info *re,
2318 unsigned int length)
2319{
3fbd9187 2320 struct sk_buff *skb;
2321 struct rx_ring_info nre;
14d0263f
SH		 2322 unsigned hdr_space = sky2->rx_data_size;
2323
3fbd9187 2324 nre.skb = sky2_rx_alloc(sky2);
2325 if (unlikely(!nre.skb))
2326 goto nobuf;
2327
2328 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2329 goto nomap;
14d0263f
SH		 2330
2331 skb = re->skb;
2332 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2333 prefetch(skb->data);
3fbd9187 2334 *re = nre;
14d0263f
SH		 2335
2336 if (skb_shinfo(skb)->nr_frags)
2337 skb_put_frags(skb, hdr_space, length);
2338 else
489b10c1 2339 skb_put(skb, length);
14d0263f 2340 return skb;
3fbd9187 2341
2342nomap:
2343 dev_kfree_skb(nre.skb);
2344nobuf:
2345 return NULL;
14d0263f
SH		 2346}
2347
cd28ab6a
SH		 2348/*
2349 * Receive one packet.
d571b694 2350 * For larger packets, get new buffer.
cd28ab6a 2351 */
497d7c86 2352static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2353 u16 length, u32 status)
2354{
497d7c86 2355 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2356 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2357 struct sk_buff *skb = NULL;
d6532232
SH		 2358 u16 count = (status & GMR_FS_LEN) >> 16;
2359
2360#ifdef SKY2_VLAN_TAG_USED
2361 /* Account for vlan tag */
2362 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2363 count -= VLAN_HLEN;
2364#endif
cd28ab6a
SH		 2365
2366 if (unlikely(netif_msg_rx_status(sky2)))
2367 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2368 dev->name, sky2->rx_next, status, length);
cd28ab6a 2369
793b883e 2370 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2371 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2372
3b12e014
SH		 2373 /* This chip has hardware problems that generates bogus status.
2374 * So do only marginal checking and expect higher level protocols
2375 * to handle crap frames.
2376 */
2377 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2378 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2379 length != count)
2380 goto okay;
2381
42eeea01 2382 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2383 goto error;
2384
42eeea01 2385 if (!(status & GMR_FS_RX_OK))
2386 goto resubmit;
2387
d6532232
SH		 2388 /* if length reported by DMA does not match PHY, packet was truncated */
2389 if (length != count)
3b12e014 2390 goto len_error;
71749531 2391
3b12e014 2392okay:
14d0263f
SH		 2393 if (length < copybreak)
2394 skb = receive_copy(sky2, re, length);
2395 else
2396 skb = receive_new(sky2, re, length);
90c30335
SH		 2397
2398 dev->stats.rx_dropped += (skb == NULL);
2399
793b883e 2400resubmit:
14d0263f 2401 sky2_rx_submit(sky2, re);
79e57d32 2402
cd28ab6a
SH		 2403 return skb;
2404
3b12e014 2405len_error:
71749531
SH		 2406 /* Truncation of overlength packets
2407 causes PHY length to not match MAC length */
7138a0f5 2408 ++dev->stats.rx_length_errors;
d6532232 2409 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2410 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2411 dev->name, status, length);
d6532232 2412 goto resubmit;
71749531 2413
cd28ab6a 2414error:
7138a0f5 2415 ++dev->stats.rx_errors;
b6d77734 2416 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2417 dev->stats.rx_over_errors++;
b6d77734
SH		 2418 goto resubmit;
2419 }
6e15b712 2420
3be92a70 2421 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2422 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2423 dev->name, status, length);
793b883e
SH		 2424
2425 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2426 dev->stats.rx_length_errors++;
cd28ab6a 2427 if (status & GMR_FS_FRAGMENT)
7138a0f5 2428 dev->stats.rx_frame_errors++;
cd28ab6a 2429 if (status & GMR_FS_CRC_ERR)
7138a0f5 2430 dev->stats.rx_crc_errors++;
79e57d32 2431
793b883e 2432 goto resubmit;
cd28ab6a
SH		 2433}
2434
e07b1aa8
SH		 2435/* Transmit complete */
2436static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2437{
e07b1aa8 2438 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2439
49d4b8ba 2440 if (netif_running(dev))
e07b1aa8 2441 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2442}
2443
37e5a243
SH		 2444static inline void sky2_skb_rx(const struct sky2_port *sky2,
2445 u32 status, struct sk_buff *skb)
2446{
2447#ifdef SKY2_VLAN_TAG_USED
2448 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2449 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2450 if (skb->ip_summed == CHECKSUM_NONE)
2451 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2452 else
2453 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2454 vlan_tag, skb);
2455 return;
2456 }
2457#endif
2458 if (skb->ip_summed == CHECKSUM_NONE)
2459 netif_receive_skb(skb);
2460 else
2461 napi_gro_receive(&sky2->hw->napi, skb);
2462}
2463
bf15fe99
SH		 2464static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2465 unsigned packets, unsigned bytes)
2466{
2467 if (packets) {
2468 struct net_device *dev = hw->dev[port];
2469
2470 dev->stats.rx_packets += packets;
2471 dev->stats.rx_bytes += bytes;
2472 dev->last_rx = jiffies;
2473 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2474 }
2475}
2476
375c5688 2477static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2478{
2479 /* If this happens then driver assuming wrong format for chip type */
2480 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2481
2482 /* Both checksum counters are programmed to start at
2483 * the same offset, so unless there is a problem they
2484 * should match. This failure is an early indication that
2485 * hardware receive checksumming won't work.
2486 */
2487 if (likely((u16)(status >> 16) == (u16)status)) {
2488 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2489 skb->ip_summed = CHECKSUM_COMPLETE;
2490 skb->csum = le16_to_cpu(status);
2491 } else {
2492 dev_notice(&sky2->hw->pdev->dev,
2493 "%s: receive checksum problem (status = %#x)\n",
2494 sky2->netdev->name, status);
2495
2496 /* Disable checksum offload */
2497 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2498 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2499 BMU_DIS_RX_CHKSUM);
2500 }
2501}
2502
e07b1aa8 2503/* Process status response ring */
26691830 2504static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2505{
e07b1aa8 2506 int work_done = 0;
bf15fe99
SH		 2507 unsigned int total_bytes[2] = { 0 };
2508 unsigned int total_packets[2] = { 0 };
a8fd6266 2509
af2a58ac 2510 rmb();
26691830 2511 do {
55c9dd35 2512 struct sky2_port *sky2;
13210ce5 2513 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2514 unsigned port;
13210ce5 2515 struct net_device *dev;
cd28ab6a 2516 struct sk_buff *skb;
cd28ab6a
SH		 2517 u32 status;
2518 u16 length;
ab5adecb
SH		 2519 u8 opcode = le->opcode;
2520
2521 if (!(opcode & HW_OWNER))
2522 break;
cd28ab6a 2523
cb5d9547 2524 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2525
ab5adecb 2526 port = le->css & CSS_LINK_BIT;
69161611 2527 dev = hw->dev[port];
13210ce5 2528 sky2 = netdev_priv(dev);
f65b138c
SH		 2529 length = le16_to_cpu(le->length);
2530 status = le32_to_cpu(le->status);
cd28ab6a 2531
ab5adecb
SH		 2532 le->opcode = 0;
2533 switch (opcode & ~HW_OWNER) {
cd28ab6a 2534 case OP_RXSTAT:
bf15fe99
SH		 2535 total_packets[port]++;
2536 total_bytes[port] += length;
90c30335 2537
497d7c86 2538 skb = sky2_receive(dev, length, status);
90c30335 2539 if (!skb)
55c9dd35 2540 break;
13210ce5 2541
69161611 2542 /* This chip reports checksum status differently */
05745c4a 2543 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2544 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2545 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2546 (le->css & CSS_TCPUDPCSOK))
2547 skb->ip_summed = CHECKSUM_UNNECESSARY;
2548 else
2549 skb->ip_summed = CHECKSUM_NONE;
2550 }
2551
13210ce5 2552 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2553
37e5a243 2554 sky2_skb_rx(sky2, status, skb);
13210ce5 2555
22e11703 2556 /* Stop after net poll weight */
13210ce5 2557 if (++work_done >= to_do)
2558 goto exit_loop;
cd28ab6a
SH		 2559 break;
2560
d1f13708 2561#ifdef SKY2_VLAN_TAG_USED
2562 case OP_RXVLAN:
2563 sky2->rx_tag = length;
2564 break;
2565
2566 case OP_RXCHKSVLAN:
2567 sky2->rx_tag = length;
2568 /* fall through */
2569#endif
cd28ab6a 2570 case OP_RXCHKS:
375c5688 2571 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2572 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2573 break;
2574
2575 case OP_TXINDEXLE:
13b97b74 2576 /* TX index reports status for both ports */
f55925d7 2577 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2578 if (hw->dev[1])
2579 sky2_tx_done(hw->dev[1],
2580 ((status >> 24) & 0xff)
2581 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2582 break;
2583
cd28ab6a
SH		 2584 default:
2585 if (net_ratelimit())
793b883e 2586 printk(KERN_WARNING PFX
ab5adecb 2587 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2588 }
26691830 2589 } while (hw->st_idx != idx);
cd28ab6a 2590
fe2a24df
SH		 2591 /* Fully processed status ring so clear irq */
2592 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2593
13210ce5 2594exit_loop:
bf15fe99
SH		 2595 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2596 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2597
e07b1aa8 2598 return work_done;
cd28ab6a
SH		 2599}
2600
2601static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2602{
2603 struct net_device *dev = hw->dev[port];
2604
3be92a70
SH		 2605 if (net_ratelimit())
2606 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2607 dev->name, status);
cd28ab6a
SH		 2608
2609 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2610 if (net_ratelimit())
2611 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2612 dev->name);
cd28ab6a
SH		 2613 /* Clear IRQ */
2614 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2615 }
2616
2617 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2618 if (net_ratelimit())
2619 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2620 dev->name);
cd28ab6a
SH		 2621
2622 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2623 }
2624
2625 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2626 if (net_ratelimit())
2627 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2628 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2629 }
2630
2631 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2632 if (net_ratelimit())
2633 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2634 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2635 }
2636
2637 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2638 if (net_ratelimit())
2639 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2640 dev->name);
cd28ab6a
SH		 2641 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2642 }
2643}
2644
2645static void sky2_hw_intr(struct sky2_hw *hw)
2646{
555382cb 2647 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2648 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2649 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2650
2651 status &= hwmsk;
cd28ab6a 2652
793b883e 2653 if (status & Y2_IS_TIST_OV)
cd28ab6a 2654 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2655
2656 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2657 u16 pci_err;
2658
a40ccc68 2659 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2660 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2661 if (net_ratelimit())
555382cb 2662 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2663 pci_err);
cd28ab6a 2664
b32f40c4 2665 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2666 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2667 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2668 }
2669
2670 if (status & Y2_IS_PCI_EXP) {
d571b694 2671 /* PCI-Express uncorrectable Error occurred */
555382cb 2672 u32 err;
cd28ab6a 2673
a40ccc68 2674 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2675 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2676 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2677 0xfffffffful);
3be92a70 2678 if (net_ratelimit())
555382cb 2679 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2680
7782c8c4 2681 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2682 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2683 }
2684
2685 if (status & Y2_HWE_L1_MASK)
2686 sky2_hw_error(hw, 0, status);
2687 status >>= 8;
2688 if (status & Y2_HWE_L1_MASK)
2689 sky2_hw_error(hw, 1, status);
2690}
2691
2692static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2693{
2694 struct net_device *dev = hw->dev[port];
2695 struct sky2_port *sky2 = netdev_priv(dev);
2696 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2697
2698 if (netif_msg_intr(sky2))
2699 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2700 dev->name, status);
2701
a3caeada
SH		 2702 if (status & GM_IS_RX_CO_OV)
2703 gma_read16(hw, port, GM_RX_IRQ_SRC);
2704
2705 if (status & GM_IS_TX_CO_OV)
2706 gma_read16(hw, port, GM_TX_IRQ_SRC);
2707
cd28ab6a 2708 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2709 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2710 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2711 }
2712
2713 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2714 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2715 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2716 }
cd28ab6a
SH		 2717}
2718
40b01727 2719/* This should never happen it is a bug. */
c119731d 2720static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2721{
2722 struct net_device *dev = hw->dev[port];
c119731d 2723 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2724
c119731d
SH		 2725 dev_err(&hw->pdev->dev, PFX
2726 "%s: descriptor error q=%#x get=%u put=%u\n",
2727 dev->name, (unsigned) q, (unsigned) idx,
2728 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2729
40b01727 2730 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2731}
cd28ab6a 2732
75e80683
SH		 2733static int sky2_rx_hung(struct net_device *dev)
2734{
2735 struct sky2_port *sky2 = netdev_priv(dev);
2736 struct sky2_hw *hw = sky2->hw;
2737 unsigned port = sky2->port;
2738 unsigned rxq = rxqaddr[port];
2739 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2740 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2741 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2742 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2743
2744 /* If idle and MAC or PCI is stuck */
2745 if (sky2->check.last == dev->last_rx &&
2746 ((mac_rp == sky2->check.mac_rp &&
2747 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2748 /* Check if the PCI RX hang */
2749 (fifo_rp == sky2->check.fifo_rp &&
2750 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2751 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2752 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2753 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2754 return 1;
2755 } else {
2756 sky2->check.last = dev->last_rx;
2757 sky2->check.mac_rp = mac_rp;
2758 sky2->check.mac_lev = mac_lev;
2759 sky2->check.fifo_rp = fifo_rp;
2760 sky2->check.fifo_lev = fifo_lev;
2761 return 0;
2762 }
2763}
2764
32c2c300 2765static void sky2_watchdog(unsigned long arg)
d27ed387 2766{
01bd7564 2767 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2768
75e80683 2769 /* Check for lost IRQ once a second */
32c2c300 2770 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2771 napi_schedule(&hw->napi);
75e80683
SH		 2772 } else {
2773 int i, active = 0;
2774
2775 for (i = 0; i < hw->ports; i++) {
bea3348e 2776 struct net_device *dev = hw->dev[i];
75e80683
SH		 2777 if (!netif_running(dev))
2778 continue;
2779 ++active;
2780
2781 /* For chips with Rx FIFO, check if stuck */
39dbd958 2782 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2783 sky2_rx_hung(dev)) {
2784 pr_info(PFX "%s: receiver hang detected\n",
2785 dev->name);
2786 schedule_work(&hw->restart_work);
2787 return;
2788 }
2789 }
2790
2791 if (active == 0)
2792 return;
32c2c300 2793 }
01bd7564 2794
75e80683 2795 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2796}
2797
40b01727
SH		 2798/* Hardware/software error handling */
2799static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2800{
40b01727
SH		 2801 if (net_ratelimit())
2802 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2803
1e5f1283
SH		 2804 if (status & Y2_IS_HW_ERR)
2805 sky2_hw_intr(hw);
d257924e 2806
1e5f1283
SH		 2807 if (status & Y2_IS_IRQ_MAC1)
2808 sky2_mac_intr(hw, 0);
cd28ab6a 2809
1e5f1283
SH		 2810 if (status & Y2_IS_IRQ_MAC2)
2811 sky2_mac_intr(hw, 1);
cd28ab6a 2812
1e5f1283 2813 if (status & Y2_IS_CHK_RX1)
c119731d 2814 sky2_le_error(hw, 0, Q_R1);
d257924e 2815
1e5f1283 2816 if (status & Y2_IS_CHK_RX2)
c119731d 2817 sky2_le_error(hw, 1, Q_R2);
d257924e 2818
1e5f1283 2819 if (status & Y2_IS_CHK_TXA1)
c119731d 2820 sky2_le_error(hw, 0, Q_XA1);
d257924e 2821
1e5f1283 2822 if (status & Y2_IS_CHK_TXA2)
c119731d 2823 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2824}
2825
bea3348e 2826static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2827{
bea3348e 2828 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2829 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2830 int work_done = 0;
26691830 2831 u16 idx;
40b01727
SH		 2832
2833 if (unlikely(status & Y2_IS_ERROR))
2834 sky2_err_intr(hw, status);
2835
2836 if (status & Y2_IS_IRQ_PHY1)
2837 sky2_phy_intr(hw, 0);
2838
2839 if (status & Y2_IS_IRQ_PHY2)
2840 sky2_phy_intr(hw, 1);
cd28ab6a 2841
0f5aac70
SH		 2842 if (status & Y2_IS_PHY_QLNK)
2843 sky2_qlink_intr(hw);
2844
26691830
SH		 2845 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2846 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2847
2848 if (work_done >= work_limit)
26691830
SH		 2849 goto done;
2850 }
6f535763 2851
26691830
SH		 2852 napi_complete(napi);
2853 sky2_read32(hw, B0_Y2_SP_LISR);
2854done:
6f535763 2855
bea3348e 2856 return work_done;
e07b1aa8
SH		 2857}
2858
7d12e780 2859static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2860{
2861 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2862 u32 status;
2863
2864 /* Reading this mask interrupts as side effect */
2865 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2866 if (status == 0 || status == ~0)
2867 return IRQ_NONE;
793b883e 2868
e07b1aa8 2869 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2870
2871 napi_schedule(&hw->napi);
793b883e 2872
cd28ab6a
SH		 2873 return IRQ_HANDLED;
2874}
2875
2876#ifdef CONFIG_NET_POLL_CONTROLLER
2877static void sky2_netpoll(struct net_device *dev)
2878{
2879 struct sky2_port *sky2 = netdev_priv(dev);
2880
bea3348e 2881 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2882}
2883#endif
2884
2885/* Chip internal frequency for clock calculations */
05745c4a 2886static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2887{
793b883e 2888 switch (hw->chip_id) {
cd28ab6a 2889 case CHIP_ID_YUKON_EC:
5a5b1ea0 2890 case CHIP_ID_YUKON_EC_U:
93745494 2891 case CHIP_ID_YUKON_EX:
ed4d4161 2892 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2893 case CHIP_ID_YUKON_UL_2:
0f5aac70 2894 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2895 return 125;
2896
cd28ab6a 2897 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2898 return 100;
2899
2900 case CHIP_ID_YUKON_FE_P:
2901 return 50;
2902
2903 case CHIP_ID_YUKON_XL:
2904 return 156;
2905
2906 default:
2907 BUG();
cd28ab6a
SH		 2908 }
2909}
2910
fb17358f 2911static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2912{
fb17358f 2913 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2914}
2915
fb17358f 2916static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2917{
fb17358f 2918 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2919}
2920
fb17358f 2921
e3173832 2922static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2923{
b89165f2 2924 u8 t8;
cd28ab6a 2925
167f53d0 2926 /* Enable all clocks and check for bad PCI access */
b32f40c4 2927 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2928
cd28ab6a 2929 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2930
cd28ab6a 2931 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2932 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2933
2934 switch(hw->chip_id) {
2935 case CHIP_ID_YUKON_XL:
39dbd958 2936 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2937 break;
2938
2939 case CHIP_ID_YUKON_EC_U:
2940 hw->flags = SKY2_HW_GIGABIT
2941 | SKY2_HW_NEWER_PHY
2942 | SKY2_HW_ADV_POWER_CTL;
2943 break;
2944
2945 case CHIP_ID_YUKON_EX:
2946 hw->flags = SKY2_HW_GIGABIT
2947 | SKY2_HW_NEWER_PHY
2948 | SKY2_HW_NEW_LE
2949 | SKY2_HW_ADV_POWER_CTL;
2950
2951 /* New transmit checksum */
2952 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2953 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2954 break;
2955
2956 case CHIP_ID_YUKON_EC:
2957 /* This rev is really old, and requires untested workarounds */
2958 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2959 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2960 return -EOPNOTSUPP;
2961 }
39dbd958 2962 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2963 break;
2964
2965 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2966 break;
2967
05745c4a
SH		 2968 case CHIP_ID_YUKON_FE_P:
2969 hw->flags = SKY2_HW_NEWER_PHY
2970 | SKY2_HW_NEW_LE
2971 | SKY2_HW_AUTO_TX_SUM
2972 | SKY2_HW_ADV_POWER_CTL;
2973 break;
ed4d4161
SH		 2974
2975 case CHIP_ID_YUKON_SUPR:
2976 hw->flags = SKY2_HW_GIGABIT
2977 | SKY2_HW_NEWER_PHY
2978 | SKY2_HW_NEW_LE
2979 | SKY2_HW_AUTO_TX_SUM
2980 | SKY2_HW_ADV_POWER_CTL;
2981 break;
2982
0ce8b98d 2983 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 2984 hw->flags = SKY2_HW_GIGABIT
2985 | SKY2_HW_ADV_POWER_CTL;
2986 break;
2987
0f5aac70 2988 case CHIP_ID_YUKON_OPT:
0ce8b98d 2989 hw->flags = SKY2_HW_GIGABIT
b338682d 2990 | SKY2_HW_NEW_LE
0ce8b98d
SH		 2991 | SKY2_HW_ADV_POWER_CTL;
2992 break;
2993
ea76e635 2994 default:
b02a9258
SH		 2995 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2996 hw->chip_id);
cd28ab6a
SH		 2997 return -EOPNOTSUPP;
2998 }
2999
ea76e635
SH		 3000 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3001 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3002 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3003
e3173832
SH		 3004 hw->ports = 1;
3005 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3006 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3007 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3008 ++hw->ports;
3009 }
3010
74a61ebf
MM		 3011 if (sky2_read8(hw, B2_E_0))
3012 hw->flags |= SKY2_HW_RAM_BUFFER;
3013
e3173832
SH		 3014 return 0;
3015}
3016
3017static void sky2_reset(struct sky2_hw *hw)
3018{
555382cb 3019 struct pci_dev *pdev = hw->pdev;
e3173832 3020 u16 status;
555382cb
SH		 3021 int i, cap;
3022 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3023
cd28ab6a 3024 /* disable ASF */
acd12dde 3025 if (hw->chip_id == CHIP_ID_YUKON_EX
3026 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3027 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3028 status = sky2_read16(hw, HCU_CCSR);
3029 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3030 HCU_CCSR_UC_STATE_MSK);
acd12dde 3031 /*
3032 * CPU clock divider shouldn't be used because
3033 * - ASF firmware may malfunction
3034 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3035 */
3036 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3037 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3038 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3039 } else
3040 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3041 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3042
3043 /* do a SW reset */
3044 sky2_write8(hw, B0_CTST, CS_RST_SET);
3045 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3046
ac93a394
SH		 3047 /* allow writes to PCI config */
3048 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3049
cd28ab6a 3050 /* clear PCI errors, if any */
b32f40c4 3051 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3052 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3053 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3054
3055 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3056
555382cb
SH		 3057 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3058 if (cap) {
7782c8c4
SH		 3059 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3060 0xfffffffful);
555382cb
SH		 3061
3062 /* If error bit is stuck on ignore it */
3063 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3064 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3065 else
555382cb
SH		 3066 hwe_mask |= Y2_IS_PCI_EXP;
3067 }
cd28ab6a 3068
ae306cca 3069 sky2_power_on(hw);
a40ccc68 3070 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3071
3072 for (i = 0; i < hw->ports; i++) {
3073 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3074 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3075
ed4d4161
SH		 3076 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3077 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3078 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3079 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3080 | GMC_BYP_RETR_ON);
877c8570
SH		 3081
3082 }
3083
3084 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3085 /* enable MACSec clock gating */
3086 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3087 }
3088
0f5aac70
SH		 3089 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3090 u16 reg;
3091 u32 msk;
3092
3093 if (hw->chip_rev == 0) {
3094 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3095 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3096
3097 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3098 reg = 10;
3099 } else {
3100 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3101 reg = 3;
3102 }
3103
3104 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3105
3106 /* reset PHY Link Detect */
a40ccc68 3107 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3108 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3109 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3110 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3111
3112
3113 /* enable PHY Quick Link */
3114 msk = sky2_read32(hw, B0_IMSK);
3115 msk |= Y2_IS_PHY_QLNK;
3116 sky2_write32(hw, B0_IMSK, msk);
3117
3118 /* check if PSMv2 was running before */
3119 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3120 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3121 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3122 /* restore the PCIe Link Control register */
3123 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3124 }
a40ccc68 3125 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3126
3127 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3128 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3129 }
3130
793b883e
SH		 3131 /* Clear I2C IRQ noise */
3132 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3133
3134 /* turn off hardware timer (unused) */
3135 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3136 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3137
69634ee7
SH		 3138 /* Turn off descriptor polling */
3139 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3140
3141 /* Turn off receive timestamp */
3142 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3143 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3144
3145 /* enable the Tx Arbiters */
3146 for (i = 0; i < hw->ports; i++)
3147 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3148
3149 /* Initialize ram interface */
3150 for (i = 0; i < hw->ports; i++) {
793b883e 3151 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3152
3153 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3154 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3155 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3156 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3157 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3158 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3159 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3160 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3161 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3162 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3163 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3164 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3165 }
3166
555382cb 3167 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3168
cd28ab6a 3169 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3170 sky2_gmac_reset(hw, i);
cd28ab6a 3171
cd28ab6a
SH		 3172 memset(hw->st_le, 0, STATUS_LE_BYTES);
3173 hw->st_idx = 0;
3174
3175 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3176 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3177
3178 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3179 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3180
3181 /* Set the list last index */
793b883e 3182 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3183
290d4de5
SH		 3184 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3185 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3186
290d4de5
SH		 3187 /* set Status-FIFO ISR watermark */
3188 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3189 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3190 else
3191 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3192
290d4de5 3193 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3194 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3195 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3196
793b883e 3197 /* enable status unit */
cd28ab6a
SH		 3198 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3199
3200 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3201 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3202 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3203}
3204
af18d8b8
SH		 3205/* Take device down (offline).
3206 * Equivalent to doing dev_stop() but this does not
3207 * inform upper layers of the transistion.
3208 */
3209static void sky2_detach(struct net_device *dev)
3210{
3211 if (netif_running(dev)) {
c36531b9 3212 netif_tx_lock(dev);
af18d8b8 3213 netif_device_detach(dev); /* stop txq */
c36531b9 3214 netif_tx_unlock(dev);
af18d8b8
SH		 3215 sky2_down(dev);
3216 }
3217}
3218
3219/* Bring device back after doing sky2_detach */
3220static int sky2_reattach(struct net_device *dev)
3221{
3222 int err = 0;
3223
3224 if (netif_running(dev)) {
3225 err = sky2_up(dev);
3226 if (err) {
3227 printk(KERN_INFO PFX "%s: could not restart %d\n",
3228 dev->name, err);
3229 dev_close(dev);
3230 } else {
3231 netif_device_attach(dev);
3232 sky2_set_multicast(dev);
3233 }
3234 }
3235
3236 return err;
3237}
3238
81906791
SH		 3239static void sky2_restart(struct work_struct *work)
3240{
3241 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3242 int i;
81906791 3243
81906791 3244 rtnl_lock();
af18d8b8
SH		 3245 for (i = 0; i < hw->ports; i++)
3246 sky2_detach(hw->dev[i]);
81906791 3247
8cfcbe99
SH		 3248 napi_disable(&hw->napi);
3249 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3250 sky2_reset(hw);
3251 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3252 napi_enable(&hw->napi);
81906791 3253
af18d8b8
SH		 3254 for (i = 0; i < hw->ports; i++)
3255 sky2_reattach(hw->dev[i]);
81906791 3256
81906791
SH		 3257 rtnl_unlock();
3258}
3259
e3173832
SH		 3260static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3261{
3262 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3263}
3264
3265static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3266{
3267 const struct sky2_port *sky2 = netdev_priv(dev);
3268
3269 wol->supported = sky2_wol_supported(sky2->hw);
3270 wol->wolopts = sky2->wol;
3271}
3272
3273static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3274{
3275 struct sky2_port *sky2 = netdev_priv(dev);
3276 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3277
8e95a202
JP		 3278 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3279 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3280 return -EOPNOTSUPP;
3281
3282 sky2->wol = wol->wolopts;
cd28ab6a
SH		 3283 return 0;
3284}
3285
28bd181a 3286static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3287{
b89165f2
SH		 3288 if (sky2_is_copper(hw)) {
3289 u32 modes = SUPPORTED_10baseT_Half
3290 | SUPPORTED_10baseT_Full
3291 | SUPPORTED_100baseT_Half
3292 | SUPPORTED_100baseT_Full
3293 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3294
ea76e635 3295 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3296 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3297 | SUPPORTED_1000baseT_Full;
3298 return modes;
cd28ab6a 3299 } else
b89165f2
SH		 3300 return SUPPORTED_1000baseT_Half
3301 | SUPPORTED_1000baseT_Full
3302 | SUPPORTED_Autoneg
3303 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3304}
3305
793b883e 3306static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3307{
3308 struct sky2_port *sky2 = netdev_priv(dev);
3309 struct sky2_hw *hw = sky2->hw;
3310
3311 ecmd->transceiver = XCVR_INTERNAL;
3312 ecmd->supported = sky2_supported_modes(hw);
3313 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3314 if (sky2_is_copper(hw)) {
cd28ab6a 3315 ecmd->port = PORT_TP;
b89165f2
SH		 3316 ecmd->speed = sky2->speed;
3317 } else {
3318 ecmd->speed = SPEED_1000;
cd28ab6a 3319 ecmd->port = PORT_FIBRE;
b89165f2 3320 }
cd28ab6a
SH		 3321
3322 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3323 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3324 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3325 ecmd->duplex = sky2->duplex;
3326 return 0;
3327}
3328
3329static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3330{
3331 struct sky2_port *sky2 = netdev_priv(dev);
3332 const struct sky2_hw *hw = sky2->hw;
3333 u32 supported = sky2_supported_modes(hw);
3334
3335 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3336 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3337 ecmd->advertising = supported;
3338 sky2->duplex = -1;
3339 sky2->speed = -1;
3340 } else {
3341 u32 setting;
3342
793b883e 3343 switch (ecmd->speed) {
cd28ab6a
SH		 3344 case SPEED_1000:
3345 if (ecmd->duplex == DUPLEX_FULL)
3346 setting = SUPPORTED_1000baseT_Full;
3347 else if (ecmd->duplex == DUPLEX_HALF)
3348 setting = SUPPORTED_1000baseT_Half;
3349 else
3350 return -EINVAL;
3351 break;
3352 case SPEED_100:
3353 if (ecmd->duplex == DUPLEX_FULL)
3354 setting = SUPPORTED_100baseT_Full;
3355 else if (ecmd->duplex == DUPLEX_HALF)
3356 setting = SUPPORTED_100baseT_Half;
3357 else
3358 return -EINVAL;
3359 break;
3360
3361 case SPEED_10:
3362 if (ecmd->duplex == DUPLEX_FULL)
3363 setting = SUPPORTED_10baseT_Full;
3364 else if (ecmd->duplex == DUPLEX_HALF)
3365 setting = SUPPORTED_10baseT_Half;
3366 else
3367 return -EINVAL;
3368 break;
3369 default:
3370 return -EINVAL;
3371 }
3372
3373 if ((setting & supported) == 0)
3374 return -EINVAL;
3375
3376 sky2->speed = ecmd->speed;
3377 sky2->duplex = ecmd->duplex;
0ea065e5 3378 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3379 }
3380
cd28ab6a
SH		 3381 sky2->advertising = ecmd->advertising;
3382
d1b139c0 3383 if (netif_running(dev)) {
1b537565 3384 sky2_phy_reinit(sky2);
d1b139c0
SH		 3385 sky2_set_multicast(dev);
3386 }
cd28ab6a
SH		 3387
3388 return 0;
3389}
3390
3391static void sky2_get_drvinfo(struct net_device *dev,
3392 struct ethtool_drvinfo *info)
3393{
3394 struct sky2_port *sky2 = netdev_priv(dev);
3395
3396 strcpy(info->driver, DRV_NAME);
3397 strcpy(info->version, DRV_VERSION);
3398 strcpy(info->fw_version, "N/A");
3399 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3400}
3401
3402static const struct sky2_stat {
793b883e
SH		 3403 char name[ETH_GSTRING_LEN];
3404 u16 offset;
cd28ab6a
SH		 3405} sky2_stats[] = {
3406 { "tx_bytes", GM_TXO_OK_HI },
3407 { "rx_bytes", GM_RXO_OK_HI },
3408 { "tx_broadcast", GM_TXF_BC_OK },
3409 { "rx_broadcast", GM_RXF_BC_OK },
3410 { "tx_multicast", GM_TXF_MC_OK },
3411 { "rx_multicast", GM_RXF_MC_OK },
3412 { "tx_unicast", GM_TXF_UC_OK },
3413 { "rx_unicast", GM_RXF_UC_OK },
3414 { "tx_mac_pause", GM_TXF_MPAUSE },
3415 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3416 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3417 { "late_collision",GM_TXF_LAT_COL },
3418 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3419 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3420 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3421
d2604540 3422 { "rx_short", GM_RXF_SHT },
cd28ab6a 3423 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3424 { "rx_64_byte_packets", GM_RXF_64B },
3425 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3426 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3427 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3428 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3429 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3430 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3431 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3432 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3433 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3434 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3435
3436 { "tx_64_byte_packets", GM_TXF_64B },
3437 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3438 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3439 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3440 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3441 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3442 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3443 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3444};
3445
cd28ab6a
SH		 3446static u32 sky2_get_rx_csum(struct net_device *dev)
3447{
3448 struct sky2_port *sky2 = netdev_priv(dev);
3449
0ea065e5 3450 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3451}
3452
3453static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3454{
3455 struct sky2_port *sky2 = netdev_priv(dev);
3456
0ea065e5
SH		 3457 if (data)
3458 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3459 else
3460 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3461
cd28ab6a
SH		 3462 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3463 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3464
3465 return 0;
3466}
3467
3468static u32 sky2_get_msglevel(struct net_device *netdev)
3469{
3470 struct sky2_port *sky2 = netdev_priv(netdev);
3471 return sky2->msg_enable;
3472}
3473
9a7ae0a9
SH		 3474static int sky2_nway_reset(struct net_device *dev)
3475{
3476 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3477
0ea065e5 3478 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3479 return -EINVAL;
3480
1b537565 3481 sky2_phy_reinit(sky2);
d1b139c0 3482 sky2_set_multicast(dev);
9a7ae0a9
SH		 3483
3484 return 0;
3485}
3486
793b883e 3487static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3488{
3489 struct sky2_hw *hw = sky2->hw;
3490 unsigned port = sky2->port;
3491 int i;
3492
3493 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3494 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3495 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3496 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3497
793b883e 3498 for (i = 2; i < count; i++)
cd28ab6a
SH		 3499 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3500}
3501
cd28ab6a
SH		 3502static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3503{
3504 struct sky2_port *sky2 = netdev_priv(netdev);
3505 sky2->msg_enable = value;
3506}
3507
b9f2c044 3508static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3509{
b9f2c044
JG		 3510 switch (sset) {
3511 case ETH_SS_STATS:
3512 return ARRAY_SIZE(sky2_stats);
3513 default:
3514 return -EOPNOTSUPP;
3515 }
cd28ab6a
SH		 3516}
3517
3518static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3519 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3520{
3521 struct sky2_port *sky2 = netdev_priv(dev);
3522
793b883e 3523 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3524}
3525
793b883e 3526static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3527{
3528 int i;
3529
3530 switch (stringset) {
3531 case ETH_SS_STATS:
3532 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3533 memcpy(data + i * ETH_GSTRING_LEN,
3534 sky2_stats[i].name, ETH_GSTRING_LEN);
3535 break;
3536 }
3537}
3538
cd28ab6a
SH		 3539static int sky2_set_mac_address(struct net_device *dev, void *p)
3540{
3541 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3542 struct sky2_hw *hw = sky2->hw;
3543 unsigned port = sky2->port;
3544 const struct sockaddr *addr = p;
cd28ab6a
SH		 3545
3546 if (!is_valid_ether_addr(addr->sa_data))
3547 return -EADDRNOTAVAIL;
3548
cd28ab6a 3549 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3550 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3551 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3552 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3553 dev->dev_addr, ETH_ALEN);
1b537565 3554
a8ab1ec0
SH		 3555 /* virtual address for data */
3556 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3557
3558 /* physical address: used for pause frames */
3559 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3560
3561 return 0;
cd28ab6a
SH		 3562}
3563
a052b52f
SH		 3564static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3565{
3566 u32 bit;
3567
3568 bit = ether_crc(ETH_ALEN, addr) & 63;
3569 filter[bit >> 3] |= 1 << (bit & 7);
3570}
3571
cd28ab6a
SH		 3572static void sky2_set_multicast(struct net_device *dev)
3573{
3574 struct sky2_port *sky2 = netdev_priv(dev);
3575 struct sky2_hw *hw = sky2->hw;
3576 unsigned port = sky2->port;
3577 struct dev_mc_list *list = dev->mc_list;
3578 u16 reg;
3579 u8 filter[8];
a052b52f
SH		 3580 int rx_pause;
3581 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3582
a052b52f 3583 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3584 memset(filter, 0, sizeof(filter));
3585
3586 reg = gma_read16(hw, port, GM_RX_CTRL);
3587 reg |= GM_RXCR_UCF_ENA;
3588
d571b694 3589 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3590 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3591 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3592 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3593 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3594 reg &= ~GM_RXCR_MCF_ENA;
3595 else {
3596 int i;
3597 reg |= GM_RXCR_MCF_ENA;
3598
a052b52f
SH		 3599 if (rx_pause)
3600 sky2_add_filter(filter, pause_mc_addr);
3601
4cd24eaf 3602 for (i = 0; list && i < netdev_mc_count(dev); i++, list = list->next)
a052b52f 3603 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3604 }
3605
cd28ab6a 3606 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3607 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3608 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3609 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3610 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3611 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3612 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3613 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3614
3615 gma_write16(hw, port, GM_RX_CTRL, reg);
3616}
3617
3618/* Can have one global because blinking is controlled by
3619 * ethtool and that is always under RTNL mutex
3620 */
a84d0a3d 3621static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3622{
a84d0a3d
SH		 3623 struct sky2_hw *hw = sky2->hw;
3624 unsigned port = sky2->port;
793b883e 3625
a84d0a3d
SH		 3626 spin_lock_bh(&sky2->phy_lock);
3627 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3628 hw->chip_id == CHIP_ID_YUKON_EX ||
3629 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3630 u16 pg;
793b883e
SH		 3631 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3632 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3633
a84d0a3d
SH		 3634 switch (mode) {
3635 case MO_LED_OFF:
3636 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3637 PHY_M_LEDC_LOS_CTRL(8) |
3638 PHY_M_LEDC_INIT_CTRL(8) |
3639 PHY_M_LEDC_STA1_CTRL(8) |
3640 PHY_M_LEDC_STA0_CTRL(8));
3641 break;
3642 case MO_LED_ON:
3643 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3644 PHY_M_LEDC_LOS_CTRL(9) |
3645 PHY_M_LEDC_INIT_CTRL(9) |
3646 PHY_M_LEDC_STA1_CTRL(9) |
3647 PHY_M_LEDC_STA0_CTRL(9));
3648 break;
3649 case MO_LED_BLINK:
3650 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3651 PHY_M_LEDC_LOS_CTRL(0xa) |
3652 PHY_M_LEDC_INIT_CTRL(0xa) |
3653 PHY_M_LEDC_STA1_CTRL(0xa) |
3654 PHY_M_LEDC_STA0_CTRL(0xa));
3655 break;
3656 case MO_LED_NORM:
3657 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3658 PHY_M_LEDC_LOS_CTRL(1) |
3659 PHY_M_LEDC_INIT_CTRL(8) |
3660 PHY_M_LEDC_STA1_CTRL(7) |
3661 PHY_M_LEDC_STA0_CTRL(7));
3662 }
793b883e 3663
a84d0a3d
SH		 3664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3665 } else
7d2e3cb7 3666 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3667 PHY_M_LED_MO_DUP(mode) |
3668 PHY_M_LED_MO_10(mode) |
3669 PHY_M_LED_MO_100(mode) |
3670 PHY_M_LED_MO_1000(mode) |
3671 PHY_M_LED_MO_RX(mode) |
3672 PHY_M_LED_MO_TX(mode));
3673
3674 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3675}
3676
3677/* blink LED's for finding board */
3678static int sky2_phys_id(struct net_device *dev, u32 data)
3679{
3680 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3681 unsigned int i;
cd28ab6a 3682
a84d0a3d
SH		 3683 if (data == 0)
3684 data = UINT_MAX;
cd28ab6a 3685
a84d0a3d
SH		 3686 for (i = 0; i < data; i++) {
3687 sky2_led(sky2, MO_LED_ON);
3688 if (msleep_interruptible(500))
3689 break;
3690 sky2_led(sky2, MO_LED_OFF);
3691 if (msleep_interruptible(500))
3692 break;
793b883e 3693 }
a84d0a3d 3694 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3695
3696 return 0;
3697}
3698
3699static void sky2_get_pauseparam(struct net_device *dev,
3700 struct ethtool_pauseparam *ecmd)
3701{
3702 struct sky2_port *sky2 = netdev_priv(dev);
3703
16ad91e1
SH		 3704 switch (sky2->flow_mode) {
3705 case FC_NONE:
3706 ecmd->tx_pause = ecmd->rx_pause = 0;
3707 break;
3708 case FC_TX:
3709 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3710 break;
3711 case FC_RX:
3712 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3713 break;
3714 case FC_BOTH:
3715 ecmd->tx_pause = ecmd->rx_pause = 1;
3716 }
3717
0ea065e5
SH		 3718 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3719 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3720}
3721
3722static int sky2_set_pauseparam(struct net_device *dev,
3723 struct ethtool_pauseparam *ecmd)
3724{
3725 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3726
0ea065e5
SH		 3727 if (ecmd->autoneg == AUTONEG_ENABLE)
3728 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3729 else
3730 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3731
16ad91e1 3732 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3733
16ad91e1
SH		 3734 if (netif_running(dev))
3735 sky2_phy_reinit(sky2);
cd28ab6a 3736
2eaba1a2 3737 return 0;
cd28ab6a
SH		 3738}
3739
fb17358f
SH		 3740static int sky2_get_coalesce(struct net_device *dev,
3741 struct ethtool_coalesce *ecmd)
3742{
3743 struct sky2_port *sky2 = netdev_priv(dev);
3744 struct sky2_hw *hw = sky2->hw;
3745
3746 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3747 ecmd->tx_coalesce_usecs = 0;
3748 else {
3749 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3750 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3751 }
3752 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3753
3754 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3755 ecmd->rx_coalesce_usecs = 0;
3756 else {
3757 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3758 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3759 }
3760 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3761
3762 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3763 ecmd->rx_coalesce_usecs_irq = 0;
3764 else {
3765 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3766 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3767 }
3768
3769 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3770
3771 return 0;
3772}
3773
3774/* Note: this affect both ports */
3775static int sky2_set_coalesce(struct net_device *dev,
3776 struct ethtool_coalesce *ecmd)
3777{
3778 struct sky2_port *sky2 = netdev_priv(dev);
3779 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3780 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3781
77b3d6a2
SH		 3782 if (ecmd->tx_coalesce_usecs > tmax ||
3783 ecmd->rx_coalesce_usecs > tmax ||
3784 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3785 return -EINVAL;
3786
ee5f68fe 3787 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3788 return -EINVAL;
ff81fbbe 3789 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3790 return -EINVAL;
ff81fbbe 3791 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3792 return -EINVAL;
3793
3794 if (ecmd->tx_coalesce_usecs == 0)
3795 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3796 else {
3797 sky2_write32(hw, STAT_TX_TIMER_INI,
3798 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3799 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3800 }
3801 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3802
3803 if (ecmd->rx_coalesce_usecs == 0)
3804 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3805 else {
3806 sky2_write32(hw, STAT_LEV_TIMER_INI,
3807 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3808 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3809 }
3810 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3811
3812 if (ecmd->rx_coalesce_usecs_irq == 0)
3813 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3814 else {
d28d4870 3815 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3816 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3817 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3818 }
3819 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3820 return 0;
3821}
3822
793b883e
SH		 3823static void sky2_get_ringparam(struct net_device *dev,
3824 struct ethtool_ringparam *ering)
3825{
3826 struct sky2_port *sky2 = netdev_priv(dev);
3827
3828 ering->rx_max_pending = RX_MAX_PENDING;
3829 ering->rx_mini_max_pending = 0;
3830 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3831 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3832
3833 ering->rx_pending = sky2->rx_pending;
3834 ering->rx_mini_pending = 0;
3835 ering->rx_jumbo_pending = 0;
3836 ering->tx_pending = sky2->tx_pending;
3837}
3838
3839static int sky2_set_ringparam(struct net_device *dev,
3840 struct ethtool_ringparam *ering)
3841{
3842 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3843
3844 if (ering->rx_pending > RX_MAX_PENDING ||
3845 ering->rx_pending < 8 ||
ee5f68fe
SH		 3846 ering->tx_pending < TX_MIN_PENDING ||
3847 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3848 return -EINVAL;
3849
af18d8b8 3850 sky2_detach(dev);
793b883e
SH		 3851
3852 sky2->rx_pending = ering->rx_pending;
3853 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3854 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3855
af18d8b8 3856 return sky2_reattach(dev);
793b883e
SH		 3857}
3858
793b883e
SH		 3859static int sky2_get_regs_len(struct net_device *dev)
3860{
6e4cbb34 3861 return 0x4000;
793b883e
SH		 3862}
3863
c32bbff8
MM		 3864static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3865{
3866 /* This complicated switch statement is to make sure and
3867 * only access regions that are unreserved.
3868 * Some blocks are only valid on dual port cards.
3869 */
3870 switch (b) {
3871 /* second port */
3872 case 5: /* Tx Arbiter 2 */
3873 case 9: /* RX2 */
3874 case 14 ... 15: /* TX2 */
3875 case 17: case 19: /* Ram Buffer 2 */
3876 case 22 ... 23: /* Tx Ram Buffer 2 */
3877 case 25: /* Rx MAC Fifo 1 */
3878 case 27: /* Tx MAC Fifo 2 */
3879 case 31: /* GPHY 2 */
3880 case 40 ... 47: /* Pattern Ram 2 */
3881 case 52: case 54: /* TCP Segmentation 2 */
3882 case 112 ... 116: /* GMAC 2 */
3883 return hw->ports > 1;
3884
3885 case 0: /* Control */
3886 case 2: /* Mac address */
3887 case 4: /* Tx Arbiter 1 */
3888 case 7: /* PCI express reg */
3889 case 8: /* RX1 */
3890 case 12 ... 13: /* TX1 */
3891 case 16: case 18:/* Rx Ram Buffer 1 */
3892 case 20 ... 21: /* Tx Ram Buffer 1 */
3893 case 24: /* Rx MAC Fifo 1 */
3894 case 26: /* Tx MAC Fifo 1 */
3895 case 28 ... 29: /* Descriptor and status unit */
3896 case 30: /* GPHY 1*/
3897 case 32 ... 39: /* Pattern Ram 1 */
3898 case 48: case 50: /* TCP Segmentation 1 */
3899 case 56 ... 60: /* PCI space */
3900 case 80 ... 84: /* GMAC 1 */
3901 return 1;
3902
3903 default:
3904 return 0;
3905 }
3906}
3907
793b883e
SH		 3908/*
3909 * Returns copy of control register region
3ead5db7 3910 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3911 */
3912static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3913 void *p)
3914{
3915 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3916 const void __iomem *io = sky2->hw->regs;
295b54c4 3917 unsigned int b;
793b883e
SH		 3918
3919 regs->version = 1;
793b883e 3920
295b54c4 3921 for (b = 0; b < 128; b++) {
c32bbff8
MM		 3922 /* skip poisonous diagnostic ram region in block 3 */
3923 if (b == 3)
295b54c4 3924 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 3925 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 3926 memcpy_fromio(p, io, 128);
c32bbff8 3927 else
295b54c4 3928 memset(p, 0, 128);
3ead5db7 3929
295b54c4
SH		 3930 p += 128;
3931 io += 128;
3932 }
793b883e 3933}
cd28ab6a 3934
b628ed98
SH		 3935/* In order to do Jumbo packets on these chips, need to turn off the
3936 * transmit store/forward. Therefore checksum offload won't work.
3937 */
3938static int no_tx_offload(struct net_device *dev)
3939{
3940 const struct sky2_port *sky2 = netdev_priv(dev);
3941 const struct sky2_hw *hw = sky2->hw;
3942
69161611 3943 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3944}
3945
3946static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3947{
3948 if (data && no_tx_offload(dev))
3949 return -EINVAL;
3950
3951 return ethtool_op_set_tx_csum(dev, data);
3952}
3953
3954
3955static int sky2_set_tso(struct net_device *dev, u32 data)
3956{
3957 if (data && no_tx_offload(dev))
3958 return -EINVAL;
3959
3960 return ethtool_op_set_tso(dev, data);
3961}
3962
f4331a6d
SH		 3963static int sky2_get_eeprom_len(struct net_device *dev)
3964{
3965 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3966 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3967 u16 reg2;
3968
b32f40c4 3969 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3970 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3971}
3972
1413235c 3973static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3974{
1413235c 3975 unsigned long start = jiffies;
f4331a6d 3976
1413235c
SH		 3977 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3978 /* Can take up to 10.6 ms for write */
3979 if (time_after(jiffies, start + HZ/4)) {
3980 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3981 return -ETIMEDOUT;
3982 }
3983 mdelay(1);
3984 }
167f53d0 3985
1413235c
SH		 3986 return 0;
3987}
167f53d0 3988
1413235c
SH		 3989static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3990 u16 offset, size_t length)
3991{
3992 int rc = 0;
3993
3994 while (length > 0) {
3995 u32 val;
3996
3997 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3998 rc = sky2_vpd_wait(hw, cap, 0);
3999 if (rc)
4000 break;
4001
4002 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4003
4004 memcpy(data, &val, min(sizeof(val), length));
4005 offset += sizeof(u32);
4006 data += sizeof(u32);
4007 length -= sizeof(u32);
4008 }
4009
4010 return rc;
f4331a6d
SH		 4011}
4012
1413235c
SH		 4013static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4014 u16 offset, unsigned int length)
f4331a6d 4015{
1413235c
SH		 4016 unsigned int i;
4017 int rc = 0;
4018
4019 for (i = 0; i < length; i += sizeof(u32)) {
4020 u32 val = *(u32 *)(data + i);
4021
4022 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4023 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4024
4025 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4026 if (rc)
4027 break;
4028 }
4029 return rc;
f4331a6d
SH		 4030}
4031
4032static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4033 u8 *data)
4034{
4035 struct sky2_port *sky2 = netdev_priv(dev);
4036 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4037
4038 if (!cap)
4039 return -EINVAL;
4040
4041 eeprom->magic = SKY2_EEPROM_MAGIC;
4042
1413235c 4043 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4044}
4045
4046static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4047 u8 *data)
4048{
4049 struct sky2_port *sky2 = netdev_priv(dev);
4050 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4051
4052 if (!cap)
4053 return -EINVAL;
4054
4055 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4056 return -EINVAL;
4057
1413235c
SH		 4058 /* Partial writes not supported */
4059 if ((eeprom->offset & 3) || (eeprom->len & 3))
4060 return -EINVAL;
f4331a6d 4061
1413235c 4062 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4063}
4064
4065
7282d491 4066static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4067 .get_settings = sky2_get_settings,
4068 .set_settings = sky2_set_settings,
4069 .get_drvinfo = sky2_get_drvinfo,
4070 .get_wol = sky2_get_wol,
4071 .set_wol = sky2_set_wol,
4072 .get_msglevel = sky2_get_msglevel,
4073 .set_msglevel = sky2_set_msglevel,
4074 .nway_reset = sky2_nway_reset,
4075 .get_regs_len = sky2_get_regs_len,
4076 .get_regs = sky2_get_regs,
4077 .get_link = ethtool_op_get_link,
4078 .get_eeprom_len = sky2_get_eeprom_len,
4079 .get_eeprom = sky2_get_eeprom,
4080 .set_eeprom = sky2_set_eeprom,
f4331a6d 4081 .set_sg = ethtool_op_set_sg,
f4331a6d 4082 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4083 .set_tso = sky2_set_tso,
4084 .get_rx_csum = sky2_get_rx_csum,
4085 .set_rx_csum = sky2_set_rx_csum,
4086 .get_strings = sky2_get_strings,
4087 .get_coalesce = sky2_get_coalesce,
4088 .set_coalesce = sky2_set_coalesce,
4089 .get_ringparam = sky2_get_ringparam,
4090 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4091 .get_pauseparam = sky2_get_pauseparam,
4092 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4093 .phys_id = sky2_phys_id,
b9f2c044 4094 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4095 .get_ethtool_stats = sky2_get_ethtool_stats,
4096};
4097
3cf26753
SH		 4098#ifdef CONFIG_SKY2_DEBUG
4099
4100static struct dentry *sky2_debug;
4101
e4c2abe2
SH		 4102
4103/*
4104 * Read and parse the first part of Vital Product Data
4105 */
4106#define VPD_SIZE 128
4107#define VPD_MAGIC 0x82
4108
4109static const struct vpd_tag {
4110 char tag[2];
4111 char *label;
4112} vpd_tags[] = {
4113 { "PN", "Part Number" },
4114 { "EC", "Engineering Level" },
4115 { "MN", "Manufacturer" },
4116 { "SN", "Serial Number" },
4117 { "YA", "Asset Tag" },
4118 { "VL", "First Error Log Message" },
4119 { "VF", "Second Error Log Message" },
4120 { "VB", "Boot Agent ROM Configuration" },
4121 { "VE", "EFI UNDI Configuration" },
4122};
4123
4124static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4125{
4126 size_t vpd_size;
4127 loff_t offs;
4128 u8 len;
4129 unsigned char *buf;
4130 u16 reg2;
4131
4132 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4133 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4134
4135 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4136 buf = kmalloc(vpd_size, GFP_KERNEL);
4137 if (!buf) {
4138 seq_puts(seq, "no memory!\n");
4139 return;
4140 }
4141
4142 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4143 seq_puts(seq, "VPD read failed\n");
4144 goto out;
4145 }
4146
4147 if (buf[0] != VPD_MAGIC) {
4148 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4149 goto out;
4150 }
4151 len = buf[1];
4152 if (len == 0 || len > vpd_size - 4) {
4153 seq_printf(seq, "Invalid id length: %d\n", len);
4154 goto out;
4155 }
4156
4157 seq_printf(seq, "%.*s\n", len, buf + 3);
4158 offs = len + 3;
4159
4160 while (offs < vpd_size - 4) {
4161 int i;
4162
4163 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4164 break;
4165 len = buf[offs + 2];
4166 if (offs + len + 3 >= vpd_size)
4167 break;
4168
4169 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4170 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4171 seq_printf(seq, " %s: %.*s\n",
4172 vpd_tags[i].label, len, buf + offs + 3);
4173 break;
4174 }
4175 }
4176 offs += len + 3;
4177 }
4178out:
4179 kfree(buf);
4180}
4181
3cf26753
SH		 4182static int sky2_debug_show(struct seq_file *seq, void *v)
4183{
4184 struct net_device *dev = seq->private;
4185 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4186 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4187 unsigned port = sky2->port;
4188 unsigned idx, last;
4189 int sop;
4190
e4c2abe2 4191 sky2_show_vpd(seq, hw);
3cf26753 4192
e4c2abe2 4193 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4194 sky2_read32(hw, B0_ISRC),
4195 sky2_read32(hw, B0_IMSK),
4196 sky2_read32(hw, B0_Y2_SP_ICR));
4197
e4c2abe2
SH		 4198 if (!netif_running(dev)) {
4199 seq_printf(seq, "network not running\n");
4200 return 0;
4201 }
4202
bea3348e 4203 napi_disable(&hw->napi);
3cf26753
SH		 4204 last = sky2_read16(hw, STAT_PUT_IDX);
4205
4206 if (hw->st_idx == last)
4207 seq_puts(seq, "Status ring (empty)\n");
4208 else {
4209 seq_puts(seq, "Status ring\n");
4210 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4211 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4212 const struct sky2_status_le *le = hw->st_le + idx;
4213 seq_printf(seq, "[%d] %#x %d %#x\n",
4214 idx, le->opcode, le->length, le->status);
4215 }
4216 seq_puts(seq, "\n");
4217 }
4218
4219 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4220 sky2->tx_cons, sky2->tx_prod,
4221 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4222 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4223
4224 /* Dump contents of tx ring */
4225 sop = 1;
ee5f68fe
SH		 4226 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4227 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4228 const struct sky2_tx_le *le = sky2->tx_le + idx;
4229 u32 a = le32_to_cpu(le->addr);
4230
4231 if (sop)
4232 seq_printf(seq, "%u:", idx);
4233 sop = 0;
4234
4235 switch(le->opcode & ~HW_OWNER) {
4236 case OP_ADDR64:
4237 seq_printf(seq, " %#x:", a);
4238 break;
4239 case OP_LRGLEN:
4240 seq_printf(seq, " mtu=%d", a);
4241 break;
4242 case OP_VLAN:
4243 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4244 break;
4245 case OP_TCPLISW:
4246 seq_printf(seq, " csum=%#x", a);
4247 break;
4248 case OP_LARGESEND:
4249 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4250 break;
4251 case OP_PACKET:
4252 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4253 break;
4254 case OP_BUFFER:
4255 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4256 break;
4257 default:
4258 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4259 a, le16_to_cpu(le->length));
4260 }
4261
4262 if (le->ctrl & EOP) {
4263 seq_putc(seq, '\n');
4264 sop = 1;
4265 }
4266 }
4267
4268 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4269 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4270 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4271 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4272
d1d08d12 4273 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4274 napi_enable(&hw->napi);
3cf26753
SH		 4275 return 0;
4276}
4277
4278static int sky2_debug_open(struct inode *inode, struct file *file)
4279{
4280 return single_open(file, sky2_debug_show, inode->i_private);
4281}
4282
4283static const struct file_operations sky2_debug_fops = {
4284 .owner = THIS_MODULE,
4285 .open = sky2_debug_open,
4286 .read = seq_read,
4287 .llseek = seq_lseek,
4288 .release = single_release,
4289};
4290
4291/*
4292 * Use network device events to create/remove/rename
4293 * debugfs file entries
4294 */
4295static int sky2_device_event(struct notifier_block *unused,
4296 unsigned long event, void *ptr)
4297{
4298 struct net_device *dev = ptr;
5b296bc9 4299 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4300
1436b301 4301 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4302 return NOTIFY_DONE;
3cf26753 4303
5b296bc9
SH		 4304 switch(event) {
4305 case NETDEV_CHANGENAME:
4306 if (sky2->debugfs) {
4307 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4308 sky2_debug, dev->name);
4309 }
4310 break;
3cf26753 4311
5b296bc9
SH		 4312 case NETDEV_GOING_DOWN:
4313 if (sky2->debugfs) {
4314 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4315 dev->name);
4316 debugfs_remove(sky2->debugfs);
4317 sky2->debugfs = NULL;
3cf26753 4318 }
5b296bc9
SH		 4319 break;
4320
4321 case NETDEV_UP:
4322 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4323 sky2_debug, dev,
4324 &sky2_debug_fops);
4325 if (IS_ERR(sky2->debugfs))
4326 sky2->debugfs = NULL;
3cf26753
SH		 4327 }
4328
4329 return NOTIFY_DONE;
4330}
4331
4332static struct notifier_block sky2_notifier = {
4333 .notifier_call = sky2_device_event,
4334};
4335
4336
4337static __init void sky2_debug_init(void)
4338{
4339 struct dentry *ent;
4340
4341 ent = debugfs_create_dir("sky2", NULL);
4342 if (!ent || IS_ERR(ent))
4343 return;
4344
4345 sky2_debug = ent;
4346 register_netdevice_notifier(&sky2_notifier);
4347}
4348
4349static __exit void sky2_debug_cleanup(void)
4350{
4351 if (sky2_debug) {
4352 unregister_netdevice_notifier(&sky2_notifier);
4353 debugfs_remove(sky2_debug);
4354 sky2_debug = NULL;
4355 }
4356}
4357
4358#else
4359#define sky2_debug_init()
4360#define sky2_debug_cleanup()
4361#endif
4362
1436b301
SH		 4363/* Two copies of network device operations to handle special case of
4364 not allowing netpoll on second port */
4365static const struct net_device_ops sky2_netdev_ops[2] = {
4366 {
4367 .ndo_open = sky2_up,
4368 .ndo_stop = sky2_down,
00829823 4369 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4370 .ndo_do_ioctl = sky2_ioctl,
4371 .ndo_validate_addr = eth_validate_addr,
4372 .ndo_set_mac_address = sky2_set_mac_address,
4373 .ndo_set_multicast_list = sky2_set_multicast,
4374 .ndo_change_mtu = sky2_change_mtu,
4375 .ndo_tx_timeout = sky2_tx_timeout,
4376#ifdef SKY2_VLAN_TAG_USED
4377 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4378#endif
4379#ifdef CONFIG_NET_POLL_CONTROLLER
4380 .ndo_poll_controller = sky2_netpoll,
4381#endif
4382 },
4383 {
4384 .ndo_open = sky2_up,
4385 .ndo_stop = sky2_down,
00829823 4386 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4387 .ndo_do_ioctl = sky2_ioctl,
4388 .ndo_validate_addr = eth_validate_addr,
4389 .ndo_set_mac_address = sky2_set_mac_address,
4390 .ndo_set_multicast_list = sky2_set_multicast,
4391 .ndo_change_mtu = sky2_change_mtu,
4392 .ndo_tx_timeout = sky2_tx_timeout,
4393#ifdef SKY2_VLAN_TAG_USED
4394 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4395#endif
4396 },
4397};
3cf26753 4398
cd28ab6a
SH		 4399/* Initialize network device */
4400static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4401 unsigned port,
be63a21c 4402 int highmem, int wol)
cd28ab6a
SH		 4403{
4404 struct sky2_port *sky2;
4405 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4406
4407 if (!dev) {
898eb71c 4408 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4409 return NULL;
4410 }
4411
cd28ab6a 4412 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4413 dev->irq = hw->pdev->irq;
cd28ab6a 4414 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4415 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4416 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4417
4418 sky2 = netdev_priv(dev);
4419 sky2->netdev = dev;
4420 sky2->hw = hw;
4421 sky2->msg_enable = netif_msg_init(debug, default_msg);
4422
cd28ab6a 4423 /* Auto speed and flow control */
0ea065e5
SH		 4424 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4425 if (hw->chip_id != CHIP_ID_YUKON_XL)
4426 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4427
16ad91e1
SH		 4428 sky2->flow_mode = FC_BOTH;
4429
cd28ab6a
SH		 4430 sky2->duplex = -1;
4431 sky2->speed = -1;
4432 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4433 sky2->wol = wol;
75d070c5 4434
e07b1aa8 4435 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4436
793b883e 4437 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4438 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4439 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4440
4441 hw->dev[port] = dev;
4442
4443 sky2->port = port;
4444
4a50a876 4445 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4446 if (highmem)
4447 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4448
d1f13708 4449#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4450 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4451 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4452 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4453 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4454 }
d1f13708 4455#endif
4456
cd28ab6a 4457 /* read the mac address */
793b883e 4458 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4459 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4460
cd28ab6a
SH		 4461 return dev;
4462}
4463
28bd181a 4464static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4465{
4466 const struct sky2_port *sky2 = netdev_priv(dev);
4467
4468 if (netif_msg_probe(sky2))
e174961c
JB		 4469 printk(KERN_INFO PFX "%s: addr %pM\n",
4470 dev->name, dev->dev_addr);
cd28ab6a
SH		 4471}
4472
fb2690a9 4473/* Handle software interrupt used during MSI test */
7d12e780 4474static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4475{
4476 struct sky2_hw *hw = dev_id;
4477 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4478
4479 if (status == 0)
4480 return IRQ_NONE;
4481
4482 if (status & Y2_IS_IRQ_SW) {
ea76e635 4483 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4484 wake_up(&hw->msi_wait);
4485 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4486 }
4487 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4488
4489 return IRQ_HANDLED;
4490}
4491
4492/* Test interrupt path by forcing a a software IRQ */
4493static int __devinit sky2_test_msi(struct sky2_hw *hw)
4494{
4495 struct pci_dev *pdev = hw->pdev;
4496 int err;
4497
bb507fe1 4498 init_waitqueue_head (&hw->msi_wait);
4499
fb2690a9
SH		 4500 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4501
b0a20ded 4502 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4503 if (err) {
b02a9258 4504 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4505 return err;
4506 }
4507
fb2690a9 4508 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4509 sky2_read8(hw, B0_CTST);
fb2690a9 4510
ea76e635 4511 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4512
ea76e635 4513 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4514 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4515 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4516 "switching to INTx mode.\n");
fb2690a9
SH		 4517
4518 err = -EOPNOTSUPP;
4519 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4520 }
4521
4522 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4523 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4524
4525 free_irq(pdev->irq, hw);
4526
4527 return err;
4528}
4529
c7127a34
SH		 4530/* This driver supports yukon2 chipset only */
4531static const char *sky2_name(u8 chipid, char *buf, int sz)
4532{
4533 const char *name[] = {
4534 "XL", /* 0xb3 */
4535 "EC Ultra", /* 0xb4 */
4536 "Extreme", /* 0xb5 */
4537 "EC", /* 0xb6 */
4538 "FE", /* 0xb7 */
4539 "FE+", /* 0xb8 */
4540 "Supreme", /* 0xb9 */
0ce8b98d 4541 "UL 2", /* 0xba */
0f5aac70
SH		 4542 "Unknown", /* 0xbb */
4543 "Optima", /* 0xbc */
c7127a34
SH		 4544 };
4545
dae3a511 4546 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4547 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4548 else
4549 snprintf(buf, sz, "(chip %#x)", chipid);
4550 return buf;
4551}
4552
cd28ab6a
SH		 4553static int __devinit sky2_probe(struct pci_dev *pdev,
4554 const struct pci_device_id *ent)
4555{
7f60c64b 4556 struct net_device *dev;
cd28ab6a 4557 struct sky2_hw *hw;
be63a21c 4558 int err, using_dac = 0, wol_default;
3834507d 4559 u32 reg;
c7127a34 4560 char buf1[16];
cd28ab6a 4561
793b883e
SH		 4562 err = pci_enable_device(pdev);
4563 if (err) {
b02a9258 4564 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4565 goto err_out;
4566 }
4567
6cc90a5a
SH		 4568 /* Get configuration information
4569 * Note: only regular PCI config access once to test for HW issues
4570 * other PCI access through shared memory for speed and to
4571 * avoid MMCONFIG problems.
4572 */
4573 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4574 if (err) {
4575 dev_err(&pdev->dev, "PCI read config failed\n");
4576 goto err_out;
4577 }
4578
4579 if (~reg == 0) {
4580 dev_err(&pdev->dev, "PCI configuration read error\n");
4581 goto err_out;
4582 }
4583
793b883e
SH		 4584 err = pci_request_regions(pdev, DRV_NAME);
4585 if (err) {
b02a9258 4586 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4587 goto err_out_disable;
cd28ab6a
SH		 4588 }
4589
4590 pci_set_master(pdev);
4591
d1f3d4dd 4592 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4593 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4594 using_dac = 1;
6a35528a 4595 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4596 if (err < 0) {
b02a9258
SH		 4597 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4598 "for consistent allocations\n");
d1f3d4dd
SH		 4599 goto err_out_free_regions;
4600 }
d1f3d4dd 4601 } else {
284901a9 4602 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4603 if (err) {
b02a9258 4604 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4605 goto err_out_free_regions;
4606 }
4607 }
d1f3d4dd 4608
3834507d
SH		 4609
4610#ifdef __BIG_ENDIAN
4611 /* The sk98lin vendor driver uses hardware byte swapping but
4612 * this driver uses software swapping.
4613 */
4614 reg &= ~PCI_REV_DESC;
4615 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4616 if (err) {
4617 dev_err(&pdev->dev, "PCI write config failed\n");
4618 goto err_out_free_regions;
4619 }
4620#endif
4621
9d731d77 4622 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4623
cd28ab6a 4624 err = -ENOMEM;
66466797
SH		 4625
4626 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4627 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4628 if (!hw) {
b02a9258 4629 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4630 goto err_out_free_regions;
4631 }
4632
cd28ab6a 4633 hw->pdev = pdev;
66466797 4634 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4635
4636 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4637 if (!hw->regs) {
b02a9258 4638 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4639 goto err_out_free_hw;
4640 }
4641
08c06d8a 4642 /* ring for status responses */
167f53d0 4643 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4644 if (!hw->st_le)
4645 goto err_out_iounmap;
4646
e3173832 4647 err = sky2_init(hw);
cd28ab6a 4648 if (err)
793b883e 4649 goto err_out_iounmap;
cd28ab6a 4650
c844d483
SH		 4651 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4652 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4653
e3173832
SH		 4654 sky2_reset(hw);
4655
be63a21c 4656 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4657 if (!dev) {
4658 err = -ENOMEM;
cd28ab6a 4659 goto err_out_free_pci;
7f60c64b 4660 }
cd28ab6a 4661
9fa1b1f3
SH		 4662 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4663 err = sky2_test_msi(hw);
4664 if (err == -EOPNOTSUPP)
4665 pci_disable_msi(pdev);
4666 else if (err)
4667 goto err_out_free_netdev;
4668 }
4669
793b883e
SH		 4670 err = register_netdev(dev);
4671 if (err) {
b02a9258 4672 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4673 goto err_out_free_netdev;
4674 }
4675
33cb7d33
BP		 4676 netif_carrier_off(dev);
4677
6de16237
SH		 4678 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4679
ea76e635
SH		 4680 err = request_irq(pdev->irq, sky2_intr,
4681 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4682 hw->irq_name, hw);
9fa1b1f3 4683 if (err) {
b02a9258 4684 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4685 goto err_out_unregister;
4686 }
4687 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4688 napi_enable(&hw->napi);
9fa1b1f3 4689
cd28ab6a
SH		 4690 sky2_show_addr(dev);
4691
7f60c64b 4692 if (hw->ports > 1) {
4693 struct net_device *dev1;
4694
ca519274 4695 err = -ENOMEM;
be63a21c 4696 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4697 if (dev1 && (err = register_netdev(dev1)) == 0)
4698 sky2_show_addr(dev1);
4699 else {
b02a9258
SH		 4700 dev_warn(&pdev->dev,
4701 "register of second port failed (%d)\n", err);
cd28ab6a 4702 hw->dev[1] = NULL;
ca519274
SH		 4703 hw->ports = 1;
4704 if (dev1)
4705 free_netdev(dev1);
4706 }
cd28ab6a
SH		 4707 }
4708
32c2c300 4709 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4710 INIT_WORK(&hw->restart_work, sky2_restart);
4711
793b883e 4712 pci_set_drvdata(pdev, hw);
1ae861e6 4713 pdev->d3_delay = 150;
793b883e 4714
cd28ab6a
SH		 4715 return 0;
4716
793b883e 4717err_out_unregister:
ea76e635 4718 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4719 pci_disable_msi(pdev);
793b883e 4720 unregister_netdev(dev);
cd28ab6a
SH		 4721err_out_free_netdev:
4722 free_netdev(dev);
cd28ab6a 4723err_out_free_pci:
793b883e 4724 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4725 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4726err_out_iounmap:
4727 iounmap(hw->regs);
4728err_out_free_hw:
4729 kfree(hw);
4730err_out_free_regions:
4731 pci_release_regions(pdev);
44a1d2e5 4732err_out_disable:
cd28ab6a 4733 pci_disable_device(pdev);
cd28ab6a 4734err_out:
549a68c3 4735 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4736 return err;
4737}
4738
4739static void __devexit sky2_remove(struct pci_dev *pdev)
4740{
793b883e 4741 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4742 int i;
cd28ab6a 4743
793b883e 4744 if (!hw)
cd28ab6a
SH		 4745 return;
4746
32c2c300 4747 del_timer_sync(&hw->watchdog_timer);
6de16237 4748 cancel_work_sync(&hw->restart_work);
d27ed387 4749
b877fe28 4750 for (i = hw->ports-1; i >= 0; --i)
6de16237 4751 unregister_netdev(hw->dev[i]);
81906791 4752
d27ed387 4753 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4754
ae306cca
SH		 4755 sky2_power_aux(hw);
4756
793b883e 4757 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4758 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4759
4760 free_irq(pdev->irq, hw);
ea76e635 4761 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4762 pci_disable_msi(pdev);
793b883e 4763 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4764 pci_release_regions(pdev);
4765 pci_disable_device(pdev);
793b883e 4766
b877fe28 4767 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4768 free_netdev(hw->dev[i]);
4769
cd28ab6a
SH		 4770 iounmap(hw->regs);
4771 kfree(hw);
5afa0a9c 4772
cd28ab6a
SH		 4773 pci_set_drvdata(pdev, NULL);
4774}
4775
cd28ab6a
SH		 4776static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4777{
793b883e 4778 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4779 int i, wol = 0;
cd28ab6a 4780
549a68c3
SH		 4781 if (!hw)
4782 return 0;
4783
063a0b38
SH		 4784 del_timer_sync(&hw->watchdog_timer);
4785 cancel_work_sync(&hw->restart_work);
4786
19720737 4787 rtnl_lock();
f05267e7 4788 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4789 struct net_device *dev = hw->dev[i];
e3173832 4790 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4791
af18d8b8 4792 sky2_detach(dev);
e3173832
SH		 4793
4794 if (sky2->wol)
4795 sky2_wol_init(sky2);
4796
4797 wol |= sky2->wol;
cd28ab6a
SH		 4798 }
4799
5f8ae5c5 4800 device_set_wakeup_enable(&pdev->dev, wol != 0);
4801
8ab8fca2 4802 sky2_write32(hw, B0_IMSK, 0);
6de16237 4803 napi_disable(&hw->napi);
ae306cca 4804 sky2_power_aux(hw);
19720737 4805 rtnl_unlock();
e3173832 4806
d374c1c1 4807 pci_save_state(pdev);
e3173832 4808 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4809 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4810
2ccc99b7 4811 return 0;
cd28ab6a
SH		 4812}
4813
5f8ae5c5 4814#ifdef CONFIG_PM
cd28ab6a
SH		 4815static int sky2_resume(struct pci_dev *pdev)
4816{
793b883e 4817 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4818 int i, err;
cd28ab6a 4819
549a68c3
SH		 4820 if (!hw)
4821 return 0;
4822
f71eb1a2
SH		 4823 err = pci_set_power_state(pdev, PCI_D0);
4824 if (err)
4825 goto out;
ae306cca
SH		 4826
4827 err = pci_restore_state(pdev);
4828 if (err)
4829 goto out;
4830
cd28ab6a 4831 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4832
4833 /* Re-enable all clocks */
a0db28b8 4834 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4835 if (err) {
4836 dev_err(&pdev->dev, "PCI write config failed\n");
4837 goto out;
4838 }
1ad5b4a5 4839
e3173832 4840 sky2_reset(hw);
8ab8fca2 4841 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4842 napi_enable(&hw->napi);
8ab8fca2 4843
af18d8b8 4844 rtnl_lock();
f05267e7 4845 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4846 err = sky2_reattach(hw->dev[i]);
4847 if (err)
4848 goto out;
cd28ab6a 4849 }
af18d8b8 4850 rtnl_unlock();
eb35cf60 4851
ae306cca 4852 return 0;
08c06d8a 4853out:
af18d8b8
SH		 4854 rtnl_unlock();
4855
b02a9258 4856 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4857 pci_disable_device(pdev);
08c06d8a 4858 return err;
cd28ab6a
SH		 4859}
4860#endif
4861
e3173832
SH		 4862static void sky2_shutdown(struct pci_dev *pdev)
4863{
5f8ae5c5 4864 sky2_suspend(pdev, PMSG_SUSPEND);
e3173832
SH		 4865}
4866
cd28ab6a 4867static struct pci_driver sky2_driver = {
793b883e
SH		 4868 .name = DRV_NAME,
4869 .id_table = sky2_id_table,
4870 .probe = sky2_probe,
4871 .remove = __devexit_p(sky2_remove),
cd28ab6a 4872#ifdef CONFIG_PM
793b883e
SH		 4873 .suspend = sky2_suspend,
4874 .resume = sky2_resume,
cd28ab6a 4875#endif
e3173832 4876 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4877};
4878
4879static int __init sky2_init_module(void)
4880{
c844d483
SH		 4881 pr_info(PFX "driver version " DRV_VERSION "\n");
4882
3cf26753 4883 sky2_debug_init();
50241c4c 4884 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4885}
4886
4887static void __exit sky2_cleanup_module(void)
4888{
4889 pci_unregister_driver(&sky2_driver);
3cf26753 4890 sky2_debug_cleanup();
cd28ab6a
SH		 4891}
4892
4893module_init(sky2_init_module);
4894module_exit(sky2_cleanup_module);
4895
4896MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4897MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4898MODULE_LICENSE("GPL");
5f4f9dc1 4899MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)