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[PATCH] sky2: don't inline so much
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
cd28ab6a
SH		 27 * TOTEST
28 * - speed setting
724bca3c 29 * - suspend/resume
cd28ab6a
SH		 30 */
31
32#include <linux/config.h>
793b883e 33#include <linux/crc32.h>
cd28ab6a
SH		 34#include <linux/kernel.h>
35#include <linux/version.h>
36#include <linux/module.h>
37#include <linux/netdevice.h>
d0bbccfa 38#include <linux/dma-mapping.h>
cd28ab6a
SH		 39#include <linux/etherdevice.h>
40#include <linux/ethtool.h>
41#include <linux/pci.h>
42#include <linux/ip.h>
43#include <linux/tcp.h>
44#include <linux/in.h>
45#include <linux/delay.h>
91c86df5 46#include <linux/workqueue.h>
d1f13708 47#include <linux/if_vlan.h>
d70cd51a 48#include <linux/prefetch.h>
ef743d33 49#include <linux/mii.h>
cd28ab6a
SH		 50
51#include <asm/irq.h>
52
d1f13708 53#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
54#define SKY2_VLAN_TAG_USED 1
55#endif
56
cd28ab6a
SH		 57#include "sky2.h"
58
59#define DRV_NAME "sky2"
e0c94455 60#define DRV_VERSION "0.12"
cd28ab6a
SH		 61#define PFX DRV_NAME " "
62
63/*
64 * The Yukon II chipset takes 64 bit command blocks (called list elements)
65 * that are organized into three (receive, transmit, status) different rings
66 * similar to Tigon3. A transmit can require several elements;
67 * a receive requires one (or two if using 64 bit dma).
68 */
69
cd28ab6a 70#define is_ec_a1(hw) \
21437643 71 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
72 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
cd28ab6a 73
13210ce5 74#define RX_LE_SIZE 512
cd28ab6a 75#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 76#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 77#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 78#define RX_SKB_ALIGN 8
793b883e
SH		 79
80#define TX_RING_SIZE 512
81#define TX_DEF_PENDING (TX_RING_SIZE - 1)
82#define TX_MIN_PENDING 64
83#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
cd28ab6a 84
793b883e 85#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 86#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
87#define ETH_JUMBO_MTU 9000
88#define TX_WATCHDOG (5 * HZ)
89#define NAPI_WEIGHT 64
90#define PHY_RETRIES 1000
91
92static const u32 default_msg =
793b883e
SH		 93 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
94 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 95 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 96
793b883e 97static int debug = -1; /* defaults above */
cd28ab6a
SH		 98module_param(debug, int, 0);
99MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
100
bdb5c58e
SH		 101static int copybreak __read_mostly = 256;
102module_param(copybreak, int, 0);
103MODULE_PARM_DESC(copybreak, "Receive copy threshold");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 125 { 0 }
126};
793b883e 127
cd28ab6a
SH		 128MODULE_DEVICE_TABLE(pci, sky2_id_table);
129
130/* Avoid conditionals by using array */
131static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
132static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
133
92f965e8
SH		 134/* This driver supports yukon2 chipset only */
135static const char *yukon2_name[] = {
136 "XL", /* 0xb3 */
137 "EC Ultra", /* 0xb4 */
138 "UNKNOWN", /* 0xb5 */
139 "EC", /* 0xb6 */
140 "FE", /* 0xb7 */
793b883e
SH		 141};
142
793b883e 143/* Access to external PHY */
ef743d33 144static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 145{
146 int i;
147
148 gma_write16(hw, port, GM_SMI_DATA, val);
149 gma_write16(hw, port, GM_SMI_CTRL,
150 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
151
152 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 153 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 154 return 0;
793b883e 155 udelay(1);
cd28ab6a 156 }
ef743d33 157
793b883e 158 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 159 return -ETIMEDOUT;
cd28ab6a
SH		 160}
161
ef743d33 162static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 163{
164 int i;
165
793b883e 166 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 167 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
168
169 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 170 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
171 *val = gma_read16(hw, port, GM_SMI_DATA);
172 return 0;
173 }
174
793b883e 175 udelay(1);
cd28ab6a
SH		 176 }
177
ef743d33 178 return -ETIMEDOUT;
179}
180
181static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
182{
183 u16 v;
184
185 if (__gm_phy_read(hw, port, reg, &v) != 0)
186 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
187 return v;
cd28ab6a
SH		 188}
189
5afa0a9c 190static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
191{
192 u16 power_control;
193 u32 reg1;
194 int vaux;
195 int ret = 0;
196
197 pr_debug("sky2_set_power_state %d\n", state);
198 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
199
200 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
201 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
202 (power_control & PCI_PM_CAP_PME_D3cold);
203
204 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
205
206 power_control |= PCI_PM_CTRL_PME_STATUS;
207 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
208
209 switch (state) {
210 case PCI_D0:
211 /* switch power to VCC (WA for VAUX problem) */
212 sky2_write8(hw, B0_POWER_CTRL,
213 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
214
215 /* disable Core Clock Division, */
216 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
217
218 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
219 /* enable bits are inverted */
220 sky2_write8(hw, B2_Y2_CLK_GATE,
221 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
222 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
223 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
224 else
225 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
226
227 /* Turn off phy power saving */
228 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
229 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
230
d571b694 231 /* looks like this XL is back asswards .. */
5afa0a9c 232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
233 reg1 |= PCI_Y2_PHY1_COMA;
234 if (hw->ports > 1)
235 reg1 |= PCI_Y2_PHY2_COMA;
236 }
237 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
238 break;
239
240 case PCI_D3hot:
241 case PCI_D3cold:
242 /* Turn on phy power saving */
243 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 else
247 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
248 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
249
250 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
251 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
252 else
253 /* enable bits are inverted */
254 sky2_write8(hw, B2_Y2_CLK_GATE,
255 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
256 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
257 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
258
259 /* switch power to VAUX */
260 if (vaux && state != PCI_D3cold)
261 sky2_write8(hw, B0_POWER_CTRL,
262 (PC_VAUX_ENA | PC_VCC_ENA |
263 PC_VAUX_ON | PC_VCC_OFF));
264 break;
265 default:
266 printk(KERN_ERR PFX "Unknown power state %d\n", state);
267 ret = -1;
268 }
269
270 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
271 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
272 return ret;
273}
274
cd28ab6a
SH		 275static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
276{
277 u16 reg;
278
279 /* disable all GMAC IRQ's */
280 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
281 /* disable PHY IRQs */
282 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
294static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
295{
296 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 297 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 298
793b883e 299 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 300 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
301
302 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 303 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 304 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
305
306 if (hw->chip_id == CHIP_ID_YUKON_EC)
307 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
308 else
309 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
310
311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
312 }
313
314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
315 if (hw->copper) {
316 if (hw->chip_id == CHIP_ID_YUKON_FE) {
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
319 } else {
320 /* disable energy detect */
321 ctrl &= ~PHY_M_PC_EN_DET_MSK;
322
323 /* enable automatic crossover */
324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
325
326 if (sky2->autoneg == AUTONEG_ENABLE &&
327 hw->chip_id == CHIP_ID_YUKON_XL) {
328 ctrl &= ~PHY_M_PC_DSC_MSK;
329 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
330 }
331 }
332 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
333 } else {
334 /* workaround for deviation #4.88 (CRC errors) */
335 /* disable Automatic Crossover */
336
337 ctrl &= ~PHY_M_PC_MDIX_MSK;
338 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
339
340 if (hw->chip_id == CHIP_ID_YUKON_XL) {
341 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 ctrl &= ~PHY_M_MAC_MD_MSK;
345 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347
348 /* select page 1 to access Fiber registers */
349 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
350 }
cd28ab6a
SH		 351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
354 if (sky2->autoneg == AUTONEG_DISABLE)
355 ctrl &= ~PHY_CT_ANE;
356 else
357 ctrl |= PHY_CT_ANE;
358
359 ctrl |= PHY_CT_RESET;
360 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
361
362 ctrl = 0;
363 ct1000 = 0;
364 adv = PHY_AN_CSMA;
365
366 if (sky2->autoneg == AUTONEG_ENABLE) {
367 if (hw->copper) {
368 if (sky2->advertising & ADVERTISED_1000baseT_Full)
369 ct1000 |= PHY_M_1000C_AFD;
370 if (sky2->advertising & ADVERTISED_1000baseT_Half)
371 ct1000 |= PHY_M_1000C_AHD;
372 if (sky2->advertising & ADVERTISED_100baseT_Full)
373 adv |= PHY_M_AN_100_FD;
374 if (sky2->advertising & ADVERTISED_100baseT_Half)
375 adv |= PHY_M_AN_100_HD;
376 if (sky2->advertising & ADVERTISED_10baseT_Full)
377 adv |= PHY_M_AN_10_FD;
378 if (sky2->advertising & ADVERTISED_10baseT_Half)
379 adv |= PHY_M_AN_10_HD;
793b883e 380 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 381 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
382
383 /* Set Flow-control capabilities */
384 if (sky2->tx_pause && sky2->rx_pause)
793b883e 385 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 386 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 387 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 388 else if (!sky2->rx_pause && sky2->tx_pause)
389 adv |= PHY_AN_PAUSE_ASYM; /* local */
390
391 /* Restart Auto-negotiation */
392 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
393 } else {
394 /* forced speed/duplex settings */
395 ct1000 = PHY_M_1000C_MSE;
396
397 if (sky2->duplex == DUPLEX_FULL)
398 ctrl |= PHY_CT_DUP_MD;
399
400 switch (sky2->speed) {
401 case SPEED_1000:
402 ctrl |= PHY_CT_SP1000;
403 break;
404 case SPEED_100:
405 ctrl |= PHY_CT_SP100;
406 break;
407 }
408
409 ctrl |= PHY_CT_RESET;
410 }
411
412 if (hw->chip_id != CHIP_ID_YUKON_FE)
413 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
414
415 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
416 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
417
418 /* Setup Phy LED's */
419 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
420 ledover = 0;
421
422 switch (hw->chip_id) {
423 case CHIP_ID_YUKON_FE:
424 /* on 88E3082 these bits are at 11..9 (shifted left) */
425 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
426
427 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
428
429 /* delete ACT LED control bits */
430 ctrl &= ~PHY_M_FELP_LED1_MSK;
431 /* change ACT LED control to blink mode */
432 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
433 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
434 break;
435
436 case CHIP_ID_YUKON_XL:
793b883e 437 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 438
439 /* select page 3 to access LED control register */
440 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
441
442 /* set LED Function Control register */
793b883e
SH		 443 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
444 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
445 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
446 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 447
448 /* set Polarity Control register */
449 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 450 (PHY_M_POLC_LS1_P_MIX(4) |
451 PHY_M_POLC_IS0_P_MIX(4) |
452 PHY_M_POLC_LOS_CTRL(2) |
453 PHY_M_POLC_INIT_CTRL(2) |
454 PHY_M_POLC_STA1_CTRL(2) |
455 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 456
457 /* restore page register */
793b883e 458 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 459 break;
460
461 default:
462 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
463 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
464 /* turn off the Rx LED (LED_RX) */
465 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
466 }
467
468 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
469
470 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
471 /* turn on 100 Mbps LED (LED_LINK100) */
472 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
473 }
474
475 if (ledover)
476 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
477
d571b694 478 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 479 if (sky2->autoneg == AUTONEG_ENABLE)
480 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
481 else
482 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
483}
484
1b537565
SH		 485/* Force a renegotiation */
486static void sky2_phy_reinit(struct sky2_port *sky2)
487{
488 down(&sky2->phy_sema);
489 sky2_phy_init(sky2->hw, sky2->port);
490 up(&sky2->phy_sema);
491}
492
cd28ab6a
SH		 493static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
494{
495 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
496 u16 reg;
497 int i;
498 const u8 *addr = hw->dev[port]->dev_addr;
499
42eeea01 500 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
501 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 502
503 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
504
793b883e 505 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 506 /* WA DEV_472 -- looks like crossed wires on port 2 */
507 /* clear GMAC 1 Control reset */
508 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
509 do {
510 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
511 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
512 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
513 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
514 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
515 }
516
cd28ab6a
SH		 517 if (sky2->autoneg == AUTONEG_DISABLE) {
518 reg = gma_read16(hw, port, GM_GP_CTRL);
519 reg |= GM_GPCR_AU_ALL_DIS;
520 gma_write16(hw, port, GM_GP_CTRL, reg);
521 gma_read16(hw, port, GM_GP_CTRL);
522
cd28ab6a
SH		 523 switch (sky2->speed) {
524 case SPEED_1000:
525 reg |= GM_GPCR_SPEED_1000;
526 /* fallthru */
527 case SPEED_100:
528 reg |= GM_GPCR_SPEED_100;
529 }
530
531 if (sky2->duplex == DUPLEX_FULL)
532 reg |= GM_GPCR_DUP_FULL;
533 } else
534 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
535
536 if (!sky2->tx_pause && !sky2->rx_pause) {
537 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 538 reg |=
539 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
540 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 541 /* disable Rx flow-control */
542 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
543 }
544
545 gma_write16(hw, port, GM_GP_CTRL, reg);
546
793b883e 547 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 548
91c86df5 549 down(&sky2->phy_sema);
cd28ab6a 550 sky2_phy_init(hw, port);
91c86df5 551 up(&sky2->phy_sema);
cd28ab6a
SH		 552
553 /* MIB clear */
554 reg = gma_read16(hw, port, GM_PHY_ADDR);
555 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
556
557 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 558 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 559 gma_write16(hw, port, GM_PHY_ADDR, reg);
560
561 /* transmit control */
562 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
563
564 /* receive control reg: unicast + multicast + no FCS */
565 gma_write16(hw, port, GM_RX_CTRL,
793b883e 566 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 567
568 /* transmit flow control */
569 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
570
571 /* transmit parameter */
572 gma_write16(hw, port, GM_TX_PARAM,
573 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
574 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
575 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
576 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
577
578 /* serial mode register */
579 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 580 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 581
6b1a3aef 582 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 583 reg |= GM_SMOD_JUMBO_ENA;
584
585 gma_write16(hw, port, GM_SERIAL_MODE, reg);
586
cd28ab6a
SH		 587 /* virtual address for data */
588 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
589
793b883e
SH		 590 /* physical address: used for pause frames */
591 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
592
593 /* ignore counter overflows */
cd28ab6a
SH		 594 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
595 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
596 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
597
598 /* Configure Rx MAC FIFO */
599 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
793b883e 600 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
d1f13708 601 GMF_RX_CTRL_DEF);
cd28ab6a 602
d571b694 603 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 604 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 605
793b883e
SH		 606 /* Set threshold to 0xa (64 bytes)
607 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 608 */
609 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
610
611 /* Configure Tx MAC FIFO */
612 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
613 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 614
615 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
616 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
617 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
618 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
619 /* set Tx GMAC FIFO Almost Empty Threshold */
620 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
621 /* Disable Store & Forward mode for TX */
622 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
623 }
624 }
625
cd28ab6a
SH		 626}
627
1c28f6ba
SH		 628/* Assign Ram Buffer allocation.
629 * start and end are in units of 4k bytes
630 * ram registers are in units of 64bit words
631 */
632static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 633{
1c28f6ba 634 u32 start, end;
cd28ab6a 635
1c28f6ba
SH		 636 start = startk * 4096/8;
637 end = (endk * 4096/8) - 1;
793b883e 638
cd28ab6a
SH		 639 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
640 sky2_write32(hw, RB_ADDR(q, RB_START), start);
641 sky2_write32(hw, RB_ADDR(q, RB_END), end);
642 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
643 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
644
645 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 646 u32 space = (endk - startk) * 4096/8;
647 u32 tp = space - space/4;
793b883e 648
1c28f6ba
SH		 649 /* On receive queue's set the thresholds
650 * give receiver priority when > 3/4 full
651 * send pause when down to 2K
652 */
653 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
654 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 655
1c28f6ba
SH		 656 tp = space - 2048/8;
657 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
658 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 659 } else {
660 /* Enable store & forward on Tx queue's because
661 * Tx FIFO is only 1K on Yukon
662 */
663 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
664 }
665
666 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 667 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 668}
669
cd28ab6a 670/* Setup Bus Memory Interface */
af4ed7e6 671static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 672{
673 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
674 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
675 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 676 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 677}
678
cd28ab6a
SH		 679/* Setup prefetch unit registers. This is the interface between
680 * hardware and driver list elements
681 */
8cc048e3 682static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 683 u64 addr, u32 last)
684{
cd28ab6a
SH		 685 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
686 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
687 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
688 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
689 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
690 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 691
692 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 693}
694
793b883e
SH		 695static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
696{
697 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
698
699 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
700 return le;
701}
cd28ab6a
SH		 702
703/*
d571b694 704 * This is a workaround code taken from SysKonnect sk98lin driver
793b883e 705 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
cd28ab6a 706 */
28bd181a 707static void sky2_put_idx(struct sky2_hw *hw, unsigned q,
cd28ab6a 708 u16 idx, u16 *last, u16 size)
cd28ab6a 709{
762c2de2 710 wmb();
cd28ab6a
SH		 711 if (is_ec_a1(hw) && idx < *last) {
712 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
713
714 if (hwget == 0) {
715 /* Start prefetching again */
793b883e 716 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
cd28ab6a
SH		 717 goto setnew;
718 }
719
793b883e 720 if (hwget == size - 1) {
cd28ab6a
SH		 721 /* set watermark to one list element */
722 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
723
724 /* set put index to first list element */
725 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
793b883e
SH		 726 } else /* have hardware go to end of list */
727 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
728 size - 1);
cd28ab6a 729 } else {
793b883e 730setnew:
cd28ab6a 731 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
cd28ab6a 732 }
bea86103 733 *last = idx;
762c2de2 734 mmiowb();
cd28ab6a
SH		 735}
736
793b883e 737
cd28ab6a
SH		 738static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
739{
740 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
741 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
742 return le;
743}
744
a018e330 745/* Return high part of DMA address (could be 32 or 64 bit) */
746static inline u32 high32(dma_addr_t a)
747{
a036119f 748 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 749}
750
793b883e 751/* Build description to hardware about buffer */
28bd181a 752static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 753{
754 struct sky2_rx_le *le;
734d1868
SH		 755 u32 hi = high32(map);
756 u16 len = sky2->rx_bufsize;
cd28ab6a 757
793b883e 758 if (sky2->rx_addr64 != hi) {
cd28ab6a 759 le = sky2_next_rx(sky2);
793b883e 760 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 761 le->ctrl = 0;
762 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 763 sky2->rx_addr64 = high32(map + len);
cd28ab6a 764 }
793b883e 765
cd28ab6a 766 le = sky2_next_rx(sky2);
734d1868
SH		 767 le->addr = cpu_to_le32((u32) map);
768 le->length = cpu_to_le16(len);
cd28ab6a
SH		 769 le->ctrl = 0;
770 le->opcode = OP_PACKET | HW_OWNER;
771}
772
793b883e 773
cd28ab6a
SH		 774/* Tell chip where to start receive checksum.
775 * Actually has two checksums, but set both same to avoid possible byte
776 * order problems.
777 */
793b883e 778static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 779{
780 struct sky2_rx_le *le;
781
cd28ab6a 782 le = sky2_next_rx(sky2);
793b883e 783 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 784 le->ctrl = 0;
785 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 786
793b883e
SH		 787 sky2_write32(sky2->hw,
788 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
789 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 790
791}
792
6b1a3aef 793/*
794 * The RX Stop command will not work for Yukon-2 if the BMU does not
795 * reach the end of packet and since we can't make sure that we have
796 * incoming data, we must reset the BMU while it is not doing a DMA
797 * transfer. Since it is possible that the RX path is still active,
798 * the RX RAM buffer will be stopped first, so any possible incoming
799 * data will not trigger a DMA. After the RAM buffer is stopped, the
800 * BMU is polled until any DMA in progress is ended and only then it
801 * will be reset.
802 */
803static void sky2_rx_stop(struct sky2_port *sky2)
804{
805 struct sky2_hw *hw = sky2->hw;
806 unsigned rxq = rxqaddr[sky2->port];
807 int i;
808
809 /* disable the RAM Buffer receive queue */
810 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
811
812 for (i = 0; i < 0xffff; i++)
813 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
814 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
815 goto stopped;
816
817 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
818 sky2->netdev->name);
819stopped:
820 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
821
822 /* reset the Rx prefetch unit */
823 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
824}
793b883e 825
d571b694 826/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 827static void sky2_rx_clean(struct sky2_port *sky2)
828{
829 unsigned i;
830
831 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 832 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 833 struct ring_info *re = sky2->rx_ring + i;
834
835 if (re->skb) {
793b883e 836 pci_unmap_single(sky2->hw->pdev,
734d1868 837 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 838 PCI_DMA_FROMDEVICE);
839 kfree_skb(re->skb);
840 re->skb = NULL;
841 }
842 }
843}
844
ef743d33 845/* Basic MII support */
846static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
847{
848 struct mii_ioctl_data *data = if_mii(ifr);
849 struct sky2_port *sky2 = netdev_priv(dev);
850 struct sky2_hw *hw = sky2->hw;
851 int err = -EOPNOTSUPP;
852
853 if (!netif_running(dev))
854 return -ENODEV; /* Phy still in reset */
855
856 switch(cmd) {
857 case SIOCGMIIPHY:
858 data->phy_id = PHY_ADDR_MARV;
859
860 /* fallthru */
861 case SIOCGMIIREG: {
862 u16 val = 0;
91c86df5
SH		 863
864 down(&sky2->phy_sema);
ef743d33 865 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
91c86df5
SH		 866 up(&sky2->phy_sema);
867
ef743d33 868 data->val_out = val;
869 break;
870 }
871
872 case SIOCSMIIREG:
873 if (!capable(CAP_NET_ADMIN))
874 return -EPERM;
875
91c86df5 876 down(&sky2->phy_sema);
ef743d33 877 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
878 data->val_in);
91c86df5 879 up(&sky2->phy_sema);
ef743d33 880 break;
881 }
882 return err;
883}
884
d1f13708 885#ifdef SKY2_VLAN_TAG_USED
886static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
887{
888 struct sky2_port *sky2 = netdev_priv(dev);
889 struct sky2_hw *hw = sky2->hw;
890 u16 port = sky2->port;
d1f13708 891
f2e46561 892 spin_lock(&sky2->tx_lock);
d1f13708 893
894 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
895 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
896 sky2->vlgrp = grp;
897
f2e46561 898 spin_unlock(&sky2->tx_lock);
d1f13708 899}
900
901static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
902{
903 struct sky2_port *sky2 = netdev_priv(dev);
904 struct sky2_hw *hw = sky2->hw;
905 u16 port = sky2->port;
d1f13708 906
f2e46561 907 spin_lock(&sky2->tx_lock);
d1f13708 908
909 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
910 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
911 if (sky2->vlgrp)
912 sky2->vlgrp->vlan_devices[vid] = NULL;
913
f2e46561 914 spin_unlock(&sky2->tx_lock);
d1f13708 915}
916#endif
917
82788c7a
SH		 918/*
919 * It appears the hardware has a bug in the FIFO logic that
920 * cause it to hang if the FIFO gets overrun and the receive buffer
921 * is not aligned. ALso alloc_skb() won't align properly if slab
922 * debugging is enabled.
923 */
924static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
925{
926 struct sk_buff *skb;
927
928 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
929 if (likely(skb)) {
930 unsigned long p = (unsigned long) skb->data;
931 skb_reserve(skb,
932 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
933 }
934
935 return skb;
936}
937
cd28ab6a
SH		 938/*
939 * Allocate and setup receiver buffer pool.
940 * In case of 64 bit dma, there are 2X as many list elements
941 * available as ring entries
942 * and need to reserve one list element so we don't wrap around.
943 */
6b1a3aef 944static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 945{
6b1a3aef 946 struct sky2_hw *hw = sky2->hw;
6b1a3aef 947 unsigned rxq = rxqaddr[sky2->port];
948 int i;
cd28ab6a 949
6b1a3aef 950 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 951 sky2_qset(hw, rxq);
6b1a3aef 952 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
953
954 rx_set_checksum(sky2);
793b883e 955 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 956 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 957
82788c7a 958 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 959 if (!re->skb)
960 goto nomem;
961
6b1a3aef 962 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 963 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
964 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 965 }
966
6b1a3aef 967 /* Tell chip about available buffers */
968 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
969 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 970 return 0;
971nomem:
972 sky2_rx_clean(sky2);
973 return -ENOMEM;
974}
975
976/* Bring up network interface. */
977static int sky2_up(struct net_device *dev)
978{
979 struct sky2_port *sky2 = netdev_priv(dev);
980 struct sky2_hw *hw = sky2->hw;
981 unsigned port = sky2->port;
982 u32 ramsize, rxspace;
983 int err = -ENOMEM;
984
985 if (netif_msg_ifup(sky2))
986 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
987
988 /* must be power of 2 */
989 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 990 TX_RING_SIZE *
991 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 992 &sky2->tx_le_map);
993 if (!sky2->tx_le)
994 goto err_out;
995
6cdbbdf3 996 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 997 GFP_KERNEL);
998 if (!sky2->tx_ring)
999 goto err_out;
1000 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1001
1002 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1003 &sky2->rx_le_map);
1004 if (!sky2->rx_le)
1005 goto err_out;
1006 memset(sky2->rx_le, 0, RX_LE_BYTES);
1007
6cdbbdf3 1008 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1009 GFP_KERNEL);
1010 if (!sky2->rx_ring)
1011 goto err_out;
1012
1013 sky2_mac_init(hw, port);
1014
1c28f6ba
SH		 1015 /* Determine available ram buffer space (in 4K blocks).
1016 * Note: not sure about the FE setting below yet
1017 */
1018 if (hw->chip_id == CHIP_ID_YUKON_FE)
1019 ramsize = 4;
1020 else
1021 ramsize = sky2_read8(hw, B2_E_0);
1022
1023 /* Give transmitter one third (rounded up) */
1024 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1025
cd28ab6a 1026 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1027 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1028
793b883e
SH		 1029 /* Make sure SyncQ is disabled */
1030 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1031 RB_RST_SET);
1032
af4ed7e6 1033 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1034 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1035 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1036
1037
6b1a3aef 1038 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1039 TX_RING_SIZE - 1);
cd28ab6a 1040
6b1a3aef 1041 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1042 if (err)
1043 goto err_out;
1044
cd28ab6a
SH		 1045 /* Enable interrupts from phy/mac for port */
1046 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1047 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1048 return 0;
1049
1050err_out:
1b537565 1051 if (sky2->rx_le) {
cd28ab6a
SH		 1052 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1053 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1054 sky2->rx_le = NULL;
1055 }
1056 if (sky2->tx_le) {
cd28ab6a
SH		 1057 pci_free_consistent(hw->pdev,
1058 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1059 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1060 sky2->tx_le = NULL;
1061 }
1062 kfree(sky2->tx_ring);
1063 kfree(sky2->rx_ring);
cd28ab6a 1064
1b537565
SH		 1065 sky2->tx_ring = NULL;
1066 sky2->rx_ring = NULL;
cd28ab6a
SH		 1067 return err;
1068}
1069
793b883e
SH		 1070/* Modular subtraction in ring */
1071static inline int tx_dist(unsigned tail, unsigned head)
1072{
129372d0 1073 return (head - tail) % TX_RING_SIZE;
793b883e 1074}
cd28ab6a 1075
793b883e
SH		 1076/* Number of list elements available for next tx */
1077static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1078{
793b883e 1079 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1080}
1081
793b883e 1082/* Estimate of number of transmit list elements required */
28bd181a 1083static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1084{
793b883e
SH		 1085 unsigned count;
1086
1087 count = sizeof(dma_addr_t) / sizeof(u32);
1088 count += skb_shinfo(skb)->nr_frags * count;
1089
1090 if (skb_shinfo(skb)->tso_size)
1091 ++count;
1092
0e3ff6aa 1093 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1094 ++count;
1095
1096 return count;
cd28ab6a
SH		 1097}
1098
793b883e
SH		 1099/*
1100 * Put one packet in ring for transmit.
1101 * A single packet can generate multiple list elements, and
1102 * the number of ring elements will probably be less than the number
1103 * of list elements used.
f2e46561
SH		 1104 *
1105 * No BH disabling for tx_lock here (like tg3)
793b883e 1106 */
cd28ab6a
SH		 1107static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1108{
1109 struct sky2_port *sky2 = netdev_priv(dev);
1110 struct sky2_hw *hw = sky2->hw;
d1f13708 1111 struct sky2_tx_le *le = NULL;
6cdbbdf3 1112 struct tx_ring_info *re;
cd28ab6a
SH		 1113 unsigned i, len;
1114 dma_addr_t mapping;
1115 u32 addr64;
1116 u16 mss;
1117 u8 ctrl;
1118
f2e46561 1119 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1120 return NETDEV_TX_LOCKED;
1121
793b883e 1122 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1123 /* There is a known but harmless race with lockless tx
1124 * and netif_stop_queue.
1125 */
1126 if (!netif_queue_stopped(dev)) {
1127 netif_stop_queue(dev);
3be92a70
SH		 1128 if (net_ratelimit())
1129 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1130 dev->name);
8c463ef7 1131 }
f2e46561 1132 spin_unlock(&sky2->tx_lock);
cd28ab6a 1133
cd28ab6a
SH		 1134 return NETDEV_TX_BUSY;
1135 }
1136
793b883e 1137 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1138 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1139 dev->name, sky2->tx_prod, skb->len);
1140
cd28ab6a
SH		 1141 len = skb_headlen(skb);
1142 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1143 addr64 = high32(mapping);
793b883e
SH		 1144
1145 re = sky2->tx_ring + sky2->tx_prod;
1146
a018e330 1147 /* Send high bits if changed or crosses boundary */
1148 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1149 le = get_tx_le(sky2);
1150 le->tx.addr = cpu_to_le32(addr64);
1151 le->ctrl = 0;
1152 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1153 sky2->tx_addr64 = high32(mapping + len);
793b883e 1154 }
cd28ab6a
SH		 1155
1156 /* Check for TCP Segmentation Offload */
1157 mss = skb_shinfo(skb)->tso_size;
793b883e 1158 if (mss != 0) {
cd28ab6a
SH		 1159 /* just drop the packet if non-linear expansion fails */
1160 if (skb_header_cloned(skb) &&
1161 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
793b883e
SH		 1162 dev_kfree_skb_any(skb);
1163 goto out_unlock;
cd28ab6a
SH		 1164 }
1165
1166 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1167 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1168 mss += ETH_HLEN;
793b883e 1169 }
cd28ab6a 1170
793b883e 1171 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1172 le = get_tx_le(sky2);
1173 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1174 le->tx.tso.rsvd = 0;
cd28ab6a 1175 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1176 le->ctrl = 0;
793b883e 1177 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1178 }
1179
cd28ab6a 1180 ctrl = 0;
d1f13708 1181#ifdef SKY2_VLAN_TAG_USED
1182 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1183 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1184 if (!le) {
1185 le = get_tx_le(sky2);
1186 le->tx.addr = 0;
1187 le->opcode = OP_VLAN|HW_OWNER;
1188 le->ctrl = 0;
1189 } else
1190 le->opcode |= OP_VLAN;
1191 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1192 ctrl |= INS_VLAN;
1193 }
1194#endif
1195
1196 /* Handle TCP checksum offload */
cd28ab6a 1197 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1198 u16 hdr = skb->h.raw - skb->data;
1199 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1200
1201 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1202 if (skb->nh.iph->protocol == IPPROTO_UDP)
1203 ctrl |= UDPTCP;
1204
1205 le = get_tx_le(sky2);
1206 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1207 le->tx.csum.offset = cpu_to_le16(offset);
1208 le->length = 0; /* initial checksum value */
cd28ab6a 1209 le->ctrl = 1; /* one packet */
793b883e 1210 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1211 }
1212
1213 le = get_tx_le(sky2);
1214 le->tx.addr = cpu_to_le32((u32) mapping);
1215 le->length = cpu_to_le16(len);
1216 le->ctrl = ctrl;
793b883e 1217 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1218
793b883e 1219 /* Record the transmit mapping info */
cd28ab6a 1220 re->skb = skb;
6cdbbdf3 1221 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1222
1223 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1224 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1225 struct tx_ring_info *fre;
cd28ab6a
SH		 1226
1227 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1228 frag->size, PCI_DMA_TODEVICE);
a036119f 1229 addr64 = high32(mapping);
793b883e
SH		 1230 if (addr64 != sky2->tx_addr64) {
1231 le = get_tx_le(sky2);
1232 le->tx.addr = cpu_to_le32(addr64);
1233 le->ctrl = 0;
1234 le->opcode = OP_ADDR64 | HW_OWNER;
1235 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1236 }
1237
1238 le = get_tx_le(sky2);
1239 le->tx.addr = cpu_to_le32((u32) mapping);
1240 le->length = cpu_to_le16(frag->size);
1241 le->ctrl = ctrl;
793b883e 1242 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1243
793b883e
SH		 1244 fre = sky2->tx_ring
1245 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
6cdbbdf3 1246 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1247 }
6cdbbdf3 1248
793b883e 1249 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1250 le->ctrl |= EOP;
1251
724bca3c 1252 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
cd28ab6a
SH		 1253 &sky2->tx_last_put, TX_RING_SIZE);
1254
0e3ff6aa 1255 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
cd28ab6a 1256 netif_stop_queue(dev);
793b883e
SH		 1257
1258out_unlock:
f2e46561 1259 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1260
1261 dev->trans_start = jiffies;
1262 return NETDEV_TX_OK;
1263}
1264
cd28ab6a 1265/*
793b883e
SH		 1266 * Free ring elements from starting at tx_cons until "done"
1267 *
1268 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1269 * buffers; these are deferred until completion.
cd28ab6a 1270 */
d11c13e7 1271static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1272{
d11c13e7 1273 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1274 struct pci_dev *pdev = sky2->hw->pdev;
1275 u16 nxt, put;
793b883e 1276 unsigned i;
cd28ab6a 1277
0e3ff6aa 1278 BUG_ON(done >= TX_RING_SIZE);
2224795d 1279
d11c13e7 1280 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1281 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1282 dev->name, done);
cd28ab6a 1283
af2a58ac
SH		 1284 for (put = sky2->tx_cons; put != done; put = nxt) {
1285 struct tx_ring_info *re = sky2->tx_ring + put;
1286 struct sk_buff *skb = re->skb;
cd28ab6a 1287
af2a58ac
SH		 1288 nxt = re->idx;
1289 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1290 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1291
793b883e 1292 /* Check for partial status */
af2a58ac
SH		 1293 if (tx_dist(put, done) < tx_dist(put, nxt))
1294 break;
793b883e
SH		 1295
1296 skb = re->skb;
af2a58ac 1297 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1298 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1299
1300 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1301 struct tx_ring_info *fre;
af2a58ac
SH		 1302 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1303 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1304 skb_shinfo(skb)->frags[i].size,
734d1868 1305 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1306 }
1307
cd28ab6a 1308 dev_kfree_skb_any(skb);
793b883e 1309 }
793b883e 1310
af2a58ac
SH		 1311 spin_lock(&sky2->tx_lock);
1312 sky2->tx_cons = put;
793b883e 1313 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a
SH		 1314 netif_wake_queue(dev);
1315 spin_unlock(&sky2->tx_lock);
1316}
1317
1318/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1319static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1320{
d11c13e7 1321 sky2_tx_complete(sky2, sky2->tx_prod);
cd28ab6a
SH		 1322}
1323
1324/* Network shutdown */
1325static int sky2_down(struct net_device *dev)
1326{
1327 struct sky2_port *sky2 = netdev_priv(dev);
1328 struct sky2_hw *hw = sky2->hw;
1329 unsigned port = sky2->port;
1330 u16 ctrl;
cd28ab6a 1331
1b537565
SH		 1332 /* Never really got started! */
1333 if (!sky2->tx_le)
1334 return 0;
1335
cd28ab6a
SH		 1336 if (netif_msg_ifdown(sky2))
1337 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1338
018d1c66 1339 /* Stop more packets from being queued */
cd28ab6a
SH		 1340 netif_stop_queue(dev);
1341
018d1c66 1342 /* Disable port IRQ */
1343 local_irq_disable();
1344 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1345 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1346 local_irq_enable();
1347
91c86df5 1348 flush_scheduled_work();
018d1c66 1349
793b883e
SH		 1350 sky2_phy_reset(hw, port);
1351
cd28ab6a
SH		 1352 /* Stop transmitter */
1353 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1354 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1355
1356 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1357 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1358
1359 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1360 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1361 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1362
1363 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1364
1365 /* Workaround shared GMAC reset */
793b883e
SH		 1366 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1367 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1368 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1369
1370 /* Disable Force Sync bit and Enable Alloc bit */
1371 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1372 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1373
1374 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1375 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1376 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1377
1378 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1379 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1380 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1381
1382 /* Reset the Tx prefetch units */
1383 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1384 PREF_UNIT_RST_SET);
1385
1386 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1387
6b1a3aef 1388 sky2_rx_stop(sky2);
cd28ab6a
SH		 1389
1390 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1391 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1392
d571b694 1393 /* turn off LED's */
cd28ab6a
SH		 1394 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1395
018d1c66 1396 synchronize_irq(hw->pdev->irq);
1397
cd28ab6a
SH		 1398 sky2_tx_clean(sky2);
1399 sky2_rx_clean(sky2);
1400
1401 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1402 sky2->rx_le, sky2->rx_le_map);
1403 kfree(sky2->rx_ring);
1404
1405 pci_free_consistent(hw->pdev,
1406 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1407 sky2->tx_le, sky2->tx_le_map);
1408 kfree(sky2->tx_ring);
1409
1b537565
SH		 1410 sky2->tx_le = NULL;
1411 sky2->rx_le = NULL;
1412
1413 sky2->rx_ring = NULL;
1414 sky2->tx_ring = NULL;
1415
cd28ab6a
SH		 1416 return 0;
1417}
1418
1419static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1420{
793b883e
SH		 1421 if (!hw->copper)
1422 return SPEED_1000;
1423
cd28ab6a
SH		 1424 if (hw->chip_id == CHIP_ID_YUKON_FE)
1425 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1426
1427 switch (aux & PHY_M_PS_SPEED_MSK) {
1428 case PHY_M_PS_SPEED_1000:
1429 return SPEED_1000;
1430 case PHY_M_PS_SPEED_100:
1431 return SPEED_100;
1432 default:
1433 return SPEED_10;
1434 }
1435}
1436
1437static void sky2_link_up(struct sky2_port *sky2)
1438{
1439 struct sky2_hw *hw = sky2->hw;
1440 unsigned port = sky2->port;
1441 u16 reg;
1442
1443 /* Enable Transmit FIFO Underrun */
793b883e 1444 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1445
1446 reg = gma_read16(hw, port, GM_GP_CTRL);
1447 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1448 reg |= GM_GPCR_DUP_FULL;
1449
cd28ab6a
SH		 1450 /* enable Rx/Tx */
1451 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1452 gma_write16(hw, port, GM_GP_CTRL, reg);
1453 gma_read16(hw, port, GM_GP_CTRL);
1454
1455 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1456
1457 netif_carrier_on(sky2->netdev);
1458 netif_wake_queue(sky2->netdev);
1459
1460 /* Turn on link LED */
793b883e 1461 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1462 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1463
793b883e
SH		 1464 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1465 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1466
1467 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1468 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1469 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1470 SPEED_10 ? 7 : 0) |
1471 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1472 SPEED_100 ? 7 : 0) |
1473 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1474 SPEED_1000 ? 7 : 0));
1475 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1476 }
1477
cd28ab6a
SH		 1478 if (netif_msg_link(sky2))
1479 printk(KERN_INFO PFX
d571b694 1480 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1481 sky2->netdev->name, sky2->speed,
1482 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1483 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1484 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1485}
1486
1487static void sky2_link_down(struct sky2_port *sky2)
1488{
1489 struct sky2_hw *hw = sky2->hw;
1490 unsigned port = sky2->port;
1491 u16 reg;
1492
1493 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1494
1495 reg = gma_read16(hw, port, GM_GP_CTRL);
1496 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1497 gma_write16(hw, port, GM_GP_CTRL, reg);
1498 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1499
1500 if (sky2->rx_pause && !sky2->tx_pause) {
1501 /* restore Asymmetric Pause bit */
1502 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1503 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1504 | PHY_M_AN_ASP);
cd28ab6a
SH		 1505 }
1506
cd28ab6a
SH		 1507 netif_carrier_off(sky2->netdev);
1508 netif_stop_queue(sky2->netdev);
1509
1510 /* Turn on link LED */
1511 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1512
1513 if (netif_msg_link(sky2))
1514 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1515 sky2_phy_init(hw, port);
1516}
1517
793b883e
SH		 1518static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1519{
1520 struct sky2_hw *hw = sky2->hw;
1521 unsigned port = sky2->port;
1522 u16 lpa;
1523
1524 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1525
1526 if (lpa & PHY_M_AN_RF) {
1527 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1528 return -1;
1529 }
1530
1531 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1532 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1533 printk(KERN_ERR PFX "%s: master/slave fault",
1534 sky2->netdev->name);
1535 return -1;
1536 }
1537
1538 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1539 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1540 sky2->netdev->name);
1541 return -1;
1542 }
1543
1544 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1545
1546 sky2->speed = sky2_phy_speed(hw, aux);
1547
1548 /* Pause bits are offset (9..8) */
1549 if (hw->chip_id == CHIP_ID_YUKON_XL)
1550 aux >>= 6;
1551
1552 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1553 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1554
1555 if ((sky2->tx_pause || sky2->rx_pause)
1556 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1557 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1558 else
1559 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1560
1561 return 0;
1562}
cd28ab6a
SH		 1563
1564/*
91c86df5 1565 * Interrupt from PHY are handled outside of interrupt context
cd28ab6a
SH		 1566 * because accessing phy registers requires spin wait which might
1567 * cause excess interrupt latency.
1568 */
91c86df5 1569static void sky2_phy_task(void *arg)
cd28ab6a 1570{
91c86df5 1571 struct sky2_port *sky2 = arg;
cd28ab6a 1572 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1573 u16 istatus, phystat;
1574
91c86df5 1575 down(&sky2->phy_sema);
793b883e
SH		 1576 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1577 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
cd28ab6a
SH		 1578
1579 if (netif_msg_intr(sky2))
1580 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1581 sky2->netdev->name, istatus, phystat);
1582
1583 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1584 if (sky2_autoneg_done(sky2, phystat) == 0)
1585 sky2_link_up(sky2);
1586 goto out;
1587 }
cd28ab6a 1588
793b883e
SH		 1589 if (istatus & PHY_M_IS_LSP_CHANGE)
1590 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1591
793b883e
SH		 1592 if (istatus & PHY_M_IS_DUP_CHANGE)
1593 sky2->duplex =
1594 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1595
793b883e
SH		 1596 if (istatus & PHY_M_IS_LST_CHANGE) {
1597 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1598 sky2_link_up(sky2);
793b883e
SH		 1599 else
1600 sky2_link_down(sky2);
cd28ab6a 1601 }
793b883e 1602out:
91c86df5 1603 up(&sky2->phy_sema);
cd28ab6a
SH		 1604
1605 local_irq_disable();
793b883e 1606 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
cd28ab6a
SH		 1607 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1608 local_irq_enable();
1609}
1610
1611static void sky2_tx_timeout(struct net_device *dev)
1612{
1613 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1614 struct sky2_hw *hw = sky2->hw;
1615 unsigned txq = txqaddr[sky2->port];
cd28ab6a
SH		 1616
1617 if (netif_msg_timer(sky2))
1618 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1619
8cc048e3
SH		 1620 netif_stop_queue(dev);
1621
1622 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1623 sky2_read32(hw, Q_ADDR(txq, Q_CSR));
1624
1625 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
cd28ab6a
SH		 1626
1627 sky2_tx_clean(sky2);
8cc048e3
SH		 1628
1629 sky2_qset(hw, txq);
1630 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1631
1632 netif_wake_queue(dev);
cd28ab6a
SH		 1633}
1634
734d1868
SH		 1635
1636#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1637/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1638static inline unsigned sky2_buf_size(int mtu)
1639{
1640 return roundup(mtu + ETH_HLEN + 4, 8);
1641}
1642
cd28ab6a
SH		 1643static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1644{
6b1a3aef 1645 struct sky2_port *sky2 = netdev_priv(dev);
1646 struct sky2_hw *hw = sky2->hw;
1647 int err;
1648 u16 ctl, mode;
cd28ab6a
SH		 1649
1650 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1651 return -EINVAL;
1652
5a5b1ea0 1653 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1654 return -EINVAL;
1655
6b1a3aef 1656 if (!netif_running(dev)) {
1657 dev->mtu = new_mtu;
1658 return 0;
1659 }
1660
6b1a3aef 1661 sky2_write32(hw, B0_IMSK, 0);
1662
018d1c66 1663 dev->trans_start = jiffies; /* prevent tx timeout */
1664 netif_stop_queue(dev);
1665 netif_poll_disable(hw->dev[0]);
1666
6b1a3aef 1667 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1668 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1669 sky2_rx_stop(sky2);
1670 sky2_rx_clean(sky2);
cd28ab6a
SH		 1671
1672 dev->mtu = new_mtu;
734d1868 1673 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef 1674 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1675 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1676
1677 if (dev->mtu > ETH_DATA_LEN)
1678 mode |= GM_SMOD_JUMBO_ENA;
1679
1680 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1681
6b1a3aef 1682 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1683
6b1a3aef 1684 err = sky2_rx_start(sky2);
6b1a3aef 1685 sky2_write32(hw, B0_IMSK, hw->intr_mask);
018d1c66 1686
1b537565
SH		 1687 if (err)
1688 dev_close(dev);
1689 else {
1690 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1691
1692 netif_poll_enable(hw->dev[0]);
1693 netif_wake_queue(dev);
1694 }
1695
cd28ab6a
SH		 1696 return err;
1697}
1698
1699/*
1700 * Receive one packet.
1701 * For small packets or errors, just reuse existing skb.
d571b694 1702 * For larger packets, get new buffer.
cd28ab6a 1703 */
d11c13e7 1704static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1705 u16 length, u32 status)
1706{
cd28ab6a 1707 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1708 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1709
1710 if (unlikely(netif_msg_rx_status(sky2)))
1711 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1712 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1713
793b883e 1714 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1715 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1716
42eeea01 1717 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1718 goto error;
1719
42eeea01 1720 if (!(status & GMR_FS_RX_OK))
1721 goto resubmit;
1722
6e15b712
SH		 1723 if ((status >> 16) != length || length > sky2->rx_bufsize)
1724 goto oversize;
1725
bdb5c58e 1726 if (length < copybreak) {
79e57d32
SH		 1727 skb = alloc_skb(length + 2, GFP_ATOMIC);
1728 if (!skb)
793b883e
SH		 1729 goto resubmit;
1730
79e57d32 1731 skb_reserve(skb, 2);
793b883e
SH		 1732 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1733 length, PCI_DMA_FROMDEVICE);
79e57d32 1734 memcpy(skb->data, re->skb->data, length);
d11c13e7 1735 skb->ip_summed = re->skb->ip_summed;
1736 skb->csum = re->skb->csum;
793b883e
SH		 1737 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1738 length, PCI_DMA_FROMDEVICE);
793b883e 1739 } else {
79e57d32
SH		 1740 struct sk_buff *nskb;
1741
82788c7a 1742 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1743 if (!nskb)
1744 goto resubmit;
cd28ab6a 1745
793b883e 1746 skb = re->skb;
79e57d32 1747 re->skb = nskb;
793b883e 1748 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1749 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1750 prefetch(skb->data);
cd28ab6a 1751
793b883e 1752 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1753 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1754 }
cd28ab6a 1755
79e57d32 1756 skb_put(skb, length);
793b883e 1757resubmit:
d11c13e7 1758 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1759 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1760
bea86103 1761 /* Tell receiver about new buffers. */
1762 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1763 &sky2->rx_last_put, RX_LE_SIZE);
1764
cd28ab6a
SH		 1765 return skb;
1766
6e15b712
SH		 1767oversize:
1768 ++sky2->net_stats.rx_over_errors;
1769 goto resubmit;
1770
cd28ab6a 1771error:
6e15b712
SH		 1772 ++sky2->net_stats.rx_errors;
1773
3be92a70 1774 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a
SH		 1775 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1776 sky2->netdev->name, status, length);
793b883e
SH		 1777
1778 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1779 sky2->net_stats.rx_length_errors++;
1780 if (status & GMR_FS_FRAGMENT)
1781 sky2->net_stats.rx_frame_errors++;
1782 if (status & GMR_FS_CRC_ERR)
1783 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1784 if (status & GMR_FS_RX_FF_OV)
1785 sky2->net_stats.rx_fifo_errors++;
79e57d32 1786
793b883e 1787 goto resubmit;
cd28ab6a
SH		 1788}
1789
2224795d 1790/*
1791 * Check for transmit complete
793b883e 1792 */
13b97b74 1793#define TX_NO_STATUS 0xffff
2224795d 1794
28bd181a 1795static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
13b97b74
SH		 1796{
1797 if (last != TX_NO_STATUS) {
1798 struct net_device *dev = hw->dev[port];
1799 if (dev && netif_running(dev)) {
1800 struct sky2_port *sky2 = netdev_priv(dev);
1801 sky2_tx_complete(sky2, last);
1802 }
2224795d 1803 }
cd28ab6a
SH		 1804}
1805
1806/*
cd28ab6a
SH		 1807 * Both ports share the same status interrupt, therefore there is only
1808 * one poll routine.
cd28ab6a 1809 */
d11c13e7 1810static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 1811{
d11c13e7 1812 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1813 unsigned int to_do = min(dev0->quota, *budget);
cd28ab6a 1814 unsigned int work_done = 0;
793b883e 1815 u16 hwidx;
13b97b74 1816 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
cd28ab6a 1817
793b883e 1818 hwidx = sky2_read16(hw, STAT_PUT_IDX);
79e57d32 1819 BUG_ON(hwidx >= STATUS_RING_SIZE);
af2a58ac 1820 rmb();
bea86103 1821
13210ce5 1822 while (hwidx != hw->st_idx) {
1823 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1824 struct net_device *dev;
d11c13e7 1825 struct sky2_port *sky2;
cd28ab6a 1826 struct sk_buff *skb;
cd28ab6a
SH		 1827 u32 status;
1828 u16 length;
1829
13210ce5 1830 le = hw->st_le + hw->st_idx;
bea86103 1831 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
13210ce5 1832 prefetch(hw->st_le + hw->st_idx);
bea86103 1833
13210ce5 1834 BUG_ON(le->link >= 2);
1835 dev = hw->dev[le->link];
1836 if (dev == NULL || !netif_running(dev))
1837 continue;
1838
1839 sky2 = netdev_priv(dev);
cd28ab6a
SH		 1840 status = le32_to_cpu(le->status);
1841 length = le16_to_cpu(le->length);
cd28ab6a 1842
dc4d5ea2 1843 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1844 case OP_RXSTAT:
d11c13e7 1845 skb = sky2_receive(sky2, length, status);
d1f13708 1846 if (!skb)
1847 break;
13210ce5 1848
1849 skb->dev = dev;
1850 skb->protocol = eth_type_trans(skb, dev);
1851 dev->last_rx = jiffies;
1852
d1f13708 1853#ifdef SKY2_VLAN_TAG_USED
1854 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1855 vlan_hwaccel_receive_skb(skb,
1856 sky2->vlgrp,
1857 be16_to_cpu(sky2->rx_tag));
1858 } else
1859#endif
cd28ab6a 1860 netif_receive_skb(skb);
13210ce5 1861
1862 if (++work_done >= to_do)
1863 goto exit_loop;
cd28ab6a
SH		 1864 break;
1865
d1f13708 1866#ifdef SKY2_VLAN_TAG_USED
1867 case OP_RXVLAN:
1868 sky2->rx_tag = length;
1869 break;
1870
1871 case OP_RXCHKSVLAN:
1872 sky2->rx_tag = length;
1873 /* fall through */
1874#endif
cd28ab6a 1875 case OP_RXCHKS:
d11c13e7 1876 skb = sky2->rx_ring[sky2->rx_next].skb;
1877 skb->ip_summed = CHECKSUM_HW;
1878 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1879 break;
1880
1881 case OP_TXINDEXLE:
13b97b74
SH		 1882 /* TX index reports status for both ports */
1883 tx_done[0] = status & 0xffff;
1884 tx_done[1] = ((status >> 24) & 0xff)
1885 | (u16)(length & 0xf) << 8;
cd28ab6a
SH		 1886 break;
1887
cd28ab6a
SH		 1888 default:
1889 if (net_ratelimit())
793b883e 1890 printk(KERN_WARNING PFX
dc4d5ea2 1891 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a
SH		 1892 break;
1893 }
13210ce5 1894 }
cd28ab6a 1895
13210ce5 1896exit_loop:
3e4b32e1 1897 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
793b883e 1898
13b97b74
SH		 1899 sky2_tx_check(hw, 0, tx_done[0]);
1900 sky2_tx_check(hw, 1, tx_done[1]);
1901
3e4b32e1 1902 if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
13b97b74 1903 /* need to restart TX timer */
cd28ab6a
SH		 1904 if (is_ec_a1(hw)) {
1905 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1906 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1907 }
1908
bea86103 1909 netif_rx_complete(dev0);
cd28ab6a
SH		 1910 hw->intr_mask |= Y2_IS_STAT_BMU;
1911 sky2_write32(hw, B0_IMSK, hw->intr_mask);
13210ce5 1912 return 0;
1913 } else {
1914 *budget -= work_done;
1915 dev0->quota -= work_done;
1916 return 1;
cd28ab6a 1917 }
cd28ab6a
SH		 1918}
1919
1920static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1921{
1922 struct net_device *dev = hw->dev[port];
1923
3be92a70
SH		 1924 if (net_ratelimit())
1925 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1926 dev->name, status);
cd28ab6a
SH		 1927
1928 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 1929 if (net_ratelimit())
1930 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1931 dev->name);
cd28ab6a
SH		 1932 /* Clear IRQ */
1933 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1934 }
1935
1936 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 1937 if (net_ratelimit())
1938 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1939 dev->name);
cd28ab6a
SH		 1940
1941 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1942 }
1943
1944 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 1945 if (net_ratelimit())
1946 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 1947 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1948 }
1949
1950 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 1951 if (net_ratelimit())
1952 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 1953 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1954 }
1955
1956 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 1957 if (net_ratelimit())
1958 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
1959 dev->name);
cd28ab6a
SH		 1960 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1961 }
1962}
1963
1964static void sky2_hw_intr(struct sky2_hw *hw)
1965{
1966 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1967
793b883e 1968 if (status & Y2_IS_TIST_OV)
cd28ab6a 1969 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1970
1971 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 1972 u16 pci_err;
1973
1974 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
3be92a70
SH		 1975 if (net_ratelimit())
1976 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1977 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 1978
1979 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1980 pci_write_config_word(hw->pdev, PCI_STATUS,
1981 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1982 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1983 }
1984
1985 if (status & Y2_IS_PCI_EXP) {
d571b694 1986 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 1987 u32 pex_err;
1988
1989 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
cd28ab6a 1990
3be92a70
SH		 1991 if (net_ratelimit())
1992 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1993 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 1994
1995 /* clear the interrupt */
1996 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1997 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1998 0xffffffffUL);
cd28ab6a
SH		 1999 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2000
2001 if (pex_err & PEX_FATAL_ERRORS) {
2002 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2003 hwmsk &= ~Y2_IS_PCI_EXP;
2004 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2005 }
2006 }
2007
2008 if (status & Y2_HWE_L1_MASK)
2009 sky2_hw_error(hw, 0, status);
2010 status >>= 8;
2011 if (status & Y2_HWE_L1_MASK)
2012 sky2_hw_error(hw, 1, status);
2013}
2014
2015static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2016{
2017 struct net_device *dev = hw->dev[port];
2018 struct sky2_port *sky2 = netdev_priv(dev);
2019 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2020
2021 if (netif_msg_intr(sky2))
2022 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2023 dev->name, status);
2024
2025 if (status & GM_IS_RX_FF_OR) {
2026 ++sky2->net_stats.rx_fifo_errors;
2027 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2028 }
2029
2030 if (status & GM_IS_TX_FF_UR) {
2031 ++sky2->net_stats.tx_fifo_errors;
2032 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2033 }
cd28ab6a
SH		 2034}
2035
2036static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2037{
2038 struct net_device *dev = hw->dev[port];
2039 struct sky2_port *sky2 = netdev_priv(dev);
2040
2041 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2042 sky2_write32(hw, B0_IMSK, hw->intr_mask);
91c86df5 2043 schedule_work(&sky2->phy_task);
cd28ab6a
SH		 2044}
2045
2046static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2047{
2048 struct sky2_hw *hw = dev_id;
bea86103 2049 struct net_device *dev0 = hw->dev[0];
cd28ab6a
SH		 2050 u32 status;
2051
2052 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
793b883e 2053 if (status == 0 || status == ~0)
cd28ab6a
SH		 2054 return IRQ_NONE;
2055
2056 if (status & Y2_IS_HW_ERR)
2057 sky2_hw_intr(hw);
2058
793b883e 2059 /* Do NAPI for Rx and Tx status */
bea86103 2060 if (status & Y2_IS_STAT_BMU) {
cd28ab6a
SH		 2061 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2062 sky2_write32(hw, B0_IMSK, hw->intr_mask);
bea86103 2063
0a122576 2064 if (likely(__netif_rx_schedule_prep(dev0))) {
2065 prefetch(&hw->st_le[hw->st_idx]);
bea86103 2066 __netif_rx_schedule(dev0);
0a122576 2067 }
cd28ab6a
SH		 2068 }
2069
793b883e 2070 if (status & Y2_IS_IRQ_PHY1)
cd28ab6a
SH		 2071 sky2_phy_intr(hw, 0);
2072
2073 if (status & Y2_IS_IRQ_PHY2)
2074 sky2_phy_intr(hw, 1);
2075
2076 if (status & Y2_IS_IRQ_MAC1)
2077 sky2_mac_intr(hw, 0);
2078
2079 if (status & Y2_IS_IRQ_MAC2)
2080 sky2_mac_intr(hw, 1);
2081
cd28ab6a 2082 sky2_write32(hw, B0_Y2_SP_ICR, 2);
793b883e
SH		 2083
2084 sky2_read32(hw, B0_IMSK);
2085
cd28ab6a
SH		 2086 return IRQ_HANDLED;
2087}
2088
2089#ifdef CONFIG_NET_POLL_CONTROLLER
2090static void sky2_netpoll(struct net_device *dev)
2091{
2092 struct sky2_port *sky2 = netdev_priv(dev);
2093
793b883e 2094 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2095}
2096#endif
2097
2098/* Chip internal frequency for clock calculations */
fb17358f 2099static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2100{
793b883e 2101 switch (hw->chip_id) {
cd28ab6a 2102 case CHIP_ID_YUKON_EC:
5a5b1ea0 2103 case CHIP_ID_YUKON_EC_U:
fb17358f 2104 return 125; /* 125 Mhz */
cd28ab6a 2105 case CHIP_ID_YUKON_FE:
fb17358f 2106 return 100; /* 100 Mhz */
793b883e 2107 default: /* YUKON_XL */
fb17358f 2108 return 156; /* 156 Mhz */
cd28ab6a
SH		 2109 }
2110}
2111
fb17358f 2112static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2113{
fb17358f 2114 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2115}
2116
fb17358f 2117static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2118{
fb17358f 2119 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2120}
2121
fb17358f 2122
cd28ab6a
SH		 2123static int sky2_reset(struct sky2_hw *hw)
2124{
5afa0a9c 2125 u32 ctst;
cd28ab6a
SH		 2126 u16 status;
2127 u8 t8, pmd_type;
2128 int i;
2129
2130 ctst = sky2_read32(hw, B0_CTST);
2131
2132 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2133 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2134 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2135 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2136 pci_name(hw->pdev), hw->chip_id);
2137 return -EOPNOTSUPP;
2138 }
2139
793b883e
SH		 2140 /* ring for status responses */
2141 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2142 &hw->st_dma);
2143 if (!hw->st_le)
2144 return -ENOMEM;
2145
cd28ab6a
SH		 2146 /* disable ASF */
2147 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2148 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2149 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2150 }
2151
2152 /* do a SW reset */
2153 sky2_write8(hw, B0_CTST, CS_RST_SET);
2154 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2155
2156 /* clear PCI errors, if any */
793b883e 2157 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
cd28ab6a 2158 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 2159 pci_write_config_word(hw->pdev, PCI_STATUS,
2160 status | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2161
2162 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2163
2164 /* clear any PEX errors */
2165 if (is_pciex(hw)) {
793b883e
SH		 2166 u16 lstat;
2167 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2168 0xffffffffUL);
2169 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
cd28ab6a
SH		 2170 }
2171
2172 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2173 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2174
2175 hw->ports = 1;
2176 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2177 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2178 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2179 ++hw->ports;
2180 }
2181 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2182
5afa0a9c 2183 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2184
2185 for (i = 0; i < hw->ports; i++) {
2186 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2187 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2188 }
2189
2190 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2191
793b883e
SH		 2192 /* Clear I2C IRQ noise */
2193 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2194
2195 /* turn off hardware timer (unused) */
2196 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2197 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2198
cd28ab6a
SH		 2199 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2200
69634ee7
SH		 2201 /* Turn off descriptor polling */
2202 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2203
2204 /* Turn off receive timestamp */
2205 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2206 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2207
2208 /* enable the Tx Arbiters */
2209 for (i = 0; i < hw->ports; i++)
2210 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2211
2212 /* Initialize ram interface */
2213 for (i = 0; i < hw->ports; i++) {
793b883e 2214 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2215
2216 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2217 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2218 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2219 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2220 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2221 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2222 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2223 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2224 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2225 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2226 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2227 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2228 }
2229
cd28ab6a
SH		 2230 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2231
cd28ab6a
SH		 2232 for (i = 0; i < hw->ports; i++)
2233 sky2_phy_reset(hw, i);
cd28ab6a 2234
cd28ab6a
SH		 2235 memset(hw->st_le, 0, STATUS_LE_BYTES);
2236 hw->st_idx = 0;
2237
2238 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2239 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2240
2241 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2242 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2243
2244 /* Set the list last index */
793b883e 2245 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2246
793b883e 2247 /* These status setup values are copied from SysKonnect's driver */
cd28ab6a
SH		 2248 if (is_ec_a1(hw)) {
2249 /* WA for dev. #4.3 */
793b883e 2250 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
cd28ab6a
SH		 2251
2252 /* set Status-FIFO watermark */
2253 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2254
2255 /* set Status-FIFO ISR watermark */
793b883e 2256 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
69634ee7 2257 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
cd28ab6a 2258 } else {
69634ee7
SH		 2259 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2260 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a
SH		 2261
2262 /* set Status-FIFO ISR watermark */
2263 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
69634ee7
SH		 2264 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2265 else
2266 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2267
69634ee7
SH		 2268 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2269 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2270 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
cd28ab6a
SH		 2271 }
2272
793b883e 2273 /* enable status unit */
cd28ab6a
SH		 2274 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2275
2276 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2277 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2278 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2279
2280 return 0;
2281}
2282
28bd181a 2283static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2284{
2285 u32 modes;
2286 if (hw->copper) {
793b883e
SH		 2287 modes = SUPPORTED_10baseT_Half
2288 | SUPPORTED_10baseT_Full
2289 | SUPPORTED_100baseT_Half
2290 | SUPPORTED_100baseT_Full
2291 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2292
2293 if (hw->chip_id != CHIP_ID_YUKON_FE)
2294 modes |= SUPPORTED_1000baseT_Half
793b883e 2295 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2296 } else
2297 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2298 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2299 return modes;
2300}
2301
793b883e 2302static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2303{
2304 struct sky2_port *sky2 = netdev_priv(dev);
2305 struct sky2_hw *hw = sky2->hw;
2306
2307 ecmd->transceiver = XCVR_INTERNAL;
2308 ecmd->supported = sky2_supported_modes(hw);
2309 ecmd->phy_address = PHY_ADDR_MARV;
2310 if (hw->copper) {
2311 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2312 | SUPPORTED_10baseT_Full
2313 | SUPPORTED_100baseT_Half
2314 | SUPPORTED_100baseT_Full
2315 | SUPPORTED_1000baseT_Half
2316 | SUPPORTED_1000baseT_Full
2317 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2318 ecmd->port = PORT_TP;
2319 } else
2320 ecmd->port = PORT_FIBRE;
2321
2322 ecmd->advertising = sky2->advertising;
2323 ecmd->autoneg = sky2->autoneg;
2324 ecmd->speed = sky2->speed;
2325 ecmd->duplex = sky2->duplex;
2326 return 0;
2327}
2328
2329static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2330{
2331 struct sky2_port *sky2 = netdev_priv(dev);
2332 const struct sky2_hw *hw = sky2->hw;
2333 u32 supported = sky2_supported_modes(hw);
2334
2335 if (ecmd->autoneg == AUTONEG_ENABLE) {
2336 ecmd->advertising = supported;
2337 sky2->duplex = -1;
2338 sky2->speed = -1;
2339 } else {
2340 u32 setting;
2341
793b883e 2342 switch (ecmd->speed) {
cd28ab6a
SH		 2343 case SPEED_1000:
2344 if (ecmd->duplex == DUPLEX_FULL)
2345 setting = SUPPORTED_1000baseT_Full;
2346 else if (ecmd->duplex == DUPLEX_HALF)
2347 setting = SUPPORTED_1000baseT_Half;
2348 else
2349 return -EINVAL;
2350 break;
2351 case SPEED_100:
2352 if (ecmd->duplex == DUPLEX_FULL)
2353 setting = SUPPORTED_100baseT_Full;
2354 else if (ecmd->duplex == DUPLEX_HALF)
2355 setting = SUPPORTED_100baseT_Half;
2356 else
2357 return -EINVAL;
2358 break;
2359
2360 case SPEED_10:
2361 if (ecmd->duplex == DUPLEX_FULL)
2362 setting = SUPPORTED_10baseT_Full;
2363 else if (ecmd->duplex == DUPLEX_HALF)
2364 setting = SUPPORTED_10baseT_Half;
2365 else
2366 return -EINVAL;
2367 break;
2368 default:
2369 return -EINVAL;
2370 }
2371
2372 if ((setting & supported) == 0)
2373 return -EINVAL;
2374
2375 sky2->speed = ecmd->speed;
2376 sky2->duplex = ecmd->duplex;
2377 }
2378
2379 sky2->autoneg = ecmd->autoneg;
2380 sky2->advertising = ecmd->advertising;
2381
1b537565
SH		 2382 if (netif_running(dev))
2383 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2384
2385 return 0;
2386}
2387
2388static void sky2_get_drvinfo(struct net_device *dev,
2389 struct ethtool_drvinfo *info)
2390{
2391 struct sky2_port *sky2 = netdev_priv(dev);
2392
2393 strcpy(info->driver, DRV_NAME);
2394 strcpy(info->version, DRV_VERSION);
2395 strcpy(info->fw_version, "N/A");
2396 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2397}
2398
2399static const struct sky2_stat {
793b883e
SH		 2400 char name[ETH_GSTRING_LEN];
2401 u16 offset;
cd28ab6a
SH		 2402} sky2_stats[] = {
2403 { "tx_bytes", GM_TXO_OK_HI },
2404 { "rx_bytes", GM_RXO_OK_HI },
2405 { "tx_broadcast", GM_TXF_BC_OK },
2406 { "rx_broadcast", GM_RXF_BC_OK },
2407 { "tx_multicast", GM_TXF_MC_OK },
2408 { "rx_multicast", GM_RXF_MC_OK },
2409 { "tx_unicast", GM_TXF_UC_OK },
2410 { "rx_unicast", GM_RXF_UC_OK },
2411 { "tx_mac_pause", GM_TXF_MPAUSE },
2412 { "rx_mac_pause", GM_RXF_MPAUSE },
2413 { "collisions", GM_TXF_SNG_COL },
2414 { "late_collision",GM_TXF_LAT_COL },
2415 { "aborted", GM_TXF_ABO_COL },
2416 { "multi_collisions", GM_TXF_MUL_COL },
2417 { "fifo_underrun", GM_TXE_FIFO_UR },
2418 { "fifo_overflow", GM_RXE_FIFO_OV },
2419 { "rx_toolong", GM_RXF_LNG_ERR },
2420 { "rx_jabber", GM_RXF_JAB_PKT },
2421 { "rx_runt", GM_RXE_FRAG },
2422 { "rx_too_long", GM_RXF_LNG_ERR },
2423 { "rx_fcs_error", GM_RXF_FCS_ERR },
2424};
2425
cd28ab6a
SH		 2426static u32 sky2_get_rx_csum(struct net_device *dev)
2427{
2428 struct sky2_port *sky2 = netdev_priv(dev);
2429
2430 return sky2->rx_csum;
2431}
2432
2433static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2434{
2435 struct sky2_port *sky2 = netdev_priv(dev);
2436
2437 sky2->rx_csum = data;
793b883e 2438
cd28ab6a
SH		 2439 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2440 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2441
2442 return 0;
2443}
2444
2445static u32 sky2_get_msglevel(struct net_device *netdev)
2446{
2447 struct sky2_port *sky2 = netdev_priv(netdev);
2448 return sky2->msg_enable;
2449}
2450
9a7ae0a9
SH		 2451static int sky2_nway_reset(struct net_device *dev)
2452{
2453 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2454
2455 if (sky2->autoneg != AUTONEG_ENABLE)
2456 return -EINVAL;
2457
1b537565 2458 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2459
2460 return 0;
2461}
2462
793b883e 2463static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2464{
2465 struct sky2_hw *hw = sky2->hw;
2466 unsigned port = sky2->port;
2467 int i;
2468
2469 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2470 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2471 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2472 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2473
793b883e 2474 for (i = 2; i < count; i++)
cd28ab6a
SH		 2475 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2476}
2477
cd28ab6a
SH		 2478static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2479{
2480 struct sky2_port *sky2 = netdev_priv(netdev);
2481 sky2->msg_enable = value;
2482}
2483
2484static int sky2_get_stats_count(struct net_device *dev)
2485{
2486 return ARRAY_SIZE(sky2_stats);
2487}
2488
2489static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2490 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2491{
2492 struct sky2_port *sky2 = netdev_priv(dev);
2493
793b883e 2494 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2495}
2496
793b883e 2497static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2498{
2499 int i;
2500
2501 switch (stringset) {
2502 case ETH_SS_STATS:
2503 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2504 memcpy(data + i * ETH_GSTRING_LEN,
2505 sky2_stats[i].name, ETH_GSTRING_LEN);
2506 break;
2507 }
2508}
2509
2510/* Use hardware MIB variables for critical path statistics and
2511 * transmit feedback not reported at interrupt.
2512 * Other errors are accounted for in interrupt handler.
2513 */
2514static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2515{
2516 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2517 u64 data[13];
cd28ab6a 2518
793b883e 2519 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2520
2521 sky2->net_stats.tx_bytes = data[0];
2522 sky2->net_stats.rx_bytes = data[1];
2523 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2524 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2525 sky2->net_stats.multicast = data[5] + data[7];
2526 sky2->net_stats.collisions = data[10];
2527 sky2->net_stats.tx_aborted_errors = data[12];
2528
2529 return &sky2->net_stats;
2530}
2531
2532static int sky2_set_mac_address(struct net_device *dev, void *p)
2533{
2534 struct sky2_port *sky2 = netdev_priv(dev);
2535 struct sockaddr *addr = p;
cd28ab6a
SH		 2536
2537 if (!is_valid_ether_addr(addr->sa_data))
2538 return -EADDRNOTAVAIL;
2539
cd28ab6a 2540 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
793b883e 2541 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
cd28ab6a 2542 dev->dev_addr, ETH_ALEN);
793b883e 2543 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
cd28ab6a 2544 dev->dev_addr, ETH_ALEN);
1b537565
SH		 2545
2546 if (netif_running(dev))
2547 sky2_phy_reinit(sky2);
2548
2549 return 0;
cd28ab6a
SH		 2550}
2551
2552static void sky2_set_multicast(struct net_device *dev)
2553{
2554 struct sky2_port *sky2 = netdev_priv(dev);
2555 struct sky2_hw *hw = sky2->hw;
2556 unsigned port = sky2->port;
2557 struct dev_mc_list *list = dev->mc_list;
2558 u16 reg;
2559 u8 filter[8];
2560
2561 memset(filter, 0, sizeof(filter));
2562
2563 reg = gma_read16(hw, port, GM_RX_CTRL);
2564 reg |= GM_RXCR_UCF_ENA;
2565
d571b694 2566 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2567 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2568 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2569 memset(filter, 0xff, sizeof(filter));
793b883e 2570 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2571 reg &= ~GM_RXCR_MCF_ENA;
2572 else {
2573 int i;
2574 reg |= GM_RXCR_MCF_ENA;
2575
2576 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2577 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2578 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2579 }
2580 }
2581
cd28ab6a 2582 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2583 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2584 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2585 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2586 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2587 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2588 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2589 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2590
2591 gma_write16(hw, port, GM_RX_CTRL, reg);
2592}
2593
2594/* Can have one global because blinking is controlled by
2595 * ethtool and that is always under RTNL mutex
2596 */
91c86df5 2597static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2598{
793b883e
SH		 2599 u16 pg;
2600
793b883e
SH		 2601 switch (hw->chip_id) {
2602 case CHIP_ID_YUKON_XL:
2603 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2604 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2605 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2606 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2607 PHY_M_LEDC_INIT_CTRL(7) |
2608 PHY_M_LEDC_STA1_CTRL(7) |
2609 PHY_M_LEDC_STA0_CTRL(7))
2610 : 0);
2611
2612 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2613 break;
2614
2615 default:
2616 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2617 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2618 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2619 PHY_M_LED_MO_10(MO_LED_ON) |
2620 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2621 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2622 PHY_M_LED_MO_RX(MO_LED_ON)
2623 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2624 PHY_M_LED_MO_10(MO_LED_OFF) |
2625 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2626 PHY_M_LED_MO_1000(MO_LED_OFF) |
2627 PHY_M_LED_MO_RX(MO_LED_OFF));
2628
793b883e 2629 }
cd28ab6a
SH		 2630}
2631
2632/* blink LED's for finding board */
2633static int sky2_phys_id(struct net_device *dev, u32 data)
2634{
2635 struct sky2_port *sky2 = netdev_priv(dev);
2636 struct sky2_hw *hw = sky2->hw;
2637 unsigned port = sky2->port;
793b883e 2638 u16 ledctrl, ledover = 0;
cd28ab6a 2639 long ms;
91c86df5 2640 int interrupted;
cd28ab6a
SH		 2641 int onoff = 1;
2642
793b883e 2643 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2644 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2645 else
2646 ms = data * 1000;
2647
2648 /* save initial values */
91c86df5 2649 down(&sky2->phy_sema);
793b883e
SH		 2650 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2651 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2652 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2653 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2654 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2655 } else {
2656 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2657 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2658 }
cd28ab6a 2659
91c86df5
SH		 2660 interrupted = 0;
2661 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2662 sky2_led(hw, port, onoff);
2663 onoff = !onoff;
2664
91c86df5
SH		 2665 up(&sky2->phy_sema);
2666 interrupted = msleep_interruptible(250);
2667 down(&sky2->phy_sema);
2668
cd28ab6a
SH		 2669 ms -= 250;
2670 }
2671
2672 /* resume regularly scheduled programming */
793b883e
SH		 2673 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2674 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2676 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2678 } else {
2679 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2680 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2681 }
91c86df5 2682 up(&sky2->phy_sema);
cd28ab6a
SH		 2683
2684 return 0;
2685}
2686
2687static void sky2_get_pauseparam(struct net_device *dev,
2688 struct ethtool_pauseparam *ecmd)
2689{
2690 struct sky2_port *sky2 = netdev_priv(dev);
2691
2692 ecmd->tx_pause = sky2->tx_pause;
2693 ecmd->rx_pause = sky2->rx_pause;
2694 ecmd->autoneg = sky2->autoneg;
2695}
2696
2697static int sky2_set_pauseparam(struct net_device *dev,
2698 struct ethtool_pauseparam *ecmd)
2699{
2700 struct sky2_port *sky2 = netdev_priv(dev);
2701 int err = 0;
2702
2703 sky2->autoneg = ecmd->autoneg;
2704 sky2->tx_pause = ecmd->tx_pause != 0;
2705 sky2->rx_pause = ecmd->rx_pause != 0;
2706
1b537565 2707 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2708
2709 return err;
2710}
2711
2712#ifdef CONFIG_PM
2713static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2714{
2715 struct sky2_port *sky2 = netdev_priv(dev);
2716
2717 wol->supported = WAKE_MAGIC;
2718 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2719}
2720
2721static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2722{
2723 struct sky2_port *sky2 = netdev_priv(dev);
2724 struct sky2_hw *hw = sky2->hw;
2725
2726 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2727 return -EOPNOTSUPP;
2728
2729 sky2->wol = wol->wolopts == WAKE_MAGIC;
2730
2731 if (sky2->wol) {
2732 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2733
2734 sky2_write16(hw, WOL_CTRL_STAT,
2735 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2736 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2737 } else
2738 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2739
2740 return 0;
2741}
2742#endif
2743
fb17358f
SH		 2744static int sky2_get_coalesce(struct net_device *dev,
2745 struct ethtool_coalesce *ecmd)
2746{
2747 struct sky2_port *sky2 = netdev_priv(dev);
2748 struct sky2_hw *hw = sky2->hw;
2749
2750 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2751 ecmd->tx_coalesce_usecs = 0;
2752 else {
2753 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2754 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2755 }
2756 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2757
2758 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2759 ecmd->rx_coalesce_usecs = 0;
2760 else {
2761 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2762 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2763 }
2764 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2765
2766 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2767 ecmd->rx_coalesce_usecs_irq = 0;
2768 else {
2769 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2770 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2771 }
2772
2773 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2774
2775 return 0;
2776}
2777
2778/* Note: this affect both ports */
2779static int sky2_set_coalesce(struct net_device *dev,
2780 struct ethtool_coalesce *ecmd)
2781{
2782 struct sky2_port *sky2 = netdev_priv(dev);
2783 struct sky2_hw *hw = sky2->hw;
2784 const u32 tmin = sky2_clk2us(hw, 1);
2785 const u32 tmax = 5000;
2786
2787 if (ecmd->tx_coalesce_usecs != 0 &&
2788 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2789 return -EINVAL;
2790
2791 if (ecmd->rx_coalesce_usecs != 0 &&
2792 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2793 return -EINVAL;
2794
2795 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2796 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2797 return -EINVAL;
2798
2799 if (ecmd->tx_max_coalesced_frames > 0xffff)
2800 return -EINVAL;
2801 if (ecmd->rx_max_coalesced_frames > 0xff)
2802 return -EINVAL;
2803 if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2804 return -EINVAL;
2805
2806 if (ecmd->tx_coalesce_usecs == 0)
2807 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2808 else {
2809 sky2_write32(hw, STAT_TX_TIMER_INI,
2810 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2811 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2812 }
2813 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2814
2815 if (ecmd->rx_coalesce_usecs == 0)
2816 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2817 else {
2818 sky2_write32(hw, STAT_LEV_TIMER_INI,
2819 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2820 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2821 }
2822 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2823
2824 if (ecmd->rx_coalesce_usecs_irq == 0)
2825 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2826 else {
2827 sky2_write32(hw, STAT_TX_TIMER_INI,
2828 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2829 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2830 }
2831 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2832 return 0;
2833}
2834
793b883e
SH		 2835static void sky2_get_ringparam(struct net_device *dev,
2836 struct ethtool_ringparam *ering)
2837{
2838 struct sky2_port *sky2 = netdev_priv(dev);
2839
2840 ering->rx_max_pending = RX_MAX_PENDING;
2841 ering->rx_mini_max_pending = 0;
2842 ering->rx_jumbo_max_pending = 0;
2843 ering->tx_max_pending = TX_RING_SIZE - 1;
2844
2845 ering->rx_pending = sky2->rx_pending;
2846 ering->rx_mini_pending = 0;
2847 ering->rx_jumbo_pending = 0;
2848 ering->tx_pending = sky2->tx_pending;
2849}
2850
2851static int sky2_set_ringparam(struct net_device *dev,
2852 struct ethtool_ringparam *ering)
2853{
2854 struct sky2_port *sky2 = netdev_priv(dev);
2855 int err = 0;
2856
2857 if (ering->rx_pending > RX_MAX_PENDING ||
2858 ering->rx_pending < 8 ||
2859 ering->tx_pending < MAX_SKB_TX_LE ||
2860 ering->tx_pending > TX_RING_SIZE - 1)
2861 return -EINVAL;
2862
2863 if (netif_running(dev))
2864 sky2_down(dev);
2865
2866 sky2->rx_pending = ering->rx_pending;
2867 sky2->tx_pending = ering->tx_pending;
2868
1b537565 2869 if (netif_running(dev)) {
793b883e 2870 err = sky2_up(dev);
1b537565
SH		 2871 if (err)
2872 dev_close(dev);
6ed995bb
SH		 2873 else
2874 sky2_set_multicast(dev);
1b537565 2875 }
793b883e
SH		 2876
2877 return err;
2878}
2879
793b883e
SH		 2880static int sky2_get_regs_len(struct net_device *dev)
2881{
6e4cbb34 2882 return 0x4000;
793b883e
SH		 2883}
2884
2885/*
2886 * Returns copy of control register region
6e4cbb34 2887 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2888 */
2889static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2890 void *p)
2891{
2892 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2893 const void __iomem *io = sky2->hw->regs;
793b883e 2894
6e4cbb34 2895 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2896 regs->version = 1;
6e4cbb34 2897 memset(p, 0, regs->len);
793b883e 2898
6e4cbb34
SH		 2899 memcpy_fromio(p, io, B3_RAM_ADDR);
2900
2901 memcpy_fromio(p + B3_RI_WTO_R1,
2902 io + B3_RI_WTO_R1,
2903 regs->len - B3_RI_WTO_R1);
793b883e 2904}
cd28ab6a
SH		 2905
2906static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2907 .get_settings = sky2_get_settings,
2908 .set_settings = sky2_set_settings,
2909 .get_drvinfo = sky2_get_drvinfo,
2910 .get_msglevel = sky2_get_msglevel,
2911 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2912 .nway_reset = sky2_nway_reset,
793b883e
SH		 2913 .get_regs_len = sky2_get_regs_len,
2914 .get_regs = sky2_get_regs,
2915 .get_link = ethtool_op_get_link,
2916 .get_sg = ethtool_op_get_sg,
2917 .set_sg = ethtool_op_set_sg,
2918 .get_tx_csum = ethtool_op_get_tx_csum,
2919 .set_tx_csum = ethtool_op_set_tx_csum,
2920 .get_tso = ethtool_op_get_tso,
2921 .set_tso = ethtool_op_set_tso,
2922 .get_rx_csum = sky2_get_rx_csum,
2923 .set_rx_csum = sky2_set_rx_csum,
2924 .get_strings = sky2_get_strings,
fb17358f
SH		 2925 .get_coalesce = sky2_get_coalesce,
2926 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 2927 .get_ringparam = sky2_get_ringparam,
2928 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2929 .get_pauseparam = sky2_get_pauseparam,
2930 .set_pauseparam = sky2_set_pauseparam,
2931#ifdef CONFIG_PM
793b883e
SH		 2932 .get_wol = sky2_get_wol,
2933 .set_wol = sky2_set_wol,
cd28ab6a 2934#endif
793b883e 2935 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2936 .get_stats_count = sky2_get_stats_count,
2937 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2938 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2939};
2940
2941/* Initialize network device */
2942static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2943 unsigned port, int highmem)
2944{
2945 struct sky2_port *sky2;
2946 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2947
2948 if (!dev) {
2949 printk(KERN_ERR "sky2 etherdev alloc failed");
2950 return NULL;
2951 }
2952
2953 SET_MODULE_OWNER(dev);
2954 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 2955 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 2956 dev->open = sky2_up;
2957 dev->stop = sky2_down;
ef743d33 2958 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 2959 dev->hard_start_xmit = sky2_xmit_frame;
2960 dev->get_stats = sky2_get_stats;
2961 dev->set_multicast_list = sky2_set_multicast;
2962 dev->set_mac_address = sky2_set_mac_address;
2963 dev->change_mtu = sky2_change_mtu;
2964 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2965 dev->tx_timeout = sky2_tx_timeout;
2966 dev->watchdog_timeo = TX_WATCHDOG;
2967 if (port == 0)
2968 dev->poll = sky2_poll;
2969 dev->weight = NAPI_WEIGHT;
2970#ifdef CONFIG_NET_POLL_CONTROLLER
2971 dev->poll_controller = sky2_netpoll;
2972#endif
cd28ab6a
SH		 2973
2974 sky2 = netdev_priv(dev);
2975 sky2->netdev = dev;
2976 sky2->hw = hw;
2977 sky2->msg_enable = netif_msg_init(debug, default_msg);
2978
2979 spin_lock_init(&sky2->tx_lock);
2980 /* Auto speed and flow control */
2981 sky2->autoneg = AUTONEG_ENABLE;
585b5601 2982 sky2->tx_pause = 1;
cd28ab6a
SH		 2983 sky2->rx_pause = 1;
2984 sky2->duplex = -1;
2985 sky2->speed = -1;
2986 sky2->advertising = sky2_supported_modes(hw);
75d070c5
SH		 2987
2988 /* Receive checksum disabled for Yukon XL
2989 * because of observed problems with incorrect
2990 * values when multiple packets are received in one interrupt
2991 */
2992 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
2993
91c86df5
SH		 2994 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
2995 init_MUTEX(&sky2->phy_sema);
793b883e
SH		 2996 sky2->tx_pending = TX_DEF_PENDING;
2997 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
734d1868 2998 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 2999
3000 hw->dev[port] = dev;
3001
3002 sky2->port = port;
3003
5a5b1ea0 3004 dev->features |= NETIF_F_LLTX;
3005 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3006 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3007 if (highmem)
3008 dev->features |= NETIF_F_HIGHDMA;
793b883e 3009 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3010
d1f13708 3011#ifdef SKY2_VLAN_TAG_USED
3012 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3013 dev->vlan_rx_register = sky2_vlan_rx_register;
3014 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3015#endif
3016
cd28ab6a 3017 /* read the mac address */
793b883e 3018 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3019 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3020
3021 /* device is off until link detection */
3022 netif_carrier_off(dev);
3023 netif_stop_queue(dev);
3024
3025 return dev;
3026}
3027
28bd181a 3028static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3029{
3030 const struct sky2_port *sky2 = netdev_priv(dev);
3031
3032 if (netif_msg_probe(sky2))
3033 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3034 dev->name,
3035 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3036 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3037}
3038
3039static int __devinit sky2_probe(struct pci_dev *pdev,
3040 const struct pci_device_id *ent)
3041{
793b883e 3042 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3043 struct sky2_hw *hw;
5afa0a9c 3044 int err, pm_cap, using_dac = 0;
cd28ab6a 3045
793b883e
SH		 3046 err = pci_enable_device(pdev);
3047 if (err) {
cd28ab6a
SH		 3048 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3049 pci_name(pdev));
3050 goto err_out;
3051 }
3052
793b883e
SH		 3053 err = pci_request_regions(pdev, DRV_NAME);
3054 if (err) {
cd28ab6a
SH		 3055 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3056 pci_name(pdev));
793b883e 3057 goto err_out;
cd28ab6a
SH		 3058 }
3059
3060 pci_set_master(pdev);
3061
5afa0a9c 3062 /* Find power-management capability. */
3063 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3064 if (pm_cap == 0) {
3065 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3066 "aborting.\n");
3067 err = -EIO;
3068 goto err_out_free_regions;
3069 }
3070
d1f3d4dd
SH		 3071 if (sizeof(dma_addr_t) > sizeof(u32) &&
3072 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3073 using_dac = 1;
3074 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3075 if (err < 0) {
3076 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3077 "for consistent allocations\n", pci_name(pdev));
3078 goto err_out_free_regions;
3079 }
cd28ab6a 3080
d1f3d4dd 3081 } else {
cd28ab6a
SH		 3082 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3083 if (err) {
3084 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3085 pci_name(pdev));
3086 goto err_out_free_regions;
3087 }
3088 }
d1f3d4dd 3089
cd28ab6a 3090#ifdef __BIG_ENDIAN
d571b694 3091 /* byte swap descriptors in hardware */
cd28ab6a
SH		 3092 {
3093 u32 reg;
3094
3095 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3096 reg |= PCI_REV_DESC;
3097 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3098 }
3099#endif
3100
3101 err = -ENOMEM;
6aad85d6 3102 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3103 if (!hw) {
3104 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3105 pci_name(pdev));
3106 goto err_out_free_regions;
3107 }
3108
cd28ab6a 3109 hw->pdev = pdev;
cd28ab6a
SH		 3110
3111 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3112 if (!hw->regs) {
3113 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3114 pci_name(pdev));
3115 goto err_out_free_hw;
3116 }
5afa0a9c 3117 hw->pm_cap = pm_cap;
cd28ab6a 3118
cd28ab6a
SH		 3119 err = sky2_reset(hw);
3120 if (err)
793b883e 3121 goto err_out_iounmap;
cd28ab6a 3122
5f4f9dc1 3123 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3124 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3125 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3126 hw->chip_id, hw->chip_rev);
cd28ab6a 3127
793b883e
SH		 3128 dev = sky2_init_netdev(hw, 0, using_dac);
3129 if (!dev)
cd28ab6a
SH		 3130 goto err_out_free_pci;
3131
793b883e
SH		 3132 err = register_netdev(dev);
3133 if (err) {
cd28ab6a
SH		 3134 printk(KERN_ERR PFX "%s: cannot register net device\n",
3135 pci_name(pdev));
3136 goto err_out_free_netdev;
3137 }
3138
3139 sky2_show_addr(dev);
3140
3141 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3142 if (register_netdev(dev1) == 0)
3143 sky2_show_addr(dev1);
3144 else {
3145 /* Failure to register second port need not be fatal */
793b883e
SH		 3146 printk(KERN_WARNING PFX
3147 "register of second port failed\n");
cd28ab6a
SH		 3148 hw->dev[1] = NULL;
3149 free_netdev(dev1);
3150 }
3151 }
3152
793b883e
SH		 3153 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3154 if (err) {
3155 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3156 pci_name(pdev), pdev->irq);
3157 goto err_out_unregister;
3158 }
3159
3160 hw->intr_mask = Y2_IS_BASE;
3161 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3162
3163 pci_set_drvdata(pdev, hw);
3164
cd28ab6a
SH		 3165 return 0;
3166
793b883e
SH		 3167err_out_unregister:
3168 if (dev1) {
3169 unregister_netdev(dev1);
3170 free_netdev(dev1);
3171 }
3172 unregister_netdev(dev);
cd28ab6a
SH		 3173err_out_free_netdev:
3174 free_netdev(dev);
cd28ab6a 3175err_out_free_pci:
793b883e 3176 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3177 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3178err_out_iounmap:
3179 iounmap(hw->regs);
3180err_out_free_hw:
3181 kfree(hw);
3182err_out_free_regions:
3183 pci_release_regions(pdev);
cd28ab6a 3184 pci_disable_device(pdev);
cd28ab6a
SH		 3185err_out:
3186 return err;
3187}
3188
3189static void __devexit sky2_remove(struct pci_dev *pdev)
3190{
793b883e 3191 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3192 struct net_device *dev0, *dev1;
3193
793b883e 3194 if (!hw)
cd28ab6a
SH		 3195 return;
3196
cd28ab6a 3197 dev0 = hw->dev[0];
793b883e
SH		 3198 dev1 = hw->dev[1];
3199 if (dev1)
3200 unregister_netdev(dev1);
cd28ab6a
SH		 3201 unregister_netdev(dev0);
3202
793b883e 3203 sky2_write32(hw, B0_IMSK, 0);
5afa0a9c 3204 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3205 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3206 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3207 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3208
3209 free_irq(pdev->irq, hw);
793b883e 3210 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3211 pci_release_regions(pdev);
3212 pci_disable_device(pdev);
793b883e 3213
cd28ab6a
SH		 3214 if (dev1)
3215 free_netdev(dev1);
3216 free_netdev(dev0);
3217 iounmap(hw->regs);
3218 kfree(hw);
5afa0a9c 3219
cd28ab6a
SH		 3220 pci_set_drvdata(pdev, NULL);
3221}
3222
3223#ifdef CONFIG_PM
3224static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3225{
793b883e 3226 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3227 int i;
cd28ab6a
SH		 3228
3229 for (i = 0; i < 2; i++) {
3230 struct net_device *dev = hw->dev[i];
3231
3232 if (dev) {
5afa0a9c 3233 if (!netif_running(dev))
3234 continue;
3235
3236 sky2_down(dev);
cd28ab6a 3237 netif_device_detach(dev);
cd28ab6a
SH		 3238 }
3239 }
3240
5afa0a9c 3241 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3242}
3243
3244static int sky2_resume(struct pci_dev *pdev)
3245{
793b883e 3246 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3247 int i;
3248
cd28ab6a
SH		 3249 pci_restore_state(pdev);
3250 pci_enable_wake(pdev, PCI_D0, 0);
5afa0a9c 3251 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 3252
3253 sky2_reset(hw);
3254
3255 for (i = 0; i < 2; i++) {
3256 struct net_device *dev = hw->dev[i];
3257 if (dev) {
5afa0a9c 3258 if (netif_running(dev)) {
3259 netif_device_attach(dev);
1b537565
SH		 3260 if (sky2_up(dev))
3261 dev_close(dev);
5afa0a9c 3262 }
cd28ab6a
SH		 3263 }
3264 }
3265 return 0;
3266}
3267#endif
3268
3269static struct pci_driver sky2_driver = {
793b883e
SH		 3270 .name = DRV_NAME,
3271 .id_table = sky2_id_table,
3272 .probe = sky2_probe,
3273 .remove = __devexit_p(sky2_remove),
cd28ab6a 3274#ifdef CONFIG_PM
793b883e
SH		 3275 .suspend = sky2_suspend,
3276 .resume = sky2_resume,
cd28ab6a
SH		 3277#endif
3278};
3279
3280static int __init sky2_init_module(void)
3281{
50241c4c 3282 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3283}
3284
3285static void __exit sky2_cleanup_module(void)
3286{
3287 pci_unregister_driver(&sky2_driver);
3288}
3289
3290module_init(sky2_init_module);
3291module_exit(sky2_cleanup_module);
3292
3293MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3294MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3295MODULE_LICENSE("GPL");
5f4f9dc1 3296MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)