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[PATCH] irq-flags: drivers/net: Use the new IRQF_ constants
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
c9b84dca 53#define DRV_VERSION "1.4"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
61 */
62
13210ce5 63#define RX_LE_SIZE 512
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 65#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76#define ETH_JUMBO_MTU 9000
77#define TX_WATCHDOG (5 * HZ)
78#define NAPI_WEIGHT 64
79#define PHY_RETRIES 1000
80
cb5d9547
SH		 81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH		 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH		 89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
bdb5c58e
SH		 92static int copybreak __read_mostly = 256;
93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH		 96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
01bd7564
SH		 100static int idle_timeout = 100;
101module_param(idle_timeout, int, 0);
102MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
103
cd28ab6a 104static const struct pci_device_id sky2_id_table[] = {
793b883e 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
cd28ab6a
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 123 { 0 }
124};
793b883e 125
cd28ab6a
SH		 126MODULE_DEVICE_TABLE(pci, sky2_id_table);
127
128/* Avoid conditionals by using array */
129static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 131static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 132
92f965e8
SH		 133/* This driver supports yukon2 chipset only */
134static const char *yukon2_name[] = {
135 "XL", /* 0xb3 */
136 "EC Ultra", /* 0xb4 */
137 "UNKNOWN", /* 0xb5 */
138 "EC", /* 0xb6 */
139 "FE", /* 0xb7 */
793b883e
SH		 140};
141
793b883e 142/* Access to external PHY */
ef743d33 143static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 144{
145 int i;
146
147 gma_write16(hw, port, GM_SMI_DATA, val);
148 gma_write16(hw, port, GM_SMI_CTRL,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
150
151 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 152 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 153 return 0;
793b883e 154 udelay(1);
cd28ab6a 155 }
ef743d33 156
793b883e 157 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 158 return -ETIMEDOUT;
cd28ab6a
SH		 159}
160
ef743d33 161static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 162{
163 int i;
164
793b883e 165 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 166 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
167
168 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 169 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
170 *val = gma_read16(hw, port, GM_SMI_DATA);
171 return 0;
172 }
173
793b883e 174 udelay(1);
cd28ab6a
SH		 175 }
176
ef743d33 177 return -ETIMEDOUT;
178}
179
180static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
181{
182 u16 v;
183
184 if (__gm_phy_read(hw, port, reg, &v) != 0)
185 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
186 return v;
cd28ab6a
SH		 187}
188
2ccc99b7 189static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c 190{
191 u16 power_control;
192 u32 reg1;
193 int vaux;
5afa0a9c 194
195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
197
56a645cc 198 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 199 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c 200 (power_control & PCI_PM_CAP_PME_D3cold);
201
56a645cc 202 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c 203
204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
206
207 switch (state) {
208 case PCI_D0:
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 else
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224
225 /* Turn off phy power saving */
56a645cc 226 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c 227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
228
d571b694 229 /* looks like this XL is back asswards .. */
5afa0a9c 230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
231 reg1 |= PCI_Y2_PHY1_COMA;
232 if (hw->ports > 1)
233 reg1 |= PCI_Y2_PHY2_COMA;
234 }
977bdf06
SH		 235
236 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
86a31a75 237 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
56a645cc
SH		 238 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
239 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 240 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
242 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 243 }
244
56a645cc 245 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
977bdf06 246
5afa0a9c 247 break;
248
249 case PCI_D3hot:
250 case PCI_D3cold:
251 /* Turn on phy power saving */
56a645cc 252 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c 253 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
254 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
255 else
256 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
56a645cc 257 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
5afa0a9c 258
259 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
260 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
261 else
262 /* enable bits are inverted */
263 sky2_write8(hw, B2_Y2_CLK_GATE,
264 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
265 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
266 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
267
268 /* switch power to VAUX */
269 if (vaux && state != PCI_D3cold)
270 sky2_write8(hw, B0_POWER_CTRL,
271 (PC_VAUX_ENA | PC_VCC_ENA |
272 PC_VAUX_ON | PC_VCC_OFF));
273 break;
274 default:
275 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c 276 }
277
56a645cc 278 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 279 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c 280}
281
cd28ab6a
SH		 282static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
283{
284 u16 reg;
285
286 /* disable all GMAC IRQ's */
287 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
288 /* disable PHY IRQs */
289 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 290
cd28ab6a
SH		 291 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
292 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
293 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
295
296 reg = gma_read16(hw, port, GM_RX_CTRL);
297 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
298 gma_write16(hw, port, GM_RX_CTRL, reg);
299}
300
301static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
302{
303 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 304 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 305
ed6d32c7 306 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 307 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 308 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
309
310 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 311 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 312 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
313
314 if (hw->chip_id == CHIP_ID_YUKON_EC)
315 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
316 else
317 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
318
319 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
320 }
321
322 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
323 if (hw->copper) {
324 if (hw->chip_id == CHIP_ID_YUKON_FE) {
325 /* enable automatic crossover */
326 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
327 } else {
328 /* disable energy detect */
329 ctrl &= ~PHY_M_PC_EN_DET_MSK;
330
331 /* enable automatic crossover */
332 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
333
334 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 335 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 336 ctrl &= ~PHY_M_PC_DSC_MSK;
337 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
338 }
339 }
340 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
341 } else {
342 /* workaround for deviation #4.88 (CRC errors) */
343 /* disable Automatic Crossover */
344
345 ctrl &= ~PHY_M_PC_MDIX_MSK;
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347
348 if (hw->chip_id == CHIP_ID_YUKON_XL) {
349 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl &= ~PHY_M_MAC_MD_MSK;
353 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
354 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
355
356 /* select page 1 to access Fiber registers */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
358 }
cd28ab6a
SH		 359 }
360
361 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
362 if (sky2->autoneg == AUTONEG_DISABLE)
363 ctrl &= ~PHY_CT_ANE;
364 else
365 ctrl |= PHY_CT_ANE;
366
367 ctrl |= PHY_CT_RESET;
368 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
369
370 ctrl = 0;
371 ct1000 = 0;
372 adv = PHY_AN_CSMA;
373
374 if (sky2->autoneg == AUTONEG_ENABLE) {
375 if (hw->copper) {
376 if (sky2->advertising & ADVERTISED_1000baseT_Full)
377 ct1000 |= PHY_M_1000C_AFD;
378 if (sky2->advertising & ADVERTISED_1000baseT_Half)
379 ct1000 |= PHY_M_1000C_AHD;
380 if (sky2->advertising & ADVERTISED_100baseT_Full)
381 adv |= PHY_M_AN_100_FD;
382 if (sky2->advertising & ADVERTISED_100baseT_Half)
383 adv |= PHY_M_AN_100_HD;
384 if (sky2->advertising & ADVERTISED_10baseT_Full)
385 adv |= PHY_M_AN_10_FD;
386 if (sky2->advertising & ADVERTISED_10baseT_Half)
387 adv |= PHY_M_AN_10_HD;
793b883e 388 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 389 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
390
391 /* Set Flow-control capabilities */
392 if (sky2->tx_pause && sky2->rx_pause)
793b883e 393 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 394 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 395 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 396 else if (!sky2->rx_pause && sky2->tx_pause)
397 adv |= PHY_AN_PAUSE_ASYM; /* local */
398
399 /* Restart Auto-negotiation */
400 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
401 } else {
402 /* forced speed/duplex settings */
403 ct1000 = PHY_M_1000C_MSE;
404
405 if (sky2->duplex == DUPLEX_FULL)
406 ctrl |= PHY_CT_DUP_MD;
407
408 switch (sky2->speed) {
409 case SPEED_1000:
410 ctrl |= PHY_CT_SP1000;
411 break;
412 case SPEED_100:
413 ctrl |= PHY_CT_SP100;
414 break;
415 }
416
417 ctrl |= PHY_CT_RESET;
418 }
419
420 if (hw->chip_id != CHIP_ID_YUKON_FE)
421 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
422
423 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
424 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
425
426 /* Setup Phy LED's */
427 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
428 ledover = 0;
429
430 switch (hw->chip_id) {
431 case CHIP_ID_YUKON_FE:
432 /* on 88E3082 these bits are at 11..9 (shifted left) */
433 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
434
435 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
436
437 /* delete ACT LED control bits */
438 ctrl &= ~PHY_M_FELP_LED1_MSK;
439 /* change ACT LED control to blink mode */
440 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
441 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
442 break;
443
444 case CHIP_ID_YUKON_XL:
793b883e 445 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 446
447 /* select page 3 to access LED control register */
448 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
449
450 /* set LED Function Control register */
ed6d32c7
SH		 451 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
452 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
453 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
454 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
455 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 456
457 /* set Polarity Control register */
458 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 459 (PHY_M_POLC_LS1_P_MIX(4) |
460 PHY_M_POLC_IS0_P_MIX(4) |
461 PHY_M_POLC_LOS_CTRL(2) |
462 PHY_M_POLC_INIT_CTRL(2) |
463 PHY_M_POLC_STA1_CTRL(2) |
464 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 465
466 /* restore page register */
793b883e 467 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 468 break;
ed6d32c7
SH		 469 case CHIP_ID_YUKON_EC_U:
470 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
471
472 /* select page 3 to access LED control register */
473 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
474
475 /* set LED Function Control register */
476 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
477 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
478 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
479 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
480 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
481
482 /* set Blink Rate in LED Timer Control Register */
483 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
484 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
485 /* restore page register */
486 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
487 break;
cd28ab6a
SH		 488
489 default:
490 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
491 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
492 /* turn off the Rx LED (LED_RX) */
493 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
494 }
495
ed6d32c7 496 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 497 /* apply fixes in PHY AFE */
ed6d32c7
SH		 498 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
499 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
500
977bdf06 501 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 502 gm_phy_write(hw, port, 0x18, 0xaa99);
503 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 504
977bdf06 505 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 506 gm_phy_write(hw, port, 0x18, 0xa204);
507 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 508
509 /* set page register to 0 */
ed6d32c7 510 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 511 } else {
512 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 513
977bdf06
SH		 514 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
515 /* turn on 100 Mbps LED (LED_LINK100) */
516 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
517 }
cd28ab6a 518
977bdf06
SH		 519 if (ledover)
520 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
521
522 }
d571b694 523 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 524 if (sky2->autoneg == AUTONEG_ENABLE)
525 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
526 else
527 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
528}
529
1b537565
SH		 530/* Force a renegotiation */
531static void sky2_phy_reinit(struct sky2_port *sky2)
532{
e07b1aa8 533 spin_lock_bh(&sky2->phy_lock);
1b537565 534 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 535 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 536}
537
cd28ab6a
SH		 538static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
539{
540 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
541 u16 reg;
542 int i;
543 const u8 *addr = hw->dev[port]->dev_addr;
544
42eeea01 545 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
546 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 547
548 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
549
793b883e 550 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 551 /* WA DEV_472 -- looks like crossed wires on port 2 */
552 /* clear GMAC 1 Control reset */
553 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
554 do {
555 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
556 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
557 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
558 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
559 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
560 }
561
cd28ab6a
SH		 562 if (sky2->autoneg == AUTONEG_DISABLE) {
563 reg = gma_read16(hw, port, GM_GP_CTRL);
564 reg |= GM_GPCR_AU_ALL_DIS;
565 gma_write16(hw, port, GM_GP_CTRL, reg);
566 gma_read16(hw, port, GM_GP_CTRL);
567
cd28ab6a
SH		 568 switch (sky2->speed) {
569 case SPEED_1000:
6f4c56b2 570 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 571 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 572 break;
cd28ab6a 573 case SPEED_100:
6f4c56b2 574 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 575 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 576 break;
577 case SPEED_10:
578 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
579 break;
cd28ab6a
SH		 580 }
581
582 if (sky2->duplex == DUPLEX_FULL)
583 reg |= GM_GPCR_DUP_FULL;
ed6d32c7
SH		 584
585 /* turn off pause in 10/100mbps half duplex */
586 else if (sky2->speed != SPEED_1000 &&
587 hw->chip_id != CHIP_ID_YUKON_EC_U)
588 sky2->tx_pause = sky2->rx_pause = 0;
cd28ab6a
SH		 589 } else
590 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
591
592 if (!sky2->tx_pause && !sky2->rx_pause) {
593 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 594 reg |=
595 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
596 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 597 /* disable Rx flow-control */
598 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
599 }
600
601 gma_write16(hw, port, GM_GP_CTRL, reg);
602
793b883e 603 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 604
e07b1aa8 605 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 606 sky2_phy_init(hw, port);
e07b1aa8 607 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 608
609 /* MIB clear */
610 reg = gma_read16(hw, port, GM_PHY_ADDR);
611 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
612
43f2f104
SH		 613 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
614 gma_read16(hw, port, i);
cd28ab6a
SH		 615 gma_write16(hw, port, GM_PHY_ADDR, reg);
616
617 /* transmit control */
618 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
619
620 /* receive control reg: unicast + multicast + no FCS */
621 gma_write16(hw, port, GM_RX_CTRL,
793b883e 622 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 623
624 /* transmit flow control */
625 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
626
627 /* transmit parameter */
628 gma_write16(hw, port, GM_TX_PARAM,
629 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
630 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
631 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
632 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
633
634 /* serial mode register */
635 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 636 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 637
6b1a3aef 638 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 639 reg |= GM_SMOD_JUMBO_ENA;
640
641 gma_write16(hw, port, GM_SERIAL_MODE, reg);
642
cd28ab6a
SH		 643 /* virtual address for data */
644 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
645
793b883e
SH		 646 /* physical address: used for pause frames */
647 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
648
649 /* ignore counter overflows */
cd28ab6a
SH		 650 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
651 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
652 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
653
654 /* Configure Rx MAC FIFO */
655 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 656 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
657 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 658
d571b694 659 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 660 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 661
793b883e
SH		 662 /* Set threshold to 0xa (64 bytes)
663 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 664 */
665 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
666
667 /* Configure Tx MAC FIFO */
668 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
669 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 670
671 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
672 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
673 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
674 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
675 /* set Tx GMAC FIFO Almost Empty Threshold */
676 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
677 /* Disable Store & Forward mode for TX */
678 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
679 }
680 }
681
cd28ab6a
SH		 682}
683
1c28f6ba
SH		 684/* Assign Ram Buffer allocation.
685 * start and end are in units of 4k bytes
686 * ram registers are in units of 64bit words
687 */
688static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 689{
1c28f6ba 690 u32 start, end;
cd28ab6a 691
1c28f6ba
SH		 692 start = startk * 4096/8;
693 end = (endk * 4096/8) - 1;
793b883e 694
cd28ab6a
SH		 695 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
696 sky2_write32(hw, RB_ADDR(q, RB_START), start);
697 sky2_write32(hw, RB_ADDR(q, RB_END), end);
698 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
699 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
700
701 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 702 u32 space = (endk - startk) * 4096/8;
703 u32 tp = space - space/4;
793b883e 704
1c28f6ba
SH		 705 /* On receive queue's set the thresholds
706 * give receiver priority when > 3/4 full
707 * send pause when down to 2K
708 */
709 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
710 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 711
1c28f6ba
SH		 712 tp = space - 2048/8;
713 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
714 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 715 } else {
716 /* Enable store & forward on Tx queue's because
717 * Tx FIFO is only 1K on Yukon
718 */
719 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
720 }
721
722 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 723 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 724}
725
cd28ab6a 726/* Setup Bus Memory Interface */
af4ed7e6 727static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 728{
729 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
730 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
731 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 732 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 733}
734
cd28ab6a
SH		 735/* Setup prefetch unit registers. This is the interface between
736 * hardware and driver list elements
737 */
8cc048e3 738static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 739 u64 addr, u32 last)
740{
cd28ab6a
SH		 741 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
742 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
743 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
744 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
745 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
746 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 747
748 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 749}
750
793b883e
SH		 751static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
752{
753 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
754
cb5d9547 755 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
793b883e
SH		 756 return le;
757}
cd28ab6a 758
290d4de5
SH		 759/* Update chip's next pointer */
760static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 761{
762c2de2 762 wmb();
290d4de5 763 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
762c2de2 764 mmiowb();
cd28ab6a
SH		 765}
766
793b883e 767
cd28ab6a
SH		 768static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
769{
770 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 771 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
cd28ab6a
SH		 772 return le;
773}
774
a018e330 775/* Return high part of DMA address (could be 32 or 64 bit) */
776static inline u32 high32(dma_addr_t a)
777{
a036119f 778 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 779}
780
793b883e 781/* Build description to hardware about buffer */
28bd181a 782static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 783{
784 struct sky2_rx_le *le;
734d1868
SH		 785 u32 hi = high32(map);
786 u16 len = sky2->rx_bufsize;
cd28ab6a 787
793b883e 788 if (sky2->rx_addr64 != hi) {
cd28ab6a 789 le = sky2_next_rx(sky2);
793b883e 790 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 791 le->ctrl = 0;
792 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 793 sky2->rx_addr64 = high32(map + len);
cd28ab6a 794 }
793b883e 795
cd28ab6a 796 le = sky2_next_rx(sky2);
734d1868
SH		 797 le->addr = cpu_to_le32((u32) map);
798 le->length = cpu_to_le16(len);
cd28ab6a
SH		 799 le->ctrl = 0;
800 le->opcode = OP_PACKET | HW_OWNER;
801}
802
793b883e 803
cd28ab6a
SH		 804/* Tell chip where to start receive checksum.
805 * Actually has two checksums, but set both same to avoid possible byte
806 * order problems.
807 */
793b883e 808static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 809{
810 struct sky2_rx_le *le;
811
cd28ab6a 812 le = sky2_next_rx(sky2);
793b883e 813 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 814 le->ctrl = 0;
815 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 816
793b883e
SH		 817 sky2_write32(sky2->hw,
818 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
819 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 820
821}
822
6b1a3aef 823/*
824 * The RX Stop command will not work for Yukon-2 if the BMU does not
825 * reach the end of packet and since we can't make sure that we have
826 * incoming data, we must reset the BMU while it is not doing a DMA
827 * transfer. Since it is possible that the RX path is still active,
828 * the RX RAM buffer will be stopped first, so any possible incoming
829 * data will not trigger a DMA. After the RAM buffer is stopped, the
830 * BMU is polled until any DMA in progress is ended and only then it
831 * will be reset.
832 */
833static void sky2_rx_stop(struct sky2_port *sky2)
834{
835 struct sky2_hw *hw = sky2->hw;
836 unsigned rxq = rxqaddr[sky2->port];
837 int i;
838
839 /* disable the RAM Buffer receive queue */
840 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
841
842 for (i = 0; i < 0xffff; i++)
843 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
844 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
845 goto stopped;
846
847 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
848 sky2->netdev->name);
849stopped:
850 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
851
852 /* reset the Rx prefetch unit */
853 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
854}
793b883e 855
d571b694 856/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 857static void sky2_rx_clean(struct sky2_port *sky2)
858{
859 unsigned i;
860
861 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 862 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 863 struct ring_info *re = sky2->rx_ring + i;
864
865 if (re->skb) {
793b883e 866 pci_unmap_single(sky2->hw->pdev,
734d1868 867 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 868 PCI_DMA_FROMDEVICE);
869 kfree_skb(re->skb);
870 re->skb = NULL;
871 }
872 }
873}
874
ef743d33 875/* Basic MII support */
876static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
877{
878 struct mii_ioctl_data *data = if_mii(ifr);
879 struct sky2_port *sky2 = netdev_priv(dev);
880 struct sky2_hw *hw = sky2->hw;
881 int err = -EOPNOTSUPP;
882
883 if (!netif_running(dev))
884 return -ENODEV; /* Phy still in reset */
885
d89e1343 886 switch (cmd) {
ef743d33 887 case SIOCGMIIPHY:
888 data->phy_id = PHY_ADDR_MARV;
889
890 /* fallthru */
891 case SIOCGMIIREG: {
892 u16 val = 0;
91c86df5 893
e07b1aa8 894 spin_lock_bh(&sky2->phy_lock);
ef743d33 895 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 896 spin_unlock_bh(&sky2->phy_lock);
91c86df5 897
ef743d33 898 data->val_out = val;
899 break;
900 }
901
902 case SIOCSMIIREG:
903 if (!capable(CAP_NET_ADMIN))
904 return -EPERM;
905
e07b1aa8 906 spin_lock_bh(&sky2->phy_lock);
ef743d33 907 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
908 data->val_in);
e07b1aa8 909 spin_unlock_bh(&sky2->phy_lock);
ef743d33 910 break;
911 }
912 return err;
913}
914
d1f13708 915#ifdef SKY2_VLAN_TAG_USED
916static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
917{
918 struct sky2_port *sky2 = netdev_priv(dev);
919 struct sky2_hw *hw = sky2->hw;
920 u16 port = sky2->port;
d1f13708 921
302d1252 922 spin_lock_bh(&sky2->tx_lock);
d1f13708 923
924 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
925 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
926 sky2->vlgrp = grp;
927
302d1252 928 spin_unlock_bh(&sky2->tx_lock);
d1f13708 929}
930
931static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
932{
933 struct sky2_port *sky2 = netdev_priv(dev);
934 struct sky2_hw *hw = sky2->hw;
935 u16 port = sky2->port;
d1f13708 936
302d1252 937 spin_lock_bh(&sky2->tx_lock);
d1f13708 938
939 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
940 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
941 if (sky2->vlgrp)
942 sky2->vlgrp->vlan_devices[vid] = NULL;
943
302d1252 944 spin_unlock_bh(&sky2->tx_lock);
d1f13708 945}
946#endif
947
82788c7a
SH		 948/*
949 * It appears the hardware has a bug in the FIFO logic that
950 * cause it to hang if the FIFO gets overrun and the receive buffer
951 * is not aligned. ALso alloc_skb() won't align properly if slab
952 * debugging is enabled.
953 */
954static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
955{
956 struct sk_buff *skb;
957
958 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
959 if (likely(skb)) {
960 unsigned long p = (unsigned long) skb->data;
4a15d56f 961 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 962 }
963
964 return skb;
965}
966
cd28ab6a
SH		 967/*
968 * Allocate and setup receiver buffer pool.
969 * In case of 64 bit dma, there are 2X as many list elements
970 * available as ring entries
971 * and need to reserve one list element so we don't wrap around.
972 */
6b1a3aef 973static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 974{
6b1a3aef 975 struct sky2_hw *hw = sky2->hw;
6b1a3aef 976 unsigned rxq = rxqaddr[sky2->port];
977 int i;
a1433ac4 978 unsigned thresh;
cd28ab6a 979
6b1a3aef 980 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 981 sky2_qset(hw, rxq);
977bdf06
SH		 982
983 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
984 /* MAC Rx RAM Read is controlled by hardware */
985 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
986 }
987
6b1a3aef 988 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
989
990 rx_set_checksum(sky2);
793b883e 991 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 992 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 993
82788c7a 994 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 995 if (!re->skb)
996 goto nomem;
997
6b1a3aef 998 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 999 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1000 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 1001 }
1002
a1433ac4
SH		 1003
1004 /*
1005 * The receiver hangs if it receives frames larger than the
1006 * packet buffer. As a workaround, truncate oversize frames, but
1007 * the register is limited to 9 bits, so if you do frames > 2052
1008 * you better get the MTU right!
1009 */
1010 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1011 if (thresh > 0x1ff)
1012 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1013 else {
1014 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1015 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1016 }
1017
70f1be48 1018
6b1a3aef 1019 /* Tell chip about available buffers */
1020 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1021 return 0;
1022nomem:
1023 sky2_rx_clean(sky2);
1024 return -ENOMEM;
1025}
1026
1027/* Bring up network interface. */
1028static int sky2_up(struct net_device *dev)
1029{
1030 struct sky2_port *sky2 = netdev_priv(dev);
1031 struct sky2_hw *hw = sky2->hw;
1032 unsigned port = sky2->port;
e07b1aa8 1033 u32 ramsize, rxspace, imask;
ee7abb04 1034 int cap, err = -ENOMEM;
843a46f4 1035 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1036
ee7abb04
SH		 1037 /*
1038 * On dual port PCI-X card, there is an problem where status
1039 * can be received out of order due to split transactions
843a46f4 1040 */
ee7abb04
SH		 1041 if (otherdev && netif_running(otherdev) &&
1042 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1043 struct sky2_port *osky2 = netdev_priv(otherdev);
1044 u16 cmd;
1045
1046 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1047 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1048 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1049
1050 sky2->rx_csum = 0;
1051 osky2->rx_csum = 0;
1052 }
843a46f4 1053
cd28ab6a
SH		 1054 if (netif_msg_ifup(sky2))
1055 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1056
1057 /* must be power of 2 */
1058 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1059 TX_RING_SIZE *
1060 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1061 &sky2->tx_le_map);
1062 if (!sky2->tx_le)
1063 goto err_out;
1064
6cdbbdf3 1065 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1066 GFP_KERNEL);
1067 if (!sky2->tx_ring)
1068 goto err_out;
1069 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1070
1071 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1072 &sky2->rx_le_map);
1073 if (!sky2->rx_le)
1074 goto err_out;
1075 memset(sky2->rx_le, 0, RX_LE_BYTES);
1076
6cdbbdf3 1077 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1078 GFP_KERNEL);
1079 if (!sky2->rx_ring)
1080 goto err_out;
1081
1082 sky2_mac_init(hw, port);
1083
1c28f6ba
SH		 1084 /* Determine available ram buffer space (in 4K blocks).
1085 * Note: not sure about the FE setting below yet
1086 */
1087 if (hw->chip_id == CHIP_ID_YUKON_FE)
1088 ramsize = 4;
1089 else
1090 ramsize = sky2_read8(hw, B2_E_0);
1091
1092 /* Give transmitter one third (rounded up) */
1093 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1094
cd28ab6a 1095 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1096 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1097
793b883e
SH		 1098 /* Make sure SyncQ is disabled */
1099 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1100 RB_RST_SET);
1101
af4ed7e6 1102 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1103
977bdf06
SH		 1104 /* Set almost empty threshold */
1105 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1106 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1107
6b1a3aef 1108 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1109 TX_RING_SIZE - 1);
cd28ab6a 1110
6b1a3aef 1111 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1112 if (err)
1113 goto err_out;
1114
cd28ab6a 1115 /* Enable interrupts from phy/mac for port */
e07b1aa8 1116 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1117 imask |= portirq_msk[port];
e07b1aa8
SH		 1118 sky2_write32(hw, B0_IMSK, imask);
1119
cd28ab6a
SH		 1120 return 0;
1121
1122err_out:
1b537565 1123 if (sky2->rx_le) {
cd28ab6a
SH		 1124 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1125 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1126 sky2->rx_le = NULL;
1127 }
1128 if (sky2->tx_le) {
cd28ab6a
SH		 1129 pci_free_consistent(hw->pdev,
1130 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1131 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1132 sky2->tx_le = NULL;
1133 }
1134 kfree(sky2->tx_ring);
1135 kfree(sky2->rx_ring);
cd28ab6a 1136
1b537565
SH		 1137 sky2->tx_ring = NULL;
1138 sky2->rx_ring = NULL;
cd28ab6a
SH		 1139 return err;
1140}
1141
793b883e
SH		 1142/* Modular subtraction in ring */
1143static inline int tx_dist(unsigned tail, unsigned head)
1144{
cb5d9547 1145 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1146}
cd28ab6a 1147
793b883e
SH		 1148/* Number of list elements available for next tx */
1149static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1150{
793b883e 1151 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1152}
1153
793b883e 1154/* Estimate of number of transmit list elements required */
28bd181a 1155static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1156{
793b883e
SH		 1157 unsigned count;
1158
1159 count = sizeof(dma_addr_t) / sizeof(u32);
1160 count += skb_shinfo(skb)->nr_frags * count;
1161
7967168c 1162 if (skb_shinfo(skb)->gso_size)
793b883e
SH		 1163 ++count;
1164
0e3ff6aa 1165 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1166 ++count;
1167
1168 return count;
cd28ab6a
SH		 1169}
1170
793b883e
SH		 1171/*
1172 * Put one packet in ring for transmit.
1173 * A single packet can generate multiple list elements, and
1174 * the number of ring elements will probably be less than the number
1175 * of list elements used.
f2e46561
SH		 1176 *
1177 * No BH disabling for tx_lock here (like tg3)
793b883e 1178 */
cd28ab6a
SH		 1179static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1180{
1181 struct sky2_port *sky2 = netdev_priv(dev);
1182 struct sky2_hw *hw = sky2->hw;
d1f13708 1183 struct sky2_tx_le *le = NULL;
6cdbbdf3 1184 struct tx_ring_info *re;
cd28ab6a 1185 unsigned i, len;
b19666d9 1186 int avail;
cd28ab6a
SH		 1187 dma_addr_t mapping;
1188 u32 addr64;
1189 u16 mss;
1190 u8 ctrl;
1191
302d1252
SH		 1192 /* No BH disabling for tx_lock here. We are running in BH disabled
1193 * context and TX reclaim runs via poll inside of a software
1194 * interrupt, and no related locks in IRQ processing.
1195 */
f2e46561 1196 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1197 return NETDEV_TX_LOCKED;
1198
793b883e 1199 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1200 /* There is a known but harmless race with lockless tx
1201 * and netif_stop_queue.
1202 */
1203 if (!netif_queue_stopped(dev)) {
1204 netif_stop_queue(dev);
3be92a70
SH		 1205 if (net_ratelimit())
1206 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1207 dev->name);
8c463ef7 1208 }
f2e46561 1209 spin_unlock(&sky2->tx_lock);
cd28ab6a 1210
cd28ab6a
SH		 1211 return NETDEV_TX_BUSY;
1212 }
1213
793b883e 1214 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1215 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1216 dev->name, sky2->tx_prod, skb->len);
1217
cd28ab6a
SH		 1218 len = skb_headlen(skb);
1219 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1220 addr64 = high32(mapping);
793b883e
SH		 1221
1222 re = sky2->tx_ring + sky2->tx_prod;
1223
a018e330 1224 /* Send high bits if changed or crosses boundary */
1225 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1226 le = get_tx_le(sky2);
1227 le->tx.addr = cpu_to_le32(addr64);
1228 le->ctrl = 0;
1229 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1230 sky2->tx_addr64 = high32(mapping + len);
793b883e 1231 }
cd28ab6a
SH		 1232
1233 /* Check for TCP Segmentation Offload */
7967168c 1234 mss = skb_shinfo(skb)->gso_size;
793b883e 1235 if (mss != 0) {
cd28ab6a
SH		 1236 /* just drop the packet if non-linear expansion fails */
1237 if (skb_header_cloned(skb) &&
1238 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
15240072 1239 dev_kfree_skb(skb);
793b883e 1240 goto out_unlock;
cd28ab6a
SH		 1241 }
1242
1243 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1244 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1245 mss += ETH_HLEN;
793b883e 1246 }
cd28ab6a 1247
793b883e 1248 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1249 le = get_tx_le(sky2);
1250 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1251 le->tx.tso.rsvd = 0;
cd28ab6a 1252 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1253 le->ctrl = 0;
793b883e 1254 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1255 }
1256
cd28ab6a 1257 ctrl = 0;
d1f13708 1258#ifdef SKY2_VLAN_TAG_USED
1259 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1260 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1261 if (!le) {
1262 le = get_tx_le(sky2);
1263 le->tx.addr = 0;
1264 le->opcode = OP_VLAN|HW_OWNER;
1265 le->ctrl = 0;
1266 } else
1267 le->opcode |= OP_VLAN;
1268 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1269 ctrl |= INS_VLAN;
1270 }
1271#endif
1272
1273 /* Handle TCP checksum offload */
cd28ab6a 1274 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1275 u16 hdr = skb->h.raw - skb->data;
1276 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1277
1278 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1279 if (skb->nh.iph->protocol == IPPROTO_UDP)
1280 ctrl |= UDPTCP;
1281
1282 le = get_tx_le(sky2);
1283 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1284 le->tx.csum.offset = cpu_to_le16(offset);
1285 le->length = 0; /* initial checksum value */
cd28ab6a 1286 le->ctrl = 1; /* one packet */
793b883e 1287 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1288 }
1289
1290 le = get_tx_le(sky2);
1291 le->tx.addr = cpu_to_le32((u32) mapping);
1292 le->length = cpu_to_le16(len);
1293 le->ctrl = ctrl;
793b883e 1294 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1295
793b883e 1296 /* Record the transmit mapping info */
cd28ab6a 1297 re->skb = skb;
6cdbbdf3 1298 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1299
1300 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1301 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1302 struct tx_ring_info *fre;
cd28ab6a
SH		 1303
1304 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1305 frag->size, PCI_DMA_TODEVICE);
a036119f 1306 addr64 = high32(mapping);
793b883e
SH		 1307 if (addr64 != sky2->tx_addr64) {
1308 le = get_tx_le(sky2);
1309 le->tx.addr = cpu_to_le32(addr64);
1310 le->ctrl = 0;
1311 le->opcode = OP_ADDR64 | HW_OWNER;
1312 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1313 }
1314
1315 le = get_tx_le(sky2);
1316 le->tx.addr = cpu_to_le32((u32) mapping);
1317 le->length = cpu_to_le16(frag->size);
1318 le->ctrl = ctrl;
793b883e 1319 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1320
793b883e 1321 fre = sky2->tx_ring
cb5d9547 1322 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
6cdbbdf3 1323 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1324 }
6cdbbdf3 1325
793b883e 1326 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1327 le->ctrl |= EOP;
1328
b19666d9
SH		 1329 avail = tx_avail(sky2);
1330 if (mss != 0 || avail < TX_MIN_PENDING) {
1331 le->ctrl |= FRC_STAT;
1332 if (avail <= MAX_SKB_TX_LE)
1333 netif_stop_queue(dev);
1334 }
1335
290d4de5 1336 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1337
793b883e 1338out_unlock:
f2e46561 1339 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1340
1341 dev->trans_start = jiffies;
1342 return NETDEV_TX_OK;
1343}
1344
cd28ab6a 1345/*
793b883e
SH		 1346 * Free ring elements from starting at tx_cons until "done"
1347 *
1348 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1349 * buffers; these are deferred until completion.
cd28ab6a 1350 */
d11c13e7 1351static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1352{
d11c13e7 1353 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1354 struct pci_dev *pdev = sky2->hw->pdev;
1355 u16 nxt, put;
793b883e 1356 unsigned i;
cd28ab6a 1357
0e3ff6aa 1358 BUG_ON(done >= TX_RING_SIZE);
2224795d 1359
d11c13e7 1360 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1361 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1362 dev->name, done);
cd28ab6a 1363
af2a58ac
SH		 1364 for (put = sky2->tx_cons; put != done; put = nxt) {
1365 struct tx_ring_info *re = sky2->tx_ring + put;
1366 struct sk_buff *skb = re->skb;
cd28ab6a 1367
d89e1343 1368 nxt = re->idx;
af2a58ac 1369 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1370 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1371
793b883e 1372 /* Check for partial status */
af2a58ac
SH		 1373 if (tx_dist(put, done) < tx_dist(put, nxt))
1374 break;
793b883e
SH		 1375
1376 skb = re->skb;
af2a58ac 1377 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1378 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1379
1380 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1381 struct tx_ring_info *fre;
cb5d9547 1382 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
af2a58ac 1383 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1384 skb_shinfo(skb)->frags[i].size,
734d1868 1385 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1386 }
1387
15240072 1388 dev_kfree_skb(skb);
793b883e 1389 }
793b883e 1390
af2a58ac 1391 sky2->tx_cons = put;
8f24664d 1392 if (tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a 1393 netif_wake_queue(dev);
cd28ab6a
SH		 1394}
1395
1396/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1397static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1398{
302d1252 1399 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1400 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1401 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1402}
1403
1404/* Network shutdown */
1405static int sky2_down(struct net_device *dev)
1406{
1407 struct sky2_port *sky2 = netdev_priv(dev);
1408 struct sky2_hw *hw = sky2->hw;
1409 unsigned port = sky2->port;
1410 u16 ctrl;
e07b1aa8 1411 u32 imask;
cd28ab6a 1412
1b537565
SH		 1413 /* Never really got started! */
1414 if (!sky2->tx_le)
1415 return 0;
1416
cd28ab6a
SH		 1417 if (netif_msg_ifdown(sky2))
1418 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1419
018d1c66 1420 /* Stop more packets from being queued */
cd28ab6a
SH		 1421 netif_stop_queue(dev);
1422
793b883e
SH		 1423 sky2_phy_reset(hw, port);
1424
cd28ab6a
SH		 1425 /* Stop transmitter */
1426 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1427 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1428
1429 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1430 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1431
1432 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1433 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1434 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1435
1436 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1437
1438 /* Workaround shared GMAC reset */
793b883e
SH		 1439 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1440 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1441 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1442
1443 /* Disable Force Sync bit and Enable Alloc bit */
1444 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1445 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1446
1447 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1448 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1449 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1450
1451 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1452 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1453 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1454
1455 /* Reset the Tx prefetch units */
1456 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1457 PREF_UNIT_RST_SET);
1458
1459 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1460
6b1a3aef 1461 sky2_rx_stop(sky2);
cd28ab6a
SH		 1462
1463 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1464 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1465
e07b1aa8
SH		 1466 /* Disable port IRQ */
1467 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1468 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1469 sky2_write32(hw, B0_IMSK, imask);
1470
d571b694 1471 /* turn off LED's */
cd28ab6a
SH		 1472 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1473
018d1c66 1474 synchronize_irq(hw->pdev->irq);
1475
cd28ab6a
SH		 1476 sky2_tx_clean(sky2);
1477 sky2_rx_clean(sky2);
1478
1479 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1480 sky2->rx_le, sky2->rx_le_map);
1481 kfree(sky2->rx_ring);
1482
1483 pci_free_consistent(hw->pdev,
1484 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1485 sky2->tx_le, sky2->tx_le_map);
1486 kfree(sky2->tx_ring);
1487
1b537565
SH		 1488 sky2->tx_le = NULL;
1489 sky2->rx_le = NULL;
1490
1491 sky2->rx_ring = NULL;
1492 sky2->tx_ring = NULL;
1493
cd28ab6a
SH		 1494 return 0;
1495}
1496
1497static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1498{
793b883e
SH		 1499 if (!hw->copper)
1500 return SPEED_1000;
1501
cd28ab6a
SH		 1502 if (hw->chip_id == CHIP_ID_YUKON_FE)
1503 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1504
1505 switch (aux & PHY_M_PS_SPEED_MSK) {
1506 case PHY_M_PS_SPEED_1000:
1507 return SPEED_1000;
1508 case PHY_M_PS_SPEED_100:
1509 return SPEED_100;
1510 default:
1511 return SPEED_10;
1512 }
1513}
1514
1515static void sky2_link_up(struct sky2_port *sky2)
1516{
1517 struct sky2_hw *hw = sky2->hw;
1518 unsigned port = sky2->port;
1519 u16 reg;
1520
1521 /* Enable Transmit FIFO Underrun */
793b883e 1522 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1523
1524 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1525 if (sky2->autoneg == AUTONEG_DISABLE) {
1526 reg |= GM_GPCR_AU_ALL_DIS;
1527
1528 /* Is write/read necessary? Copied from sky2_mac_init */
1529 gma_write16(hw, port, GM_GP_CTRL, reg);
1530 gma_read16(hw, port, GM_GP_CTRL);
1531
1532 switch (sky2->speed) {
1533 case SPEED_1000:
1534 reg &= ~GM_GPCR_SPEED_100;
1535 reg |= GM_GPCR_SPEED_1000;
1536 break;
1537 case SPEED_100:
1538 reg &= ~GM_GPCR_SPEED_1000;
1539 reg |= GM_GPCR_SPEED_100;
1540 break;
1541 case SPEED_10:
1542 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1543 break;
1544 }
1545 } else
1546 reg &= ~GM_GPCR_AU_ALL_DIS;
1547
cd28ab6a
SH		 1548 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1549 reg |= GM_GPCR_DUP_FULL;
1550
cd28ab6a
SH		 1551 /* enable Rx/Tx */
1552 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1553 gma_write16(hw, port, GM_GP_CTRL, reg);
1554 gma_read16(hw, port, GM_GP_CTRL);
1555
1556 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1557
1558 netif_carrier_on(sky2->netdev);
1559 netif_wake_queue(sky2->netdev);
1560
1561 /* Turn on link LED */
793b883e 1562 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1563 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1564
ed6d32c7 1565 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1566 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1567 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1568
1569 switch(sky2->speed) {
1570 case SPEED_10:
1571 led |= PHY_M_LEDC_INIT_CTRL(7);
1572 break;
1573
1574 case SPEED_100:
1575 led |= PHY_M_LEDC_STA1_CTRL(7);
1576 break;
1577
1578 case SPEED_1000:
1579 led |= PHY_M_LEDC_STA0_CTRL(7);
1580 break;
1581 }
793b883e
SH		 1582
1583 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1584 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1585 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1586 }
1587
cd28ab6a
SH		 1588 if (netif_msg_link(sky2))
1589 printk(KERN_INFO PFX
d571b694 1590 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1591 sky2->netdev->name, sky2->speed,
1592 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1593 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1594 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1595}
1596
1597static void sky2_link_down(struct sky2_port *sky2)
1598{
1599 struct sky2_hw *hw = sky2->hw;
1600 unsigned port = sky2->port;
1601 u16 reg;
1602
1603 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1604
1605 reg = gma_read16(hw, port, GM_GP_CTRL);
1606 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1607 gma_write16(hw, port, GM_GP_CTRL, reg);
1608 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1609
1610 if (sky2->rx_pause && !sky2->tx_pause) {
1611 /* restore Asymmetric Pause bit */
1612 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1613 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1614 | PHY_M_AN_ASP);
cd28ab6a
SH		 1615 }
1616
cd28ab6a
SH		 1617 netif_carrier_off(sky2->netdev);
1618 netif_stop_queue(sky2->netdev);
1619
1620 /* Turn on link LED */
1621 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1622
1623 if (netif_msg_link(sky2))
1624 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1625 sky2_phy_init(hw, port);
1626}
1627
793b883e
SH		 1628static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1629{
1630 struct sky2_hw *hw = sky2->hw;
1631 unsigned port = sky2->port;
1632 u16 lpa;
1633
1634 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1635
1636 if (lpa & PHY_M_AN_RF) {
1637 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1638 return -1;
1639 }
1640
1641 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1642 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1643 printk(KERN_ERR PFX "%s: master/slave fault",
1644 sky2->netdev->name);
1645 return -1;
1646 }
1647
1648 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1649 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1650 sky2->netdev->name);
1651 return -1;
1652 }
1653
1654 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1655
1656 sky2->speed = sky2_phy_speed(hw, aux);
1657
1658 /* Pause bits are offset (9..8) */
ed6d32c7 1659 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1660 aux >>= 6;
1661
1662 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1663 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1664
1665 if ((sky2->tx_pause || sky2->rx_pause)
1666 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1667 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1668 else
1669 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1670
1671 return 0;
1672}
cd28ab6a 1673
e07b1aa8
SH		 1674/* Interrupt from PHY */
1675static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1676{
e07b1aa8
SH		 1677 struct net_device *dev = hw->dev[port];
1678 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1679 u16 istatus, phystat;
1680
e07b1aa8
SH		 1681 spin_lock(&sky2->phy_lock);
1682 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1683 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1684
1685 if (!netif_running(dev))
1686 goto out;
cd28ab6a
SH		 1687
1688 if (netif_msg_intr(sky2))
1689 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1690 sky2->netdev->name, istatus, phystat);
1691
1692 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1693 if (sky2_autoneg_done(sky2, phystat) == 0)
1694 sky2_link_up(sky2);
1695 goto out;
1696 }
cd28ab6a 1697
793b883e
SH		 1698 if (istatus & PHY_M_IS_LSP_CHANGE)
1699 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1700
793b883e
SH		 1701 if (istatus & PHY_M_IS_DUP_CHANGE)
1702 sky2->duplex =
1703 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1704
793b883e
SH		 1705 if (istatus & PHY_M_IS_LST_CHANGE) {
1706 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1707 sky2_link_up(sky2);
793b883e
SH		 1708 else
1709 sky2_link_down(sky2);
cd28ab6a 1710 }
793b883e 1711out:
e07b1aa8 1712 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1713}
1714
302d1252
SH		 1715
1716/* Transmit timeout is only called if we are running, carries is up
1717 * and tx queue is full (stopped).
1718 */
cd28ab6a
SH		 1719static void sky2_tx_timeout(struct net_device *dev)
1720{
1721 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1722 struct sky2_hw *hw = sky2->hw;
1723 unsigned txq = txqaddr[sky2->port];
8f24664d 1724 u16 report, done;
cd28ab6a
SH		 1725
1726 if (netif_msg_timer(sky2))
1727 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1728
8f24664d
SH		 1729 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1730 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1731
8f24664d
SH		 1732 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1733 dev->name,
1734 sky2->tx_cons, sky2->tx_prod, report, done);
1735
1736 if (report != done) {
1737 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1738
1739 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1740 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1741 } else if (report != sky2->tx_cons) {
1742 printk(KERN_INFO PFX "status report lost?\n");
1743
1744 spin_lock_bh(&sky2->tx_lock);
1745 sky2_tx_complete(sky2, report);
1746 spin_unlock_bh(&sky2->tx_lock);
1747 } else {
1748 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1749
8f24664d
SH		 1750 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1751 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1752
1753 sky2_tx_clean(sky2);
1754
1755 sky2_qset(hw, txq);
1756 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1757 }
cd28ab6a
SH		 1758}
1759
734d1868 1760
70f1be48
SH		 1761/* Want receive buffer size to be multiple of 64 bits
1762 * and incl room for vlan and truncation
1763 */
734d1868
SH		 1764static inline unsigned sky2_buf_size(int mtu)
1765{
4a15d56f 1766 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1767}
1768
cd28ab6a
SH		 1769static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1770{
6b1a3aef 1771 struct sky2_port *sky2 = netdev_priv(dev);
1772 struct sky2_hw *hw = sky2->hw;
1773 int err;
1774 u16 ctl, mode;
e07b1aa8 1775 u32 imask;
cd28ab6a
SH		 1776
1777 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1778 return -EINVAL;
1779
5a5b1ea0 1780 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1781 return -EINVAL;
1782
6b1a3aef 1783 if (!netif_running(dev)) {
1784 dev->mtu = new_mtu;
1785 return 0;
1786 }
1787
e07b1aa8 1788 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1789 sky2_write32(hw, B0_IMSK, 0);
1790
018d1c66 1791 dev->trans_start = jiffies; /* prevent tx timeout */
1792 netif_stop_queue(dev);
1793 netif_poll_disable(hw->dev[0]);
1794
e07b1aa8
SH		 1795 synchronize_irq(hw->pdev->irq);
1796
6b1a3aef 1797 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1798 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1799 sky2_rx_stop(sky2);
1800 sky2_rx_clean(sky2);
cd28ab6a
SH		 1801
1802 dev->mtu = new_mtu;
734d1868 1803 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef 1804 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1805 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1806
1807 if (dev->mtu > ETH_DATA_LEN)
1808 mode |= GM_SMOD_JUMBO_ENA;
1809
1810 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1811
6b1a3aef 1812 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1813
6b1a3aef 1814 err = sky2_rx_start(sky2);
e07b1aa8 1815 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1816
1b537565
SH		 1817 if (err)
1818 dev_close(dev);
1819 else {
1820 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1821
1822 netif_poll_enable(hw->dev[0]);
1823 netif_wake_queue(dev);
1824 }
1825
cd28ab6a
SH		 1826 return err;
1827}
1828
1829/*
1830 * Receive one packet.
1831 * For small packets or errors, just reuse existing skb.
d571b694 1832 * For larger packets, get new buffer.
cd28ab6a 1833 */
d11c13e7 1834static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1835 u16 length, u32 status)
1836{
cd28ab6a 1837 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1838 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1839
1840 if (unlikely(netif_msg_rx_status(sky2)))
1841 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1842 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1843
793b883e 1844 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1845 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1846
42eeea01 1847 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1848 goto error;
1849
42eeea01 1850 if (!(status & GMR_FS_RX_OK))
1851 goto resubmit;
1852
70f1be48 1853 if (length > sky2->netdev->mtu + ETH_HLEN)
6e15b712
SH		 1854 goto oversize;
1855
bdb5c58e 1856 if (length < copybreak) {
79e57d32
SH		 1857 skb = alloc_skb(length + 2, GFP_ATOMIC);
1858 if (!skb)
793b883e
SH		 1859 goto resubmit;
1860
79e57d32 1861 skb_reserve(skb, 2);
793b883e
SH		 1862 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1863 length, PCI_DMA_FROMDEVICE);
79e57d32 1864 memcpy(skb->data, re->skb->data, length);
d11c13e7 1865 skb->ip_summed = re->skb->ip_summed;
1866 skb->csum = re->skb->csum;
793b883e
SH		 1867 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1868 length, PCI_DMA_FROMDEVICE);
793b883e 1869 } else {
79e57d32
SH		 1870 struct sk_buff *nskb;
1871
82788c7a 1872 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1873 if (!nskb)
1874 goto resubmit;
cd28ab6a 1875
793b883e 1876 skb = re->skb;
79e57d32 1877 re->skb = nskb;
793b883e 1878 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1879 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1880 prefetch(skb->data);
cd28ab6a 1881
793b883e 1882 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1883 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1884 }
cd28ab6a 1885
79e57d32 1886 skb_put(skb, length);
793b883e 1887resubmit:
d11c13e7 1888 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1889 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1890
bea86103 1891 /* Tell receiver about new buffers. */
290d4de5 1892 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
bea86103 1893
cd28ab6a
SH		 1894 return skb;
1895
6e15b712
SH		 1896oversize:
1897 ++sky2->net_stats.rx_over_errors;
1898 goto resubmit;
1899
cd28ab6a 1900error:
6e15b712
SH		 1901 ++sky2->net_stats.rx_errors;
1902
3be92a70 1903 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a
SH		 1904 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1905 sky2->netdev->name, status, length);
793b883e
SH		 1906
1907 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1908 sky2->net_stats.rx_length_errors++;
1909 if (status & GMR_FS_FRAGMENT)
1910 sky2->net_stats.rx_frame_errors++;
1911 if (status & GMR_FS_CRC_ERR)
1912 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1913 if (status & GMR_FS_RX_FF_OV)
1914 sky2->net_stats.rx_fifo_errors++;
79e57d32 1915
793b883e 1916 goto resubmit;
cd28ab6a
SH		 1917}
1918
e07b1aa8
SH		 1919/* Transmit complete */
1920static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1921{
e07b1aa8 1922 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1923
e07b1aa8
SH		 1924 if (netif_running(dev)) {
1925 spin_lock(&sky2->tx_lock);
1926 sky2_tx_complete(sky2, last);
1927 spin_unlock(&sky2->tx_lock);
2224795d 1928 }
cd28ab6a
SH		 1929}
1930
86fba634
SH		 1931/* Is status ring empty or is there more to do? */
1932static inline int sky2_more_work(const struct sky2_hw *hw)
1933{
1934 return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX));
1935}
1936
e07b1aa8
SH		 1937/* Process status response ring */
1938static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1939{
e07b1aa8 1940 int work_done = 0;
e71ebd73 1941 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 1942
af2a58ac 1943 rmb();
bea86103 1944
e71ebd73 1945 while (hw->st_idx != hwidx) {
13210ce5 1946 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1947 struct net_device *dev;
d11c13e7 1948 struct sky2_port *sky2;
cd28ab6a 1949 struct sk_buff *skb;
cd28ab6a
SH		 1950 u32 status;
1951 u16 length;
1952
cb5d9547 1953 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 1954
e71ebd73
SH		 1955 BUG_ON(le->link >= 2);
1956 dev = hw->dev[le->link];
13210ce5 1957
1958 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1959 length = le->length;
1960 status = le->status;
cd28ab6a 1961
e71ebd73 1962 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1963 case OP_RXSTAT:
d11c13e7 1964 skb = sky2_receive(sky2, length, status);
d1f13708 1965 if (!skb)
1966 break;
13210ce5 1967
1968 skb->dev = dev;
1969 skb->protocol = eth_type_trans(skb, dev);
1970 dev->last_rx = jiffies;
1971
d1f13708 1972#ifdef SKY2_VLAN_TAG_USED
1973 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1974 vlan_hwaccel_receive_skb(skb,
1975 sky2->vlgrp,
1976 be16_to_cpu(sky2->rx_tag));
1977 } else
1978#endif
cd28ab6a 1979 netif_receive_skb(skb);
13210ce5 1980
1981 if (++work_done >= to_do)
1982 goto exit_loop;
cd28ab6a
SH		 1983 break;
1984
d1f13708 1985#ifdef SKY2_VLAN_TAG_USED
1986 case OP_RXVLAN:
1987 sky2->rx_tag = length;
1988 break;
1989
1990 case OP_RXCHKSVLAN:
1991 sky2->rx_tag = length;
1992 /* fall through */
1993#endif
cd28ab6a 1994 case OP_RXCHKS:
d11c13e7 1995 skb = sky2->rx_ring[sky2->rx_next].skb;
1996 skb->ip_summed = CHECKSUM_HW;
1997 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1998 break;
1999
2000 case OP_TXINDEXLE:
13b97b74 2001 /* TX index reports status for both ports */
f55925d7
SH		 2002 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2003 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2004 if (hw->dev[1])
2005 sky2_tx_done(hw->dev[1],
2006 ((status >> 24) & 0xff)
2007 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2008 break;
2009
cd28ab6a
SH		 2010 default:
2011 if (net_ratelimit())
793b883e 2012 printk(KERN_WARNING PFX
e71ebd73
SH		 2013 "unknown status opcode 0x%x\n", le->opcode);
2014 goto exit_loop;
cd28ab6a 2015 }
13210ce5 2016 }
cd28ab6a 2017
13210ce5 2018exit_loop:
e07b1aa8 2019 return work_done;
cd28ab6a
SH		 2020}
2021
2022static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2023{
2024 struct net_device *dev = hw->dev[port];
2025
3be92a70
SH		 2026 if (net_ratelimit())
2027 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2028 dev->name, status);
cd28ab6a
SH		 2029
2030 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2031 if (net_ratelimit())
2032 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2033 dev->name);
cd28ab6a
SH		 2034 /* Clear IRQ */
2035 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2036 }
2037
2038 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2039 if (net_ratelimit())
2040 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2041 dev->name);
cd28ab6a
SH		 2042
2043 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2044 }
2045
2046 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2047 if (net_ratelimit())
2048 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2049 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2050 }
2051
2052 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2053 if (net_ratelimit())
2054 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2055 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2056 }
2057
2058 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2059 if (net_ratelimit())
2060 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2061 dev->name);
cd28ab6a
SH		 2062 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2063 }
2064}
2065
2066static void sky2_hw_intr(struct sky2_hw *hw)
2067{
2068 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2069
793b883e 2070 if (status & Y2_IS_TIST_OV)
cd28ab6a 2071 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2072
2073 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2074 u16 pci_err;
2075
56a645cc 2076 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2077 if (net_ratelimit())
2078 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2079 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2080
2081 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2082 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2083 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2084 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2085 }
2086
2087 if (status & Y2_IS_PCI_EXP) {
d571b694 2088 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2089 u32 pex_err;
2090
56a645cc 2091 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2092
3be92a70
SH		 2093 if (net_ratelimit())
2094 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2095 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2096
2097 /* clear the interrupt */
2098 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2099 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2100 0xffffffffUL);
cd28ab6a
SH		 2101 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2102
2103 if (pex_err & PEX_FATAL_ERRORS) {
2104 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2105 hwmsk &= ~Y2_IS_PCI_EXP;
2106 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2107 }
2108 }
2109
2110 if (status & Y2_HWE_L1_MASK)
2111 sky2_hw_error(hw, 0, status);
2112 status >>= 8;
2113 if (status & Y2_HWE_L1_MASK)
2114 sky2_hw_error(hw, 1, status);
2115}
2116
2117static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2118{
2119 struct net_device *dev = hw->dev[port];
2120 struct sky2_port *sky2 = netdev_priv(dev);
2121 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2122
2123 if (netif_msg_intr(sky2))
2124 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2125 dev->name, status);
2126
2127 if (status & GM_IS_RX_FF_OR) {
2128 ++sky2->net_stats.rx_fifo_errors;
2129 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2130 }
2131
2132 if (status & GM_IS_TX_FF_UR) {
2133 ++sky2->net_stats.tx_fifo_errors;
2134 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2135 }
cd28ab6a
SH		 2136}
2137
d257924e
SH		 2138/* This should never happen it is a fatal situation */
2139static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2140 const char *rxtx, u32 mask)
2141{
2142 struct net_device *dev = hw->dev[port];
2143 struct sky2_port *sky2 = netdev_priv(dev);
2144 u32 imask;
2145
2146 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2147 dev ? dev->name : "<not registered>", rxtx);
2148
2149 imask = sky2_read32(hw, B0_IMSK);
2150 imask &= ~mask;
2151 sky2_write32(hw, B0_IMSK, imask);
2152
2153 if (dev) {
2154 spin_lock(&sky2->phy_lock);
2155 sky2_link_down(sky2);
2156 spin_unlock(&sky2->phy_lock);
2157 }
2158}
cd28ab6a 2159
d27ed387
SH		 2160/* If idle then force a fake soft NAPI poll once a second
2161 * to work around cases where sharing an edge triggered interrupt.
2162 */
eb35cf60
SH		 2163static inline void sky2_idle_start(struct sky2_hw *hw)
2164{
2165 if (idle_timeout > 0)
2166 mod_timer(&hw->idle_timer,
2167 jiffies + msecs_to_jiffies(idle_timeout));
2168}
2169
d27ed387
SH		 2170static void sky2_idle(unsigned long arg)
2171{
01bd7564
SH		 2172 struct sky2_hw *hw = (struct sky2_hw *) arg;
2173 struct net_device *dev = hw->dev[0];
d27ed387 2174
d27ed387
SH		 2175 if (__netif_rx_schedule_prep(dev))
2176 __netif_rx_schedule(dev);
01bd7564
SH		 2177
2178 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2179}
2180
2181
e07b1aa8 2182static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2183{
e07b1aa8
SH		 2184 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2185 int work_limit = min(dev0->quota, *budget);
2186 int work_done = 0;
fb2690a9 2187 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2188
d374c1c1 2189 if (!~status)
26ec43f1 2190 goto out;
d374c1c1 2191
1e5f1283
SH		 2192 if (status & Y2_IS_HW_ERR)
2193 sky2_hw_intr(hw);
d257924e 2194
1e5f1283
SH		 2195 if (status & Y2_IS_IRQ_PHY1)
2196 sky2_phy_intr(hw, 0);
cd28ab6a 2197
1e5f1283
SH		 2198 if (status & Y2_IS_IRQ_PHY2)
2199 sky2_phy_intr(hw, 1);
cd28ab6a 2200
1e5f1283
SH		 2201 if (status & Y2_IS_IRQ_MAC1)
2202 sky2_mac_intr(hw, 0);
cd28ab6a 2203
1e5f1283
SH		 2204 if (status & Y2_IS_IRQ_MAC2)
2205 sky2_mac_intr(hw, 1);
cd28ab6a 2206
1e5f1283
SH		 2207 if (status & Y2_IS_CHK_RX1)
2208 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2209
1e5f1283
SH		 2210 if (status & Y2_IS_CHK_RX2)
2211 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2212
1e5f1283
SH		 2213 if (status & Y2_IS_CHK_TXA1)
2214 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2215
1e5f1283
SH		 2216 if (status & Y2_IS_CHK_TXA2)
2217 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2218
1e5f1283
SH		 2219 work_done = sky2_status_intr(hw, work_limit);
2220 *budget -= work_done;
2221 dev0->quota -= work_done;
e07b1aa8 2222
86fba634
SH		 2223 if (status & Y2_IS_STAT_BMU)
2224 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2225
2226 if (sky2_more_work(hw))
1e5f1283 2227 return 1;
26ec43f1 2228out:
d3240312 2229 netif_rx_complete(dev0);
e07b1aa8 2230
86fba634 2231 sky2_read32(hw, B0_Y2_SP_LISR);
e07b1aa8
SH		 2232 return 0;
2233}
2234
2235static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2236{
2237 struct sky2_hw *hw = dev_id;
2238 struct net_device *dev0 = hw->dev[0];
2239 u32 status;
2240
2241 /* Reading this mask interrupts as side effect */
2242 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2243 if (status == 0 || status == ~0)
2244 return IRQ_NONE;
793b883e 2245
e07b1aa8
SH		 2246 prefetch(&hw->st_le[hw->st_idx]);
2247 if (likely(__netif_rx_schedule_prep(dev0)))
2248 __netif_rx_schedule(dev0);
793b883e 2249
cd28ab6a
SH		 2250 return IRQ_HANDLED;
2251}
2252
2253#ifdef CONFIG_NET_POLL_CONTROLLER
2254static void sky2_netpoll(struct net_device *dev)
2255{
2256 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2257 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2258
88d11360
SH		 2259 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2260 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2261}
2262#endif
2263
2264/* Chip internal frequency for clock calculations */
fb17358f 2265static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2266{
793b883e 2267 switch (hw->chip_id) {
cd28ab6a 2268 case CHIP_ID_YUKON_EC:
5a5b1ea0 2269 case CHIP_ID_YUKON_EC_U:
fb17358f 2270 return 125; /* 125 Mhz */
cd28ab6a 2271 case CHIP_ID_YUKON_FE:
fb17358f 2272 return 100; /* 100 Mhz */
793b883e 2273 default: /* YUKON_XL */
fb17358f 2274 return 156; /* 156 Mhz */
cd28ab6a
SH		 2275 }
2276}
2277
fb17358f 2278static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2279{
fb17358f 2280 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2281}
2282
fb17358f 2283static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2284{
fb17358f 2285 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2286}
2287
fb17358f 2288
98712e5e 2289static int __devinit sky2_reset(struct sky2_hw *hw)
cd28ab6a 2290{
cd28ab6a
SH		 2291 u16 status;
2292 u8 t8, pmd_type;
56a645cc 2293 int i;
cd28ab6a 2294
cd28ab6a 2295 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2296
cd28ab6a
SH		 2297 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2298 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2299 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2300 pci_name(hw->pdev), hw->chip_id);
2301 return -EOPNOTSUPP;
2302 }
2303
290d4de5
SH		 2304 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2305
2306 /* This rev is really old, and requires untested workarounds */
2307 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2308 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2309 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2310 hw->chip_id, hw->chip_rev);
2311 return -EOPNOTSUPP;
2312 }
2313
cd28ab6a
SH		 2314 /* disable ASF */
2315 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2316 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2317 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2318 }
2319
2320 /* do a SW reset */
2321 sky2_write8(hw, B0_CTST, CS_RST_SET);
2322 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2323
2324 /* clear PCI errors, if any */
56a645cc 2325 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2326
cd28ab6a 2327 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2328 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2329
cd28ab6a
SH		 2330
2331 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2332
2333 /* clear any PEX errors */
d89e1343 2334 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2335 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2336
cd28ab6a
SH		 2337
2338 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2339 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2340
2341 hw->ports = 1;
2342 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2343 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2344 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2345 ++hw->ports;
2346 }
cd28ab6a 2347
5afa0a9c 2348 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2349
2350 for (i = 0; i < hw->ports; i++) {
2351 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2352 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2353 }
2354
2355 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2356
793b883e
SH		 2357 /* Clear I2C IRQ noise */
2358 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2359
2360 /* turn off hardware timer (unused) */
2361 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2362 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2363
cd28ab6a
SH		 2364 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2365
69634ee7
SH		 2366 /* Turn off descriptor polling */
2367 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2368
2369 /* Turn off receive timestamp */
2370 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2371 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2372
2373 /* enable the Tx Arbiters */
2374 for (i = 0; i < hw->ports; i++)
2375 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2376
2377 /* Initialize ram interface */
2378 for (i = 0; i < hw->ports; i++) {
793b883e 2379 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2380
2381 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2382 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2383 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2384 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2385 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2386 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2387 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2388 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2389 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2390 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2391 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2392 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2393 }
2394
cd28ab6a
SH		 2395 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2396
cd28ab6a
SH		 2397 for (i = 0; i < hw->ports; i++)
2398 sky2_phy_reset(hw, i);
cd28ab6a 2399
cd28ab6a
SH		 2400 memset(hw->st_le, 0, STATUS_LE_BYTES);
2401 hw->st_idx = 0;
2402
2403 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2404 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2405
2406 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2407 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2408
2409 /* Set the list last index */
793b883e 2410 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2411
290d4de5
SH		 2412 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2413 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2414
290d4de5
SH		 2415 /* set Status-FIFO ISR watermark */
2416 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2417 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2418 else
2419 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2420
290d4de5 2421 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2422 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2423 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2424
793b883e 2425 /* enable status unit */
cd28ab6a
SH		 2426 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2427
2428 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2429 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2430 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2431
2432 return 0;
2433}
2434
28bd181a 2435static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2436{
2437 u32 modes;
2438 if (hw->copper) {
793b883e
SH		 2439 modes = SUPPORTED_10baseT_Half
2440 | SUPPORTED_10baseT_Full
2441 | SUPPORTED_100baseT_Half
2442 | SUPPORTED_100baseT_Full
2443 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2444
2445 if (hw->chip_id != CHIP_ID_YUKON_FE)
2446 modes |= SUPPORTED_1000baseT_Half
793b883e 2447 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2448 } else
2449 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2450 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2451 return modes;
2452}
2453
793b883e 2454static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2455{
2456 struct sky2_port *sky2 = netdev_priv(dev);
2457 struct sky2_hw *hw = sky2->hw;
2458
2459 ecmd->transceiver = XCVR_INTERNAL;
2460 ecmd->supported = sky2_supported_modes(hw);
2461 ecmd->phy_address = PHY_ADDR_MARV;
2462 if (hw->copper) {
2463 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2464 | SUPPORTED_10baseT_Full
2465 | SUPPORTED_100baseT_Half
2466 | SUPPORTED_100baseT_Full
2467 | SUPPORTED_1000baseT_Half
2468 | SUPPORTED_1000baseT_Full
2469 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2470 ecmd->port = PORT_TP;
2471 } else
2472 ecmd->port = PORT_FIBRE;
2473
2474 ecmd->advertising = sky2->advertising;
2475 ecmd->autoneg = sky2->autoneg;
2476 ecmd->speed = sky2->speed;
2477 ecmd->duplex = sky2->duplex;
2478 return 0;
2479}
2480
2481static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2482{
2483 struct sky2_port *sky2 = netdev_priv(dev);
2484 const struct sky2_hw *hw = sky2->hw;
2485 u32 supported = sky2_supported_modes(hw);
2486
2487 if (ecmd->autoneg == AUTONEG_ENABLE) {
2488 ecmd->advertising = supported;
2489 sky2->duplex = -1;
2490 sky2->speed = -1;
2491 } else {
2492 u32 setting;
2493
793b883e 2494 switch (ecmd->speed) {
cd28ab6a
SH		 2495 case SPEED_1000:
2496 if (ecmd->duplex == DUPLEX_FULL)
2497 setting = SUPPORTED_1000baseT_Full;
2498 else if (ecmd->duplex == DUPLEX_HALF)
2499 setting = SUPPORTED_1000baseT_Half;
2500 else
2501 return -EINVAL;
2502 break;
2503 case SPEED_100:
2504 if (ecmd->duplex == DUPLEX_FULL)
2505 setting = SUPPORTED_100baseT_Full;
2506 else if (ecmd->duplex == DUPLEX_HALF)
2507 setting = SUPPORTED_100baseT_Half;
2508 else
2509 return -EINVAL;
2510 break;
2511
2512 case SPEED_10:
2513 if (ecmd->duplex == DUPLEX_FULL)
2514 setting = SUPPORTED_10baseT_Full;
2515 else if (ecmd->duplex == DUPLEX_HALF)
2516 setting = SUPPORTED_10baseT_Half;
2517 else
2518 return -EINVAL;
2519 break;
2520 default:
2521 return -EINVAL;
2522 }
2523
2524 if ((setting & supported) == 0)
2525 return -EINVAL;
2526
2527 sky2->speed = ecmd->speed;
2528 sky2->duplex = ecmd->duplex;
2529 }
2530
2531 sky2->autoneg = ecmd->autoneg;
2532 sky2->advertising = ecmd->advertising;
2533
1b537565
SH		 2534 if (netif_running(dev))
2535 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2536
2537 return 0;
2538}
2539
2540static void sky2_get_drvinfo(struct net_device *dev,
2541 struct ethtool_drvinfo *info)
2542{
2543 struct sky2_port *sky2 = netdev_priv(dev);
2544
2545 strcpy(info->driver, DRV_NAME);
2546 strcpy(info->version, DRV_VERSION);
2547 strcpy(info->fw_version, "N/A");
2548 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2549}
2550
2551static const struct sky2_stat {
793b883e
SH		 2552 char name[ETH_GSTRING_LEN];
2553 u16 offset;
cd28ab6a
SH		 2554} sky2_stats[] = {
2555 { "tx_bytes", GM_TXO_OK_HI },
2556 { "rx_bytes", GM_RXO_OK_HI },
2557 { "tx_broadcast", GM_TXF_BC_OK },
2558 { "rx_broadcast", GM_RXF_BC_OK },
2559 { "tx_multicast", GM_TXF_MC_OK },
2560 { "rx_multicast", GM_RXF_MC_OK },
2561 { "tx_unicast", GM_TXF_UC_OK },
2562 { "rx_unicast", GM_RXF_UC_OK },
2563 { "tx_mac_pause", GM_TXF_MPAUSE },
2564 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2565 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2566 { "late_collision",GM_TXF_LAT_COL },
2567 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2568 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2569 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2570
d2604540 2571 { "rx_short", GM_RXF_SHT },
cd28ab6a 2572 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2573 { "rx_64_byte_packets", GM_RXF_64B },
2574 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2575 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2576 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2577 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2578 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2579 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2580 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2581 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2582 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2583 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2584
2585 { "tx_64_byte_packets", GM_TXF_64B },
2586 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2587 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2588 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2589 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2590 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2591 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2592 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2593};
2594
cd28ab6a
SH		 2595static u32 sky2_get_rx_csum(struct net_device *dev)
2596{
2597 struct sky2_port *sky2 = netdev_priv(dev);
2598
2599 return sky2->rx_csum;
2600}
2601
2602static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2603{
2604 struct sky2_port *sky2 = netdev_priv(dev);
2605
2606 sky2->rx_csum = data;
793b883e 2607
cd28ab6a
SH		 2608 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2609 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2610
2611 return 0;
2612}
2613
2614static u32 sky2_get_msglevel(struct net_device *netdev)
2615{
2616 struct sky2_port *sky2 = netdev_priv(netdev);
2617 return sky2->msg_enable;
2618}
2619
9a7ae0a9
SH		 2620static int sky2_nway_reset(struct net_device *dev)
2621{
2622 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2623
2624 if (sky2->autoneg != AUTONEG_ENABLE)
2625 return -EINVAL;
2626
1b537565 2627 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2628
2629 return 0;
2630}
2631
793b883e 2632static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2633{
2634 struct sky2_hw *hw = sky2->hw;
2635 unsigned port = sky2->port;
2636 int i;
2637
2638 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2639 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2640 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2641 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2642
793b883e 2643 for (i = 2; i < count; i++)
cd28ab6a
SH		 2644 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2645}
2646
cd28ab6a
SH		 2647static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2648{
2649 struct sky2_port *sky2 = netdev_priv(netdev);
2650 sky2->msg_enable = value;
2651}
2652
2653static int sky2_get_stats_count(struct net_device *dev)
2654{
2655 return ARRAY_SIZE(sky2_stats);
2656}
2657
2658static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2659 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2660{
2661 struct sky2_port *sky2 = netdev_priv(dev);
2662
793b883e 2663 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2664}
2665
793b883e 2666static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2667{
2668 int i;
2669
2670 switch (stringset) {
2671 case ETH_SS_STATS:
2672 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2673 memcpy(data + i * ETH_GSTRING_LEN,
2674 sky2_stats[i].name, ETH_GSTRING_LEN);
2675 break;
2676 }
2677}
2678
2679/* Use hardware MIB variables for critical path statistics and
2680 * transmit feedback not reported at interrupt.
2681 * Other errors are accounted for in interrupt handler.
2682 */
2683static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2684{
2685 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2686 u64 data[13];
cd28ab6a 2687
793b883e 2688 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2689
2690 sky2->net_stats.tx_bytes = data[0];
2691 sky2->net_stats.rx_bytes = data[1];
2692 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2693 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2694 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2695 sky2->net_stats.collisions = data[10];
2696 sky2->net_stats.tx_aborted_errors = data[12];
2697
2698 return &sky2->net_stats;
2699}
2700
2701static int sky2_set_mac_address(struct net_device *dev, void *p)
2702{
2703 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2704 struct sky2_hw *hw = sky2->hw;
2705 unsigned port = sky2->port;
2706 const struct sockaddr *addr = p;
cd28ab6a
SH		 2707
2708 if (!is_valid_ether_addr(addr->sa_data))
2709 return -EADDRNOTAVAIL;
2710
cd28ab6a 2711 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2712 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2713 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2714 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2715 dev->dev_addr, ETH_ALEN);
1b537565 2716
a8ab1ec0
SH		 2717 /* virtual address for data */
2718 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2719
2720 /* physical address: used for pause frames */
2721 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2722
2723 return 0;
cd28ab6a
SH		 2724}
2725
2726static void sky2_set_multicast(struct net_device *dev)
2727{
2728 struct sky2_port *sky2 = netdev_priv(dev);
2729 struct sky2_hw *hw = sky2->hw;
2730 unsigned port = sky2->port;
2731 struct dev_mc_list *list = dev->mc_list;
2732 u16 reg;
2733 u8 filter[8];
2734
2735 memset(filter, 0, sizeof(filter));
2736
2737 reg = gma_read16(hw, port, GM_RX_CTRL);
2738 reg |= GM_RXCR_UCF_ENA;
2739
d571b694 2740 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2741 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2742 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2743 memset(filter, 0xff, sizeof(filter));
793b883e 2744 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2745 reg &= ~GM_RXCR_MCF_ENA;
2746 else {
2747 int i;
2748 reg |= GM_RXCR_MCF_ENA;
2749
2750 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2751 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2752 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2753 }
2754 }
2755
cd28ab6a 2756 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2757 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2758 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2759 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2760 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2761 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2762 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2763 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2764
2765 gma_write16(hw, port, GM_RX_CTRL, reg);
2766}
2767
2768/* Can have one global because blinking is controlled by
2769 * ethtool and that is always under RTNL mutex
2770 */
91c86df5 2771static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2772{
793b883e
SH		 2773 u16 pg;
2774
793b883e
SH		 2775 switch (hw->chip_id) {
2776 case CHIP_ID_YUKON_XL:
2777 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2778 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2779 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2780 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2781 PHY_M_LEDC_INIT_CTRL(7) |
2782 PHY_M_LEDC_STA1_CTRL(7) |
2783 PHY_M_LEDC_STA0_CTRL(7))
2784 : 0);
2785
2786 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2787 break;
2788
2789 default:
2790 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2791 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2792 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2793 PHY_M_LED_MO_10(MO_LED_ON) |
2794 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2795 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2796 PHY_M_LED_MO_RX(MO_LED_ON)
2797 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2798 PHY_M_LED_MO_10(MO_LED_OFF) |
2799 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2800 PHY_M_LED_MO_1000(MO_LED_OFF) |
2801 PHY_M_LED_MO_RX(MO_LED_OFF));
2802
793b883e 2803 }
cd28ab6a
SH		 2804}
2805
2806/* blink LED's for finding board */
2807static int sky2_phys_id(struct net_device *dev, u32 data)
2808{
2809 struct sky2_port *sky2 = netdev_priv(dev);
2810 struct sky2_hw *hw = sky2->hw;
2811 unsigned port = sky2->port;
793b883e 2812 u16 ledctrl, ledover = 0;
cd28ab6a 2813 long ms;
91c86df5 2814 int interrupted;
cd28ab6a
SH		 2815 int onoff = 1;
2816
793b883e 2817 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2818 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2819 else
2820 ms = data * 1000;
2821
2822 /* save initial values */
e07b1aa8 2823 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2824 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2825 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2826 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2827 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2828 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2829 } else {
2830 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2831 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2832 }
cd28ab6a 2833
91c86df5
SH		 2834 interrupted = 0;
2835 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2836 sky2_led(hw, port, onoff);
2837 onoff = !onoff;
2838
e07b1aa8 2839 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2840 interrupted = msleep_interruptible(250);
e07b1aa8 2841 spin_lock_bh(&sky2->phy_lock);
91c86df5 2842
cd28ab6a
SH		 2843 ms -= 250;
2844 }
2845
2846 /* resume regularly scheduled programming */
793b883e
SH		 2847 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2848 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2849 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2850 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2851 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2852 } else {
2853 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2854 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2855 }
e07b1aa8 2856 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2857
2858 return 0;
2859}
2860
2861static void sky2_get_pauseparam(struct net_device *dev,
2862 struct ethtool_pauseparam *ecmd)
2863{
2864 struct sky2_port *sky2 = netdev_priv(dev);
2865
2866 ecmd->tx_pause = sky2->tx_pause;
2867 ecmd->rx_pause = sky2->rx_pause;
2868 ecmd->autoneg = sky2->autoneg;
2869}
2870
2871static int sky2_set_pauseparam(struct net_device *dev,
2872 struct ethtool_pauseparam *ecmd)
2873{
2874 struct sky2_port *sky2 = netdev_priv(dev);
2875 int err = 0;
2876
2877 sky2->autoneg = ecmd->autoneg;
2878 sky2->tx_pause = ecmd->tx_pause != 0;
2879 sky2->rx_pause = ecmd->rx_pause != 0;
2880
1b537565 2881 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2882
2883 return err;
2884}
2885
fb17358f
SH		 2886static int sky2_get_coalesce(struct net_device *dev,
2887 struct ethtool_coalesce *ecmd)
2888{
2889 struct sky2_port *sky2 = netdev_priv(dev);
2890 struct sky2_hw *hw = sky2->hw;
2891
2892 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2893 ecmd->tx_coalesce_usecs = 0;
2894 else {
2895 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2896 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2897 }
2898 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2899
2900 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2901 ecmd->rx_coalesce_usecs = 0;
2902 else {
2903 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2904 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2905 }
2906 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2907
2908 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2909 ecmd->rx_coalesce_usecs_irq = 0;
2910 else {
2911 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2912 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2913 }
2914
2915 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2916
2917 return 0;
2918}
2919
2920/* Note: this affect both ports */
2921static int sky2_set_coalesce(struct net_device *dev,
2922 struct ethtool_coalesce *ecmd)
2923{
2924 struct sky2_port *sky2 = netdev_priv(dev);
2925 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2926 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2927
77b3d6a2
SH		 2928 if (ecmd->tx_coalesce_usecs > tmax ||
2929 ecmd->rx_coalesce_usecs > tmax ||
2930 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2931 return -EINVAL;
2932
ff81fbbe 2933 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2934 return -EINVAL;
ff81fbbe 2935 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2936 return -EINVAL;
ff81fbbe 2937 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2938 return -EINVAL;
2939
2940 if (ecmd->tx_coalesce_usecs == 0)
2941 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2942 else {
2943 sky2_write32(hw, STAT_TX_TIMER_INI,
2944 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2945 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2946 }
2947 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2948
2949 if (ecmd->rx_coalesce_usecs == 0)
2950 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2951 else {
2952 sky2_write32(hw, STAT_LEV_TIMER_INI,
2953 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2954 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2955 }
2956 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2957
2958 if (ecmd->rx_coalesce_usecs_irq == 0)
2959 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2960 else {
d28d4870 2961 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2962 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2963 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2964 }
2965 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2966 return 0;
2967}
2968
793b883e
SH		 2969static void sky2_get_ringparam(struct net_device *dev,
2970 struct ethtool_ringparam *ering)
2971{
2972 struct sky2_port *sky2 = netdev_priv(dev);
2973
2974 ering->rx_max_pending = RX_MAX_PENDING;
2975 ering->rx_mini_max_pending = 0;
2976 ering->rx_jumbo_max_pending = 0;
2977 ering->tx_max_pending = TX_RING_SIZE - 1;
2978
2979 ering->rx_pending = sky2->rx_pending;
2980 ering->rx_mini_pending = 0;
2981 ering->rx_jumbo_pending = 0;
2982 ering->tx_pending = sky2->tx_pending;
2983}
2984
2985static int sky2_set_ringparam(struct net_device *dev,
2986 struct ethtool_ringparam *ering)
2987{
2988 struct sky2_port *sky2 = netdev_priv(dev);
2989 int err = 0;
2990
2991 if (ering->rx_pending > RX_MAX_PENDING ||
2992 ering->rx_pending < 8 ||
2993 ering->tx_pending < MAX_SKB_TX_LE ||
2994 ering->tx_pending > TX_RING_SIZE - 1)
2995 return -EINVAL;
2996
2997 if (netif_running(dev))
2998 sky2_down(dev);
2999
3000 sky2->rx_pending = ering->rx_pending;
3001 sky2->tx_pending = ering->tx_pending;
3002
1b537565 3003 if (netif_running(dev)) {
793b883e 3004 err = sky2_up(dev);
1b537565
SH		 3005 if (err)
3006 dev_close(dev);
6ed995bb
SH		 3007 else
3008 sky2_set_multicast(dev);
1b537565 3009 }
793b883e
SH		 3010
3011 return err;
3012}
3013
793b883e
SH		 3014static int sky2_get_regs_len(struct net_device *dev)
3015{
6e4cbb34 3016 return 0x4000;
793b883e
SH		 3017}
3018
3019/*
3020 * Returns copy of control register region
6e4cbb34 3021 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3022 */
3023static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3024 void *p)
3025{
3026 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3027 const void __iomem *io = sky2->hw->regs;
793b883e 3028
6e4cbb34 3029 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3030 regs->version = 1;
6e4cbb34 3031 memset(p, 0, regs->len);
793b883e 3032
6e4cbb34
SH		 3033 memcpy_fromio(p, io, B3_RAM_ADDR);
3034
3035 memcpy_fromio(p + B3_RI_WTO_R1,
3036 io + B3_RI_WTO_R1,
3037 regs->len - B3_RI_WTO_R1);
793b883e 3038}
cd28ab6a
SH		 3039
3040static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3041 .get_settings = sky2_get_settings,
3042 .set_settings = sky2_set_settings,
3043 .get_drvinfo = sky2_get_drvinfo,
3044 .get_msglevel = sky2_get_msglevel,
3045 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3046 .nway_reset = sky2_nway_reset,
793b883e
SH		 3047 .get_regs_len = sky2_get_regs_len,
3048 .get_regs = sky2_get_regs,
3049 .get_link = ethtool_op_get_link,
3050 .get_sg = ethtool_op_get_sg,
3051 .set_sg = ethtool_op_set_sg,
3052 .get_tx_csum = ethtool_op_get_tx_csum,
3053 .set_tx_csum = ethtool_op_set_tx_csum,
3054 .get_tso = ethtool_op_get_tso,
3055 .set_tso = ethtool_op_set_tso,
3056 .get_rx_csum = sky2_get_rx_csum,
3057 .set_rx_csum = sky2_set_rx_csum,
3058 .get_strings = sky2_get_strings,
fb17358f
SH		 3059 .get_coalesce = sky2_get_coalesce,
3060 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3061 .get_ringparam = sky2_get_ringparam,
3062 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3063 .get_pauseparam = sky2_get_pauseparam,
3064 .set_pauseparam = sky2_set_pauseparam,
793b883e 3065 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3066 .get_stats_count = sky2_get_stats_count,
3067 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3068 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3069};
3070
3071/* Initialize network device */
3072static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3073 unsigned port, int highmem)
3074{
3075 struct sky2_port *sky2;
3076 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3077
3078 if (!dev) {
3079 printk(KERN_ERR "sky2 etherdev alloc failed");
3080 return NULL;
3081 }
3082
3083 SET_MODULE_OWNER(dev);
3084 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3085 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3086 dev->open = sky2_up;
3087 dev->stop = sky2_down;
ef743d33 3088 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3089 dev->hard_start_xmit = sky2_xmit_frame;
3090 dev->get_stats = sky2_get_stats;
3091 dev->set_multicast_list = sky2_set_multicast;
3092 dev->set_mac_address = sky2_set_mac_address;
3093 dev->change_mtu = sky2_change_mtu;
3094 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3095 dev->tx_timeout = sky2_tx_timeout;
3096 dev->watchdog_timeo = TX_WATCHDOG;
3097 if (port == 0)
3098 dev->poll = sky2_poll;
3099 dev->weight = NAPI_WEIGHT;
3100#ifdef CONFIG_NET_POLL_CONTROLLER
3101 dev->poll_controller = sky2_netpoll;
3102#endif
cd28ab6a
SH		 3103
3104 sky2 = netdev_priv(dev);
3105 sky2->netdev = dev;
3106 sky2->hw = hw;
3107 sky2->msg_enable = netif_msg_init(debug, default_msg);
3108
3109 spin_lock_init(&sky2->tx_lock);
3110 /* Auto speed and flow control */
3111 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3112 sky2->tx_pause = 1;
cd28ab6a
SH		 3113 sky2->rx_pause = 1;
3114 sky2->duplex = -1;
3115 sky2->speed = -1;
3116 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3117 sky2->rx_csum = 1;
75d070c5 3118
e07b1aa8 3119 spin_lock_init(&sky2->phy_lock);
793b883e 3120 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3121 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3122 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3123
3124 hw->dev[port] = dev;
3125
3126 sky2->port = port;
3127
5a5b1ea0 3128 dev->features |= NETIF_F_LLTX;
3129 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3130 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3131 if (highmem)
3132 dev->features |= NETIF_F_HIGHDMA;
793b883e 3133 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3134
d1f13708 3135#ifdef SKY2_VLAN_TAG_USED
3136 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3137 dev->vlan_rx_register = sky2_vlan_rx_register;
3138 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3139#endif
3140
cd28ab6a 3141 /* read the mac address */
793b883e 3142 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3143 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3144
3145 /* device is off until link detection */
3146 netif_carrier_off(dev);
3147 netif_stop_queue(dev);
3148
3149 return dev;
3150}
3151
28bd181a 3152static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3153{
3154 const struct sky2_port *sky2 = netdev_priv(dev);
3155
3156 if (netif_msg_probe(sky2))
3157 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3158 dev->name,
3159 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3160 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3161}
3162
fb2690a9
SH		 3163/* Handle software interrupt used during MSI test */
3164static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3165 struct pt_regs *regs)
3166{
3167 struct sky2_hw *hw = dev_id;
3168 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3169
3170 if (status == 0)
3171 return IRQ_NONE;
3172
3173 if (status & Y2_IS_IRQ_SW) {
3174 hw->msi_detected = 1;
3175 wake_up(&hw->msi_wait);
3176 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3177 }
3178 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3179
3180 return IRQ_HANDLED;
3181}
3182
3183/* Test interrupt path by forcing a a software IRQ */
3184static int __devinit sky2_test_msi(struct sky2_hw *hw)
3185{
3186 struct pci_dev *pdev = hw->pdev;
3187 int err;
3188
3189 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3190
1fb9df5d 3191 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3192 if (err) {
3193 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3194 pci_name(pdev), pdev->irq);
3195 return err;
3196 }
3197
3198 init_waitqueue_head (&hw->msi_wait);
3199
3200 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3201 wmb();
3202
3203 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3204
3205 if (!hw->msi_detected) {
3206 /* MSI test failed, go back to INTx mode */
3207 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3208 "switching to INTx mode. Please report this failure to "
3209 "the PCI maintainer and include system chipset information.\n",
3210 pci_name(pdev));
3211
3212 err = -EOPNOTSUPP;
3213 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3214 }
3215
3216 sky2_write32(hw, B0_IMSK, 0);
3217
3218 free_irq(pdev->irq, hw);
3219
3220 return err;
3221}
3222
cd28ab6a
SH		 3223static int __devinit sky2_probe(struct pci_dev *pdev,
3224 const struct pci_device_id *ent)
3225{
793b883e 3226 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3227 struct sky2_hw *hw;
5afa0a9c 3228 int err, pm_cap, using_dac = 0;
cd28ab6a 3229
793b883e
SH		 3230 err = pci_enable_device(pdev);
3231 if (err) {
cd28ab6a
SH		 3232 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3233 pci_name(pdev));
3234 goto err_out;
3235 }
3236
793b883e
SH		 3237 err = pci_request_regions(pdev, DRV_NAME);
3238 if (err) {
cd28ab6a
SH		 3239 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3240 pci_name(pdev));
793b883e 3241 goto err_out;
cd28ab6a
SH		 3242 }
3243
3244 pci_set_master(pdev);
3245
5afa0a9c 3246 /* Find power-management capability. */
3247 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3248 if (pm_cap == 0) {
3249 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3250 "aborting.\n");
3251 err = -EIO;
3252 goto err_out_free_regions;
3253 }
3254
d1f3d4dd
SH		 3255 if (sizeof(dma_addr_t) > sizeof(u32) &&
3256 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3257 using_dac = 1;
3258 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3259 if (err < 0) {
3260 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3261 "for consistent allocations\n", pci_name(pdev));
3262 goto err_out_free_regions;
3263 }
cd28ab6a 3264
d1f3d4dd 3265 } else {
cd28ab6a
SH		 3266 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3267 if (err) {
3268 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3269 pci_name(pdev));
3270 goto err_out_free_regions;
3271 }
3272 }
d1f3d4dd 3273
cd28ab6a 3274 err = -ENOMEM;
6aad85d6 3275 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3276 if (!hw) {
3277 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3278 pci_name(pdev));
3279 goto err_out_free_regions;
3280 }
3281
cd28ab6a 3282 hw->pdev = pdev;
cd28ab6a
SH		 3283
3284 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3285 if (!hw->regs) {
3286 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3287 pci_name(pdev));
3288 goto err_out_free_hw;
3289 }
5afa0a9c 3290 hw->pm_cap = pm_cap;
cd28ab6a 3291
56a645cc
SH		 3292#ifdef __BIG_ENDIAN
3293 /* byte swap descriptors in hardware */
3294 {
3295 u32 reg;
3296
3297 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3298 reg |= PCI_REV_DESC;
3299 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3300 }
3301#endif
3302
08c06d8a
SH		 3303 /* ring for status responses */
3304 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3305 &hw->st_dma);
3306 if (!hw->st_le)
3307 goto err_out_iounmap;
3308
cd28ab6a
SH		 3309 err = sky2_reset(hw);
3310 if (err)
793b883e 3311 goto err_out_iounmap;
cd28ab6a 3312
7c7459d1
GKH		 3313 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3314 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3315 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3316 hw->chip_id, hw->chip_rev);
cd28ab6a 3317
793b883e
SH		 3318 dev = sky2_init_netdev(hw, 0, using_dac);
3319 if (!dev)
cd28ab6a
SH		 3320 goto err_out_free_pci;
3321
793b883e
SH		 3322 err = register_netdev(dev);
3323 if (err) {
cd28ab6a
SH		 3324 printk(KERN_ERR PFX "%s: cannot register net device\n",
3325 pci_name(pdev));
3326 goto err_out_free_netdev;
3327 }
3328
3329 sky2_show_addr(dev);
3330
3331 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3332 if (register_netdev(dev1) == 0)
3333 sky2_show_addr(dev1);
3334 else {
3335 /* Failure to register second port need not be fatal */
793b883e
SH		 3336 printk(KERN_WARNING PFX
3337 "register of second port failed\n");
cd28ab6a
SH		 3338 hw->dev[1] = NULL;
3339 free_netdev(dev1);
3340 }
3341 }
3342
fb2690a9
SH		 3343 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3344 err = sky2_test_msi(hw);
3345 if (err == -EOPNOTSUPP)
3346 pci_disable_msi(pdev);
3347 else if (err)
3348 goto err_out_unregister;
3349 }
3350
1fb9df5d 3351 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw);
793b883e
SH		 3352 if (err) {
3353 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3354 pci_name(pdev), pdev->irq);
3355 goto err_out_unregister;
3356 }
3357
e07b1aa8 3358 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3359
01bd7564 3360 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3361 sky2_idle_start(hw);
d27ed387 3362
793b883e
SH		 3363 pci_set_drvdata(pdev, hw);
3364
cd28ab6a
SH		 3365 return 0;
3366
793b883e 3367err_out_unregister:
fb2690a9 3368 pci_disable_msi(pdev);
793b883e
SH		 3369 if (dev1) {
3370 unregister_netdev(dev1);
3371 free_netdev(dev1);
3372 }
3373 unregister_netdev(dev);
cd28ab6a
SH		 3374err_out_free_netdev:
3375 free_netdev(dev);
cd28ab6a 3376err_out_free_pci:
793b883e 3377 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3378 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3379err_out_iounmap:
3380 iounmap(hw->regs);
3381err_out_free_hw:
3382 kfree(hw);
3383err_out_free_regions:
3384 pci_release_regions(pdev);
cd28ab6a 3385 pci_disable_device(pdev);
cd28ab6a
SH		 3386err_out:
3387 return err;
3388}
3389
3390static void __devexit sky2_remove(struct pci_dev *pdev)
3391{
793b883e 3392 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3393 struct net_device *dev0, *dev1;
3394
793b883e 3395 if (!hw)
cd28ab6a
SH		 3396 return;
3397
d27ed387
SH		 3398 del_timer_sync(&hw->idle_timer);
3399
3400 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3401 synchronize_irq(hw->pdev->irq);
3402
cd28ab6a 3403 dev0 = hw->dev[0];
793b883e
SH		 3404 dev1 = hw->dev[1];
3405 if (dev1)
3406 unregister_netdev(dev1);
cd28ab6a
SH		 3407 unregister_netdev(dev0);
3408
5afa0a9c 3409 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3410 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3411 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3412 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3413
3414 free_irq(pdev->irq, hw);
fb2690a9 3415 pci_disable_msi(pdev);
793b883e 3416 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3417 pci_release_regions(pdev);
3418 pci_disable_device(pdev);
793b883e 3419
cd28ab6a
SH		 3420 if (dev1)
3421 free_netdev(dev1);
3422 free_netdev(dev0);
3423 iounmap(hw->regs);
3424 kfree(hw);
5afa0a9c 3425
cd28ab6a
SH		 3426 pci_set_drvdata(pdev, NULL);
3427}
3428
3429#ifdef CONFIG_PM
3430static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3431{
793b883e 3432 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3433 int i;
2ccc99b7
SH		 3434 pci_power_t pstate = pci_choose_state(pdev, state);
3435
3436 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3437 return -EINVAL;
cd28ab6a 3438
eb35cf60
SH		 3439 del_timer_sync(&hw->idle_timer);
3440
f05267e7 3441 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3442 struct net_device *dev = hw->dev[i];
3443
3444 if (dev) {
5afa0a9c 3445 if (!netif_running(dev))
3446 continue;
3447
3448 sky2_down(dev);
cd28ab6a 3449 netif_device_detach(dev);
88d11360 3450 netif_poll_disable(dev);
cd28ab6a
SH		 3451 }
3452 }
3453
8ab8fca2 3454 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3455 pci_save_state(pdev);
2ccc99b7
SH		 3456 sky2_set_power_state(hw, pstate);
3457 return 0;
cd28ab6a
SH		 3458}
3459
3460static int sky2_resume(struct pci_dev *pdev)
3461{
793b883e 3462 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3463 int i, err;
cd28ab6a 3464
cd28ab6a
SH		 3465 pci_restore_state(pdev);
3466 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3467 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3468
08c06d8a
SH		 3469 err = sky2_reset(hw);
3470 if (err)
3471 goto out;
cd28ab6a 3472
8ab8fca2
SH		 3473 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3474
f05267e7 3475 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3476 struct net_device *dev = hw->dev[i];
08c06d8a
SH		 3477 if (dev && netif_running(dev)) {
3478 netif_device_attach(dev);
88d11360
SH		 3479 netif_poll_enable(dev);
3480
08c06d8a
SH		 3481 err = sky2_up(dev);
3482 if (err) {
3483 printk(KERN_ERR PFX "%s: could not up: %d\n",
3484 dev->name, err);
3485 dev_close(dev);
eb35cf60 3486 goto out;
5afa0a9c 3487 }
cd28ab6a
SH		 3488 }
3489 }
eb35cf60
SH		 3490
3491 sky2_idle_start(hw);
08c06d8a
SH		 3492out:
3493 return err;
cd28ab6a
SH		 3494}
3495#endif
3496
3497static struct pci_driver sky2_driver = {
793b883e
SH		 3498 .name = DRV_NAME,
3499 .id_table = sky2_id_table,
3500 .probe = sky2_probe,
3501 .remove = __devexit_p(sky2_remove),
cd28ab6a 3502#ifdef CONFIG_PM
793b883e
SH		 3503 .suspend = sky2_suspend,
3504 .resume = sky2_resume,
cd28ab6a
SH		 3505#endif
3506};
3507
3508static int __init sky2_init_module(void)
3509{
50241c4c 3510 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3511}
3512
3513static void __exit sky2_cleanup_module(void)
3514{
3515 pci_unregister_driver(&sky2_driver);
3516}
3517
3518module_init(sky2_init_module);
3519module_exit(sky2_cleanup_module);
3520
3521MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3522MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3523MODULE_LICENSE("GPL");
5f4f9dc1 3524MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)