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sky2: hold spinlock around phy_power_down
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
e4f1482e 53#define DRV_VERSION "1.23"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 66
67#define TX_RING_SIZE 512
e9c1be80 68#define TX_DEF_PENDING 128
b19666d9 69#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
cd28ab6a 71
793b883e 72#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 73#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 74#define TX_WATCHDOG (5 * HZ)
75#define NAPI_WEIGHT 64
76#define PHY_RETRIES 1000
77
f4331a6d
SH		 78#define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
cb5d9547
SH		 81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH		 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH		 89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
14d0263f 92static int copybreak __read_mostly = 128;
bdb5c58e
SH		 93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH		 96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
e6cac9ba 100static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0
SH		 150static void sky2_set_multicast(struct net_device *dev);
151
af043aa5 152/* Access to PHY via serial interconnect */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
af043aa5
SH		 168
169 udelay(10);
cd28ab6a 170 }
ef743d33 171
af043aa5 172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 173 return -ETIMEDOUT;
af043aa5
SH		 174
175io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
cd28ab6a
SH		 178}
179
ef743d33 180static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 181{
182 int i;
183
793b883e 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
af043aa5 197 udelay(10);
cd28ab6a
SH		 198 }
199
af043aa5 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 201 return -ETIMEDOUT;
af043aa5
SH		 202io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
ef743d33 205}
206
af043aa5 207static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 208{
209 u16 v;
af043aa5 210 __gm_phy_read(hw, port, reg, &v);
ef743d33 211 return v;
cd28ab6a
SH		 212}
213
5afa0a9c 214
ae306cca
SH		 215static void sky2_power_on(struct sky2_hw *hw)
216{
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 220
ae306cca
SH		 221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 223
ae306cca
SH		 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 232
ea76e635 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 234 u32 reg;
5afa0a9c 235
b32f40c4 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 237
b32f40c4 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 247
b32f40c4 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 254
255 sky2_read32(hw, B2_GP_IO);
5afa0a9c 256 }
ae306cca 257}
5afa0a9c 258
ae306cca
SH		 259static void sky2_power_aux(struct sky2_hw *hw)
260{
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 275}
276
d3bcfbeb 277static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
16ad91e1
SH		 294/* flow control to advertise bits */
295static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300};
301
302/* flow control to advertise bits when using 1000BaseX */
303static const u16 fiber_fc_adv[] = {
df3fe1f3 304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 308};
309
310/* flow control to GMA disable bits */
311static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316};
317
318
cd28ab6a
SH		 319static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320{
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 323
ea76e635
SH		 324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 329 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
53419c68 332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 333 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 334 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
53419c68
SH		 337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 344 if (sky2_is_copper(hw)) {
05745c4a 345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
cd28ab6a
SH		 358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
53419c68 365 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 366 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 368 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
cd28ab6a
SH		 373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 378 }
cd28ab6a 379
b89165f2
SH		 380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
ea76e635 383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 385
b89165f2
SH		 386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 401 }
b89165f2
SH		 402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 404 }
405
7800fddc 406 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
2eaba1a2 409 reg = 0;
cd28ab6a
SH		 410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 412 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
709c6e7b 425
16ad91e1 426 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 432
16ad91e1 433 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 434 }
cd28ab6a
SH		 435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
2eaba1a2
SH		 442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
2eaba1a2 448 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
2eaba1a2 452 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 453 break;
454 }
455
2eaba1a2
SH		 456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
2eaba1a2 461
2eaba1a2 462
16ad91e1 463 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 464
465 /* Forward pause packets to GMAC? */
16ad91e1 466 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 470 }
471
2eaba1a2
SH		 472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
05745c4a 474 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
05745c4a
SH		 498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
cd28ab6a 515 case CHIP_ID_YUKON_XL:
793b883e 516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
ed6d32c7
SH		 522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 536
537 /* restore page register */
793b883e 538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 539 break;
93745494 540
ed6d32c7 541 case CHIP_ID_YUKON_EC_U:
93745494 542 case CHIP_ID_YUKON_EX:
ed4d4161 543 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
cd28ab6a
SH		 562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 566
cd28ab6a 567 /* turn off the Rx LED (LED_RX) */
a84d0a3d 568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 569 }
570
0ce8b98d 571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 572 /* apply fixes in PHY AFE */
ed6d32c7
SH		 573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
977bdf06 575 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 578
0ce8b98d
SH		 579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
977bdf06
SH		 584
585 /* set page register to 0 */
9467a8fc 586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 594 /* no effect on Yukon-XL */
977bdf06 595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 596
977bdf06
SH		 597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 600 }
cd28ab6a 601
977bdf06
SH		 602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
2eaba1a2 606
d571b694 607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612}
613
b96936da
SH		 614static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 618{
619 u32 reg1;
d3bcfbeb 620
82637e80 621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 623 reg1 &= ~phy_power[port];
d3bcfbeb 624
b96936da 625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 626 reg1 |= coma_mode[port];
627
b32f40c4 628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 636}
167f53d0 637
b96936da
SH		 638static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639{
640 u32 reg1;
db99b988
SH		 641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 670
e484d5f5 671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
b96936da
SH		 683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 689}
690
1b537565
SH		 691/* Force a renegotiation */
692static void sky2_phy_reinit(struct sky2_port *sky2)
693{
e07b1aa8 694 spin_lock_bh(&sky2->phy_lock);
1b537565 695 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 696 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 697}
698
e3173832
SH		 699/* Put device in state to listen for Wake On Lan */
700static void sky2_wol_init(struct sky2_port *sky2)
701{
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
b96936da
SH		 723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
b32f40c4 758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 759 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765}
766
69161611
SH		 767static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768{
05745c4a
SH		 769 struct net_device *dev = hw->dev[port];
770
ed4d4161
SH		 771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
05745c4a 777
ed4d4161
SH		 778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 781
ed4d4161
SH		 782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 792
ed4d4161
SH		 793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
69161611
SH		 798 }
799}
800
cd28ab6a
SH		 801static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802{
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
25cccecc 805 u32 rx_reg;
cd28ab6a
SH		 806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
f350339c
SH		 809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
793b883e 814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
793b883e 826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 827
2eaba1a2
SH		 828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
e07b1aa8 831 spin_lock_bh(&sky2->phy_lock);
b96936da 832 sky2_phy_power_up(hw, port);
cd28ab6a 833 sky2_phy_init(hw, port);
e07b1aa8 834 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
43f2f104
SH		 840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
cd28ab6a
SH		 842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
793b883e 849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 864
6b1a3aef 865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
cd28ab6a
SH		 870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
793b883e
SH		 873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
cd28ab6a
SH		 877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 886 rx_reg |= GMF_RX_OVER_ON;
69161611 887
25cccecc 888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 889
798fdd07
SH		 890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
cd28ab6a 897
8df9a876 898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 909
e0c28116 910 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 914
69161611 915 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 916 }
917
e970d1f8
SH		 918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
cd28ab6a
SH		 925}
926
67712901
SH		 927/* Assign Ram Buffer allocation to queue */
928static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 929{
67712901
SH		 930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
793b883e 936
cd28ab6a
SH		 937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 944 u32 tp = space - space/4;
793b883e 945
1c28f6ba
SH		 946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 952
1c28f6ba
SH		 953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 965}
966
cd28ab6a 967/* Setup Bus Memory Interface */
af4ed7e6 968static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 969{
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 974}
975
cd28ab6a
SH		 976/* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
8cc048e3 979static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 980 u64 addr, u32 last)
981{
cd28ab6a
SH		 982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 990}
991
9b289c33 992static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 993{
9b289c33 994 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 995
9b289c33 996 *slot = RING_NEXT(*slot, TX_RING_SIZE);
291ea614 997 le->ctrl = 0;
793b883e
SH		 998 return le;
999}
cd28ab6a 1000
88f5f0ca
SH		 1001static void tx_init(struct sky2_port *sky2)
1002{
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
9b289c33 1009 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1012}
1013
291ea614
SH		 1014static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016{
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018}
1019
290d4de5
SH		 1020/* Update chip's next pointer */
1021static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1022{
50432cb5 1023 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1024 wmb();
50432cb5
SH		 1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
cd28ab6a
SH		 1029}
1030
793b883e 1031
cd28ab6a
SH		 1032static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033{
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1036 le->ctrl = 0;
cd28ab6a
SH		 1037 return le;
1038}
1039
14d0263f
SH		 1040/* Build description to hardware for one receive segment */
1041static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1043{
1044 struct sky2_rx_le *le;
1045
86c6887e 1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1047 le = sky2_next_rx(sky2);
86c6887e 1048 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
793b883e 1051
cd28ab6a 1052 le = sky2_next_rx(sky2);
734d1868
SH		 1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
14d0263f 1055 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1056}
1057
14d0263f
SH		 1058/* Build description to hardware for one possibly fragmented skb */
1059static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061{
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068}
1069
1070
454e6cb6 1071static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1072 unsigned size)
1073{
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1079 return -EIO;
1080
14d0263f
SH		 1081 pci_unmap_len_set(re, data_size, size);
1082
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
454e6cb6 1089 return 0;
14d0263f
SH		 1090}
1091
1092static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1093{
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1099
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1104}
793b883e 1105
cd28ab6a
SH		 1106/* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1108 * order problems.
1109 */
793b883e 1110static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1111{
ea76e635 1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1113
ea76e635
SH		 1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1115 le->ctrl = 0;
1116 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1117
ea76e635
SH		 1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1121}
1122
6b1a3aef 1123/*
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1131 * will be reset.
1132 */
1133static void sky2_rx_stop(struct sky2_port *sky2)
1134{
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1137 int i;
1138
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1141
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1145 goto stopped;
1146
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1149stopped:
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1151
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1154 mmiowb();
6b1a3aef 1155}
793b883e 1156
d571b694 1157/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1158static void sky2_rx_clean(struct sky2_port *sky2)
1159{
1160 unsigned i;
1161
1162 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1163 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1164 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1165
1166 if (re->skb) {
14d0263f 1167 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1168 kfree_skb(re->skb);
1169 re->skb = NULL;
1170 }
1171 }
bd1c6869 1172 skb_queue_purge(&sky2->rx_recycle);
cd28ab6a
SH		 1173}
1174
ef743d33 1175/* Basic MII support */
1176static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1177{
1178 struct mii_ioctl_data *data = if_mii(ifr);
1179 struct sky2_port *sky2 = netdev_priv(dev);
1180 struct sky2_hw *hw = sky2->hw;
1181 int err = -EOPNOTSUPP;
1182
1183 if (!netif_running(dev))
1184 return -ENODEV; /* Phy still in reset */
1185
d89e1343 1186 switch (cmd) {
ef743d33 1187 case SIOCGMIIPHY:
1188 data->phy_id = PHY_ADDR_MARV;
1189
1190 /* fallthru */
1191 case SIOCGMIIREG: {
1192 u16 val = 0;
91c86df5 1193
e07b1aa8 1194 spin_lock_bh(&sky2->phy_lock);
ef743d33 1195 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1196 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1197
ef743d33 1198 data->val_out = val;
1199 break;
1200 }
1201
1202 case SIOCSMIIREG:
1203 if (!capable(CAP_NET_ADMIN))
1204 return -EPERM;
1205
e07b1aa8 1206 spin_lock_bh(&sky2->phy_lock);
ef743d33 1207 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1208 data->val_in);
e07b1aa8 1209 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1210 break;
1211 }
1212 return err;
1213}
1214
d1f13708 1215#ifdef SKY2_VLAN_TAG_USED
d494eacd 1216static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1217{
d494eacd 1218 if (onoff) {
3d4e66f5
SH		 1219 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1220 RX_VLAN_STRIP_ON);
1221 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1222 TX_VLAN_TAG_ON);
1223 } else {
1224 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1225 RX_VLAN_STRIP_OFF);
1226 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1227 TX_VLAN_TAG_OFF);
1228 }
d494eacd
SH		 1229}
1230
1231static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1232{
1233 struct sky2_port *sky2 = netdev_priv(dev);
1234 struct sky2_hw *hw = sky2->hw;
1235 u16 port = sky2->port;
1236
1237 netif_tx_lock_bh(dev);
1238 napi_disable(&hw->napi);
1239
1240 sky2->vlgrp = grp;
1241 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1242
d1d08d12 1243 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1244 napi_enable(&hw->napi);
2bb8c262 1245 netif_tx_unlock_bh(dev);
d1f13708 1246}
1247#endif
1248
bd1c6869
SH		 1249/* Amount of required worst case padding in rx buffer */
1250static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1251{
1252 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1253}
1254
82788c7a 1255/*
14d0263f
SH		 1256 * Allocate an skb for receiving. If the MTU is large enough
1257 * make the skb non-linear with a fragment list of pages.
82788c7a 1258 */
14d0263f 1259static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1260{
1261 struct sk_buff *skb;
14d0263f 1262 int i;
82788c7a 1263
bd1c6869
SH		 1264 skb = __skb_dequeue(&sky2->rx_recycle);
1265 if (!skb)
1266 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size
1267 + sky2_rx_pad(sky2->hw));
1268 if (!skb)
1269 goto nomem;
1270
39dbd958 1271 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1272 unsigned char *start;
1273 /*
1274 * Workaround for a bug in FIFO that cause hang
1275 * if the FIFO if the receive buffer is not 64 byte aligned.
1276 * The buffer returned from netdev_alloc_skb is
1277 * aligned except if slab debugging is enabled.
1278 */
f03b8654
SH		 1279 start = PTR_ALIGN(skb->data, 8);
1280 skb_reserve(skb, start - skb->data);
bd1c6869 1281 } else
f03b8654 1282 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1283
1284 for (i = 0; i < sky2->rx_nfrags; i++) {
1285 struct page *page = alloc_page(GFP_ATOMIC);
1286
1287 if (!page)
1288 goto free_partial;
1289 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1290 }
1291
1292 return skb;
14d0263f
SH		 1293free_partial:
1294 kfree_skb(skb);
1295nomem:
1296 return NULL;
82788c7a
SH		 1297}
1298
55c9dd35
SH		 1299static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1300{
1301 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1302}
1303
cd28ab6a
SH		 1304/*
1305 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1306 * Normal case this ends up creating one list element for skb
1307 * in the receive ring. Worst case if using large MTU and each
1308 * allocation falls on a different 64 bit region, that results
1309 * in 6 list elements per ring entry.
1310 * One element is used for checksum enable/disable, and one
1311 * extra to avoid wrap.
cd28ab6a 1312 */
6b1a3aef 1313static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1314{
6b1a3aef 1315 struct sky2_hw *hw = sky2->hw;
14d0263f 1316 struct rx_ring_info *re;
6b1a3aef 1317 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1318 unsigned i, size, thresh;
cd28ab6a 1319
6b1a3aef 1320 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1321 sky2_qset(hw, rxq);
977bdf06 1322
c3905bc4
SH		 1323 /* On PCI express lowering the watermark gives better performance */
1324 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1325 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1326
1327 /* These chips have no ram buffer?
1328 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1329 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1330 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1331 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1332 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1333
6b1a3aef 1334 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1335
ea76e635
SH		 1336 if (!(hw->flags & SKY2_HW_NEW_LE))
1337 rx_set_checksum(sky2);
14d0263f
SH		 1338
1339 /* Space needed for frame data + headers rounded up */
f957da2a 1340 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1341
1342 /* Stopping point for hardware truncation */
1343 thresh = (size - 8) / sizeof(u32);
1344
5f06eba4 1345 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1346 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1347
5f06eba4
SH		 1348 /* Compute residue after pages */
1349 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1350
5f06eba4
SH		 1351 /* Optimize to handle small packets and headers */
1352 if (size < copybreak)
1353 size = copybreak;
1354 if (size < ETH_HLEN)
1355 size = ETH_HLEN;
14d0263f 1356
14d0263f
SH		 1357 sky2->rx_data_size = size;
1358
bd1c6869
SH		 1359 skb_queue_head_init(&sky2->rx_recycle);
1360
14d0263f 1361 /* Fill Rx ring */
793b883e 1362 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1363 re = sky2->rx_ring + i;
cd28ab6a 1364
14d0263f 1365 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1366 if (!re->skb)
1367 goto nomem;
1368
454e6cb6
SH		 1369 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1370 dev_kfree_skb(re->skb);
1371 re->skb = NULL;
1372 goto nomem;
1373 }
1374
14d0263f 1375 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1376 }
1377
a1433ac4
SH		 1378 /*
1379 * The receiver hangs if it receives frames larger than the
1380 * packet buffer. As a workaround, truncate oversize frames, but
1381 * the register is limited to 9 bits, so if you do frames > 2052
1382 * you better get the MTU right!
1383 */
a1433ac4
SH		 1384 if (thresh > 0x1ff)
1385 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1386 else {
1387 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1388 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1389 }
1390
6b1a3aef 1391 /* Tell chip about available buffers */
55c9dd35 1392 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1393 return 0;
1394nomem:
1395 sky2_rx_clean(sky2);
1396 return -ENOMEM;
1397}
1398
1399/* Bring up network interface. */
1400static int sky2_up(struct net_device *dev)
1401{
1402 struct sky2_port *sky2 = netdev_priv(dev);
1403 struct sky2_hw *hw = sky2->hw;
1404 unsigned port = sky2->port;
e0c28116 1405 u32 imask, ramsize;
ee7abb04 1406 int cap, err = -ENOMEM;
843a46f4 1407 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1408
ee7abb04
SH		 1409 /*
1410 * On dual port PCI-X card, there is an problem where status
1411 * can be received out of order due to split transactions
843a46f4 1412 */
ee7abb04
SH		 1413 if (otherdev && netif_running(otherdev) &&
1414 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1415 u16 cmd;
1416
b32f40c4 1417 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1418 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1419 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1420
ee7abb04 1421 }
843a46f4 1422
55d7b4e6
SH		 1423 netif_carrier_off(dev);
1424
cd28ab6a
SH		 1425 /* must be power of 2 */
1426 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1427 TX_RING_SIZE *
1428 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1429 &sky2->tx_le_map);
1430 if (!sky2->tx_le)
1431 goto err_out;
1432
6cdbbdf3 1433 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1434 GFP_KERNEL);
1435 if (!sky2->tx_ring)
1436 goto err_out;
88f5f0ca
SH		 1437
1438 tx_init(sky2);
cd28ab6a
SH		 1439
1440 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1441 &sky2->rx_le_map);
1442 if (!sky2->rx_le)
1443 goto err_out;
1444 memset(sky2->rx_le, 0, RX_LE_BYTES);
1445
291ea614 1446 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1447 GFP_KERNEL);
1448 if (!sky2->rx_ring)
1449 goto err_out;
1450
1451 sky2_mac_init(hw, port);
1452
e0c28116
SH		 1453 /* Register is number of 4K blocks on internal RAM buffer. */
1454 ramsize = sky2_read8(hw, B2_E_0) * 4;
1455 if (ramsize > 0) {
67712901 1456 u32 rxspace;
cd28ab6a 1457
39dbd958 1458 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1459 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1460 if (ramsize < 16)
1461 rxspace = ramsize / 2;
1462 else
1463 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1464
67712901
SH		 1465 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1466 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1467
1468 /* Make sure SyncQ is disabled */
1469 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1470 RB_RST_SET);
1471 }
793b883e 1472
af4ed7e6 1473 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1474
69161611
SH		 1475 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1476 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1477 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1478
977bdf06 1479 /* Set almost empty threshold */
c2716fb4
SH		 1480 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1481 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1482 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1483
6b1a3aef 1484 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1485 TX_RING_SIZE - 1);
cd28ab6a 1486
d494eacd
SH		 1487#ifdef SKY2_VLAN_TAG_USED
1488 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1489#endif
1490
f6caa14a
MM		 1491 sky2->restarting = 0;
1492
6b1a3aef 1493 err = sky2_rx_start(sky2);
6de16237 1494 if (err)
cd28ab6a
SH		 1495 goto err_out;
1496
cd28ab6a 1497 /* Enable interrupts from phy/mac for port */
e07b1aa8 1498 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1499 imask |= portirq_msk[port];
e07b1aa8 1500 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1501 sky2_read32(hw, B0_IMSK);
e07b1aa8 1502
a7bffe72 1503 sky2_set_multicast(dev);
a11da890 1504
f6caa14a
MM		 1505 /* wake queue incase we are restarting */
1506 netif_wake_queue(dev);
1507
a11da890
AD		 1508 if (netif_msg_ifup(sky2))
1509 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
cd28ab6a
SH		 1510 return 0;
1511
1512err_out:
1b537565 1513 if (sky2->rx_le) {
cd28ab6a
SH		 1514 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1515 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1516 sky2->rx_le = NULL;
1517 }
1518 if (sky2->tx_le) {
cd28ab6a
SH		 1519 pci_free_consistent(hw->pdev,
1520 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1521 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1522 sky2->tx_le = NULL;
1523 }
1524 kfree(sky2->tx_ring);
1525 kfree(sky2->rx_ring);
cd28ab6a 1526
1b537565
SH		 1527 sky2->tx_ring = NULL;
1528 sky2->rx_ring = NULL;
cd28ab6a
SH		 1529 return err;
1530}
1531
793b883e
SH		 1532/* Modular subtraction in ring */
1533static inline int tx_dist(unsigned tail, unsigned head)
1534{
cb5d9547 1535 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1536}
cd28ab6a 1537
793b883e
SH		 1538/* Number of list elements available for next tx */
1539static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1540{
f6caa14a
MM		 1541 if (unlikely(sky2->restarting))
1542 return 0;
793b883e 1543 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1544}
1545
793b883e 1546/* Estimate of number of transmit list elements required */
28bd181a 1547static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1548{
793b883e
SH		 1549 unsigned count;
1550
1551 count = sizeof(dma_addr_t) / sizeof(u32);
1552 count += skb_shinfo(skb)->nr_frags * count;
1553
89114afd 1554 if (skb_is_gso(skb))
793b883e
SH		 1555 ++count;
1556
84fa7933 1557 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1558 ++count;
1559
1560 return count;
cd28ab6a
SH		 1561}
1562
793b883e
SH		 1563/*
1564 * Put one packet in ring for transmit.
1565 * A single packet can generate multiple list elements, and
1566 * the number of ring elements will probably be less than the number
1567 * of list elements used.
1568 */
cd28ab6a
SH		 1569static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1570{
1571 struct sky2_port *sky2 = netdev_priv(dev);
1572 struct sky2_hw *hw = sky2->hw;
d1f13708 1573 struct sky2_tx_le *le = NULL;
6cdbbdf3 1574 struct tx_ring_info *re;
9b289c33
MM		 1575 unsigned i, len;
1576 u16 slot;
cd28ab6a 1577 dma_addr_t mapping;
cd28ab6a
SH		 1578 u16 mss;
1579 u8 ctrl;
1580
2bb8c262
SH		 1581 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1582 return NETDEV_TX_BUSY;
cd28ab6a 1583
cd28ab6a
SH		 1584 len = skb_headlen(skb);
1585 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1586
454e6cb6
SH		 1587 if (pci_dma_mapping_error(hw->pdev, mapping))
1588 goto mapping_error;
1589
9b289c33 1590 slot = sky2->tx_prod;
454e6cb6
SH		 1591 if (unlikely(netif_msg_tx_queued(sky2)))
1592 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1593 dev->name, slot, skb->len);
454e6cb6 1594
86c6887e
SH		 1595 /* Send high bits if needed */
1596 if (sizeof(dma_addr_t) > sizeof(u32)) {
9b289c33 1597 le = get_tx_le(sky2, &slot);
86c6887e 1598 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1599 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1600 }
cd28ab6a
SH		 1601
1602 /* Check for TCP Segmentation Offload */
7967168c 1603 mss = skb_shinfo(skb)->gso_size;
793b883e 1604 if (mss != 0) {
ea76e635
SH		 1605
1606 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1607 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1608
1609 if (mss != sky2->tx_last_mss) {
9b289c33 1610 le = get_tx_le(sky2, &slot);
69161611 1611 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1612
1613 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1614 le->opcode = OP_MSS | HW_OWNER;
1615 else
1616 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1617 sky2->tx_last_mss = mss;
1618 }
cd28ab6a
SH		 1619 }
1620
cd28ab6a 1621 ctrl = 0;
d1f13708 1622#ifdef SKY2_VLAN_TAG_USED
1623 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1624 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1625 if (!le) {
9b289c33 1626 le = get_tx_le(sky2, &slot);
f65b138c 1627 le->addr = 0;
d1f13708 1628 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1629 } else
1630 le->opcode |= OP_VLAN;
1631 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1632 ctrl |= INS_VLAN;
1633 }
1634#endif
1635
1636 /* Handle TCP checksum offload */
84fa7933 1637 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1638 /* On Yukon EX (some versions) encoding change. */
ea76e635 1639 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1640 ctrl |= CALSUM; /* auto checksum */
1641 else {
1642 const unsigned offset = skb_transport_offset(skb);
1643 u32 tcpsum;
1644
1645 tcpsum = offset << 16; /* sum start */
1646 tcpsum |= offset + skb->csum_offset; /* sum write */
1647
1648 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1649 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1650 ctrl |= UDPTCP;
1651
1652 if (tcpsum != sky2->tx_tcpsum) {
1653 sky2->tx_tcpsum = tcpsum;
1654
9b289c33 1655 le = get_tx_le(sky2, &slot);
69161611
SH		 1656 le->addr = cpu_to_le32(tcpsum);
1657 le->length = 0; /* initial checksum value */
1658 le->ctrl = 1; /* one packet */
1659 le->opcode = OP_TCPLISW | HW_OWNER;
1660 }
1d179332 1661 }
cd28ab6a
SH		 1662 }
1663
9b289c33 1664 le = get_tx_le(sky2, &slot);
f65b138c 1665 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1666 le->length = cpu_to_le16(len);
1667 le->ctrl = ctrl;
793b883e 1668 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1669
291ea614 1670 re = tx_le_re(sky2, le);
cd28ab6a 1671 re->skb = skb;
6cdbbdf3 1672 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1673 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1674
1675 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1676 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1677
1678 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1679 frag->size, PCI_DMA_TODEVICE);
86c6887e 1680
454e6cb6
SH		 1681 if (pci_dma_mapping_error(hw->pdev, mapping))
1682 goto mapping_unwind;
1683
86c6887e 1684 if (sizeof(dma_addr_t) > sizeof(u32)) {
9b289c33 1685 le = get_tx_le(sky2, &slot);
86c6887e 1686 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1687 le->ctrl = 0;
1688 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1689 }
1690
9b289c33 1691 le = get_tx_le(sky2, &slot);
f65b138c 1692 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1693 le->length = cpu_to_le16(frag->size);
1694 le->ctrl = ctrl;
793b883e 1695 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1696
291ea614
SH		 1697 re = tx_le_re(sky2, le);
1698 re->skb = skb;
1699 pci_unmap_addr_set(re, mapaddr, mapping);
1700 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1701 }
6cdbbdf3 1702
cd28ab6a
SH		 1703 le->ctrl |= EOP;
1704
9b289c33
MM		 1705 sky2->tx_prod = slot;
1706
97bda706 1707 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1708 netif_stop_queue(dev);
b19666d9 1709
290d4de5 1710 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1711
cd28ab6a 1712 return NETDEV_TX_OK;
454e6cb6
SH		 1713
1714mapping_unwind:
9b289c33 1715 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, TX_RING_SIZE)) {
454e6cb6
SH		 1716 le = sky2->tx_le + i;
1717 re = sky2->tx_ring + i;
1718
1719 switch(le->opcode & ~HW_OWNER) {
1720 case OP_LARGESEND:
1721 case OP_PACKET:
1722 pci_unmap_single(hw->pdev,
1723 pci_unmap_addr(re, mapaddr),
1724 pci_unmap_len(re, maplen),
1725 PCI_DMA_TODEVICE);
1726 break;
1727 case OP_BUFFER:
1728 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1729 pci_unmap_len(re, maplen),
1730 PCI_DMA_TODEVICE);
1731 break;
1732 }
1733 }
1734
454e6cb6
SH		 1735mapping_error:
1736 if (net_ratelimit())
1737 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1738 dev_kfree_skb(skb);
1739 return NETDEV_TX_OK;
cd28ab6a
SH		 1740}
1741
cd28ab6a 1742/*
793b883e
SH		 1743 * Free ring elements from starting at tx_cons until "done"
1744 *
1745 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1746 * buffers so make sure not to free skb to early.
cd28ab6a 1747 */
d11c13e7 1748static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1749{
d11c13e7 1750 struct net_device *dev = sky2->netdev;
af2a58ac 1751 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1752 unsigned idx;
cd28ab6a 1753
0e3ff6aa 1754 BUG_ON(done >= TX_RING_SIZE);
2224795d 1755
291ea614
SH		 1756 for (idx = sky2->tx_cons; idx != done;
1757 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1758 struct sky2_tx_le *le = sky2->tx_le + idx;
1759 struct tx_ring_info *re = sky2->tx_ring + idx;
1760
1761 switch(le->opcode & ~HW_OWNER) {
1762 case OP_LARGESEND:
1763 case OP_PACKET:
1764 pci_unmap_single(pdev,
1765 pci_unmap_addr(re, mapaddr),
1766 pci_unmap_len(re, maplen),
1767 PCI_DMA_TODEVICE);
af2a58ac 1768 break;
291ea614
SH		 1769 case OP_BUFFER:
1770 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1771 pci_unmap_len(re, maplen),
734d1868 1772 PCI_DMA_TODEVICE);
291ea614
SH		 1773 break;
1774 }
1775
1776 if (le->ctrl & EOP) {
bd1c6869
SH		 1777 struct sk_buff *skb = re->skb;
1778
291ea614
SH		 1779 if (unlikely(netif_msg_tx_done(sky2)))
1780 printk(KERN_DEBUG "%s: tx done %u\n",
1781 dev->name, idx);
3cf26753 1782
7138a0f5 1783 dev->stats.tx_packets++;
bd1c6869
SH		 1784 dev->stats.tx_bytes += skb->len;
1785
1786 if (skb_queue_len(&sky2->rx_recycle) < sky2->rx_pending
1787 && skb_recycle_check(skb, sky2->rx_data_size
1788 + sky2_rx_pad(sky2->hw)))
1789 __skb_queue_head(&sky2->rx_recycle, skb);
1790 else
1791 dev_kfree_skb_any(skb);
2bf56fe2 1792
3cf26753 1793 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1794 }
793b883e 1795 }
793b883e 1796
291ea614 1797 sky2->tx_cons = idx;
50432cb5
SH		 1798 smp_mb();
1799
22e11703 1800 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1801 netif_wake_queue(dev);
cd28ab6a
SH		 1802}
1803
1804/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1805static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1806{
2bb8c262
SH		 1807 struct sky2_port *sky2 = netdev_priv(dev);
1808
1809 netif_tx_lock_bh(dev);
d11c13e7 1810 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1811 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1812}
1813
264bb4fa 1814static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1815{
a510996b
MM		 1816 /* Disable Force Sync bit and Enable Alloc bit */
1817 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1818 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1819
1820 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1821 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1822 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1823
1824 /* Reset the PCI FIFO of the async Tx queue */
1825 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1826 BMU_RST_SET | BMU_FIFO_RST);
1827
1828 /* Reset the Tx prefetch units */
1829 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1830 PREF_UNIT_RST_SET);
1831
1832 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1833 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1834}
1835
cd28ab6a
SH		 1836/* Network shutdown */
1837static int sky2_down(struct net_device *dev)
1838{
1839 struct sky2_port *sky2 = netdev_priv(dev);
1840 struct sky2_hw *hw = sky2->hw;
1841 unsigned port = sky2->port;
1842 u16 ctrl;
e07b1aa8 1843 u32 imask;
cd28ab6a 1844
1b537565
SH		 1845 /* Never really got started! */
1846 if (!sky2->tx_le)
1847 return 0;
1848
cd28ab6a
SH		 1849 if (netif_msg_ifdown(sky2))
1850 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1851
f6caa14a
MM		 1852 /* explicitly shut off tx incase we're restarting */
1853 sky2->restarting = 1;
1854 netif_tx_disable(dev);
1855
d104acaf
SH		 1856 /* Force flow control off */
1857 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1858
cd28ab6a
SH		 1859 /* Stop transmitter */
1860 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1861 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1862
1863 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1864 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1865
1866 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1867 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1868 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1869
1870 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1871
1872 /* Workaround shared GMAC reset */
793b883e
SH		 1873 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1874 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1875 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1876
cd28ab6a 1877 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1878
6c83504f
SH		 1879 /* Force any delayed status interrrupt and NAPI */
1880 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1881 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1882 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1883 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1884
a947a39d
MM		 1885 sky2_rx_stop(sky2);
1886
1887 /* Disable port IRQ */
1888 imask = sky2_read32(hw, B0_IMSK);
1889 imask &= ~portirq_msk[port];
1890 sky2_write32(hw, B0_IMSK, imask);
1891 sky2_read32(hw, B0_IMSK);
1892
6c83504f
SH		 1893 synchronize_irq(hw->pdev->irq);
1894 napi_synchronize(&hw->napi);
1895
0da6d7b3 1896 spin_lock_bh(&sky2->phy_lock);
b96936da 1897 sky2_phy_power_down(hw, port);
0da6d7b3 1898 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1899
d571b694 1900 /* turn off LED's */
cd28ab6a
SH		 1901 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1902
264bb4fa
MM		 1903 sky2_tx_reset(hw, port);
1904
2bb8c262 1905 sky2_tx_clean(dev);
cd28ab6a
SH		 1906 sky2_rx_clean(sky2);
1907
1908 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1909 sky2->rx_le, sky2->rx_le_map);
1910 kfree(sky2->rx_ring);
1911
1912 pci_free_consistent(hw->pdev,
1913 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1914 sky2->tx_le, sky2->tx_le_map);
1915 kfree(sky2->tx_ring);
1916
1b537565
SH		 1917 sky2->tx_le = NULL;
1918 sky2->rx_le = NULL;
1919
1920 sky2->rx_ring = NULL;
1921 sky2->tx_ring = NULL;
1922
cd28ab6a
SH		 1923 return 0;
1924}
1925
1926static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1927{
ea76e635 1928 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1929 return SPEED_1000;
1930
05745c4a
SH		 1931 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1932 if (aux & PHY_M_PS_SPEED_100)
1933 return SPEED_100;
1934 else
1935 return SPEED_10;
1936 }
cd28ab6a
SH		 1937
1938 switch (aux & PHY_M_PS_SPEED_MSK) {
1939 case PHY_M_PS_SPEED_1000:
1940 return SPEED_1000;
1941 case PHY_M_PS_SPEED_100:
1942 return SPEED_100;
1943 default:
1944 return SPEED_10;
1945 }
1946}
1947
1948static void sky2_link_up(struct sky2_port *sky2)
1949{
1950 struct sky2_hw *hw = sky2->hw;
1951 unsigned port = sky2->port;
1952 u16 reg;
16ad91e1
SH		 1953 static const char *fc_name[] = {
1954 [FC_NONE] = "none",
1955 [FC_TX] = "tx",
1956 [FC_RX] = "rx",
1957 [FC_BOTH] = "both",
1958 };
cd28ab6a 1959
cd28ab6a 1960 /* enable Rx/Tx */
2eaba1a2 1961 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1962 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1963 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1964
1965 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1966
1967 netif_carrier_on(sky2->netdev);
cd28ab6a 1968
75e80683 1969 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1970
cd28ab6a 1971 /* Turn on link LED */
793b883e 1972 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1973 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1974
1975 if (netif_msg_link(sky2))
1976 printk(KERN_INFO PFX
d571b694 1977 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1978 sky2->netdev->name, sky2->speed,
1979 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1980 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1981}
1982
1983static void sky2_link_down(struct sky2_port *sky2)
1984{
1985 struct sky2_hw *hw = sky2->hw;
1986 unsigned port = sky2->port;
1987 u16 reg;
1988
1989 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1990
1991 reg = gma_read16(hw, port, GM_GP_CTRL);
1992 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1993 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1994
cd28ab6a 1995 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1996
1997 /* Turn on link LED */
1998 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1999
2000 if (netif_msg_link(sky2))
2001 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 2002
cd28ab6a
SH		 2003 sky2_phy_init(hw, port);
2004}
2005
16ad91e1
SH		 2006static enum flow_control sky2_flow(int rx, int tx)
2007{
2008 if (rx)
2009 return tx ? FC_BOTH : FC_RX;
2010 else
2011 return tx ? FC_TX : FC_NONE;
2012}
2013
793b883e
SH		 2014static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2015{
2016 struct sky2_hw *hw = sky2->hw;
2017 unsigned port = sky2->port;
da4c1ff4 2018 u16 advert, lpa;
793b883e 2019
da4c1ff4 2020 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2021 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2022 if (lpa & PHY_M_AN_RF) {
2023 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2024 return -1;
2025 }
2026
793b883e
SH		 2027 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2028 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2029 sky2->netdev->name);
2030 return -1;
2031 }
2032
793b883e 2033 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2034 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2035
da4c1ff4
SH		 2036 /* Since the pause result bits seem to in different positions on
2037 * different chips. look at registers.
2038 */
ea76e635 2039 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2040 /* Shift for bits in fiber PHY */
2041 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2042 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2043
2044 if (advert & ADVERTISE_1000XPAUSE)
2045 advert |= ADVERTISE_PAUSE_CAP;
2046 if (advert & ADVERTISE_1000XPSE_ASYM)
2047 advert |= ADVERTISE_PAUSE_ASYM;
2048 if (lpa & LPA_1000XPAUSE)
2049 lpa |= LPA_PAUSE_CAP;
2050 if (lpa & LPA_1000XPAUSE_ASYM)
2051 lpa |= LPA_PAUSE_ASYM;
2052 }
793b883e 2053
da4c1ff4
SH		 2054 sky2->flow_status = FC_NONE;
2055 if (advert & ADVERTISE_PAUSE_CAP) {
2056 if (lpa & LPA_PAUSE_CAP)
2057 sky2->flow_status = FC_BOTH;
2058 else if (advert & ADVERTISE_PAUSE_ASYM)
2059 sky2->flow_status = FC_RX;
2060 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2061 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2062 sky2->flow_status = FC_TX;
2063 }
793b883e 2064
16ad91e1 2065 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2066 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2067 sky2->flow_status = FC_NONE;
2eaba1a2 2068
da4c1ff4 2069 if (sky2->flow_status & FC_TX)
793b883e
SH		 2070 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2071 else
2072 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2073
2074 return 0;
2075}
cd28ab6a 2076
e07b1aa8
SH		 2077/* Interrupt from PHY */
2078static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2079{
e07b1aa8
SH		 2080 struct net_device *dev = hw->dev[port];
2081 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2082 u16 istatus, phystat;
2083
ebc646f6
SH		 2084 if (!netif_running(dev))
2085 return;
2086
e07b1aa8
SH		 2087 spin_lock(&sky2->phy_lock);
2088 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2089 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2090
cd28ab6a
SH		 2091 if (netif_msg_intr(sky2))
2092 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2093 sky2->netdev->name, istatus, phystat);
2094
2eaba1a2 2095 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 2096 if (sky2_autoneg_done(sky2, phystat) == 0)
2097 sky2_link_up(sky2);
2098 goto out;
2099 }
cd28ab6a 2100
793b883e
SH		 2101 if (istatus & PHY_M_IS_LSP_CHANGE)
2102 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2103
793b883e
SH		 2104 if (istatus & PHY_M_IS_DUP_CHANGE)
2105 sky2->duplex =
2106 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2107
793b883e
SH		 2108 if (istatus & PHY_M_IS_LST_CHANGE) {
2109 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2110 sky2_link_up(sky2);
793b883e
SH		 2111 else
2112 sky2_link_down(sky2);
cd28ab6a 2113 }
793b883e 2114out:
e07b1aa8 2115 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2116}
2117
62335ab0 2118/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2119 * and tx queue is full (stopped).
2120 */
cd28ab6a
SH		 2121static void sky2_tx_timeout(struct net_device *dev)
2122{
2123 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2124 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2125
2126 if (netif_msg_timer(sky2))
2127 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2128
8f24664d 2129 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2130 dev->name, sky2->tx_cons, sky2->tx_prod,
2131 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2132 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2133
81906791
SH		 2134 /* can't restart safely under softirq */
2135 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2136}
2137
2138static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2139{
6b1a3aef 2140 struct sky2_port *sky2 = netdev_priv(dev);
2141 struct sky2_hw *hw = sky2->hw;
b628ed98 2142 unsigned port = sky2->port;
6b1a3aef 2143 int err;
2144 u16 ctl, mode;
e07b1aa8 2145 u32 imask;
cd28ab6a
SH		 2146
2147 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2148 return -EINVAL;
2149
05745c4a
SH		 2150 if (new_mtu > ETH_DATA_LEN &&
2151 (hw->chip_id == CHIP_ID_YUKON_FE ||
2152 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2153 return -EINVAL;
2154
6b1a3aef 2155 if (!netif_running(dev)) {
2156 dev->mtu = new_mtu;
2157 return 0;
2158 }
2159
e07b1aa8 2160 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2161 sky2_write32(hw, B0_IMSK, 0);
2162
018d1c66 2163 dev->trans_start = jiffies; /* prevent tx timeout */
2164 netif_stop_queue(dev);
bea3348e 2165 napi_disable(&hw->napi);
018d1c66 2166
e07b1aa8
SH		 2167 synchronize_irq(hw->pdev->irq);
2168
39dbd958 2169 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2170 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2171
2172 ctl = gma_read16(hw, port, GM_GP_CTRL);
2173 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2174 sky2_rx_stop(sky2);
2175 sky2_rx_clean(sky2);
cd28ab6a
SH		 2176
2177 dev->mtu = new_mtu;
14d0263f 2178
6b1a3aef 2179 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2180 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2181
2182 if (dev->mtu > ETH_DATA_LEN)
2183 mode |= GM_SMOD_JUMBO_ENA;
2184
b628ed98 2185 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2186
b628ed98 2187 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2188
6b1a3aef 2189 err = sky2_rx_start(sky2);
e07b1aa8 2190 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2191
d1d08d12 2192 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2193 napi_enable(&hw->napi);
2194
1b537565
SH		 2195 if (err)
2196 dev_close(dev);
2197 else {
b628ed98 2198 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2199
1b537565
SH		 2200 netif_wake_queue(dev);
2201 }
2202
cd28ab6a
SH		 2203 return err;
2204}
2205
14d0263f
SH		 2206/* For small just reuse existing skb for next receive */
2207static struct sk_buff *receive_copy(struct sky2_port *sky2,
2208 const struct rx_ring_info *re,
2209 unsigned length)
2210{
2211 struct sk_buff *skb;
2212
2213 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2214 if (likely(skb)) {
2215 skb_reserve(skb, 2);
2216 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2217 length, PCI_DMA_FROMDEVICE);
d626f62b 2218 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2219 skb->ip_summed = re->skb->ip_summed;
2220 skb->csum = re->skb->csum;
2221 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2222 length, PCI_DMA_FROMDEVICE);
2223 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2224 skb_put(skb, length);
14d0263f
SH		 2225 }
2226 return skb;
2227}
2228
2229/* Adjust length of skb with fragments to match received data */
2230static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2231 unsigned int length)
2232{
2233 int i, num_frags;
2234 unsigned int size;
2235
2236 /* put header into skb */
2237 size = min(length, hdr_space);
2238 skb->tail += size;
2239 skb->len += size;
2240 length -= size;
2241
2242 num_frags = skb_shinfo(skb)->nr_frags;
2243 for (i = 0; i < num_frags; i++) {
2244 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2245
2246 if (length == 0) {
2247 /* don't need this page */
2248 __free_page(frag->page);
2249 --skb_shinfo(skb)->nr_frags;
2250 } else {
2251 size = min(length, (unsigned) PAGE_SIZE);
2252
2253 frag->size = size;
2254 skb->data_len += size;
2255 skb->truesize += size;
2256 skb->len += size;
2257 length -= size;
2258 }
2259 }
2260}
2261
2262/* Normal packet - take skb from ring element and put in a new one */
2263static struct sk_buff *receive_new(struct sky2_port *sky2,
2264 struct rx_ring_info *re,
2265 unsigned int length)
2266{
2267 struct sk_buff *skb, *nskb;
2268 unsigned hdr_space = sky2->rx_data_size;
2269
14d0263f
SH		 2270 /* Don't be tricky about reusing pages (yet) */
2271 nskb = sky2_rx_alloc(sky2);
2272 if (unlikely(!nskb))
2273 return NULL;
2274
2275 skb = re->skb;
2276 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2277
2278 prefetch(skb->data);
2279 re->skb = nskb;
454e6cb6
SH		 2280 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2281 dev_kfree_skb(nskb);
2282 re->skb = skb;
2283 return NULL;
2284 }
14d0263f
SH		 2285
2286 if (skb_shinfo(skb)->nr_frags)
2287 skb_put_frags(skb, hdr_space, length);
2288 else
489b10c1 2289 skb_put(skb, length);
14d0263f
SH		 2290 return skb;
2291}
2292
cd28ab6a
SH		 2293/*
2294 * Receive one packet.
d571b694 2295 * For larger packets, get new buffer.
cd28ab6a 2296 */
497d7c86 2297static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2298 u16 length, u32 status)
2299{
497d7c86 2300 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2301 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2302 struct sk_buff *skb = NULL;
d6532232
SH		 2303 u16 count = (status & GMR_FS_LEN) >> 16;
2304
2305#ifdef SKY2_VLAN_TAG_USED
2306 /* Account for vlan tag */
2307 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2308 count -= VLAN_HLEN;
2309#endif
cd28ab6a
SH		 2310
2311 if (unlikely(netif_msg_rx_status(sky2)))
2312 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2313 dev->name, sky2->rx_next, status, length);
cd28ab6a 2314
793b883e 2315 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2316 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2317
3b12e014
SH		 2318 /* This chip has hardware problems that generates bogus status.
2319 * So do only marginal checking and expect higher level protocols
2320 * to handle crap frames.
2321 */
2322 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2323 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2324 length != count)
2325 goto okay;
2326
42eeea01 2327 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2328 goto error;
2329
42eeea01 2330 if (!(status & GMR_FS_RX_OK))
2331 goto resubmit;
2332
d6532232
SH		 2333 /* if length reported by DMA does not match PHY, packet was truncated */
2334 if (length != count)
3b12e014 2335 goto len_error;
71749531 2336
3b12e014 2337okay:
14d0263f
SH		 2338 if (length < copybreak)
2339 skb = receive_copy(sky2, re, length);
2340 else
2341 skb = receive_new(sky2, re, length);
793b883e 2342resubmit:
14d0263f 2343 sky2_rx_submit(sky2, re);
79e57d32 2344
cd28ab6a
SH		 2345 return skb;
2346
3b12e014 2347len_error:
71749531
SH		 2348 /* Truncation of overlength packets
2349 causes PHY length to not match MAC length */
7138a0f5 2350 ++dev->stats.rx_length_errors;
d6532232 2351 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2352 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2353 dev->name, status, length);
d6532232 2354 goto resubmit;
71749531 2355
cd28ab6a 2356error:
7138a0f5 2357 ++dev->stats.rx_errors;
b6d77734 2358 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2359 dev->stats.rx_over_errors++;
b6d77734
SH		 2360 goto resubmit;
2361 }
6e15b712 2362
3be92a70 2363 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2364 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2365 dev->name, status, length);
793b883e
SH		 2366
2367 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2368 dev->stats.rx_length_errors++;
cd28ab6a 2369 if (status & GMR_FS_FRAGMENT)
7138a0f5 2370 dev->stats.rx_frame_errors++;
cd28ab6a 2371 if (status & GMR_FS_CRC_ERR)
7138a0f5 2372 dev->stats.rx_crc_errors++;
79e57d32 2373
793b883e 2374 goto resubmit;
cd28ab6a
SH		 2375}
2376
e07b1aa8
SH		 2377/* Transmit complete */
2378static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2379{
e07b1aa8 2380 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2381
f6caa14a 2382 if (likely(netif_running(dev) && !sky2->restarting)) {
2bb8c262 2383 netif_tx_lock(dev);
e07b1aa8 2384 sky2_tx_complete(sky2, last);
2bb8c262 2385 netif_tx_unlock(dev);
2224795d 2386 }
cd28ab6a
SH		 2387}
2388
37e5a243
SH		 2389static inline void sky2_skb_rx(const struct sky2_port *sky2,
2390 u32 status, struct sk_buff *skb)
2391{
2392#ifdef SKY2_VLAN_TAG_USED
2393 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2394 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2395 if (skb->ip_summed == CHECKSUM_NONE)
2396 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2397 else
2398 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2399 vlan_tag, skb);
2400 return;
2401 }
2402#endif
2403 if (skb->ip_summed == CHECKSUM_NONE)
2404 netif_receive_skb(skb);
2405 else
2406 napi_gro_receive(&sky2->hw->napi, skb);
2407}
2408
bf15fe99
SH		 2409static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2410 unsigned packets, unsigned bytes)
2411{
2412 if (packets) {
2413 struct net_device *dev = hw->dev[port];
2414
2415 dev->stats.rx_packets += packets;
2416 dev->stats.rx_bytes += bytes;
2417 dev->last_rx = jiffies;
2418 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2419 }
2420}
2421
e07b1aa8 2422/* Process status response ring */
26691830 2423static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2424{
e07b1aa8 2425 int work_done = 0;
bf15fe99
SH		 2426 unsigned int total_bytes[2] = { 0 };
2427 unsigned int total_packets[2] = { 0 };
a8fd6266 2428
af2a58ac 2429 rmb();
26691830 2430 do {
55c9dd35 2431 struct sky2_port *sky2;
13210ce5 2432 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2433 unsigned port;
13210ce5 2434 struct net_device *dev;
cd28ab6a 2435 struct sk_buff *skb;
cd28ab6a
SH		 2436 u32 status;
2437 u16 length;
ab5adecb
SH		 2438 u8 opcode = le->opcode;
2439
2440 if (!(opcode & HW_OWNER))
2441 break;
cd28ab6a 2442
cb5d9547 2443 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2444
ab5adecb 2445 port = le->css & CSS_LINK_BIT;
69161611 2446 dev = hw->dev[port];
13210ce5 2447 sky2 = netdev_priv(dev);
f65b138c
SH		 2448 length = le16_to_cpu(le->length);
2449 status = le32_to_cpu(le->status);
cd28ab6a 2450
ab5adecb
SH		 2451 le->opcode = 0;
2452 switch (opcode & ~HW_OWNER) {
cd28ab6a 2453 case OP_RXSTAT:
bf15fe99
SH		 2454 total_packets[port]++;
2455 total_bytes[port] += length;
497d7c86 2456 skb = sky2_receive(dev, length, status);
3225b919 2457 if (unlikely(!skb)) {
7138a0f5 2458 dev->stats.rx_dropped++;
55c9dd35 2459 break;
3225b919 2460 }
13210ce5 2461
69161611 2462 /* This chip reports checksum status differently */
05745c4a 2463 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2464 if (sky2->rx_csum &&
2465 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2466 (le->css & CSS_TCPUDPCSOK))
2467 skb->ip_summed = CHECKSUM_UNNECESSARY;
2468 else
2469 skb->ip_summed = CHECKSUM_NONE;
2470 }
2471
13210ce5 2472 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2473
37e5a243 2474 sky2_skb_rx(sky2, status, skb);
13210ce5 2475
22e11703 2476 /* Stop after net poll weight */
13210ce5 2477 if (++work_done >= to_do)
2478 goto exit_loop;
cd28ab6a
SH		 2479 break;
2480
d1f13708 2481#ifdef SKY2_VLAN_TAG_USED
2482 case OP_RXVLAN:
2483 sky2->rx_tag = length;
2484 break;
2485
2486 case OP_RXCHKSVLAN:
2487 sky2->rx_tag = length;
2488 /* fall through */
2489#endif
cd28ab6a 2490 case OP_RXCHKS:
87418307
SH		 2491 if (!sky2->rx_csum)
2492 break;
2493
05745c4a
SH		 2494 /* If this happens then driver assuming wrong format */
2495 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2496 if (net_ratelimit())
2497 printk(KERN_NOTICE "%s: unexpected"
2498 " checksum status\n",
2499 dev->name);
69161611 2500 break;
05745c4a 2501 }
69161611 2502
87418307
SH		 2503 /* Both checksum counters are programmed to start at
2504 * the same offset, so unless there is a problem they
2505 * should match. This failure is an early indication that
2506 * hardware receive checksumming won't work.
2507 */
2508 if (likely(status >> 16 == (status & 0xffff))) {
2509 skb = sky2->rx_ring[sky2->rx_next].skb;
2510 skb->ip_summed = CHECKSUM_COMPLETE;
b9389796 2511 skb->csum = le16_to_cpu(status);
87418307
SH		 2512 } else {
2513 printk(KERN_NOTICE PFX "%s: hardware receive "
2514 "checksum problem (status = %#x)\n",
2515 dev->name, status);
2516 sky2->rx_csum = 0;
2517 sky2_write32(sky2->hw,
69161611 2518 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2519 BMU_DIS_RX_CHKSUM);
2520 }
cd28ab6a
SH		 2521 break;
2522
2523 case OP_TXINDEXLE:
13b97b74 2524 /* TX index reports status for both ports */
f55925d7
SH		 2525 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2526 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2527 if (hw->dev[1])
2528 sky2_tx_done(hw->dev[1],
2529 ((status >> 24) & 0xff)
2530 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2531 break;
2532
cd28ab6a
SH		 2533 default:
2534 if (net_ratelimit())
793b883e 2535 printk(KERN_WARNING PFX
ab5adecb 2536 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2537 }
26691830 2538 } while (hw->st_idx != idx);
cd28ab6a 2539
fe2a24df
SH		 2540 /* Fully processed status ring so clear irq */
2541 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2542
13210ce5 2543exit_loop:
bf15fe99
SH		 2544 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2545 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2546
e07b1aa8 2547 return work_done;
cd28ab6a
SH		 2548}
2549
2550static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2551{
2552 struct net_device *dev = hw->dev[port];
2553
3be92a70
SH		 2554 if (net_ratelimit())
2555 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2556 dev->name, status);
cd28ab6a
SH		 2557
2558 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2559 if (net_ratelimit())
2560 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2561 dev->name);
cd28ab6a
SH		 2562 /* Clear IRQ */
2563 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2564 }
2565
2566 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2567 if (net_ratelimit())
2568 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2569 dev->name);
cd28ab6a
SH		 2570
2571 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2572 }
2573
2574 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2575 if (net_ratelimit())
2576 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2577 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2578 }
2579
2580 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2581 if (net_ratelimit())
2582 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2583 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2584 }
2585
2586 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2587 if (net_ratelimit())
2588 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2589 dev->name);
cd28ab6a
SH		 2590 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2591 }
2592}
2593
2594static void sky2_hw_intr(struct sky2_hw *hw)
2595{
555382cb 2596 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2597 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2598 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2599
2600 status &= hwmsk;
cd28ab6a 2601
793b883e 2602 if (status & Y2_IS_TIST_OV)
cd28ab6a 2603 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2604
2605 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2606 u16 pci_err;
2607
82637e80 2608 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2609 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2610 if (net_ratelimit())
555382cb 2611 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2612 pci_err);
cd28ab6a 2613
b32f40c4 2614 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2615 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2616 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2617 }
2618
2619 if (status & Y2_IS_PCI_EXP) {
d571b694 2620 /* PCI-Express uncorrectable Error occurred */
555382cb 2621 u32 err;
cd28ab6a 2622
82637e80 2623 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2624 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2625 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2626 0xfffffffful);
3be92a70 2627 if (net_ratelimit())
555382cb 2628 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2629
7782c8c4 2630 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2631 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2632 }
2633
2634 if (status & Y2_HWE_L1_MASK)
2635 sky2_hw_error(hw, 0, status);
2636 status >>= 8;
2637 if (status & Y2_HWE_L1_MASK)
2638 sky2_hw_error(hw, 1, status);
2639}
2640
2641static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2642{
2643 struct net_device *dev = hw->dev[port];
2644 struct sky2_port *sky2 = netdev_priv(dev);
2645 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2646
2647 if (netif_msg_intr(sky2))
2648 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2649 dev->name, status);
2650
a3caeada
SH		 2651 if (status & GM_IS_RX_CO_OV)
2652 gma_read16(hw, port, GM_RX_IRQ_SRC);
2653
2654 if (status & GM_IS_TX_CO_OV)
2655 gma_read16(hw, port, GM_TX_IRQ_SRC);
2656
cd28ab6a 2657 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2658 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2659 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2660 }
2661
2662 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2663 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2664 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2665 }
cd28ab6a
SH		 2666}
2667
40b01727
SH		 2668/* This should never happen it is a bug. */
2669static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2670 u16 q, unsigned ring_size)
d257924e
SH		 2671{
2672 struct net_device *dev = hw->dev[port];
2673 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2674 unsigned idx;
2675 const u64 *le = (q == Q_R1 || q == Q_R2)
2676 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2677
40b01727
SH		 2678 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2679 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2680 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2681 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2682
40b01727 2683 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2684}
cd28ab6a 2685
75e80683
SH		 2686static int sky2_rx_hung(struct net_device *dev)
2687{
2688 struct sky2_port *sky2 = netdev_priv(dev);
2689 struct sky2_hw *hw = sky2->hw;
2690 unsigned port = sky2->port;
2691 unsigned rxq = rxqaddr[port];
2692 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2693 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2694 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2695 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2696
2697 /* If idle and MAC or PCI is stuck */
2698 if (sky2->check.last == dev->last_rx &&
2699 ((mac_rp == sky2->check.mac_rp &&
2700 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2701 /* Check if the PCI RX hang */
2702 (fifo_rp == sky2->check.fifo_rp &&
2703 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2704 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2705 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2706 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2707 return 1;
2708 } else {
2709 sky2->check.last = dev->last_rx;
2710 sky2->check.mac_rp = mac_rp;
2711 sky2->check.mac_lev = mac_lev;
2712 sky2->check.fifo_rp = fifo_rp;
2713 sky2->check.fifo_lev = fifo_lev;
2714 return 0;
2715 }
2716}
2717
32c2c300 2718static void sky2_watchdog(unsigned long arg)
d27ed387 2719{
01bd7564 2720 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2721
75e80683 2722 /* Check for lost IRQ once a second */
32c2c300 2723 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2724 napi_schedule(&hw->napi);
75e80683
SH		 2725 } else {
2726 int i, active = 0;
2727
2728 for (i = 0; i < hw->ports; i++) {
bea3348e 2729 struct net_device *dev = hw->dev[i];
75e80683
SH		 2730 if (!netif_running(dev))
2731 continue;
2732 ++active;
2733
2734 /* For chips with Rx FIFO, check if stuck */
39dbd958 2735 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2736 sky2_rx_hung(dev)) {
2737 pr_info(PFX "%s: receiver hang detected\n",
2738 dev->name);
2739 schedule_work(&hw->restart_work);
2740 return;
2741 }
2742 }
2743
2744 if (active == 0)
2745 return;
32c2c300 2746 }
01bd7564 2747
75e80683 2748 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2749}
2750
40b01727
SH		 2751/* Hardware/software error handling */
2752static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2753{
40b01727
SH		 2754 if (net_ratelimit())
2755 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2756
1e5f1283
SH		 2757 if (status & Y2_IS_HW_ERR)
2758 sky2_hw_intr(hw);
d257924e 2759
1e5f1283
SH		 2760 if (status & Y2_IS_IRQ_MAC1)
2761 sky2_mac_intr(hw, 0);
cd28ab6a 2762
1e5f1283
SH		 2763 if (status & Y2_IS_IRQ_MAC2)
2764 sky2_mac_intr(hw, 1);
cd28ab6a 2765
1e5f1283 2766 if (status & Y2_IS_CHK_RX1)
40b01727 2767 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2768
1e5f1283 2769 if (status & Y2_IS_CHK_RX2)
40b01727 2770 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2771
1e5f1283 2772 if (status & Y2_IS_CHK_TXA1)
40b01727 2773 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2774
1e5f1283 2775 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2776 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2777}
2778
bea3348e 2779static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2780{
bea3348e 2781 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2782 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2783 int work_done = 0;
26691830 2784 u16 idx;
40b01727
SH		 2785
2786 if (unlikely(status & Y2_IS_ERROR))
2787 sky2_err_intr(hw, status);
2788
2789 if (status & Y2_IS_IRQ_PHY1)
2790 sky2_phy_intr(hw, 0);
2791
2792 if (status & Y2_IS_IRQ_PHY2)
2793 sky2_phy_intr(hw, 1);
cd28ab6a 2794
26691830
SH		 2795 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2796 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2797
2798 if (work_done >= work_limit)
26691830
SH		 2799 goto done;
2800 }
6f535763 2801
26691830
SH		 2802 napi_complete(napi);
2803 sky2_read32(hw, B0_Y2_SP_LISR);
2804done:
6f535763 2805
bea3348e 2806 return work_done;
e07b1aa8
SH		 2807}
2808
7d12e780 2809static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2810{
2811 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2812 u32 status;
2813
2814 /* Reading this mask interrupts as side effect */
2815 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2816 if (status == 0 || status == ~0)
2817 return IRQ_NONE;
793b883e 2818
e07b1aa8 2819 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2820
2821 napi_schedule(&hw->napi);
793b883e 2822
cd28ab6a
SH		 2823 return IRQ_HANDLED;
2824}
2825
2826#ifdef CONFIG_NET_POLL_CONTROLLER
2827static void sky2_netpoll(struct net_device *dev)
2828{
2829 struct sky2_port *sky2 = netdev_priv(dev);
2830
bea3348e 2831 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2832}
2833#endif
2834
2835/* Chip internal frequency for clock calculations */
05745c4a 2836static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2837{
793b883e 2838 switch (hw->chip_id) {
cd28ab6a 2839 case CHIP_ID_YUKON_EC:
5a5b1ea0 2840 case CHIP_ID_YUKON_EC_U:
93745494 2841 case CHIP_ID_YUKON_EX:
ed4d4161 2842 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2843 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2844 return 125;
2845
cd28ab6a 2846 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2847 return 100;
2848
2849 case CHIP_ID_YUKON_FE_P:
2850 return 50;
2851
2852 case CHIP_ID_YUKON_XL:
2853 return 156;
2854
2855 default:
2856 BUG();
cd28ab6a
SH		 2857 }
2858}
2859
fb17358f 2860static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2861{
fb17358f 2862 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2863}
2864
fb17358f 2865static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2866{
fb17358f 2867 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2868}
2869
fb17358f 2870
e3173832 2871static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2872{
b89165f2 2873 u8 t8;
cd28ab6a 2874
167f53d0 2875 /* Enable all clocks and check for bad PCI access */
b32f40c4 2876 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2877
cd28ab6a 2878 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2879
cd28ab6a 2880 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2881 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2882
2883 switch(hw->chip_id) {
2884 case CHIP_ID_YUKON_XL:
39dbd958 2885 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2886 break;
2887
2888 case CHIP_ID_YUKON_EC_U:
2889 hw->flags = SKY2_HW_GIGABIT
2890 | SKY2_HW_NEWER_PHY
2891 | SKY2_HW_ADV_POWER_CTL;
2892 break;
2893
2894 case CHIP_ID_YUKON_EX:
2895 hw->flags = SKY2_HW_GIGABIT
2896 | SKY2_HW_NEWER_PHY
2897 | SKY2_HW_NEW_LE
2898 | SKY2_HW_ADV_POWER_CTL;
2899
2900 /* New transmit checksum */
2901 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2902 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2903 break;
2904
2905 case CHIP_ID_YUKON_EC:
2906 /* This rev is really old, and requires untested workarounds */
2907 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2908 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2909 return -EOPNOTSUPP;
2910 }
39dbd958 2911 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2912 break;
2913
2914 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2915 break;
2916
05745c4a
SH		 2917 case CHIP_ID_YUKON_FE_P:
2918 hw->flags = SKY2_HW_NEWER_PHY
2919 | SKY2_HW_NEW_LE
2920 | SKY2_HW_AUTO_TX_SUM
2921 | SKY2_HW_ADV_POWER_CTL;
2922 break;
ed4d4161
SH		 2923
2924 case CHIP_ID_YUKON_SUPR:
2925 hw->flags = SKY2_HW_GIGABIT
2926 | SKY2_HW_NEWER_PHY
2927 | SKY2_HW_NEW_LE
2928 | SKY2_HW_AUTO_TX_SUM
2929 | SKY2_HW_ADV_POWER_CTL;
2930 break;
2931
0ce8b98d
SH		 2932 case CHIP_ID_YUKON_UL_2:
2933 hw->flags = SKY2_HW_GIGABIT
2934 | SKY2_HW_ADV_POWER_CTL;
2935 break;
2936
ea76e635 2937 default:
b02a9258
SH		 2938 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2939 hw->chip_id);
cd28ab6a
SH		 2940 return -EOPNOTSUPP;
2941 }
2942
ea76e635
SH		 2943 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2944 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2945 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2946
e3173832
SH		 2947 hw->ports = 1;
2948 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2949 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2950 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2951 ++hw->ports;
2952 }
2953
2954 return 0;
2955}
2956
2957static void sky2_reset(struct sky2_hw *hw)
2958{
555382cb 2959 struct pci_dev *pdev = hw->pdev;
e3173832 2960 u16 status;
555382cb
SH		 2961 int i, cap;
2962 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2963
cd28ab6a 2964 /* disable ASF */
4f44d8ba
SH		 2965 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2966 status = sky2_read16(hw, HCU_CCSR);
2967 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2968 HCU_CCSR_UC_STATE_MSK);
2969 sky2_write16(hw, HCU_CCSR, status);
2970 } else
2971 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2972 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2973
2974 /* do a SW reset */
2975 sky2_write8(hw, B0_CTST, CS_RST_SET);
2976 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2977
ac93a394
SH		 2978 /* allow writes to PCI config */
2979 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2980
cd28ab6a 2981 /* clear PCI errors, if any */
b32f40c4 2982 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2983 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2984 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2985
2986 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2987
555382cb
SH		 2988 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2989 if (cap) {
7782c8c4
SH		 2990 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2991 0xfffffffful);
555382cb
SH		 2992
2993 /* If error bit is stuck on ignore it */
2994 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2995 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2996 else
555382cb
SH		 2997 hwe_mask |= Y2_IS_PCI_EXP;
2998 }
cd28ab6a 2999
ae306cca 3000 sky2_power_on(hw);
82637e80 3001 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3002
3003 for (i = 0; i < hw->ports; i++) {
3004 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3005 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3006
ed4d4161
SH		 3007 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3008 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3009 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3010 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3011 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 3012 }
3013
793b883e
SH		 3014 /* Clear I2C IRQ noise */
3015 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3016
3017 /* turn off hardware timer (unused) */
3018 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3019 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3020
cd28ab6a
SH		 3021 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
3022
69634ee7
SH		 3023 /* Turn off descriptor polling */
3024 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3025
3026 /* Turn off receive timestamp */
3027 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3028 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3029
3030 /* enable the Tx Arbiters */
3031 for (i = 0; i < hw->ports; i++)
3032 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3033
3034 /* Initialize ram interface */
3035 for (i = 0; i < hw->ports; i++) {
793b883e 3036 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3037
3038 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3039 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3040 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3041 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3042 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3043 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3044 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3045 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3046 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3047 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3048 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3049 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3050 }
3051
555382cb 3052 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3053
cd28ab6a 3054 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3055 sky2_gmac_reset(hw, i);
cd28ab6a 3056
cd28ab6a
SH		 3057 memset(hw->st_le, 0, STATUS_LE_BYTES);
3058 hw->st_idx = 0;
3059
3060 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3061 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3062
3063 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3064 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3065
3066 /* Set the list last index */
793b883e 3067 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3068
290d4de5
SH		 3069 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3070 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3071
290d4de5
SH		 3072 /* set Status-FIFO ISR watermark */
3073 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3074 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3075 else
3076 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3077
290d4de5 3078 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3079 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3080 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3081
793b883e 3082 /* enable status unit */
cd28ab6a
SH		 3083 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3084
3085 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3086 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3087 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3088}
3089
81906791
SH		 3090static void sky2_restart(struct work_struct *work)
3091{
3092 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3093 struct net_device *dev;
3094 int i, err;
3095
81906791 3096 rtnl_lock();
81906791
SH		 3097 for (i = 0; i < hw->ports; i++) {
3098 dev = hw->dev[i];
3099 if (netif_running(dev))
3100 sky2_down(dev);
3101 }
3102
8cfcbe99
SH		 3103 napi_disable(&hw->napi);
3104 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3105 sky2_reset(hw);
3106 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3107 napi_enable(&hw->napi);
81906791
SH		 3108
3109 for (i = 0; i < hw->ports; i++) {
3110 dev = hw->dev[i];
3111 if (netif_running(dev)) {
3112 err = sky2_up(dev);
3113 if (err) {
3114 printk(KERN_INFO PFX "%s: could not restart %d\n",
3115 dev->name, err);
3116 dev_close(dev);
3117 }
3118 }
3119 }
3120
81906791
SH		 3121 rtnl_unlock();
3122}
3123
e3173832
SH		 3124static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3125{
3126 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3127}
3128
3129static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3130{
3131 const struct sky2_port *sky2 = netdev_priv(dev);
3132
3133 wol->supported = sky2_wol_supported(sky2->hw);
3134 wol->wolopts = sky2->wol;
3135}
3136
3137static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3138{
3139 struct sky2_port *sky2 = netdev_priv(dev);
3140 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3141
9d731d77
RW		 3142 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3143 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3144 return -EOPNOTSUPP;
3145
3146 sky2->wol = wol->wolopts;
3147
05745c4a
SH		 3148 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3149 hw->chip_id == CHIP_ID_YUKON_EX ||
3150 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3151 sky2_write32(hw, B0_CTST, sky2->wol
3152 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3153
9d731d77
RW		 3154 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3155
e3173832
SH		 3156 if (!netif_running(dev))
3157 sky2_wol_init(sky2);
cd28ab6a
SH		 3158 return 0;
3159}
3160
28bd181a 3161static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3162{
b89165f2
SH		 3163 if (sky2_is_copper(hw)) {
3164 u32 modes = SUPPORTED_10baseT_Half
3165 | SUPPORTED_10baseT_Full
3166 | SUPPORTED_100baseT_Half
3167 | SUPPORTED_100baseT_Full
3168 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3169
ea76e635 3170 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3171 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3172 | SUPPORTED_1000baseT_Full;
3173 return modes;
cd28ab6a 3174 } else
b89165f2
SH		 3175 return SUPPORTED_1000baseT_Half
3176 | SUPPORTED_1000baseT_Full
3177 | SUPPORTED_Autoneg
3178 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3179}
3180
793b883e 3181static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3182{
3183 struct sky2_port *sky2 = netdev_priv(dev);
3184 struct sky2_hw *hw = sky2->hw;
3185
3186 ecmd->transceiver = XCVR_INTERNAL;
3187 ecmd->supported = sky2_supported_modes(hw);
3188 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3189 if (sky2_is_copper(hw)) {
cd28ab6a 3190 ecmd->port = PORT_TP;
b89165f2
SH		 3191 ecmd->speed = sky2->speed;
3192 } else {
3193 ecmd->speed = SPEED_1000;
cd28ab6a 3194 ecmd->port = PORT_FIBRE;
b89165f2 3195 }
cd28ab6a
SH		 3196
3197 ecmd->advertising = sky2->advertising;
3198 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3199 ecmd->duplex = sky2->duplex;
3200 return 0;
3201}
3202
3203static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3204{
3205 struct sky2_port *sky2 = netdev_priv(dev);
3206 const struct sky2_hw *hw = sky2->hw;
3207 u32 supported = sky2_supported_modes(hw);
3208
3209 if (ecmd->autoneg == AUTONEG_ENABLE) {
3210 ecmd->advertising = supported;
3211 sky2->duplex = -1;
3212 sky2->speed = -1;
3213 } else {
3214 u32 setting;
3215
793b883e 3216 switch (ecmd->speed) {
cd28ab6a
SH		 3217 case SPEED_1000:
3218 if (ecmd->duplex == DUPLEX_FULL)
3219 setting = SUPPORTED_1000baseT_Full;
3220 else if (ecmd->duplex == DUPLEX_HALF)
3221 setting = SUPPORTED_1000baseT_Half;
3222 else
3223 return -EINVAL;
3224 break;
3225 case SPEED_100:
3226 if (ecmd->duplex == DUPLEX_FULL)
3227 setting = SUPPORTED_100baseT_Full;
3228 else if (ecmd->duplex == DUPLEX_HALF)
3229 setting = SUPPORTED_100baseT_Half;
3230 else
3231 return -EINVAL;
3232 break;
3233
3234 case SPEED_10:
3235 if (ecmd->duplex == DUPLEX_FULL)
3236 setting = SUPPORTED_10baseT_Full;
3237 else if (ecmd->duplex == DUPLEX_HALF)
3238 setting = SUPPORTED_10baseT_Half;
3239 else
3240 return -EINVAL;
3241 break;
3242 default:
3243 return -EINVAL;
3244 }
3245
3246 if ((setting & supported) == 0)
3247 return -EINVAL;
3248
3249 sky2->speed = ecmd->speed;
3250 sky2->duplex = ecmd->duplex;
3251 }
3252
3253 sky2->autoneg = ecmd->autoneg;
3254 sky2->advertising = ecmd->advertising;
3255
d1b139c0 3256 if (netif_running(dev)) {
1b537565 3257 sky2_phy_reinit(sky2);
d1b139c0
SH		 3258 sky2_set_multicast(dev);
3259 }
cd28ab6a
SH		 3260
3261 return 0;
3262}
3263
3264static void sky2_get_drvinfo(struct net_device *dev,
3265 struct ethtool_drvinfo *info)
3266{
3267 struct sky2_port *sky2 = netdev_priv(dev);
3268
3269 strcpy(info->driver, DRV_NAME);
3270 strcpy(info->version, DRV_VERSION);
3271 strcpy(info->fw_version, "N/A");
3272 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3273}
3274
3275static const struct sky2_stat {
793b883e
SH		 3276 char name[ETH_GSTRING_LEN];
3277 u16 offset;
cd28ab6a
SH		 3278} sky2_stats[] = {
3279 { "tx_bytes", GM_TXO_OK_HI },
3280 { "rx_bytes", GM_RXO_OK_HI },
3281 { "tx_broadcast", GM_TXF_BC_OK },
3282 { "rx_broadcast", GM_RXF_BC_OK },
3283 { "tx_multicast", GM_TXF_MC_OK },
3284 { "rx_multicast", GM_RXF_MC_OK },
3285 { "tx_unicast", GM_TXF_UC_OK },
3286 { "rx_unicast", GM_RXF_UC_OK },
3287 { "tx_mac_pause", GM_TXF_MPAUSE },
3288 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3289 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3290 { "late_collision",GM_TXF_LAT_COL },
3291 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3292 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3293 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3294
d2604540 3295 { "rx_short", GM_RXF_SHT },
cd28ab6a 3296 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3297 { "rx_64_byte_packets", GM_RXF_64B },
3298 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3299 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3300 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3301 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3302 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3303 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3304 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3305 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3306 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3307 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3308
3309 { "tx_64_byte_packets", GM_TXF_64B },
3310 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3311 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3312 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3313 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3314 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3315 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3316 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3317};
3318
cd28ab6a
SH		 3319static u32 sky2_get_rx_csum(struct net_device *dev)
3320{
3321 struct sky2_port *sky2 = netdev_priv(dev);
3322
3323 return sky2->rx_csum;
3324}
3325
3326static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3327{
3328 struct sky2_port *sky2 = netdev_priv(dev);
3329
3330 sky2->rx_csum = data;
793b883e 3331
cd28ab6a
SH		 3332 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3333 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3334
3335 return 0;
3336}
3337
3338static u32 sky2_get_msglevel(struct net_device *netdev)
3339{
3340 struct sky2_port *sky2 = netdev_priv(netdev);
3341 return sky2->msg_enable;
3342}
3343
9a7ae0a9
SH		 3344static int sky2_nway_reset(struct net_device *dev)
3345{
3346 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3347
16ad91e1 3348 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3349 return -EINVAL;
3350
1b537565 3351 sky2_phy_reinit(sky2);
d1b139c0 3352 sky2_set_multicast(dev);
9a7ae0a9
SH		 3353
3354 return 0;
3355}
3356
793b883e 3357static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3358{
3359 struct sky2_hw *hw = sky2->hw;
3360 unsigned port = sky2->port;
3361 int i;
3362
3363 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3364 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3365 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3366 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3367
793b883e 3368 for (i = 2; i < count; i++)
cd28ab6a
SH		 3369 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3370}
3371
cd28ab6a
SH		 3372static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3373{
3374 struct sky2_port *sky2 = netdev_priv(netdev);
3375 sky2->msg_enable = value;
3376}
3377
b9f2c044 3378static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3379{
b9f2c044
JG		 3380 switch (sset) {
3381 case ETH_SS_STATS:
3382 return ARRAY_SIZE(sky2_stats);
3383 default:
3384 return -EOPNOTSUPP;
3385 }
cd28ab6a
SH		 3386}
3387
3388static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3389 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3390{
3391 struct sky2_port *sky2 = netdev_priv(dev);
3392
793b883e 3393 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3394}
3395
793b883e 3396static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3397{
3398 int i;
3399
3400 switch (stringset) {
3401 case ETH_SS_STATS:
3402 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3403 memcpy(data + i * ETH_GSTRING_LEN,
3404 sky2_stats[i].name, ETH_GSTRING_LEN);
3405 break;
3406 }
3407}
3408
cd28ab6a
SH		 3409static int sky2_set_mac_address(struct net_device *dev, void *p)
3410{
3411 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3412 struct sky2_hw *hw = sky2->hw;
3413 unsigned port = sky2->port;
3414 const struct sockaddr *addr = p;
cd28ab6a
SH		 3415
3416 if (!is_valid_ether_addr(addr->sa_data))
3417 return -EADDRNOTAVAIL;
3418
cd28ab6a 3419 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3420 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3421 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3422 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3423 dev->dev_addr, ETH_ALEN);
1b537565 3424
a8ab1ec0
SH		 3425 /* virtual address for data */
3426 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3427
3428 /* physical address: used for pause frames */
3429 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3430
3431 return 0;
cd28ab6a
SH		 3432}
3433
a052b52f
SH		 3434static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3435{
3436 u32 bit;
3437
3438 bit = ether_crc(ETH_ALEN, addr) & 63;
3439 filter[bit >> 3] |= 1 << (bit & 7);
3440}
3441
cd28ab6a
SH		 3442static void sky2_set_multicast(struct net_device *dev)
3443{
3444 struct sky2_port *sky2 = netdev_priv(dev);
3445 struct sky2_hw *hw = sky2->hw;
3446 unsigned port = sky2->port;
3447 struct dev_mc_list *list = dev->mc_list;
3448 u16 reg;
3449 u8 filter[8];
a052b52f
SH		 3450 int rx_pause;
3451 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3452
a052b52f 3453 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3454 memset(filter, 0, sizeof(filter));
3455
3456 reg = gma_read16(hw, port, GM_RX_CTRL);
3457 reg |= GM_RXCR_UCF_ENA;
3458
d571b694 3459 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3460 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3461 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3462 memset(filter, 0xff, sizeof(filter));
a052b52f 3463 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3464 reg &= ~GM_RXCR_MCF_ENA;
3465 else {
3466 int i;
3467 reg |= GM_RXCR_MCF_ENA;
3468
a052b52f
SH		 3469 if (rx_pause)
3470 sky2_add_filter(filter, pause_mc_addr);
3471
3472 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3473 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3474 }
3475
cd28ab6a 3476 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3477 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3478 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3479 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3480 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3481 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3482 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3483 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3484
3485 gma_write16(hw, port, GM_RX_CTRL, reg);
3486}
3487
3488/* Can have one global because blinking is controlled by
3489 * ethtool and that is always under RTNL mutex
3490 */
a84d0a3d 3491static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3492{
a84d0a3d
SH		 3493 struct sky2_hw *hw = sky2->hw;
3494 unsigned port = sky2->port;
793b883e 3495
a84d0a3d
SH		 3496 spin_lock_bh(&sky2->phy_lock);
3497 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3498 hw->chip_id == CHIP_ID_YUKON_EX ||
3499 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3500 u16 pg;
793b883e
SH		 3501 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3503
a84d0a3d
SH		 3504 switch (mode) {
3505 case MO_LED_OFF:
3506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3507 PHY_M_LEDC_LOS_CTRL(8) |
3508 PHY_M_LEDC_INIT_CTRL(8) |
3509 PHY_M_LEDC_STA1_CTRL(8) |
3510 PHY_M_LEDC_STA0_CTRL(8));
3511 break;
3512 case MO_LED_ON:
3513 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3514 PHY_M_LEDC_LOS_CTRL(9) |
3515 PHY_M_LEDC_INIT_CTRL(9) |
3516 PHY_M_LEDC_STA1_CTRL(9) |
3517 PHY_M_LEDC_STA0_CTRL(9));
3518 break;
3519 case MO_LED_BLINK:
3520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3521 PHY_M_LEDC_LOS_CTRL(0xa) |
3522 PHY_M_LEDC_INIT_CTRL(0xa) |
3523 PHY_M_LEDC_STA1_CTRL(0xa) |
3524 PHY_M_LEDC_STA0_CTRL(0xa));
3525 break;
3526 case MO_LED_NORM:
3527 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3528 PHY_M_LEDC_LOS_CTRL(1) |
3529 PHY_M_LEDC_INIT_CTRL(8) |
3530 PHY_M_LEDC_STA1_CTRL(7) |
3531 PHY_M_LEDC_STA0_CTRL(7));
3532 }
793b883e 3533
a84d0a3d
SH		 3534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3535 } else
7d2e3cb7 3536 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3537 PHY_M_LED_MO_DUP(mode) |
3538 PHY_M_LED_MO_10(mode) |
3539 PHY_M_LED_MO_100(mode) |
3540 PHY_M_LED_MO_1000(mode) |
3541 PHY_M_LED_MO_RX(mode) |
3542 PHY_M_LED_MO_TX(mode));
3543
3544 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3545}
3546
3547/* blink LED's for finding board */
3548static int sky2_phys_id(struct net_device *dev, u32 data)
3549{
3550 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3551 unsigned int i;
cd28ab6a 3552
a84d0a3d
SH		 3553 if (data == 0)
3554 data = UINT_MAX;
cd28ab6a 3555
a84d0a3d
SH		 3556 for (i = 0; i < data; i++) {
3557 sky2_led(sky2, MO_LED_ON);
3558 if (msleep_interruptible(500))
3559 break;
3560 sky2_led(sky2, MO_LED_OFF);
3561 if (msleep_interruptible(500))
3562 break;
793b883e 3563 }
a84d0a3d 3564 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3565
3566 return 0;
3567}
3568
3569static void sky2_get_pauseparam(struct net_device *dev,
3570 struct ethtool_pauseparam *ecmd)
3571{
3572 struct sky2_port *sky2 = netdev_priv(dev);
3573
16ad91e1
SH		 3574 switch (sky2->flow_mode) {
3575 case FC_NONE:
3576 ecmd->tx_pause = ecmd->rx_pause = 0;
3577 break;
3578 case FC_TX:
3579 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3580 break;
3581 case FC_RX:
3582 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3583 break;
3584 case FC_BOTH:
3585 ecmd->tx_pause = ecmd->rx_pause = 1;
3586 }
3587
cd28ab6a
SH		 3588 ecmd->autoneg = sky2->autoneg;
3589}
3590
3591static int sky2_set_pauseparam(struct net_device *dev,
3592 struct ethtool_pauseparam *ecmd)
3593{
3594 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3595
3596 sky2->autoneg = ecmd->autoneg;
16ad91e1 3597 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3598
16ad91e1
SH		 3599 if (netif_running(dev))
3600 sky2_phy_reinit(sky2);
cd28ab6a 3601
2eaba1a2 3602 return 0;
cd28ab6a
SH		 3603}
3604
fb17358f
SH		 3605static int sky2_get_coalesce(struct net_device *dev,
3606 struct ethtool_coalesce *ecmd)
3607{
3608 struct sky2_port *sky2 = netdev_priv(dev);
3609 struct sky2_hw *hw = sky2->hw;
3610
3611 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3612 ecmd->tx_coalesce_usecs = 0;
3613 else {
3614 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3615 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3616 }
3617 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3618
3619 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3620 ecmd->rx_coalesce_usecs = 0;
3621 else {
3622 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3623 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3624 }
3625 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3626
3627 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3628 ecmd->rx_coalesce_usecs_irq = 0;
3629 else {
3630 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3631 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3632 }
3633
3634 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3635
3636 return 0;
3637}
3638
3639/* Note: this affect both ports */
3640static int sky2_set_coalesce(struct net_device *dev,
3641 struct ethtool_coalesce *ecmd)
3642{
3643 struct sky2_port *sky2 = netdev_priv(dev);
3644 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3645 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3646
77b3d6a2
SH		 3647 if (ecmd->tx_coalesce_usecs > tmax ||
3648 ecmd->rx_coalesce_usecs > tmax ||
3649 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3650 return -EINVAL;
3651
ff81fbbe 3652 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3653 return -EINVAL;
ff81fbbe 3654 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3655 return -EINVAL;
ff81fbbe 3656 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3657 return -EINVAL;
3658
3659 if (ecmd->tx_coalesce_usecs == 0)
3660 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3661 else {
3662 sky2_write32(hw, STAT_TX_TIMER_INI,
3663 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3664 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3665 }
3666 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3667
3668 if (ecmd->rx_coalesce_usecs == 0)
3669 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3670 else {
3671 sky2_write32(hw, STAT_LEV_TIMER_INI,
3672 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3673 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3674 }
3675 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3676
3677 if (ecmd->rx_coalesce_usecs_irq == 0)
3678 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3679 else {
d28d4870 3680 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3681 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3682 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3683 }
3684 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3685 return 0;
3686}
3687
793b883e
SH		 3688static void sky2_get_ringparam(struct net_device *dev,
3689 struct ethtool_ringparam *ering)
3690{
3691 struct sky2_port *sky2 = netdev_priv(dev);
3692
3693 ering->rx_max_pending = RX_MAX_PENDING;
3694 ering->rx_mini_max_pending = 0;
3695 ering->rx_jumbo_max_pending = 0;
3696 ering->tx_max_pending = TX_RING_SIZE - 1;
3697
3698 ering->rx_pending = sky2->rx_pending;
3699 ering->rx_mini_pending = 0;
3700 ering->rx_jumbo_pending = 0;
3701 ering->tx_pending = sky2->tx_pending;
3702}
3703
3704static int sky2_set_ringparam(struct net_device *dev,
3705 struct ethtool_ringparam *ering)
3706{
3707 struct sky2_port *sky2 = netdev_priv(dev);
3708 int err = 0;
3709
3710 if (ering->rx_pending > RX_MAX_PENDING ||
3711 ering->rx_pending < 8 ||
3712 ering->tx_pending < MAX_SKB_TX_LE ||
3713 ering->tx_pending > TX_RING_SIZE - 1)
3714 return -EINVAL;
3715
3716 if (netif_running(dev))
3717 sky2_down(dev);
3718
3719 sky2->rx_pending = ering->rx_pending;
3720 sky2->tx_pending = ering->tx_pending;
3721
1b537565 3722 if (netif_running(dev)) {
793b883e 3723 err = sky2_up(dev);
1b537565
SH		 3724 if (err)
3725 dev_close(dev);
3726 }
793b883e
SH		 3727
3728 return err;
3729}
3730
793b883e
SH		 3731static int sky2_get_regs_len(struct net_device *dev)
3732{
6e4cbb34 3733 return 0x4000;
793b883e
SH		 3734}
3735
3736/*
3737 * Returns copy of control register region
3ead5db7 3738 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3739 */
3740static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3741 void *p)
3742{
3743 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3744 const void __iomem *io = sky2->hw->regs;
295b54c4 3745 unsigned int b;
793b883e
SH		 3746
3747 regs->version = 1;
793b883e 3748
295b54c4
SH		 3749 for (b = 0; b < 128; b++) {
3750 /* This complicated switch statement is to make sure and
3751 * only access regions that are unreserved.
3752 * Some blocks are only valid on dual port cards.
3753 * and block 3 has some special diagnostic registers that
3754 * are poison.
3755 */
3756 switch (b) {
3757 case 3:
3758 /* skip diagnostic ram region */
3759 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3760 break;
3ead5db7 3761
295b54c4
SH		 3762 /* dual port cards only */
3763 case 5: /* Tx Arbiter 2 */
3764 case 9: /* RX2 */
3765 case 14 ... 15: /* TX2 */
3766 case 17: case 19: /* Ram Buffer 2 */
3767 case 22 ... 23: /* Tx Ram Buffer 2 */
3768 case 25: /* Rx MAC Fifo 1 */
3769 case 27: /* Tx MAC Fifo 2 */
3770 case 31: /* GPHY 2 */
3771 case 40 ... 47: /* Pattern Ram 2 */
3772 case 52: case 54: /* TCP Segmentation 2 */
3773 case 112 ... 116: /* GMAC 2 */
3774 if (sky2->hw->ports == 1)
3775 goto reserved;
3776 /* fall through */
3777 case 0: /* Control */
3778 case 2: /* Mac address */
3779 case 4: /* Tx Arbiter 1 */
3780 case 7: /* PCI express reg */
3781 case 8: /* RX1 */
3782 case 12 ... 13: /* TX1 */
3783 case 16: case 18:/* Rx Ram Buffer 1 */
3784 case 20 ... 21: /* Tx Ram Buffer 1 */
3785 case 24: /* Rx MAC Fifo 1 */
3786 case 26: /* Tx MAC Fifo 1 */
3787 case 28 ... 29: /* Descriptor and status unit */
3788 case 30: /* GPHY 1*/
3789 case 32 ... 39: /* Pattern Ram 1 */
3790 case 48: case 50: /* TCP Segmentation 1 */
3791 case 56 ... 60: /* PCI space */
3792 case 80 ... 84: /* GMAC 1 */
3793 memcpy_fromio(p, io, 128);
3794 break;
3795 default:
3796reserved:
3797 memset(p, 0, 128);
3798 }
3ead5db7 3799
295b54c4
SH		 3800 p += 128;
3801 io += 128;
3802 }
793b883e 3803}
cd28ab6a 3804
b628ed98
SH		 3805/* In order to do Jumbo packets on these chips, need to turn off the
3806 * transmit store/forward. Therefore checksum offload won't work.
3807 */
3808static int no_tx_offload(struct net_device *dev)
3809{
3810 const struct sky2_port *sky2 = netdev_priv(dev);
3811 const struct sky2_hw *hw = sky2->hw;
3812
69161611 3813 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3814}
3815
3816static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3817{
3818 if (data && no_tx_offload(dev))
3819 return -EINVAL;
3820
3821 return ethtool_op_set_tx_csum(dev, data);
3822}
3823
3824
3825static int sky2_set_tso(struct net_device *dev, u32 data)
3826{
3827 if (data && no_tx_offload(dev))
3828 return -EINVAL;
3829
3830 return ethtool_op_set_tso(dev, data);
3831}
3832
f4331a6d
SH		 3833static int sky2_get_eeprom_len(struct net_device *dev)
3834{
3835 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3836 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3837 u16 reg2;
3838
b32f40c4 3839 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3840 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3841}
3842
1413235c 3843static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3844{
1413235c 3845 unsigned long start = jiffies;
f4331a6d 3846
1413235c
SH		 3847 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3848 /* Can take up to 10.6 ms for write */
3849 if (time_after(jiffies, start + HZ/4)) {
3850 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3851 return -ETIMEDOUT;
3852 }
3853 mdelay(1);
3854 }
167f53d0 3855
1413235c
SH		 3856 return 0;
3857}
167f53d0 3858
1413235c
SH		 3859static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3860 u16 offset, size_t length)
3861{
3862 int rc = 0;
3863
3864 while (length > 0) {
3865 u32 val;
3866
3867 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3868 rc = sky2_vpd_wait(hw, cap, 0);
3869 if (rc)
3870 break;
3871
3872 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3873
3874 memcpy(data, &val, min(sizeof(val), length));
3875 offset += sizeof(u32);
3876 data += sizeof(u32);
3877 length -= sizeof(u32);
3878 }
3879
3880 return rc;
f4331a6d
SH		 3881}
3882
1413235c
SH		 3883static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3884 u16 offset, unsigned int length)
f4331a6d 3885{
1413235c
SH		 3886 unsigned int i;
3887 int rc = 0;
3888
3889 for (i = 0; i < length; i += sizeof(u32)) {
3890 u32 val = *(u32 *)(data + i);
3891
3892 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3893 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3894
3895 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3896 if (rc)
3897 break;
3898 }
3899 return rc;
f4331a6d
SH		 3900}
3901
3902static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3903 u8 *data)
3904{
3905 struct sky2_port *sky2 = netdev_priv(dev);
3906 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3907
3908 if (!cap)
3909 return -EINVAL;
3910
3911 eeprom->magic = SKY2_EEPROM_MAGIC;
3912
1413235c 3913 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3914}
3915
3916static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3917 u8 *data)
3918{
3919 struct sky2_port *sky2 = netdev_priv(dev);
3920 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3921
3922 if (!cap)
3923 return -EINVAL;
3924
3925 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3926 return -EINVAL;
3927
1413235c
SH		 3928 /* Partial writes not supported */
3929 if ((eeprom->offset & 3) || (eeprom->len & 3))
3930 return -EINVAL;
f4331a6d 3931
1413235c 3932 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3933}
3934
3935
7282d491 3936static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3937 .get_settings = sky2_get_settings,
3938 .set_settings = sky2_set_settings,
3939 .get_drvinfo = sky2_get_drvinfo,
3940 .get_wol = sky2_get_wol,
3941 .set_wol = sky2_set_wol,
3942 .get_msglevel = sky2_get_msglevel,
3943 .set_msglevel = sky2_set_msglevel,
3944 .nway_reset = sky2_nway_reset,
3945 .get_regs_len = sky2_get_regs_len,
3946 .get_regs = sky2_get_regs,
3947 .get_link = ethtool_op_get_link,
3948 .get_eeprom_len = sky2_get_eeprom_len,
3949 .get_eeprom = sky2_get_eeprom,
3950 .set_eeprom = sky2_set_eeprom,
f4331a6d 3951 .set_sg = ethtool_op_set_sg,
f4331a6d 3952 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3953 .set_tso = sky2_set_tso,
3954 .get_rx_csum = sky2_get_rx_csum,
3955 .set_rx_csum = sky2_set_rx_csum,
3956 .get_strings = sky2_get_strings,
3957 .get_coalesce = sky2_get_coalesce,
3958 .set_coalesce = sky2_set_coalesce,
3959 .get_ringparam = sky2_get_ringparam,
3960 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3961 .get_pauseparam = sky2_get_pauseparam,
3962 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3963 .phys_id = sky2_phys_id,
b9f2c044 3964 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3965 .get_ethtool_stats = sky2_get_ethtool_stats,
3966};
3967
3cf26753
SH		 3968#ifdef CONFIG_SKY2_DEBUG
3969
3970static struct dentry *sky2_debug;
3971
e4c2abe2
SH		 3972
3973/*
3974 * Read and parse the first part of Vital Product Data
3975 */
3976#define VPD_SIZE 128
3977#define VPD_MAGIC 0x82
3978
3979static const struct vpd_tag {
3980 char tag[2];
3981 char *label;
3982} vpd_tags[] = {
3983 { "PN", "Part Number" },
3984 { "EC", "Engineering Level" },
3985 { "MN", "Manufacturer" },
3986 { "SN", "Serial Number" },
3987 { "YA", "Asset Tag" },
3988 { "VL", "First Error Log Message" },
3989 { "VF", "Second Error Log Message" },
3990 { "VB", "Boot Agent ROM Configuration" },
3991 { "VE", "EFI UNDI Configuration" },
3992};
3993
3994static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3995{
3996 size_t vpd_size;
3997 loff_t offs;
3998 u8 len;
3999 unsigned char *buf;
4000 u16 reg2;
4001
4002 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4003 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4004
4005 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4006 buf = kmalloc(vpd_size, GFP_KERNEL);
4007 if (!buf) {
4008 seq_puts(seq, "no memory!\n");
4009 return;
4010 }
4011
4012 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4013 seq_puts(seq, "VPD read failed\n");
4014 goto out;
4015 }
4016
4017 if (buf[0] != VPD_MAGIC) {
4018 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4019 goto out;
4020 }
4021 len = buf[1];
4022 if (len == 0 || len > vpd_size - 4) {
4023 seq_printf(seq, "Invalid id length: %d\n", len);
4024 goto out;
4025 }
4026
4027 seq_printf(seq, "%.*s\n", len, buf + 3);
4028 offs = len + 3;
4029
4030 while (offs < vpd_size - 4) {
4031 int i;
4032
4033 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4034 break;
4035 len = buf[offs + 2];
4036 if (offs + len + 3 >= vpd_size)
4037 break;
4038
4039 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4040 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4041 seq_printf(seq, " %s: %.*s\n",
4042 vpd_tags[i].label, len, buf + offs + 3);
4043 break;
4044 }
4045 }
4046 offs += len + 3;
4047 }
4048out:
4049 kfree(buf);
4050}
4051
3cf26753
SH		 4052static int sky2_debug_show(struct seq_file *seq, void *v)
4053{
4054 struct net_device *dev = seq->private;
4055 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4056 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4057 unsigned port = sky2->port;
4058 unsigned idx, last;
4059 int sop;
4060
e4c2abe2 4061 sky2_show_vpd(seq, hw);
3cf26753 4062
e4c2abe2 4063 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4064 sky2_read32(hw, B0_ISRC),
4065 sky2_read32(hw, B0_IMSK),
4066 sky2_read32(hw, B0_Y2_SP_ICR));
4067
e4c2abe2
SH		 4068 if (!netif_running(dev)) {
4069 seq_printf(seq, "network not running\n");
4070 return 0;
4071 }
4072
bea3348e 4073 napi_disable(&hw->napi);
3cf26753
SH		 4074 last = sky2_read16(hw, STAT_PUT_IDX);
4075
4076 if (hw->st_idx == last)
4077 seq_puts(seq, "Status ring (empty)\n");
4078 else {
4079 seq_puts(seq, "Status ring\n");
4080 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4081 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4082 const struct sky2_status_le *le = hw->st_le + idx;
4083 seq_printf(seq, "[%d] %#x %d %#x\n",
4084 idx, le->opcode, le->length, le->status);
4085 }
4086 seq_puts(seq, "\n");
4087 }
4088
4089 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4090 sky2->tx_cons, sky2->tx_prod,
4091 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4092 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4093
4094 /* Dump contents of tx ring */
4095 sop = 1;
4096 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4097 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4098 const struct sky2_tx_le *le = sky2->tx_le + idx;
4099 u32 a = le32_to_cpu(le->addr);
4100
4101 if (sop)
4102 seq_printf(seq, "%u:", idx);
4103 sop = 0;
4104
4105 switch(le->opcode & ~HW_OWNER) {
4106 case OP_ADDR64:
4107 seq_printf(seq, " %#x:", a);
4108 break;
4109 case OP_LRGLEN:
4110 seq_printf(seq, " mtu=%d", a);
4111 break;
4112 case OP_VLAN:
4113 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4114 break;
4115 case OP_TCPLISW:
4116 seq_printf(seq, " csum=%#x", a);
4117 break;
4118 case OP_LARGESEND:
4119 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4120 break;
4121 case OP_PACKET:
4122 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4123 break;
4124 case OP_BUFFER:
4125 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4126 break;
4127 default:
4128 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4129 a, le16_to_cpu(le->length));
4130 }
4131
4132 if (le->ctrl & EOP) {
4133 seq_putc(seq, '\n');
4134 sop = 1;
4135 }
4136 }
4137
4138 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4139 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4140 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4141 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4142
d1d08d12 4143 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4144 napi_enable(&hw->napi);
3cf26753
SH		 4145 return 0;
4146}
4147
4148static int sky2_debug_open(struct inode *inode, struct file *file)
4149{
4150 return single_open(file, sky2_debug_show, inode->i_private);
4151}
4152
4153static const struct file_operations sky2_debug_fops = {
4154 .owner = THIS_MODULE,
4155 .open = sky2_debug_open,
4156 .read = seq_read,
4157 .llseek = seq_lseek,
4158 .release = single_release,
4159};
4160
4161/*
4162 * Use network device events to create/remove/rename
4163 * debugfs file entries
4164 */
4165static int sky2_device_event(struct notifier_block *unused,
4166 unsigned long event, void *ptr)
4167{
4168 struct net_device *dev = ptr;
5b296bc9 4169 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4170
1436b301 4171 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4172 return NOTIFY_DONE;
3cf26753 4173
5b296bc9
SH		 4174 switch(event) {
4175 case NETDEV_CHANGENAME:
4176 if (sky2->debugfs) {
4177 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4178 sky2_debug, dev->name);
4179 }
4180 break;
3cf26753 4181
5b296bc9
SH		 4182 case NETDEV_GOING_DOWN:
4183 if (sky2->debugfs) {
4184 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4185 dev->name);
4186 debugfs_remove(sky2->debugfs);
4187 sky2->debugfs = NULL;
3cf26753 4188 }
5b296bc9
SH		 4189 break;
4190
4191 case NETDEV_UP:
4192 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4193 sky2_debug, dev,
4194 &sky2_debug_fops);
4195 if (IS_ERR(sky2->debugfs))
4196 sky2->debugfs = NULL;
3cf26753
SH		 4197 }
4198
4199 return NOTIFY_DONE;
4200}
4201
4202static struct notifier_block sky2_notifier = {
4203 .notifier_call = sky2_device_event,
4204};
4205
4206
4207static __init void sky2_debug_init(void)
4208{
4209 struct dentry *ent;
4210
4211 ent = debugfs_create_dir("sky2", NULL);
4212 if (!ent || IS_ERR(ent))
4213 return;
4214
4215 sky2_debug = ent;
4216 register_netdevice_notifier(&sky2_notifier);
4217}
4218
4219static __exit void sky2_debug_cleanup(void)
4220{
4221 if (sky2_debug) {
4222 unregister_netdevice_notifier(&sky2_notifier);
4223 debugfs_remove(sky2_debug);
4224 sky2_debug = NULL;
4225 }
4226}
4227
4228#else
4229#define sky2_debug_init()
4230#define sky2_debug_cleanup()
4231#endif
4232
1436b301
SH		 4233/* Two copies of network device operations to handle special case of
4234 not allowing netpoll on second port */
4235static const struct net_device_ops sky2_netdev_ops[2] = {
4236 {
4237 .ndo_open = sky2_up,
4238 .ndo_stop = sky2_down,
00829823 4239 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4240 .ndo_do_ioctl = sky2_ioctl,
4241 .ndo_validate_addr = eth_validate_addr,
4242 .ndo_set_mac_address = sky2_set_mac_address,
4243 .ndo_set_multicast_list = sky2_set_multicast,
4244 .ndo_change_mtu = sky2_change_mtu,
4245 .ndo_tx_timeout = sky2_tx_timeout,
4246#ifdef SKY2_VLAN_TAG_USED
4247 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4248#endif
4249#ifdef CONFIG_NET_POLL_CONTROLLER
4250 .ndo_poll_controller = sky2_netpoll,
4251#endif
4252 },
4253 {
4254 .ndo_open = sky2_up,
4255 .ndo_stop = sky2_down,
00829823 4256 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4257 .ndo_do_ioctl = sky2_ioctl,
4258 .ndo_validate_addr = eth_validate_addr,
4259 .ndo_set_mac_address = sky2_set_mac_address,
4260 .ndo_set_multicast_list = sky2_set_multicast,
4261 .ndo_change_mtu = sky2_change_mtu,
4262 .ndo_tx_timeout = sky2_tx_timeout,
4263#ifdef SKY2_VLAN_TAG_USED
4264 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4265#endif
4266 },
4267};
3cf26753 4268
cd28ab6a
SH		 4269/* Initialize network device */
4270static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4271 unsigned port,
be63a21c 4272 int highmem, int wol)
cd28ab6a
SH		 4273{
4274 struct sky2_port *sky2;
4275 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4276
4277 if (!dev) {
898eb71c 4278 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4279 return NULL;
4280 }
4281
cd28ab6a 4282 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4283 dev->irq = hw->pdev->irq;
cd28ab6a 4284 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4285 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4286 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4287
4288 sky2 = netdev_priv(dev);
4289 sky2->netdev = dev;
4290 sky2->hw = hw;
4291 sky2->msg_enable = netif_msg_init(debug, default_msg);
4292
cd28ab6a
SH		 4293 /* Auto speed and flow control */
4294 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4295 sky2->flow_mode = FC_BOTH;
4296
cd28ab6a
SH		 4297 sky2->duplex = -1;
4298 sky2->speed = -1;
4299 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4300 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4301 sky2->wol = wol;
75d070c5 4302
e07b1aa8 4303 spin_lock_init(&sky2->phy_lock);
793b883e 4304 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4305 sky2->rx_pending = RX_DEF_PENDING;
f6caa14a 4306 sky2->restarting = 0;
cd28ab6a
SH		 4307
4308 hw->dev[port] = dev;
4309
4310 sky2->port = port;
4311
4a50a876 4312 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4313 if (highmem)
4314 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4315
d1f13708 4316#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4317 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4318 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4319 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4320 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4321 }
d1f13708 4322#endif
4323
cd28ab6a 4324 /* read the mac address */
793b883e 4325 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4326 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4327
cd28ab6a
SH		 4328 return dev;
4329}
4330
28bd181a 4331static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4332{
4333 const struct sky2_port *sky2 = netdev_priv(dev);
4334
4335 if (netif_msg_probe(sky2))
e174961c
JB		 4336 printk(KERN_INFO PFX "%s: addr %pM\n",
4337 dev->name, dev->dev_addr);
cd28ab6a
SH		 4338}
4339
fb2690a9 4340/* Handle software interrupt used during MSI test */
7d12e780 4341static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4342{
4343 struct sky2_hw *hw = dev_id;
4344 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4345
4346 if (status == 0)
4347 return IRQ_NONE;
4348
4349 if (status & Y2_IS_IRQ_SW) {
ea76e635 4350 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4351 wake_up(&hw->msi_wait);
4352 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4353 }
4354 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4355
4356 return IRQ_HANDLED;
4357}
4358
4359/* Test interrupt path by forcing a a software IRQ */
4360static int __devinit sky2_test_msi(struct sky2_hw *hw)
4361{
4362 struct pci_dev *pdev = hw->pdev;
4363 int err;
4364
bb507fe1 4365 init_waitqueue_head (&hw->msi_wait);
4366
fb2690a9
SH		 4367 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4368
b0a20ded 4369 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4370 if (err) {
b02a9258 4371 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4372 return err;
4373 }
4374
fb2690a9 4375 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4376 sky2_read8(hw, B0_CTST);
fb2690a9 4377
ea76e635 4378 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4379
ea76e635 4380 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4381 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4382 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4383 "switching to INTx mode.\n");
fb2690a9
SH		 4384
4385 err = -EOPNOTSUPP;
4386 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4387 }
4388
4389 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4390 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4391
4392 free_irq(pdev->irq, hw);
4393
4394 return err;
4395}
4396
c7127a34
SH		 4397/* This driver supports yukon2 chipset only */
4398static const char *sky2_name(u8 chipid, char *buf, int sz)
4399{
4400 const char *name[] = {
4401 "XL", /* 0xb3 */
4402 "EC Ultra", /* 0xb4 */
4403 "Extreme", /* 0xb5 */
4404 "EC", /* 0xb6 */
4405 "FE", /* 0xb7 */
4406 "FE+", /* 0xb8 */
4407 "Supreme", /* 0xb9 */
0ce8b98d 4408 "UL 2", /* 0xba */
c7127a34
SH		 4409 };
4410
0ce8b98d 4411 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4412 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4413 else
4414 snprintf(buf, sz, "(chip %#x)", chipid);
4415 return buf;
4416}
4417
cd28ab6a
SH		 4418static int __devinit sky2_probe(struct pci_dev *pdev,
4419 const struct pci_device_id *ent)
4420{
7f60c64b 4421 struct net_device *dev;
cd28ab6a 4422 struct sky2_hw *hw;
be63a21c 4423 int err, using_dac = 0, wol_default;
3834507d 4424 u32 reg;
c7127a34 4425 char buf1[16];
cd28ab6a 4426
793b883e
SH		 4427 err = pci_enable_device(pdev);
4428 if (err) {
b02a9258 4429 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4430 goto err_out;
4431 }
4432
6cc90a5a
SH		 4433 /* Get configuration information
4434 * Note: only regular PCI config access once to test for HW issues
4435 * other PCI access through shared memory for speed and to
4436 * avoid MMCONFIG problems.
4437 */
4438 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4439 if (err) {
4440 dev_err(&pdev->dev, "PCI read config failed\n");
4441 goto err_out;
4442 }
4443
4444 if (~reg == 0) {
4445 dev_err(&pdev->dev, "PCI configuration read error\n");
4446 goto err_out;
4447 }
4448
793b883e
SH		 4449 err = pci_request_regions(pdev, DRV_NAME);
4450 if (err) {
b02a9258 4451 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4452 goto err_out_disable;
cd28ab6a
SH		 4453 }
4454
4455 pci_set_master(pdev);
4456
d1f3d4dd 4457 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4458 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4459 using_dac = 1;
6a35528a 4460 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4461 if (err < 0) {
b02a9258
SH		 4462 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4463 "for consistent allocations\n");
d1f3d4dd
SH		 4464 goto err_out_free_regions;
4465 }
d1f3d4dd 4466 } else {
284901a9 4467 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4468 if (err) {
b02a9258 4469 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4470 goto err_out_free_regions;
4471 }
4472 }
d1f3d4dd 4473
3834507d
SH		 4474
4475#ifdef __BIG_ENDIAN
4476 /* The sk98lin vendor driver uses hardware byte swapping but
4477 * this driver uses software swapping.
4478 */
4479 reg &= ~PCI_REV_DESC;
4480 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4481 if (err) {
4482 dev_err(&pdev->dev, "PCI write config failed\n");
4483 goto err_out_free_regions;
4484 }
4485#endif
4486
9d731d77 4487 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4488
cd28ab6a 4489 err = -ENOMEM;
6aad85d6 4490 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4491 if (!hw) {
b02a9258 4492 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4493 goto err_out_free_regions;
4494 }
4495
cd28ab6a 4496 hw->pdev = pdev;
cd28ab6a
SH		 4497
4498 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4499 if (!hw->regs) {
b02a9258 4500 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4501 goto err_out_free_hw;
4502 }
4503
08c06d8a 4504 /* ring for status responses */
167f53d0 4505 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4506 if (!hw->st_le)
4507 goto err_out_iounmap;
4508
e3173832 4509 err = sky2_init(hw);
cd28ab6a 4510 if (err)
793b883e 4511 goto err_out_iounmap;
cd28ab6a 4512
c844d483
SH		 4513 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4514 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4515
e3173832
SH		 4516 sky2_reset(hw);
4517
be63a21c 4518 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4519 if (!dev) {
4520 err = -ENOMEM;
cd28ab6a 4521 goto err_out_free_pci;
7f60c64b 4522 }
cd28ab6a 4523
9fa1b1f3
SH		 4524 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4525 err = sky2_test_msi(hw);
4526 if (err == -EOPNOTSUPP)
4527 pci_disable_msi(pdev);
4528 else if (err)
4529 goto err_out_free_netdev;
4530 }
4531
793b883e
SH		 4532 err = register_netdev(dev);
4533 if (err) {
b02a9258 4534 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4535 goto err_out_free_netdev;
4536 }
4537
6de16237
SH		 4538 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4539
ea76e635
SH		 4540 err = request_irq(pdev->irq, sky2_intr,
4541 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4542 dev->name, hw);
9fa1b1f3 4543 if (err) {
b02a9258 4544 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4545 goto err_out_unregister;
4546 }
4547 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4548 napi_enable(&hw->napi);
9fa1b1f3 4549
cd28ab6a
SH		 4550 sky2_show_addr(dev);
4551
7f60c64b 4552 if (hw->ports > 1) {
4553 struct net_device *dev1;
4554
be63a21c 4555 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4556 if (!dev1)
4557 dev_warn(&pdev->dev, "allocation for second device failed\n");
4558 else if ((err = register_netdev(dev1))) {
4559 dev_warn(&pdev->dev,
4560 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4561 hw->dev[1] = NULL;
4562 free_netdev(dev1);
b02a9258
SH		 4563 } else
4564 sky2_show_addr(dev1);
cd28ab6a
SH		 4565 }
4566
32c2c300 4567 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4568 INIT_WORK(&hw->restart_work, sky2_restart);
4569
793b883e
SH		 4570 pci_set_drvdata(pdev, hw);
4571
cd28ab6a
SH		 4572 return 0;
4573
793b883e 4574err_out_unregister:
ea76e635 4575 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4576 pci_disable_msi(pdev);
793b883e 4577 unregister_netdev(dev);
cd28ab6a
SH		 4578err_out_free_netdev:
4579 free_netdev(dev);
cd28ab6a 4580err_out_free_pci:
793b883e 4581 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4582 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4583err_out_iounmap:
4584 iounmap(hw->regs);
4585err_out_free_hw:
4586 kfree(hw);
4587err_out_free_regions:
4588 pci_release_regions(pdev);
44a1d2e5 4589err_out_disable:
cd28ab6a 4590 pci_disable_device(pdev);
cd28ab6a 4591err_out:
549a68c3 4592 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4593 return err;
4594}
4595
4596static void __devexit sky2_remove(struct pci_dev *pdev)
4597{
793b883e 4598 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4599 int i;
cd28ab6a 4600
793b883e 4601 if (!hw)
cd28ab6a
SH		 4602 return;
4603
32c2c300 4604 del_timer_sync(&hw->watchdog_timer);
6de16237 4605 cancel_work_sync(&hw->restart_work);
d27ed387 4606
b877fe28 4607 for (i = hw->ports-1; i >= 0; --i)
6de16237 4608 unregister_netdev(hw->dev[i]);
81906791 4609
d27ed387 4610 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4611
ae306cca
SH		 4612 sky2_power_aux(hw);
4613
cd28ab6a 4614 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4615 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4616 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4617
4618 free_irq(pdev->irq, hw);
ea76e635 4619 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4620 pci_disable_msi(pdev);
793b883e 4621 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4622 pci_release_regions(pdev);
4623 pci_disable_device(pdev);
793b883e 4624
b877fe28 4625 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4626 free_netdev(hw->dev[i]);
4627
cd28ab6a
SH		 4628 iounmap(hw->regs);
4629 kfree(hw);
5afa0a9c 4630
cd28ab6a
SH		 4631 pci_set_drvdata(pdev, NULL);
4632}
4633
4634#ifdef CONFIG_PM
4635static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4636{
793b883e 4637 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4638 int i, wol = 0;
cd28ab6a 4639
549a68c3
SH		 4640 if (!hw)
4641 return 0;
4642
063a0b38
SH		 4643 del_timer_sync(&hw->watchdog_timer);
4644 cancel_work_sync(&hw->restart_work);
4645
f05267e7 4646 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4647 struct net_device *dev = hw->dev[i];
e3173832 4648 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4649
063a0b38 4650 netif_device_detach(dev);
e3173832 4651 if (netif_running(dev))
5afa0a9c 4652 sky2_down(dev);
e3173832
SH		 4653
4654 if (sky2->wol)
4655 sky2_wol_init(sky2);
4656
4657 wol |= sky2->wol;
cd28ab6a
SH		 4658 }
4659
8ab8fca2 4660 sky2_write32(hw, B0_IMSK, 0);
6de16237 4661 napi_disable(&hw->napi);
ae306cca 4662 sky2_power_aux(hw);
e3173832 4663
d374c1c1 4664 pci_save_state(pdev);
e3173832 4665 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4666 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4667
2ccc99b7 4668 return 0;
cd28ab6a
SH		 4669}
4670
4671static int sky2_resume(struct pci_dev *pdev)
4672{
793b883e 4673 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4674 int i, err;
cd28ab6a 4675
549a68c3
SH		 4676 if (!hw)
4677 return 0;
4678
f71eb1a2
SH		 4679 err = pci_set_power_state(pdev, PCI_D0);
4680 if (err)
4681 goto out;
ae306cca
SH		 4682
4683 err = pci_restore_state(pdev);
4684 if (err)
4685 goto out;
4686
cd28ab6a 4687 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4688
4689 /* Re-enable all clocks */
05745c4a
SH		 4690 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4691 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4692 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4693 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4694
e3173832 4695 sky2_reset(hw);
8ab8fca2 4696 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4697 napi_enable(&hw->napi);
8ab8fca2 4698
f05267e7 4699 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4700 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4701
4702 netif_device_attach(dev);
6a5706b9 4703 if (netif_running(dev)) {
08c06d8a
SH		 4704 err = sky2_up(dev);
4705 if (err) {
4706 printk(KERN_ERR PFX "%s: could not up: %d\n",
4707 dev->name, err);
68c28898 4708 rtnl_lock();
08c06d8a 4709 dev_close(dev);
68c28898 4710 rtnl_unlock();
eb35cf60 4711 goto out;
5afa0a9c 4712 }
cd28ab6a
SH		 4713 }
4714 }
eb35cf60 4715
ae306cca 4716 return 0;
08c06d8a 4717out:
b02a9258 4718 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4719 pci_disable_device(pdev);
08c06d8a 4720 return err;
cd28ab6a
SH		 4721}
4722#endif
4723
e3173832
SH		 4724static void sky2_shutdown(struct pci_dev *pdev)
4725{
4726 struct sky2_hw *hw = pci_get_drvdata(pdev);
4727 int i, wol = 0;
4728
549a68c3
SH		 4729 if (!hw)
4730 return;
4731
5c0d6b34 4732 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4733
4734 for (i = 0; i < hw->ports; i++) {
4735 struct net_device *dev = hw->dev[i];
4736 struct sky2_port *sky2 = netdev_priv(dev);
4737
4738 if (sky2->wol) {
4739 wol = 1;
4740 sky2_wol_init(sky2);
4741 }
4742 }
4743
4744 if (wol)
4745 sky2_power_aux(hw);
4746
4747 pci_enable_wake(pdev, PCI_D3hot, wol);
4748 pci_enable_wake(pdev, PCI_D3cold, wol);
4749
4750 pci_disable_device(pdev);
f71eb1a2 4751 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4752}
4753
cd28ab6a 4754static struct pci_driver sky2_driver = {
793b883e
SH		 4755 .name = DRV_NAME,
4756 .id_table = sky2_id_table,
4757 .probe = sky2_probe,
4758 .remove = __devexit_p(sky2_remove),
cd28ab6a 4759#ifdef CONFIG_PM
793b883e
SH		 4760 .suspend = sky2_suspend,
4761 .resume = sky2_resume,
cd28ab6a 4762#endif
e3173832 4763 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4764};
4765
4766static int __init sky2_init_module(void)
4767{
c844d483
SH		 4768 pr_info(PFX "driver version " DRV_VERSION "\n");
4769
3cf26753 4770 sky2_debug_init();
50241c4c 4771 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4772}
4773
4774static void __exit sky2_cleanup_module(void)
4775{
4776 pci_unregister_driver(&sky2_driver);
3cf26753 4777 sky2_debug_cleanup();
cd28ab6a
SH		 4778}
4779
4780module_init(sky2_init_module);
4781module_exit(sky2_cleanup_module);
4782
4783MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4784MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4785MODULE_LICENSE("GPL");
5f4f9dc1 4786MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)