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sky2: transmit ring accounting
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
0c3f450b 53#define DRV_VERSION "1.25"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 66
ee5f68fe 67/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 71#define TX_MAX_PENDING 4096
72#define TX_DEF_PENDING 127
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 142 { 0 }
143};
793b883e 144
cd28ab6a
SH		 145MODULE_DEVICE_TABLE(pci, sky2_id_table);
146
147/* Avoid conditionals by using array */
148static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
149static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 150static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 151
d1b139c0
SH		 152static void sky2_set_multicast(struct net_device *dev);
153
af043aa5 154/* Access to PHY via serial interconnect */
ef743d33 155static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 156{
157 int i;
158
159 gma_write16(hw, port, GM_SMI_DATA, val);
160 gma_write16(hw, port, GM_SMI_CTRL,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
162
163 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 164 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
165 if (ctrl == 0xffff)
166 goto io_error;
167
168 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 169 return 0;
af043aa5
SH		 170
171 udelay(10);
cd28ab6a 172 }
ef743d33 173
af043aa5 174 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 175 return -ETIMEDOUT;
af043aa5
SH		 176
177io_error:
178 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
179 return -EIO;
cd28ab6a
SH		 180}
181
ef743d33 182static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 183{
184 int i;
185
793b883e 186 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 187 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
188
189 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 190 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
191 if (ctrl == 0xffff)
192 goto io_error;
193
194 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 195 *val = gma_read16(hw, port, GM_SMI_DATA);
196 return 0;
197 }
198
af043aa5 199 udelay(10);
cd28ab6a
SH		 200 }
201
af043aa5 202 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 203 return -ETIMEDOUT;
af043aa5
SH		 204io_error:
205 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
206 return -EIO;
ef743d33 207}
208
af043aa5 209static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 210{
211 u16 v;
af043aa5 212 __gm_phy_read(hw, port, reg, &v);
ef743d33 213 return v;
cd28ab6a
SH		 214}
215
5afa0a9c 216
ae306cca
SH		 217static void sky2_power_on(struct sky2_hw *hw)
218{
219 /* switch power to VCC (WA for VAUX problem) */
220 sky2_write8(hw, B0_POWER_CTRL,
221 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 222
ae306cca
SH		 223 /* disable Core Clock Division, */
224 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 225
ae306cca
SH		 226 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
227 /* enable bits are inverted */
228 sky2_write8(hw, B2_Y2_CLK_GATE,
229 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
230 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
231 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
232 else
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 234
ea76e635 235 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 236 u32 reg;
5afa0a9c 237
b32f40c4 238 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 239
b32f40c4 240 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 241 /* set all bits to 0 except bits 15..12 and 8 */
242 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 243 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 244
b32f40c4 245 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 246 /* set all bits to 0 except bits 28 & 27 */
247 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 248 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 249
b32f40c4 250 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 251
252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
253 reg = sky2_read32(hw, B2_GP_IO);
254 reg |= GLB_GPIO_STAT_RACE_DIS;
255 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 256
257 sky2_read32(hw, B2_GP_IO);
5afa0a9c 258 }
10547ae2
SH		 259
260 /* Turn on "driver loaded" LED */
261 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 262}
5afa0a9c 263
ae306cca
SH		 264static void sky2_power_aux(struct sky2_hw *hw)
265{
266 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
267 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
268 else
269 /* enable bits are inverted */
270 sky2_write8(hw, B2_Y2_CLK_GATE,
271 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
272 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
273 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
274
c23ddf8f
SH		 275 /* switch power to VAUX if supported and PME from D3cold */
276 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
277 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 278 sky2_write8(hw, B0_POWER_CTRL,
279 (PC_VAUX_ENA | PC_VCC_ENA |
280 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 281
282 /* turn off "driver loaded LED" */
283 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c 284}
285
d3bcfbeb 286static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 287{
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 292
cd28ab6a
SH		 293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301}
302
16ad91e1
SH		 303/* flow control to advertise bits */
304static const u16 copper_fc_adv[] = {
305 [FC_NONE] = 0,
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
309};
310
311/* flow control to advertise bits when using 1000BaseX */
312static const u16 fiber_fc_adv[] = {
df3fe1f3 313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 317};
318
319/* flow control to GMA disable bits */
320static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
324 [FC_BOTH] = 0,
325};
326
327
cd28ab6a
SH		 328static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
329{
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 332
0ea065e5 333 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
336
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 338 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
340
53419c68 341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 342 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 343 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
345 else
53419c68
SH		 346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 348
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 353 if (sky2_is_copper(hw)) {
05745c4a 354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 357
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
360 u16 spec;
361
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
366 }
cd28ab6a
SH		 367 } else {
368 /* disable energy detect */
369 ctrl &= ~PHY_M_PC_EN_DET_MSK;
370
371 /* enable automatic crossover */
372 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
373
53419c68 374 /* downshift on PHY 88E1112 and 88E1149 is changed */
0ea065e5 375 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED)
ea76e635 376 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 377 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 378 ctrl &= ~PHY_M_PC_DSC_MSK;
379 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
380 }
381 }
cd28ab6a
SH		 382 } else {
383 /* workaround for deviation #4.88 (CRC errors) */
384 /* disable Automatic Crossover */
385
386 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 387 }
cd28ab6a 388
b89165f2
SH		 389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
390
391 /* special setup for PHY 88E1112 Fiber */
ea76e635 392 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 393 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 394
b89165f2
SH		 395 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
397 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
398 ctrl &= ~PHY_M_MAC_MD_MSK;
399 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401
402 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 403 /* select page 1 to access Fiber registers */
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 405
406 /* for SFP-module set SIGDET polarity to low */
407 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
408 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 410 }
b89165f2
SH		 411
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 413 }
414
7800fddc 415 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 416 ct1000 = 0;
417 adv = PHY_AN_CSMA;
2eaba1a2 418 reg = 0;
cd28ab6a 419
0ea065e5 420 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 421 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 422 if (sky2->advertising & ADVERTISED_1000baseT_Full)
423 ct1000 |= PHY_M_1000C_AFD;
424 if (sky2->advertising & ADVERTISED_1000baseT_Half)
425 ct1000 |= PHY_M_1000C_AHD;
426 if (sky2->advertising & ADVERTISED_100baseT_Full)
427 adv |= PHY_M_AN_100_FD;
428 if (sky2->advertising & ADVERTISED_100baseT_Half)
429 adv |= PHY_M_AN_100_HD;
430 if (sky2->advertising & ADVERTISED_10baseT_Full)
431 adv |= PHY_M_AN_10_FD;
432 if (sky2->advertising & ADVERTISED_10baseT_Half)
433 adv |= PHY_M_AN_10_HD;
709c6e7b 434
b89165f2
SH		 435 } else { /* special defines for FIBER (88E1040S only) */
436 if (sky2->advertising & ADVERTISED_1000baseT_Full)
437 adv |= PHY_M_AN_1000X_AFD;
438 if (sky2->advertising & ADVERTISED_1000baseT_Half)
439 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 440 }
cd28ab6a
SH		 441
442 /* Restart Auto-negotiation */
443 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
444 } else {
445 /* forced speed/duplex settings */
446 ct1000 = PHY_M_1000C_MSE;
447
0ea065e5
SH		 448 /* Disable auto update for duplex flow control and duplex */
449 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 450
451 switch (sky2->speed) {
452 case SPEED_1000:
453 ctrl |= PHY_CT_SP1000;
2eaba1a2 454 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 455 break;
456 case SPEED_100:
457 ctrl |= PHY_CT_SP100;
2eaba1a2 458 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 459 break;
460 }
461
2eaba1a2
SH		 462 if (sky2->duplex == DUPLEX_FULL) {
463 reg |= GM_GPCR_DUP_FULL;
464 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 465 } else if (sky2->speed < SPEED_1000)
466 sky2->flow_mode = FC_NONE;
0ea065e5 467 }
2eaba1a2 468
0ea065e5
SH		 469 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
470 if (sky2_is_copper(hw))
471 adv |= copper_fc_adv[sky2->flow_mode];
472 else
473 adv |= fiber_fc_adv[sky2->flow_mode];
474 } else {
475 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 476 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 477
478 /* Forward pause packets to GMAC? */
16ad91e1 479 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 480 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
481 else
482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 483 }
484
2eaba1a2
SH		 485 gma_write16(hw, port, GM_GP_CTRL, reg);
486
05745c4a 487 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 488 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
489
490 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
491 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
492
493 /* Setup Phy LED's */
494 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
495 ledover = 0;
496
497 switch (hw->chip_id) {
498 case CHIP_ID_YUKON_FE:
499 /* on 88E3082 these bits are at 11..9 (shifted left) */
500 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
501
502 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
503
504 /* delete ACT LED control bits */
505 ctrl &= ~PHY_M_FELP_LED1_MSK;
506 /* change ACT LED control to blink mode */
507 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
508 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
509 break;
510
05745c4a
SH		 511 case CHIP_ID_YUKON_FE_P:
512 /* Enable Link Partner Next Page */
513 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
514 ctrl |= PHY_M_PC_ENA_LIP_NP;
515
516 /* disable Energy Detect and enable scrambler */
517 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
518 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
519
520 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
521 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
522 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
523 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
524
525 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
526 break;
527
cd28ab6a 528 case CHIP_ID_YUKON_XL:
793b883e 529 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 530
531 /* select page 3 to access LED control register */
532 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
533
534 /* set LED Function Control register */
ed6d32c7
SH		 535 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
536 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
537 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
538 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
539 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 540
541 /* set Polarity Control register */
542 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 543 (PHY_M_POLC_LS1_P_MIX(4) |
544 PHY_M_POLC_IS0_P_MIX(4) |
545 PHY_M_POLC_LOS_CTRL(2) |
546 PHY_M_POLC_INIT_CTRL(2) |
547 PHY_M_POLC_STA1_CTRL(2) |
548 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 549
550 /* restore page register */
793b883e 551 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 552 break;
93745494 553
ed6d32c7 554 case CHIP_ID_YUKON_EC_U:
93745494 555 case CHIP_ID_YUKON_EX:
ed4d4161 556 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 557 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
558
559 /* select page 3 to access LED control register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
561
562 /* set LED Function Control register */
563 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
564 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
565 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
566 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
567 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
568
569 /* set Blink Rate in LED Timer Control Register */
570 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
571 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
572 /* restore page register */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
574 break;
cd28ab6a
SH		 575
576 default:
577 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
578 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 579
cd28ab6a 580 /* turn off the Rx LED (LED_RX) */
a84d0a3d 581 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 582 }
583
0ce8b98d 584 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 585 /* apply fixes in PHY AFE */
ed6d32c7
SH		 586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
587
977bdf06 588 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 589 gm_phy_write(hw, port, 0x18, 0xaa99);
590 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 591
0ce8b98d
SH		 592 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
593 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
594 gm_phy_write(hw, port, 0x18, 0xa204);
595 gm_phy_write(hw, port, 0x17, 0x2002);
596 }
977bdf06
SH		 597
598 /* set page register to 0 */
9467a8fc 599 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 600 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
601 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
602 /* apply workaround for integrated resistors calibration */
603 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
604 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 605 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
606 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 607 /* no effect on Yukon-XL */
977bdf06 608 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 609
0ea065e5
SH		 610 if ( !(sky2->flags & SKY2_FLAG_AUTO_SPEED)
611 || sky2->speed == SPEED_100) {
977bdf06 612 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 613 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 614 }
cd28ab6a 615
977bdf06
SH		 616 if (ledover)
617 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
618
619 }
2eaba1a2 620
d571b694 621 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 622 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 623 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
624 else
625 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
626}
627
b96936da
SH		 628static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
629static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
630
631static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 632{
633 u32 reg1;
d3bcfbeb 634
82637e80 635 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 636 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 637 reg1 &= ~phy_power[port];
d3bcfbeb 638
b96936da 639 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 640 reg1 |= coma_mode[port];
641
b32f40c4 642 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 643 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
644 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 645
646 if (hw->chip_id == CHIP_ID_YUKON_FE)
647 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
648 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
649 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 650}
167f53d0 651
b96936da
SH		 652static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
653{
654 u32 reg1;
db99b988
SH		 655 u16 ctrl;
656
657 /* release GPHY Control reset */
658 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
659
660 /* release GMAC reset */
661 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
662
663 if (hw->flags & SKY2_HW_NEWER_PHY) {
664 /* select page 2 to access MAC control register */
665 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
666
667 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
668 /* allow GMII Power Down */
669 ctrl &= ~PHY_M_MAC_GMIF_PUP;
670 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
671
672 /* set page register back to 0 */
673 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
674 }
675
676 /* setup General Purpose Control Register */
677 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 678 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
679 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
680 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 681
682 if (hw->chip_id != CHIP_ID_YUKON_EC) {
683 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 684 /* select page 2 to access MAC control register */
685 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 686
e484d5f5 687 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 688 /* enable Power Down */
689 ctrl |= PHY_M_PC_POW_D_ENA;
690 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 691
692 /* set page register back to 0 */
693 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 694 }
695
696 /* set IEEE compatible Power Down Mode (dev. #4.99) */
697 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
698 }
b96936da
SH		 699
700 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
701 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 702 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 703 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
704 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 705}
706
1b537565
SH		 707/* Force a renegotiation */
708static void sky2_phy_reinit(struct sky2_port *sky2)
709{
e07b1aa8 710 spin_lock_bh(&sky2->phy_lock);
1b537565 711 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 712 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 713}
714
e3173832
SH		 715/* Put device in state to listen for Wake On Lan */
716static void sky2_wol_init(struct sky2_port *sky2)
717{
718 struct sky2_hw *hw = sky2->hw;
719 unsigned port = sky2->port;
720 enum flow_control save_mode;
721 u16 ctrl;
722 u32 reg1;
723
724 /* Bring hardware out of reset */
725 sky2_write16(hw, B0_CTST, CS_RST_CLR);
726 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
727
728 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
730
731 /* Force to 10/100
732 * sky2_reset will re-enable on resume
733 */
734 save_mode = sky2->flow_mode;
735 ctrl = sky2->advertising;
736
737 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
738 sky2->flow_mode = FC_NONE;
b96936da
SH		 739
740 spin_lock_bh(&sky2->phy_lock);
741 sky2_phy_power_up(hw, port);
742 sky2_phy_init(hw, port);
743 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 744
745 sky2->flow_mode = save_mode;
746 sky2->advertising = ctrl;
747
748 /* Set GMAC to no flow control and auto update for speed/duplex */
749 gma_write16(hw, port, GM_GP_CTRL,
750 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
751 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
752
753 /* Set WOL address */
754 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
755 sky2->netdev->dev_addr, ETH_ALEN);
756
757 /* Turn on appropriate WOL control bits */
758 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
759 ctrl = 0;
760 if (sky2->wol & WAKE_PHY)
761 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
762 else
763 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
764
765 if (sky2->wol & WAKE_MAGIC)
766 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
767 else
768 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
769
770 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
771 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
772
773 /* Turn on legacy PCI-Express PME mode */
b32f40c4 774 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 775 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 776 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 777
778 /* block receiver */
779 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
780
781}
782
69161611
SH		 783static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
784{
05745c4a
SH		 785 struct net_device *dev = hw->dev[port];
786
ed4d4161
SH		 787 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
788 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
789 hw->chip_id == CHIP_ID_YUKON_FE_P ||
790 hw->chip_id == CHIP_ID_YUKON_SUPR) {
791 /* Yukon-Extreme B0 and further Extreme devices */
792 /* enable Store & Forward mode for TX */
05745c4a 793
ed4d4161
SH		 794 if (dev->mtu <= ETH_DATA_LEN)
795 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
796 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 797
ed4d4161
SH		 798 else
799 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
800 TX_JUMBO_ENA| TX_STFW_ENA);
801 } else {
802 if (dev->mtu <= ETH_DATA_LEN)
803 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
804 else {
805 /* set Tx GMAC FIFO Almost Empty Threshold */
806 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
807 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 808
ed4d4161
SH		 809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
810
811 /* Can't do offload because of lack of store/forward */
812 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
813 }
69161611
SH		 814 }
815}
816
cd28ab6a
SH		 817static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
818{
819 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
820 u16 reg;
25cccecc 821 u32 rx_reg;
cd28ab6a
SH		 822 int i;
823 const u8 *addr = hw->dev[port]->dev_addr;
824
f350339c
SH		 825 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
826 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 827
828 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
829
793b883e 830 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 831 /* WA DEV_472 -- looks like crossed wires on port 2 */
832 /* clear GMAC 1 Control reset */
833 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
834 do {
835 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
836 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
837 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
838 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
839 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
840 }
841
793b883e 842 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 843
2eaba1a2
SH		 844 /* Enable Transmit FIFO Underrun */
845 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
846
e07b1aa8 847 spin_lock_bh(&sky2->phy_lock);
b96936da 848 sky2_phy_power_up(hw, port);
cd28ab6a 849 sky2_phy_init(hw, port);
e07b1aa8 850 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 851
852 /* MIB clear */
853 reg = gma_read16(hw, port, GM_PHY_ADDR);
854 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
855
43f2f104
SH		 856 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
857 gma_read16(hw, port, i);
cd28ab6a
SH		 858 gma_write16(hw, port, GM_PHY_ADDR, reg);
859
860 /* transmit control */
861 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
862
863 /* receive control reg: unicast + multicast + no FCS */
864 gma_write16(hw, port, GM_RX_CTRL,
793b883e 865 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 866
867 /* transmit flow control */
868 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
869
870 /* transmit parameter */
871 gma_write16(hw, port, GM_TX_PARAM,
872 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
873 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
874 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
875 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
876
877 /* serial mode register */
878 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 879 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 880
6b1a3aef 881 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 882 reg |= GM_SMOD_JUMBO_ENA;
883
884 gma_write16(hw, port, GM_SERIAL_MODE, reg);
885
cd28ab6a
SH		 886 /* virtual address for data */
887 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
888
793b883e
SH		 889 /* physical address: used for pause frames */
890 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
891
892 /* ignore counter overflows */
cd28ab6a
SH		 893 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
894 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
895 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
896
897 /* Configure Rx MAC FIFO */
898 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 899 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 900 if (hw->chip_id == CHIP_ID_YUKON_EX ||
901 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 902 rx_reg |= GMF_RX_OVER_ON;
69161611 903
25cccecc 904 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 905
798fdd07
SH		 906 if (hw->chip_id == CHIP_ID_YUKON_XL) {
907 /* Hardware errata - clear flush mask */
908 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
909 } else {
910 /* Flush Rx MAC FIFO on any flow control or error */
911 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
912 }
cd28ab6a 913
8df9a876 914 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 915 reg = RX_GMF_FL_THR_DEF + 1;
916 /* Another magic mystery workaround from sk98lin */
917 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
918 hw->chip_rev == CHIP_REV_YU_FE2_A0)
919 reg = 0x178;
920 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 921
922 /* Configure Tx MAC FIFO */
923 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
924 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 925
e0c28116 926 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 927 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 928 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 929 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 930
69161611 931 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 932 }
933
e970d1f8
SH		 934 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
935 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
936 /* disable dynamic watermark */
937 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
938 reg &= ~TX_DYN_WM_ENA;
939 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
940 }
cd28ab6a
SH		 941}
942
67712901
SH		 943/* Assign Ram Buffer allocation to queue */
944static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 945{
67712901
SH		 946 u32 end;
947
948 /* convert from K bytes to qwords used for hw register */
949 start *= 1024/8;
950 space *= 1024/8;
951 end = start + space - 1;
793b883e 952
cd28ab6a
SH		 953 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
954 sky2_write32(hw, RB_ADDR(q, RB_START), start);
955 sky2_write32(hw, RB_ADDR(q, RB_END), end);
956 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
957 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
958
959 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 960 u32 tp = space - space/4;
793b883e 961
1c28f6ba
SH		 962 /* On receive queue's set the thresholds
963 * give receiver priority when > 3/4 full
964 * send pause when down to 2K
965 */
966 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
967 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 968
1c28f6ba
SH		 969 tp = space - 2048/8;
970 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
971 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 972 } else {
973 /* Enable store & forward on Tx queue's because
974 * Tx FIFO is only 1K on Yukon
975 */
976 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
977 }
978
979 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 980 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 981}
982
cd28ab6a 983/* Setup Bus Memory Interface */
af4ed7e6 984static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 985{
986 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
987 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
988 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 989 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 990}
991
cd28ab6a
SH		 992/* Setup prefetch unit registers. This is the interface between
993 * hardware and driver list elements
994 */
8cc048e3 995static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 996 dma_addr_t addr, u32 last)
cd28ab6a 997{
cd28ab6a
SH		 998 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
999 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1000 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1001 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1002 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1003 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1004
1005 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1006}
1007
9b289c33 1008static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1009{
9b289c33 1010 struct sky2_tx_le *le = sky2->tx_le + *slot;
6b84daca 1011 struct tx_ring_info *re = sky2->tx_ring + *slot;
793b883e 1012
ee5f68fe 1013 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
6b84daca
SH		 1014 re->flags = 0;
1015 re->skb = NULL;
291ea614 1016 le->ctrl = 0;
793b883e
SH		 1017 return le;
1018}
cd28ab6a 1019
88f5f0ca
SH		 1020static void tx_init(struct sky2_port *sky2)
1021{
1022 struct sky2_tx_le *le;
1023
1024 sky2->tx_prod = sky2->tx_cons = 0;
1025 sky2->tx_tcpsum = 0;
1026 sky2->tx_last_mss = 0;
1027
9b289c33 1028 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1029 le->addr = 0;
1030 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1031 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1032}
1033
290d4de5
SH		 1034/* Update chip's next pointer */
1035static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1036{
50432cb5 1037 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1038 wmb();
50432cb5
SH		 1039 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1040
1041 /* Synchronize I/O on since next processor may write to tail */
1042 mmiowb();
cd28ab6a
SH		 1043}
1044
793b883e 1045
cd28ab6a
SH		 1046static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1047{
1048 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1049 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1050 le->ctrl = 0;
cd28ab6a
SH		 1051 return le;
1052}
1053
14d0263f
SH		 1054/* Build description to hardware for one receive segment */
1055static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1056 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1057{
1058 struct sky2_rx_le *le;
1059
86c6887e 1060 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1061 le = sky2_next_rx(sky2);
86c6887e 1062 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1063 le->opcode = OP_ADDR64 | HW_OWNER;
1064 }
793b883e 1065
cd28ab6a 1066 le = sky2_next_rx(sky2);
d6e74b6b 1067 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1068 le->length = cpu_to_le16(len);
14d0263f 1069 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1070}
1071
14d0263f
SH		 1072/* Build description to hardware for one possibly fragmented skb */
1073static void sky2_rx_submit(struct sky2_port *sky2,
1074 const struct rx_ring_info *re)
1075{
1076 int i;
1077
1078 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1079
1080 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1081 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1082}
1083
1084
454e6cb6 1085static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1086 unsigned size)
1087{
1088 struct sk_buff *skb = re->skb;
1089 int i;
1090
1091 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1092 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1093 return -EIO;
1094
14d0263f
SH		 1095 pci_unmap_len_set(re, data_size, size);
1096
1097 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1098 re->frag_addr[i] = pci_map_page(pdev,
1099 skb_shinfo(skb)->frags[i].page,
1100 skb_shinfo(skb)->frags[i].page_offset,
1101 skb_shinfo(skb)->frags[i].size,
1102 PCI_DMA_FROMDEVICE);
454e6cb6 1103 return 0;
14d0263f
SH		 1104}
1105
1106static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1107{
1108 struct sk_buff *skb = re->skb;
1109 int i;
1110
1111 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1112 PCI_DMA_FROMDEVICE);
1113
1114 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1115 pci_unmap_page(pdev, re->frag_addr[i],
1116 skb_shinfo(skb)->frags[i].size,
1117 PCI_DMA_FROMDEVICE);
1118}
793b883e 1119
cd28ab6a
SH		 1120/* Tell chip where to start receive checksum.
1121 * Actually has two checksums, but set both same to avoid possible byte
1122 * order problems.
1123 */
793b883e 1124static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1125{
ea76e635 1126 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1127
ea76e635
SH		 1128 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1129 le->ctrl = 0;
1130 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1131
ea76e635
SH		 1132 sky2_write32(sky2->hw,
1133 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1134 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1135 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1136}
1137
6b1a3aef 1138/*
1139 * The RX Stop command will not work for Yukon-2 if the BMU does not
1140 * reach the end of packet and since we can't make sure that we have
1141 * incoming data, we must reset the BMU while it is not doing a DMA
1142 * transfer. Since it is possible that the RX path is still active,
1143 * the RX RAM buffer will be stopped first, so any possible incoming
1144 * data will not trigger a DMA. After the RAM buffer is stopped, the
1145 * BMU is polled until any DMA in progress is ended and only then it
1146 * will be reset.
1147 */
1148static void sky2_rx_stop(struct sky2_port *sky2)
1149{
1150 struct sky2_hw *hw = sky2->hw;
1151 unsigned rxq = rxqaddr[sky2->port];
1152 int i;
1153
1154 /* disable the RAM Buffer receive queue */
1155 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1156
1157 for (i = 0; i < 0xffff; i++)
1158 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1159 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1160 goto stopped;
1161
1162 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1163 sky2->netdev->name);
1164stopped:
1165 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1166
1167 /* reset the Rx prefetch unit */
1168 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1169 mmiowb();
6b1a3aef 1170}
793b883e 1171
d571b694 1172/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1173static void sky2_rx_clean(struct sky2_port *sky2)
1174{
1175 unsigned i;
1176
1177 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1178 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1179 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1180
1181 if (re->skb) {
14d0263f 1182 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1183 kfree_skb(re->skb);
1184 re->skb = NULL;
1185 }
1186 }
1187}
1188
ef743d33 1189/* Basic MII support */
1190static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1191{
1192 struct mii_ioctl_data *data = if_mii(ifr);
1193 struct sky2_port *sky2 = netdev_priv(dev);
1194 struct sky2_hw *hw = sky2->hw;
1195 int err = -EOPNOTSUPP;
1196
1197 if (!netif_running(dev))
1198 return -ENODEV; /* Phy still in reset */
1199
d89e1343 1200 switch (cmd) {
ef743d33 1201 case SIOCGMIIPHY:
1202 data->phy_id = PHY_ADDR_MARV;
1203
1204 /* fallthru */
1205 case SIOCGMIIREG: {
1206 u16 val = 0;
91c86df5 1207
e07b1aa8 1208 spin_lock_bh(&sky2->phy_lock);
ef743d33 1209 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1210 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1211
ef743d33 1212 data->val_out = val;
1213 break;
1214 }
1215
1216 case SIOCSMIIREG:
e07b1aa8 1217 spin_lock_bh(&sky2->phy_lock);
ef743d33 1218 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1219 data->val_in);
e07b1aa8 1220 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1221 break;
1222 }
1223 return err;
1224}
1225
d1f13708 1226#ifdef SKY2_VLAN_TAG_USED
d494eacd 1227static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1228{
d494eacd 1229 if (onoff) {
3d4e66f5
SH		 1230 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1231 RX_VLAN_STRIP_ON);
1232 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1233 TX_VLAN_TAG_ON);
1234 } else {
1235 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1236 RX_VLAN_STRIP_OFF);
1237 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1238 TX_VLAN_TAG_OFF);
1239 }
d494eacd
SH		 1240}
1241
1242static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1243{
1244 struct sky2_port *sky2 = netdev_priv(dev);
1245 struct sky2_hw *hw = sky2->hw;
1246 u16 port = sky2->port;
1247
1248 netif_tx_lock_bh(dev);
1249 napi_disable(&hw->napi);
1250
1251 sky2->vlgrp = grp;
1252 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1253
d1d08d12 1254 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1255 napi_enable(&hw->napi);
2bb8c262 1256 netif_tx_unlock_bh(dev);
d1f13708 1257}
1258#endif
1259
bd1c6869
SH		 1260/* Amount of required worst case padding in rx buffer */
1261static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1262{
1263 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1264}
1265
82788c7a 1266/*
14d0263f
SH		 1267 * Allocate an skb for receiving. If the MTU is large enough
1268 * make the skb non-linear with a fragment list of pages.
82788c7a 1269 */
14d0263f 1270static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1271{
1272 struct sk_buff *skb;
14d0263f 1273 int i;
82788c7a 1274
724b6942
SH		 1275 skb = netdev_alloc_skb(sky2->netdev,
1276 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1277 if (!skb)
1278 goto nomem;
1279
39dbd958 1280 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1281 unsigned char *start;
1282 /*
1283 * Workaround for a bug in FIFO that cause hang
1284 * if the FIFO if the receive buffer is not 64 byte aligned.
1285 * The buffer returned from netdev_alloc_skb is
1286 * aligned except if slab debugging is enabled.
1287 */
f03b8654
SH		 1288 start = PTR_ALIGN(skb->data, 8);
1289 skb_reserve(skb, start - skb->data);
bd1c6869 1290 } else
f03b8654 1291 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1292
1293 for (i = 0; i < sky2->rx_nfrags; i++) {
1294 struct page *page = alloc_page(GFP_ATOMIC);
1295
1296 if (!page)
1297 goto free_partial;
1298 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1299 }
1300
1301 return skb;
14d0263f
SH		 1302free_partial:
1303 kfree_skb(skb);
1304nomem:
1305 return NULL;
82788c7a
SH		 1306}
1307
55c9dd35
SH		 1308static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1309{
1310 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1311}
1312
cd28ab6a
SH		 1313/*
1314 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1315 * Normal case this ends up creating one list element for skb
1316 * in the receive ring. Worst case if using large MTU and each
1317 * allocation falls on a different 64 bit region, that results
1318 * in 6 list elements per ring entry.
1319 * One element is used for checksum enable/disable, and one
1320 * extra to avoid wrap.
cd28ab6a 1321 */
6b1a3aef 1322static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1323{
6b1a3aef 1324 struct sky2_hw *hw = sky2->hw;
14d0263f 1325 struct rx_ring_info *re;
6b1a3aef 1326 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1327 unsigned i, size, thresh;
cd28ab6a 1328
6b1a3aef 1329 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1330 sky2_qset(hw, rxq);
977bdf06 1331
c3905bc4
SH		 1332 /* On PCI express lowering the watermark gives better performance */
1333 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1334 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1335
1336 /* These chips have no ram buffer?
1337 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1338 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1339 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1340 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1341 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1342
6b1a3aef 1343 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1344
ea76e635
SH		 1345 if (!(hw->flags & SKY2_HW_NEW_LE))
1346 rx_set_checksum(sky2);
14d0263f
SH		 1347
1348 /* Space needed for frame data + headers rounded up */
f957da2a 1349 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1350
1351 /* Stopping point for hardware truncation */
1352 thresh = (size - 8) / sizeof(u32);
1353
5f06eba4 1354 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1355 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1356
5f06eba4
SH		 1357 /* Compute residue after pages */
1358 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1359
5f06eba4
SH		 1360 /* Optimize to handle small packets and headers */
1361 if (size < copybreak)
1362 size = copybreak;
1363 if (size < ETH_HLEN)
1364 size = ETH_HLEN;
14d0263f 1365
14d0263f
SH		 1366 sky2->rx_data_size = size;
1367
1368 /* Fill Rx ring */
793b883e 1369 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1370 re = sky2->rx_ring + i;
cd28ab6a 1371
14d0263f 1372 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1373 if (!re->skb)
1374 goto nomem;
1375
454e6cb6
SH		 1376 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1377 dev_kfree_skb(re->skb);
1378 re->skb = NULL;
1379 goto nomem;
1380 }
1381
14d0263f 1382 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1383 }
1384
a1433ac4
SH		 1385 /*
1386 * The receiver hangs if it receives frames larger than the
1387 * packet buffer. As a workaround, truncate oversize frames, but
1388 * the register is limited to 9 bits, so if you do frames > 2052
1389 * you better get the MTU right!
1390 */
a1433ac4
SH		 1391 if (thresh > 0x1ff)
1392 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1393 else {
1394 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1395 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1396 }
1397
6b1a3aef 1398 /* Tell chip about available buffers */
55c9dd35 1399 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1400 return 0;
1401nomem:
1402 sky2_rx_clean(sky2);
1403 return -ENOMEM;
1404}
1405
90bbebb4
MM		 1406static int sky2_alloc_buffers(struct sky2_port *sky2)
1407{
1408 struct sky2_hw *hw = sky2->hw;
1409
1410 /* must be power of 2 */
1411 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1412 sky2->tx_ring_size *
1413 sizeof(struct sky2_tx_le),
1414 &sky2->tx_le_map);
1415 if (!sky2->tx_le)
1416 goto nomem;
1417
1418 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1419 GFP_KERNEL);
1420 if (!sky2->tx_ring)
1421 goto nomem;
1422
1423 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1424 &sky2->rx_le_map);
1425 if (!sky2->rx_le)
1426 goto nomem;
1427 memset(sky2->rx_le, 0, RX_LE_BYTES);
1428
1429 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1430 GFP_KERNEL);
1431 if (!sky2->rx_ring)
1432 goto nomem;
1433
1434 return 0;
1435nomem:
1436 return -ENOMEM;
1437}
1438
1439static void sky2_free_buffers(struct sky2_port *sky2)
1440{
1441 struct sky2_hw *hw = sky2->hw;
1442
1443 if (sky2->rx_le) {
1444 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1445 sky2->rx_le, sky2->rx_le_map);
1446 sky2->rx_le = NULL;
1447 }
1448 if (sky2->tx_le) {
1449 pci_free_consistent(hw->pdev,
1450 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1451 sky2->tx_le, sky2->tx_le_map);
1452 sky2->tx_le = NULL;
1453 }
1454 kfree(sky2->tx_ring);
1455 kfree(sky2->rx_ring);
1456
1457 sky2->tx_ring = NULL;
1458 sky2->rx_ring = NULL;
1459}
1460
cd28ab6a
SH		 1461/* Bring up network interface. */
1462static int sky2_up(struct net_device *dev)
1463{
1464 struct sky2_port *sky2 = netdev_priv(dev);
1465 struct sky2_hw *hw = sky2->hw;
1466 unsigned port = sky2->port;
e0c28116 1467 u32 imask, ramsize;
90bbebb4 1468 int cap, err;
843a46f4 1469 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1470
ee7abb04
SH		 1471 /*
1472 * On dual port PCI-X card, there is an problem where status
1473 * can be received out of order due to split transactions
843a46f4 1474 */
ee7abb04
SH		 1475 if (otherdev && netif_running(otherdev) &&
1476 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1477 u16 cmd;
1478
b32f40c4 1479 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1480 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1481 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1482
ee7abb04 1483 }
843a46f4 1484
55d7b4e6
SH		 1485 netif_carrier_off(dev);
1486
90bbebb4
MM		 1487 err = sky2_alloc_buffers(sky2);
1488 if (err)
cd28ab6a 1489 goto err_out;
88f5f0ca
SH		 1490
1491 tx_init(sky2);
cd28ab6a 1492
cd28ab6a
SH		 1493 sky2_mac_init(hw, port);
1494
e0c28116
SH		 1495 /* Register is number of 4K blocks on internal RAM buffer. */
1496 ramsize = sky2_read8(hw, B2_E_0) * 4;
1497 if (ramsize > 0) {
67712901 1498 u32 rxspace;
cd28ab6a 1499
39dbd958 1500 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1501 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1502 if (ramsize < 16)
1503 rxspace = ramsize / 2;
1504 else
1505 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1506
67712901
SH		 1507 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1508 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1509
1510 /* Make sure SyncQ is disabled */
1511 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1512 RB_RST_SET);
1513 }
793b883e 1514
af4ed7e6 1515 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1516
69161611
SH		 1517 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1518 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1519 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1520
977bdf06 1521 /* Set almost empty threshold */
c2716fb4
SH		 1522 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1523 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1524 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1525
6b1a3aef 1526 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1527 sky2->tx_ring_size - 1);
cd28ab6a 1528
d494eacd
SH		 1529#ifdef SKY2_VLAN_TAG_USED
1530 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1531#endif
1532
6b1a3aef 1533 err = sky2_rx_start(sky2);
6de16237 1534 if (err)
cd28ab6a
SH		 1535 goto err_out;
1536
cd28ab6a 1537 /* Enable interrupts from phy/mac for port */
e07b1aa8 1538 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1539 imask |= portirq_msk[port];
e07b1aa8 1540 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1541 sky2_read32(hw, B0_IMSK);
e07b1aa8 1542
a11da890
AD		 1543 if (netif_msg_ifup(sky2))
1544 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1545
cd28ab6a
SH		 1546 return 0;
1547
1548err_out:
90bbebb4 1549 sky2_free_buffers(sky2);
cd28ab6a
SH		 1550 return err;
1551}
1552
793b883e 1553/* Modular subtraction in ring */
ee5f68fe 1554static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1555{
ee5f68fe 1556 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1557}
cd28ab6a 1558
793b883e
SH		 1559/* Number of list elements available for next tx */
1560static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1561{
ee5f68fe 1562 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1563}
1564
793b883e 1565/* Estimate of number of transmit list elements required */
28bd181a 1566static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1567{
793b883e
SH		 1568 unsigned count;
1569
07e31637
SH		 1570 count = (skb_shinfo(skb)->nr_frags + 1)
1571 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1572
89114afd 1573 if (skb_is_gso(skb))
793b883e 1574 ++count;
07e31637
SH		 1575 else if (sizeof(dma_addr_t) == sizeof(u32))
1576 ++count; /* possible vlan */
793b883e 1577
84fa7933 1578 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1579 ++count;
1580
1581 return count;
cd28ab6a
SH		 1582}
1583
6b84daca
SH		 1584static void sky2_tx_unmap(struct pci_dev *pdev,
1585 const struct tx_ring_info *re)
1586{
1587 if (re->flags & TX_MAP_SINGLE)
1588 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1589 pci_unmap_len(re, maplen),
1590 PCI_DMA_TODEVICE);
1591 else if (re->flags & TX_MAP_PAGE)
1592 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1593 pci_unmap_len(re, maplen),
1594 PCI_DMA_TODEVICE);
1595}
1596
793b883e
SH		 1597/*
1598 * Put one packet in ring for transmit.
1599 * A single packet can generate multiple list elements, and
1600 * the number of ring elements will probably be less than the number
1601 * of list elements used.
1602 */
61357325
SH		 1603static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1604 struct net_device *dev)
cd28ab6a
SH		 1605{
1606 struct sky2_port *sky2 = netdev_priv(dev);
1607 struct sky2_hw *hw = sky2->hw;
d1f13708 1608 struct sky2_tx_le *le = NULL;
6cdbbdf3 1609 struct tx_ring_info *re;
9b289c33 1610 unsigned i, len;
cd28ab6a 1611 dma_addr_t mapping;
5dce95e5
SH		 1612 u32 upper;
1613 u16 slot;
cd28ab6a
SH		 1614 u16 mss;
1615 u8 ctrl;
1616
2bb8c262
SH		 1617 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1618 return NETDEV_TX_BUSY;
cd28ab6a 1619
cd28ab6a
SH		 1620 len = skb_headlen(skb);
1621 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1622
454e6cb6
SH		 1623 if (pci_dma_mapping_error(hw->pdev, mapping))
1624 goto mapping_error;
1625
9b289c33 1626 slot = sky2->tx_prod;
454e6cb6
SH		 1627 if (unlikely(netif_msg_tx_queued(sky2)))
1628 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1629 dev->name, slot, skb->len);
454e6cb6 1630
86c6887e 1631 /* Send high bits if needed */
5dce95e5
SH		 1632 upper = upper_32_bits(mapping);
1633 if (upper != sky2->tx_last_upper) {
9b289c33 1634 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1635 le->addr = cpu_to_le32(upper);
1636 sky2->tx_last_upper = upper;
793b883e 1637 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1638 }
cd28ab6a
SH		 1639
1640 /* Check for TCP Segmentation Offload */
7967168c 1641 mss = skb_shinfo(skb)->gso_size;
793b883e 1642 if (mss != 0) {
ea76e635
SH		 1643
1644 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1645 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1646
1647 if (mss != sky2->tx_last_mss) {
9b289c33 1648 le = get_tx_le(sky2, &slot);
69161611 1649 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1650
1651 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1652 le->opcode = OP_MSS | HW_OWNER;
1653 else
1654 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1655 sky2->tx_last_mss = mss;
1656 }
cd28ab6a
SH		 1657 }
1658
cd28ab6a 1659 ctrl = 0;
d1f13708 1660#ifdef SKY2_VLAN_TAG_USED
1661 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1662 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1663 if (!le) {
9b289c33 1664 le = get_tx_le(sky2, &slot);
f65b138c 1665 le->addr = 0;
d1f13708 1666 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1667 } else
1668 le->opcode |= OP_VLAN;
1669 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1670 ctrl |= INS_VLAN;
1671 }
1672#endif
1673
1674 /* Handle TCP checksum offload */
84fa7933 1675 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1676 /* On Yukon EX (some versions) encoding change. */
ea76e635 1677 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1678 ctrl |= CALSUM; /* auto checksum */
1679 else {
1680 const unsigned offset = skb_transport_offset(skb);
1681 u32 tcpsum;
1682
1683 tcpsum = offset << 16; /* sum start */
1684 tcpsum |= offset + skb->csum_offset; /* sum write */
1685
1686 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1687 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1688 ctrl |= UDPTCP;
1689
1690 if (tcpsum != sky2->tx_tcpsum) {
1691 sky2->tx_tcpsum = tcpsum;
1692
9b289c33 1693 le = get_tx_le(sky2, &slot);
69161611
SH		 1694 le->addr = cpu_to_le32(tcpsum);
1695 le->length = 0; /* initial checksum value */
1696 le->ctrl = 1; /* one packet */
1697 le->opcode = OP_TCPLISW | HW_OWNER;
1698 }
1d179332 1699 }
cd28ab6a
SH		 1700 }
1701
6b84daca
SH		 1702 re = sky2->tx_ring + slot;
1703 re->flags = TX_MAP_SINGLE;
1704 pci_unmap_addr_set(re, mapaddr, mapping);
1705 pci_unmap_len_set(re, maplen, len);
1706
9b289c33 1707 le = get_tx_le(sky2, &slot);
d6e74b6b 1708 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1709 le->length = cpu_to_le16(len);
1710 le->ctrl = ctrl;
793b883e 1711 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1712
cd28ab6a
SH		 1713
1714 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1715 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1716
1717 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1718 frag->size, PCI_DMA_TODEVICE);
86c6887e 1719
454e6cb6
SH		 1720 if (pci_dma_mapping_error(hw->pdev, mapping))
1721 goto mapping_unwind;
1722
5dce95e5
SH		 1723 upper = upper_32_bits(mapping);
1724 if (upper != sky2->tx_last_upper) {
9b289c33 1725 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1726 le->addr = cpu_to_le32(upper);
1727 sky2->tx_last_upper = upper;
793b883e 1728 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1729 }
1730
6b84daca
SH		 1731 re = sky2->tx_ring + slot;
1732 re->flags = TX_MAP_PAGE;
1733 pci_unmap_addr_set(re, mapaddr, mapping);
1734 pci_unmap_len_set(re, maplen, frag->size);
1735
9b289c33 1736 le = get_tx_le(sky2, &slot);
d6e74b6b 1737 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1738 le->length = cpu_to_le16(frag->size);
1739 le->ctrl = ctrl;
793b883e 1740 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1741 }
6cdbbdf3 1742
6b84daca 1743 re->skb = skb;
cd28ab6a
SH		 1744 le->ctrl |= EOP;
1745
9b289c33
MM		 1746 sky2->tx_prod = slot;
1747
97bda706 1748 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1749 netif_stop_queue(dev);
b19666d9 1750
290d4de5 1751 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1752
cd28ab6a 1753 return NETDEV_TX_OK;
454e6cb6
SH		 1754
1755mapping_unwind:
ee5f68fe 1756 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1757 re = sky2->tx_ring + i;
1758
6b84daca 1759 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1760 }
1761
454e6cb6
SH		 1762mapping_error:
1763 if (net_ratelimit())
1764 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1765 dev_kfree_skb(skb);
1766 return NETDEV_TX_OK;
cd28ab6a
SH		 1767}
1768
cd28ab6a 1769/*
793b883e
SH		 1770 * Free ring elements from starting at tx_cons until "done"
1771 *
481cea4a
SH		 1772 * NB:
1773 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1774 * buffers so make sure not to free skb to early.
481cea4a
SH		 1775 * 2. This may run in parallel start_xmit because the it only
1776 * looks at the tail of the queue of FIFO (tx_cons), not
1777 * the head (tx_prod)
cd28ab6a 1778 */
d11c13e7 1779static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1780{
d11c13e7 1781 struct net_device *dev = sky2->netdev;
291ea614 1782 unsigned idx;
cd28ab6a 1783
ee5f68fe 1784 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1785
291ea614 1786 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1787 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1788 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1789 struct sk_buff *skb = re->skb;
291ea614 1790
6b84daca 1791 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1792
6b84daca 1793 if (skb) {
291ea614
SH		 1794 if (unlikely(netif_msg_tx_done(sky2)))
1795 printk(KERN_DEBUG "%s: tx done %u\n",
1796 dev->name, idx);
3cf26753 1797
7138a0f5 1798 dev->stats.tx_packets++;
bd1c6869
SH		 1799 dev->stats.tx_bytes += skb->len;
1800
724b6942 1801 dev_kfree_skb_any(skb);
2bf56fe2 1802
ee5f68fe 1803 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1804 }
793b883e 1805 }
793b883e 1806
291ea614 1807 sky2->tx_cons = idx;
50432cb5
SH		 1808 smp_mb();
1809
22e11703 1810 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1811 netif_wake_queue(dev);
cd28ab6a
SH		 1812}
1813
264bb4fa 1814static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1815{
a510996b
MM		 1816 /* Disable Force Sync bit and Enable Alloc bit */
1817 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1818 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1819
1820 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1821 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1822 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1823
1824 /* Reset the PCI FIFO of the async Tx queue */
1825 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1826 BMU_RST_SET | BMU_FIFO_RST);
1827
1828 /* Reset the Tx prefetch units */
1829 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1830 PREF_UNIT_RST_SET);
1831
1832 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1833 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1834}
1835
cd28ab6a
SH		 1836/* Network shutdown */
1837static int sky2_down(struct net_device *dev)
1838{
1839 struct sky2_port *sky2 = netdev_priv(dev);
1840 struct sky2_hw *hw = sky2->hw;
1841 unsigned port = sky2->port;
1842 u16 ctrl;
e07b1aa8 1843 u32 imask;
cd28ab6a 1844
1b537565
SH		 1845 /* Never really got started! */
1846 if (!sky2->tx_le)
1847 return 0;
1848
cd28ab6a
SH		 1849 if (netif_msg_ifdown(sky2))
1850 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1851
d104acaf
SH		 1852 /* Force flow control off */
1853 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1854
cd28ab6a
SH		 1855 /* Stop transmitter */
1856 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1857 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1858
1859 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1860 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1861
1862 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1863 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1864 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1865
1866 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1867
1868 /* Workaround shared GMAC reset */
793b883e
SH		 1869 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1870 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1871 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1872
cd28ab6a 1873 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1874
6c83504f
SH		 1875 /* Force any delayed status interrrupt and NAPI */
1876 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1877 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1878 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1879 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1880
a947a39d
MM		 1881 sky2_rx_stop(sky2);
1882
1883 /* Disable port IRQ */
1884 imask = sky2_read32(hw, B0_IMSK);
1885 imask &= ~portirq_msk[port];
1886 sky2_write32(hw, B0_IMSK, imask);
1887 sky2_read32(hw, B0_IMSK);
1888
6c83504f
SH		 1889 synchronize_irq(hw->pdev->irq);
1890 napi_synchronize(&hw->napi);
1891
0da6d7b3 1892 spin_lock_bh(&sky2->phy_lock);
b96936da 1893 sky2_phy_power_down(hw, port);
0da6d7b3 1894 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1895
264bb4fa
MM		 1896 sky2_tx_reset(hw, port);
1897
481cea4a
SH		 1898 /* Free any pending frames stuck in HW queue */
1899 sky2_tx_complete(sky2, sky2->tx_prod);
1900
cd28ab6a
SH		 1901 sky2_rx_clean(sky2);
1902
90bbebb4 1903 sky2_free_buffers(sky2);
1b537565 1904
cd28ab6a
SH		 1905 return 0;
1906}
1907
1908static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1909{
ea76e635 1910 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1911 return SPEED_1000;
1912
05745c4a
SH		 1913 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1914 if (aux & PHY_M_PS_SPEED_100)
1915 return SPEED_100;
1916 else
1917 return SPEED_10;
1918 }
cd28ab6a
SH		 1919
1920 switch (aux & PHY_M_PS_SPEED_MSK) {
1921 case PHY_M_PS_SPEED_1000:
1922 return SPEED_1000;
1923 case PHY_M_PS_SPEED_100:
1924 return SPEED_100;
1925 default:
1926 return SPEED_10;
1927 }
1928}
1929
1930static void sky2_link_up(struct sky2_port *sky2)
1931{
1932 struct sky2_hw *hw = sky2->hw;
1933 unsigned port = sky2->port;
1934 u16 reg;
16ad91e1
SH		 1935 static const char *fc_name[] = {
1936 [FC_NONE] = "none",
1937 [FC_TX] = "tx",
1938 [FC_RX] = "rx",
1939 [FC_BOTH] = "both",
1940 };
cd28ab6a 1941
cd28ab6a 1942 /* enable Rx/Tx */
2eaba1a2 1943 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1944 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1945 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1946
1947 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1948
1949 netif_carrier_on(sky2->netdev);
cd28ab6a 1950
75e80683 1951 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1952
cd28ab6a 1953 /* Turn on link LED */
793b883e 1954 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1955 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1956
1957 if (netif_msg_link(sky2))
1958 printk(KERN_INFO PFX
d571b694 1959 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1960 sky2->netdev->name, sky2->speed,
1961 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1962 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1963}
1964
1965static void sky2_link_down(struct sky2_port *sky2)
1966{
1967 struct sky2_hw *hw = sky2->hw;
1968 unsigned port = sky2->port;
1969 u16 reg;
1970
1971 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1972
1973 reg = gma_read16(hw, port, GM_GP_CTRL);
1974 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1975 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1976
cd28ab6a 1977 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1978
1979 /* Turn on link LED */
1980 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1981
1982 if (netif_msg_link(sky2))
1983 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1984
cd28ab6a
SH		 1985 sky2_phy_init(hw, port);
1986}
1987
16ad91e1
SH		 1988static enum flow_control sky2_flow(int rx, int tx)
1989{
1990 if (rx)
1991 return tx ? FC_BOTH : FC_RX;
1992 else
1993 return tx ? FC_TX : FC_NONE;
1994}
1995
793b883e
SH		 1996static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1997{
1998 struct sky2_hw *hw = sky2->hw;
1999 unsigned port = sky2->port;
da4c1ff4 2000 u16 advert, lpa;
793b883e 2001
da4c1ff4 2002 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2003 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2004 if (lpa & PHY_M_AN_RF) {
2005 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2006 return -1;
2007 }
2008
793b883e
SH		 2009 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2010 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2011 sky2->netdev->name);
2012 return -1;
2013 }
2014
793b883e 2015 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2016 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2017
da4c1ff4
SH		 2018 /* Since the pause result bits seem to in different positions on
2019 * different chips. look at registers.
2020 */
ea76e635 2021 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2022 /* Shift for bits in fiber PHY */
2023 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2024 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2025
2026 if (advert & ADVERTISE_1000XPAUSE)
2027 advert |= ADVERTISE_PAUSE_CAP;
2028 if (advert & ADVERTISE_1000XPSE_ASYM)
2029 advert |= ADVERTISE_PAUSE_ASYM;
2030 if (lpa & LPA_1000XPAUSE)
2031 lpa |= LPA_PAUSE_CAP;
2032 if (lpa & LPA_1000XPAUSE_ASYM)
2033 lpa |= LPA_PAUSE_ASYM;
2034 }
793b883e 2035
da4c1ff4
SH		 2036 sky2->flow_status = FC_NONE;
2037 if (advert & ADVERTISE_PAUSE_CAP) {
2038 if (lpa & LPA_PAUSE_CAP)
2039 sky2->flow_status = FC_BOTH;
2040 else if (advert & ADVERTISE_PAUSE_ASYM)
2041 sky2->flow_status = FC_RX;
2042 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2043 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2044 sky2->flow_status = FC_TX;
2045 }
793b883e 2046
16ad91e1 2047 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2048 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2049 sky2->flow_status = FC_NONE;
2eaba1a2 2050
da4c1ff4 2051 if (sky2->flow_status & FC_TX)
793b883e
SH		 2052 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2053 else
2054 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2055
2056 return 0;
2057}
cd28ab6a 2058
e07b1aa8
SH		 2059/* Interrupt from PHY */
2060static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2061{
e07b1aa8
SH		 2062 struct net_device *dev = hw->dev[port];
2063 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2064 u16 istatus, phystat;
2065
ebc646f6
SH		 2066 if (!netif_running(dev))
2067 return;
2068
e07b1aa8
SH		 2069 spin_lock(&sky2->phy_lock);
2070 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2071 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2072
cd28ab6a
SH		 2073 if (netif_msg_intr(sky2))
2074 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2075 sky2->netdev->name, istatus, phystat);
2076
0ea065e5 2077 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2078 if (sky2_autoneg_done(sky2, phystat) == 0)
2079 sky2_link_up(sky2);
2080 goto out;
2081 }
cd28ab6a 2082
793b883e
SH		 2083 if (istatus & PHY_M_IS_LSP_CHANGE)
2084 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2085
793b883e
SH		 2086 if (istatus & PHY_M_IS_DUP_CHANGE)
2087 sky2->duplex =
2088 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2089
793b883e
SH		 2090 if (istatus & PHY_M_IS_LST_CHANGE) {
2091 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2092 sky2_link_up(sky2);
793b883e
SH		 2093 else
2094 sky2_link_down(sky2);
cd28ab6a 2095 }
793b883e 2096out:
e07b1aa8 2097 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2098}
2099
62335ab0 2100/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2101 * and tx queue is full (stopped).
2102 */
cd28ab6a
SH		 2103static void sky2_tx_timeout(struct net_device *dev)
2104{
2105 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2106 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2107
2108 if (netif_msg_timer(sky2))
2109 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2110
8f24664d 2111 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2112 dev->name, sky2->tx_cons, sky2->tx_prod,
2113 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2114 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2115
81906791
SH		 2116 /* can't restart safely under softirq */
2117 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2118}
2119
2120static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2121{
6b1a3aef 2122 struct sky2_port *sky2 = netdev_priv(dev);
2123 struct sky2_hw *hw = sky2->hw;
b628ed98 2124 unsigned port = sky2->port;
6b1a3aef 2125 int err;
2126 u16 ctl, mode;
e07b1aa8 2127 u32 imask;
cd28ab6a
SH		 2128
2129 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2130 return -EINVAL;
2131
05745c4a
SH		 2132 if (new_mtu > ETH_DATA_LEN &&
2133 (hw->chip_id == CHIP_ID_YUKON_FE ||
2134 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2135 return -EINVAL;
2136
6b1a3aef 2137 if (!netif_running(dev)) {
2138 dev->mtu = new_mtu;
2139 return 0;
2140 }
2141
e07b1aa8 2142 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2143 sky2_write32(hw, B0_IMSK, 0);
2144
018d1c66 2145 dev->trans_start = jiffies; /* prevent tx timeout */
2146 netif_stop_queue(dev);
bea3348e 2147 napi_disable(&hw->napi);
018d1c66 2148
e07b1aa8
SH		 2149 synchronize_irq(hw->pdev->irq);
2150
39dbd958 2151 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2152 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2153
2154 ctl = gma_read16(hw, port, GM_GP_CTRL);
2155 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2156 sky2_rx_stop(sky2);
2157 sky2_rx_clean(sky2);
cd28ab6a
SH		 2158
2159 dev->mtu = new_mtu;
14d0263f 2160
6b1a3aef 2161 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2162 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2163
2164 if (dev->mtu > ETH_DATA_LEN)
2165 mode |= GM_SMOD_JUMBO_ENA;
2166
b628ed98 2167 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2168
b628ed98 2169 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2170
6b1a3aef 2171 err = sky2_rx_start(sky2);
e07b1aa8 2172 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2173
d1d08d12 2174 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2175 napi_enable(&hw->napi);
2176
1b537565
SH		 2177 if (err)
2178 dev_close(dev);
2179 else {
b628ed98 2180 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2181
1b537565
SH		 2182 netif_wake_queue(dev);
2183 }
2184
cd28ab6a
SH		 2185 return err;
2186}
2187
14d0263f
SH		 2188/* For small just reuse existing skb for next receive */
2189static struct sk_buff *receive_copy(struct sky2_port *sky2,
2190 const struct rx_ring_info *re,
2191 unsigned length)
2192{
2193 struct sk_buff *skb;
2194
2195 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2196 if (likely(skb)) {
2197 skb_reserve(skb, 2);
2198 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2199 length, PCI_DMA_FROMDEVICE);
d626f62b 2200 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2201 skb->ip_summed = re->skb->ip_summed;
2202 skb->csum = re->skb->csum;
2203 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2204 length, PCI_DMA_FROMDEVICE);
2205 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2206 skb_put(skb, length);
14d0263f
SH		 2207 }
2208 return skb;
2209}
2210
2211/* Adjust length of skb with fragments to match received data */
2212static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2213 unsigned int length)
2214{
2215 int i, num_frags;
2216 unsigned int size;
2217
2218 /* put header into skb */
2219 size = min(length, hdr_space);
2220 skb->tail += size;
2221 skb->len += size;
2222 length -= size;
2223
2224 num_frags = skb_shinfo(skb)->nr_frags;
2225 for (i = 0; i < num_frags; i++) {
2226 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2227
2228 if (length == 0) {
2229 /* don't need this page */
2230 __free_page(frag->page);
2231 --skb_shinfo(skb)->nr_frags;
2232 } else {
2233 size = min(length, (unsigned) PAGE_SIZE);
2234
2235 frag->size = size;
2236 skb->data_len += size;
2237 skb->truesize += size;
2238 skb->len += size;
2239 length -= size;
2240 }
2241 }
2242}
2243
2244/* Normal packet - take skb from ring element and put in a new one */
2245static struct sk_buff *receive_new(struct sky2_port *sky2,
2246 struct rx_ring_info *re,
2247 unsigned int length)
2248{
2249 struct sk_buff *skb, *nskb;
2250 unsigned hdr_space = sky2->rx_data_size;
2251
14d0263f
SH		 2252 /* Don't be tricky about reusing pages (yet) */
2253 nskb = sky2_rx_alloc(sky2);
2254 if (unlikely(!nskb))
2255 return NULL;
2256
2257 skb = re->skb;
2258 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2259
2260 prefetch(skb->data);
2261 re->skb = nskb;
454e6cb6
SH		 2262 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2263 dev_kfree_skb(nskb);
2264 re->skb = skb;
2265 return NULL;
2266 }
14d0263f
SH		 2267
2268 if (skb_shinfo(skb)->nr_frags)
2269 skb_put_frags(skb, hdr_space, length);
2270 else
489b10c1 2271 skb_put(skb, length);
14d0263f
SH		 2272 return skb;
2273}
2274
cd28ab6a
SH		 2275/*
2276 * Receive one packet.
d571b694 2277 * For larger packets, get new buffer.
cd28ab6a 2278 */
497d7c86 2279static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2280 u16 length, u32 status)
2281{
497d7c86 2282 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2283 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2284 struct sk_buff *skb = NULL;
d6532232
SH		 2285 u16 count = (status & GMR_FS_LEN) >> 16;
2286
2287#ifdef SKY2_VLAN_TAG_USED
2288 /* Account for vlan tag */
2289 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2290 count -= VLAN_HLEN;
2291#endif
cd28ab6a
SH		 2292
2293 if (unlikely(netif_msg_rx_status(sky2)))
2294 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2295 dev->name, sky2->rx_next, status, length);
cd28ab6a 2296
793b883e 2297 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2298 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2299
3b12e014
SH		 2300 /* This chip has hardware problems that generates bogus status.
2301 * So do only marginal checking and expect higher level protocols
2302 * to handle crap frames.
2303 */
2304 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2305 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2306 length != count)
2307 goto okay;
2308
42eeea01 2309 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2310 goto error;
2311
42eeea01 2312 if (!(status & GMR_FS_RX_OK))
2313 goto resubmit;
2314
d6532232
SH		 2315 /* if length reported by DMA does not match PHY, packet was truncated */
2316 if (length != count)
3b12e014 2317 goto len_error;
71749531 2318
3b12e014 2319okay:
14d0263f
SH		 2320 if (length < copybreak)
2321 skb = receive_copy(sky2, re, length);
2322 else
2323 skb = receive_new(sky2, re, length);
793b883e 2324resubmit:
14d0263f 2325 sky2_rx_submit(sky2, re);
79e57d32 2326
cd28ab6a
SH		 2327 return skb;
2328
3b12e014 2329len_error:
71749531
SH		 2330 /* Truncation of overlength packets
2331 causes PHY length to not match MAC length */
7138a0f5 2332 ++dev->stats.rx_length_errors;
d6532232 2333 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2334 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2335 dev->name, status, length);
d6532232 2336 goto resubmit;
71749531 2337
cd28ab6a 2338error:
7138a0f5 2339 ++dev->stats.rx_errors;
b6d77734 2340 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2341 dev->stats.rx_over_errors++;
b6d77734
SH		 2342 goto resubmit;
2343 }
6e15b712 2344
3be92a70 2345 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2346 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2347 dev->name, status, length);
793b883e
SH		 2348
2349 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2350 dev->stats.rx_length_errors++;
cd28ab6a 2351 if (status & GMR_FS_FRAGMENT)
7138a0f5 2352 dev->stats.rx_frame_errors++;
cd28ab6a 2353 if (status & GMR_FS_CRC_ERR)
7138a0f5 2354 dev->stats.rx_crc_errors++;
79e57d32 2355
793b883e 2356 goto resubmit;
cd28ab6a
SH		 2357}
2358
e07b1aa8
SH		 2359/* Transmit complete */
2360static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2361{
e07b1aa8 2362 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2363
49d4b8ba 2364 if (netif_running(dev))
e07b1aa8 2365 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2366}
2367
37e5a243
SH		 2368static inline void sky2_skb_rx(const struct sky2_port *sky2,
2369 u32 status, struct sk_buff *skb)
2370{
2371#ifdef SKY2_VLAN_TAG_USED
2372 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2373 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2374 if (skb->ip_summed == CHECKSUM_NONE)
2375 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2376 else
2377 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2378 vlan_tag, skb);
2379 return;
2380 }
2381#endif
2382 if (skb->ip_summed == CHECKSUM_NONE)
2383 netif_receive_skb(skb);
2384 else
2385 napi_gro_receive(&sky2->hw->napi, skb);
2386}
2387
bf15fe99
SH		 2388static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2389 unsigned packets, unsigned bytes)
2390{
2391 if (packets) {
2392 struct net_device *dev = hw->dev[port];
2393
2394 dev->stats.rx_packets += packets;
2395 dev->stats.rx_bytes += bytes;
2396 dev->last_rx = jiffies;
2397 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2398 }
2399}
2400
e07b1aa8 2401/* Process status response ring */
26691830 2402static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2403{
e07b1aa8 2404 int work_done = 0;
bf15fe99
SH		 2405 unsigned int total_bytes[2] = { 0 };
2406 unsigned int total_packets[2] = { 0 };
a8fd6266 2407
af2a58ac 2408 rmb();
26691830 2409 do {
55c9dd35 2410 struct sky2_port *sky2;
13210ce5 2411 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2412 unsigned port;
13210ce5 2413 struct net_device *dev;
cd28ab6a 2414 struct sk_buff *skb;
cd28ab6a
SH		 2415 u32 status;
2416 u16 length;
ab5adecb
SH		 2417 u8 opcode = le->opcode;
2418
2419 if (!(opcode & HW_OWNER))
2420 break;
cd28ab6a 2421
cb5d9547 2422 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2423
ab5adecb 2424 port = le->css & CSS_LINK_BIT;
69161611 2425 dev = hw->dev[port];
13210ce5 2426 sky2 = netdev_priv(dev);
f65b138c
SH		 2427 length = le16_to_cpu(le->length);
2428 status = le32_to_cpu(le->status);
cd28ab6a 2429
ab5adecb
SH		 2430 le->opcode = 0;
2431 switch (opcode & ~HW_OWNER) {
cd28ab6a 2432 case OP_RXSTAT:
bf15fe99
SH		 2433 total_packets[port]++;
2434 total_bytes[port] += length;
497d7c86 2435 skb = sky2_receive(dev, length, status);
3225b919 2436 if (unlikely(!skb)) {
7138a0f5 2437 dev->stats.rx_dropped++;
55c9dd35 2438 break;
3225b919 2439 }
13210ce5 2440
69161611 2441 /* This chip reports checksum status differently */
05745c4a 2442 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2443 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2444 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2445 (le->css & CSS_TCPUDPCSOK))
2446 skb->ip_summed = CHECKSUM_UNNECESSARY;
2447 else
2448 skb->ip_summed = CHECKSUM_NONE;
2449 }
2450
13210ce5 2451 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2452
37e5a243 2453 sky2_skb_rx(sky2, status, skb);
13210ce5 2454
22e11703 2455 /* Stop after net poll weight */
13210ce5 2456 if (++work_done >= to_do)
2457 goto exit_loop;
cd28ab6a
SH		 2458 break;
2459
d1f13708 2460#ifdef SKY2_VLAN_TAG_USED
2461 case OP_RXVLAN:
2462 sky2->rx_tag = length;
2463 break;
2464
2465 case OP_RXCHKSVLAN:
2466 sky2->rx_tag = length;
2467 /* fall through */
2468#endif
cd28ab6a 2469 case OP_RXCHKS:
0ea065e5 2470 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
87418307
SH		 2471 break;
2472
05745c4a
SH		 2473 /* If this happens then driver assuming wrong format */
2474 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2475 if (net_ratelimit())
2476 printk(KERN_NOTICE "%s: unexpected"
2477 " checksum status\n",
2478 dev->name);
69161611 2479 break;
05745c4a 2480 }
69161611 2481
87418307
SH		 2482 /* Both checksum counters are programmed to start at
2483 * the same offset, so unless there is a problem they
2484 * should match. This failure is an early indication that
2485 * hardware receive checksumming won't work.
2486 */
2487 if (likely(status >> 16 == (status & 0xffff))) {
2488 skb = sky2->rx_ring[sky2->rx_next].skb;
2489 skb->ip_summed = CHECKSUM_COMPLETE;
b9389796 2490 skb->csum = le16_to_cpu(status);
87418307
SH		 2491 } else {
2492 printk(KERN_NOTICE PFX "%s: hardware receive "
2493 "checksum problem (status = %#x)\n",
2494 dev->name, status);
0ea065e5
SH		 2495 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2496
87418307 2497 sky2_write32(sky2->hw,
69161611 2498 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2499 BMU_DIS_RX_CHKSUM);
2500 }
cd28ab6a
SH		 2501 break;
2502
2503 case OP_TXINDEXLE:
13b97b74 2504 /* TX index reports status for both ports */
f55925d7 2505 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2506 if (hw->dev[1])
2507 sky2_tx_done(hw->dev[1],
2508 ((status >> 24) & 0xff)
2509 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2510 break;
2511
cd28ab6a
SH		 2512 default:
2513 if (net_ratelimit())
793b883e 2514 printk(KERN_WARNING PFX
ab5adecb 2515 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2516 }
26691830 2517 } while (hw->st_idx != idx);
cd28ab6a 2518
fe2a24df
SH		 2519 /* Fully processed status ring so clear irq */
2520 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2521
13210ce5 2522exit_loop:
bf15fe99
SH		 2523 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2524 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2525
e07b1aa8 2526 return work_done;
cd28ab6a
SH		 2527}
2528
2529static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2530{
2531 struct net_device *dev = hw->dev[port];
2532
3be92a70
SH		 2533 if (net_ratelimit())
2534 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2535 dev->name, status);
cd28ab6a
SH		 2536
2537 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2538 if (net_ratelimit())
2539 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2540 dev->name);
cd28ab6a
SH		 2541 /* Clear IRQ */
2542 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2543 }
2544
2545 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2546 if (net_ratelimit())
2547 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2548 dev->name);
cd28ab6a
SH		 2549
2550 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2551 }
2552
2553 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2554 if (net_ratelimit())
2555 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2556 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2557 }
2558
2559 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2560 if (net_ratelimit())
2561 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2562 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2563 }
2564
2565 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2566 if (net_ratelimit())
2567 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2568 dev->name);
cd28ab6a
SH		 2569 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2570 }
2571}
2572
2573static void sky2_hw_intr(struct sky2_hw *hw)
2574{
555382cb 2575 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2576 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2577 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2578
2579 status &= hwmsk;
cd28ab6a 2580
793b883e 2581 if (status & Y2_IS_TIST_OV)
cd28ab6a 2582 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2583
2584 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2585 u16 pci_err;
2586
82637e80 2587 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2588 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2589 if (net_ratelimit())
555382cb 2590 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2591 pci_err);
cd28ab6a 2592
b32f40c4 2593 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2594 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2595 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2596 }
2597
2598 if (status & Y2_IS_PCI_EXP) {
d571b694 2599 /* PCI-Express uncorrectable Error occurred */
555382cb 2600 u32 err;
cd28ab6a 2601
82637e80 2602 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2603 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2604 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2605 0xfffffffful);
3be92a70 2606 if (net_ratelimit())
555382cb 2607 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2608
7782c8c4 2609 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2610 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2611 }
2612
2613 if (status & Y2_HWE_L1_MASK)
2614 sky2_hw_error(hw, 0, status);
2615 status >>= 8;
2616 if (status & Y2_HWE_L1_MASK)
2617 sky2_hw_error(hw, 1, status);
2618}
2619
2620static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2621{
2622 struct net_device *dev = hw->dev[port];
2623 struct sky2_port *sky2 = netdev_priv(dev);
2624 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2625
2626 if (netif_msg_intr(sky2))
2627 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2628 dev->name, status);
2629
a3caeada
SH		 2630 if (status & GM_IS_RX_CO_OV)
2631 gma_read16(hw, port, GM_RX_IRQ_SRC);
2632
2633 if (status & GM_IS_TX_CO_OV)
2634 gma_read16(hw, port, GM_TX_IRQ_SRC);
2635
cd28ab6a 2636 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2637 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2638 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2639 }
2640
2641 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2642 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2643 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2644 }
cd28ab6a
SH		 2645}
2646
40b01727 2647/* This should never happen it is a bug. */
c119731d 2648static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2649{
2650 struct net_device *dev = hw->dev[port];
c119731d 2651 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2652
c119731d
SH		 2653 dev_err(&hw->pdev->dev, PFX
2654 "%s: descriptor error q=%#x get=%u put=%u\n",
2655 dev->name, (unsigned) q, (unsigned) idx,
2656 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2657
40b01727 2658 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2659}
cd28ab6a 2660
75e80683
SH		 2661static int sky2_rx_hung(struct net_device *dev)
2662{
2663 struct sky2_port *sky2 = netdev_priv(dev);
2664 struct sky2_hw *hw = sky2->hw;
2665 unsigned port = sky2->port;
2666 unsigned rxq = rxqaddr[port];
2667 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2668 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2669 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2670 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2671
2672 /* If idle and MAC or PCI is stuck */
2673 if (sky2->check.last == dev->last_rx &&
2674 ((mac_rp == sky2->check.mac_rp &&
2675 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2676 /* Check if the PCI RX hang */
2677 (fifo_rp == sky2->check.fifo_rp &&
2678 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2679 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2680 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2681 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2682 return 1;
2683 } else {
2684 sky2->check.last = dev->last_rx;
2685 sky2->check.mac_rp = mac_rp;
2686 sky2->check.mac_lev = mac_lev;
2687 sky2->check.fifo_rp = fifo_rp;
2688 sky2->check.fifo_lev = fifo_lev;
2689 return 0;
2690 }
2691}
2692
32c2c300 2693static void sky2_watchdog(unsigned long arg)
d27ed387 2694{
01bd7564 2695 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2696
75e80683 2697 /* Check for lost IRQ once a second */
32c2c300 2698 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2699 napi_schedule(&hw->napi);
75e80683
SH		 2700 } else {
2701 int i, active = 0;
2702
2703 for (i = 0; i < hw->ports; i++) {
bea3348e 2704 struct net_device *dev = hw->dev[i];
75e80683
SH		 2705 if (!netif_running(dev))
2706 continue;
2707 ++active;
2708
2709 /* For chips with Rx FIFO, check if stuck */
39dbd958 2710 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2711 sky2_rx_hung(dev)) {
2712 pr_info(PFX "%s: receiver hang detected\n",
2713 dev->name);
2714 schedule_work(&hw->restart_work);
2715 return;
2716 }
2717 }
2718
2719 if (active == 0)
2720 return;
32c2c300 2721 }
01bd7564 2722
75e80683 2723 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2724}
2725
40b01727
SH		 2726/* Hardware/software error handling */
2727static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2728{
40b01727
SH		 2729 if (net_ratelimit())
2730 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2731
1e5f1283
SH		 2732 if (status & Y2_IS_HW_ERR)
2733 sky2_hw_intr(hw);
d257924e 2734
1e5f1283
SH		 2735 if (status & Y2_IS_IRQ_MAC1)
2736 sky2_mac_intr(hw, 0);
cd28ab6a 2737
1e5f1283
SH		 2738 if (status & Y2_IS_IRQ_MAC2)
2739 sky2_mac_intr(hw, 1);
cd28ab6a 2740
1e5f1283 2741 if (status & Y2_IS_CHK_RX1)
c119731d 2742 sky2_le_error(hw, 0, Q_R1);
d257924e 2743
1e5f1283 2744 if (status & Y2_IS_CHK_RX2)
c119731d 2745 sky2_le_error(hw, 1, Q_R2);
d257924e 2746
1e5f1283 2747 if (status & Y2_IS_CHK_TXA1)
c119731d 2748 sky2_le_error(hw, 0, Q_XA1);
d257924e 2749
1e5f1283 2750 if (status & Y2_IS_CHK_TXA2)
c119731d 2751 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2752}
2753
bea3348e 2754static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2755{
bea3348e 2756 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2757 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2758 int work_done = 0;
26691830 2759 u16 idx;
40b01727
SH		 2760
2761 if (unlikely(status & Y2_IS_ERROR))
2762 sky2_err_intr(hw, status);
2763
2764 if (status & Y2_IS_IRQ_PHY1)
2765 sky2_phy_intr(hw, 0);
2766
2767 if (status & Y2_IS_IRQ_PHY2)
2768 sky2_phy_intr(hw, 1);
cd28ab6a 2769
26691830
SH		 2770 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2771 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2772
2773 if (work_done >= work_limit)
26691830
SH		 2774 goto done;
2775 }
6f535763 2776
26691830
SH		 2777 napi_complete(napi);
2778 sky2_read32(hw, B0_Y2_SP_LISR);
2779done:
6f535763 2780
bea3348e 2781 return work_done;
e07b1aa8
SH		 2782}
2783
7d12e780 2784static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2785{
2786 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2787 u32 status;
2788
2789 /* Reading this mask interrupts as side effect */
2790 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2791 if (status == 0 || status == ~0)
2792 return IRQ_NONE;
793b883e 2793
e07b1aa8 2794 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2795
2796 napi_schedule(&hw->napi);
793b883e 2797
cd28ab6a
SH		 2798 return IRQ_HANDLED;
2799}
2800
2801#ifdef CONFIG_NET_POLL_CONTROLLER
2802static void sky2_netpoll(struct net_device *dev)
2803{
2804 struct sky2_port *sky2 = netdev_priv(dev);
2805
bea3348e 2806 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2807}
2808#endif
2809
2810/* Chip internal frequency for clock calculations */
05745c4a 2811static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2812{
793b883e 2813 switch (hw->chip_id) {
cd28ab6a 2814 case CHIP_ID_YUKON_EC:
5a5b1ea0 2815 case CHIP_ID_YUKON_EC_U:
93745494 2816 case CHIP_ID_YUKON_EX:
ed4d4161 2817 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2818 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2819 return 125;
2820
cd28ab6a 2821 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2822 return 100;
2823
2824 case CHIP_ID_YUKON_FE_P:
2825 return 50;
2826
2827 case CHIP_ID_YUKON_XL:
2828 return 156;
2829
2830 default:
2831 BUG();
cd28ab6a
SH		 2832 }
2833}
2834
fb17358f 2835static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2836{
fb17358f 2837 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2838}
2839
fb17358f 2840static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2841{
fb17358f 2842 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2843}
2844
fb17358f 2845
e3173832 2846static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2847{
b89165f2 2848 u8 t8;
cd28ab6a 2849
167f53d0 2850 /* Enable all clocks and check for bad PCI access */
b32f40c4 2851 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2852
cd28ab6a 2853 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2854
cd28ab6a 2855 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2856 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2857
2858 switch(hw->chip_id) {
2859 case CHIP_ID_YUKON_XL:
39dbd958 2860 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2861 break;
2862
2863 case CHIP_ID_YUKON_EC_U:
2864 hw->flags = SKY2_HW_GIGABIT
2865 | SKY2_HW_NEWER_PHY
2866 | SKY2_HW_ADV_POWER_CTL;
2867 break;
2868
2869 case CHIP_ID_YUKON_EX:
2870 hw->flags = SKY2_HW_GIGABIT
2871 | SKY2_HW_NEWER_PHY
2872 | SKY2_HW_NEW_LE
2873 | SKY2_HW_ADV_POWER_CTL;
2874
2875 /* New transmit checksum */
2876 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2877 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2878 break;
2879
2880 case CHIP_ID_YUKON_EC:
2881 /* This rev is really old, and requires untested workarounds */
2882 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2883 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2884 return -EOPNOTSUPP;
2885 }
39dbd958 2886 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2887 break;
2888
2889 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2890 break;
2891
05745c4a
SH		 2892 case CHIP_ID_YUKON_FE_P:
2893 hw->flags = SKY2_HW_NEWER_PHY
2894 | SKY2_HW_NEW_LE
2895 | SKY2_HW_AUTO_TX_SUM
2896 | SKY2_HW_ADV_POWER_CTL;
2897 break;
ed4d4161
SH		 2898
2899 case CHIP_ID_YUKON_SUPR:
2900 hw->flags = SKY2_HW_GIGABIT
2901 | SKY2_HW_NEWER_PHY
2902 | SKY2_HW_NEW_LE
2903 | SKY2_HW_AUTO_TX_SUM
2904 | SKY2_HW_ADV_POWER_CTL;
2905 break;
2906
0ce8b98d
SH		 2907 case CHIP_ID_YUKON_UL_2:
2908 hw->flags = SKY2_HW_GIGABIT
2909 | SKY2_HW_ADV_POWER_CTL;
2910 break;
2911
ea76e635 2912 default:
b02a9258
SH		 2913 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2914 hw->chip_id);
cd28ab6a
SH		 2915 return -EOPNOTSUPP;
2916 }
2917
ea76e635
SH		 2918 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2919 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2920 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2921
e3173832
SH		 2922 hw->ports = 1;
2923 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2924 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2925 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2926 ++hw->ports;
2927 }
2928
2929 return 0;
2930}
2931
2932static void sky2_reset(struct sky2_hw *hw)
2933{
555382cb 2934 struct pci_dev *pdev = hw->pdev;
e3173832 2935 u16 status;
555382cb
SH		 2936 int i, cap;
2937 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2938
cd28ab6a 2939 /* disable ASF */
4f44d8ba
SH		 2940 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2941 status = sky2_read16(hw, HCU_CCSR);
2942 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2943 HCU_CCSR_UC_STATE_MSK);
2944 sky2_write16(hw, HCU_CCSR, status);
2945 } else
2946 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2947 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2948
2949 /* do a SW reset */
2950 sky2_write8(hw, B0_CTST, CS_RST_SET);
2951 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2952
ac93a394
SH		 2953 /* allow writes to PCI config */
2954 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2955
cd28ab6a 2956 /* clear PCI errors, if any */
b32f40c4 2957 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2958 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2959 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2960
2961 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2962
555382cb
SH		 2963 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2964 if (cap) {
7782c8c4
SH		 2965 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2966 0xfffffffful);
555382cb
SH		 2967
2968 /* If error bit is stuck on ignore it */
2969 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2970 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2971 else
555382cb
SH		 2972 hwe_mask |= Y2_IS_PCI_EXP;
2973 }
cd28ab6a 2974
ae306cca 2975 sky2_power_on(hw);
82637e80 2976 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2977
2978 for (i = 0; i < hw->ports; i++) {
2979 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2980 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2981
ed4d4161
SH		 2982 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2983 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2984 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2985 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2986 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2987 }
2988
793b883e
SH		 2989 /* Clear I2C IRQ noise */
2990 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2991
2992 /* turn off hardware timer (unused) */
2993 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2994 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2995
69634ee7
SH		 2996 /* Turn off descriptor polling */
2997 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2998
2999 /* Turn off receive timestamp */
3000 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3001 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3002
3003 /* enable the Tx Arbiters */
3004 for (i = 0; i < hw->ports; i++)
3005 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3006
3007 /* Initialize ram interface */
3008 for (i = 0; i < hw->ports; i++) {
793b883e 3009 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3010
3011 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3012 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3013 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3014 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3015 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3016 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3017 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3018 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3019 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3020 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3021 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3022 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3023 }
3024
555382cb 3025 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3026
cd28ab6a 3027 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3028 sky2_gmac_reset(hw, i);
cd28ab6a 3029
cd28ab6a
SH		 3030 memset(hw->st_le, 0, STATUS_LE_BYTES);
3031 hw->st_idx = 0;
3032
3033 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3034 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3035
3036 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3037 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3038
3039 /* Set the list last index */
793b883e 3040 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3041
290d4de5
SH		 3042 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3043 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3044
290d4de5
SH		 3045 /* set Status-FIFO ISR watermark */
3046 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3047 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3048 else
3049 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3050
290d4de5 3051 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3052 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3053 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3054
793b883e 3055 /* enable status unit */
cd28ab6a
SH		 3056 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3057
3058 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3059 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3060 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3061}
3062
af18d8b8
SH		 3063/* Take device down (offline).
3064 * Equivalent to doing dev_stop() but this does not
3065 * inform upper layers of the transistion.
3066 */
3067static void sky2_detach(struct net_device *dev)
3068{
3069 if (netif_running(dev)) {
3070 netif_device_detach(dev); /* stop txq */
3071 sky2_down(dev);
3072 }
3073}
3074
3075/* Bring device back after doing sky2_detach */
3076static int sky2_reattach(struct net_device *dev)
3077{
3078 int err = 0;
3079
3080 if (netif_running(dev)) {
3081 err = sky2_up(dev);
3082 if (err) {
3083 printk(KERN_INFO PFX "%s: could not restart %d\n",
3084 dev->name, err);
3085 dev_close(dev);
3086 } else {
3087 netif_device_attach(dev);
3088 sky2_set_multicast(dev);
3089 }
3090 }
3091
3092 return err;
3093}
3094
81906791
SH		 3095static void sky2_restart(struct work_struct *work)
3096{
3097 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3098 int i;
81906791 3099
81906791 3100 rtnl_lock();
af18d8b8
SH		 3101 for (i = 0; i < hw->ports; i++)
3102 sky2_detach(hw->dev[i]);
81906791 3103
8cfcbe99
SH		 3104 napi_disable(&hw->napi);
3105 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3106 sky2_reset(hw);
3107 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3108 napi_enable(&hw->napi);
81906791 3109
af18d8b8
SH		 3110 for (i = 0; i < hw->ports; i++)
3111 sky2_reattach(hw->dev[i]);
81906791 3112
81906791
SH		 3113 rtnl_unlock();
3114}
3115
e3173832
SH		 3116static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3117{
3118 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3119}
3120
3121static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3122{
3123 const struct sky2_port *sky2 = netdev_priv(dev);
3124
3125 wol->supported = sky2_wol_supported(sky2->hw);
3126 wol->wolopts = sky2->wol;
3127}
3128
3129static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3130{
3131 struct sky2_port *sky2 = netdev_priv(dev);
3132 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3133
9d731d77
RW		 3134 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3135 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3136 return -EOPNOTSUPP;
3137
3138 sky2->wol = wol->wolopts;
3139
05745c4a
SH		 3140 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3141 hw->chip_id == CHIP_ID_YUKON_EX ||
3142 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3143 sky2_write32(hw, B0_CTST, sky2->wol
3144 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3145
9d731d77
RW		 3146 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3147
e3173832
SH		 3148 if (!netif_running(dev))
3149 sky2_wol_init(sky2);
cd28ab6a
SH		 3150 return 0;
3151}
3152
28bd181a 3153static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3154{
b89165f2
SH		 3155 if (sky2_is_copper(hw)) {
3156 u32 modes = SUPPORTED_10baseT_Half
3157 | SUPPORTED_10baseT_Full
3158 | SUPPORTED_100baseT_Half
3159 | SUPPORTED_100baseT_Full
3160 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3161
ea76e635 3162 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3163 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3164 | SUPPORTED_1000baseT_Full;
3165 return modes;
cd28ab6a 3166 } else
b89165f2
SH		 3167 return SUPPORTED_1000baseT_Half
3168 | SUPPORTED_1000baseT_Full
3169 | SUPPORTED_Autoneg
3170 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3171}
3172
793b883e 3173static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3174{
3175 struct sky2_port *sky2 = netdev_priv(dev);
3176 struct sky2_hw *hw = sky2->hw;
3177
3178 ecmd->transceiver = XCVR_INTERNAL;
3179 ecmd->supported = sky2_supported_modes(hw);
3180 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3181 if (sky2_is_copper(hw)) {
cd28ab6a 3182 ecmd->port = PORT_TP;
b89165f2
SH		 3183 ecmd->speed = sky2->speed;
3184 } else {
3185 ecmd->speed = SPEED_1000;
cd28ab6a 3186 ecmd->port = PORT_FIBRE;
b89165f2 3187 }
cd28ab6a
SH		 3188
3189 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3190 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3191 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3192 ecmd->duplex = sky2->duplex;
3193 return 0;
3194}
3195
3196static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3197{
3198 struct sky2_port *sky2 = netdev_priv(dev);
3199 const struct sky2_hw *hw = sky2->hw;
3200 u32 supported = sky2_supported_modes(hw);
3201
3202 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3203 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3204 ecmd->advertising = supported;
3205 sky2->duplex = -1;
3206 sky2->speed = -1;
3207 } else {
3208 u32 setting;
3209
793b883e 3210 switch (ecmd->speed) {
cd28ab6a
SH		 3211 case SPEED_1000:
3212 if (ecmd->duplex == DUPLEX_FULL)
3213 setting = SUPPORTED_1000baseT_Full;
3214 else if (ecmd->duplex == DUPLEX_HALF)
3215 setting = SUPPORTED_1000baseT_Half;
3216 else
3217 return -EINVAL;
3218 break;
3219 case SPEED_100:
3220 if (ecmd->duplex == DUPLEX_FULL)
3221 setting = SUPPORTED_100baseT_Full;
3222 else if (ecmd->duplex == DUPLEX_HALF)
3223 setting = SUPPORTED_100baseT_Half;
3224 else
3225 return -EINVAL;
3226 break;
3227
3228 case SPEED_10:
3229 if (ecmd->duplex == DUPLEX_FULL)
3230 setting = SUPPORTED_10baseT_Full;
3231 else if (ecmd->duplex == DUPLEX_HALF)
3232 setting = SUPPORTED_10baseT_Half;
3233 else
3234 return -EINVAL;
3235 break;
3236 default:
3237 return -EINVAL;
3238 }
3239
3240 if ((setting & supported) == 0)
3241 return -EINVAL;
3242
3243 sky2->speed = ecmd->speed;
3244 sky2->duplex = ecmd->duplex;
0ea065e5 3245 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3246 }
3247
cd28ab6a
SH		 3248 sky2->advertising = ecmd->advertising;
3249
d1b139c0 3250 if (netif_running(dev)) {
1b537565 3251 sky2_phy_reinit(sky2);
d1b139c0
SH		 3252 sky2_set_multicast(dev);
3253 }
cd28ab6a
SH		 3254
3255 return 0;
3256}
3257
3258static void sky2_get_drvinfo(struct net_device *dev,
3259 struct ethtool_drvinfo *info)
3260{
3261 struct sky2_port *sky2 = netdev_priv(dev);
3262
3263 strcpy(info->driver, DRV_NAME);
3264 strcpy(info->version, DRV_VERSION);
3265 strcpy(info->fw_version, "N/A");
3266 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3267}
3268
3269static const struct sky2_stat {
793b883e
SH		 3270 char name[ETH_GSTRING_LEN];
3271 u16 offset;
cd28ab6a
SH		 3272} sky2_stats[] = {
3273 { "tx_bytes", GM_TXO_OK_HI },
3274 { "rx_bytes", GM_RXO_OK_HI },
3275 { "tx_broadcast", GM_TXF_BC_OK },
3276 { "rx_broadcast", GM_RXF_BC_OK },
3277 { "tx_multicast", GM_TXF_MC_OK },
3278 { "rx_multicast", GM_RXF_MC_OK },
3279 { "tx_unicast", GM_TXF_UC_OK },
3280 { "rx_unicast", GM_RXF_UC_OK },
3281 { "tx_mac_pause", GM_TXF_MPAUSE },
3282 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3283 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3284 { "late_collision",GM_TXF_LAT_COL },
3285 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3286 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3287 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3288
d2604540 3289 { "rx_short", GM_RXF_SHT },
cd28ab6a 3290 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3291 { "rx_64_byte_packets", GM_RXF_64B },
3292 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3293 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3294 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3295 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3296 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3297 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3298 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3299 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3300 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3301 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3302
3303 { "tx_64_byte_packets", GM_TXF_64B },
3304 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3305 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3306 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3307 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3308 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3309 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3310 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3311};
3312
cd28ab6a
SH		 3313static u32 sky2_get_rx_csum(struct net_device *dev)
3314{
3315 struct sky2_port *sky2 = netdev_priv(dev);
3316
0ea065e5 3317 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3318}
3319
3320static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3321{
3322 struct sky2_port *sky2 = netdev_priv(dev);
3323
0ea065e5
SH		 3324 if (data)
3325 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3326 else
3327 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3328
cd28ab6a
SH		 3329 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3330 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3331
3332 return 0;
3333}
3334
3335static u32 sky2_get_msglevel(struct net_device *netdev)
3336{
3337 struct sky2_port *sky2 = netdev_priv(netdev);
3338 return sky2->msg_enable;
3339}
3340
9a7ae0a9
SH		 3341static int sky2_nway_reset(struct net_device *dev)
3342{
3343 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3344
0ea065e5 3345 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3346 return -EINVAL;
3347
1b537565 3348 sky2_phy_reinit(sky2);
d1b139c0 3349 sky2_set_multicast(dev);
9a7ae0a9
SH		 3350
3351 return 0;
3352}
3353
793b883e 3354static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3355{
3356 struct sky2_hw *hw = sky2->hw;
3357 unsigned port = sky2->port;
3358 int i;
3359
3360 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3361 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3362 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3363 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3364
793b883e 3365 for (i = 2; i < count; i++)
cd28ab6a
SH		 3366 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3367}
3368
cd28ab6a
SH		 3369static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3370{
3371 struct sky2_port *sky2 = netdev_priv(netdev);
3372 sky2->msg_enable = value;
3373}
3374
b9f2c044 3375static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3376{
b9f2c044
JG		 3377 switch (sset) {
3378 case ETH_SS_STATS:
3379 return ARRAY_SIZE(sky2_stats);
3380 default:
3381 return -EOPNOTSUPP;
3382 }
cd28ab6a
SH		 3383}
3384
3385static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3386 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3387{
3388 struct sky2_port *sky2 = netdev_priv(dev);
3389
793b883e 3390 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3391}
3392
793b883e 3393static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3394{
3395 int i;
3396
3397 switch (stringset) {
3398 case ETH_SS_STATS:
3399 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3400 memcpy(data + i * ETH_GSTRING_LEN,
3401 sky2_stats[i].name, ETH_GSTRING_LEN);
3402 break;
3403 }
3404}
3405
cd28ab6a
SH		 3406static int sky2_set_mac_address(struct net_device *dev, void *p)
3407{
3408 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3409 struct sky2_hw *hw = sky2->hw;
3410 unsigned port = sky2->port;
3411 const struct sockaddr *addr = p;
cd28ab6a
SH		 3412
3413 if (!is_valid_ether_addr(addr->sa_data))
3414 return -EADDRNOTAVAIL;
3415
cd28ab6a 3416 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3417 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3418 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3419 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3420 dev->dev_addr, ETH_ALEN);
1b537565 3421
a8ab1ec0
SH		 3422 /* virtual address for data */
3423 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3424
3425 /* physical address: used for pause frames */
3426 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3427
3428 return 0;
cd28ab6a
SH		 3429}
3430
a052b52f
SH		 3431static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3432{
3433 u32 bit;
3434
3435 bit = ether_crc(ETH_ALEN, addr) & 63;
3436 filter[bit >> 3] |= 1 << (bit & 7);
3437}
3438
cd28ab6a
SH		 3439static void sky2_set_multicast(struct net_device *dev)
3440{
3441 struct sky2_port *sky2 = netdev_priv(dev);
3442 struct sky2_hw *hw = sky2->hw;
3443 unsigned port = sky2->port;
3444 struct dev_mc_list *list = dev->mc_list;
3445 u16 reg;
3446 u8 filter[8];
a052b52f
SH		 3447 int rx_pause;
3448 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3449
a052b52f 3450 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3451 memset(filter, 0, sizeof(filter));
3452
3453 reg = gma_read16(hw, port, GM_RX_CTRL);
3454 reg |= GM_RXCR_UCF_ENA;
3455
d571b694 3456 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3457 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3458 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3459 memset(filter, 0xff, sizeof(filter));
a052b52f 3460 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3461 reg &= ~GM_RXCR_MCF_ENA;
3462 else {
3463 int i;
3464 reg |= GM_RXCR_MCF_ENA;
3465
a052b52f
SH		 3466 if (rx_pause)
3467 sky2_add_filter(filter, pause_mc_addr);
3468
3469 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3470 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3471 }
3472
cd28ab6a 3473 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3474 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3475 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3476 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3477 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3478 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3479 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3480 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3481
3482 gma_write16(hw, port, GM_RX_CTRL, reg);
3483}
3484
3485/* Can have one global because blinking is controlled by
3486 * ethtool and that is always under RTNL mutex
3487 */
a84d0a3d 3488static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3489{
a84d0a3d
SH		 3490 struct sky2_hw *hw = sky2->hw;
3491 unsigned port = sky2->port;
793b883e 3492
a84d0a3d
SH		 3493 spin_lock_bh(&sky2->phy_lock);
3494 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3495 hw->chip_id == CHIP_ID_YUKON_EX ||
3496 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3497 u16 pg;
793b883e
SH		 3498 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3499 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3500
a84d0a3d
SH		 3501 switch (mode) {
3502 case MO_LED_OFF:
3503 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3504 PHY_M_LEDC_LOS_CTRL(8) |
3505 PHY_M_LEDC_INIT_CTRL(8) |
3506 PHY_M_LEDC_STA1_CTRL(8) |
3507 PHY_M_LEDC_STA0_CTRL(8));
3508 break;
3509 case MO_LED_ON:
3510 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3511 PHY_M_LEDC_LOS_CTRL(9) |
3512 PHY_M_LEDC_INIT_CTRL(9) |
3513 PHY_M_LEDC_STA1_CTRL(9) |
3514 PHY_M_LEDC_STA0_CTRL(9));
3515 break;
3516 case MO_LED_BLINK:
3517 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3518 PHY_M_LEDC_LOS_CTRL(0xa) |
3519 PHY_M_LEDC_INIT_CTRL(0xa) |
3520 PHY_M_LEDC_STA1_CTRL(0xa) |
3521 PHY_M_LEDC_STA0_CTRL(0xa));
3522 break;
3523 case MO_LED_NORM:
3524 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3525 PHY_M_LEDC_LOS_CTRL(1) |
3526 PHY_M_LEDC_INIT_CTRL(8) |
3527 PHY_M_LEDC_STA1_CTRL(7) |
3528 PHY_M_LEDC_STA0_CTRL(7));
3529 }
793b883e 3530
a84d0a3d
SH		 3531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3532 } else
7d2e3cb7 3533 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3534 PHY_M_LED_MO_DUP(mode) |
3535 PHY_M_LED_MO_10(mode) |
3536 PHY_M_LED_MO_100(mode) |
3537 PHY_M_LED_MO_1000(mode) |
3538 PHY_M_LED_MO_RX(mode) |
3539 PHY_M_LED_MO_TX(mode));
3540
3541 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3542}
3543
3544/* blink LED's for finding board */
3545static int sky2_phys_id(struct net_device *dev, u32 data)
3546{
3547 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3548 unsigned int i;
cd28ab6a 3549
a84d0a3d
SH		 3550 if (data == 0)
3551 data = UINT_MAX;
cd28ab6a 3552
a84d0a3d
SH		 3553 for (i = 0; i < data; i++) {
3554 sky2_led(sky2, MO_LED_ON);
3555 if (msleep_interruptible(500))
3556 break;
3557 sky2_led(sky2, MO_LED_OFF);
3558 if (msleep_interruptible(500))
3559 break;
793b883e 3560 }
a84d0a3d 3561 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3562
3563 return 0;
3564}
3565
3566static void sky2_get_pauseparam(struct net_device *dev,
3567 struct ethtool_pauseparam *ecmd)
3568{
3569 struct sky2_port *sky2 = netdev_priv(dev);
3570
16ad91e1
SH		 3571 switch (sky2->flow_mode) {
3572 case FC_NONE:
3573 ecmd->tx_pause = ecmd->rx_pause = 0;
3574 break;
3575 case FC_TX:
3576 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3577 break;
3578 case FC_RX:
3579 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3580 break;
3581 case FC_BOTH:
3582 ecmd->tx_pause = ecmd->rx_pause = 1;
3583 }
3584
0ea065e5
SH		 3585 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3586 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3587}
3588
3589static int sky2_set_pauseparam(struct net_device *dev,
3590 struct ethtool_pauseparam *ecmd)
3591{
3592 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3593
0ea065e5
SH		 3594 if (ecmd->autoneg == AUTONEG_ENABLE)
3595 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3596 else
3597 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3598
16ad91e1 3599 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3600
16ad91e1
SH		 3601 if (netif_running(dev))
3602 sky2_phy_reinit(sky2);
cd28ab6a 3603
2eaba1a2 3604 return 0;
cd28ab6a
SH		 3605}
3606
fb17358f
SH		 3607static int sky2_get_coalesce(struct net_device *dev,
3608 struct ethtool_coalesce *ecmd)
3609{
3610 struct sky2_port *sky2 = netdev_priv(dev);
3611 struct sky2_hw *hw = sky2->hw;
3612
3613 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3614 ecmd->tx_coalesce_usecs = 0;
3615 else {
3616 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3617 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3618 }
3619 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3620
3621 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3622 ecmd->rx_coalesce_usecs = 0;
3623 else {
3624 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3625 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3626 }
3627 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3628
3629 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3630 ecmd->rx_coalesce_usecs_irq = 0;
3631 else {
3632 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3633 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3634 }
3635
3636 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3637
3638 return 0;
3639}
3640
3641/* Note: this affect both ports */
3642static int sky2_set_coalesce(struct net_device *dev,
3643 struct ethtool_coalesce *ecmd)
3644{
3645 struct sky2_port *sky2 = netdev_priv(dev);
3646 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3647 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3648
77b3d6a2
SH		 3649 if (ecmd->tx_coalesce_usecs > tmax ||
3650 ecmd->rx_coalesce_usecs > tmax ||
3651 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3652 return -EINVAL;
3653
ee5f68fe 3654 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3655 return -EINVAL;
ff81fbbe 3656 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3657 return -EINVAL;
ff81fbbe 3658 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3659 return -EINVAL;
3660
3661 if (ecmd->tx_coalesce_usecs == 0)
3662 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3663 else {
3664 sky2_write32(hw, STAT_TX_TIMER_INI,
3665 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3666 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3667 }
3668 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3669
3670 if (ecmd->rx_coalesce_usecs == 0)
3671 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3672 else {
3673 sky2_write32(hw, STAT_LEV_TIMER_INI,
3674 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3675 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3676 }
3677 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3678
3679 if (ecmd->rx_coalesce_usecs_irq == 0)
3680 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3681 else {
d28d4870 3682 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3683 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3684 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3685 }
3686 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3687 return 0;
3688}
3689
793b883e
SH		 3690static void sky2_get_ringparam(struct net_device *dev,
3691 struct ethtool_ringparam *ering)
3692{
3693 struct sky2_port *sky2 = netdev_priv(dev);
3694
3695 ering->rx_max_pending = RX_MAX_PENDING;
3696 ering->rx_mini_max_pending = 0;
3697 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3698 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3699
3700 ering->rx_pending = sky2->rx_pending;
3701 ering->rx_mini_pending = 0;
3702 ering->rx_jumbo_pending = 0;
3703 ering->tx_pending = sky2->tx_pending;
3704}
3705
3706static int sky2_set_ringparam(struct net_device *dev,
3707 struct ethtool_ringparam *ering)
3708{
3709 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3710
3711 if (ering->rx_pending > RX_MAX_PENDING ||
3712 ering->rx_pending < 8 ||
ee5f68fe
SH		 3713 ering->tx_pending < TX_MIN_PENDING ||
3714 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3715 return -EINVAL;
3716
af18d8b8 3717 sky2_detach(dev);
793b883e
SH		 3718
3719 sky2->rx_pending = ering->rx_pending;
3720 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3721 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3722
af18d8b8 3723 return sky2_reattach(dev);
793b883e
SH		 3724}
3725
793b883e
SH		 3726static int sky2_get_regs_len(struct net_device *dev)
3727{
6e4cbb34 3728 return 0x4000;
793b883e
SH		 3729}
3730
3731/*
3732 * Returns copy of control register region
3ead5db7 3733 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3734 */
3735static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3736 void *p)
3737{
3738 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3739 const void __iomem *io = sky2->hw->regs;
295b54c4 3740 unsigned int b;
793b883e
SH		 3741
3742 regs->version = 1;
793b883e 3743
295b54c4
SH		 3744 for (b = 0; b < 128; b++) {
3745 /* This complicated switch statement is to make sure and
3746 * only access regions that are unreserved.
3747 * Some blocks are only valid on dual port cards.
3748 * and block 3 has some special diagnostic registers that
3749 * are poison.
3750 */
3751 switch (b) {
3752 case 3:
3753 /* skip diagnostic ram region */
3754 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3755 break;
3ead5db7 3756
295b54c4
SH		 3757 /* dual port cards only */
3758 case 5: /* Tx Arbiter 2 */
3759 case 9: /* RX2 */
3760 case 14 ... 15: /* TX2 */
3761 case 17: case 19: /* Ram Buffer 2 */
3762 case 22 ... 23: /* Tx Ram Buffer 2 */
3763 case 25: /* Rx MAC Fifo 1 */
3764 case 27: /* Tx MAC Fifo 2 */
3765 case 31: /* GPHY 2 */
3766 case 40 ... 47: /* Pattern Ram 2 */
3767 case 52: case 54: /* TCP Segmentation 2 */
3768 case 112 ... 116: /* GMAC 2 */
3769 if (sky2->hw->ports == 1)
3770 goto reserved;
3771 /* fall through */
3772 case 0: /* Control */
3773 case 2: /* Mac address */
3774 case 4: /* Tx Arbiter 1 */
3775 case 7: /* PCI express reg */
3776 case 8: /* RX1 */
3777 case 12 ... 13: /* TX1 */
3778 case 16: case 18:/* Rx Ram Buffer 1 */
3779 case 20 ... 21: /* Tx Ram Buffer 1 */
3780 case 24: /* Rx MAC Fifo 1 */
3781 case 26: /* Tx MAC Fifo 1 */
3782 case 28 ... 29: /* Descriptor and status unit */
3783 case 30: /* GPHY 1*/
3784 case 32 ... 39: /* Pattern Ram 1 */
3785 case 48: case 50: /* TCP Segmentation 1 */
3786 case 56 ... 60: /* PCI space */
3787 case 80 ... 84: /* GMAC 1 */
3788 memcpy_fromio(p, io, 128);
3789 break;
3790 default:
3791reserved:
3792 memset(p, 0, 128);
3793 }
3ead5db7 3794
295b54c4
SH		 3795 p += 128;
3796 io += 128;
3797 }
793b883e 3798}
cd28ab6a 3799
b628ed98
SH		 3800/* In order to do Jumbo packets on these chips, need to turn off the
3801 * transmit store/forward. Therefore checksum offload won't work.
3802 */
3803static int no_tx_offload(struct net_device *dev)
3804{
3805 const struct sky2_port *sky2 = netdev_priv(dev);
3806 const struct sky2_hw *hw = sky2->hw;
3807
69161611 3808 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3809}
3810
3811static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3812{
3813 if (data && no_tx_offload(dev))
3814 return -EINVAL;
3815
3816 return ethtool_op_set_tx_csum(dev, data);
3817}
3818
3819
3820static int sky2_set_tso(struct net_device *dev, u32 data)
3821{
3822 if (data && no_tx_offload(dev))
3823 return -EINVAL;
3824
3825 return ethtool_op_set_tso(dev, data);
3826}
3827
f4331a6d
SH		 3828static int sky2_get_eeprom_len(struct net_device *dev)
3829{
3830 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3831 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3832 u16 reg2;
3833
b32f40c4 3834 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3835 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3836}
3837
1413235c 3838static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3839{
1413235c 3840 unsigned long start = jiffies;
f4331a6d 3841
1413235c
SH		 3842 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3843 /* Can take up to 10.6 ms for write */
3844 if (time_after(jiffies, start + HZ/4)) {
3845 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3846 return -ETIMEDOUT;
3847 }
3848 mdelay(1);
3849 }
167f53d0 3850
1413235c
SH		 3851 return 0;
3852}
167f53d0 3853
1413235c
SH		 3854static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3855 u16 offset, size_t length)
3856{
3857 int rc = 0;
3858
3859 while (length > 0) {
3860 u32 val;
3861
3862 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3863 rc = sky2_vpd_wait(hw, cap, 0);
3864 if (rc)
3865 break;
3866
3867 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3868
3869 memcpy(data, &val, min(sizeof(val), length));
3870 offset += sizeof(u32);
3871 data += sizeof(u32);
3872 length -= sizeof(u32);
3873 }
3874
3875 return rc;
f4331a6d
SH		 3876}
3877
1413235c
SH		 3878static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3879 u16 offset, unsigned int length)
f4331a6d 3880{
1413235c
SH		 3881 unsigned int i;
3882 int rc = 0;
3883
3884 for (i = 0; i < length; i += sizeof(u32)) {
3885 u32 val = *(u32 *)(data + i);
3886
3887 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3888 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3889
3890 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3891 if (rc)
3892 break;
3893 }
3894 return rc;
f4331a6d
SH		 3895}
3896
3897static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3898 u8 *data)
3899{
3900 struct sky2_port *sky2 = netdev_priv(dev);
3901 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3902
3903 if (!cap)
3904 return -EINVAL;
3905
3906 eeprom->magic = SKY2_EEPROM_MAGIC;
3907
1413235c 3908 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3909}
3910
3911static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3912 u8 *data)
3913{
3914 struct sky2_port *sky2 = netdev_priv(dev);
3915 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3916
3917 if (!cap)
3918 return -EINVAL;
3919
3920 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3921 return -EINVAL;
3922
1413235c
SH		 3923 /* Partial writes not supported */
3924 if ((eeprom->offset & 3) || (eeprom->len & 3))
3925 return -EINVAL;
f4331a6d 3926
1413235c 3927 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3928}
3929
3930
7282d491 3931static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3932 .get_settings = sky2_get_settings,
3933 .set_settings = sky2_set_settings,
3934 .get_drvinfo = sky2_get_drvinfo,
3935 .get_wol = sky2_get_wol,
3936 .set_wol = sky2_set_wol,
3937 .get_msglevel = sky2_get_msglevel,
3938 .set_msglevel = sky2_set_msglevel,
3939 .nway_reset = sky2_nway_reset,
3940 .get_regs_len = sky2_get_regs_len,
3941 .get_regs = sky2_get_regs,
3942 .get_link = ethtool_op_get_link,
3943 .get_eeprom_len = sky2_get_eeprom_len,
3944 .get_eeprom = sky2_get_eeprom,
3945 .set_eeprom = sky2_set_eeprom,
f4331a6d 3946 .set_sg = ethtool_op_set_sg,
f4331a6d 3947 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3948 .set_tso = sky2_set_tso,
3949 .get_rx_csum = sky2_get_rx_csum,
3950 .set_rx_csum = sky2_set_rx_csum,
3951 .get_strings = sky2_get_strings,
3952 .get_coalesce = sky2_get_coalesce,
3953 .set_coalesce = sky2_set_coalesce,
3954 .get_ringparam = sky2_get_ringparam,
3955 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3956 .get_pauseparam = sky2_get_pauseparam,
3957 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3958 .phys_id = sky2_phys_id,
b9f2c044 3959 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3960 .get_ethtool_stats = sky2_get_ethtool_stats,
3961};
3962
3cf26753
SH		 3963#ifdef CONFIG_SKY2_DEBUG
3964
3965static struct dentry *sky2_debug;
3966
e4c2abe2
SH		 3967
3968/*
3969 * Read and parse the first part of Vital Product Data
3970 */
3971#define VPD_SIZE 128
3972#define VPD_MAGIC 0x82
3973
3974static const struct vpd_tag {
3975 char tag[2];
3976 char *label;
3977} vpd_tags[] = {
3978 { "PN", "Part Number" },
3979 { "EC", "Engineering Level" },
3980 { "MN", "Manufacturer" },
3981 { "SN", "Serial Number" },
3982 { "YA", "Asset Tag" },
3983 { "VL", "First Error Log Message" },
3984 { "VF", "Second Error Log Message" },
3985 { "VB", "Boot Agent ROM Configuration" },
3986 { "VE", "EFI UNDI Configuration" },
3987};
3988
3989static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3990{
3991 size_t vpd_size;
3992 loff_t offs;
3993 u8 len;
3994 unsigned char *buf;
3995 u16 reg2;
3996
3997 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3998 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3999
4000 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4001 buf = kmalloc(vpd_size, GFP_KERNEL);
4002 if (!buf) {
4003 seq_puts(seq, "no memory!\n");
4004 return;
4005 }
4006
4007 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4008 seq_puts(seq, "VPD read failed\n");
4009 goto out;
4010 }
4011
4012 if (buf[0] != VPD_MAGIC) {
4013 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4014 goto out;
4015 }
4016 len = buf[1];
4017 if (len == 0 || len > vpd_size - 4) {
4018 seq_printf(seq, "Invalid id length: %d\n", len);
4019 goto out;
4020 }
4021
4022 seq_printf(seq, "%.*s\n", len, buf + 3);
4023 offs = len + 3;
4024
4025 while (offs < vpd_size - 4) {
4026 int i;
4027
4028 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4029 break;
4030 len = buf[offs + 2];
4031 if (offs + len + 3 >= vpd_size)
4032 break;
4033
4034 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4035 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4036 seq_printf(seq, " %s: %.*s\n",
4037 vpd_tags[i].label, len, buf + offs + 3);
4038 break;
4039 }
4040 }
4041 offs += len + 3;
4042 }
4043out:
4044 kfree(buf);
4045}
4046
3cf26753
SH		 4047static int sky2_debug_show(struct seq_file *seq, void *v)
4048{
4049 struct net_device *dev = seq->private;
4050 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4051 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4052 unsigned port = sky2->port;
4053 unsigned idx, last;
4054 int sop;
4055
e4c2abe2 4056 sky2_show_vpd(seq, hw);
3cf26753 4057
e4c2abe2 4058 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4059 sky2_read32(hw, B0_ISRC),
4060 sky2_read32(hw, B0_IMSK),
4061 sky2_read32(hw, B0_Y2_SP_ICR));
4062
e4c2abe2
SH		 4063 if (!netif_running(dev)) {
4064 seq_printf(seq, "network not running\n");
4065 return 0;
4066 }
4067
bea3348e 4068 napi_disable(&hw->napi);
3cf26753
SH		 4069 last = sky2_read16(hw, STAT_PUT_IDX);
4070
4071 if (hw->st_idx == last)
4072 seq_puts(seq, "Status ring (empty)\n");
4073 else {
4074 seq_puts(seq, "Status ring\n");
4075 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4076 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4077 const struct sky2_status_le *le = hw->st_le + idx;
4078 seq_printf(seq, "[%d] %#x %d %#x\n",
4079 idx, le->opcode, le->length, le->status);
4080 }
4081 seq_puts(seq, "\n");
4082 }
4083
4084 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4085 sky2->tx_cons, sky2->tx_prod,
4086 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4087 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4088
4089 /* Dump contents of tx ring */
4090 sop = 1;
ee5f68fe
SH		 4091 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4092 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4093 const struct sky2_tx_le *le = sky2->tx_le + idx;
4094 u32 a = le32_to_cpu(le->addr);
4095
4096 if (sop)
4097 seq_printf(seq, "%u:", idx);
4098 sop = 0;
4099
4100 switch(le->opcode & ~HW_OWNER) {
4101 case OP_ADDR64:
4102 seq_printf(seq, " %#x:", a);
4103 break;
4104 case OP_LRGLEN:
4105 seq_printf(seq, " mtu=%d", a);
4106 break;
4107 case OP_VLAN:
4108 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4109 break;
4110 case OP_TCPLISW:
4111 seq_printf(seq, " csum=%#x", a);
4112 break;
4113 case OP_LARGESEND:
4114 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4115 break;
4116 case OP_PACKET:
4117 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4118 break;
4119 case OP_BUFFER:
4120 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4121 break;
4122 default:
4123 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4124 a, le16_to_cpu(le->length));
4125 }
4126
4127 if (le->ctrl & EOP) {
4128 seq_putc(seq, '\n');
4129 sop = 1;
4130 }
4131 }
4132
4133 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4134 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4135 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4136 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4137
d1d08d12 4138 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4139 napi_enable(&hw->napi);
3cf26753
SH		 4140 return 0;
4141}
4142
4143static int sky2_debug_open(struct inode *inode, struct file *file)
4144{
4145 return single_open(file, sky2_debug_show, inode->i_private);
4146}
4147
4148static const struct file_operations sky2_debug_fops = {
4149 .owner = THIS_MODULE,
4150 .open = sky2_debug_open,
4151 .read = seq_read,
4152 .llseek = seq_lseek,
4153 .release = single_release,
4154};
4155
4156/*
4157 * Use network device events to create/remove/rename
4158 * debugfs file entries
4159 */
4160static int sky2_device_event(struct notifier_block *unused,
4161 unsigned long event, void *ptr)
4162{
4163 struct net_device *dev = ptr;
5b296bc9 4164 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4165
1436b301 4166 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4167 return NOTIFY_DONE;
3cf26753 4168
5b296bc9
SH		 4169 switch(event) {
4170 case NETDEV_CHANGENAME:
4171 if (sky2->debugfs) {
4172 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4173 sky2_debug, dev->name);
4174 }
4175 break;
3cf26753 4176
5b296bc9
SH		 4177 case NETDEV_GOING_DOWN:
4178 if (sky2->debugfs) {
4179 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4180 dev->name);
4181 debugfs_remove(sky2->debugfs);
4182 sky2->debugfs = NULL;
3cf26753 4183 }
5b296bc9
SH		 4184 break;
4185
4186 case NETDEV_UP:
4187 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4188 sky2_debug, dev,
4189 &sky2_debug_fops);
4190 if (IS_ERR(sky2->debugfs))
4191 sky2->debugfs = NULL;
3cf26753
SH		 4192 }
4193
4194 return NOTIFY_DONE;
4195}
4196
4197static struct notifier_block sky2_notifier = {
4198 .notifier_call = sky2_device_event,
4199};
4200
4201
4202static __init void sky2_debug_init(void)
4203{
4204 struct dentry *ent;
4205
4206 ent = debugfs_create_dir("sky2", NULL);
4207 if (!ent || IS_ERR(ent))
4208 return;
4209
4210 sky2_debug = ent;
4211 register_netdevice_notifier(&sky2_notifier);
4212}
4213
4214static __exit void sky2_debug_cleanup(void)
4215{
4216 if (sky2_debug) {
4217 unregister_netdevice_notifier(&sky2_notifier);
4218 debugfs_remove(sky2_debug);
4219 sky2_debug = NULL;
4220 }
4221}
4222
4223#else
4224#define sky2_debug_init()
4225#define sky2_debug_cleanup()
4226#endif
4227
1436b301
SH		 4228/* Two copies of network device operations to handle special case of
4229 not allowing netpoll on second port */
4230static const struct net_device_ops sky2_netdev_ops[2] = {
4231 {
4232 .ndo_open = sky2_up,
4233 .ndo_stop = sky2_down,
00829823 4234 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4235 .ndo_do_ioctl = sky2_ioctl,
4236 .ndo_validate_addr = eth_validate_addr,
4237 .ndo_set_mac_address = sky2_set_mac_address,
4238 .ndo_set_multicast_list = sky2_set_multicast,
4239 .ndo_change_mtu = sky2_change_mtu,
4240 .ndo_tx_timeout = sky2_tx_timeout,
4241#ifdef SKY2_VLAN_TAG_USED
4242 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4243#endif
4244#ifdef CONFIG_NET_POLL_CONTROLLER
4245 .ndo_poll_controller = sky2_netpoll,
4246#endif
4247 },
4248 {
4249 .ndo_open = sky2_up,
4250 .ndo_stop = sky2_down,
00829823 4251 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4252 .ndo_do_ioctl = sky2_ioctl,
4253 .ndo_validate_addr = eth_validate_addr,
4254 .ndo_set_mac_address = sky2_set_mac_address,
4255 .ndo_set_multicast_list = sky2_set_multicast,
4256 .ndo_change_mtu = sky2_change_mtu,
4257 .ndo_tx_timeout = sky2_tx_timeout,
4258#ifdef SKY2_VLAN_TAG_USED
4259 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4260#endif
4261 },
4262};
3cf26753 4263
cd28ab6a
SH		 4264/* Initialize network device */
4265static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4266 unsigned port,
be63a21c 4267 int highmem, int wol)
cd28ab6a
SH		 4268{
4269 struct sky2_port *sky2;
4270 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4271
4272 if (!dev) {
898eb71c 4273 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4274 return NULL;
4275 }
4276
cd28ab6a 4277 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4278 dev->irq = hw->pdev->irq;
cd28ab6a 4279 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4280 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4281 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4282
4283 sky2 = netdev_priv(dev);
4284 sky2->netdev = dev;
4285 sky2->hw = hw;
4286 sky2->msg_enable = netif_msg_init(debug, default_msg);
4287
cd28ab6a 4288 /* Auto speed and flow control */
0ea065e5
SH		 4289 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4290 if (hw->chip_id != CHIP_ID_YUKON_XL)
4291 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4292
16ad91e1
SH		 4293 sky2->flow_mode = FC_BOTH;
4294
cd28ab6a
SH		 4295 sky2->duplex = -1;
4296 sky2->speed = -1;
4297 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4298 sky2->wol = wol;
75d070c5 4299
e07b1aa8 4300 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4301
793b883e 4302 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4303 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4304 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4305
4306 hw->dev[port] = dev;
4307
4308 sky2->port = port;
4309
4a50a876 4310 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4311 if (highmem)
4312 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4313
d1f13708 4314#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4315 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4316 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4317 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4318 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4319 }
d1f13708 4320#endif
4321
cd28ab6a 4322 /* read the mac address */
793b883e 4323 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4324 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4325
cd28ab6a
SH		 4326 return dev;
4327}
4328
28bd181a 4329static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4330{
4331 const struct sky2_port *sky2 = netdev_priv(dev);
4332
4333 if (netif_msg_probe(sky2))
e174961c
JB		 4334 printk(KERN_INFO PFX "%s: addr %pM\n",
4335 dev->name, dev->dev_addr);
cd28ab6a
SH		 4336}
4337
fb2690a9 4338/* Handle software interrupt used during MSI test */
7d12e780 4339static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4340{
4341 struct sky2_hw *hw = dev_id;
4342 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4343
4344 if (status == 0)
4345 return IRQ_NONE;
4346
4347 if (status & Y2_IS_IRQ_SW) {
ea76e635 4348 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4349 wake_up(&hw->msi_wait);
4350 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4351 }
4352 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4353
4354 return IRQ_HANDLED;
4355}
4356
4357/* Test interrupt path by forcing a a software IRQ */
4358static int __devinit sky2_test_msi(struct sky2_hw *hw)
4359{
4360 struct pci_dev *pdev = hw->pdev;
4361 int err;
4362
bb507fe1 4363 init_waitqueue_head (&hw->msi_wait);
4364
fb2690a9
SH		 4365 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4366
b0a20ded 4367 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4368 if (err) {
b02a9258 4369 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4370 return err;
4371 }
4372
fb2690a9 4373 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4374 sky2_read8(hw, B0_CTST);
fb2690a9 4375
ea76e635 4376 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4377
ea76e635 4378 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4379 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4380 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4381 "switching to INTx mode.\n");
fb2690a9
SH		 4382
4383 err = -EOPNOTSUPP;
4384 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4385 }
4386
4387 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4388 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4389
4390 free_irq(pdev->irq, hw);
4391
4392 return err;
4393}
4394
c7127a34
SH		 4395/* This driver supports yukon2 chipset only */
4396static const char *sky2_name(u8 chipid, char *buf, int sz)
4397{
4398 const char *name[] = {
4399 "XL", /* 0xb3 */
4400 "EC Ultra", /* 0xb4 */
4401 "Extreme", /* 0xb5 */
4402 "EC", /* 0xb6 */
4403 "FE", /* 0xb7 */
4404 "FE+", /* 0xb8 */
4405 "Supreme", /* 0xb9 */
0ce8b98d 4406 "UL 2", /* 0xba */
c7127a34
SH		 4407 };
4408
0ce8b98d 4409 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4410 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4411 else
4412 snprintf(buf, sz, "(chip %#x)", chipid);
4413 return buf;
4414}
4415
cd28ab6a
SH		 4416static int __devinit sky2_probe(struct pci_dev *pdev,
4417 const struct pci_device_id *ent)
4418{
7f60c64b 4419 struct net_device *dev;
cd28ab6a 4420 struct sky2_hw *hw;
be63a21c 4421 int err, using_dac = 0, wol_default;
3834507d 4422 u32 reg;
c7127a34 4423 char buf1[16];
cd28ab6a 4424
793b883e
SH		 4425 err = pci_enable_device(pdev);
4426 if (err) {
b02a9258 4427 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4428 goto err_out;
4429 }
4430
6cc90a5a
SH		 4431 /* Get configuration information
4432 * Note: only regular PCI config access once to test for HW issues
4433 * other PCI access through shared memory for speed and to
4434 * avoid MMCONFIG problems.
4435 */
4436 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4437 if (err) {
4438 dev_err(&pdev->dev, "PCI read config failed\n");
4439 goto err_out;
4440 }
4441
4442 if (~reg == 0) {
4443 dev_err(&pdev->dev, "PCI configuration read error\n");
4444 goto err_out;
4445 }
4446
793b883e
SH		 4447 err = pci_request_regions(pdev, DRV_NAME);
4448 if (err) {
b02a9258 4449 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4450 goto err_out_disable;
cd28ab6a
SH		 4451 }
4452
4453 pci_set_master(pdev);
4454
d1f3d4dd 4455 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4456 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4457 using_dac = 1;
6a35528a 4458 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4459 if (err < 0) {
b02a9258
SH		 4460 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4461 "for consistent allocations\n");
d1f3d4dd
SH		 4462 goto err_out_free_regions;
4463 }
d1f3d4dd 4464 } else {
284901a9 4465 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4466 if (err) {
b02a9258 4467 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4468 goto err_out_free_regions;
4469 }
4470 }
d1f3d4dd 4471
3834507d
SH		 4472
4473#ifdef __BIG_ENDIAN
4474 /* The sk98lin vendor driver uses hardware byte swapping but
4475 * this driver uses software swapping.
4476 */
4477 reg &= ~PCI_REV_DESC;
4478 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4479 if (err) {
4480 dev_err(&pdev->dev, "PCI write config failed\n");
4481 goto err_out_free_regions;
4482 }
4483#endif
4484
9d731d77 4485 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4486
cd28ab6a 4487 err = -ENOMEM;
6aad85d6 4488 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4489 if (!hw) {
b02a9258 4490 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4491 goto err_out_free_regions;
4492 }
4493
cd28ab6a 4494 hw->pdev = pdev;
cd28ab6a
SH		 4495
4496 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4497 if (!hw->regs) {
b02a9258 4498 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4499 goto err_out_free_hw;
4500 }
4501
08c06d8a 4502 /* ring for status responses */
167f53d0 4503 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4504 if (!hw->st_le)
4505 goto err_out_iounmap;
4506
e3173832 4507 err = sky2_init(hw);
cd28ab6a 4508 if (err)
793b883e 4509 goto err_out_iounmap;
cd28ab6a 4510
c844d483
SH		 4511 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4512 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4513
e3173832
SH		 4514 sky2_reset(hw);
4515
be63a21c 4516 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4517 if (!dev) {
4518 err = -ENOMEM;
cd28ab6a 4519 goto err_out_free_pci;
7f60c64b 4520 }
cd28ab6a 4521
9fa1b1f3
SH		 4522 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4523 err = sky2_test_msi(hw);
4524 if (err == -EOPNOTSUPP)
4525 pci_disable_msi(pdev);
4526 else if (err)
4527 goto err_out_free_netdev;
4528 }
4529
793b883e
SH		 4530 err = register_netdev(dev);
4531 if (err) {
b02a9258 4532 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4533 goto err_out_free_netdev;
4534 }
4535
6de16237
SH		 4536 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4537
ea76e635
SH		 4538 err = request_irq(pdev->irq, sky2_intr,
4539 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4540 dev->name, hw);
9fa1b1f3 4541 if (err) {
b02a9258 4542 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4543 goto err_out_unregister;
4544 }
4545 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4546 napi_enable(&hw->napi);
9fa1b1f3 4547
cd28ab6a
SH		 4548 sky2_show_addr(dev);
4549
7f60c64b 4550 if (hw->ports > 1) {
4551 struct net_device *dev1;
4552
be63a21c 4553 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4554 if (!dev1)
4555 dev_warn(&pdev->dev, "allocation for second device failed\n");
4556 else if ((err = register_netdev(dev1))) {
4557 dev_warn(&pdev->dev,
4558 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4559 hw->dev[1] = NULL;
4560 free_netdev(dev1);
b02a9258
SH		 4561 } else
4562 sky2_show_addr(dev1);
cd28ab6a
SH		 4563 }
4564
32c2c300 4565 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4566 INIT_WORK(&hw->restart_work, sky2_restart);
4567
793b883e
SH		 4568 pci_set_drvdata(pdev, hw);
4569
cd28ab6a
SH		 4570 return 0;
4571
793b883e 4572err_out_unregister:
ea76e635 4573 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4574 pci_disable_msi(pdev);
793b883e 4575 unregister_netdev(dev);
cd28ab6a
SH		 4576err_out_free_netdev:
4577 free_netdev(dev);
cd28ab6a 4578err_out_free_pci:
793b883e 4579 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4580 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4581err_out_iounmap:
4582 iounmap(hw->regs);
4583err_out_free_hw:
4584 kfree(hw);
4585err_out_free_regions:
4586 pci_release_regions(pdev);
44a1d2e5 4587err_out_disable:
cd28ab6a 4588 pci_disable_device(pdev);
cd28ab6a 4589err_out:
549a68c3 4590 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4591 return err;
4592}
4593
4594static void __devexit sky2_remove(struct pci_dev *pdev)
4595{
793b883e 4596 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4597 int i;
cd28ab6a 4598
793b883e 4599 if (!hw)
cd28ab6a
SH		 4600 return;
4601
32c2c300 4602 del_timer_sync(&hw->watchdog_timer);
6de16237 4603 cancel_work_sync(&hw->restart_work);
d27ed387 4604
b877fe28 4605 for (i = hw->ports-1; i >= 0; --i)
6de16237 4606 unregister_netdev(hw->dev[i]);
81906791 4607
d27ed387 4608 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4609
ae306cca
SH		 4610 sky2_power_aux(hw);
4611
793b883e 4612 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4613 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4614
4615 free_irq(pdev->irq, hw);
ea76e635 4616 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4617 pci_disable_msi(pdev);
793b883e 4618 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4619 pci_release_regions(pdev);
4620 pci_disable_device(pdev);
793b883e 4621
b877fe28 4622 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4623 free_netdev(hw->dev[i]);
4624
cd28ab6a
SH		 4625 iounmap(hw->regs);
4626 kfree(hw);
5afa0a9c 4627
cd28ab6a
SH		 4628 pci_set_drvdata(pdev, NULL);
4629}
4630
4631#ifdef CONFIG_PM
4632static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4633{
793b883e 4634 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4635 int i, wol = 0;
cd28ab6a 4636
549a68c3
SH		 4637 if (!hw)
4638 return 0;
4639
063a0b38
SH		 4640 del_timer_sync(&hw->watchdog_timer);
4641 cancel_work_sync(&hw->restart_work);
4642
19720737 4643 rtnl_lock();
f05267e7 4644 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4645 struct net_device *dev = hw->dev[i];
e3173832 4646 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4647
af18d8b8 4648 sky2_detach(dev);
e3173832
SH		 4649
4650 if (sky2->wol)
4651 sky2_wol_init(sky2);
4652
4653 wol |= sky2->wol;
cd28ab6a
SH		 4654 }
4655
8ab8fca2 4656 sky2_write32(hw, B0_IMSK, 0);
6de16237 4657 napi_disable(&hw->napi);
ae306cca 4658 sky2_power_aux(hw);
19720737 4659 rtnl_unlock();
e3173832 4660
d374c1c1 4661 pci_save_state(pdev);
e3173832 4662 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4663 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4664
2ccc99b7 4665 return 0;
cd28ab6a
SH		 4666}
4667
4668static int sky2_resume(struct pci_dev *pdev)
4669{
793b883e 4670 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4671 int i, err;
cd28ab6a 4672
549a68c3
SH		 4673 if (!hw)
4674 return 0;
4675
f71eb1a2
SH		 4676 err = pci_set_power_state(pdev, PCI_D0);
4677 if (err)
4678 goto out;
ae306cca
SH		 4679
4680 err = pci_restore_state(pdev);
4681 if (err)
4682 goto out;
4683
cd28ab6a 4684 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4685
4686 /* Re-enable all clocks */
05745c4a
SH		 4687 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4688 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4689 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4690 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4691
e3173832 4692 sky2_reset(hw);
8ab8fca2 4693 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4694 napi_enable(&hw->napi);
8ab8fca2 4695
af18d8b8 4696 rtnl_lock();
f05267e7 4697 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4698 err = sky2_reattach(hw->dev[i]);
4699 if (err)
4700 goto out;
cd28ab6a 4701 }
af18d8b8 4702 rtnl_unlock();
eb35cf60 4703
ae306cca 4704 return 0;
08c06d8a 4705out:
af18d8b8
SH		 4706 rtnl_unlock();
4707
b02a9258 4708 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4709 pci_disable_device(pdev);
08c06d8a 4710 return err;
cd28ab6a
SH		 4711}
4712#endif
4713
e3173832
SH		 4714static void sky2_shutdown(struct pci_dev *pdev)
4715{
4716 struct sky2_hw *hw = pci_get_drvdata(pdev);
4717 int i, wol = 0;
4718
549a68c3
SH		 4719 if (!hw)
4720 return;
4721
19720737 4722 rtnl_lock();
5c0d6b34 4723 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4724
4725 for (i = 0; i < hw->ports; i++) {
4726 struct net_device *dev = hw->dev[i];
4727 struct sky2_port *sky2 = netdev_priv(dev);
4728
4729 if (sky2->wol) {
4730 wol = 1;
4731 sky2_wol_init(sky2);
4732 }
4733 }
4734
4735 if (wol)
4736 sky2_power_aux(hw);
19720737 4737 rtnl_unlock();
e3173832
SH		 4738
4739 pci_enable_wake(pdev, PCI_D3hot, wol);
4740 pci_enable_wake(pdev, PCI_D3cold, wol);
4741
4742 pci_disable_device(pdev);
f71eb1a2 4743 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4744}
4745
cd28ab6a 4746static struct pci_driver sky2_driver = {
793b883e
SH		 4747 .name = DRV_NAME,
4748 .id_table = sky2_id_table,
4749 .probe = sky2_probe,
4750 .remove = __devexit_p(sky2_remove),
cd28ab6a 4751#ifdef CONFIG_PM
793b883e
SH		 4752 .suspend = sky2_suspend,
4753 .resume = sky2_resume,
cd28ab6a 4754#endif
e3173832 4755 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4756};
4757
4758static int __init sky2_init_module(void)
4759{
c844d483
SH		 4760 pr_info(PFX "driver version " DRV_VERSION "\n");
4761
3cf26753 4762 sky2_debug_init();
50241c4c 4763 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4764}
4765
4766static void __exit sky2_cleanup_module(void)
4767{
4768 pci_unregister_driver(&sky2_driver);
3cf26753 4769 sky2_debug_cleanup();
cd28ab6a
SH		 4770}
4771
4772module_init(sky2_init_module);
4773module_exit(sky2_cleanup_module);
4774
4775MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4776MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4777MODULE_LICENSE("GPL");
5f4f9dc1 4778MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)