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sky2: 1.16 version
[linux-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
0640b8dc 54#define DRV_VERSION "1.16"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
c59697e0 102static int idle_timeout = 100;
01bd7564 103module_param(idle_timeout, int, 0);
e561a83b 104MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 105
cd28ab6a 106static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
108 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 112 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 137 { 0 }
138};
793b883e 139
cd28ab6a
SH		 140MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142/* Avoid conditionals by using array */
143static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 145static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 146
92f965e8
SH		 147/* This driver supports yukon2 chipset only */
148static const char *yukon2_name[] = {
149 "XL", /* 0xb3 */
150 "EC Ultra", /* 0xb4 */
93745494 151 "Extreme", /* 0xb5 */
92f965e8
SH		 152 "EC", /* 0xb6 */
153 "FE", /* 0xb7 */
793b883e
SH		 154};
155
793b883e 156/* Access to external PHY */
ef743d33 157static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 158{
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 166 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
793b883e 168 udelay(1);
cd28ab6a 169 }
ef743d33 170
793b883e 171 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 172 return -ETIMEDOUT;
cd28ab6a
SH		 173}
174
ef743d33 175static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 176{
177 int i;
178
793b883e 179 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 180 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
181
182 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 183 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
184 *val = gma_read16(hw, port, GM_SMI_DATA);
185 return 0;
186 }
187
793b883e 188 udelay(1);
cd28ab6a
SH		 189 }
190
ef743d33 191 return -ETIMEDOUT;
192}
193
194static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
195{
196 u16 v;
197
198 if (__gm_phy_read(hw, port, reg, &v) != 0)
199 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
200 return v;
cd28ab6a
SH		 201}
202
5afa0a9c 203
ae306cca
SH		 204static void sky2_power_on(struct sky2_hw *hw)
205{
206 /* switch power to VCC (WA for VAUX problem) */
207 sky2_write8(hw, B0_POWER_CTRL,
208 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 209
ae306cca
SH		 210 /* disable Core Clock Division, */
211 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 212
ae306cca
SH		 213 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
214 /* enable bits are inverted */
215 sky2_write8(hw, B2_Y2_CLK_GATE,
216 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
217 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
218 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
219 else
220 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 221
93745494 222 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
fc99fe06 223 u32 reg;
5afa0a9c 224
fc99fe06
SH		 225 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
226 /* set all bits to 0 except bits 15..12 and 8 */
227 reg &= P_ASPM_CONTROL_MSK;
228 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
229
230 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
231 /* set all bits to 0 except bits 28 & 27 */
232 reg &= P_CTL_TIM_VMAIN_AV_MSK;
233 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
234
235 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 236
237 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
238 reg = sky2_read32(hw, B2_GP_IO);
239 reg |= GLB_GPIO_STAT_RACE_DIS;
240 sky2_write32(hw, B2_GP_IO, reg);
5afa0a9c 241 }
ae306cca 242}
5afa0a9c 243
ae306cca
SH		 244static void sky2_power_aux(struct sky2_hw *hw)
245{
246 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
247 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
248 else
249 /* enable bits are inverted */
250 sky2_write8(hw, B2_Y2_CLK_GATE,
251 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
252 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
253 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
254
255 /* switch power to VAUX */
256 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
257 sky2_write8(hw, B0_POWER_CTRL,
258 (PC_VAUX_ENA | PC_VCC_ENA |
259 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 260}
261
d3bcfbeb 262static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 263{
264 u16 reg;
265
266 /* disable all GMAC IRQ's */
267 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
268 /* disable PHY IRQs */
269 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 270
cd28ab6a
SH		 271 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
272 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
273 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
274 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
275
276 reg = gma_read16(hw, port, GM_RX_CTRL);
277 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
278 gma_write16(hw, port, GM_RX_CTRL, reg);
279}
280
16ad91e1
SH		 281/* flow control to advertise bits */
282static const u16 copper_fc_adv[] = {
283 [FC_NONE] = 0,
284 [FC_TX] = PHY_M_AN_ASP,
285 [FC_RX] = PHY_M_AN_PC,
286 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
287};
288
289/* flow control to advertise bits when using 1000BaseX */
290static const u16 fiber_fc_adv[] = {
291 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
292 [FC_TX] = PHY_M_P_ASYM_MD_X,
293 [FC_RX] = PHY_M_P_SYM_MD_X,
294 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
295};
296
297/* flow control to GMA disable bits */
298static const u16 gm_fc_disable[] = {
299 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
300 [FC_TX] = GM_GPCR_FC_RX_DIS,
301 [FC_RX] = GM_GPCR_FC_TX_DIS,
302 [FC_BOTH] = 0,
303};
304
305
cd28ab6a
SH		 306static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
307{
308 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 309 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 310
93745494
SH		 311 if (sky2->autoneg == AUTONEG_ENABLE
312 && !(hw->chip_id == CHIP_ID_YUKON_XL
313 || hw->chip_id == CHIP_ID_YUKON_EC_U
314 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 315 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
316
317 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 318 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 319 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
320
53419c68 321 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 322 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 323 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 324 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
325 else
53419c68
SH		 326 /* set master & slave downshift counter to 1x */
327 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 328
329 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
330 }
331
332 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 333 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 334 if (hw->chip_id == CHIP_ID_YUKON_FE) {
335 /* enable automatic crossover */
336 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
337 } else {
338 /* disable energy detect */
339 ctrl &= ~PHY_M_PC_EN_DET_MSK;
340
341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
343
53419c68 344 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 345 if (sky2->autoneg == AUTONEG_ENABLE
346 && (hw->chip_id == CHIP_ID_YUKON_XL
347 || hw->chip_id == CHIP_ID_YUKON_EC_U
348 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 349 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 350 ctrl &= ~PHY_M_PC_DSC_MSK;
351 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
352 }
353 }
cd28ab6a
SH		 354 } else {
355 /* workaround for deviation #4.88 (CRC errors) */
356 /* disable Automatic Crossover */
357
358 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 359 }
cd28ab6a 360
b89165f2
SH		 361 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
362
363 /* special setup for PHY 88E1112 Fiber */
364 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
365 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 366
b89165f2
SH		 367 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
368 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
369 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
370 ctrl &= ~PHY_M_MAC_MD_MSK;
371 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
372 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
373
374 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 375 /* select page 1 to access Fiber registers */
376 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 377
378 /* for SFP-module set SIGDET polarity to low */
379 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
380 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 381 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 382 }
b89165f2
SH		 383
384 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 385 }
386
7800fddc 387 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 388 ct1000 = 0;
389 adv = PHY_AN_CSMA;
2eaba1a2 390 reg = 0;
cd28ab6a
SH		 391
392 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 393 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 394 if (sky2->advertising & ADVERTISED_1000baseT_Full)
395 ct1000 |= PHY_M_1000C_AFD;
396 if (sky2->advertising & ADVERTISED_1000baseT_Half)
397 ct1000 |= PHY_M_1000C_AHD;
398 if (sky2->advertising & ADVERTISED_100baseT_Full)
399 adv |= PHY_M_AN_100_FD;
400 if (sky2->advertising & ADVERTISED_100baseT_Half)
401 adv |= PHY_M_AN_100_HD;
402 if (sky2->advertising & ADVERTISED_10baseT_Full)
403 adv |= PHY_M_AN_10_FD;
404 if (sky2->advertising & ADVERTISED_10baseT_Half)
405 adv |= PHY_M_AN_10_HD;
709c6e7b 406
16ad91e1 407 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 408 } else { /* special defines for FIBER (88E1040S only) */
409 if (sky2->advertising & ADVERTISED_1000baseT_Full)
410 adv |= PHY_M_AN_1000X_AFD;
411 if (sky2->advertising & ADVERTISED_1000baseT_Half)
412 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 413
16ad91e1 414 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 415 }
cd28ab6a
SH		 416
417 /* Restart Auto-negotiation */
418 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
419 } else {
420 /* forced speed/duplex settings */
421 ct1000 = PHY_M_1000C_MSE;
422
2eaba1a2
SH		 423 /* Disable auto update for duplex flow control and speed */
424 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 425
426 switch (sky2->speed) {
427 case SPEED_1000:
428 ctrl |= PHY_CT_SP1000;
2eaba1a2 429 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 430 break;
431 case SPEED_100:
432 ctrl |= PHY_CT_SP100;
2eaba1a2 433 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 434 break;
435 }
436
2eaba1a2
SH		 437 if (sky2->duplex == DUPLEX_FULL) {
438 reg |= GM_GPCR_DUP_FULL;
439 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 440 } else if (sky2->speed < SPEED_1000)
441 sky2->flow_mode = FC_NONE;
2eaba1a2 442
2eaba1a2 443
16ad91e1 444 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 445
446 /* Forward pause packets to GMAC? */
16ad91e1 447 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 448 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
449 else
450 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 451 }
452
2eaba1a2
SH		 453 gma_write16(hw, port, GM_GP_CTRL, reg);
454
cd28ab6a
SH		 455 if (hw->chip_id != CHIP_ID_YUKON_FE)
456 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
457
458 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
459 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
460
461 /* Setup Phy LED's */
462 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
463 ledover = 0;
464
465 switch (hw->chip_id) {
466 case CHIP_ID_YUKON_FE:
467 /* on 88E3082 these bits are at 11..9 (shifted left) */
468 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
469
470 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
471
472 /* delete ACT LED control bits */
473 ctrl &= ~PHY_M_FELP_LED1_MSK;
474 /* change ACT LED control to blink mode */
475 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
476 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
477 break;
478
479 case CHIP_ID_YUKON_XL:
793b883e 480 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 481
482 /* select page 3 to access LED control register */
483 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
484
485 /* set LED Function Control register */
ed6d32c7
SH		 486 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
487 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
488 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
489 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
490 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 491
492 /* set Polarity Control register */
493 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 494 (PHY_M_POLC_LS1_P_MIX(4) |
495 PHY_M_POLC_IS0_P_MIX(4) |
496 PHY_M_POLC_LOS_CTRL(2) |
497 PHY_M_POLC_INIT_CTRL(2) |
498 PHY_M_POLC_STA1_CTRL(2) |
499 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 500
501 /* restore page register */
793b883e 502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 503 break;
93745494 504
ed6d32c7 505 case CHIP_ID_YUKON_EC_U:
93745494 506 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 507 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
508
509 /* select page 3 to access LED control register */
510 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
511
512 /* set LED Function Control register */
513 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
514 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
515 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
516 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
517 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
518
519 /* set Blink Rate in LED Timer Control Register */
520 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
521 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
522 /* restore page register */
523 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
524 break;
cd28ab6a
SH		 525
526 default:
527 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
528 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
529 /* turn off the Rx LED (LED_RX) */
0efdf262 530 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 531 }
532
9467a8fc
SH		 533 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
534 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 535 /* apply fixes in PHY AFE */
ed6d32c7
SH		 536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
537
977bdf06 538 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 539 gm_phy_write(hw, port, 0x18, 0xaa99);
540 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 541
977bdf06 542 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 543 gm_phy_write(hw, port, 0x18, 0xa204);
544 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 545
546 /* set page register to 0 */
9467a8fc 547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 548 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 549 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 550
977bdf06
SH		 551 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
552 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 553 ledover |= PHY_M_LED_MO_100;
977bdf06 554 }
cd28ab6a 555
977bdf06
SH		 556 if (ledover)
557 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
558
559 }
2eaba1a2 560
d571b694 561 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 562 if (sky2->autoneg == AUTONEG_ENABLE)
563 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
564 else
565 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
566}
567
d3bcfbeb 568static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
569{
570 u32 reg1;
571 static const u32 phy_power[]
572 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
573
574 /* looks like this XL is back asswards .. */
575 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
576 onoff = !onoff;
577
aed2cec4 578 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 579 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 580 if (onoff)
581 /* Turn off phy power saving */
582 reg1 &= ~phy_power[port];
583 else
584 reg1 |= phy_power[port];
585
586 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 587 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 588 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 589 udelay(100);
590}
591
1b537565
SH		 592/* Force a renegotiation */
593static void sky2_phy_reinit(struct sky2_port *sky2)
594{
e07b1aa8 595 spin_lock_bh(&sky2->phy_lock);
1b537565 596 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 597 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 598}
599
e3173832
SH		 600/* Put device in state to listen for Wake On Lan */
601static void sky2_wol_init(struct sky2_port *sky2)
602{
603 struct sky2_hw *hw = sky2->hw;
604 unsigned port = sky2->port;
605 enum flow_control save_mode;
606 u16 ctrl;
607 u32 reg1;
608
609 /* Bring hardware out of reset */
610 sky2_write16(hw, B0_CTST, CS_RST_CLR);
611 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
612
613 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
614 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
615
616 /* Force to 10/100
617 * sky2_reset will re-enable on resume
618 */
619 save_mode = sky2->flow_mode;
620 ctrl = sky2->advertising;
621
622 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
623 sky2->flow_mode = FC_NONE;
624 sky2_phy_power(hw, port, 1);
625 sky2_phy_reinit(sky2);
626
627 sky2->flow_mode = save_mode;
628 sky2->advertising = ctrl;
629
630 /* Set GMAC to no flow control and auto update for speed/duplex */
631 gma_write16(hw, port, GM_GP_CTRL,
632 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
633 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
634
635 /* Set WOL address */
636 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
637 sky2->netdev->dev_addr, ETH_ALEN);
638
639 /* Turn on appropriate WOL control bits */
640 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
641 ctrl = 0;
642 if (sky2->wol & WAKE_PHY)
643 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
644 else
645 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
646
647 if (sky2->wol & WAKE_MAGIC)
648 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
649 else
650 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
651
652 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
653 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
654
655 /* Turn on legacy PCI-Express PME mode */
656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
657 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
658 reg1 |= PCI_Y2_PME_LEGACY;
659 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
660 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
661
662 /* block receiver */
663 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
664
665}
666
69161611
SH		 667static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
668{
669 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
670 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
671 TX_STFW_ENA |
672 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
673 } else {
674 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
675 /* set Tx GMAC FIFO Almost Empty Threshold */
676 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
677 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
678
679 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
680 TX_JUMBO_ENA | TX_STFW_DIS);
681
682 /* Can't do offload because of lack of store/forward */
683 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
684 | NETIF_F_ALL_CSUM);
685 } else
686 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
687 TX_JUMBO_DIS | TX_STFW_ENA);
688 }
689}
690
cd28ab6a
SH		 691static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
692{
693 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
694 u16 reg;
695 int i;
696 const u8 *addr = hw->dev[port]->dev_addr;
697
42eeea01 698 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
b4ed372b 699 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 700
701 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
702
793b883e 703 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 704 /* WA DEV_472 -- looks like crossed wires on port 2 */
705 /* clear GMAC 1 Control reset */
706 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
707 do {
708 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
709 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
710 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
711 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
712 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
713 }
714
793b883e 715 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 716
2eaba1a2
SH		 717 /* Enable Transmit FIFO Underrun */
718 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
719
e07b1aa8 720 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 721 sky2_phy_init(hw, port);
e07b1aa8 722 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 723
724 /* MIB clear */
725 reg = gma_read16(hw, port, GM_PHY_ADDR);
726 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
727
43f2f104
SH		 728 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
729 gma_read16(hw, port, i);
cd28ab6a
SH		 730 gma_write16(hw, port, GM_PHY_ADDR, reg);
731
732 /* transmit control */
733 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
734
735 /* receive control reg: unicast + multicast + no FCS */
736 gma_write16(hw, port, GM_RX_CTRL,
793b883e 737 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 738
739 /* transmit flow control */
740 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
741
742 /* transmit parameter */
743 gma_write16(hw, port, GM_TX_PARAM,
744 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
745 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
746 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
747 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
748
749 /* serial mode register */
750 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 751 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 752
6b1a3aef 753 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 754 reg |= GM_SMOD_JUMBO_ENA;
755
756 gma_write16(hw, port, GM_SERIAL_MODE, reg);
757
cd28ab6a
SH		 758 /* virtual address for data */
759 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
760
793b883e
SH		 761 /* physical address: used for pause frames */
762 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
763
764 /* ignore counter overflows */
cd28ab6a
SH		 765 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
766 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
767 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
768
769 /* Configure Rx MAC FIFO */
770 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
69161611
SH		 771 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
772 if (hw->chip_id == CHIP_ID_YUKON_EX)
773 reg |= GMF_RX_OVER_ON;
774
775 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
cd28ab6a 776
d571b694 777 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 778 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 779
8df9a876
SH		 780 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
781 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 782
783 /* Configure Tx MAC FIFO */
784 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
785 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 786
93745494 787 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 788 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 789 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 790
69161611 791 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 792 }
793
cd28ab6a
SH		 794}
795
67712901
SH		 796/* Assign Ram Buffer allocation to queue */
797static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 798{
67712901
SH		 799 u32 end;
800
801 /* convert from K bytes to qwords used for hw register */
802 start *= 1024/8;
803 space *= 1024/8;
804 end = start + space - 1;
793b883e 805
cd28ab6a
SH		 806 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
807 sky2_write32(hw, RB_ADDR(q, RB_START), start);
808 sky2_write32(hw, RB_ADDR(q, RB_END), end);
809 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
810 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
811
812 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 813 u32 tp = space - space/4;
793b883e 814
1c28f6ba
SH		 815 /* On receive queue's set the thresholds
816 * give receiver priority when > 3/4 full
817 * send pause when down to 2K
818 */
819 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
820 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 821
1c28f6ba
SH		 822 tp = space - 2048/8;
823 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
824 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 825 } else {
826 /* Enable store & forward on Tx queue's because
827 * Tx FIFO is only 1K on Yukon
828 */
829 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
830 }
831
832 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 833 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 834}
835
cd28ab6a 836/* Setup Bus Memory Interface */
af4ed7e6 837static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 838{
839 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
840 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
841 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 842 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 843}
844
cd28ab6a
SH		 845/* Setup prefetch unit registers. This is the interface between
846 * hardware and driver list elements
847 */
8cc048e3 848static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 849 u64 addr, u32 last)
850{
cd28ab6a
SH		 851 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
852 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
853 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
854 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
855 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
856 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 857
858 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 859}
860
793b883e
SH		 861static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
862{
863 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
864
cb5d9547 865 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 866 le->ctrl = 0;
793b883e
SH		 867 return le;
868}
cd28ab6a 869
291ea614
SH		 870static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
871 struct sky2_tx_le *le)
872{
873 return sky2->tx_ring + (le - sky2->tx_le);
874}
875
290d4de5
SH		 876/* Update chip's next pointer */
877static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 878{
50432cb5 879 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 880 wmb();
50432cb5
SH		 881 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
882
883 /* Synchronize I/O on since next processor may write to tail */
884 mmiowb();
cd28ab6a
SH		 885}
886
793b883e 887
cd28ab6a
SH		 888static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
889{
890 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 891 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 892 le->ctrl = 0;
cd28ab6a
SH		 893 return le;
894}
895
14d0263f
SH		 896/* Build description to hardware for one receive segment */
897static void sky2_rx_add(struct sky2_port *sky2, u8 op,
898 dma_addr_t map, unsigned len)
cd28ab6a
SH		 899{
900 struct sky2_rx_le *le;
36eb0c71 901 u32 hi = upper_32_bits(map);
cd28ab6a 902
793b883e 903 if (sky2->rx_addr64 != hi) {
cd28ab6a 904 le = sky2_next_rx(sky2);
793b883e 905 le->addr = cpu_to_le32(hi);
cd28ab6a 906 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 907 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 908 }
793b883e 909
cd28ab6a 910 le = sky2_next_rx(sky2);
734d1868
SH		 911 le->addr = cpu_to_le32((u32) map);
912 le->length = cpu_to_le16(len);
14d0263f 913 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 914}
915
14d0263f
SH		 916/* Build description to hardware for one possibly fragmented skb */
917static void sky2_rx_submit(struct sky2_port *sky2,
918 const struct rx_ring_info *re)
919{
920 int i;
921
922 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
923
924 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
925 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
926}
927
928
929static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
930 unsigned size)
931{
932 struct sk_buff *skb = re->skb;
933 int i;
934
935 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
936 pci_unmap_len_set(re, data_size, size);
937
938 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
939 re->frag_addr[i] = pci_map_page(pdev,
940 skb_shinfo(skb)->frags[i].page,
941 skb_shinfo(skb)->frags[i].page_offset,
942 skb_shinfo(skb)->frags[i].size,
943 PCI_DMA_FROMDEVICE);
944}
945
946static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
947{
948 struct sk_buff *skb = re->skb;
949 int i;
950
951 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
952 PCI_DMA_FROMDEVICE);
953
954 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
955 pci_unmap_page(pdev, re->frag_addr[i],
956 skb_shinfo(skb)->frags[i].size,
957 PCI_DMA_FROMDEVICE);
958}
793b883e 959
cd28ab6a
SH		 960/* Tell chip where to start receive checksum.
961 * Actually has two checksums, but set both same to avoid possible byte
962 * order problems.
963 */
793b883e 964static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 965{
966 struct sky2_rx_le *le;
967
69161611
SH		 968 if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
969 le = sky2_next_rx(sky2);
970 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
971 le->ctrl = 0;
972 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 973
69161611
SH		 974 sky2_write32(sky2->hw,
975 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
976 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
977 }
cd28ab6a
SH		 978
979}
980
6b1a3aef 981/*
982 * The RX Stop command will not work for Yukon-2 if the BMU does not
983 * reach the end of packet and since we can't make sure that we have
984 * incoming data, we must reset the BMU while it is not doing a DMA
985 * transfer. Since it is possible that the RX path is still active,
986 * the RX RAM buffer will be stopped first, so any possible incoming
987 * data will not trigger a DMA. After the RAM buffer is stopped, the
988 * BMU is polled until any DMA in progress is ended and only then it
989 * will be reset.
990 */
991static void sky2_rx_stop(struct sky2_port *sky2)
992{
993 struct sky2_hw *hw = sky2->hw;
994 unsigned rxq = rxqaddr[sky2->port];
995 int i;
996
997 /* disable the RAM Buffer receive queue */
998 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
999
1000 for (i = 0; i < 0xffff; i++)
1001 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1002 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1003 goto stopped;
1004
1005 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1006 sky2->netdev->name);
1007stopped:
1008 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1009
1010 /* reset the Rx prefetch unit */
1011 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1012 mmiowb();
6b1a3aef 1013}
793b883e 1014
d571b694 1015/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1016static void sky2_rx_clean(struct sky2_port *sky2)
1017{
1018 unsigned i;
1019
1020 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1021 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1022 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1023
1024 if (re->skb) {
14d0263f 1025 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1026 kfree_skb(re->skb);
1027 re->skb = NULL;
1028 }
1029 }
1030}
1031
ef743d33 1032/* Basic MII support */
1033static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1034{
1035 struct mii_ioctl_data *data = if_mii(ifr);
1036 struct sky2_port *sky2 = netdev_priv(dev);
1037 struct sky2_hw *hw = sky2->hw;
1038 int err = -EOPNOTSUPP;
1039
1040 if (!netif_running(dev))
1041 return -ENODEV; /* Phy still in reset */
1042
d89e1343 1043 switch (cmd) {
ef743d33 1044 case SIOCGMIIPHY:
1045 data->phy_id = PHY_ADDR_MARV;
1046
1047 /* fallthru */
1048 case SIOCGMIIREG: {
1049 u16 val = 0;
91c86df5 1050
e07b1aa8 1051 spin_lock_bh(&sky2->phy_lock);
ef743d33 1052 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1053 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1054
ef743d33 1055 data->val_out = val;
1056 break;
1057 }
1058
1059 case SIOCSMIIREG:
1060 if (!capable(CAP_NET_ADMIN))
1061 return -EPERM;
1062
e07b1aa8 1063 spin_lock_bh(&sky2->phy_lock);
ef743d33 1064 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1065 data->val_in);
e07b1aa8 1066 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1067 break;
1068 }
1069 return err;
1070}
1071
d1f13708 1072#ifdef SKY2_VLAN_TAG_USED
1073static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1074{
1075 struct sky2_port *sky2 = netdev_priv(dev);
1076 struct sky2_hw *hw = sky2->hw;
1077 u16 port = sky2->port;
d1f13708 1078
2bb8c262 1079 netif_tx_lock_bh(dev);
3d4e66f5 1080 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1081
d1f13708 1082 sky2->vlgrp = grp;
3d4e66f5
SH		 1083 if (grp) {
1084 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1085 RX_VLAN_STRIP_ON);
1086 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1087 TX_VLAN_TAG_ON);
1088 } else {
1089 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1090 RX_VLAN_STRIP_OFF);
1091 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1092 TX_VLAN_TAG_OFF);
1093 }
d1f13708 1094
3d4e66f5 1095 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1096 netif_tx_unlock_bh(dev);
d1f13708 1097}
1098#endif
1099
82788c7a 1100/*
14d0263f
SH		 1101 * Allocate an skb for receiving. If the MTU is large enough
1102 * make the skb non-linear with a fragment list of pages.
1103 *
82788c7a
SH		 1104 * It appears the hardware has a bug in the FIFO logic that
1105 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1106 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1107 * aligned except if slab debugging is enabled.
82788c7a 1108 */
14d0263f 1109static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1110{
1111 struct sk_buff *skb;
14d0263f
SH		 1112 unsigned long p;
1113 int i;
82788c7a 1114
14d0263f
SH		 1115 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1116 if (!skb)
1117 goto nomem;
1118
1119 p = (unsigned long) skb->data;
1120 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1121
1122 for (i = 0; i < sky2->rx_nfrags; i++) {
1123 struct page *page = alloc_page(GFP_ATOMIC);
1124
1125 if (!page)
1126 goto free_partial;
1127 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1128 }
1129
1130 return skb;
14d0263f
SH		 1131free_partial:
1132 kfree_skb(skb);
1133nomem:
1134 return NULL;
82788c7a
SH		 1135}
1136
55c9dd35
SH		 1137static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1138{
1139 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1140}
1141
cd28ab6a
SH		 1142/*
1143 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1144 * Normal case this ends up creating one list element for skb
1145 * in the receive ring. Worst case if using large MTU and each
1146 * allocation falls on a different 64 bit region, that results
1147 * in 6 list elements per ring entry.
1148 * One element is used for checksum enable/disable, and one
1149 * extra to avoid wrap.
cd28ab6a 1150 */
6b1a3aef 1151static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1152{
6b1a3aef 1153 struct sky2_hw *hw = sky2->hw;
14d0263f 1154 struct rx_ring_info *re;
6b1a3aef 1155 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1156 unsigned i, size, space, thresh;
cd28ab6a 1157
6b1a3aef 1158 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1159 sky2_qset(hw, rxq);
977bdf06 1160
c3905bc4
SH		 1161 /* On PCI express lowering the watermark gives better performance */
1162 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1163 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1164
1165 /* These chips have no ram buffer?
1166 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1167 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1168 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1169 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1170 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1171
6b1a3aef 1172 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1173
1174 rx_set_checksum(sky2);
14d0263f
SH		 1175
1176 /* Space needed for frame data + headers rounded up */
f957da2a 1177 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1178
1179 /* Stopping point for hardware truncation */
1180 thresh = (size - 8) / sizeof(u32);
1181
1182 /* Account for overhead of skb - to avoid order > 0 allocation */
1183 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1184 + sizeof(struct skb_shared_info);
1185
1186 sky2->rx_nfrags = space >> PAGE_SHIFT;
1187 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1188
1189 if (sky2->rx_nfrags != 0) {
1190 /* Compute residue after pages */
1191 space = sky2->rx_nfrags << PAGE_SHIFT;
1192
1193 if (space < size)
1194 size -= space;
1195 else
1196 size = 0;
1197
1198 /* Optimize to handle small packets and headers */
1199 if (size < copybreak)
1200 size = copybreak;
1201 if (size < ETH_HLEN)
1202 size = ETH_HLEN;
1203 }
1204 sky2->rx_data_size = size;
1205
1206 /* Fill Rx ring */
793b883e 1207 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1208 re = sky2->rx_ring + i;
cd28ab6a 1209
14d0263f 1210 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1211 if (!re->skb)
1212 goto nomem;
1213
14d0263f
SH		 1214 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1215 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1216 }
1217
a1433ac4
SH		 1218 /*
1219 * The receiver hangs if it receives frames larger than the
1220 * packet buffer. As a workaround, truncate oversize frames, but
1221 * the register is limited to 9 bits, so if you do frames > 2052
1222 * you better get the MTU right!
1223 */
a1433ac4
SH		 1224 if (thresh > 0x1ff)
1225 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1226 else {
1227 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1228 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1229 }
1230
6b1a3aef 1231 /* Tell chip about available buffers */
55c9dd35 1232 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1233 return 0;
1234nomem:
1235 sky2_rx_clean(sky2);
1236 return -ENOMEM;
1237}
1238
1239/* Bring up network interface. */
1240static int sky2_up(struct net_device *dev)
1241{
1242 struct sky2_port *sky2 = netdev_priv(dev);
1243 struct sky2_hw *hw = sky2->hw;
1244 unsigned port = sky2->port;
67712901 1245 u32 ramsize, imask;
ee7abb04 1246 int cap, err = -ENOMEM;
843a46f4 1247 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1248
ee7abb04
SH		 1249 /*
1250 * On dual port PCI-X card, there is an problem where status
1251 * can be received out of order due to split transactions
843a46f4 1252 */
ee7abb04
SH		 1253 if (otherdev && netif_running(otherdev) &&
1254 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1255 struct sky2_port *osky2 = netdev_priv(otherdev);
1256 u16 cmd;
1257
1258 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1259 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1260 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1261
1262 sky2->rx_csum = 0;
1263 osky2->rx_csum = 0;
1264 }
843a46f4 1265
cd28ab6a
SH		 1266 if (netif_msg_ifup(sky2))
1267 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1268
55d7b4e6
SH		 1269 netif_carrier_off(dev);
1270
cd28ab6a
SH		 1271 /* must be power of 2 */
1272 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1273 TX_RING_SIZE *
1274 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1275 &sky2->tx_le_map);
1276 if (!sky2->tx_le)
1277 goto err_out;
1278
6cdbbdf3 1279 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1280 GFP_KERNEL);
1281 if (!sky2->tx_ring)
1282 goto err_out;
1283 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1284
1285 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1286 &sky2->rx_le_map);
1287 if (!sky2->rx_le)
1288 goto err_out;
1289 memset(sky2->rx_le, 0, RX_LE_BYTES);
1290
291ea614 1291 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1292 GFP_KERNEL);
1293 if (!sky2->rx_ring)
1294 goto err_out;
1295
d3bcfbeb 1296 sky2_phy_power(hw, port, 1);
1297
cd28ab6a
SH		 1298 sky2_mac_init(hw, port);
1299
67712901
SH		 1300 /* Register is number of 4K blocks on internal RAM buffer. */
1301 ramsize = sky2_read8(hw, B2_E_0) * 4;
1302 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1303
67712901
SH		 1304 if (ramsize > 0) {
1305 u32 rxspace;
cd28ab6a 1306
67712901
SH		 1307 if (ramsize < 16)
1308 rxspace = ramsize / 2;
1309 else
1310 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1311
67712901
SH		 1312 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1313 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1314
1315 /* Make sure SyncQ is disabled */
1316 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1317 RB_RST_SET);
1318 }
793b883e 1319
af4ed7e6 1320 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1321
69161611
SH		 1322 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1323 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1324 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1325
977bdf06 1326 /* Set almost empty threshold */
c2716fb4
SH		 1327 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1328 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1329 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1330
6b1a3aef 1331 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1332 TX_RING_SIZE - 1);
cd28ab6a 1333
6b1a3aef 1334 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1335 if (err)
1336 goto err_out;
1337
cd28ab6a 1338 /* Enable interrupts from phy/mac for port */
e07b1aa8 1339 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1340 imask |= portirq_msk[port];
e07b1aa8
SH		 1341 sky2_write32(hw, B0_IMSK, imask);
1342
cd28ab6a
SH		 1343 return 0;
1344
1345err_out:
1b537565 1346 if (sky2->rx_le) {
cd28ab6a
SH		 1347 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1348 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1349 sky2->rx_le = NULL;
1350 }
1351 if (sky2->tx_le) {
cd28ab6a
SH		 1352 pci_free_consistent(hw->pdev,
1353 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1354 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1355 sky2->tx_le = NULL;
1356 }
1357 kfree(sky2->tx_ring);
1358 kfree(sky2->rx_ring);
cd28ab6a 1359
1b537565
SH		 1360 sky2->tx_ring = NULL;
1361 sky2->rx_ring = NULL;
cd28ab6a
SH		 1362 return err;
1363}
1364
793b883e
SH		 1365/* Modular subtraction in ring */
1366static inline int tx_dist(unsigned tail, unsigned head)
1367{
cb5d9547 1368 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1369}
cd28ab6a 1370
793b883e
SH		 1371/* Number of list elements available for next tx */
1372static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1373{
793b883e 1374 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1375}
1376
793b883e 1377/* Estimate of number of transmit list elements required */
28bd181a 1378static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1379{
793b883e
SH		 1380 unsigned count;
1381
1382 count = sizeof(dma_addr_t) / sizeof(u32);
1383 count += skb_shinfo(skb)->nr_frags * count;
1384
89114afd 1385 if (skb_is_gso(skb))
793b883e
SH		 1386 ++count;
1387
84fa7933 1388 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1389 ++count;
1390
1391 return count;
cd28ab6a
SH		 1392}
1393
793b883e
SH		 1394/*
1395 * Put one packet in ring for transmit.
1396 * A single packet can generate multiple list elements, and
1397 * the number of ring elements will probably be less than the number
1398 * of list elements used.
1399 */
cd28ab6a
SH		 1400static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1401{
1402 struct sky2_port *sky2 = netdev_priv(dev);
1403 struct sky2_hw *hw = sky2->hw;
d1f13708 1404 struct sky2_tx_le *le = NULL;
6cdbbdf3 1405 struct tx_ring_info *re;
cd28ab6a
SH		 1406 unsigned i, len;
1407 dma_addr_t mapping;
1408 u32 addr64;
1409 u16 mss;
1410 u8 ctrl;
1411
2bb8c262
SH		 1412 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1413 return NETDEV_TX_BUSY;
cd28ab6a 1414
793b883e 1415 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1416 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1417 dev->name, sky2->tx_prod, skb->len);
1418
cd28ab6a
SH		 1419 len = skb_headlen(skb);
1420 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1421 addr64 = upper_32_bits(mapping);
793b883e 1422
a018e330 1423 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1424 if (addr64 != sky2->tx_addr64 ||
1425 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1426 le = get_tx_le(sky2);
f65b138c 1427 le->addr = cpu_to_le32(addr64);
793b883e 1428 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1429 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1430 }
cd28ab6a
SH		 1431
1432 /* Check for TCP Segmentation Offload */
7967168c 1433 mss = skb_shinfo(skb)->gso_size;
793b883e 1434 if (mss != 0) {
69161611
SH		 1435 if (hw->chip_id != CHIP_ID_YUKON_EX)
1436 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1437
1438 if (mss != sky2->tx_last_mss) {
1439 le = get_tx_le(sky2);
1440 le->addr = cpu_to_le32(mss);
1441 if (hw->chip_id == CHIP_ID_YUKON_EX)
1442 le->opcode = OP_MSS | HW_OWNER;
1443 else
1444 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1445 sky2->tx_last_mss = mss;
1446 }
cd28ab6a
SH		 1447 }
1448
cd28ab6a 1449 ctrl = 0;
d1f13708 1450#ifdef SKY2_VLAN_TAG_USED
1451 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1452 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1453 if (!le) {
1454 le = get_tx_le(sky2);
f65b138c 1455 le->addr = 0;
d1f13708 1456 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1457 } else
1458 le->opcode |= OP_VLAN;
1459 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1460 ctrl |= INS_VLAN;
1461 }
1462#endif
1463
1464 /* Handle TCP checksum offload */
84fa7933 1465 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611
SH		 1466 /* On Yukon EX (some versions) encoding change. */
1467 if (hw->chip_id == CHIP_ID_YUKON_EX
1468 && hw->chip_rev != CHIP_REV_YU_EX_B0)
1469 ctrl |= CALSUM; /* auto checksum */
1470 else {
1471 const unsigned offset = skb_transport_offset(skb);
1472 u32 tcpsum;
1473
1474 tcpsum = offset << 16; /* sum start */
1475 tcpsum |= offset + skb->csum_offset; /* sum write */
1476
1477 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1478 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1479 ctrl |= UDPTCP;
1480
1481 if (tcpsum != sky2->tx_tcpsum) {
1482 sky2->tx_tcpsum = tcpsum;
1483
1484 le = get_tx_le(sky2);
1485 le->addr = cpu_to_le32(tcpsum);
1486 le->length = 0; /* initial checksum value */
1487 le->ctrl = 1; /* one packet */
1488 le->opcode = OP_TCPLISW | HW_OWNER;
1489 }
1d179332 1490 }
cd28ab6a
SH		 1491 }
1492
1493 le = get_tx_le(sky2);
f65b138c 1494 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1495 le->length = cpu_to_le16(len);
1496 le->ctrl = ctrl;
793b883e 1497 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1498
291ea614 1499 re = tx_le_re(sky2, le);
cd28ab6a 1500 re->skb = skb;
6cdbbdf3 1501 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1502 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1503
1504 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1505 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1506
1507 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1508 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1509 addr64 = upper_32_bits(mapping);
793b883e
SH		 1510 if (addr64 != sky2->tx_addr64) {
1511 le = get_tx_le(sky2);
f65b138c 1512 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1513 le->ctrl = 0;
1514 le->opcode = OP_ADDR64 | HW_OWNER;
1515 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1516 }
1517
1518 le = get_tx_le(sky2);
f65b138c 1519 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1520 le->length = cpu_to_le16(frag->size);
1521 le->ctrl = ctrl;
793b883e 1522 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1523
291ea614
SH		 1524 re = tx_le_re(sky2, le);
1525 re->skb = skb;
1526 pci_unmap_addr_set(re, mapaddr, mapping);
1527 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1528 }
6cdbbdf3 1529
cd28ab6a
SH		 1530 le->ctrl |= EOP;
1531
97bda706 1532 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1533 netif_stop_queue(dev);
b19666d9 1534
290d4de5 1535 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1536
cd28ab6a
SH		 1537 dev->trans_start = jiffies;
1538 return NETDEV_TX_OK;
1539}
1540
cd28ab6a 1541/*
793b883e
SH		 1542 * Free ring elements from starting at tx_cons until "done"
1543 *
1544 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1545 * buffers so make sure not to free skb to early.
cd28ab6a 1546 */
d11c13e7 1547static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1548{
d11c13e7 1549 struct net_device *dev = sky2->netdev;
af2a58ac 1550 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1551 unsigned idx;
cd28ab6a 1552
0e3ff6aa 1553 BUG_ON(done >= TX_RING_SIZE);
2224795d 1554
291ea614
SH		 1555 for (idx = sky2->tx_cons; idx != done;
1556 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1557 struct sky2_tx_le *le = sky2->tx_le + idx;
1558 struct tx_ring_info *re = sky2->tx_ring + idx;
1559
1560 switch(le->opcode & ~HW_OWNER) {
1561 case OP_LARGESEND:
1562 case OP_PACKET:
1563 pci_unmap_single(pdev,
1564 pci_unmap_addr(re, mapaddr),
1565 pci_unmap_len(re, maplen),
1566 PCI_DMA_TODEVICE);
af2a58ac 1567 break;
291ea614
SH		 1568 case OP_BUFFER:
1569 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1570 pci_unmap_len(re, maplen),
734d1868 1571 PCI_DMA_TODEVICE);
291ea614
SH		 1572 break;
1573 }
1574
1575 if (le->ctrl & EOP) {
1576 if (unlikely(netif_msg_tx_done(sky2)))
1577 printk(KERN_DEBUG "%s: tx done %u\n",
1578 dev->name, idx);
3cf26753 1579
2bf56fe2 1580 sky2->net_stats.tx_packets++;
1581 sky2->net_stats.tx_bytes += re->skb->len;
1582
794b2bd2 1583 dev_kfree_skb_any(re->skb);
3cf26753 1584 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1585 }
793b883e 1586 }
793b883e 1587
291ea614 1588 sky2->tx_cons = idx;
50432cb5
SH		 1589 smp_mb();
1590
22e11703 1591 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1592 netif_wake_queue(dev);
cd28ab6a
SH		 1593}
1594
1595/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1596static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1597{
2bb8c262
SH		 1598 struct sky2_port *sky2 = netdev_priv(dev);
1599
1600 netif_tx_lock_bh(dev);
d11c13e7 1601 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1602 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1603}
1604
1605/* Network shutdown */
1606static int sky2_down(struct net_device *dev)
1607{
1608 struct sky2_port *sky2 = netdev_priv(dev);
1609 struct sky2_hw *hw = sky2->hw;
1610 unsigned port = sky2->port;
1611 u16 ctrl;
e07b1aa8 1612 u32 imask;
cd28ab6a 1613
1b537565
SH		 1614 /* Never really got started! */
1615 if (!sky2->tx_le)
1616 return 0;
1617
cd28ab6a
SH		 1618 if (netif_msg_ifdown(sky2))
1619 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1620
018d1c66 1621 /* Stop more packets from being queued */
cd28ab6a
SH		 1622 netif_stop_queue(dev);
1623
ebc646f6
SH		 1624 /* Disable port IRQ */
1625 imask = sky2_read32(hw, B0_IMSK);
1626 imask &= ~portirq_msk[port];
1627 sky2_write32(hw, B0_IMSK, imask);
1628
d3bcfbeb 1629 sky2_gmac_reset(hw, port);
793b883e 1630
cd28ab6a
SH		 1631 /* Stop transmitter */
1632 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1633 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1634
1635 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1636 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1637
1638 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1639 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1640 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1641
1642 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1643
1644 /* Workaround shared GMAC reset */
793b883e
SH		 1645 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1646 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1648
1649 /* Disable Force Sync bit and Enable Alloc bit */
1650 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1651 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1652
1653 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1654 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1655 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1656
1657 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1658 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1659 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1660
1661 /* Reset the Tx prefetch units */
1662 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1663 PREF_UNIT_RST_SET);
1664
1665 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1666
6b1a3aef 1667 sky2_rx_stop(sky2);
cd28ab6a
SH		 1668
1669 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1670 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1671
d3bcfbeb 1672 sky2_phy_power(hw, port, 0);
1673
55d7b4e6
SH		 1674 netif_carrier_off(dev);
1675
d571b694 1676 /* turn off LED's */
cd28ab6a
SH		 1677 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1678
018d1c66 1679 synchronize_irq(hw->pdev->irq);
1680
2bb8c262 1681 sky2_tx_clean(dev);
cd28ab6a
SH		 1682 sky2_rx_clean(sky2);
1683
1684 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1685 sky2->rx_le, sky2->rx_le_map);
1686 kfree(sky2->rx_ring);
1687
1688 pci_free_consistent(hw->pdev,
1689 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1690 sky2->tx_le, sky2->tx_le_map);
1691 kfree(sky2->tx_ring);
1692
1b537565
SH		 1693 sky2->tx_le = NULL;
1694 sky2->rx_le = NULL;
1695
1696 sky2->rx_ring = NULL;
1697 sky2->tx_ring = NULL;
1698
cd28ab6a
SH		 1699 return 0;
1700}
1701
1702static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1703{
b89165f2 1704 if (!sky2_is_copper(hw))
793b883e
SH		 1705 return SPEED_1000;
1706
cd28ab6a
SH		 1707 if (hw->chip_id == CHIP_ID_YUKON_FE)
1708 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1709
1710 switch (aux & PHY_M_PS_SPEED_MSK) {
1711 case PHY_M_PS_SPEED_1000:
1712 return SPEED_1000;
1713 case PHY_M_PS_SPEED_100:
1714 return SPEED_100;
1715 default:
1716 return SPEED_10;
1717 }
1718}
1719
1720static void sky2_link_up(struct sky2_port *sky2)
1721{
1722 struct sky2_hw *hw = sky2->hw;
1723 unsigned port = sky2->port;
1724 u16 reg;
16ad91e1
SH		 1725 static const char *fc_name[] = {
1726 [FC_NONE] = "none",
1727 [FC_TX] = "tx",
1728 [FC_RX] = "rx",
1729 [FC_BOTH] = "both",
1730 };
cd28ab6a 1731
cd28ab6a 1732 /* enable Rx/Tx */
2eaba1a2 1733 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1734 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1735 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1736
1737 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1738
1739 netif_carrier_on(sky2->netdev);
cd28ab6a
SH		 1740
1741 /* Turn on link LED */
793b883e 1742 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1743 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1744
93745494
SH		 1745 if (hw->chip_id == CHIP_ID_YUKON_XL
1746 || hw->chip_id == CHIP_ID_YUKON_EC_U
1747 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1748 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1749 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1750
1751 switch(sky2->speed) {
1752 case SPEED_10:
1753 led |= PHY_M_LEDC_INIT_CTRL(7);
1754 break;
1755
1756 case SPEED_100:
1757 led |= PHY_M_LEDC_STA1_CTRL(7);
1758 break;
1759
1760 case SPEED_1000:
1761 led |= PHY_M_LEDC_STA0_CTRL(7);
1762 break;
1763 }
793b883e
SH		 1764
1765 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1766 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1767 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1768 }
1769
cd28ab6a
SH		 1770 if (netif_msg_link(sky2))
1771 printk(KERN_INFO PFX
d571b694 1772 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1773 sky2->netdev->name, sky2->speed,
1774 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1775 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1776}
1777
1778static void sky2_link_down(struct sky2_port *sky2)
1779{
1780 struct sky2_hw *hw = sky2->hw;
1781 unsigned port = sky2->port;
1782 u16 reg;
1783
1784 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1785
1786 reg = gma_read16(hw, port, GM_GP_CTRL);
1787 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1788 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1789
cd28ab6a 1790 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1791
1792 /* Turn on link LED */
1793 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1794
1795 if (netif_msg_link(sky2))
1796 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1797
cd28ab6a
SH		 1798 sky2_phy_init(hw, port);
1799}
1800
16ad91e1
SH		 1801static enum flow_control sky2_flow(int rx, int tx)
1802{
1803 if (rx)
1804 return tx ? FC_BOTH : FC_RX;
1805 else
1806 return tx ? FC_TX : FC_NONE;
1807}
1808
793b883e
SH		 1809static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1810{
1811 struct sky2_hw *hw = sky2->hw;
1812 unsigned port = sky2->port;
da4c1ff4 1813 u16 advert, lpa;
793b883e 1814
da4c1ff4 1815 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1816 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1817 if (lpa & PHY_M_AN_RF) {
1818 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1819 return -1;
1820 }
1821
793b883e
SH		 1822 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1823 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1824 sky2->netdev->name);
1825 return -1;
1826 }
1827
793b883e 1828 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1829 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1830
da4c1ff4
SH		 1831 /* Since the pause result bits seem to in different positions on
1832 * different chips. look at registers.
1833 */
1834 if (!sky2_is_copper(hw)) {
1835 /* Shift for bits in fiber PHY */
1836 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1837 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1838
1839 if (advert & ADVERTISE_1000XPAUSE)
1840 advert |= ADVERTISE_PAUSE_CAP;
1841 if (advert & ADVERTISE_1000XPSE_ASYM)
1842 advert |= ADVERTISE_PAUSE_ASYM;
1843 if (lpa & LPA_1000XPAUSE)
1844 lpa |= LPA_PAUSE_CAP;
1845 if (lpa & LPA_1000XPAUSE_ASYM)
1846 lpa |= LPA_PAUSE_ASYM;
1847 }
793b883e 1848
da4c1ff4
SH		 1849 sky2->flow_status = FC_NONE;
1850 if (advert & ADVERTISE_PAUSE_CAP) {
1851 if (lpa & LPA_PAUSE_CAP)
1852 sky2->flow_status = FC_BOTH;
1853 else if (advert & ADVERTISE_PAUSE_ASYM)
1854 sky2->flow_status = FC_RX;
1855 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1856 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1857 sky2->flow_status = FC_TX;
1858 }
793b883e 1859
16ad91e1 1860 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1861 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1862 sky2->flow_status = FC_NONE;
2eaba1a2 1863
da4c1ff4 1864 if (sky2->flow_status & FC_TX)
793b883e
SH		 1865 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1866 else
1867 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1868
1869 return 0;
1870}
cd28ab6a 1871
e07b1aa8
SH		 1872/* Interrupt from PHY */
1873static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1874{
e07b1aa8
SH		 1875 struct net_device *dev = hw->dev[port];
1876 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1877 u16 istatus, phystat;
1878
ebc646f6
SH		 1879 if (!netif_running(dev))
1880 return;
1881
e07b1aa8
SH		 1882 spin_lock(&sky2->phy_lock);
1883 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1884 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1885
cd28ab6a
SH		 1886 if (netif_msg_intr(sky2))
1887 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1888 sky2->netdev->name, istatus, phystat);
1889
2eaba1a2 1890 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1891 if (sky2_autoneg_done(sky2, phystat) == 0)
1892 sky2_link_up(sky2);
1893 goto out;
1894 }
cd28ab6a 1895
793b883e
SH		 1896 if (istatus & PHY_M_IS_LSP_CHANGE)
1897 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1898
793b883e
SH		 1899 if (istatus & PHY_M_IS_DUP_CHANGE)
1900 sky2->duplex =
1901 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1902
793b883e
SH		 1903 if (istatus & PHY_M_IS_LST_CHANGE) {
1904 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1905 sky2_link_up(sky2);
793b883e
SH		 1906 else
1907 sky2_link_down(sky2);
cd28ab6a 1908 }
793b883e 1909out:
e07b1aa8 1910 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1911}
1912
62335ab0 1913/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1914 * and tx queue is full (stopped).
1915 */
cd28ab6a
SH		 1916static void sky2_tx_timeout(struct net_device *dev)
1917{
1918 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1919 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1920
1921 if (netif_msg_timer(sky2))
1922 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1923
8f24664d 1924 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1925 dev->name, sky2->tx_cons, sky2->tx_prod,
1926 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1927 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1928
81906791
SH		 1929 /* can't restart safely under softirq */
1930 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1931}
1932
1933static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1934{
6b1a3aef 1935 struct sky2_port *sky2 = netdev_priv(dev);
1936 struct sky2_hw *hw = sky2->hw;
b628ed98 1937 unsigned port = sky2->port;
6b1a3aef 1938 int err;
1939 u16 ctl, mode;
e07b1aa8 1940 u32 imask;
cd28ab6a
SH		 1941
1942 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1943 return -EINVAL;
1944
d2adf4f6
SH		 1945 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1946 return -EINVAL;
1947
6b1a3aef 1948 if (!netif_running(dev)) {
1949 dev->mtu = new_mtu;
1950 return 0;
1951 }
1952
e07b1aa8 1953 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1954 sky2_write32(hw, B0_IMSK, 0);
1955
018d1c66 1956 dev->trans_start = jiffies; /* prevent tx timeout */
1957 netif_stop_queue(dev);
1958 netif_poll_disable(hw->dev[0]);
1959
e07b1aa8
SH		 1960 synchronize_irq(hw->pdev->irq);
1961
69161611
SH		 1962 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1963 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 1964
1965 ctl = gma_read16(hw, port, GM_GP_CTRL);
1966 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 1967 sky2_rx_stop(sky2);
1968 sky2_rx_clean(sky2);
cd28ab6a
SH		 1969
1970 dev->mtu = new_mtu;
14d0263f 1971
6b1a3aef 1972 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1973 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1974
1975 if (dev->mtu > ETH_DATA_LEN)
1976 mode |= GM_SMOD_JUMBO_ENA;
1977
b628ed98 1978 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1979
b628ed98 1980 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1981
6b1a3aef 1982 err = sky2_rx_start(sky2);
e07b1aa8 1983 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1984
1b537565
SH		 1985 if (err)
1986 dev_close(dev);
1987 else {
b628ed98 1988 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1989
1990 netif_poll_enable(hw->dev[0]);
1991 netif_wake_queue(dev);
1992 }
1993
cd28ab6a
SH		 1994 return err;
1995}
1996
14d0263f
SH		 1997/* For small just reuse existing skb for next receive */
1998static struct sk_buff *receive_copy(struct sky2_port *sky2,
1999 const struct rx_ring_info *re,
2000 unsigned length)
2001{
2002 struct sk_buff *skb;
2003
2004 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2005 if (likely(skb)) {
2006 skb_reserve(skb, 2);
2007 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2008 length, PCI_DMA_FROMDEVICE);
d626f62b 2009 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2010 skb->ip_summed = re->skb->ip_summed;
2011 skb->csum = re->skb->csum;
2012 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2013 length, PCI_DMA_FROMDEVICE);
2014 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2015 skb_put(skb, length);
14d0263f
SH		 2016 }
2017 return skb;
2018}
2019
2020/* Adjust length of skb with fragments to match received data */
2021static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2022 unsigned int length)
2023{
2024 int i, num_frags;
2025 unsigned int size;
2026
2027 /* put header into skb */
2028 size = min(length, hdr_space);
2029 skb->tail += size;
2030 skb->len += size;
2031 length -= size;
2032
2033 num_frags = skb_shinfo(skb)->nr_frags;
2034 for (i = 0; i < num_frags; i++) {
2035 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2036
2037 if (length == 0) {
2038 /* don't need this page */
2039 __free_page(frag->page);
2040 --skb_shinfo(skb)->nr_frags;
2041 } else {
2042 size = min(length, (unsigned) PAGE_SIZE);
2043
2044 frag->size = size;
2045 skb->data_len += size;
2046 skb->truesize += size;
2047 skb->len += size;
2048 length -= size;
2049 }
2050 }
2051}
2052
2053/* Normal packet - take skb from ring element and put in a new one */
2054static struct sk_buff *receive_new(struct sky2_port *sky2,
2055 struct rx_ring_info *re,
2056 unsigned int length)
2057{
2058 struct sk_buff *skb, *nskb;
2059 unsigned hdr_space = sky2->rx_data_size;
2060
14d0263f
SH		 2061 /* Don't be tricky about reusing pages (yet) */
2062 nskb = sky2_rx_alloc(sky2);
2063 if (unlikely(!nskb))
2064 return NULL;
2065
2066 skb = re->skb;
2067 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2068
2069 prefetch(skb->data);
2070 re->skb = nskb;
2071 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2072
2073 if (skb_shinfo(skb)->nr_frags)
2074 skb_put_frags(skb, hdr_space, length);
2075 else
489b10c1 2076 skb_put(skb, length);
14d0263f
SH		 2077 return skb;
2078}
2079
cd28ab6a
SH		 2080/*
2081 * Receive one packet.
d571b694 2082 * For larger packets, get new buffer.
cd28ab6a 2083 */
497d7c86 2084static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2085 u16 length, u32 status)
2086{
497d7c86 2087 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2088 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2089 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2090
2091 if (unlikely(netif_msg_rx_status(sky2)))
2092 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2093 dev->name, sky2->rx_next, status, length);
cd28ab6a 2094
793b883e 2095 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2096 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2097
42eeea01 2098 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2099 goto error;
2100
42eeea01 2101 if (!(status & GMR_FS_RX_OK))
2102 goto resubmit;
2103
71749531
SH		 2104 if (status >> 16 != length)
2105 goto len_mismatch;
2106
14d0263f
SH		 2107 if (length < copybreak)
2108 skb = receive_copy(sky2, re, length);
2109 else
2110 skb = receive_new(sky2, re, length);
793b883e 2111resubmit:
14d0263f 2112 sky2_rx_submit(sky2, re);
79e57d32 2113
cd28ab6a
SH		 2114 return skb;
2115
71749531
SH		 2116len_mismatch:
2117 /* Truncation of overlength packets
2118 causes PHY length to not match MAC length */
2119 ++sky2->net_stats.rx_length_errors;
2120
cd28ab6a 2121error:
6e15b712 2122 ++sky2->net_stats.rx_errors;
b6d77734 2123 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2124 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2125 goto resubmit;
2126 }
6e15b712 2127
3be92a70 2128 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2129 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2130 dev->name, status, length);
793b883e
SH		 2131
2132 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2133 sky2->net_stats.rx_length_errors++;
2134 if (status & GMR_FS_FRAGMENT)
2135 sky2->net_stats.rx_frame_errors++;
2136 if (status & GMR_FS_CRC_ERR)
2137 sky2->net_stats.rx_crc_errors++;
79e57d32 2138
793b883e 2139 goto resubmit;
cd28ab6a
SH		 2140}
2141
e07b1aa8
SH		 2142/* Transmit complete */
2143static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2144{
e07b1aa8 2145 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2146
e07b1aa8 2147 if (netif_running(dev)) {
2bb8c262 2148 netif_tx_lock(dev);
e07b1aa8 2149 sky2_tx_complete(sky2, last);
2bb8c262 2150 netif_tx_unlock(dev);
2224795d 2151 }
cd28ab6a
SH		 2152}
2153
e07b1aa8
SH		 2154/* Process status response ring */
2155static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2156{
e07b1aa8 2157 int work_done = 0;
55c9dd35 2158 unsigned rx[2] = { 0, 0 };
e71ebd73 2159 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2160
af2a58ac 2161 rmb();
bea86103 2162
e71ebd73 2163 while (hw->st_idx != hwidx) {
55c9dd35 2164 struct sky2_port *sky2;
13210ce5 2165 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2166 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2167 struct net_device *dev;
cd28ab6a 2168 struct sk_buff *skb;
cd28ab6a
SH		 2169 u32 status;
2170 u16 length;
2171
cb5d9547 2172 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2173
69161611 2174 dev = hw->dev[port];
13210ce5 2175 sky2 = netdev_priv(dev);
f65b138c
SH		 2176 length = le16_to_cpu(le->length);
2177 status = le32_to_cpu(le->status);
cd28ab6a 2178
e71ebd73 2179 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2180 case OP_RXSTAT:
55c9dd35 2181 ++rx[port];
497d7c86 2182 skb = sky2_receive(dev, length, status);
3225b919
SH		 2183 if (unlikely(!skb)) {
2184 sky2->net_stats.rx_dropped++;
55c9dd35 2185 break;
3225b919 2186 }
13210ce5 2187
69161611
SH		 2188 /* This chip reports checksum status differently */
2189 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2190 if (sky2->rx_csum &&
2191 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2192 (le->css & CSS_TCPUDPCSOK))
2193 skb->ip_summed = CHECKSUM_UNNECESSARY;
2194 else
2195 skb->ip_summed = CHECKSUM_NONE;
2196 }
2197
13210ce5 2198 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2199 sky2->net_stats.rx_packets++;
2200 sky2->net_stats.rx_bytes += skb->len;
13210ce5 2201 dev->last_rx = jiffies;
2202
d1f13708 2203#ifdef SKY2_VLAN_TAG_USED
2204 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2205 vlan_hwaccel_receive_skb(skb,
2206 sky2->vlgrp,
2207 be16_to_cpu(sky2->rx_tag));
2208 } else
2209#endif
cd28ab6a 2210 netif_receive_skb(skb);
13210ce5 2211
22e11703 2212 /* Stop after net poll weight */
13210ce5 2213 if (++work_done >= to_do)
2214 goto exit_loop;
cd28ab6a
SH		 2215 break;
2216
d1f13708 2217#ifdef SKY2_VLAN_TAG_USED
2218 case OP_RXVLAN:
2219 sky2->rx_tag = length;
2220 break;
2221
2222 case OP_RXCHKSVLAN:
2223 sky2->rx_tag = length;
2224 /* fall through */
2225#endif
cd28ab6a 2226 case OP_RXCHKS:
87418307
SH		 2227 if (!sky2->rx_csum)
2228 break;
2229
69161611
SH		 2230 if (hw->chip_id == CHIP_ID_YUKON_EX)
2231 break;
2232
87418307
SH		 2233 /* Both checksum counters are programmed to start at
2234 * the same offset, so unless there is a problem they
2235 * should match. This failure is an early indication that
2236 * hardware receive checksumming won't work.
2237 */
2238 if (likely(status >> 16 == (status & 0xffff))) {
2239 skb = sky2->rx_ring[sky2->rx_next].skb;
2240 skb->ip_summed = CHECKSUM_COMPLETE;
2241 skb->csum = status & 0xffff;
2242 } else {
2243 printk(KERN_NOTICE PFX "%s: hardware receive "
2244 "checksum problem (status = %#x)\n",
2245 dev->name, status);
2246 sky2->rx_csum = 0;
2247 sky2_write32(sky2->hw,
69161611 2248 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2249 BMU_DIS_RX_CHKSUM);
2250 }
cd28ab6a
SH		 2251 break;
2252
2253 case OP_TXINDEXLE:
13b97b74 2254 /* TX index reports status for both ports */
f55925d7
SH		 2255 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2256 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2257 if (hw->dev[1])
2258 sky2_tx_done(hw->dev[1],
2259 ((status >> 24) & 0xff)
2260 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2261 break;
2262
cd28ab6a
SH		 2263 default:
2264 if (net_ratelimit())
793b883e 2265 printk(KERN_WARNING PFX
e71ebd73 2266 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a 2267 }
13210ce5 2268 }
cd28ab6a 2269
fe2a24df
SH		 2270 /* Fully processed status ring so clear irq */
2271 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2272
13210ce5 2273exit_loop:
55c9dd35
SH		 2274 if (rx[0])
2275 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2276
55c9dd35
SH		 2277 if (rx[1])
2278 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2279
e07b1aa8 2280 return work_done;
cd28ab6a
SH		 2281}
2282
2283static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2284{
2285 struct net_device *dev = hw->dev[port];
2286
3be92a70
SH		 2287 if (net_ratelimit())
2288 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2289 dev->name, status);
cd28ab6a
SH		 2290
2291 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2292 if (net_ratelimit())
2293 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2294 dev->name);
cd28ab6a
SH		 2295 /* Clear IRQ */
2296 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2297 }
2298
2299 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2300 if (net_ratelimit())
2301 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2302 dev->name);
cd28ab6a
SH		 2303
2304 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2305 }
2306
2307 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2308 if (net_ratelimit())
2309 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2310 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2311 }
2312
2313 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2314 if (net_ratelimit())
2315 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2316 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2317 }
2318
2319 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2320 if (net_ratelimit())
2321 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2322 dev->name);
cd28ab6a
SH		 2323 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2324 }
2325}
2326
2327static void sky2_hw_intr(struct sky2_hw *hw)
2328{
2329 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2330
793b883e 2331 if (status & Y2_IS_TIST_OV)
cd28ab6a 2332 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2333
2334 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2335 u16 pci_err;
2336
56a645cc 2337 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2338 if (net_ratelimit())
b02a9258
SH		 2339 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2340 pci_err);
cd28ab6a
SH		 2341
2342 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2343 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2344 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2345 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2346 }
2347
2348 if (status & Y2_IS_PCI_EXP) {
d571b694 2349 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2350 u32 pex_err;
2351
7bd656d1 2352 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2353
3be92a70 2354 if (net_ratelimit())
b02a9258
SH		 2355 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2356 pex_err);
cd28ab6a
SH		 2357
2358 /* clear the interrupt */
2359 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2360 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2361 0xffffffffUL);
cd28ab6a
SH		 2362 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2363
7bd656d1 2364 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2365 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2366 hwmsk &= ~Y2_IS_PCI_EXP;
2367 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2368 }
2369 }
2370
2371 if (status & Y2_HWE_L1_MASK)
2372 sky2_hw_error(hw, 0, status);
2373 status >>= 8;
2374 if (status & Y2_HWE_L1_MASK)
2375 sky2_hw_error(hw, 1, status);
2376}
2377
2378static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2379{
2380 struct net_device *dev = hw->dev[port];
2381 struct sky2_port *sky2 = netdev_priv(dev);
2382 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2383
2384 if (netif_msg_intr(sky2))
2385 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2386 dev->name, status);
2387
a3caeada
SH		 2388 if (status & GM_IS_RX_CO_OV)
2389 gma_read16(hw, port, GM_RX_IRQ_SRC);
2390
2391 if (status & GM_IS_TX_CO_OV)
2392 gma_read16(hw, port, GM_TX_IRQ_SRC);
2393
cd28ab6a
SH		 2394 if (status & GM_IS_RX_FF_OR) {
2395 ++sky2->net_stats.rx_fifo_errors;
2396 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2397 }
2398
2399 if (status & GM_IS_TX_FF_UR) {
2400 ++sky2->net_stats.tx_fifo_errors;
2401 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2402 }
cd28ab6a
SH		 2403}
2404
40b01727
SH		 2405/* This should never happen it is a bug. */
2406static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2407 u16 q, unsigned ring_size)
d257924e
SH		 2408{
2409 struct net_device *dev = hw->dev[port];
2410 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2411 unsigned idx;
2412 const u64 *le = (q == Q_R1 || q == Q_R2)
2413 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2414
40b01727
SH		 2415 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2416 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2417 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2418 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2419
40b01727 2420 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2421}
cd28ab6a 2422
d27ed387
SH		 2423/* If idle then force a fake soft NAPI poll once a second
2424 * to work around cases where sharing an edge triggered interrupt.
2425 */
eb35cf60
SH		 2426static inline void sky2_idle_start(struct sky2_hw *hw)
2427{
2428 if (idle_timeout > 0)
2429 mod_timer(&hw->idle_timer,
2430 jiffies + msecs_to_jiffies(idle_timeout));
2431}
2432
d27ed387
SH		 2433static void sky2_idle(unsigned long arg)
2434{
01bd7564
SH		 2435 struct sky2_hw *hw = (struct sky2_hw *) arg;
2436 struct net_device *dev = hw->dev[0];
d27ed387 2437
d27ed387
SH		 2438 if (__netif_rx_schedule_prep(dev))
2439 __netif_rx_schedule(dev);
01bd7564
SH		 2440
2441 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2442}
2443
40b01727
SH		 2444/* Hardware/software error handling */
2445static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2446{
40b01727
SH		 2447 if (net_ratelimit())
2448 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2449
1e5f1283
SH		 2450 if (status & Y2_IS_HW_ERR)
2451 sky2_hw_intr(hw);
d257924e 2452
1e5f1283
SH		 2453 if (status & Y2_IS_IRQ_MAC1)
2454 sky2_mac_intr(hw, 0);
cd28ab6a 2455
1e5f1283
SH		 2456 if (status & Y2_IS_IRQ_MAC2)
2457 sky2_mac_intr(hw, 1);
cd28ab6a 2458
1e5f1283 2459 if (status & Y2_IS_CHK_RX1)
40b01727 2460 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2461
1e5f1283 2462 if (status & Y2_IS_CHK_RX2)
40b01727 2463 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2464
1e5f1283 2465 if (status & Y2_IS_CHK_TXA1)
40b01727 2466 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2467
1e5f1283 2468 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2469 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2470}
2471
2472static int sky2_poll(struct net_device *dev0, int *budget)
2473{
2474 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
5c11ce70 2475 int work_done;
40b01727
SH		 2476 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2477
2478 if (unlikely(status & Y2_IS_ERROR))
2479 sky2_err_intr(hw, status);
2480
2481 if (status & Y2_IS_IRQ_PHY1)
2482 sky2_phy_intr(hw, 0);
2483
2484 if (status & Y2_IS_IRQ_PHY2)
2485 sky2_phy_intr(hw, 1);
cd28ab6a 2486
5c11ce70
SH		 2487 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2488 *budget -= work_done;
2489 dev0->quota -= work_done;
86fba634 2490
5c11ce70
SH		 2491 /* More work? */
2492 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
1e5f1283 2493 return 1;
5c11ce70
SH		 2494
2495 /* Bug/Errata workaround?
2496 * Need to kick the TX irq moderation timer.
2497 */
2498 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2499 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2500 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2501 }
5c11ce70
SH		 2502 netif_rx_complete(dev0);
2503
2504 sky2_read32(hw, B0_Y2_SP_LISR);
2505 return 0;
e07b1aa8
SH		 2506}
2507
7d12e780 2508static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2509{
2510 struct sky2_hw *hw = dev_id;
2511 struct net_device *dev0 = hw->dev[0];
2512 u32 status;
2513
2514 /* Reading this mask interrupts as side effect */
2515 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2516 if (status == 0 || status == ~0)
2517 return IRQ_NONE;
793b883e 2518
e07b1aa8
SH		 2519 prefetch(&hw->st_le[hw->st_idx]);
2520 if (likely(__netif_rx_schedule_prep(dev0)))
2521 __netif_rx_schedule(dev0);
793b883e 2522
cd28ab6a
SH		 2523 return IRQ_HANDLED;
2524}
2525
2526#ifdef CONFIG_NET_POLL_CONTROLLER
2527static void sky2_netpoll(struct net_device *dev)
2528{
2529 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2530 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2531
88d11360
SH		 2532 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2533 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2534}
2535#endif
2536
2537/* Chip internal frequency for clock calculations */
fb17358f 2538static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2539{
793b883e 2540 switch (hw->chip_id) {
cd28ab6a 2541 case CHIP_ID_YUKON_EC:
5a5b1ea0 2542 case CHIP_ID_YUKON_EC_U:
93745494 2543 case CHIP_ID_YUKON_EX:
fb17358f 2544 return 125; /* 125 Mhz */
cd28ab6a 2545 case CHIP_ID_YUKON_FE:
fb17358f 2546 return 100; /* 100 Mhz */
793b883e 2547 default: /* YUKON_XL */
fb17358f 2548 return 156; /* 156 Mhz */
cd28ab6a
SH		 2549 }
2550}
2551
fb17358f 2552static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2553{
fb17358f 2554 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2555}
2556
fb17358f 2557static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2558{
fb17358f 2559 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2560}
2561
fb17358f 2562
e3173832 2563static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2564{
b89165f2 2565 u8 t8;
cd28ab6a 2566
451af335
SH		 2567 /* Enable all clocks */
2568 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2569
cd28ab6a 2570 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2571
cd28ab6a
SH		 2572 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2573 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2574 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2575 hw->chip_id);
cd28ab6a
SH		 2576 return -EOPNOTSUPP;
2577 }
2578
290d4de5
SH		 2579 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2580
2581 /* This rev is really old, and requires untested workarounds */
2582 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2583 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2584 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2585 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2586 return -EOPNOTSUPP;
2587 }
2588
e3173832
SH		 2589 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2590 hw->ports = 1;
2591 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2592 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2593 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2594 ++hw->ports;
2595 }
2596
2597 return 0;
2598}
2599
2600static void sky2_reset(struct sky2_hw *hw)
2601{
2602 u16 status;
2603 int i;
2604
cd28ab6a 2605 /* disable ASF */
4f44d8ba
SH		 2606 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2607 status = sky2_read16(hw, HCU_CCSR);
2608 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2609 HCU_CCSR_UC_STATE_MSK);
2610 sky2_write16(hw, HCU_CCSR, status);
2611 } else
2612 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2613 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2614
2615 /* do a SW reset */
2616 sky2_write8(hw, B0_CTST, CS_RST_SET);
2617 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2618
2619 /* clear PCI errors, if any */
56a645cc 2620 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2621
cd28ab6a 2622 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2623 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2624
cd28ab6a
SH		 2625
2626 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2627
2628 /* clear any PEX errors */
7bd656d1
SH		 2629 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2630 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2631
cd28ab6a 2632
ae306cca 2633 sky2_power_on(hw);
cd28ab6a
SH		 2634
2635 for (i = 0; i < hw->ports; i++) {
2636 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2637 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2638
2639 if (hw->chip_id == CHIP_ID_YUKON_EX)
2640 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2641 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2642 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2643 }
2644
2645 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2646
793b883e
SH		 2647 /* Clear I2C IRQ noise */
2648 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2649
2650 /* turn off hardware timer (unused) */
2651 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2652 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2653
cd28ab6a
SH		 2654 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2655
69634ee7
SH		 2656 /* Turn off descriptor polling */
2657 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2658
2659 /* Turn off receive timestamp */
2660 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2661 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2662
2663 /* enable the Tx Arbiters */
2664 for (i = 0; i < hw->ports; i++)
2665 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2666
2667 /* Initialize ram interface */
2668 for (i = 0; i < hw->ports; i++) {
793b883e 2669 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2670
2671 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2672 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2673 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2674 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2675 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2676 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2677 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2678 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2679 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2680 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2681 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2682 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2683 }
2684
7bd656d1 2685 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2686
cd28ab6a 2687 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2688 sky2_gmac_reset(hw, i);
cd28ab6a 2689
cd28ab6a
SH		 2690 memset(hw->st_le, 0, STATUS_LE_BYTES);
2691 hw->st_idx = 0;
2692
2693 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2694 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2695
2696 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2697 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2698
2699 /* Set the list last index */
793b883e 2700 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2701
290d4de5
SH		 2702 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2703 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2704
290d4de5
SH		 2705 /* set Status-FIFO ISR watermark */
2706 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2707 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2708 else
2709 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2710
290d4de5 2711 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2712 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2713 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2714
793b883e 2715 /* enable status unit */
cd28ab6a
SH		 2716 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2717
2718 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2719 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2720 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2721}
2722
81906791
SH		 2723static void sky2_restart(struct work_struct *work)
2724{
2725 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2726 struct net_device *dev;
2727 int i, err;
2728
81906791
SH		 2729 del_timer_sync(&hw->idle_timer);
2730
2731 rtnl_lock();
2732 sky2_write32(hw, B0_IMSK, 0);
2733 sky2_read32(hw, B0_IMSK);
2734
2735 netif_poll_disable(hw->dev[0]);
2736
2737 for (i = 0; i < hw->ports; i++) {
2738 dev = hw->dev[i];
2739 if (netif_running(dev))
2740 sky2_down(dev);
2741 }
2742
2743 sky2_reset(hw);
2744 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2745 netif_poll_enable(hw->dev[0]);
2746
2747 for (i = 0; i < hw->ports; i++) {
2748 dev = hw->dev[i];
2749 if (netif_running(dev)) {
2750 err = sky2_up(dev);
2751 if (err) {
2752 printk(KERN_INFO PFX "%s: could not restart %d\n",
2753 dev->name, err);
2754 dev_close(dev);
2755 }
2756 }
2757 }
2758
2759 sky2_idle_start(hw);
2760
2761 rtnl_unlock();
2762}
2763
e3173832
SH		 2764static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2765{
2766 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2767}
2768
2769static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2770{
2771 const struct sky2_port *sky2 = netdev_priv(dev);
2772
2773 wol->supported = sky2_wol_supported(sky2->hw);
2774 wol->wolopts = sky2->wol;
2775}
2776
2777static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2778{
2779 struct sky2_port *sky2 = netdev_priv(dev);
2780 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2781
e3173832
SH		 2782 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2783 return -EOPNOTSUPP;
2784
2785 sky2->wol = wol->wolopts;
2786
69161611 2787 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
e3173832
SH		 2788 sky2_write32(hw, B0_CTST, sky2->wol
2789 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2790
2791 if (!netif_running(dev))
2792 sky2_wol_init(sky2);
cd28ab6a
SH		 2793 return 0;
2794}
2795
28bd181a 2796static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2797{
b89165f2
SH		 2798 if (sky2_is_copper(hw)) {
2799 u32 modes = SUPPORTED_10baseT_Half
2800 | SUPPORTED_10baseT_Full
2801 | SUPPORTED_100baseT_Half
2802 | SUPPORTED_100baseT_Full
2803 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2804
2805 if (hw->chip_id != CHIP_ID_YUKON_FE)
2806 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2807 | SUPPORTED_1000baseT_Full;
2808 return modes;
cd28ab6a 2809 } else
b89165f2
SH		 2810 return SUPPORTED_1000baseT_Half
2811 | SUPPORTED_1000baseT_Full
2812 | SUPPORTED_Autoneg
2813 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2814}
2815
793b883e 2816static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2817{
2818 struct sky2_port *sky2 = netdev_priv(dev);
2819 struct sky2_hw *hw = sky2->hw;
2820
2821 ecmd->transceiver = XCVR_INTERNAL;
2822 ecmd->supported = sky2_supported_modes(hw);
2823 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2824 if (sky2_is_copper(hw)) {
cd28ab6a 2825 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2826 | SUPPORTED_10baseT_Full
2827 | SUPPORTED_100baseT_Half
2828 | SUPPORTED_100baseT_Full
2829 | SUPPORTED_1000baseT_Half
2830 | SUPPORTED_1000baseT_Full
2831 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2832 ecmd->port = PORT_TP;
b89165f2
SH		 2833 ecmd->speed = sky2->speed;
2834 } else {
2835 ecmd->speed = SPEED_1000;
cd28ab6a 2836 ecmd->port = PORT_FIBRE;
b89165f2 2837 }
cd28ab6a
SH		 2838
2839 ecmd->advertising = sky2->advertising;
2840 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2841 ecmd->duplex = sky2->duplex;
2842 return 0;
2843}
2844
2845static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2846{
2847 struct sky2_port *sky2 = netdev_priv(dev);
2848 const struct sky2_hw *hw = sky2->hw;
2849 u32 supported = sky2_supported_modes(hw);
2850
2851 if (ecmd->autoneg == AUTONEG_ENABLE) {
2852 ecmd->advertising = supported;
2853 sky2->duplex = -1;
2854 sky2->speed = -1;
2855 } else {
2856 u32 setting;
2857
793b883e 2858 switch (ecmd->speed) {
cd28ab6a
SH		 2859 case SPEED_1000:
2860 if (ecmd->duplex == DUPLEX_FULL)
2861 setting = SUPPORTED_1000baseT_Full;
2862 else if (ecmd->duplex == DUPLEX_HALF)
2863 setting = SUPPORTED_1000baseT_Half;
2864 else
2865 return -EINVAL;
2866 break;
2867 case SPEED_100:
2868 if (ecmd->duplex == DUPLEX_FULL)
2869 setting = SUPPORTED_100baseT_Full;
2870 else if (ecmd->duplex == DUPLEX_HALF)
2871 setting = SUPPORTED_100baseT_Half;
2872 else
2873 return -EINVAL;
2874 break;
2875
2876 case SPEED_10:
2877 if (ecmd->duplex == DUPLEX_FULL)
2878 setting = SUPPORTED_10baseT_Full;
2879 else if (ecmd->duplex == DUPLEX_HALF)
2880 setting = SUPPORTED_10baseT_Half;
2881 else
2882 return -EINVAL;
2883 break;
2884 default:
2885 return -EINVAL;
2886 }
2887
2888 if ((setting & supported) == 0)
2889 return -EINVAL;
2890
2891 sky2->speed = ecmd->speed;
2892 sky2->duplex = ecmd->duplex;
2893 }
2894
2895 sky2->autoneg = ecmd->autoneg;
2896 sky2->advertising = ecmd->advertising;
2897
1b537565
SH		 2898 if (netif_running(dev))
2899 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2900
2901 return 0;
2902}
2903
2904static void sky2_get_drvinfo(struct net_device *dev,
2905 struct ethtool_drvinfo *info)
2906{
2907 struct sky2_port *sky2 = netdev_priv(dev);
2908
2909 strcpy(info->driver, DRV_NAME);
2910 strcpy(info->version, DRV_VERSION);
2911 strcpy(info->fw_version, "N/A");
2912 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2913}
2914
2915static const struct sky2_stat {
793b883e
SH		 2916 char name[ETH_GSTRING_LEN];
2917 u16 offset;
cd28ab6a
SH		 2918} sky2_stats[] = {
2919 { "tx_bytes", GM_TXO_OK_HI },
2920 { "rx_bytes", GM_RXO_OK_HI },
2921 { "tx_broadcast", GM_TXF_BC_OK },
2922 { "rx_broadcast", GM_RXF_BC_OK },
2923 { "tx_multicast", GM_TXF_MC_OK },
2924 { "rx_multicast", GM_RXF_MC_OK },
2925 { "tx_unicast", GM_TXF_UC_OK },
2926 { "rx_unicast", GM_RXF_UC_OK },
2927 { "tx_mac_pause", GM_TXF_MPAUSE },
2928 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2929 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2930 { "late_collision",GM_TXF_LAT_COL },
2931 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2932 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2933 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2934
d2604540 2935 { "rx_short", GM_RXF_SHT },
cd28ab6a 2936 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2937 { "rx_64_byte_packets", GM_RXF_64B },
2938 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2939 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2940 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2941 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2942 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2943 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2944 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2945 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2946 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2947 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2948
2949 { "tx_64_byte_packets", GM_TXF_64B },
2950 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2951 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2952 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2953 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2954 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2955 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2956 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2957};
2958
cd28ab6a
SH		 2959static u32 sky2_get_rx_csum(struct net_device *dev)
2960{
2961 struct sky2_port *sky2 = netdev_priv(dev);
2962
2963 return sky2->rx_csum;
2964}
2965
2966static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2967{
2968 struct sky2_port *sky2 = netdev_priv(dev);
2969
2970 sky2->rx_csum = data;
793b883e 2971
cd28ab6a
SH		 2972 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2973 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2974
2975 return 0;
2976}
2977
2978static u32 sky2_get_msglevel(struct net_device *netdev)
2979{
2980 struct sky2_port *sky2 = netdev_priv(netdev);
2981 return sky2->msg_enable;
2982}
2983
9a7ae0a9
SH		 2984static int sky2_nway_reset(struct net_device *dev)
2985{
2986 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2987
16ad91e1 2988 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2989 return -EINVAL;
2990
1b537565 2991 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2992
2993 return 0;
2994}
2995
793b883e 2996static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2997{
2998 struct sky2_hw *hw = sky2->hw;
2999 unsigned port = sky2->port;
3000 int i;
3001
3002 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3003 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3004 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3005 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3006
793b883e 3007 for (i = 2; i < count; i++)
cd28ab6a
SH		 3008 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3009}
3010
cd28ab6a
SH		 3011static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3012{
3013 struct sky2_port *sky2 = netdev_priv(netdev);
3014 sky2->msg_enable = value;
3015}
3016
3017static int sky2_get_stats_count(struct net_device *dev)
3018{
3019 return ARRAY_SIZE(sky2_stats);
3020}
3021
3022static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3023 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3024{
3025 struct sky2_port *sky2 = netdev_priv(dev);
3026
793b883e 3027 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3028}
3029
793b883e 3030static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3031{
3032 int i;
3033
3034 switch (stringset) {
3035 case ETH_SS_STATS:
3036 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3037 memcpy(data + i * ETH_GSTRING_LEN,
3038 sky2_stats[i].name, ETH_GSTRING_LEN);
3039 break;
3040 }
3041}
3042
cd28ab6a
SH		 3043static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3044{
3045 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3046 return &sky2->net_stats;
3047}
3048
3049static int sky2_set_mac_address(struct net_device *dev, void *p)
3050{
3051 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3052 struct sky2_hw *hw = sky2->hw;
3053 unsigned port = sky2->port;
3054 const struct sockaddr *addr = p;
cd28ab6a
SH		 3055
3056 if (!is_valid_ether_addr(addr->sa_data))
3057 return -EADDRNOTAVAIL;
3058
cd28ab6a 3059 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3060 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3061 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3062 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3063 dev->dev_addr, ETH_ALEN);
1b537565 3064
a8ab1ec0
SH		 3065 /* virtual address for data */
3066 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3067
3068 /* physical address: used for pause frames */
3069 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3070
3071 return 0;
cd28ab6a
SH		 3072}
3073
a052b52f
SH		 3074static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3075{
3076 u32 bit;
3077
3078 bit = ether_crc(ETH_ALEN, addr) & 63;
3079 filter[bit >> 3] |= 1 << (bit & 7);
3080}
3081
cd28ab6a
SH		 3082static void sky2_set_multicast(struct net_device *dev)
3083{
3084 struct sky2_port *sky2 = netdev_priv(dev);
3085 struct sky2_hw *hw = sky2->hw;
3086 unsigned port = sky2->port;
3087 struct dev_mc_list *list = dev->mc_list;
3088 u16 reg;
3089 u8 filter[8];
a052b52f
SH		 3090 int rx_pause;
3091 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3092
a052b52f 3093 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3094 memset(filter, 0, sizeof(filter));
3095
3096 reg = gma_read16(hw, port, GM_RX_CTRL);
3097 reg |= GM_RXCR_UCF_ENA;
3098
d571b694 3099 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3100 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3101 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3102 memset(filter, 0xff, sizeof(filter));
a052b52f 3103 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3104 reg &= ~GM_RXCR_MCF_ENA;
3105 else {
3106 int i;
3107 reg |= GM_RXCR_MCF_ENA;
3108
a052b52f
SH		 3109 if (rx_pause)
3110 sky2_add_filter(filter, pause_mc_addr);
3111
3112 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3113 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3114 }
3115
cd28ab6a 3116 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3117 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3118 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3119 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3120 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3121 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3122 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3123 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3124
3125 gma_write16(hw, port, GM_RX_CTRL, reg);
3126}
3127
3128/* Can have one global because blinking is controlled by
3129 * ethtool and that is always under RTNL mutex
3130 */
91c86df5 3131static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3132{
793b883e
SH		 3133 u16 pg;
3134
793b883e
SH		 3135 switch (hw->chip_id) {
3136 case CHIP_ID_YUKON_XL:
3137 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3138 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3139 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3140 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3141 PHY_M_LEDC_INIT_CTRL(7) |
3142 PHY_M_LEDC_STA1_CTRL(7) |
3143 PHY_M_LEDC_STA0_CTRL(7))
3144 : 0);
3145
3146 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3147 break;
3148
3149 default:
3150 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3151 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3152 on ? PHY_M_LED_ALL : 0);
793b883e 3153 }
cd28ab6a
SH		 3154}
3155
3156/* blink LED's for finding board */
3157static int sky2_phys_id(struct net_device *dev, u32 data)
3158{
3159 struct sky2_port *sky2 = netdev_priv(dev);
3160 struct sky2_hw *hw = sky2->hw;
3161 unsigned port = sky2->port;
793b883e 3162 u16 ledctrl, ledover = 0;
cd28ab6a 3163 long ms;
91c86df5 3164 int interrupted;
cd28ab6a
SH		 3165 int onoff = 1;
3166
793b883e 3167 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3168 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3169 else
3170 ms = data * 1000;
3171
3172 /* save initial values */
e07b1aa8 3173 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3174 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3175 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3176 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3177 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3178 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3179 } else {
3180 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3181 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3182 }
cd28ab6a 3183
91c86df5
SH		 3184 interrupted = 0;
3185 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3186 sky2_led(hw, port, onoff);
3187 onoff = !onoff;
3188
e07b1aa8 3189 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3190 interrupted = msleep_interruptible(250);
e07b1aa8 3191 spin_lock_bh(&sky2->phy_lock);
91c86df5 3192
cd28ab6a
SH		 3193 ms -= 250;
3194 }
3195
3196 /* resume regularly scheduled programming */
793b883e
SH		 3197 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3198 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3199 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3200 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3201 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3202 } else {
3203 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3204 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3205 }
e07b1aa8 3206 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3207
3208 return 0;
3209}
3210
3211static void sky2_get_pauseparam(struct net_device *dev,
3212 struct ethtool_pauseparam *ecmd)
3213{
3214 struct sky2_port *sky2 = netdev_priv(dev);
3215
16ad91e1
SH		 3216 switch (sky2->flow_mode) {
3217 case FC_NONE:
3218 ecmd->tx_pause = ecmd->rx_pause = 0;
3219 break;
3220 case FC_TX:
3221 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3222 break;
3223 case FC_RX:
3224 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3225 break;
3226 case FC_BOTH:
3227 ecmd->tx_pause = ecmd->rx_pause = 1;
3228 }
3229
cd28ab6a
SH		 3230 ecmd->autoneg = sky2->autoneg;
3231}
3232
3233static int sky2_set_pauseparam(struct net_device *dev,
3234 struct ethtool_pauseparam *ecmd)
3235{
3236 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3237
3238 sky2->autoneg = ecmd->autoneg;
16ad91e1 3239 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3240
16ad91e1
SH		 3241 if (netif_running(dev))
3242 sky2_phy_reinit(sky2);
cd28ab6a 3243
2eaba1a2 3244 return 0;
cd28ab6a
SH		 3245}
3246
fb17358f
SH		 3247static int sky2_get_coalesce(struct net_device *dev,
3248 struct ethtool_coalesce *ecmd)
3249{
3250 struct sky2_port *sky2 = netdev_priv(dev);
3251 struct sky2_hw *hw = sky2->hw;
3252
3253 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3254 ecmd->tx_coalesce_usecs = 0;
3255 else {
3256 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3257 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3258 }
3259 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3260
3261 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3262 ecmd->rx_coalesce_usecs = 0;
3263 else {
3264 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3265 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3266 }
3267 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3268
3269 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3270 ecmd->rx_coalesce_usecs_irq = 0;
3271 else {
3272 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3273 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3274 }
3275
3276 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3277
3278 return 0;
3279}
3280
3281/* Note: this affect both ports */
3282static int sky2_set_coalesce(struct net_device *dev,
3283 struct ethtool_coalesce *ecmd)
3284{
3285 struct sky2_port *sky2 = netdev_priv(dev);
3286 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3287 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3288
77b3d6a2
SH		 3289 if (ecmd->tx_coalesce_usecs > tmax ||
3290 ecmd->rx_coalesce_usecs > tmax ||
3291 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3292 return -EINVAL;
3293
ff81fbbe 3294 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3295 return -EINVAL;
ff81fbbe 3296 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3297 return -EINVAL;
ff81fbbe 3298 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3299 return -EINVAL;
3300
3301 if (ecmd->tx_coalesce_usecs == 0)
3302 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3303 else {
3304 sky2_write32(hw, STAT_TX_TIMER_INI,
3305 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3306 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3307 }
3308 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3309
3310 if (ecmd->rx_coalesce_usecs == 0)
3311 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3312 else {
3313 sky2_write32(hw, STAT_LEV_TIMER_INI,
3314 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3315 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3316 }
3317 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3318
3319 if (ecmd->rx_coalesce_usecs_irq == 0)
3320 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3321 else {
d28d4870 3322 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3323 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3324 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3325 }
3326 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3327 return 0;
3328}
3329
793b883e
SH		 3330static void sky2_get_ringparam(struct net_device *dev,
3331 struct ethtool_ringparam *ering)
3332{
3333 struct sky2_port *sky2 = netdev_priv(dev);
3334
3335 ering->rx_max_pending = RX_MAX_PENDING;
3336 ering->rx_mini_max_pending = 0;
3337 ering->rx_jumbo_max_pending = 0;
3338 ering->tx_max_pending = TX_RING_SIZE - 1;
3339
3340 ering->rx_pending = sky2->rx_pending;
3341 ering->rx_mini_pending = 0;
3342 ering->rx_jumbo_pending = 0;
3343 ering->tx_pending = sky2->tx_pending;
3344}
3345
3346static int sky2_set_ringparam(struct net_device *dev,
3347 struct ethtool_ringparam *ering)
3348{
3349 struct sky2_port *sky2 = netdev_priv(dev);
3350 int err = 0;
3351
3352 if (ering->rx_pending > RX_MAX_PENDING ||
3353 ering->rx_pending < 8 ||
3354 ering->tx_pending < MAX_SKB_TX_LE ||
3355 ering->tx_pending > TX_RING_SIZE - 1)
3356 return -EINVAL;
3357
3358 if (netif_running(dev))
3359 sky2_down(dev);
3360
3361 sky2->rx_pending = ering->rx_pending;
3362 sky2->tx_pending = ering->tx_pending;
3363
1b537565 3364 if (netif_running(dev)) {
793b883e 3365 err = sky2_up(dev);
1b537565
SH		 3366 if (err)
3367 dev_close(dev);
6ed995bb
SH		 3368 else
3369 sky2_set_multicast(dev);
1b537565 3370 }
793b883e
SH		 3371
3372 return err;
3373}
3374
793b883e
SH		 3375static int sky2_get_regs_len(struct net_device *dev)
3376{
6e4cbb34 3377 return 0x4000;
793b883e
SH		 3378}
3379
3380/*
3381 * Returns copy of control register region
3ead5db7 3382 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3383 */
3384static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3385 void *p)
3386{
3387 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3388 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3389
3390 regs->version = 1;
6e4cbb34 3391 memset(p, 0, regs->len);
793b883e 3392
6e4cbb34
SH		 3393 memcpy_fromio(p, io, B3_RAM_ADDR);
3394
3ead5db7
SH		 3395 /* skip diagnostic ram region */
3396 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3397
3398 /* copy GMAC registers */
3399 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3400 if (sky2->hw->ports > 1)
3401 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3402
793b883e 3403}
cd28ab6a 3404
b628ed98
SH		 3405/* In order to do Jumbo packets on these chips, need to turn off the
3406 * transmit store/forward. Therefore checksum offload won't work.
3407 */
3408static int no_tx_offload(struct net_device *dev)
3409{
3410 const struct sky2_port *sky2 = netdev_priv(dev);
3411 const struct sky2_hw *hw = sky2->hw;
3412
69161611 3413 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3414}
3415
3416static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3417{
3418 if (data && no_tx_offload(dev))
3419 return -EINVAL;
3420
3421 return ethtool_op_set_tx_csum(dev, data);
3422}
3423
3424
3425static int sky2_set_tso(struct net_device *dev, u32 data)
3426{
3427 if (data && no_tx_offload(dev))
3428 return -EINVAL;
3429
3430 return ethtool_op_set_tso(dev, data);
3431}
3432
f4331a6d
SH		 3433static int sky2_get_eeprom_len(struct net_device *dev)
3434{
3435 struct sky2_port *sky2 = netdev_priv(dev);
3436 u16 reg2;
3437
3438 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3439 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3440}
3441
3442static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3443{
3444 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3445
3446 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3447 cpu_relax();
3448 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3449}
3450
3451static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3452{
3453 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3454 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3455 do {
3456 cpu_relax();
3457 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3458}
3459
3460static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3461 u8 *data)
3462{
3463 struct sky2_port *sky2 = netdev_priv(dev);
3464 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3465 int length = eeprom->len;
3466 u16 offset = eeprom->offset;
3467
3468 if (!cap)
3469 return -EINVAL;
3470
3471 eeprom->magic = SKY2_EEPROM_MAGIC;
3472
3473 while (length > 0) {
3474 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3475 int n = min_t(int, length, sizeof(val));
3476
3477 memcpy(data, &val, n);
3478 length -= n;
3479 data += n;
3480 offset += n;
3481 }
3482 return 0;
3483}
3484
3485static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3486 u8 *data)
3487{
3488 struct sky2_port *sky2 = netdev_priv(dev);
3489 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3490 int length = eeprom->len;
3491 u16 offset = eeprom->offset;
3492
3493 if (!cap)
3494 return -EINVAL;
3495
3496 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3497 return -EINVAL;
3498
3499 while (length > 0) {
3500 u32 val;
3501 int n = min_t(int, length, sizeof(val));
3502
3503 if (n < sizeof(val))
3504 val = sky2_vpd_read(sky2->hw, cap, offset);
3505 memcpy(&val, data, n);
3506
3507 sky2_vpd_write(sky2->hw, cap, offset, val);
3508
3509 length -= n;
3510 data += n;
3511 offset += n;
3512 }
3513 return 0;
3514}
3515
3516
7282d491 3517static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3518 .get_settings = sky2_get_settings,
3519 .set_settings = sky2_set_settings,
3520 .get_drvinfo = sky2_get_drvinfo,
3521 .get_wol = sky2_get_wol,
3522 .set_wol = sky2_set_wol,
3523 .get_msglevel = sky2_get_msglevel,
3524 .set_msglevel = sky2_set_msglevel,
3525 .nway_reset = sky2_nway_reset,
3526 .get_regs_len = sky2_get_regs_len,
3527 .get_regs = sky2_get_regs,
3528 .get_link = ethtool_op_get_link,
3529 .get_eeprom_len = sky2_get_eeprom_len,
3530 .get_eeprom = sky2_get_eeprom,
3531 .set_eeprom = sky2_set_eeprom,
3532 .get_sg = ethtool_op_get_sg,
3533 .set_sg = ethtool_op_set_sg,
3534 .get_tx_csum = ethtool_op_get_tx_csum,
3535 .set_tx_csum = sky2_set_tx_csum,
3536 .get_tso = ethtool_op_get_tso,
3537 .set_tso = sky2_set_tso,
3538 .get_rx_csum = sky2_get_rx_csum,
3539 .set_rx_csum = sky2_set_rx_csum,
3540 .get_strings = sky2_get_strings,
3541 .get_coalesce = sky2_get_coalesce,
3542 .set_coalesce = sky2_set_coalesce,
3543 .get_ringparam = sky2_get_ringparam,
3544 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3545 .get_pauseparam = sky2_get_pauseparam,
3546 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3547 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3548 .get_stats_count = sky2_get_stats_count,
3549 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3550 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3551};
3552
3cf26753
SH		 3553#ifdef CONFIG_SKY2_DEBUG
3554
3555static struct dentry *sky2_debug;
3556
3557static int sky2_debug_show(struct seq_file *seq, void *v)
3558{
3559 struct net_device *dev = seq->private;
3560 const struct sky2_port *sky2 = netdev_priv(dev);
3561 const struct sky2_hw *hw = sky2->hw;
3562 unsigned port = sky2->port;
3563 unsigned idx, last;
3564 int sop;
3565
3566 if (!netif_running(dev))
3567 return -ENETDOWN;
3568
3569 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3570 sky2_read32(hw, B0_ISRC),
3571 sky2_read32(hw, B0_IMSK),
3572 sky2_read32(hw, B0_Y2_SP_ICR));
3573
3574 netif_poll_disable(hw->dev[0]);
3575 last = sky2_read16(hw, STAT_PUT_IDX);
3576
3577 if (hw->st_idx == last)
3578 seq_puts(seq, "Status ring (empty)\n");
3579 else {
3580 seq_puts(seq, "Status ring\n");
3581 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3582 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3583 const struct sky2_status_le *le = hw->st_le + idx;
3584 seq_printf(seq, "[%d] %#x %d %#x\n",
3585 idx, le->opcode, le->length, le->status);
3586 }
3587 seq_puts(seq, "\n");
3588 }
3589
3590 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3591 sky2->tx_cons, sky2->tx_prod,
3592 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3593 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3594
3595 /* Dump contents of tx ring */
3596 sop = 1;
3597 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3598 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3599 const struct sky2_tx_le *le = sky2->tx_le + idx;
3600 u32 a = le32_to_cpu(le->addr);
3601
3602 if (sop)
3603 seq_printf(seq, "%u:", idx);
3604 sop = 0;
3605
3606 switch(le->opcode & ~HW_OWNER) {
3607 case OP_ADDR64:
3608 seq_printf(seq, " %#x:", a);
3609 break;
3610 case OP_LRGLEN:
3611 seq_printf(seq, " mtu=%d", a);
3612 break;
3613 case OP_VLAN:
3614 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3615 break;
3616 case OP_TCPLISW:
3617 seq_printf(seq, " csum=%#x", a);
3618 break;
3619 case OP_LARGESEND:
3620 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3621 break;
3622 case OP_PACKET:
3623 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3624 break;
3625 case OP_BUFFER:
3626 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3627 break;
3628 default:
3629 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3630 a, le16_to_cpu(le->length));
3631 }
3632
3633 if (le->ctrl & EOP) {
3634 seq_putc(seq, '\n');
3635 sop = 1;
3636 }
3637 }
3638
3639 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3640 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3641 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3642 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3643
3644 netif_poll_enable(hw->dev[0]);
3645 return 0;
3646}
3647
3648static int sky2_debug_open(struct inode *inode, struct file *file)
3649{
3650 return single_open(file, sky2_debug_show, inode->i_private);
3651}
3652
3653static const struct file_operations sky2_debug_fops = {
3654 .owner = THIS_MODULE,
3655 .open = sky2_debug_open,
3656 .read = seq_read,
3657 .llseek = seq_lseek,
3658 .release = single_release,
3659};
3660
3661/*
3662 * Use network device events to create/remove/rename
3663 * debugfs file entries
3664 */
3665static int sky2_device_event(struct notifier_block *unused,
3666 unsigned long event, void *ptr)
3667{
3668 struct net_device *dev = ptr;
3669
3670 if (dev->open == sky2_up) {
3671 struct sky2_port *sky2 = netdev_priv(dev);
3672
3673 switch(event) {
3674 case NETDEV_CHANGENAME:
3675 if (!netif_running(dev))
3676 break;
3677 /* fallthrough */
3678 case NETDEV_DOWN:
3679 case NETDEV_GOING_DOWN:
3680 if (sky2->debugfs) {
3681 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3682 dev->name);
3683 debugfs_remove(sky2->debugfs);
3684 sky2->debugfs = NULL;
3685 }
3686
3687 if (event != NETDEV_CHANGENAME)
3688 break;
3689 /* fallthrough for changename */
3690 case NETDEV_UP:
3691 if (sky2_debug) {
3692 struct dentry *d;
3693 d = debugfs_create_file(dev->name, S_IRUGO,
3694 sky2_debug, dev,
3695 &sky2_debug_fops);
3696 if (d == NULL || IS_ERR(d))
3697 printk(KERN_INFO PFX
3698 "%s: debugfs create failed\n",
3699 dev->name);
3700 else
3701 sky2->debugfs = d;
3702 }
3703 break;
3704 }
3705 }
3706
3707 return NOTIFY_DONE;
3708}
3709
3710static struct notifier_block sky2_notifier = {
3711 .notifier_call = sky2_device_event,
3712};
3713
3714
3715static __init void sky2_debug_init(void)
3716{
3717 struct dentry *ent;
3718
3719 ent = debugfs_create_dir("sky2", NULL);
3720 if (!ent || IS_ERR(ent))
3721 return;
3722
3723 sky2_debug = ent;
3724 register_netdevice_notifier(&sky2_notifier);
3725}
3726
3727static __exit void sky2_debug_cleanup(void)
3728{
3729 if (sky2_debug) {
3730 unregister_netdevice_notifier(&sky2_notifier);
3731 debugfs_remove(sky2_debug);
3732 sky2_debug = NULL;
3733 }
3734}
3735
3736#else
3737#define sky2_debug_init()
3738#define sky2_debug_cleanup()
3739#endif
3740
3741
cd28ab6a
SH		 3742/* Initialize network device */
3743static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3744 unsigned port,
3745 int highmem, int wol)
cd28ab6a
SH		 3746{
3747 struct sky2_port *sky2;
3748 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3749
3750 if (!dev) {
b02a9258 3751 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3752 return NULL;
3753 }
3754
3755 SET_MODULE_OWNER(dev);
3756 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3757 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3758 dev->open = sky2_up;
3759 dev->stop = sky2_down;
ef743d33 3760 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3761 dev->hard_start_xmit = sky2_xmit_frame;
3762 dev->get_stats = sky2_get_stats;
3763 dev->set_multicast_list = sky2_set_multicast;
3764 dev->set_mac_address = sky2_set_mac_address;
3765 dev->change_mtu = sky2_change_mtu;
3766 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3767 dev->tx_timeout = sky2_tx_timeout;
3768 dev->watchdog_timeo = TX_WATCHDOG;
3769 if (port == 0)
3770 dev->poll = sky2_poll;
3771 dev->weight = NAPI_WEIGHT;
3772#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3773 /* Network console (only works on port 0)
3774 * because netpoll makes assumptions about NAPI
3775 */
3776 if (port == 0)
3777 dev->poll_controller = sky2_netpoll;
cd28ab6a 3778#endif
cd28ab6a
SH		 3779
3780 sky2 = netdev_priv(dev);
3781 sky2->netdev = dev;
3782 sky2->hw = hw;
3783 sky2->msg_enable = netif_msg_init(debug, default_msg);
3784
cd28ab6a
SH		 3785 /* Auto speed and flow control */
3786 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3787 sky2->flow_mode = FC_BOTH;
3788
cd28ab6a
SH		 3789 sky2->duplex = -1;
3790 sky2->speed = -1;
3791 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3792 sky2->rx_csum = 1;
e3173832 3793 sky2->wol = wol;
75d070c5 3794
e07b1aa8 3795 spin_lock_init(&sky2->phy_lock);
793b883e 3796 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3797 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3798
3799 hw->dev[port] = dev;
3800
3801 sky2->port = port;
3802
4a50a876 3803 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3804 if (highmem)
3805 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3806
d1f13708 3807#ifdef SKY2_VLAN_TAG_USED
3808 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3809 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708 3810#endif
3811
cd28ab6a 3812 /* read the mac address */
793b883e 3813 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3814 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3815
cd28ab6a
SH		 3816 return dev;
3817}
3818
28bd181a 3819static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3820{
3821 const struct sky2_port *sky2 = netdev_priv(dev);
3822
3823 if (netif_msg_probe(sky2))
3824 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3825 dev->name,
3826 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3827 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3828}
3829
fb2690a9 3830/* Handle software interrupt used during MSI test */
7d12e780 3831static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3832{
3833 struct sky2_hw *hw = dev_id;
3834 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3835
3836 if (status == 0)
3837 return IRQ_NONE;
3838
3839 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3840 hw->msi = 1;
fb2690a9
SH		 3841 wake_up(&hw->msi_wait);
3842 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3843 }
3844 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3845
3846 return IRQ_HANDLED;
3847}
3848
3849/* Test interrupt path by forcing a a software IRQ */
3850static int __devinit sky2_test_msi(struct sky2_hw *hw)
3851{
3852 struct pci_dev *pdev = hw->pdev;
3853 int err;
3854
bb507fe1 3855 init_waitqueue_head (&hw->msi_wait);
3856
fb2690a9
SH		 3857 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3858
b0a20ded 3859 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3860 if (err) {
b02a9258 3861 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3862 return err;
3863 }
3864
fb2690a9 3865 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3866 sky2_read8(hw, B0_CTST);
fb2690a9 3867
b0a20ded 3868 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3869
b0a20ded 3870 if (!hw->msi) {
fb2690a9 3871 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3872 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3873 "switching to INTx mode.\n");
fb2690a9
SH		 3874
3875 err = -EOPNOTSUPP;
3876 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3877 }
3878
3879 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3880 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3881
3882 free_irq(pdev->irq, hw);
3883
3884 return err;
3885}
3886
e3173832
SH		 3887static int __devinit pci_wake_enabled(struct pci_dev *dev)
3888{
3889 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3890 u16 value;
3891
3892 if (!pm)
3893 return 0;
3894 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3895 return 0;
3896 return value & PCI_PM_CTRL_PME_ENABLE;
3897}
3898
cd28ab6a
SH		 3899static int __devinit sky2_probe(struct pci_dev *pdev,
3900 const struct pci_device_id *ent)
3901{
7f60c64b 3902 struct net_device *dev;
cd28ab6a 3903 struct sky2_hw *hw;
e3173832 3904 int err, using_dac = 0, wol_default;
cd28ab6a 3905
793b883e
SH		 3906 err = pci_enable_device(pdev);
3907 if (err) {
b02a9258 3908 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3909 goto err_out;
3910 }
3911
793b883e
SH		 3912 err = pci_request_regions(pdev, DRV_NAME);
3913 if (err) {
b02a9258 3914 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3915 goto err_out_disable;
cd28ab6a
SH		 3916 }
3917
3918 pci_set_master(pdev);
3919
d1f3d4dd
SH		 3920 if (sizeof(dma_addr_t) > sizeof(u32) &&
3921 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3922 using_dac = 1;
3923 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3924 if (err < 0) {
b02a9258
SH		 3925 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3926 "for consistent allocations\n");
d1f3d4dd
SH		 3927 goto err_out_free_regions;
3928 }
d1f3d4dd 3929 } else {
cd28ab6a
SH		 3930 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3931 if (err) {
b02a9258 3932 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3933 goto err_out_free_regions;
3934 }
3935 }
d1f3d4dd 3936
e3173832
SH		 3937 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3938
cd28ab6a 3939 err = -ENOMEM;
6aad85d6 3940 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3941 if (!hw) {
b02a9258 3942 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3943 goto err_out_free_regions;
3944 }
3945
cd28ab6a 3946 hw->pdev = pdev;
cd28ab6a
SH		 3947
3948 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3949 if (!hw->regs) {
b02a9258 3950 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3951 goto err_out_free_hw;
3952 }
3953
56a645cc 3954#ifdef __BIG_ENDIAN
f65b138c
SH		 3955 /* The sk98lin vendor driver uses hardware byte swapping but
3956 * this driver uses software swapping.
3957 */
56a645cc
SH		 3958 {
3959 u32 reg;
56a645cc 3960 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3961 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3962 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3963 }
3964#endif
3965
08c06d8a
SH		 3966 /* ring for status responses */
3967 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3968 &hw->st_dma);
3969 if (!hw->st_le)
3970 goto err_out_iounmap;
3971
e3173832 3972 err = sky2_init(hw);
cd28ab6a 3973 if (err)
793b883e 3974 goto err_out_iounmap;
cd28ab6a 3975
b02a9258 3976 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3977 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3978 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3979 hw->chip_id, hw->chip_rev);
cd28ab6a 3980
e3173832
SH		 3981 sky2_reset(hw);
3982
3983 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3984 if (!dev) {
3985 err = -ENOMEM;
cd28ab6a 3986 goto err_out_free_pci;
7f60c64b 3987 }
cd28ab6a 3988
9fa1b1f3
SH		 3989 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3990 err = sky2_test_msi(hw);
3991 if (err == -EOPNOTSUPP)
3992 pci_disable_msi(pdev);
3993 else if (err)
3994 goto err_out_free_netdev;
3995 }
3996
793b883e
SH		 3997 err = register_netdev(dev);
3998 if (err) {
b02a9258 3999 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4000 goto err_out_free_netdev;
4001 }
4002
b0a20ded
SH		 4003 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
4004 dev->name, hw);
9fa1b1f3 4005 if (err) {
b02a9258 4006 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4007 goto err_out_unregister;
4008 }
4009 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4010
cd28ab6a
SH		 4011 sky2_show_addr(dev);
4012
7f60c64b 4013 if (hw->ports > 1) {
4014 struct net_device *dev1;
4015
e3173832 4016 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4017 if (!dev1)
4018 dev_warn(&pdev->dev, "allocation for second device failed\n");
4019 else if ((err = register_netdev(dev1))) {
4020 dev_warn(&pdev->dev,
4021 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4022 hw->dev[1] = NULL;
4023 free_netdev(dev1);
b02a9258
SH		 4024 } else
4025 sky2_show_addr(dev1);
cd28ab6a
SH		 4026 }
4027
01bd7564 4028 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 4029 INIT_WORK(&hw->restart_work, sky2_restart);
4030
eb35cf60 4031 sky2_idle_start(hw);
d27ed387 4032
793b883e
SH		 4033 pci_set_drvdata(pdev, hw);
4034
cd28ab6a
SH		 4035 return 0;
4036
793b883e 4037err_out_unregister:
b0a20ded
SH		 4038 if (hw->msi)
4039 pci_disable_msi(pdev);
793b883e 4040 unregister_netdev(dev);
cd28ab6a
SH		 4041err_out_free_netdev:
4042 free_netdev(dev);
cd28ab6a 4043err_out_free_pci:
793b883e 4044 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4045 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4046err_out_iounmap:
4047 iounmap(hw->regs);
4048err_out_free_hw:
4049 kfree(hw);
4050err_out_free_regions:
4051 pci_release_regions(pdev);
44a1d2e5 4052err_out_disable:
cd28ab6a 4053 pci_disable_device(pdev);
cd28ab6a 4054err_out:
549a68c3 4055 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4056 return err;
4057}
4058
4059static void __devexit sky2_remove(struct pci_dev *pdev)
4060{
793b883e 4061 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 4062 struct net_device *dev0, *dev1;
4063
793b883e 4064 if (!hw)
cd28ab6a
SH		 4065 return;
4066
d27ed387
SH		 4067 del_timer_sync(&hw->idle_timer);
4068
81906791
SH		 4069 flush_scheduled_work();
4070
d27ed387 4071 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 4072 synchronize_irq(hw->pdev->irq);
4073
cd28ab6a 4074 dev0 = hw->dev[0];
793b883e
SH		 4075 dev1 = hw->dev[1];
4076 if (dev1)
4077 unregister_netdev(dev1);
cd28ab6a
SH		 4078 unregister_netdev(dev0);
4079
ae306cca
SH		 4080 sky2_power_aux(hw);
4081
cd28ab6a 4082 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4083 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4084 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4085
4086 free_irq(pdev->irq, hw);
b0a20ded
SH		 4087 if (hw->msi)
4088 pci_disable_msi(pdev);
793b883e 4089 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4090 pci_release_regions(pdev);
4091 pci_disable_device(pdev);
793b883e 4092
cd28ab6a
SH		 4093 if (dev1)
4094 free_netdev(dev1);
4095 free_netdev(dev0);
4096 iounmap(hw->regs);
4097 kfree(hw);
5afa0a9c 4098
cd28ab6a
SH		 4099 pci_set_drvdata(pdev, NULL);
4100}
4101
4102#ifdef CONFIG_PM
4103static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4104{
793b883e 4105 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4106 int i, wol = 0;
cd28ab6a 4107
549a68c3
SH		 4108 if (!hw)
4109 return 0;
4110
eb35cf60 4111 del_timer_sync(&hw->idle_timer);
6a5706b9 4112 netif_poll_disable(hw->dev[0]);
eb35cf60 4113
f05267e7 4114 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4115 struct net_device *dev = hw->dev[i];
e3173832 4116 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4117
e3173832 4118 if (netif_running(dev))
5afa0a9c 4119 sky2_down(dev);
e3173832
SH		 4120
4121 if (sky2->wol)
4122 sky2_wol_init(sky2);
4123
4124 wol |= sky2->wol;
cd28ab6a
SH		 4125 }
4126
8ab8fca2 4127 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4128 sky2_power_aux(hw);
e3173832 4129
d374c1c1 4130 pci_save_state(pdev);
e3173832 4131 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4132 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4133
2ccc99b7 4134 return 0;
cd28ab6a
SH		 4135}
4136
4137static int sky2_resume(struct pci_dev *pdev)
4138{
793b883e 4139 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4140 int i, err;
cd28ab6a 4141
549a68c3
SH		 4142 if (!hw)
4143 return 0;
4144
ae306cca
SH		 4145 err = pci_set_power_state(pdev, PCI_D0);
4146 if (err)
4147 goto out;
4148
4149 err = pci_restore_state(pdev);
4150 if (err)
4151 goto out;
4152
cd28ab6a 4153 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4154
4155 /* Re-enable all clocks */
4156 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
4157 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4158
e3173832 4159 sky2_reset(hw);
cd28ab6a 4160
8ab8fca2
SH		 4161 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4162
f05267e7 4163 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4164 struct net_device *dev = hw->dev[i];
6a5706b9 4165 if (netif_running(dev)) {
08c06d8a
SH		 4166 err = sky2_up(dev);
4167 if (err) {
4168 printk(KERN_ERR PFX "%s: could not up: %d\n",
4169 dev->name, err);
4170 dev_close(dev);
eb35cf60 4171 goto out;
5afa0a9c 4172 }
cd28ab6a
SH		 4173 }
4174 }
eb35cf60 4175
6a5706b9 4176 netif_poll_enable(hw->dev[0]);
eb35cf60 4177 sky2_idle_start(hw);
ae306cca 4178 return 0;
08c06d8a 4179out:
b02a9258 4180 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4181 pci_disable_device(pdev);
08c06d8a 4182 return err;
cd28ab6a
SH		 4183}
4184#endif
4185
e3173832
SH		 4186static void sky2_shutdown(struct pci_dev *pdev)
4187{
4188 struct sky2_hw *hw = pci_get_drvdata(pdev);
4189 int i, wol = 0;
4190
549a68c3
SH		 4191 if (!hw)
4192 return;
4193
e3173832
SH		 4194 del_timer_sync(&hw->idle_timer);
4195 netif_poll_disable(hw->dev[0]);
4196
4197 for (i = 0; i < hw->ports; i++) {
4198 struct net_device *dev = hw->dev[i];
4199 struct sky2_port *sky2 = netdev_priv(dev);
4200
4201 if (sky2->wol) {
4202 wol = 1;
4203 sky2_wol_init(sky2);
4204 }
4205 }
4206
4207 if (wol)
4208 sky2_power_aux(hw);
4209
4210 pci_enable_wake(pdev, PCI_D3hot, wol);
4211 pci_enable_wake(pdev, PCI_D3cold, wol);
4212
4213 pci_disable_device(pdev);
4214 pci_set_power_state(pdev, PCI_D3hot);
4215
4216}
4217
cd28ab6a 4218static struct pci_driver sky2_driver = {
793b883e
SH		 4219 .name = DRV_NAME,
4220 .id_table = sky2_id_table,
4221 .probe = sky2_probe,
4222 .remove = __devexit_p(sky2_remove),
cd28ab6a 4223#ifdef CONFIG_PM
793b883e
SH		 4224 .suspend = sky2_suspend,
4225 .resume = sky2_resume,
cd28ab6a 4226#endif
e3173832 4227 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4228};
4229
4230static int __init sky2_init_module(void)
4231{
3cf26753 4232 sky2_debug_init();
50241c4c 4233 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4234}
4235
4236static void __exit sky2_cleanup_module(void)
4237{
4238 pci_unregister_driver(&sky2_driver);
3cf26753 4239 sky2_debug_cleanup();
cd28ab6a
SH		 4240}
4241
4242module_init(sky2_init_module);
4243module_exit(sky2_cleanup_module);
4244
4245MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4246MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4247MODULE_LICENSE("GPL");
5f4f9dc1 4248MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)