projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sky2: edge triggered workaround enhancement
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
cd28ab6a 26#include <linux/config.h>
793b883e 27#include <linux/crc32.h>
cd28ab6a
SH		 28#include <linux/kernel.h>
29#include <linux/version.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
d0bbccfa 32#include <linux/dma-mapping.h>
cd28ab6a
SH		 33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
bdf9c27d 54#define DRV_VERSION "1.2"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
13210ce5 64#define RX_LE_SIZE 512
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 66#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 68#define RX_SKB_ALIGN 8
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
bdb5c58e
SH		 93static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
01bd7564
SH		 101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
cd28ab6a
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 123 { 0 }
124};
793b883e 125
cd28ab6a
SH		 126MODULE_DEVICE_TABLE(pci, sky2_id_table);
127
128/* Avoid conditionals by using array */
129static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
131
92f965e8
SH		 132/* This driver supports yukon2 chipset only */
133static const char *yukon2_name[] = {
134 "XL", /* 0xb3 */
135 "EC Ultra", /* 0xb4 */
136 "UNKNOWN", /* 0xb5 */
137 "EC", /* 0xb6 */
138 "FE", /* 0xb7 */
793b883e
SH		 139};
140
793b883e 141/* Access to external PHY */
ef743d33 142static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 143{
144 int i;
145
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
149
150 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 152 return 0;
793b883e 153 udelay(1);
cd28ab6a 154 }
ef743d33 155
793b883e 156 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 157 return -ETIMEDOUT;
cd28ab6a
SH		 158}
159
ef743d33 160static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 161{
162 int i;
163
793b883e 164 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 165 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
166
167 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 168 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
169 *val = gma_read16(hw, port, GM_SMI_DATA);
170 return 0;
171 }
172
793b883e 173 udelay(1);
cd28ab6a
SH		 174 }
175
ef743d33 176 return -ETIMEDOUT;
177}
178
179static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
180{
181 u16 v;
182
183 if (__gm_phy_read(hw, port, reg, &v) != 0)
184 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
185 return v;
cd28ab6a
SH		 186}
187
5afa0a9c 188static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
189{
190 u16 power_control;
191 u32 reg1;
192 int vaux;
193 int ret = 0;
194
195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
197
56a645cc 198 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 199 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c 200 (power_control & PCI_PM_CAP_PME_D3cold);
201
56a645cc 202 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c 203
204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
206
207 switch (state) {
208 case PCI_D0:
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 else
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224
225 /* Turn off phy power saving */
56a645cc 226 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c 227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
228
d571b694 229 /* looks like this XL is back asswards .. */
5afa0a9c 230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
231 reg1 |= PCI_Y2_PHY1_COMA;
232 if (hw->ports > 1)
233 reg1 |= PCI_Y2_PHY2_COMA;
234 }
977bdf06
SH		 235
236 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
56a645cc
SH		 237 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
238 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 239 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 240 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
241 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 242 }
243
56a645cc 244 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
977bdf06 245
5afa0a9c 246 break;
247
248 case PCI_D3hot:
249 case PCI_D3cold:
250 /* Turn on phy power saving */
56a645cc 251 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c 252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
254 else
255 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
56a645cc 256 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
5afa0a9c 257
258 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
259 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
260 else
261 /* enable bits are inverted */
262 sky2_write8(hw, B2_Y2_CLK_GATE,
263 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
264 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
265 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
266
267 /* switch power to VAUX */
268 if (vaux && state != PCI_D3cold)
269 sky2_write8(hw, B0_POWER_CTRL,
270 (PC_VAUX_ENA | PC_VCC_ENA |
271 PC_VAUX_ON | PC_VCC_OFF));
272 break;
273 default:
274 printk(KERN_ERR PFX "Unknown power state %d\n", state);
275 ret = -1;
276 }
277
56a645cc 278 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 279 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
280 return ret;
281}
282
cd28ab6a
SH		 283static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
284{
285 u16 reg;
286
287 /* disable all GMAC IRQ's */
288 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
289 /* disable PHY IRQs */
290 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 291
cd28ab6a
SH		 292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300}
301
302static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
303{
304 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 305 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 306
793b883e 307 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 308 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
309
310 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 311 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 312 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
313
314 if (hw->chip_id == CHIP_ID_YUKON_EC)
315 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
316 else
317 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
318
319 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
320 }
321
322 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
323 if (hw->copper) {
324 if (hw->chip_id == CHIP_ID_YUKON_FE) {
325 /* enable automatic crossover */
326 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
327 } else {
328 /* disable energy detect */
329 ctrl &= ~PHY_M_PC_EN_DET_MSK;
330
331 /* enable automatic crossover */
332 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
333
334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 hw->chip_id == CHIP_ID_YUKON_XL) {
336 ctrl &= ~PHY_M_PC_DSC_MSK;
337 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
338 }
339 }
340 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
341 } else {
342 /* workaround for deviation #4.88 (CRC errors) */
343 /* disable Automatic Crossover */
344
345 ctrl &= ~PHY_M_PC_MDIX_MSK;
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347
348 if (hw->chip_id == CHIP_ID_YUKON_XL) {
349 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl &= ~PHY_M_MAC_MD_MSK;
353 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
354 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
355
356 /* select page 1 to access Fiber registers */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
358 }
cd28ab6a
SH		 359 }
360
361 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
362 if (sky2->autoneg == AUTONEG_DISABLE)
363 ctrl &= ~PHY_CT_ANE;
364 else
365 ctrl |= PHY_CT_ANE;
366
367 ctrl |= PHY_CT_RESET;
368 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
369
370 ctrl = 0;
371 ct1000 = 0;
372 adv = PHY_AN_CSMA;
373
374 if (sky2->autoneg == AUTONEG_ENABLE) {
375 if (hw->copper) {
376 if (sky2->advertising & ADVERTISED_1000baseT_Full)
377 ct1000 |= PHY_M_1000C_AFD;
378 if (sky2->advertising & ADVERTISED_1000baseT_Half)
379 ct1000 |= PHY_M_1000C_AHD;
380 if (sky2->advertising & ADVERTISED_100baseT_Full)
381 adv |= PHY_M_AN_100_FD;
382 if (sky2->advertising & ADVERTISED_100baseT_Half)
383 adv |= PHY_M_AN_100_HD;
384 if (sky2->advertising & ADVERTISED_10baseT_Full)
385 adv |= PHY_M_AN_10_FD;
386 if (sky2->advertising & ADVERTISED_10baseT_Half)
387 adv |= PHY_M_AN_10_HD;
793b883e 388 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 389 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
390
391 /* Set Flow-control capabilities */
392 if (sky2->tx_pause && sky2->rx_pause)
793b883e 393 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 394 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 395 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 396 else if (!sky2->rx_pause && sky2->tx_pause)
397 adv |= PHY_AN_PAUSE_ASYM; /* local */
398
399 /* Restart Auto-negotiation */
400 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
401 } else {
402 /* forced speed/duplex settings */
403 ct1000 = PHY_M_1000C_MSE;
404
405 if (sky2->duplex == DUPLEX_FULL)
406 ctrl |= PHY_CT_DUP_MD;
407
408 switch (sky2->speed) {
409 case SPEED_1000:
410 ctrl |= PHY_CT_SP1000;
411 break;
412 case SPEED_100:
413 ctrl |= PHY_CT_SP100;
414 break;
415 }
416
417 ctrl |= PHY_CT_RESET;
418 }
419
420 if (hw->chip_id != CHIP_ID_YUKON_FE)
421 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
422
423 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
424 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
425
426 /* Setup Phy LED's */
427 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
428 ledover = 0;
429
430 switch (hw->chip_id) {
431 case CHIP_ID_YUKON_FE:
432 /* on 88E3082 these bits are at 11..9 (shifted left) */
433 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
434
435 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
436
437 /* delete ACT LED control bits */
438 ctrl &= ~PHY_M_FELP_LED1_MSK;
439 /* change ACT LED control to blink mode */
440 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
441 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
442 break;
443
444 case CHIP_ID_YUKON_XL:
793b883e 445 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 446
447 /* select page 3 to access LED control register */
448 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
449
450 /* set LED Function Control register */
793b883e
SH		 451 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
452 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
453 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
454 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 455
456 /* set Polarity Control register */
457 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 458 (PHY_M_POLC_LS1_P_MIX(4) |
459 PHY_M_POLC_IS0_P_MIX(4) |
460 PHY_M_POLC_LOS_CTRL(2) |
461 PHY_M_POLC_INIT_CTRL(2) |
462 PHY_M_POLC_STA1_CTRL(2) |
463 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 464
465 /* restore page register */
793b883e 466 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 467 break;
468
469 default:
470 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
471 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
472 /* turn off the Rx LED (LED_RX) */
473 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
474 }
475
977bdf06
SH		 476 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
477 /* apply fixes in PHY AFE */
478 gm_phy_write(hw, port, 22, 255);
479 /* increase differential signal amplitude in 10BASE-T */
480 gm_phy_write(hw, port, 24, 0xaa99);
481 gm_phy_write(hw, port, 23, 0x2011);
cd28ab6a 482
977bdf06
SH		 483 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
484 gm_phy_write(hw, port, 24, 0xa204);
485 gm_phy_write(hw, port, 23, 0x2002);
486
487 /* set page register to 0 */
488 gm_phy_write(hw, port, 22, 0);
489 } else {
490 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 491
977bdf06
SH		 492 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
493 /* turn on 100 Mbps LED (LED_LINK100) */
494 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
495 }
cd28ab6a 496
977bdf06
SH		 497 if (ledover)
498 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
499
500 }
d571b694 501 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 502 if (sky2->autoneg == AUTONEG_ENABLE)
503 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
504 else
505 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
506}
507
1b537565
SH		 508/* Force a renegotiation */
509static void sky2_phy_reinit(struct sky2_port *sky2)
510{
e07b1aa8 511 spin_lock_bh(&sky2->phy_lock);
1b537565 512 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 513 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 514}
515
cd28ab6a
SH		 516static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
517{
518 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
519 u16 reg;
520 int i;
521 const u8 *addr = hw->dev[port]->dev_addr;
522
42eeea01 523 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
524 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 525
526 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
527
793b883e 528 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 529 /* WA DEV_472 -- looks like crossed wires on port 2 */
530 /* clear GMAC 1 Control reset */
531 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
532 do {
533 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
534 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
535 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
536 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
537 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
538 }
539
cd28ab6a
SH		 540 if (sky2->autoneg == AUTONEG_DISABLE) {
541 reg = gma_read16(hw, port, GM_GP_CTRL);
542 reg |= GM_GPCR_AU_ALL_DIS;
543 gma_write16(hw, port, GM_GP_CTRL, reg);
544 gma_read16(hw, port, GM_GP_CTRL);
545
cd28ab6a
SH		 546 switch (sky2->speed) {
547 case SPEED_1000:
6f4c56b2 548 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 549 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 550 break;
cd28ab6a 551 case SPEED_100:
6f4c56b2 552 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 553 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 554 break;
555 case SPEED_10:
556 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
557 break;
cd28ab6a
SH		 558 }
559
560 if (sky2->duplex == DUPLEX_FULL)
561 reg |= GM_GPCR_DUP_FULL;
562 } else
563 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564
565 if (!sky2->tx_pause && !sky2->rx_pause) {
566 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 567 reg |=
568 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
569 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 570 /* disable Rx flow-control */
571 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
572 }
573
574 gma_write16(hw, port, GM_GP_CTRL, reg);
575
793b883e 576 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 577
e07b1aa8 578 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 579 sky2_phy_init(hw, port);
e07b1aa8 580 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 581
582 /* MIB clear */
583 reg = gma_read16(hw, port, GM_PHY_ADDR);
584 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
585
43f2f104
SH		 586 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
587 gma_read16(hw, port, i);
cd28ab6a
SH		 588 gma_write16(hw, port, GM_PHY_ADDR, reg);
589
590 /* transmit control */
591 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
592
593 /* receive control reg: unicast + multicast + no FCS */
594 gma_write16(hw, port, GM_RX_CTRL,
793b883e 595 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 596
597 /* transmit flow control */
598 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
599
600 /* transmit parameter */
601 gma_write16(hw, port, GM_TX_PARAM,
602 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
603 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
604 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
605 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
606
607 /* serial mode register */
608 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 609 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 610
6b1a3aef 611 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 612 reg |= GM_SMOD_JUMBO_ENA;
613
614 gma_write16(hw, port, GM_SERIAL_MODE, reg);
615
cd28ab6a
SH		 616 /* virtual address for data */
617 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
618
793b883e
SH		 619 /* physical address: used for pause frames */
620 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
621
622 /* ignore counter overflows */
cd28ab6a
SH		 623 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
624 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
625 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
626
627 /* Configure Rx MAC FIFO */
628 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 629 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
630 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 631
d571b694 632 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 633 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 634
793b883e
SH		 635 /* Set threshold to 0xa (64 bytes)
636 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 637 */
638 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
639
640 /* Configure Tx MAC FIFO */
641 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
642 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 643
644 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
645 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
646 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
647 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
648 /* set Tx GMAC FIFO Almost Empty Threshold */
649 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
650 /* Disable Store & Forward mode for TX */
651 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
652 }
653 }
654
cd28ab6a
SH		 655}
656
1c28f6ba
SH		 657/* Assign Ram Buffer allocation.
658 * start and end are in units of 4k bytes
659 * ram registers are in units of 64bit words
660 */
661static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 662{
1c28f6ba 663 u32 start, end;
cd28ab6a 664
1c28f6ba
SH		 665 start = startk * 4096/8;
666 end = (endk * 4096/8) - 1;
793b883e 667
cd28ab6a
SH		 668 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
669 sky2_write32(hw, RB_ADDR(q, RB_START), start);
670 sky2_write32(hw, RB_ADDR(q, RB_END), end);
671 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
672 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
673
674 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 675 u32 space = (endk - startk) * 4096/8;
676 u32 tp = space - space/4;
793b883e 677
1c28f6ba
SH		 678 /* On receive queue's set the thresholds
679 * give receiver priority when > 3/4 full
680 * send pause when down to 2K
681 */
682 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
683 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 684
1c28f6ba
SH		 685 tp = space - 2048/8;
686 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
687 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 688 } else {
689 /* Enable store & forward on Tx queue's because
690 * Tx FIFO is only 1K on Yukon
691 */
692 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
693 }
694
695 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 696 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 697}
698
cd28ab6a 699/* Setup Bus Memory Interface */
af4ed7e6 700static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 701{
702 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
703 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
704 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 705 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 706}
707
cd28ab6a
SH		 708/* Setup prefetch unit registers. This is the interface between
709 * hardware and driver list elements
710 */
8cc048e3 711static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 712 u64 addr, u32 last)
713{
cd28ab6a
SH		 714 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
715 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
716 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
717 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
718 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
719 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 720
721 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 722}
723
793b883e
SH		 724static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
725{
726 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
727
cb5d9547 728 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
793b883e
SH		 729 return le;
730}
cd28ab6a 731
290d4de5
SH		 732/* Update chip's next pointer */
733static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 734{
762c2de2 735 wmb();
290d4de5 736 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
762c2de2 737 mmiowb();
cd28ab6a
SH		 738}
739
793b883e 740
cd28ab6a
SH		 741static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
742{
743 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 744 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
cd28ab6a
SH		 745 return le;
746}
747
a018e330 748/* Return high part of DMA address (could be 32 or 64 bit) */
749static inline u32 high32(dma_addr_t a)
750{
a036119f 751 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 752}
753
793b883e 754/* Build description to hardware about buffer */
28bd181a 755static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 756{
757 struct sky2_rx_le *le;
734d1868
SH		 758 u32 hi = high32(map);
759 u16 len = sky2->rx_bufsize;
cd28ab6a 760
793b883e 761 if (sky2->rx_addr64 != hi) {
cd28ab6a 762 le = sky2_next_rx(sky2);
793b883e 763 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 764 le->ctrl = 0;
765 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 766 sky2->rx_addr64 = high32(map + len);
cd28ab6a 767 }
793b883e 768
cd28ab6a 769 le = sky2_next_rx(sky2);
734d1868
SH		 770 le->addr = cpu_to_le32((u32) map);
771 le->length = cpu_to_le16(len);
cd28ab6a
SH		 772 le->ctrl = 0;
773 le->opcode = OP_PACKET | HW_OWNER;
774}
775
793b883e 776
cd28ab6a
SH		 777/* Tell chip where to start receive checksum.
778 * Actually has two checksums, but set both same to avoid possible byte
779 * order problems.
780 */
793b883e 781static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 782{
783 struct sky2_rx_le *le;
784
cd28ab6a 785 le = sky2_next_rx(sky2);
793b883e 786 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 787 le->ctrl = 0;
788 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 789
793b883e
SH		 790 sky2_write32(sky2->hw,
791 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
792 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 793
794}
795
6b1a3aef 796/*
797 * The RX Stop command will not work for Yukon-2 if the BMU does not
798 * reach the end of packet and since we can't make sure that we have
799 * incoming data, we must reset the BMU while it is not doing a DMA
800 * transfer. Since it is possible that the RX path is still active,
801 * the RX RAM buffer will be stopped first, so any possible incoming
802 * data will not trigger a DMA. After the RAM buffer is stopped, the
803 * BMU is polled until any DMA in progress is ended and only then it
804 * will be reset.
805 */
806static void sky2_rx_stop(struct sky2_port *sky2)
807{
808 struct sky2_hw *hw = sky2->hw;
809 unsigned rxq = rxqaddr[sky2->port];
810 int i;
811
812 /* disable the RAM Buffer receive queue */
813 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
814
815 for (i = 0; i < 0xffff; i++)
816 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
817 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
818 goto stopped;
819
820 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
821 sky2->netdev->name);
822stopped:
823 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
824
825 /* reset the Rx prefetch unit */
826 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
827}
793b883e 828
d571b694 829/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 830static void sky2_rx_clean(struct sky2_port *sky2)
831{
832 unsigned i;
833
834 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 835 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 836 struct ring_info *re = sky2->rx_ring + i;
837
838 if (re->skb) {
793b883e 839 pci_unmap_single(sky2->hw->pdev,
734d1868 840 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 841 PCI_DMA_FROMDEVICE);
842 kfree_skb(re->skb);
843 re->skb = NULL;
844 }
845 }
846}
847
ef743d33 848/* Basic MII support */
849static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
850{
851 struct mii_ioctl_data *data = if_mii(ifr);
852 struct sky2_port *sky2 = netdev_priv(dev);
853 struct sky2_hw *hw = sky2->hw;
854 int err = -EOPNOTSUPP;
855
856 if (!netif_running(dev))
857 return -ENODEV; /* Phy still in reset */
858
d89e1343 859 switch (cmd) {
ef743d33 860 case SIOCGMIIPHY:
861 data->phy_id = PHY_ADDR_MARV;
862
863 /* fallthru */
864 case SIOCGMIIREG: {
865 u16 val = 0;
91c86df5 866
e07b1aa8 867 spin_lock_bh(&sky2->phy_lock);
ef743d33 868 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 869 spin_unlock_bh(&sky2->phy_lock);
91c86df5 870
ef743d33 871 data->val_out = val;
872 break;
873 }
874
875 case SIOCSMIIREG:
876 if (!capable(CAP_NET_ADMIN))
877 return -EPERM;
878
e07b1aa8 879 spin_lock_bh(&sky2->phy_lock);
ef743d33 880 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
881 data->val_in);
e07b1aa8 882 spin_unlock_bh(&sky2->phy_lock);
ef743d33 883 break;
884 }
885 return err;
886}
887
d1f13708 888#ifdef SKY2_VLAN_TAG_USED
889static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
890{
891 struct sky2_port *sky2 = netdev_priv(dev);
892 struct sky2_hw *hw = sky2->hw;
893 u16 port = sky2->port;
d1f13708 894
302d1252 895 spin_lock_bh(&sky2->tx_lock);
d1f13708 896
897 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
898 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
899 sky2->vlgrp = grp;
900
302d1252 901 spin_unlock_bh(&sky2->tx_lock);
d1f13708 902}
903
904static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
905{
906 struct sky2_port *sky2 = netdev_priv(dev);
907 struct sky2_hw *hw = sky2->hw;
908 u16 port = sky2->port;
d1f13708 909
302d1252 910 spin_lock_bh(&sky2->tx_lock);
d1f13708 911
912 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
913 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
914 if (sky2->vlgrp)
915 sky2->vlgrp->vlan_devices[vid] = NULL;
916
302d1252 917 spin_unlock_bh(&sky2->tx_lock);
d1f13708 918}
919#endif
920
82788c7a
SH		 921/*
922 * It appears the hardware has a bug in the FIFO logic that
923 * cause it to hang if the FIFO gets overrun and the receive buffer
924 * is not aligned. ALso alloc_skb() won't align properly if slab
925 * debugging is enabled.
926 */
927static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
928{
929 struct sk_buff *skb;
930
931 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
932 if (likely(skb)) {
933 unsigned long p = (unsigned long) skb->data;
4a15d56f 934 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 935 }
936
937 return skb;
938}
939
cd28ab6a
SH		 940/*
941 * Allocate and setup receiver buffer pool.
942 * In case of 64 bit dma, there are 2X as many list elements
943 * available as ring entries
944 * and need to reserve one list element so we don't wrap around.
945 */
6b1a3aef 946static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 947{
6b1a3aef 948 struct sky2_hw *hw = sky2->hw;
6b1a3aef 949 unsigned rxq = rxqaddr[sky2->port];
950 int i;
cd28ab6a 951
6b1a3aef 952 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 953 sky2_qset(hw, rxq);
977bdf06
SH		 954
955 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
956 /* MAC Rx RAM Read is controlled by hardware */
957 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
958 }
959
6b1a3aef 960 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
961
962 rx_set_checksum(sky2);
793b883e 963 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 964 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 965
82788c7a 966 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 967 if (!re->skb)
968 goto nomem;
969
6b1a3aef 970 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 971 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
972 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 973 }
974
70f1be48
SH		 975 /* Truncate oversize frames */
976 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
977 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
978
6b1a3aef 979 /* Tell chip about available buffers */
980 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 981 return 0;
982nomem:
983 sky2_rx_clean(sky2);
984 return -ENOMEM;
985}
986
987/* Bring up network interface. */
988static int sky2_up(struct net_device *dev)
989{
990 struct sky2_port *sky2 = netdev_priv(dev);
991 struct sky2_hw *hw = sky2->hw;
992 unsigned port = sky2->port;
e07b1aa8 993 u32 ramsize, rxspace, imask;
cd28ab6a
SH		 994 int err = -ENOMEM;
995
996 if (netif_msg_ifup(sky2))
997 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
998
999 /* must be power of 2 */
1000 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1001 TX_RING_SIZE *
1002 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1003 &sky2->tx_le_map);
1004 if (!sky2->tx_le)
1005 goto err_out;
1006
6cdbbdf3 1007 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1008 GFP_KERNEL);
1009 if (!sky2->tx_ring)
1010 goto err_out;
1011 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1012
1013 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1014 &sky2->rx_le_map);
1015 if (!sky2->rx_le)
1016 goto err_out;
1017 memset(sky2->rx_le, 0, RX_LE_BYTES);
1018
6cdbbdf3 1019 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1020 GFP_KERNEL);
1021 if (!sky2->rx_ring)
1022 goto err_out;
1023
1024 sky2_mac_init(hw, port);
1025
1c28f6ba
SH		 1026 /* Determine available ram buffer space (in 4K blocks).
1027 * Note: not sure about the FE setting below yet
1028 */
1029 if (hw->chip_id == CHIP_ID_YUKON_FE)
1030 ramsize = 4;
1031 else
1032 ramsize = sky2_read8(hw, B2_E_0);
1033
1034 /* Give transmitter one third (rounded up) */
1035 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1036
cd28ab6a 1037 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1038 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1039
793b883e
SH		 1040 /* Make sure SyncQ is disabled */
1041 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1042 RB_RST_SET);
1043
af4ed7e6 1044 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1045
977bdf06
SH		 1046 /* Set almost empty threshold */
1047 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1048 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1049
6b1a3aef 1050 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1051 TX_RING_SIZE - 1);
cd28ab6a 1052
6b1a3aef 1053 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1054 if (err)
1055 goto err_out;
1056
cd28ab6a 1057 /* Enable interrupts from phy/mac for port */
e07b1aa8
SH		 1058 imask = sky2_read32(hw, B0_IMSK);
1059 imask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1060 sky2_write32(hw, B0_IMSK, imask);
1061
cd28ab6a
SH		 1062 return 0;
1063
1064err_out:
1b537565 1065 if (sky2->rx_le) {
cd28ab6a
SH		 1066 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1067 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1068 sky2->rx_le = NULL;
1069 }
1070 if (sky2->tx_le) {
cd28ab6a
SH		 1071 pci_free_consistent(hw->pdev,
1072 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1073 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1074 sky2->tx_le = NULL;
1075 }
1076 kfree(sky2->tx_ring);
1077 kfree(sky2->rx_ring);
cd28ab6a 1078
1b537565
SH		 1079 sky2->tx_ring = NULL;
1080 sky2->rx_ring = NULL;
cd28ab6a
SH		 1081 return err;
1082}
1083
793b883e
SH		 1084/* Modular subtraction in ring */
1085static inline int tx_dist(unsigned tail, unsigned head)
1086{
cb5d9547 1087 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1088}
cd28ab6a 1089
793b883e
SH		 1090/* Number of list elements available for next tx */
1091static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1092{
793b883e 1093 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1094}
1095
793b883e 1096/* Estimate of number of transmit list elements required */
28bd181a 1097static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1098{
793b883e
SH		 1099 unsigned count;
1100
1101 count = sizeof(dma_addr_t) / sizeof(u32);
1102 count += skb_shinfo(skb)->nr_frags * count;
1103
1104 if (skb_shinfo(skb)->tso_size)
1105 ++count;
1106
0e3ff6aa 1107 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1108 ++count;
1109
1110 return count;
cd28ab6a
SH		 1111}
1112
793b883e
SH		 1113/*
1114 * Put one packet in ring for transmit.
1115 * A single packet can generate multiple list elements, and
1116 * the number of ring elements will probably be less than the number
1117 * of list elements used.
f2e46561
SH		 1118 *
1119 * No BH disabling for tx_lock here (like tg3)
793b883e 1120 */
cd28ab6a
SH		 1121static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1122{
1123 struct sky2_port *sky2 = netdev_priv(dev);
1124 struct sky2_hw *hw = sky2->hw;
d1f13708 1125 struct sky2_tx_le *le = NULL;
6cdbbdf3 1126 struct tx_ring_info *re;
cd28ab6a 1127 unsigned i, len;
b19666d9 1128 int avail;
cd28ab6a
SH		 1129 dma_addr_t mapping;
1130 u32 addr64;
1131 u16 mss;
1132 u8 ctrl;
1133
302d1252
SH		 1134 /* No BH disabling for tx_lock here. We are running in BH disabled
1135 * context and TX reclaim runs via poll inside of a software
1136 * interrupt, and no related locks in IRQ processing.
1137 */
f2e46561 1138 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1139 return NETDEV_TX_LOCKED;
1140
793b883e 1141 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1142 /* There is a known but harmless race with lockless tx
1143 * and netif_stop_queue.
1144 */
1145 if (!netif_queue_stopped(dev)) {
1146 netif_stop_queue(dev);
3be92a70
SH		 1147 if (net_ratelimit())
1148 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1149 dev->name);
8c463ef7 1150 }
f2e46561 1151 spin_unlock(&sky2->tx_lock);
cd28ab6a 1152
cd28ab6a
SH		 1153 return NETDEV_TX_BUSY;
1154 }
1155
793b883e 1156 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1157 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1158 dev->name, sky2->tx_prod, skb->len);
1159
cd28ab6a
SH		 1160 len = skb_headlen(skb);
1161 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1162 addr64 = high32(mapping);
793b883e
SH		 1163
1164 re = sky2->tx_ring + sky2->tx_prod;
1165
a018e330 1166 /* Send high bits if changed or crosses boundary */
1167 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1168 le = get_tx_le(sky2);
1169 le->tx.addr = cpu_to_le32(addr64);
1170 le->ctrl = 0;
1171 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1172 sky2->tx_addr64 = high32(mapping + len);
793b883e 1173 }
cd28ab6a
SH		 1174
1175 /* Check for TCP Segmentation Offload */
1176 mss = skb_shinfo(skb)->tso_size;
793b883e 1177 if (mss != 0) {
cd28ab6a
SH		 1178 /* just drop the packet if non-linear expansion fails */
1179 if (skb_header_cloned(skb) &&
1180 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
15240072 1181 dev_kfree_skb(skb);
793b883e 1182 goto out_unlock;
cd28ab6a
SH		 1183 }
1184
1185 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1186 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1187 mss += ETH_HLEN;
793b883e 1188 }
cd28ab6a 1189
793b883e 1190 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1191 le = get_tx_le(sky2);
1192 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1193 le->tx.tso.rsvd = 0;
cd28ab6a 1194 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1195 le->ctrl = 0;
793b883e 1196 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1197 }
1198
cd28ab6a 1199 ctrl = 0;
d1f13708 1200#ifdef SKY2_VLAN_TAG_USED
1201 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1202 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1203 if (!le) {
1204 le = get_tx_le(sky2);
1205 le->tx.addr = 0;
1206 le->opcode = OP_VLAN|HW_OWNER;
1207 le->ctrl = 0;
1208 } else
1209 le->opcode |= OP_VLAN;
1210 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1211 ctrl |= INS_VLAN;
1212 }
1213#endif
1214
1215 /* Handle TCP checksum offload */
cd28ab6a 1216 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1217 u16 hdr = skb->h.raw - skb->data;
1218 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1219
1220 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1221 if (skb->nh.iph->protocol == IPPROTO_UDP)
1222 ctrl |= UDPTCP;
1223
1224 le = get_tx_le(sky2);
1225 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1226 le->tx.csum.offset = cpu_to_le16(offset);
1227 le->length = 0; /* initial checksum value */
cd28ab6a 1228 le->ctrl = 1; /* one packet */
793b883e 1229 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1230 }
1231
1232 le = get_tx_le(sky2);
1233 le->tx.addr = cpu_to_le32((u32) mapping);
1234 le->length = cpu_to_le16(len);
1235 le->ctrl = ctrl;
793b883e 1236 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1237
793b883e 1238 /* Record the transmit mapping info */
cd28ab6a 1239 re->skb = skb;
6cdbbdf3 1240 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1241
1242 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1243 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1244 struct tx_ring_info *fre;
cd28ab6a
SH		 1245
1246 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1247 frag->size, PCI_DMA_TODEVICE);
a036119f 1248 addr64 = high32(mapping);
793b883e
SH		 1249 if (addr64 != sky2->tx_addr64) {
1250 le = get_tx_le(sky2);
1251 le->tx.addr = cpu_to_le32(addr64);
1252 le->ctrl = 0;
1253 le->opcode = OP_ADDR64 | HW_OWNER;
1254 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1255 }
1256
1257 le = get_tx_le(sky2);
1258 le->tx.addr = cpu_to_le32((u32) mapping);
1259 le->length = cpu_to_le16(frag->size);
1260 le->ctrl = ctrl;
793b883e 1261 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1262
793b883e 1263 fre = sky2->tx_ring
cb5d9547 1264 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
6cdbbdf3 1265 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1266 }
6cdbbdf3 1267
793b883e 1268 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1269 le->ctrl |= EOP;
1270
b19666d9
SH		 1271 avail = tx_avail(sky2);
1272 if (mss != 0 || avail < TX_MIN_PENDING) {
1273 le->ctrl |= FRC_STAT;
1274 if (avail <= MAX_SKB_TX_LE)
1275 netif_stop_queue(dev);
1276 }
1277
290d4de5 1278 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1279
793b883e 1280out_unlock:
f2e46561 1281 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1282
1283 dev->trans_start = jiffies;
1284 return NETDEV_TX_OK;
1285}
1286
cd28ab6a 1287/*
793b883e
SH		 1288 * Free ring elements from starting at tx_cons until "done"
1289 *
1290 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1291 * buffers; these are deferred until completion.
cd28ab6a 1292 */
d11c13e7 1293static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1294{
d11c13e7 1295 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1296 struct pci_dev *pdev = sky2->hw->pdev;
1297 u16 nxt, put;
793b883e 1298 unsigned i;
cd28ab6a 1299
0e3ff6aa 1300 BUG_ON(done >= TX_RING_SIZE);
2224795d 1301
d11c13e7 1302 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1303 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1304 dev->name, done);
cd28ab6a 1305
af2a58ac
SH		 1306 for (put = sky2->tx_cons; put != done; put = nxt) {
1307 struct tx_ring_info *re = sky2->tx_ring + put;
1308 struct sk_buff *skb = re->skb;
cd28ab6a 1309
d89e1343 1310 nxt = re->idx;
af2a58ac 1311 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1312 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1313
793b883e 1314 /* Check for partial status */
af2a58ac
SH		 1315 if (tx_dist(put, done) < tx_dist(put, nxt))
1316 break;
793b883e
SH		 1317
1318 skb = re->skb;
af2a58ac 1319 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1320 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1321
1322 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1323 struct tx_ring_info *fre;
cb5d9547 1324 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
af2a58ac 1325 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1326 skb_shinfo(skb)->frags[i].size,
734d1868 1327 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1328 }
1329
15240072 1330 dev_kfree_skb(skb);
793b883e 1331 }
793b883e 1332
af2a58ac 1333 sky2->tx_cons = put;
8f24664d 1334 if (tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a 1335 netif_wake_queue(dev);
cd28ab6a
SH		 1336}
1337
1338/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1339static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1340{
302d1252 1341 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1342 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1343 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1344}
1345
1346/* Network shutdown */
1347static int sky2_down(struct net_device *dev)
1348{
1349 struct sky2_port *sky2 = netdev_priv(dev);
1350 struct sky2_hw *hw = sky2->hw;
1351 unsigned port = sky2->port;
1352 u16 ctrl;
e07b1aa8 1353 u32 imask;
cd28ab6a 1354
1b537565
SH		 1355 /* Never really got started! */
1356 if (!sky2->tx_le)
1357 return 0;
1358
cd28ab6a
SH		 1359 if (netif_msg_ifdown(sky2))
1360 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1361
018d1c66 1362 /* Stop more packets from being queued */
cd28ab6a
SH		 1363 netif_stop_queue(dev);
1364
793b883e
SH		 1365 sky2_phy_reset(hw, port);
1366
cd28ab6a
SH		 1367 /* Stop transmitter */
1368 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1369 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1370
1371 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1372 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1373
1374 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1375 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1376 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1377
1378 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1379
1380 /* Workaround shared GMAC reset */
793b883e
SH		 1381 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1382 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1383 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1384
1385 /* Disable Force Sync bit and Enable Alloc bit */
1386 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1387 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1388
1389 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1390 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1391 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1392
1393 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1394 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1395 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1396
1397 /* Reset the Tx prefetch units */
1398 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1399 PREF_UNIT_RST_SET);
1400
1401 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1402
6b1a3aef 1403 sky2_rx_stop(sky2);
cd28ab6a
SH		 1404
1405 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1406 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1407
e07b1aa8
SH		 1408 /* Disable port IRQ */
1409 imask = sky2_read32(hw, B0_IMSK);
1410 imask &= ~(sky2->port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1411 sky2_write32(hw, B0_IMSK, imask);
1412
d571b694 1413 /* turn off LED's */
cd28ab6a
SH		 1414 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1415
018d1c66 1416 synchronize_irq(hw->pdev->irq);
1417
cd28ab6a
SH		 1418 sky2_tx_clean(sky2);
1419 sky2_rx_clean(sky2);
1420
1421 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1422 sky2->rx_le, sky2->rx_le_map);
1423 kfree(sky2->rx_ring);
1424
1425 pci_free_consistent(hw->pdev,
1426 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1427 sky2->tx_le, sky2->tx_le_map);
1428 kfree(sky2->tx_ring);
1429
1b537565
SH		 1430 sky2->tx_le = NULL;
1431 sky2->rx_le = NULL;
1432
1433 sky2->rx_ring = NULL;
1434 sky2->tx_ring = NULL;
1435
cd28ab6a
SH		 1436 return 0;
1437}
1438
1439static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1440{
793b883e
SH		 1441 if (!hw->copper)
1442 return SPEED_1000;
1443
cd28ab6a
SH		 1444 if (hw->chip_id == CHIP_ID_YUKON_FE)
1445 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1446
1447 switch (aux & PHY_M_PS_SPEED_MSK) {
1448 case PHY_M_PS_SPEED_1000:
1449 return SPEED_1000;
1450 case PHY_M_PS_SPEED_100:
1451 return SPEED_100;
1452 default:
1453 return SPEED_10;
1454 }
1455}
1456
1457static void sky2_link_up(struct sky2_port *sky2)
1458{
1459 struct sky2_hw *hw = sky2->hw;
1460 unsigned port = sky2->port;
1461 u16 reg;
1462
1463 /* Enable Transmit FIFO Underrun */
793b883e 1464 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1465
1466 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1467 if (sky2->autoneg == AUTONEG_DISABLE) {
1468 reg |= GM_GPCR_AU_ALL_DIS;
1469
1470 /* Is write/read necessary? Copied from sky2_mac_init */
1471 gma_write16(hw, port, GM_GP_CTRL, reg);
1472 gma_read16(hw, port, GM_GP_CTRL);
1473
1474 switch (sky2->speed) {
1475 case SPEED_1000:
1476 reg &= ~GM_GPCR_SPEED_100;
1477 reg |= GM_GPCR_SPEED_1000;
1478 break;
1479 case SPEED_100:
1480 reg &= ~GM_GPCR_SPEED_1000;
1481 reg |= GM_GPCR_SPEED_100;
1482 break;
1483 case SPEED_10:
1484 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1485 break;
1486 }
1487 } else
1488 reg &= ~GM_GPCR_AU_ALL_DIS;
1489
cd28ab6a
SH		 1490 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1491 reg |= GM_GPCR_DUP_FULL;
1492
cd28ab6a
SH		 1493 /* enable Rx/Tx */
1494 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1495 gma_write16(hw, port, GM_GP_CTRL, reg);
1496 gma_read16(hw, port, GM_GP_CTRL);
1497
1498 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1499
1500 netif_carrier_on(sky2->netdev);
1501 netif_wake_queue(sky2->netdev);
1502
1503 /* Turn on link LED */
793b883e 1504 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1505 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1506
793b883e
SH		 1507 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1508 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1509
1510 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1511 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1512 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1513 SPEED_10 ? 7 : 0) |
1514 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1515 SPEED_100 ? 7 : 0) |
1516 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1517 SPEED_1000 ? 7 : 0));
1518 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1519 }
1520
cd28ab6a
SH		 1521 if (netif_msg_link(sky2))
1522 printk(KERN_INFO PFX
d571b694 1523 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1524 sky2->netdev->name, sky2->speed,
1525 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1526 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1527 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1528}
1529
1530static void sky2_link_down(struct sky2_port *sky2)
1531{
1532 struct sky2_hw *hw = sky2->hw;
1533 unsigned port = sky2->port;
1534 u16 reg;
1535
1536 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1537
1538 reg = gma_read16(hw, port, GM_GP_CTRL);
1539 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1540 gma_write16(hw, port, GM_GP_CTRL, reg);
1541 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1542
1543 if (sky2->rx_pause && !sky2->tx_pause) {
1544 /* restore Asymmetric Pause bit */
1545 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1546 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1547 | PHY_M_AN_ASP);
cd28ab6a
SH		 1548 }
1549
cd28ab6a
SH		 1550 netif_carrier_off(sky2->netdev);
1551 netif_stop_queue(sky2->netdev);
1552
1553 /* Turn on link LED */
1554 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1555
1556 if (netif_msg_link(sky2))
1557 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1558 sky2_phy_init(hw, port);
1559}
1560
793b883e
SH		 1561static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1562{
1563 struct sky2_hw *hw = sky2->hw;
1564 unsigned port = sky2->port;
1565 u16 lpa;
1566
1567 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1568
1569 if (lpa & PHY_M_AN_RF) {
1570 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1571 return -1;
1572 }
1573
1574 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1575 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1576 printk(KERN_ERR PFX "%s: master/slave fault",
1577 sky2->netdev->name);
1578 return -1;
1579 }
1580
1581 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1582 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1583 sky2->netdev->name);
1584 return -1;
1585 }
1586
1587 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1588
1589 sky2->speed = sky2_phy_speed(hw, aux);
1590
1591 /* Pause bits are offset (9..8) */
1592 if (hw->chip_id == CHIP_ID_YUKON_XL)
1593 aux >>= 6;
1594
1595 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1596 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1597
1598 if ((sky2->tx_pause || sky2->rx_pause)
1599 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1600 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1601 else
1602 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1603
1604 return 0;
1605}
cd28ab6a 1606
e07b1aa8
SH		 1607/* Interrupt from PHY */
1608static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1609{
e07b1aa8
SH		 1610 struct net_device *dev = hw->dev[port];
1611 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1612 u16 istatus, phystat;
1613
e07b1aa8
SH		 1614 spin_lock(&sky2->phy_lock);
1615 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1616 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1617
1618 if (!netif_running(dev))
1619 goto out;
cd28ab6a
SH		 1620
1621 if (netif_msg_intr(sky2))
1622 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1623 sky2->netdev->name, istatus, phystat);
1624
1625 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1626 if (sky2_autoneg_done(sky2, phystat) == 0)
1627 sky2_link_up(sky2);
1628 goto out;
1629 }
cd28ab6a 1630
793b883e
SH		 1631 if (istatus & PHY_M_IS_LSP_CHANGE)
1632 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1633
793b883e
SH		 1634 if (istatus & PHY_M_IS_DUP_CHANGE)
1635 sky2->duplex =
1636 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1637
793b883e
SH		 1638 if (istatus & PHY_M_IS_LST_CHANGE) {
1639 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1640 sky2_link_up(sky2);
793b883e
SH		 1641 else
1642 sky2_link_down(sky2);
cd28ab6a 1643 }
793b883e 1644out:
e07b1aa8 1645 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1646}
1647
302d1252
SH		 1648
1649/* Transmit timeout is only called if we are running, carries is up
1650 * and tx queue is full (stopped).
1651 */
cd28ab6a
SH		 1652static void sky2_tx_timeout(struct net_device *dev)
1653{
1654 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1655 struct sky2_hw *hw = sky2->hw;
1656 unsigned txq = txqaddr[sky2->port];
8f24664d 1657 u16 report, done;
cd28ab6a
SH		 1658
1659 if (netif_msg_timer(sky2))
1660 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1661
8f24664d
SH		 1662 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1663 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1664
8f24664d
SH		 1665 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1666 dev->name,
1667 sky2->tx_cons, sky2->tx_prod, report, done);
1668
1669 if (report != done) {
1670 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1671
1672 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1673 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1674 } else if (report != sky2->tx_cons) {
1675 printk(KERN_INFO PFX "status report lost?\n");
1676
1677 spin_lock_bh(&sky2->tx_lock);
1678 sky2_tx_complete(sky2, report);
1679 spin_unlock_bh(&sky2->tx_lock);
1680 } else {
1681 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1682
8f24664d
SH		 1683 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1684 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1685
1686 sky2_tx_clean(sky2);
1687
1688 sky2_qset(hw, txq);
1689 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1690 }
cd28ab6a
SH		 1691}
1692
734d1868 1693
70f1be48
SH		 1694/* Want receive buffer size to be multiple of 64 bits
1695 * and incl room for vlan and truncation
1696 */
734d1868
SH		 1697static inline unsigned sky2_buf_size(int mtu)
1698{
4a15d56f 1699 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1700}
1701
cd28ab6a
SH		 1702static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1703{
6b1a3aef 1704 struct sky2_port *sky2 = netdev_priv(dev);
1705 struct sky2_hw *hw = sky2->hw;
1706 int err;
1707 u16 ctl, mode;
e07b1aa8 1708 u32 imask;
cd28ab6a
SH		 1709
1710 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1711 return -EINVAL;
1712
5a5b1ea0 1713 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1714 return -EINVAL;
1715
6b1a3aef 1716 if (!netif_running(dev)) {
1717 dev->mtu = new_mtu;
1718 return 0;
1719 }
1720
e07b1aa8 1721 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1722 sky2_write32(hw, B0_IMSK, 0);
1723
018d1c66 1724 dev->trans_start = jiffies; /* prevent tx timeout */
1725 netif_stop_queue(dev);
1726 netif_poll_disable(hw->dev[0]);
1727
e07b1aa8
SH		 1728 synchronize_irq(hw->pdev->irq);
1729
6b1a3aef 1730 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1731 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1732 sky2_rx_stop(sky2);
1733 sky2_rx_clean(sky2);
cd28ab6a
SH		 1734
1735 dev->mtu = new_mtu;
734d1868 1736 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef 1737 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1738 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1739
1740 if (dev->mtu > ETH_DATA_LEN)
1741 mode |= GM_SMOD_JUMBO_ENA;
1742
1743 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1744
6b1a3aef 1745 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1746
6b1a3aef 1747 err = sky2_rx_start(sky2);
e07b1aa8 1748 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1749
1b537565
SH		 1750 if (err)
1751 dev_close(dev);
1752 else {
1753 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1754
1755 netif_poll_enable(hw->dev[0]);
1756 netif_wake_queue(dev);
1757 }
1758
cd28ab6a
SH		 1759 return err;
1760}
1761
1762/*
1763 * Receive one packet.
1764 * For small packets or errors, just reuse existing skb.
d571b694 1765 * For larger packets, get new buffer.
cd28ab6a 1766 */
d11c13e7 1767static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1768 u16 length, u32 status)
1769{
cd28ab6a 1770 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1771 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1772
1773 if (unlikely(netif_msg_rx_status(sky2)))
1774 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1775 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1776
793b883e 1777 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1778 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1779
42eeea01 1780 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1781 goto error;
1782
42eeea01 1783 if (!(status & GMR_FS_RX_OK))
1784 goto resubmit;
1785
70f1be48 1786 if (length > sky2->netdev->mtu + ETH_HLEN)
6e15b712
SH		 1787 goto oversize;
1788
bdb5c58e 1789 if (length < copybreak) {
79e57d32
SH		 1790 skb = alloc_skb(length + 2, GFP_ATOMIC);
1791 if (!skb)
793b883e
SH		 1792 goto resubmit;
1793
79e57d32 1794 skb_reserve(skb, 2);
793b883e
SH		 1795 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1796 length, PCI_DMA_FROMDEVICE);
79e57d32 1797 memcpy(skb->data, re->skb->data, length);
d11c13e7 1798 skb->ip_summed = re->skb->ip_summed;
1799 skb->csum = re->skb->csum;
793b883e
SH		 1800 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1801 length, PCI_DMA_FROMDEVICE);
793b883e 1802 } else {
79e57d32
SH		 1803 struct sk_buff *nskb;
1804
82788c7a 1805 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1806 if (!nskb)
1807 goto resubmit;
cd28ab6a 1808
793b883e 1809 skb = re->skb;
79e57d32 1810 re->skb = nskb;
793b883e 1811 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1812 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1813 prefetch(skb->data);
cd28ab6a 1814
793b883e 1815 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1816 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1817 }
cd28ab6a 1818
79e57d32 1819 skb_put(skb, length);
793b883e 1820resubmit:
d11c13e7 1821 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1822 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1823
bea86103 1824 /* Tell receiver about new buffers. */
290d4de5 1825 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
bea86103 1826
cd28ab6a
SH		 1827 return skb;
1828
6e15b712
SH		 1829oversize:
1830 ++sky2->net_stats.rx_over_errors;
1831 goto resubmit;
1832
cd28ab6a 1833error:
6e15b712
SH		 1834 ++sky2->net_stats.rx_errors;
1835
3be92a70 1836 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a
SH		 1837 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1838 sky2->netdev->name, status, length);
793b883e
SH		 1839
1840 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1841 sky2->net_stats.rx_length_errors++;
1842 if (status & GMR_FS_FRAGMENT)
1843 sky2->net_stats.rx_frame_errors++;
1844 if (status & GMR_FS_CRC_ERR)
1845 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1846 if (status & GMR_FS_RX_FF_OV)
1847 sky2->net_stats.rx_fifo_errors++;
79e57d32 1848
793b883e 1849 goto resubmit;
cd28ab6a
SH		 1850}
1851
e07b1aa8
SH		 1852/* Transmit complete */
1853static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1854{
e07b1aa8 1855 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1856
e07b1aa8
SH		 1857 if (netif_running(dev)) {
1858 spin_lock(&sky2->tx_lock);
1859 sky2_tx_complete(sky2, last);
1860 spin_unlock(&sky2->tx_lock);
2224795d 1861 }
cd28ab6a
SH		 1862}
1863
e07b1aa8
SH		 1864/* Process status response ring */
1865static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1866{
e07b1aa8 1867 int work_done = 0;
a8fd6266 1868
af2a58ac 1869 rmb();
bea86103 1870
e07b1aa8 1871 for(;;) {
13210ce5 1872 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1873 struct net_device *dev;
d11c13e7 1874 struct sky2_port *sky2;
cd28ab6a 1875 struct sk_buff *skb;
cd28ab6a
SH		 1876 u32 status;
1877 u16 length;
e07b1aa8
SH		 1878 u8 link, opcode;
1879
1880 opcode = le->opcode;
1881 if (!opcode)
1882 break;
1883 opcode &= ~HW_OWNER;
cd28ab6a 1884
cb5d9547 1885 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
e07b1aa8 1886 le->opcode = 0;
bea86103 1887
e07b1aa8
SH		 1888 link = le->link;
1889 BUG_ON(link >= 2);
1890 dev = hw->dev[link];
13210ce5 1891
1892 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1893 length = le->length;
1894 status = le->status;
cd28ab6a 1895
e07b1aa8 1896 switch (opcode) {
cd28ab6a 1897 case OP_RXSTAT:
d11c13e7 1898 skb = sky2_receive(sky2, length, status);
d1f13708 1899 if (!skb)
1900 break;
13210ce5 1901
1902 skb->dev = dev;
1903 skb->protocol = eth_type_trans(skb, dev);
1904 dev->last_rx = jiffies;
1905
d1f13708 1906#ifdef SKY2_VLAN_TAG_USED
1907 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1908 vlan_hwaccel_receive_skb(skb,
1909 sky2->vlgrp,
1910 be16_to_cpu(sky2->rx_tag));
1911 } else
1912#endif
cd28ab6a 1913 netif_receive_skb(skb);
13210ce5 1914
1915 if (++work_done >= to_do)
1916 goto exit_loop;
cd28ab6a
SH		 1917 break;
1918
d1f13708 1919#ifdef SKY2_VLAN_TAG_USED
1920 case OP_RXVLAN:
1921 sky2->rx_tag = length;
1922 break;
1923
1924 case OP_RXCHKSVLAN:
1925 sky2->rx_tag = length;
1926 /* fall through */
1927#endif
cd28ab6a 1928 case OP_RXCHKS:
d11c13e7 1929 skb = sky2->rx_ring[sky2->rx_next].skb;
1930 skb->ip_summed = CHECKSUM_HW;
1931 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1932 break;
1933
1934 case OP_TXINDEXLE:
13b97b74 1935 /* TX index reports status for both ports */
f55925d7
SH		 1936 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
1937 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 1938 if (hw->dev[1])
1939 sky2_tx_done(hw->dev[1],
1940 ((status >> 24) & 0xff)
1941 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 1942 break;
1943
cd28ab6a
SH		 1944 default:
1945 if (net_ratelimit())
793b883e 1946 printk(KERN_WARNING PFX
e07b1aa8 1947 "unknown status opcode 0x%x\n", opcode);
cd28ab6a
SH		 1948 break;
1949 }
13210ce5 1950 }
cd28ab6a 1951
13210ce5 1952exit_loop:
e07b1aa8 1953 return work_done;
cd28ab6a
SH		 1954}
1955
1956static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1957{
1958 struct net_device *dev = hw->dev[port];
1959
3be92a70
SH		 1960 if (net_ratelimit())
1961 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1962 dev->name, status);
cd28ab6a
SH		 1963
1964 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 1965 if (net_ratelimit())
1966 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1967 dev->name);
cd28ab6a
SH		 1968 /* Clear IRQ */
1969 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1970 }
1971
1972 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 1973 if (net_ratelimit())
1974 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1975 dev->name);
cd28ab6a
SH		 1976
1977 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1978 }
1979
1980 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 1981 if (net_ratelimit())
1982 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 1983 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1984 }
1985
1986 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 1987 if (net_ratelimit())
1988 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 1989 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1990 }
1991
1992 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 1993 if (net_ratelimit())
1994 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
1995 dev->name);
cd28ab6a
SH		 1996 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1997 }
1998}
1999
2000static void sky2_hw_intr(struct sky2_hw *hw)
2001{
2002 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2003
793b883e 2004 if (status & Y2_IS_TIST_OV)
cd28ab6a 2005 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2006
2007 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2008 u16 pci_err;
2009
56a645cc 2010 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2011 if (net_ratelimit())
2012 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2013 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2014
2015 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2016 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2017 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2018 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2019 }
2020
2021 if (status & Y2_IS_PCI_EXP) {
d571b694 2022 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2023 u32 pex_err;
2024
56a645cc 2025 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2026
3be92a70
SH		 2027 if (net_ratelimit())
2028 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2029 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2030
2031 /* clear the interrupt */
2032 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2033 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2034 0xffffffffUL);
cd28ab6a
SH		 2035 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2036
2037 if (pex_err & PEX_FATAL_ERRORS) {
2038 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2039 hwmsk &= ~Y2_IS_PCI_EXP;
2040 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2041 }
2042 }
2043
2044 if (status & Y2_HWE_L1_MASK)
2045 sky2_hw_error(hw, 0, status);
2046 status >>= 8;
2047 if (status & Y2_HWE_L1_MASK)
2048 sky2_hw_error(hw, 1, status);
2049}
2050
2051static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2052{
2053 struct net_device *dev = hw->dev[port];
2054 struct sky2_port *sky2 = netdev_priv(dev);
2055 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2056
2057 if (netif_msg_intr(sky2))
2058 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2059 dev->name, status);
2060
2061 if (status & GM_IS_RX_FF_OR) {
2062 ++sky2->net_stats.rx_fifo_errors;
2063 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2064 }
2065
2066 if (status & GM_IS_TX_FF_UR) {
2067 ++sky2->net_stats.tx_fifo_errors;
2068 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2069 }
cd28ab6a
SH		 2070}
2071
d257924e
SH		 2072/* This should never happen it is a fatal situation */
2073static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2074 const char *rxtx, u32 mask)
2075{
2076 struct net_device *dev = hw->dev[port];
2077 struct sky2_port *sky2 = netdev_priv(dev);
2078 u32 imask;
2079
2080 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2081 dev ? dev->name : "<not registered>", rxtx);
2082
2083 imask = sky2_read32(hw, B0_IMSK);
2084 imask &= ~mask;
2085 sky2_write32(hw, B0_IMSK, imask);
2086
2087 if (dev) {
2088 spin_lock(&sky2->phy_lock);
2089 sky2_link_down(sky2);
2090 spin_unlock(&sky2->phy_lock);
2091 }
2092}
cd28ab6a 2093
d27ed387
SH		 2094/* If idle then force a fake soft NAPI poll once a second
2095 * to work around cases where sharing an edge triggered interrupt.
2096 */
2097static void sky2_idle(unsigned long arg)
2098{
01bd7564
SH		 2099 struct sky2_hw *hw = (struct sky2_hw *) arg;
2100 struct net_device *dev = hw->dev[0];
d27ed387 2101
d27ed387
SH		 2102 if (__netif_rx_schedule_prep(dev))
2103 __netif_rx_schedule(dev);
01bd7564
SH		 2104
2105 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2106}
2107
2108
e07b1aa8 2109static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2110{
e07b1aa8
SH		 2111 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2112 int work_limit = min(dev0->quota, *budget);
2113 int work_done = 0;
fb2690a9 2114 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2115
1e5f1283
SH		 2116 if (status & Y2_IS_HW_ERR)
2117 sky2_hw_intr(hw);
d257924e 2118
1e5f1283
SH		 2119 if (status & Y2_IS_IRQ_PHY1)
2120 sky2_phy_intr(hw, 0);
cd28ab6a 2121
1e5f1283
SH		 2122 if (status & Y2_IS_IRQ_PHY2)
2123 sky2_phy_intr(hw, 1);
cd28ab6a 2124
1e5f1283
SH		 2125 if (status & Y2_IS_IRQ_MAC1)
2126 sky2_mac_intr(hw, 0);
cd28ab6a 2127
1e5f1283
SH		 2128 if (status & Y2_IS_IRQ_MAC2)
2129 sky2_mac_intr(hw, 1);
cd28ab6a 2130
1e5f1283
SH		 2131 if (status & Y2_IS_CHK_RX1)
2132 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2133
1e5f1283
SH		 2134 if (status & Y2_IS_CHK_RX2)
2135 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2136
1e5f1283
SH		 2137 if (status & Y2_IS_CHK_TXA1)
2138 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2139
1e5f1283
SH		 2140 if (status & Y2_IS_CHK_TXA2)
2141 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2142
1e5f1283
SH		 2143 if (status & Y2_IS_STAT_BMU)
2144 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
e07b1aa8 2145
1e5f1283
SH		 2146 work_done = sky2_status_intr(hw, work_limit);
2147 *budget -= work_done;
2148 dev0->quota -= work_done;
e07b1aa8 2149
1e5f1283
SH		 2150 if (work_done >= work_limit)
2151 return 1;
e07b1aa8 2152
d3240312 2153 netif_rx_complete(dev0);
e07b1aa8 2154
fb2690a9 2155 status = sky2_read32(hw, B0_Y2_SP_LISR);
e07b1aa8
SH		 2156 return 0;
2157}
2158
2159static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2160{
2161 struct sky2_hw *hw = dev_id;
2162 struct net_device *dev0 = hw->dev[0];
2163 u32 status;
2164
2165 /* Reading this mask interrupts as side effect */
2166 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2167 if (status == 0 || status == ~0)
2168 return IRQ_NONE;
793b883e 2169
e07b1aa8
SH		 2170 prefetch(&hw->st_le[hw->st_idx]);
2171 if (likely(__netif_rx_schedule_prep(dev0)))
2172 __netif_rx_schedule(dev0);
793b883e 2173
cd28ab6a
SH		 2174 return IRQ_HANDLED;
2175}
2176
2177#ifdef CONFIG_NET_POLL_CONTROLLER
2178static void sky2_netpoll(struct net_device *dev)
2179{
2180 struct sky2_port *sky2 = netdev_priv(dev);
2181
793b883e 2182 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2183}
2184#endif
2185
2186/* Chip internal frequency for clock calculations */
fb17358f 2187static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2188{
793b883e 2189 switch (hw->chip_id) {
cd28ab6a 2190 case CHIP_ID_YUKON_EC:
5a5b1ea0 2191 case CHIP_ID_YUKON_EC_U:
fb17358f 2192 return 125; /* 125 Mhz */
cd28ab6a 2193 case CHIP_ID_YUKON_FE:
fb17358f 2194 return 100; /* 100 Mhz */
793b883e 2195 default: /* YUKON_XL */
fb17358f 2196 return 156; /* 156 Mhz */
cd28ab6a
SH		 2197 }
2198}
2199
fb17358f 2200static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2201{
fb17358f 2202 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2203}
2204
fb17358f 2205static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2206{
fb17358f 2207 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2208}
2209
fb17358f 2210
98712e5e 2211static int __devinit sky2_reset(struct sky2_hw *hw)
cd28ab6a 2212{
cd28ab6a
SH		 2213 u16 status;
2214 u8 t8, pmd_type;
56a645cc 2215 int i;
cd28ab6a 2216
cd28ab6a 2217 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2218
cd28ab6a
SH		 2219 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2220 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2221 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2222 pci_name(hw->pdev), hw->chip_id);
2223 return -EOPNOTSUPP;
2224 }
2225
290d4de5
SH		 2226 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2227
2228 /* This rev is really old, and requires untested workarounds */
2229 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2230 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2231 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2232 hw->chip_id, hw->chip_rev);
2233 return -EOPNOTSUPP;
2234 }
2235
2236 /* This chip is new and not tested yet */
2237 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
2238 pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
2239 pci_name(hw->pdev));
2240 pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
2241 }
2242
cd28ab6a
SH		 2243 /* disable ASF */
2244 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2245 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2246 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2247 }
2248
2249 /* do a SW reset */
2250 sky2_write8(hw, B0_CTST, CS_RST_SET);
2251 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2252
2253 /* clear PCI errors, if any */
56a645cc 2254 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2255
cd28ab6a 2256 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2257 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2258
cd28ab6a
SH		 2259
2260 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2261
2262 /* clear any PEX errors */
d89e1343 2263 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2264 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2265
cd28ab6a
SH		 2266
2267 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2268 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2269
2270 hw->ports = 1;
2271 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2272 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2273 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2274 ++hw->ports;
2275 }
cd28ab6a 2276
5afa0a9c 2277 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2278
2279 for (i = 0; i < hw->ports; i++) {
2280 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2281 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2282 }
2283
2284 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2285
793b883e
SH		 2286 /* Clear I2C IRQ noise */
2287 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2288
2289 /* turn off hardware timer (unused) */
2290 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2291 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2292
cd28ab6a
SH		 2293 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2294
69634ee7
SH		 2295 /* Turn off descriptor polling */
2296 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2297
2298 /* Turn off receive timestamp */
2299 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2300 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2301
2302 /* enable the Tx Arbiters */
2303 for (i = 0; i < hw->ports; i++)
2304 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2305
2306 /* Initialize ram interface */
2307 for (i = 0; i < hw->ports; i++) {
793b883e 2308 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2309
2310 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2311 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2312 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2313 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2314 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2315 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2316 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2317 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2318 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2319 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2320 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2321 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2322 }
2323
cd28ab6a
SH		 2324 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2325
cd28ab6a
SH		 2326 for (i = 0; i < hw->ports; i++)
2327 sky2_phy_reset(hw, i);
cd28ab6a 2328
cd28ab6a
SH		 2329 memset(hw->st_le, 0, STATUS_LE_BYTES);
2330 hw->st_idx = 0;
2331
2332 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2333 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2334
2335 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2336 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2337
2338 /* Set the list last index */
793b883e 2339 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2340
290d4de5
SH		 2341 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2342 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2343
290d4de5
SH		 2344 /* set Status-FIFO ISR watermark */
2345 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2346 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2347 else
2348 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2349
290d4de5 2350 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2351 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2352 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2353
793b883e 2354 /* enable status unit */
cd28ab6a
SH		 2355 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2356
2357 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2358 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2359 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2360
2361 return 0;
2362}
2363
28bd181a 2364static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2365{
2366 u32 modes;
2367 if (hw->copper) {
793b883e
SH		 2368 modes = SUPPORTED_10baseT_Half
2369 | SUPPORTED_10baseT_Full
2370 | SUPPORTED_100baseT_Half
2371 | SUPPORTED_100baseT_Full
2372 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2373
2374 if (hw->chip_id != CHIP_ID_YUKON_FE)
2375 modes |= SUPPORTED_1000baseT_Half
793b883e 2376 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2377 } else
2378 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2379 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2380 return modes;
2381}
2382
793b883e 2383static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2384{
2385 struct sky2_port *sky2 = netdev_priv(dev);
2386 struct sky2_hw *hw = sky2->hw;
2387
2388 ecmd->transceiver = XCVR_INTERNAL;
2389 ecmd->supported = sky2_supported_modes(hw);
2390 ecmd->phy_address = PHY_ADDR_MARV;
2391 if (hw->copper) {
2392 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2393 | SUPPORTED_10baseT_Full
2394 | SUPPORTED_100baseT_Half
2395 | SUPPORTED_100baseT_Full
2396 | SUPPORTED_1000baseT_Half
2397 | SUPPORTED_1000baseT_Full
2398 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2399 ecmd->port = PORT_TP;
2400 } else
2401 ecmd->port = PORT_FIBRE;
2402
2403 ecmd->advertising = sky2->advertising;
2404 ecmd->autoneg = sky2->autoneg;
2405 ecmd->speed = sky2->speed;
2406 ecmd->duplex = sky2->duplex;
2407 return 0;
2408}
2409
2410static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2411{
2412 struct sky2_port *sky2 = netdev_priv(dev);
2413 const struct sky2_hw *hw = sky2->hw;
2414 u32 supported = sky2_supported_modes(hw);
2415
2416 if (ecmd->autoneg == AUTONEG_ENABLE) {
2417 ecmd->advertising = supported;
2418 sky2->duplex = -1;
2419 sky2->speed = -1;
2420 } else {
2421 u32 setting;
2422
793b883e 2423 switch (ecmd->speed) {
cd28ab6a
SH		 2424 case SPEED_1000:
2425 if (ecmd->duplex == DUPLEX_FULL)
2426 setting = SUPPORTED_1000baseT_Full;
2427 else if (ecmd->duplex == DUPLEX_HALF)
2428 setting = SUPPORTED_1000baseT_Half;
2429 else
2430 return -EINVAL;
2431 break;
2432 case SPEED_100:
2433 if (ecmd->duplex == DUPLEX_FULL)
2434 setting = SUPPORTED_100baseT_Full;
2435 else if (ecmd->duplex == DUPLEX_HALF)
2436 setting = SUPPORTED_100baseT_Half;
2437 else
2438 return -EINVAL;
2439 break;
2440
2441 case SPEED_10:
2442 if (ecmd->duplex == DUPLEX_FULL)
2443 setting = SUPPORTED_10baseT_Full;
2444 else if (ecmd->duplex == DUPLEX_HALF)
2445 setting = SUPPORTED_10baseT_Half;
2446 else
2447 return -EINVAL;
2448 break;
2449 default:
2450 return -EINVAL;
2451 }
2452
2453 if ((setting & supported) == 0)
2454 return -EINVAL;
2455
2456 sky2->speed = ecmd->speed;
2457 sky2->duplex = ecmd->duplex;
2458 }
2459
2460 sky2->autoneg = ecmd->autoneg;
2461 sky2->advertising = ecmd->advertising;
2462
1b537565
SH		 2463 if (netif_running(dev))
2464 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2465
2466 return 0;
2467}
2468
2469static void sky2_get_drvinfo(struct net_device *dev,
2470 struct ethtool_drvinfo *info)
2471{
2472 struct sky2_port *sky2 = netdev_priv(dev);
2473
2474 strcpy(info->driver, DRV_NAME);
2475 strcpy(info->version, DRV_VERSION);
2476 strcpy(info->fw_version, "N/A");
2477 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2478}
2479
2480static const struct sky2_stat {
793b883e
SH		 2481 char name[ETH_GSTRING_LEN];
2482 u16 offset;
cd28ab6a
SH		 2483} sky2_stats[] = {
2484 { "tx_bytes", GM_TXO_OK_HI },
2485 { "rx_bytes", GM_RXO_OK_HI },
2486 { "tx_broadcast", GM_TXF_BC_OK },
2487 { "rx_broadcast", GM_RXF_BC_OK },
2488 { "tx_multicast", GM_TXF_MC_OK },
2489 { "rx_multicast", GM_RXF_MC_OK },
2490 { "tx_unicast", GM_TXF_UC_OK },
2491 { "rx_unicast", GM_RXF_UC_OK },
2492 { "tx_mac_pause", GM_TXF_MPAUSE },
2493 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2494 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2495 { "late_collision",GM_TXF_LAT_COL },
2496 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2497 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2498 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2499
d2604540 2500 { "rx_short", GM_RXF_SHT },
cd28ab6a 2501 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2502 { "rx_64_byte_packets", GM_RXF_64B },
2503 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2504 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2505 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2506 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2507 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2508 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2509 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2510 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2511 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2512 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2513
2514 { "tx_64_byte_packets", GM_TXF_64B },
2515 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2516 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2517 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2518 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2519 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2520 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2521 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2522};
2523
cd28ab6a
SH		 2524static u32 sky2_get_rx_csum(struct net_device *dev)
2525{
2526 struct sky2_port *sky2 = netdev_priv(dev);
2527
2528 return sky2->rx_csum;
2529}
2530
2531static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2532{
2533 struct sky2_port *sky2 = netdev_priv(dev);
2534
2535 sky2->rx_csum = data;
793b883e 2536
cd28ab6a
SH		 2537 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2538 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2539
2540 return 0;
2541}
2542
2543static u32 sky2_get_msglevel(struct net_device *netdev)
2544{
2545 struct sky2_port *sky2 = netdev_priv(netdev);
2546 return sky2->msg_enable;
2547}
2548
9a7ae0a9
SH		 2549static int sky2_nway_reset(struct net_device *dev)
2550{
2551 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2552
2553 if (sky2->autoneg != AUTONEG_ENABLE)
2554 return -EINVAL;
2555
1b537565 2556 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2557
2558 return 0;
2559}
2560
793b883e 2561static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2562{
2563 struct sky2_hw *hw = sky2->hw;
2564 unsigned port = sky2->port;
2565 int i;
2566
2567 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2568 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2569 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2570 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2571
793b883e 2572 for (i = 2; i < count; i++)
cd28ab6a
SH		 2573 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2574}
2575
cd28ab6a
SH		 2576static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2577{
2578 struct sky2_port *sky2 = netdev_priv(netdev);
2579 sky2->msg_enable = value;
2580}
2581
2582static int sky2_get_stats_count(struct net_device *dev)
2583{
2584 return ARRAY_SIZE(sky2_stats);
2585}
2586
2587static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2588 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2589{
2590 struct sky2_port *sky2 = netdev_priv(dev);
2591
793b883e 2592 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2593}
2594
793b883e 2595static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2596{
2597 int i;
2598
2599 switch (stringset) {
2600 case ETH_SS_STATS:
2601 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2602 memcpy(data + i * ETH_GSTRING_LEN,
2603 sky2_stats[i].name, ETH_GSTRING_LEN);
2604 break;
2605 }
2606}
2607
2608/* Use hardware MIB variables for critical path statistics and
2609 * transmit feedback not reported at interrupt.
2610 * Other errors are accounted for in interrupt handler.
2611 */
2612static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2613{
2614 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2615 u64 data[13];
cd28ab6a 2616
793b883e 2617 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2618
2619 sky2->net_stats.tx_bytes = data[0];
2620 sky2->net_stats.rx_bytes = data[1];
2621 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2622 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2623 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2624 sky2->net_stats.collisions = data[10];
2625 sky2->net_stats.tx_aborted_errors = data[12];
2626
2627 return &sky2->net_stats;
2628}
2629
2630static int sky2_set_mac_address(struct net_device *dev, void *p)
2631{
2632 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2633 struct sky2_hw *hw = sky2->hw;
2634 unsigned port = sky2->port;
2635 const struct sockaddr *addr = p;
cd28ab6a
SH		 2636
2637 if (!is_valid_ether_addr(addr->sa_data))
2638 return -EADDRNOTAVAIL;
2639
cd28ab6a 2640 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2641 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2642 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2643 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2644 dev->dev_addr, ETH_ALEN);
1b537565 2645
a8ab1ec0
SH		 2646 /* virtual address for data */
2647 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2648
2649 /* physical address: used for pause frames */
2650 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2651
2652 return 0;
cd28ab6a
SH		 2653}
2654
2655static void sky2_set_multicast(struct net_device *dev)
2656{
2657 struct sky2_port *sky2 = netdev_priv(dev);
2658 struct sky2_hw *hw = sky2->hw;
2659 unsigned port = sky2->port;
2660 struct dev_mc_list *list = dev->mc_list;
2661 u16 reg;
2662 u8 filter[8];
2663
2664 memset(filter, 0, sizeof(filter));
2665
2666 reg = gma_read16(hw, port, GM_RX_CTRL);
2667 reg |= GM_RXCR_UCF_ENA;
2668
d571b694 2669 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2670 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2671 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2672 memset(filter, 0xff, sizeof(filter));
793b883e 2673 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2674 reg &= ~GM_RXCR_MCF_ENA;
2675 else {
2676 int i;
2677 reg |= GM_RXCR_MCF_ENA;
2678
2679 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2680 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2681 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2682 }
2683 }
2684
cd28ab6a 2685 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2686 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2687 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2688 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2689 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2690 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2691 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2692 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2693
2694 gma_write16(hw, port, GM_RX_CTRL, reg);
2695}
2696
2697/* Can have one global because blinking is controlled by
2698 * ethtool and that is always under RTNL mutex
2699 */
91c86df5 2700static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2701{
793b883e
SH		 2702 u16 pg;
2703
793b883e
SH		 2704 switch (hw->chip_id) {
2705 case CHIP_ID_YUKON_XL:
2706 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2707 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2708 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2709 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2710 PHY_M_LEDC_INIT_CTRL(7) |
2711 PHY_M_LEDC_STA1_CTRL(7) |
2712 PHY_M_LEDC_STA0_CTRL(7))
2713 : 0);
2714
2715 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2716 break;
2717
2718 default:
2719 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2720 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2721 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2722 PHY_M_LED_MO_10(MO_LED_ON) |
2723 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2724 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2725 PHY_M_LED_MO_RX(MO_LED_ON)
2726 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2727 PHY_M_LED_MO_10(MO_LED_OFF) |
2728 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2729 PHY_M_LED_MO_1000(MO_LED_OFF) |
2730 PHY_M_LED_MO_RX(MO_LED_OFF));
2731
793b883e 2732 }
cd28ab6a
SH		 2733}
2734
2735/* blink LED's for finding board */
2736static int sky2_phys_id(struct net_device *dev, u32 data)
2737{
2738 struct sky2_port *sky2 = netdev_priv(dev);
2739 struct sky2_hw *hw = sky2->hw;
2740 unsigned port = sky2->port;
793b883e 2741 u16 ledctrl, ledover = 0;
cd28ab6a 2742 long ms;
91c86df5 2743 int interrupted;
cd28ab6a
SH		 2744 int onoff = 1;
2745
793b883e 2746 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2747 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2748 else
2749 ms = data * 1000;
2750
2751 /* save initial values */
e07b1aa8 2752 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2753 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2754 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2755 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2756 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2757 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2758 } else {
2759 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2760 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2761 }
cd28ab6a 2762
91c86df5
SH		 2763 interrupted = 0;
2764 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2765 sky2_led(hw, port, onoff);
2766 onoff = !onoff;
2767
e07b1aa8 2768 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2769 interrupted = msleep_interruptible(250);
e07b1aa8 2770 spin_lock_bh(&sky2->phy_lock);
91c86df5 2771
cd28ab6a
SH		 2772 ms -= 250;
2773 }
2774
2775 /* resume regularly scheduled programming */
793b883e
SH		 2776 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2777 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2778 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2779 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2780 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2781 } else {
2782 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2783 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2784 }
e07b1aa8 2785 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2786
2787 return 0;
2788}
2789
2790static void sky2_get_pauseparam(struct net_device *dev,
2791 struct ethtool_pauseparam *ecmd)
2792{
2793 struct sky2_port *sky2 = netdev_priv(dev);
2794
2795 ecmd->tx_pause = sky2->tx_pause;
2796 ecmd->rx_pause = sky2->rx_pause;
2797 ecmd->autoneg = sky2->autoneg;
2798}
2799
2800static int sky2_set_pauseparam(struct net_device *dev,
2801 struct ethtool_pauseparam *ecmd)
2802{
2803 struct sky2_port *sky2 = netdev_priv(dev);
2804 int err = 0;
2805
2806 sky2->autoneg = ecmd->autoneg;
2807 sky2->tx_pause = ecmd->tx_pause != 0;
2808 sky2->rx_pause = ecmd->rx_pause != 0;
2809
1b537565 2810 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2811
2812 return err;
2813}
2814
fb17358f
SH		 2815static int sky2_get_coalesce(struct net_device *dev,
2816 struct ethtool_coalesce *ecmd)
2817{
2818 struct sky2_port *sky2 = netdev_priv(dev);
2819 struct sky2_hw *hw = sky2->hw;
2820
2821 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2822 ecmd->tx_coalesce_usecs = 0;
2823 else {
2824 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2825 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2826 }
2827 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2828
2829 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2830 ecmd->rx_coalesce_usecs = 0;
2831 else {
2832 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2833 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2834 }
2835 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2836
2837 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2838 ecmd->rx_coalesce_usecs_irq = 0;
2839 else {
2840 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2841 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2842 }
2843
2844 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2845
2846 return 0;
2847}
2848
2849/* Note: this affect both ports */
2850static int sky2_set_coalesce(struct net_device *dev,
2851 struct ethtool_coalesce *ecmd)
2852{
2853 struct sky2_port *sky2 = netdev_priv(dev);
2854 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2855 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2856
77b3d6a2
SH		 2857 if (ecmd->tx_coalesce_usecs > tmax ||
2858 ecmd->rx_coalesce_usecs > tmax ||
2859 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2860 return -EINVAL;
2861
ff81fbbe 2862 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2863 return -EINVAL;
ff81fbbe 2864 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2865 return -EINVAL;
ff81fbbe 2866 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2867 return -EINVAL;
2868
2869 if (ecmd->tx_coalesce_usecs == 0)
2870 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2871 else {
2872 sky2_write32(hw, STAT_TX_TIMER_INI,
2873 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2874 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2875 }
2876 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2877
2878 if (ecmd->rx_coalesce_usecs == 0)
2879 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2880 else {
2881 sky2_write32(hw, STAT_LEV_TIMER_INI,
2882 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2883 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2884 }
2885 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2886
2887 if (ecmd->rx_coalesce_usecs_irq == 0)
2888 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2889 else {
d28d4870 2890 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2891 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2892 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2893 }
2894 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2895 return 0;
2896}
2897
793b883e
SH		 2898static void sky2_get_ringparam(struct net_device *dev,
2899 struct ethtool_ringparam *ering)
2900{
2901 struct sky2_port *sky2 = netdev_priv(dev);
2902
2903 ering->rx_max_pending = RX_MAX_PENDING;
2904 ering->rx_mini_max_pending = 0;
2905 ering->rx_jumbo_max_pending = 0;
2906 ering->tx_max_pending = TX_RING_SIZE - 1;
2907
2908 ering->rx_pending = sky2->rx_pending;
2909 ering->rx_mini_pending = 0;
2910 ering->rx_jumbo_pending = 0;
2911 ering->tx_pending = sky2->tx_pending;
2912}
2913
2914static int sky2_set_ringparam(struct net_device *dev,
2915 struct ethtool_ringparam *ering)
2916{
2917 struct sky2_port *sky2 = netdev_priv(dev);
2918 int err = 0;
2919
2920 if (ering->rx_pending > RX_MAX_PENDING ||
2921 ering->rx_pending < 8 ||
2922 ering->tx_pending < MAX_SKB_TX_LE ||
2923 ering->tx_pending > TX_RING_SIZE - 1)
2924 return -EINVAL;
2925
2926 if (netif_running(dev))
2927 sky2_down(dev);
2928
2929 sky2->rx_pending = ering->rx_pending;
2930 sky2->tx_pending = ering->tx_pending;
2931
1b537565 2932 if (netif_running(dev)) {
793b883e 2933 err = sky2_up(dev);
1b537565
SH		 2934 if (err)
2935 dev_close(dev);
6ed995bb
SH		 2936 else
2937 sky2_set_multicast(dev);
1b537565 2938 }
793b883e
SH		 2939
2940 return err;
2941}
2942
793b883e
SH		 2943static int sky2_get_regs_len(struct net_device *dev)
2944{
6e4cbb34 2945 return 0x4000;
793b883e
SH		 2946}
2947
2948/*
2949 * Returns copy of control register region
6e4cbb34 2950 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2951 */
2952static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2953 void *p)
2954{
2955 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2956 const void __iomem *io = sky2->hw->regs;
793b883e 2957
6e4cbb34 2958 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2959 regs->version = 1;
6e4cbb34 2960 memset(p, 0, regs->len);
793b883e 2961
6e4cbb34
SH		 2962 memcpy_fromio(p, io, B3_RAM_ADDR);
2963
2964 memcpy_fromio(p + B3_RI_WTO_R1,
2965 io + B3_RI_WTO_R1,
2966 regs->len - B3_RI_WTO_R1);
793b883e 2967}
cd28ab6a
SH		 2968
2969static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2970 .get_settings = sky2_get_settings,
2971 .set_settings = sky2_set_settings,
2972 .get_drvinfo = sky2_get_drvinfo,
2973 .get_msglevel = sky2_get_msglevel,
2974 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2975 .nway_reset = sky2_nway_reset,
793b883e
SH		 2976 .get_regs_len = sky2_get_regs_len,
2977 .get_regs = sky2_get_regs,
2978 .get_link = ethtool_op_get_link,
2979 .get_sg = ethtool_op_get_sg,
2980 .set_sg = ethtool_op_set_sg,
2981 .get_tx_csum = ethtool_op_get_tx_csum,
2982 .set_tx_csum = ethtool_op_set_tx_csum,
2983 .get_tso = ethtool_op_get_tso,
2984 .set_tso = ethtool_op_set_tso,
2985 .get_rx_csum = sky2_get_rx_csum,
2986 .set_rx_csum = sky2_set_rx_csum,
2987 .get_strings = sky2_get_strings,
fb17358f
SH		 2988 .get_coalesce = sky2_get_coalesce,
2989 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 2990 .get_ringparam = sky2_get_ringparam,
2991 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2992 .get_pauseparam = sky2_get_pauseparam,
2993 .set_pauseparam = sky2_set_pauseparam,
793b883e 2994 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2995 .get_stats_count = sky2_get_stats_count,
2996 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2997 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2998};
2999
3000/* Initialize network device */
3001static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3002 unsigned port, int highmem)
3003{
3004 struct sky2_port *sky2;
3005 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3006
3007 if (!dev) {
3008 printk(KERN_ERR "sky2 etherdev alloc failed");
3009 return NULL;
3010 }
3011
3012 SET_MODULE_OWNER(dev);
3013 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3014 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3015 dev->open = sky2_up;
3016 dev->stop = sky2_down;
ef743d33 3017 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3018 dev->hard_start_xmit = sky2_xmit_frame;
3019 dev->get_stats = sky2_get_stats;
3020 dev->set_multicast_list = sky2_set_multicast;
3021 dev->set_mac_address = sky2_set_mac_address;
3022 dev->change_mtu = sky2_change_mtu;
3023 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3024 dev->tx_timeout = sky2_tx_timeout;
3025 dev->watchdog_timeo = TX_WATCHDOG;
3026 if (port == 0)
3027 dev->poll = sky2_poll;
3028 dev->weight = NAPI_WEIGHT;
3029#ifdef CONFIG_NET_POLL_CONTROLLER
3030 dev->poll_controller = sky2_netpoll;
3031#endif
cd28ab6a
SH		 3032
3033 sky2 = netdev_priv(dev);
3034 sky2->netdev = dev;
3035 sky2->hw = hw;
3036 sky2->msg_enable = netif_msg_init(debug, default_msg);
3037
3038 spin_lock_init(&sky2->tx_lock);
3039 /* Auto speed and flow control */
3040 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3041 sky2->tx_pause = 1;
cd28ab6a
SH		 3042 sky2->rx_pause = 1;
3043 sky2->duplex = -1;
3044 sky2->speed = -1;
3045 sky2->advertising = sky2_supported_modes(hw);
75d070c5 3046
d89e1343 3047 /* Receive checksum disabled for Yukon XL
75d070c5
SH		 3048 * because of observed problems with incorrect
3049 * values when multiple packets are received in one interrupt
3050 */
3051 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3052
e07b1aa8 3053 spin_lock_init(&sky2->phy_lock);
793b883e 3054 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3055 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3056 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3057
3058 hw->dev[port] = dev;
3059
3060 sky2->port = port;
3061
5a5b1ea0 3062 dev->features |= NETIF_F_LLTX;
3063 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3064 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3065 if (highmem)
3066 dev->features |= NETIF_F_HIGHDMA;
793b883e 3067 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3068
d1f13708 3069#ifdef SKY2_VLAN_TAG_USED
3070 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3071 dev->vlan_rx_register = sky2_vlan_rx_register;
3072 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3073#endif
3074
cd28ab6a 3075 /* read the mac address */
793b883e 3076 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3077 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3078
3079 /* device is off until link detection */
3080 netif_carrier_off(dev);
3081 netif_stop_queue(dev);
3082
3083 return dev;
3084}
3085
28bd181a 3086static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3087{
3088 const struct sky2_port *sky2 = netdev_priv(dev);
3089
3090 if (netif_msg_probe(sky2))
3091 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3092 dev->name,
3093 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3094 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3095}
3096
fb2690a9
SH		 3097/* Handle software interrupt used during MSI test */
3098static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3099 struct pt_regs *regs)
3100{
3101 struct sky2_hw *hw = dev_id;
3102 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3103
3104 if (status == 0)
3105 return IRQ_NONE;
3106
3107 if (status & Y2_IS_IRQ_SW) {
3108 hw->msi_detected = 1;
3109 wake_up(&hw->msi_wait);
3110 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3111 }
3112 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3113
3114 return IRQ_HANDLED;
3115}
3116
3117/* Test interrupt path by forcing a a software IRQ */
3118static int __devinit sky2_test_msi(struct sky2_hw *hw)
3119{
3120 struct pci_dev *pdev = hw->pdev;
3121 int err;
3122
3123 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3124
3125 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3126 if (err) {
3127 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3128 pci_name(pdev), pdev->irq);
3129 return err;
3130 }
3131
3132 init_waitqueue_head (&hw->msi_wait);
3133
3134 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3135 wmb();
3136
3137 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3138
3139 if (!hw->msi_detected) {
3140 /* MSI test failed, go back to INTx mode */
3141 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3142 "switching to INTx mode. Please report this failure to "
3143 "the PCI maintainer and include system chipset information.\n",
3144 pci_name(pdev));
3145
3146 err = -EOPNOTSUPP;
3147 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3148 }
3149
3150 sky2_write32(hw, B0_IMSK, 0);
3151
3152 free_irq(pdev->irq, hw);
3153
3154 return err;
3155}
3156
cd28ab6a
SH		 3157static int __devinit sky2_probe(struct pci_dev *pdev,
3158 const struct pci_device_id *ent)
3159{
793b883e 3160 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3161 struct sky2_hw *hw;
5afa0a9c 3162 int err, pm_cap, using_dac = 0;
cd28ab6a 3163
793b883e
SH		 3164 err = pci_enable_device(pdev);
3165 if (err) {
cd28ab6a
SH		 3166 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3167 pci_name(pdev));
3168 goto err_out;
3169 }
3170
793b883e
SH		 3171 err = pci_request_regions(pdev, DRV_NAME);
3172 if (err) {
cd28ab6a
SH		 3173 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3174 pci_name(pdev));
793b883e 3175 goto err_out;
cd28ab6a
SH		 3176 }
3177
3178 pci_set_master(pdev);
3179
5afa0a9c 3180 /* Find power-management capability. */
3181 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3182 if (pm_cap == 0) {
3183 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3184 "aborting.\n");
3185 err = -EIO;
3186 goto err_out_free_regions;
3187 }
3188
d1f3d4dd
SH		 3189 if (sizeof(dma_addr_t) > sizeof(u32) &&
3190 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3191 using_dac = 1;
3192 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3193 if (err < 0) {
3194 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3195 "for consistent allocations\n", pci_name(pdev));
3196 goto err_out_free_regions;
3197 }
cd28ab6a 3198
d1f3d4dd 3199 } else {
cd28ab6a
SH		 3200 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3201 if (err) {
3202 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3203 pci_name(pdev));
3204 goto err_out_free_regions;
3205 }
3206 }
d1f3d4dd 3207
cd28ab6a 3208 err = -ENOMEM;
6aad85d6 3209 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3210 if (!hw) {
3211 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3212 pci_name(pdev));
3213 goto err_out_free_regions;
3214 }
3215
cd28ab6a 3216 hw->pdev = pdev;
cd28ab6a
SH		 3217
3218 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3219 if (!hw->regs) {
3220 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3221 pci_name(pdev));
3222 goto err_out_free_hw;
3223 }
5afa0a9c 3224 hw->pm_cap = pm_cap;
cd28ab6a 3225
56a645cc
SH		 3226#ifdef __BIG_ENDIAN
3227 /* byte swap descriptors in hardware */
3228 {
3229 u32 reg;
3230
3231 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3232 reg |= PCI_REV_DESC;
3233 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3234 }
3235#endif
3236
08c06d8a
SH		 3237 /* ring for status responses */
3238 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3239 &hw->st_dma);
3240 if (!hw->st_le)
3241 goto err_out_iounmap;
3242
cd28ab6a
SH		 3243 err = sky2_reset(hw);
3244 if (err)
793b883e 3245 goto err_out_iounmap;
cd28ab6a 3246
5f4f9dc1 3247 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3248 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3249 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3250 hw->chip_id, hw->chip_rev);
cd28ab6a 3251
793b883e
SH		 3252 dev = sky2_init_netdev(hw, 0, using_dac);
3253 if (!dev)
cd28ab6a
SH		 3254 goto err_out_free_pci;
3255
793b883e
SH		 3256 err = register_netdev(dev);
3257 if (err) {
cd28ab6a
SH		 3258 printk(KERN_ERR PFX "%s: cannot register net device\n",
3259 pci_name(pdev));
3260 goto err_out_free_netdev;
3261 }
3262
3263 sky2_show_addr(dev);
3264
3265 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3266 if (register_netdev(dev1) == 0)
3267 sky2_show_addr(dev1);
3268 else {
3269 /* Failure to register second port need not be fatal */
793b883e
SH		 3270 printk(KERN_WARNING PFX
3271 "register of second port failed\n");
cd28ab6a
SH		 3272 hw->dev[1] = NULL;
3273 free_netdev(dev1);
3274 }
3275 }
3276
fb2690a9
SH		 3277 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3278 err = sky2_test_msi(hw);
3279 if (err == -EOPNOTSUPP)
3280 pci_disable_msi(pdev);
3281 else if (err)
3282 goto err_out_unregister;
3283 }
3284
3285 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
793b883e
SH		 3286 if (err) {
3287 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3288 pci_name(pdev), pdev->irq);
3289 goto err_out_unregister;
3290 }
3291
e07b1aa8 3292 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3293
01bd7564
SH		 3294 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3295 if (idle_timeout > 0)
3296 mod_timer(&hw->idle_timer,
3297 jiffies + msecs_to_jiffies(idle_timeout));
d27ed387 3298
793b883e
SH		 3299 pci_set_drvdata(pdev, hw);
3300
cd28ab6a
SH		 3301 return 0;
3302
793b883e 3303err_out_unregister:
fb2690a9 3304 pci_disable_msi(pdev);
793b883e
SH		 3305 if (dev1) {
3306 unregister_netdev(dev1);
3307 free_netdev(dev1);
3308 }
3309 unregister_netdev(dev);
cd28ab6a
SH		 3310err_out_free_netdev:
3311 free_netdev(dev);
cd28ab6a 3312err_out_free_pci:
793b883e 3313 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3314 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3315err_out_iounmap:
3316 iounmap(hw->regs);
3317err_out_free_hw:
3318 kfree(hw);
3319err_out_free_regions:
3320 pci_release_regions(pdev);
cd28ab6a 3321 pci_disable_device(pdev);
cd28ab6a
SH		 3322err_out:
3323 return err;
3324}
3325
3326static void __devexit sky2_remove(struct pci_dev *pdev)
3327{
793b883e 3328 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3329 struct net_device *dev0, *dev1;
3330
793b883e 3331 if (!hw)
cd28ab6a
SH		 3332 return;
3333
d27ed387
SH		 3334 del_timer_sync(&hw->idle_timer);
3335
3336 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 3337 dev0 = hw->dev[0];
793b883e
SH		 3338 dev1 = hw->dev[1];
3339 if (dev1)
3340 unregister_netdev(dev1);
cd28ab6a
SH		 3341 unregister_netdev(dev0);
3342
5afa0a9c 3343 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3344 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3345 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3346 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3347
3348 free_irq(pdev->irq, hw);
fb2690a9 3349 pci_disable_msi(pdev);
793b883e 3350 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3351 pci_release_regions(pdev);
3352 pci_disable_device(pdev);
793b883e 3353
cd28ab6a
SH		 3354 if (dev1)
3355 free_netdev(dev1);
3356 free_netdev(dev0);
3357 iounmap(hw->regs);
3358 kfree(hw);
5afa0a9c 3359
cd28ab6a
SH		 3360 pci_set_drvdata(pdev, NULL);
3361}
3362
3363#ifdef CONFIG_PM
3364static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3365{
793b883e 3366 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3367 int i;
cd28ab6a
SH		 3368
3369 for (i = 0; i < 2; i++) {
3370 struct net_device *dev = hw->dev[i];
3371
3372 if (dev) {
5afa0a9c 3373 if (!netif_running(dev))
3374 continue;
3375
3376 sky2_down(dev);
cd28ab6a 3377 netif_device_detach(dev);
cd28ab6a
SH		 3378 }
3379 }
3380
5afa0a9c 3381 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3382}
3383
3384static int sky2_resume(struct pci_dev *pdev)
3385{
793b883e 3386 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3387 int i, err;
cd28ab6a 3388
cd28ab6a
SH		 3389 pci_restore_state(pdev);
3390 pci_enable_wake(pdev, PCI_D0, 0);
08c06d8a
SH		 3391 err = sky2_set_power_state(hw, PCI_D0);
3392 if (err)
3393 goto out;
cd28ab6a 3394
08c06d8a
SH		 3395 err = sky2_reset(hw);
3396 if (err)
3397 goto out;
cd28ab6a
SH		 3398
3399 for (i = 0; i < 2; i++) {
3400 struct net_device *dev = hw->dev[i];
08c06d8a
SH		 3401 if (dev && netif_running(dev)) {
3402 netif_device_attach(dev);
3403 err = sky2_up(dev);
3404 if (err) {
3405 printk(KERN_ERR PFX "%s: could not up: %d\n",
3406 dev->name, err);
3407 dev_close(dev);
3408 break;
5afa0a9c 3409 }
cd28ab6a
SH		 3410 }
3411 }
08c06d8a
SH		 3412out:
3413 return err;
cd28ab6a
SH		 3414}
3415#endif
3416
3417static struct pci_driver sky2_driver = {
793b883e
SH		 3418 .name = DRV_NAME,
3419 .id_table = sky2_id_table,
3420 .probe = sky2_probe,
3421 .remove = __devexit_p(sky2_remove),
cd28ab6a 3422#ifdef CONFIG_PM
793b883e
SH		 3423 .suspend = sky2_suspend,
3424 .resume = sky2_resume,
cd28ab6a
SH		 3425#endif
3426};
3427
3428static int __init sky2_init_module(void)
3429{
50241c4c 3430 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3431}
3432
3433static void __exit sky2_cleanup_module(void)
3434{
3435 pci_unregister_driver(&sky2_driver);
3436}
3437
3438module_init(sky2_init_module);
3439module_exit(sky2_cleanup_module);
3440
3441MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3442MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3443MODULE_LICENSE("GPL");
5f4f9dc1 3444MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)