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regulator: Provide optional dummy regulator for consumers
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
c9bdd4b5 36#include <net/ip.h>
cd28ab6a
SH		 37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
3cf26753 43#include <linux/debugfs.h>
ef743d33 44#include <linux/mii.h>
cd28ab6a
SH		 45
46#include <asm/irq.h>
47
d1f13708 48#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49#define SKY2_VLAN_TAG_USED 1
50#endif
51
cd28ab6a
SH		 52#include "sky2.h"
53
54#define DRV_NAME "sky2"
cfc0861b 55#define DRV_VERSION "1.27"
cd28ab6a
SH		 56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 67
ee5f68fe 68/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 69 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
70#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 71#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 72#define TX_MAX_PENDING 4096
73#define TX_DEF_PENDING 127
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 77#define TX_WATCHDOG (5 * HZ)
78#define NAPI_WEIGHT 64
79#define PHY_RETRIES 1000
80
f4331a6d
SH		 81#define SKY2_EEPROM_MAGIC 0x9955aabb
82
83
cb5d9547
SH		 84#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85
cd28ab6a 86static const u32 default_msg =
793b883e
SH		 87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 90
793b883e 91static int debug = -1; /* defaults above */
cd28ab6a
SH		 92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
14d0263f 95static int copybreak __read_mostly = 128;
bdb5c58e
SH		 96module_param(copybreak, int, 0);
97MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98
fb2690a9
SH		 99static int disable_msi = 0;
100module_param(disable_msi, int, 0);
101MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102
e6cac9ba 103static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 145 { 0 }
146};
793b883e 147
cd28ab6a
SH		 148MODULE_DEVICE_TABLE(pci, sky2_id_table);
149
150/* Avoid conditionals by using array */
151static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
152static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 153static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 154
d1b139c0
SH		 155static void sky2_set_multicast(struct net_device *dev);
156
af043aa5 157/* Access to PHY via serial interconnect */
ef743d33 158static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 159{
160 int i;
161
162 gma_write16(hw, port, GM_SMI_DATA, val);
163 gma_write16(hw, port, GM_SMI_CTRL,
164 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
165
166 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 167 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
168 if (ctrl == 0xffff)
169 goto io_error;
170
171 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 172 return 0;
af043aa5
SH		 173
174 udelay(10);
cd28ab6a 175 }
ef743d33 176
af043aa5 177 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 178 return -ETIMEDOUT;
af043aa5
SH		 179
180io_error:
181 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
182 return -EIO;
cd28ab6a
SH		 183}
184
ef743d33 185static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 186{
187 int i;
188
793b883e 189 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 190 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
191
192 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 193 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
194 if (ctrl == 0xffff)
195 goto io_error;
196
197 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 198 *val = gma_read16(hw, port, GM_SMI_DATA);
199 return 0;
200 }
201
af043aa5 202 udelay(10);
cd28ab6a
SH		 203 }
204
af043aa5 205 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 206 return -ETIMEDOUT;
af043aa5
SH		 207io_error:
208 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
209 return -EIO;
ef743d33 210}
211
af043aa5 212static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 213{
214 u16 v;
af043aa5 215 __gm_phy_read(hw, port, reg, &v);
ef743d33 216 return v;
cd28ab6a
SH		 217}
218
5afa0a9c 219
ae306cca
SH		 220static void sky2_power_on(struct sky2_hw *hw)
221{
222 /* switch power to VCC (WA for VAUX problem) */
223 sky2_write8(hw, B0_POWER_CTRL,
224 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 225
ae306cca
SH		 226 /* disable Core Clock Division, */
227 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 228
ae306cca
SH		 229 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
230 /* enable bits are inverted */
231 sky2_write8(hw, B2_Y2_CLK_GATE,
232 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
233 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
234 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235 else
236 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 237
ea76e635 238 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 239 u32 reg;
5afa0a9c 240
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 244 /* set all bits to 0 except bits 15..12 and 8 */
245 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 247
b32f40c4 248 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 249 /* set all bits to 0 except bits 28 & 27 */
250 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 251 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 252
b32f40c4 253 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 254
5f8ae5c5 255 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
256
8f70920f
SH		 257 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
258 reg = sky2_read32(hw, B2_GP_IO);
259 reg |= GLB_GPIO_STAT_RACE_DIS;
260 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 261
262 sky2_read32(hw, B2_GP_IO);
5afa0a9c 263 }
10547ae2
SH		 264
265 /* Turn on "driver loaded" LED */
266 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 267}
5afa0a9c 268
ae306cca
SH		 269static void sky2_power_aux(struct sky2_hw *hw)
270{
271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 else
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279
c23ddf8f
SH		 280 /* switch power to VAUX if supported and PME from D3cold */
281 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
282 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 283 sky2_write8(hw, B0_POWER_CTRL,
284 (PC_VAUX_ENA | PC_VCC_ENA |
285 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 286
287 /* turn off "driver loaded LED" */
288 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c 289}
290
d3bcfbeb 291static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 292{
293 u16 reg;
294
295 /* disable all GMAC IRQ's */
296 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 297
cd28ab6a
SH		 298 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
299 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
301 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
302
303 reg = gma_read16(hw, port, GM_RX_CTRL);
304 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
305 gma_write16(hw, port, GM_RX_CTRL, reg);
306}
307
16ad91e1
SH		 308/* flow control to advertise bits */
309static const u16 copper_fc_adv[] = {
310 [FC_NONE] = 0,
311 [FC_TX] = PHY_M_AN_ASP,
312 [FC_RX] = PHY_M_AN_PC,
313 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
314};
315
316/* flow control to advertise bits when using 1000BaseX */
317static const u16 fiber_fc_adv[] = {
df3fe1f3 318 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 319 [FC_TX] = PHY_M_P_ASYM_MD_X,
320 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 321 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 322};
323
324/* flow control to GMA disable bits */
325static const u16 gm_fc_disable[] = {
326 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
327 [FC_TX] = GM_GPCR_FC_RX_DIS,
328 [FC_RX] = GM_GPCR_FC_TX_DIS,
329 [FC_BOTH] = 0,
330};
331
332
cd28ab6a
SH		 333static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
334{
335 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 336 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 337
0ea065e5 338 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 339 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 340 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
341
342 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 343 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 344 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
345
53419c68 346 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 347 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 348 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 349 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
350 else
53419c68
SH		 351 /* set master & slave downshift counter to 1x */
352 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 353
354 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
355 }
356
357 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 358 if (sky2_is_copper(hw)) {
05745c4a 359 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 360 /* enable automatic crossover */
361 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 362
363 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
364 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
365 u16 spec;
366
367 /* Enable Class A driver for FE+ A0 */
368 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
369 spec |= PHY_M_FESC_SEL_CL_A;
370 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
371 }
cd28ab6a
SH		 372 } else {
373 /* disable energy detect */
374 ctrl &= ~PHY_M_PC_EN_DET_MSK;
375
376 /* enable automatic crossover */
377 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
378
53419c68 379 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 380 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
381 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 382 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 383 ctrl &= ~PHY_M_PC_DSC_MSK;
384 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
385 }
386 }
cd28ab6a
SH		 387 } else {
388 /* workaround for deviation #4.88 (CRC errors) */
389 /* disable Automatic Crossover */
390
391 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 392 }
cd28ab6a 393
b89165f2
SH		 394 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
395
396 /* special setup for PHY 88E1112 Fiber */
ea76e635 397 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 398 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 399
b89165f2
SH		 400 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
401 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
402 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
403 ctrl &= ~PHY_M_MAC_MD_MSK;
404 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
405 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
406
407 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 408 /* select page 1 to access Fiber registers */
409 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 410
411 /* for SFP-module set SIGDET polarity to low */
412 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
413 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 414 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 415 }
b89165f2
SH		 416
417 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 418 }
419
7800fddc 420 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 421 ct1000 = 0;
422 adv = PHY_AN_CSMA;
2eaba1a2 423 reg = 0;
cd28ab6a 424
0ea065e5 425 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 426 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 427 if (sky2->advertising & ADVERTISED_1000baseT_Full)
428 ct1000 |= PHY_M_1000C_AFD;
429 if (sky2->advertising & ADVERTISED_1000baseT_Half)
430 ct1000 |= PHY_M_1000C_AHD;
431 if (sky2->advertising & ADVERTISED_100baseT_Full)
432 adv |= PHY_M_AN_100_FD;
433 if (sky2->advertising & ADVERTISED_100baseT_Half)
434 adv |= PHY_M_AN_100_HD;
435 if (sky2->advertising & ADVERTISED_10baseT_Full)
436 adv |= PHY_M_AN_10_FD;
437 if (sky2->advertising & ADVERTISED_10baseT_Half)
438 adv |= PHY_M_AN_10_HD;
709c6e7b 439
b89165f2
SH		 440 } else { /* special defines for FIBER (88E1040S only) */
441 if (sky2->advertising & ADVERTISED_1000baseT_Full)
442 adv |= PHY_M_AN_1000X_AFD;
443 if (sky2->advertising & ADVERTISED_1000baseT_Half)
444 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 445 }
cd28ab6a
SH		 446
447 /* Restart Auto-negotiation */
448 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 } else {
450 /* forced speed/duplex settings */
451 ct1000 = PHY_M_1000C_MSE;
452
0ea065e5
SH		 453 /* Disable auto update for duplex flow control and duplex */
454 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 455
456 switch (sky2->speed) {
457 case SPEED_1000:
458 ctrl |= PHY_CT_SP1000;
2eaba1a2 459 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 460 break;
461 case SPEED_100:
462 ctrl |= PHY_CT_SP100;
2eaba1a2 463 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 464 break;
465 }
466
2eaba1a2
SH		 467 if (sky2->duplex == DUPLEX_FULL) {
468 reg |= GM_GPCR_DUP_FULL;
469 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 470 } else if (sky2->speed < SPEED_1000)
471 sky2->flow_mode = FC_NONE;
0ea065e5 472 }
2eaba1a2 473
0ea065e5
SH		 474 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
475 if (sky2_is_copper(hw))
476 adv |= copper_fc_adv[sky2->flow_mode];
477 else
478 adv |= fiber_fc_adv[sky2->flow_mode];
479 } else {
480 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 481 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 482
483 /* Forward pause packets to GMAC? */
16ad91e1 484 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 485 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
486 else
487 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 488 }
489
2eaba1a2
SH		 490 gma_write16(hw, port, GM_GP_CTRL, reg);
491
05745c4a 492 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 493 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
494
495 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
496 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
497
498 /* Setup Phy LED's */
499 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
500 ledover = 0;
501
502 switch (hw->chip_id) {
503 case CHIP_ID_YUKON_FE:
504 /* on 88E3082 these bits are at 11..9 (shifted left) */
505 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
506
507 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
508
509 /* delete ACT LED control bits */
510 ctrl &= ~PHY_M_FELP_LED1_MSK;
511 /* change ACT LED control to blink mode */
512 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
513 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
514 break;
515
05745c4a
SH		 516 case CHIP_ID_YUKON_FE_P:
517 /* Enable Link Partner Next Page */
518 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
519 ctrl |= PHY_M_PC_ENA_LIP_NP;
520
521 /* disable Energy Detect and enable scrambler */
522 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
523 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
524
525 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
526 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
527 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
528 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
529
530 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
531 break;
532
cd28ab6a 533 case CHIP_ID_YUKON_XL:
793b883e 534 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 535
536 /* select page 3 to access LED control register */
537 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
538
539 /* set LED Function Control register */
ed6d32c7
SH		 540 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
541 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
542 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
543 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
544 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 545
546 /* set Polarity Control register */
547 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 548 (PHY_M_POLC_LS1_P_MIX(4) |
549 PHY_M_POLC_IS0_P_MIX(4) |
550 PHY_M_POLC_LOS_CTRL(2) |
551 PHY_M_POLC_INIT_CTRL(2) |
552 PHY_M_POLC_STA1_CTRL(2) |
553 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 554
555 /* restore page register */
793b883e 556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 557 break;
93745494 558
ed6d32c7 559 case CHIP_ID_YUKON_EC_U:
93745494 560 case CHIP_ID_YUKON_EX:
ed4d4161 561 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 562 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
563
564 /* select page 3 to access LED control register */
565 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
566
567 /* set LED Function Control register */
568 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
569 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
570 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
571 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
572 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
573
574 /* set Blink Rate in LED Timer Control Register */
575 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
576 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
577 /* restore page register */
578 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
579 break;
cd28ab6a
SH		 580
581 default:
582 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
583 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 584
cd28ab6a 585 /* turn off the Rx LED (LED_RX) */
a84d0a3d 586 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 587 }
588
0ce8b98d 589 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 590 /* apply fixes in PHY AFE */
ed6d32c7
SH		 591 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
592
977bdf06 593 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 594 gm_phy_write(hw, port, 0x18, 0xaa99);
595 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 596
0ce8b98d
SH		 597 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
598 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
599 gm_phy_write(hw, port, 0x18, 0xa204);
600 gm_phy_write(hw, port, 0x17, 0x2002);
601 }
977bdf06
SH		 602
603 /* set page register to 0 */
9467a8fc 604 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 605 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
606 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
607 /* apply workaround for integrated resistors calibration */
608 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
609 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 610 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
611 /* apply fixes in PHY AFE */
612 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
613
614 /* apply RDAC termination workaround */
615 gm_phy_write(hw, port, 24, 0x2800);
616 gm_phy_write(hw, port, 23, 0x2001);
617
618 /* set page register back to 0 */
619 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 620 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
621 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 622 /* no effect on Yukon-XL */
977bdf06 623 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 624
8e95a202
JP		 625 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
626 sky2->speed == SPEED_100) {
977bdf06 627 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 628 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 629 }
cd28ab6a 630
977bdf06
SH		 631 if (ledover)
632 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
633
634 }
2eaba1a2 635
d571b694 636 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 637 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 638 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
639 else
640 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
641}
642
b96936da
SH		 643static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
644static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
645
646static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 647{
648 u32 reg1;
d3bcfbeb 649
a40ccc68 650 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 651 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 652 reg1 &= ~phy_power[port];
d3bcfbeb 653
b96936da 654 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 655 reg1 |= coma_mode[port];
656
b32f40c4 657 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 658 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 659 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 660
661 if (hw->chip_id == CHIP_ID_YUKON_FE)
662 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
663 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
664 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 665}
167f53d0 666
b96936da
SH		 667static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
668{
669 u32 reg1;
db99b988
SH		 670 u16 ctrl;
671
672 /* release GPHY Control reset */
673 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
674
675 /* release GMAC reset */
676 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
677
678 if (hw->flags & SKY2_HW_NEWER_PHY) {
679 /* select page 2 to access MAC control register */
680 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
681
682 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
683 /* allow GMII Power Down */
684 ctrl &= ~PHY_M_MAC_GMIF_PUP;
685 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
686
687 /* set page register back to 0 */
688 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
689 }
690
691 /* setup General Purpose Control Register */
692 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 693 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
694 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
695 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 696
697 if (hw->chip_id != CHIP_ID_YUKON_EC) {
698 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 699 /* select page 2 to access MAC control register */
700 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 701
e484d5f5 702 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 703 /* enable Power Down */
704 ctrl |= PHY_M_PC_POW_D_ENA;
705 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 706
707 /* set page register back to 0 */
708 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 709 }
710
711 /* set IEEE compatible Power Down Mode (dev. #4.99) */
712 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
713 }
b96936da 714
a40ccc68 715 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 716 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 717 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 718 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 719 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 720}
721
1b537565
SH		 722/* Force a renegotiation */
723static void sky2_phy_reinit(struct sky2_port *sky2)
724{
e07b1aa8 725 spin_lock_bh(&sky2->phy_lock);
1b537565 726 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 727 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 728}
729
e3173832
SH		 730/* Put device in state to listen for Wake On Lan */
731static void sky2_wol_init(struct sky2_port *sky2)
732{
733 struct sky2_hw *hw = sky2->hw;
734 unsigned port = sky2->port;
735 enum flow_control save_mode;
736 u16 ctrl;
e3173832
SH		 737
738 /* Bring hardware out of reset */
739 sky2_write16(hw, B0_CTST, CS_RST_CLR);
740 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
741
742 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
743 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
744
745 /* Force to 10/100
746 * sky2_reset will re-enable on resume
747 */
748 save_mode = sky2->flow_mode;
749 ctrl = sky2->advertising;
750
751 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
752 sky2->flow_mode = FC_NONE;
b96936da
SH		 753
754 spin_lock_bh(&sky2->phy_lock);
755 sky2_phy_power_up(hw, port);
756 sky2_phy_init(hw, port);
757 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 758
759 sky2->flow_mode = save_mode;
760 sky2->advertising = ctrl;
761
762 /* Set GMAC to no flow control and auto update for speed/duplex */
763 gma_write16(hw, port, GM_GP_CTRL,
764 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
765 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
766
767 /* Set WOL address */
768 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
769 sky2->netdev->dev_addr, ETH_ALEN);
770
771 /* Turn on appropriate WOL control bits */
772 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
773 ctrl = 0;
774 if (sky2->wol & WAKE_PHY)
775 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
776 else
777 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
778
779 if (sky2->wol & WAKE_MAGIC)
780 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
781 else
a419aef8 782 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 783
784 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
785 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
786
5f8ae5c5 787 /* Disable PiG firmware */
788 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
789
e3173832
SH		 790 /* block receiver */
791 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 792}
793
69161611
SH		 794static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
795{
05745c4a
SH		 796 struct net_device *dev = hw->dev[port];
797
ed4d4161
SH		 798 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
799 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 800 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 801 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 802 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
803 } else if (dev->mtu > ETH_DATA_LEN) {
804 /* set Tx GMAC FIFO Almost Empty Threshold */
805 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
806 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 807
44dde56d 808 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
809 } else
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 811}
812
cd28ab6a
SH		 813static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
814{
815 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
816 u16 reg;
25cccecc 817 u32 rx_reg;
cd28ab6a
SH		 818 int i;
819 const u8 *addr = hw->dev[port]->dev_addr;
820
f350339c
SH		 821 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
822 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 823
824 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
825
793b883e 826 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 827 /* WA DEV_472 -- looks like crossed wires on port 2 */
828 /* clear GMAC 1 Control reset */
829 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
830 do {
831 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
832 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
833 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
834 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
835 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
836 }
837
793b883e 838 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 839
2eaba1a2
SH		 840 /* Enable Transmit FIFO Underrun */
841 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
842
e07b1aa8 843 spin_lock_bh(&sky2->phy_lock);
b96936da 844 sky2_phy_power_up(hw, port);
cd28ab6a 845 sky2_phy_init(hw, port);
e07b1aa8 846 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 847
848 /* MIB clear */
849 reg = gma_read16(hw, port, GM_PHY_ADDR);
850 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
851
43f2f104
SH		 852 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
853 gma_read16(hw, port, i);
cd28ab6a
SH		 854 gma_write16(hw, port, GM_PHY_ADDR, reg);
855
856 /* transmit control */
857 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
858
859 /* receive control reg: unicast + multicast + no FCS */
860 gma_write16(hw, port, GM_RX_CTRL,
793b883e 861 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 862
863 /* transmit flow control */
864 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
865
866 /* transmit parameter */
867 gma_write16(hw, port, GM_TX_PARAM,
868 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
869 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
870 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
871 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
872
873 /* serial mode register */
874 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 875 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 876
6b1a3aef 877 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 878 reg |= GM_SMOD_JUMBO_ENA;
879
880 gma_write16(hw, port, GM_SERIAL_MODE, reg);
881
cd28ab6a
SH		 882 /* virtual address for data */
883 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
884
793b883e
SH		 885 /* physical address: used for pause frames */
886 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
887
888 /* ignore counter overflows */
cd28ab6a
SH		 889 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
890 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
891 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
892
893 /* Configure Rx MAC FIFO */
894 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 895 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 896 if (hw->chip_id == CHIP_ID_YUKON_EX ||
897 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 898 rx_reg |= GMF_RX_OVER_ON;
69161611 899
25cccecc 900 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 901
798fdd07
SH		 902 if (hw->chip_id == CHIP_ID_YUKON_XL) {
903 /* Hardware errata - clear flush mask */
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
905 } else {
906 /* Flush Rx MAC FIFO on any flow control or error */
907 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
908 }
cd28ab6a 909
8df9a876 910 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 911 reg = RX_GMF_FL_THR_DEF + 1;
912 /* Another magic mystery workaround from sk98lin */
913 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
914 hw->chip_rev == CHIP_REV_YU_FE2_A0)
915 reg = 0x178;
916 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 917
918 /* Configure Tx MAC FIFO */
919 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
920 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 921
e0c28116 922 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 923 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 924 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 925 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
926 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 927 reg = 1568 / 8;
928 else
929 reg = 1024 / 8;
930 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
931 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 932
69161611 933 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 934 }
935
e970d1f8
SH		 936 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
937 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
938 /* disable dynamic watermark */
939 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
940 reg &= ~TX_DYN_WM_ENA;
941 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
942 }
cd28ab6a
SH		 943}
944
67712901
SH		 945/* Assign Ram Buffer allocation to queue */
946static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 947{
67712901
SH		 948 u32 end;
949
950 /* convert from K bytes to qwords used for hw register */
951 start *= 1024/8;
952 space *= 1024/8;
953 end = start + space - 1;
793b883e 954
cd28ab6a
SH		 955 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
956 sky2_write32(hw, RB_ADDR(q, RB_START), start);
957 sky2_write32(hw, RB_ADDR(q, RB_END), end);
958 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
959 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
960
961 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 962 u32 tp = space - space/4;
793b883e 963
1c28f6ba
SH		 964 /* On receive queue's set the thresholds
965 * give receiver priority when > 3/4 full
966 * send pause when down to 2K
967 */
968 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
969 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 970
1c28f6ba
SH		 971 tp = space - 2048/8;
972 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
973 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 974 } else {
975 /* Enable store & forward on Tx queue's because
976 * Tx FIFO is only 1K on Yukon
977 */
978 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
979 }
980
981 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 982 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 983}
984
cd28ab6a 985/* Setup Bus Memory Interface */
af4ed7e6 986static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 987{
988 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
989 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
990 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 991 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 992}
993
cd28ab6a
SH		 994/* Setup prefetch unit registers. This is the interface between
995 * hardware and driver list elements
996 */
8cc048e3 997static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 998 dma_addr_t addr, u32 last)
cd28ab6a 999{
cd28ab6a
SH		 1000 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1001 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1002 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1003 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1004 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1005 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1006
1007 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1008}
1009
9b289c33 1010static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1011{
9b289c33 1012 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1013
ee5f68fe 1014 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1015 le->ctrl = 0;
793b883e
SH		 1016 return le;
1017}
cd28ab6a 1018
88f5f0ca
SH		 1019static void tx_init(struct sky2_port *sky2)
1020{
1021 struct sky2_tx_le *le;
1022
1023 sky2->tx_prod = sky2->tx_cons = 0;
1024 sky2->tx_tcpsum = 0;
1025 sky2->tx_last_mss = 0;
1026
9b289c33 1027 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1028 le->addr = 0;
1029 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1030 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1031}
1032
290d4de5
SH		 1033/* Update chip's next pointer */
1034static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1035{
50432cb5 1036 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1037 wmb();
50432cb5
SH		 1038 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1039
1040 /* Synchronize I/O on since next processor may write to tail */
1041 mmiowb();
cd28ab6a
SH		 1042}
1043
793b883e 1044
cd28ab6a
SH		 1045static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1046{
1047 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1048 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1049 le->ctrl = 0;
cd28ab6a
SH		 1050 return le;
1051}
1052
39ef110b
MM		 1053static unsigned sky2_get_rx_threshold(struct sky2_port* sky2)
1054{
1055 unsigned size;
1056
1057 /* Space needed for frame data + headers rounded up */
1058 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1059
1060 /* Stopping point for hardware truncation */
1061 return (size - 8) / sizeof(u32);
1062}
1063
1064static unsigned sky2_get_rx_data_size(struct sky2_port* sky2)
1065{
1066 struct rx_ring_info *re;
1067 unsigned size;
1068
1069 /* Space needed for frame data + headers rounded up */
1070 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1071
1072 sky2->rx_nfrags = size >> PAGE_SHIFT;
1073 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1074
1075 /* Compute residue after pages */
1076 size -= sky2->rx_nfrags << PAGE_SHIFT;
1077
1078 /* Optimize to handle small packets and headers */
1079 if (size < copybreak)
1080 size = copybreak;
1081 if (size < ETH_HLEN)
1082 size = ETH_HLEN;
1083
1084 return size;
1085}
1086
14d0263f
SH		 1087/* Build description to hardware for one receive segment */
1088static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1089 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1090{
1091 struct sky2_rx_le *le;
1092
86c6887e 1093 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1094 le = sky2_next_rx(sky2);
86c6887e 1095 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1096 le->opcode = OP_ADDR64 | HW_OWNER;
1097 }
793b883e 1098
cd28ab6a 1099 le = sky2_next_rx(sky2);
d6e74b6b 1100 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1101 le->length = cpu_to_le16(len);
14d0263f 1102 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1103}
1104
14d0263f
SH		 1105/* Build description to hardware for one possibly fragmented skb */
1106static void sky2_rx_submit(struct sky2_port *sky2,
1107 const struct rx_ring_info *re)
1108{
1109 int i;
1110
1111 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1112
1113 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1114 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1115}
1116
1117
454e6cb6 1118static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1119 unsigned size)
1120{
1121 struct sk_buff *skb = re->skb;
1122 int i;
1123
1124 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1125 if (pci_dma_mapping_error(pdev, re->data_addr))
1126 goto mapping_error;
454e6cb6 1127
14d0263f
SH		 1128 pci_unmap_len_set(re, data_size, size);
1129
3fbd9187 1130 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1131 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1132
1133 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1134 frag->page_offset,
1135 frag->size,
14d0263f 1136 PCI_DMA_FROMDEVICE);
3fbd9187 1137
1138 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1139 goto map_page_error;
1140 }
454e6cb6 1141 return 0;
3fbd9187 1142
1143map_page_error:
1144 while (--i >= 0) {
1145 pci_unmap_page(pdev, re->frag_addr[i],
1146 skb_shinfo(skb)->frags[i].size,
1147 PCI_DMA_FROMDEVICE);
1148 }
1149
1150 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1151 PCI_DMA_FROMDEVICE);
1152
1153mapping_error:
1154 if (net_ratelimit())
1155 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1156 skb->dev->name);
1157 return -EIO;
14d0263f
SH		 1158}
1159
1160static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1161{
1162 struct sk_buff *skb = re->skb;
1163 int i;
1164
1165 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1166 PCI_DMA_FROMDEVICE);
1167
1168 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1169 pci_unmap_page(pdev, re->frag_addr[i],
1170 skb_shinfo(skb)->frags[i].size,
1171 PCI_DMA_FROMDEVICE);
1172}
793b883e 1173
cd28ab6a
SH		 1174/* Tell chip where to start receive checksum.
1175 * Actually has two checksums, but set both same to avoid possible byte
1176 * order problems.
1177 */
793b883e 1178static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1179{
ea76e635 1180 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1181
ea76e635
SH		 1182 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1183 le->ctrl = 0;
1184 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1185
ea76e635
SH		 1186 sky2_write32(sky2->hw,
1187 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1188 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1189 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1190}
1191
6b1a3aef 1192/*
1193 * The RX Stop command will not work for Yukon-2 if the BMU does not
1194 * reach the end of packet and since we can't make sure that we have
1195 * incoming data, we must reset the BMU while it is not doing a DMA
1196 * transfer. Since it is possible that the RX path is still active,
1197 * the RX RAM buffer will be stopped first, so any possible incoming
1198 * data will not trigger a DMA. After the RAM buffer is stopped, the
1199 * BMU is polled until any DMA in progress is ended and only then it
1200 * will be reset.
1201 */
1202static void sky2_rx_stop(struct sky2_port *sky2)
1203{
1204 struct sky2_hw *hw = sky2->hw;
1205 unsigned rxq = rxqaddr[sky2->port];
1206 int i;
1207
1208 /* disable the RAM Buffer receive queue */
1209 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1210
1211 for (i = 0; i < 0xffff; i++)
1212 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1213 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1214 goto stopped;
1215
ada1db5c 1216 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef 1217stopped:
1218 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1219
1220 /* reset the Rx prefetch unit */
1221 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1222 mmiowb();
6b1a3aef 1223}
793b883e 1224
d571b694 1225/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1226static void sky2_rx_clean(struct sky2_port *sky2)
1227{
1228 unsigned i;
1229
1230 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1231 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1232 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1233
1234 if (re->skb) {
14d0263f 1235 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1236 kfree_skb(re->skb);
1237 re->skb = NULL;
1238 }
1239 }
1240}
1241
ef743d33 1242/* Basic MII support */
1243static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1244{
1245 struct mii_ioctl_data *data = if_mii(ifr);
1246 struct sky2_port *sky2 = netdev_priv(dev);
1247 struct sky2_hw *hw = sky2->hw;
1248 int err = -EOPNOTSUPP;
1249
1250 if (!netif_running(dev))
1251 return -ENODEV; /* Phy still in reset */
1252
d89e1343 1253 switch (cmd) {
ef743d33 1254 case SIOCGMIIPHY:
1255 data->phy_id = PHY_ADDR_MARV;
1256
1257 /* fallthru */
1258 case SIOCGMIIREG: {
1259 u16 val = 0;
91c86df5 1260
e07b1aa8 1261 spin_lock_bh(&sky2->phy_lock);
ef743d33 1262 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1263 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1264
ef743d33 1265 data->val_out = val;
1266 break;
1267 }
1268
1269 case SIOCSMIIREG:
e07b1aa8 1270 spin_lock_bh(&sky2->phy_lock);
ef743d33 1271 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1272 data->val_in);
e07b1aa8 1273 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1274 break;
1275 }
1276 return err;
1277}
1278
d1f13708 1279#ifdef SKY2_VLAN_TAG_USED
d494eacd 1280static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1281{
d494eacd 1282 if (onoff) {
3d4e66f5
SH		 1283 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1284 RX_VLAN_STRIP_ON);
1285 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1286 TX_VLAN_TAG_ON);
1287 } else {
1288 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1289 RX_VLAN_STRIP_OFF);
1290 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1291 TX_VLAN_TAG_OFF);
1292 }
d494eacd
SH		 1293}
1294
1295static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1296{
1297 struct sky2_port *sky2 = netdev_priv(dev);
1298 struct sky2_hw *hw = sky2->hw;
1299 u16 port = sky2->port;
1300
1301 netif_tx_lock_bh(dev);
1302 napi_disable(&hw->napi);
1303
1304 sky2->vlgrp = grp;
1305 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1306
d1d08d12 1307 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1308 napi_enable(&hw->napi);
2bb8c262 1309 netif_tx_unlock_bh(dev);
d1f13708 1310}
1311#endif
1312
bd1c6869
SH		 1313/* Amount of required worst case padding in rx buffer */
1314static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1315{
1316 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1317}
1318
82788c7a 1319/*
14d0263f
SH		 1320 * Allocate an skb for receiving. If the MTU is large enough
1321 * make the skb non-linear with a fragment list of pages.
82788c7a 1322 */
14d0263f 1323static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1324{
1325 struct sk_buff *skb;
14d0263f 1326 int i;
82788c7a 1327
724b6942
SH		 1328 skb = netdev_alloc_skb(sky2->netdev,
1329 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1330 if (!skb)
1331 goto nomem;
1332
39dbd958 1333 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1334 unsigned char *start;
1335 /*
1336 * Workaround for a bug in FIFO that cause hang
1337 * if the FIFO if the receive buffer is not 64 byte aligned.
1338 * The buffer returned from netdev_alloc_skb is
1339 * aligned except if slab debugging is enabled.
1340 */
f03b8654
SH		 1341 start = PTR_ALIGN(skb->data, 8);
1342 skb_reserve(skb, start - skb->data);
bd1c6869 1343 } else
f03b8654 1344 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1345
1346 for (i = 0; i < sky2->rx_nfrags; i++) {
1347 struct page *page = alloc_page(GFP_ATOMIC);
1348
1349 if (!page)
1350 goto free_partial;
1351 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1352 }
1353
1354 return skb;
14d0263f
SH		 1355free_partial:
1356 kfree_skb(skb);
1357nomem:
1358 return NULL;
82788c7a
SH		 1359}
1360
55c9dd35
SH		 1361static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1362{
1363 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1364}
1365
200ac492
MM		 1366static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1367{
1368 struct sky2_hw *hw = sky2->hw;
1369 unsigned i;
1370
1371 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1372
1373 /* Fill Rx ring */
1374 for (i = 0; i < sky2->rx_pending; i++) {
1375 struct rx_ring_info *re = sky2->rx_ring + i;
1376
1377 re->skb = sky2_rx_alloc(sky2);
1378 if (!re->skb)
1379 return -ENOMEM;
1380
1381 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1382 dev_kfree_skb(re->skb);
1383 re->skb = NULL;
1384 return -ENOMEM;
1385 }
1386 }
1387 return 0;
1388}
1389
cd28ab6a 1390/*
200ac492 1391 * Setup receiver buffer pool.
14d0263f
SH		 1392 * Normal case this ends up creating one list element for skb
1393 * in the receive ring. Worst case if using large MTU and each
1394 * allocation falls on a different 64 bit region, that results
1395 * in 6 list elements per ring entry.
1396 * One element is used for checksum enable/disable, and one
1397 * extra to avoid wrap.
cd28ab6a 1398 */
200ac492 1399static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1400{
6b1a3aef 1401 struct sky2_hw *hw = sky2->hw;
14d0263f 1402 struct rx_ring_info *re;
6b1a3aef 1403 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1404 unsigned i, thresh;
cd28ab6a 1405
6b1a3aef 1406 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1407 sky2_qset(hw, rxq);
977bdf06 1408
c3905bc4
SH		 1409 /* On PCI express lowering the watermark gives better performance */
1410 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1411 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1412
1413 /* These chips have no ram buffer?
1414 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1415 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
8e95a202
JP		 1416 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1417 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1418 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1419
6b1a3aef 1420 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1421
ea76e635
SH		 1422 if (!(hw->flags & SKY2_HW_NEW_LE))
1423 rx_set_checksum(sky2);
14d0263f 1424
200ac492 1425 /* submit Rx ring */
793b883e 1426 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1427 re = sky2->rx_ring + i;
14d0263f 1428 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1429 }
1430
a1433ac4
SH		 1431 /*
1432 * The receiver hangs if it receives frames larger than the
1433 * packet buffer. As a workaround, truncate oversize frames, but
1434 * the register is limited to 9 bits, so if you do frames > 2052
1435 * you better get the MTU right!
1436 */
39ef110b 1437 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1438 if (thresh > 0x1ff)
1439 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1440 else {
1441 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1442 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1443 }
1444
6b1a3aef 1445 /* Tell chip about available buffers */
55c9dd35 1446 sky2_rx_update(sky2, rxq);
877c8570
SH		 1447
1448 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1449 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1450 /*
1451 * Disable flushing of non ASF packets;
1452 * must be done after initializing the BMUs;
1453 * drivers without ASF support should do this too, otherwise
1454 * it may happen that they cannot run on ASF devices;
1455 * remember that the MAC FIFO isn't reset during initialization.
1456 */
1457 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1458 }
1459
1460 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1461 /* Enable RX Home Address & Routing Header checksum fix */
1462 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1463 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1464
1465 /* Enable TX Home Address & Routing Header checksum fix */
1466 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1467 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1468 }
cd28ab6a
SH		 1469}
1470
90bbebb4
MM		 1471static int sky2_alloc_buffers(struct sky2_port *sky2)
1472{
1473 struct sky2_hw *hw = sky2->hw;
1474
1475 /* must be power of 2 */
1476 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1477 sky2->tx_ring_size *
1478 sizeof(struct sky2_tx_le),
1479 &sky2->tx_le_map);
1480 if (!sky2->tx_le)
1481 goto nomem;
1482
1483 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1484 GFP_KERNEL);
1485 if (!sky2->tx_ring)
1486 goto nomem;
1487
1488 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1489 &sky2->rx_le_map);
1490 if (!sky2->rx_le)
1491 goto nomem;
1492 memset(sky2->rx_le, 0, RX_LE_BYTES);
1493
1494 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1495 GFP_KERNEL);
1496 if (!sky2->rx_ring)
1497 goto nomem;
1498
200ac492 1499 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1500nomem:
1501 return -ENOMEM;
1502}
1503
1504static void sky2_free_buffers(struct sky2_port *sky2)
1505{
1506 struct sky2_hw *hw = sky2->hw;
1507
200ac492
MM		 1508 sky2_rx_clean(sky2);
1509
90bbebb4
MM		 1510 if (sky2->rx_le) {
1511 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1512 sky2->rx_le, sky2->rx_le_map);
1513 sky2->rx_le = NULL;
1514 }
1515 if (sky2->tx_le) {
1516 pci_free_consistent(hw->pdev,
1517 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1518 sky2->tx_le, sky2->tx_le_map);
1519 sky2->tx_le = NULL;
1520 }
1521 kfree(sky2->tx_ring);
1522 kfree(sky2->rx_ring);
1523
1524 sky2->tx_ring = NULL;
1525 sky2->rx_ring = NULL;
1526}
1527
ea0f71e5 1528static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1529{
cd28ab6a
SH		 1530 struct sky2_hw *hw = sky2->hw;
1531 unsigned port = sky2->port;
ea0f71e5
MM		 1532 u32 ramsize;
1533 int cap;
843a46f4 1534 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1535
ea0f71e5
MM		 1536 tx_init(sky2);
1537
ee7abb04
SH		 1538 /*
1539 * On dual port PCI-X card, there is an problem where status
1540 * can be received out of order due to split transactions
843a46f4 1541 */
ee7abb04
SH		 1542 if (otherdev && netif_running(otherdev) &&
1543 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1544 u16 cmd;
1545
b32f40c4 1546 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1547 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1548 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1549 }
cd28ab6a 1550
cd28ab6a
SH		 1551 sky2_mac_init(hw, port);
1552
e0c28116
SH		 1553 /* Register is number of 4K blocks on internal RAM buffer. */
1554 ramsize = sky2_read8(hw, B2_E_0) * 4;
1555 if (ramsize > 0) {
67712901 1556 u32 rxspace;
cd28ab6a 1557
ada1db5c 1558 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1559 if (ramsize < 16)
1560 rxspace = ramsize / 2;
1561 else
1562 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1563
67712901
SH		 1564 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1565 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1566
1567 /* Make sure SyncQ is disabled */
1568 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1569 RB_RST_SET);
1570 }
793b883e 1571
af4ed7e6 1572 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1573
69161611
SH		 1574 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1575 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1576 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1577
977bdf06 1578 /* Set almost empty threshold */
8e95a202
JP		 1579 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1580 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1581 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1582
6b1a3aef 1583 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1584 sky2->tx_ring_size - 1);
cd28ab6a 1585
d494eacd
SH		 1586#ifdef SKY2_VLAN_TAG_USED
1587 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1588#endif
1589
200ac492 1590 sky2_rx_start(sky2);
ea0f71e5
MM		 1591}
1592
1593/* Bring up network interface. */
1594static int sky2_up(struct net_device *dev)
1595{
1596 struct sky2_port *sky2 = netdev_priv(dev);
1597 struct sky2_hw *hw = sky2->hw;
1598 unsigned port = sky2->port;
1599 u32 imask;
1600 int err;
1601
1602 netif_carrier_off(dev);
1603
1604 err = sky2_alloc_buffers(sky2);
1605 if (err)
1606 goto err_out;
1607
1608 sky2_hw_up(sky2);
cd28ab6a 1609
cd28ab6a 1610 /* Enable interrupts from phy/mac for port */
e07b1aa8 1611 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1612 imask |= portirq_msk[port];
e07b1aa8 1613 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1614 sky2_read32(hw, B0_IMSK);
e07b1aa8 1615
6c35abae 1616 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1617
cd28ab6a
SH		 1618 return 0;
1619
1620err_out:
90bbebb4 1621 sky2_free_buffers(sky2);
cd28ab6a
SH		 1622 return err;
1623}
1624
793b883e 1625/* Modular subtraction in ring */
ee5f68fe 1626static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1627{
ee5f68fe 1628 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1629}
cd28ab6a 1630
793b883e
SH		 1631/* Number of list elements available for next tx */
1632static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1633{
ee5f68fe 1634 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1635}
1636
793b883e 1637/* Estimate of number of transmit list elements required */
28bd181a 1638static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1639{
793b883e
SH		 1640 unsigned count;
1641
07e31637
SH		 1642 count = (skb_shinfo(skb)->nr_frags + 1)
1643 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1644
89114afd 1645 if (skb_is_gso(skb))
793b883e 1646 ++count;
07e31637
SH		 1647 else if (sizeof(dma_addr_t) == sizeof(u32))
1648 ++count; /* possible vlan */
793b883e 1649
84fa7933 1650 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1651 ++count;
1652
1653 return count;
cd28ab6a
SH		 1654}
1655
f6815077 1656static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1657{
1658 if (re->flags & TX_MAP_SINGLE)
1659 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1660 pci_unmap_len(re, maplen),
1661 PCI_DMA_TODEVICE);
1662 else if (re->flags & TX_MAP_PAGE)
1663 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1664 pci_unmap_len(re, maplen),
1665 PCI_DMA_TODEVICE);
f6815077 1666 re->flags = 0;
6b84daca
SH		 1667}
1668
793b883e
SH		 1669/*
1670 * Put one packet in ring for transmit.
1671 * A single packet can generate multiple list elements, and
1672 * the number of ring elements will probably be less than the number
1673 * of list elements used.
1674 */
61357325
SH		 1675static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1676 struct net_device *dev)
cd28ab6a
SH		 1677{
1678 struct sky2_port *sky2 = netdev_priv(dev);
1679 struct sky2_hw *hw = sky2->hw;
d1f13708 1680 struct sky2_tx_le *le = NULL;
6cdbbdf3 1681 struct tx_ring_info *re;
9b289c33 1682 unsigned i, len;
cd28ab6a 1683 dma_addr_t mapping;
5dce95e5
SH		 1684 u32 upper;
1685 u16 slot;
cd28ab6a
SH		 1686 u16 mss;
1687 u8 ctrl;
1688
2bb8c262
SH		 1689 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1690 return NETDEV_TX_BUSY;
cd28ab6a 1691
cd28ab6a
SH		 1692 len = skb_headlen(skb);
1693 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1694
454e6cb6
SH		 1695 if (pci_dma_mapping_error(hw->pdev, mapping))
1696 goto mapping_error;
1697
9b289c33 1698 slot = sky2->tx_prod;
6c35abae
JP		 1699 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1700 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1701
86c6887e 1702 /* Send high bits if needed */
5dce95e5
SH		 1703 upper = upper_32_bits(mapping);
1704 if (upper != sky2->tx_last_upper) {
9b289c33 1705 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1706 le->addr = cpu_to_le32(upper);
1707 sky2->tx_last_upper = upper;
793b883e 1708 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1709 }
cd28ab6a
SH		 1710
1711 /* Check for TCP Segmentation Offload */
7967168c 1712 mss = skb_shinfo(skb)->gso_size;
793b883e 1713 if (mss != 0) {
ea76e635
SH		 1714
1715 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1716 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1717
1718 if (mss != sky2->tx_last_mss) {
9b289c33 1719 le = get_tx_le(sky2, &slot);
69161611 1720 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1721
1722 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1723 le->opcode = OP_MSS | HW_OWNER;
1724 else
1725 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1726 sky2->tx_last_mss = mss;
1727 }
cd28ab6a
SH		 1728 }
1729
cd28ab6a 1730 ctrl = 0;
d1f13708 1731#ifdef SKY2_VLAN_TAG_USED
1732 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1733 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1734 if (!le) {
9b289c33 1735 le = get_tx_le(sky2, &slot);
f65b138c 1736 le->addr = 0;
d1f13708 1737 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1738 } else
1739 le->opcode |= OP_VLAN;
1740 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1741 ctrl |= INS_VLAN;
1742 }
1743#endif
1744
1745 /* Handle TCP checksum offload */
84fa7933 1746 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1747 /* On Yukon EX (some versions) encoding change. */
ea76e635 1748 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1749 ctrl |= CALSUM; /* auto checksum */
1750 else {
1751 const unsigned offset = skb_transport_offset(skb);
1752 u32 tcpsum;
1753
1754 tcpsum = offset << 16; /* sum start */
1755 tcpsum |= offset + skb->csum_offset; /* sum write */
1756
1757 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1758 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1759 ctrl |= UDPTCP;
1760
1761 if (tcpsum != sky2->tx_tcpsum) {
1762 sky2->tx_tcpsum = tcpsum;
1763
9b289c33 1764 le = get_tx_le(sky2, &slot);
69161611
SH		 1765 le->addr = cpu_to_le32(tcpsum);
1766 le->length = 0; /* initial checksum value */
1767 le->ctrl = 1; /* one packet */
1768 le->opcode = OP_TCPLISW | HW_OWNER;
1769 }
1d179332 1770 }
cd28ab6a
SH		 1771 }
1772
6b84daca
SH		 1773 re = sky2->tx_ring + slot;
1774 re->flags = TX_MAP_SINGLE;
1775 pci_unmap_addr_set(re, mapaddr, mapping);
1776 pci_unmap_len_set(re, maplen, len);
1777
9b289c33 1778 le = get_tx_le(sky2, &slot);
d6e74b6b 1779 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1780 le->length = cpu_to_le16(len);
1781 le->ctrl = ctrl;
793b883e 1782 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1783
cd28ab6a
SH		 1784
1785 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1786 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1787
1788 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1789 frag->size, PCI_DMA_TODEVICE);
86c6887e 1790
454e6cb6
SH		 1791 if (pci_dma_mapping_error(hw->pdev, mapping))
1792 goto mapping_unwind;
1793
5dce95e5
SH		 1794 upper = upper_32_bits(mapping);
1795 if (upper != sky2->tx_last_upper) {
9b289c33 1796 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1797 le->addr = cpu_to_le32(upper);
1798 sky2->tx_last_upper = upper;
793b883e 1799 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1800 }
1801
6b84daca
SH		 1802 re = sky2->tx_ring + slot;
1803 re->flags = TX_MAP_PAGE;
1804 pci_unmap_addr_set(re, mapaddr, mapping);
1805 pci_unmap_len_set(re, maplen, frag->size);
1806
9b289c33 1807 le = get_tx_le(sky2, &slot);
d6e74b6b 1808 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1809 le->length = cpu_to_le16(frag->size);
1810 le->ctrl = ctrl;
793b883e 1811 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1812 }
6cdbbdf3 1813
6b84daca 1814 re->skb = skb;
cd28ab6a
SH		 1815 le->ctrl |= EOP;
1816
9b289c33
MM		 1817 sky2->tx_prod = slot;
1818
97bda706 1819 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1820 netif_stop_queue(dev);
b19666d9 1821
290d4de5 1822 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1823
cd28ab6a 1824 return NETDEV_TX_OK;
454e6cb6
SH		 1825
1826mapping_unwind:
ee5f68fe 1827 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1828 re = sky2->tx_ring + i;
1829
6b84daca 1830 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1831 }
1832
454e6cb6
SH		 1833mapping_error:
1834 if (net_ratelimit())
1835 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1836 dev_kfree_skb(skb);
1837 return NETDEV_TX_OK;
cd28ab6a
SH		 1838}
1839
cd28ab6a 1840/*
793b883e
SH		 1841 * Free ring elements from starting at tx_cons until "done"
1842 *
481cea4a
SH		 1843 * NB:
1844 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1845 * buffers so make sure not to free skb to early.
481cea4a
SH		 1846 * 2. This may run in parallel start_xmit because the it only
1847 * looks at the tail of the queue of FIFO (tx_cons), not
1848 * the head (tx_prod)
cd28ab6a 1849 */
d11c13e7 1850static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1851{
d11c13e7 1852 struct net_device *dev = sky2->netdev;
291ea614 1853 unsigned idx;
cd28ab6a 1854
ee5f68fe 1855 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1856
291ea614 1857 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1858 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1859 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1860 struct sk_buff *skb = re->skb;
291ea614 1861
6b84daca 1862 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1863
6b84daca 1864 if (skb) {
6c35abae
JP		 1865 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1866 "tx done %u\n", idx);
3cf26753 1867
7138a0f5 1868 dev->stats.tx_packets++;
bd1c6869
SH		 1869 dev->stats.tx_bytes += skb->len;
1870
f6815077 1871 re->skb = NULL;
724b6942 1872 dev_kfree_skb_any(skb);
2bf56fe2 1873
ee5f68fe 1874 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1875 }
793b883e 1876 }
793b883e 1877
291ea614 1878 sky2->tx_cons = idx;
50432cb5 1879 smp_mb();
cd28ab6a
SH		 1880}
1881
264bb4fa 1882static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1883{
a510996b
MM		 1884 /* Disable Force Sync bit and Enable Alloc bit */
1885 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1886 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1887
1888 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1889 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1890 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1891
1892 /* Reset the PCI FIFO of the async Tx queue */
1893 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1894 BMU_RST_SET | BMU_FIFO_RST);
1895
1896 /* Reset the Tx prefetch units */
1897 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1898 PREF_UNIT_RST_SET);
1899
1900 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1901 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1902}
1903
f2b31cb3 1904static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 1905{
cd28ab6a
SH		 1906 struct sky2_hw *hw = sky2->hw;
1907 unsigned port = sky2->port;
f2b31cb3 1908 u16 ctrl;
cd28ab6a 1909
d104acaf
SH		 1910 /* Force flow control off */
1911 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1912
cd28ab6a
SH		 1913 /* Stop transmitter */
1914 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1915 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1916
1917 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1918 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1919
1920 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1921 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1922 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1923
1924 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1925
1926 /* Workaround shared GMAC reset */
8e95a202
JP		 1927 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1928 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1929 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1930
cd28ab6a 1931 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1932
6c83504f
SH		 1933 /* Force any delayed status interrrupt and NAPI */
1934 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1935 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1936 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1937 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1938
a947a39d
MM		 1939 sky2_rx_stop(sky2);
1940
0da6d7b3 1941 spin_lock_bh(&sky2->phy_lock);
b96936da 1942 sky2_phy_power_down(hw, port);
0da6d7b3 1943 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1944
264bb4fa
MM		 1945 sky2_tx_reset(hw, port);
1946
481cea4a
SH		 1947 /* Free any pending frames stuck in HW queue */
1948 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 1949}
1950
1951/* Network shutdown */
1952static int sky2_down(struct net_device *dev)
1953{
1954 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 1955 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 1956
1957 /* Never really got started! */
1958 if (!sky2->tx_le)
1959 return 0;
1960
6c35abae 1961 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 1962
8a0c9228
MM		 1963 /* Disable port IRQ */
1964 sky2_write32(hw, B0_IMSK,
1965 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
1966 sky2_read32(hw, B0_IMSK);
1967
1968 synchronize_irq(hw->pdev->irq);
1969 napi_synchronize(&hw->napi);
1970
f2b31cb3 1971 sky2_hw_down(sky2);
481cea4a 1972
90bbebb4 1973 sky2_free_buffers(sky2);
1b537565 1974
cd28ab6a
SH		 1975 return 0;
1976}
1977
1978static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1979{
ea76e635 1980 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1981 return SPEED_1000;
1982
05745c4a
SH		 1983 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1984 if (aux & PHY_M_PS_SPEED_100)
1985 return SPEED_100;
1986 else
1987 return SPEED_10;
1988 }
cd28ab6a
SH		 1989
1990 switch (aux & PHY_M_PS_SPEED_MSK) {
1991 case PHY_M_PS_SPEED_1000:
1992 return SPEED_1000;
1993 case PHY_M_PS_SPEED_100:
1994 return SPEED_100;
1995 default:
1996 return SPEED_10;
1997 }
1998}
1999
2000static void sky2_link_up(struct sky2_port *sky2)
2001{
2002 struct sky2_hw *hw = sky2->hw;
2003 unsigned port = sky2->port;
2004 u16 reg;
16ad91e1
SH		 2005 static const char *fc_name[] = {
2006 [FC_NONE] = "none",
2007 [FC_TX] = "tx",
2008 [FC_RX] = "rx",
2009 [FC_BOTH] = "both",
2010 };
cd28ab6a 2011
cd28ab6a 2012 /* enable Rx/Tx */
2eaba1a2 2013 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 2014 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2015 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 2016
2017 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2018
2019 netif_carrier_on(sky2->netdev);
cd28ab6a 2020
75e80683 2021 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2022
cd28ab6a 2023 /* Turn on link LED */
793b883e 2024 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2025 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2026
6c35abae
JP		 2027 netif_info(sky2, link, sky2->netdev,
2028 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2029 sky2->speed,
2030 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2031 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2032}
2033
2034static void sky2_link_down(struct sky2_port *sky2)
2035{
2036 struct sky2_hw *hw = sky2->hw;
2037 unsigned port = sky2->port;
2038 u16 reg;
2039
2040 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2041
2042 reg = gma_read16(hw, port, GM_GP_CTRL);
2043 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2044 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2045
cd28ab6a 2046 netif_carrier_off(sky2->netdev);
cd28ab6a 2047
809aaaae 2048 /* Turn off link LED */
cd28ab6a
SH		 2049 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2050
6c35abae 2051 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2052
cd28ab6a
SH		 2053 sky2_phy_init(hw, port);
2054}
2055
16ad91e1
SH		 2056static enum flow_control sky2_flow(int rx, int tx)
2057{
2058 if (rx)
2059 return tx ? FC_BOTH : FC_RX;
2060 else
2061 return tx ? FC_TX : FC_NONE;
2062}
2063
793b883e
SH		 2064static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2065{
2066 struct sky2_hw *hw = sky2->hw;
2067 unsigned port = sky2->port;
da4c1ff4 2068 u16 advert, lpa;
793b883e 2069
da4c1ff4 2070 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2071 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2072 if (lpa & PHY_M_AN_RF) {
ada1db5c 2073 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2074 return -1;
2075 }
2076
793b883e 2077 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2078 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2079 return -1;
2080 }
2081
793b883e 2082 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2083 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2084
da4c1ff4
SH		 2085 /* Since the pause result bits seem to in different positions on
2086 * different chips. look at registers.
2087 */
ea76e635 2088 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2089 /* Shift for bits in fiber PHY */
2090 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2091 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2092
2093 if (advert & ADVERTISE_1000XPAUSE)
2094 advert |= ADVERTISE_PAUSE_CAP;
2095 if (advert & ADVERTISE_1000XPSE_ASYM)
2096 advert |= ADVERTISE_PAUSE_ASYM;
2097 if (lpa & LPA_1000XPAUSE)
2098 lpa |= LPA_PAUSE_CAP;
2099 if (lpa & LPA_1000XPAUSE_ASYM)
2100 lpa |= LPA_PAUSE_ASYM;
2101 }
793b883e 2102
da4c1ff4
SH		 2103 sky2->flow_status = FC_NONE;
2104 if (advert & ADVERTISE_PAUSE_CAP) {
2105 if (lpa & LPA_PAUSE_CAP)
2106 sky2->flow_status = FC_BOTH;
2107 else if (advert & ADVERTISE_PAUSE_ASYM)
2108 sky2->flow_status = FC_RX;
2109 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2110 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2111 sky2->flow_status = FC_TX;
2112 }
793b883e 2113
8e95a202
JP		 2114 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2115 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2116 sky2->flow_status = FC_NONE;
2eaba1a2 2117
da4c1ff4 2118 if (sky2->flow_status & FC_TX)
793b883e
SH		 2119 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2120 else
2121 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2122
2123 return 0;
2124}
cd28ab6a 2125
e07b1aa8
SH		 2126/* Interrupt from PHY */
2127static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2128{
e07b1aa8
SH		 2129 struct net_device *dev = hw->dev[port];
2130 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2131 u16 istatus, phystat;
2132
ebc646f6
SH		 2133 if (!netif_running(dev))
2134 return;
2135
e07b1aa8
SH		 2136 spin_lock(&sky2->phy_lock);
2137 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2138 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2139
6c35abae
JP		 2140 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2141 istatus, phystat);
cd28ab6a 2142
0ea065e5 2143 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2144 if (sky2_autoneg_done(sky2, phystat) == 0)
2145 sky2_link_up(sky2);
2146 goto out;
2147 }
cd28ab6a 2148
793b883e
SH		 2149 if (istatus & PHY_M_IS_LSP_CHANGE)
2150 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2151
793b883e
SH		 2152 if (istatus & PHY_M_IS_DUP_CHANGE)
2153 sky2->duplex =
2154 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2155
793b883e
SH		 2156 if (istatus & PHY_M_IS_LST_CHANGE) {
2157 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2158 sky2_link_up(sky2);
793b883e
SH		 2159 else
2160 sky2_link_down(sky2);
cd28ab6a 2161 }
793b883e 2162out:
e07b1aa8 2163 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2164}
2165
0f5aac70
SH		 2166/* Special quick link interrupt (Yukon-2 Optima only) */
2167static void sky2_qlink_intr(struct sky2_hw *hw)
2168{
2169 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2170 u32 imask;
2171 u16 phy;
2172
2173 /* disable irq */
2174 imask = sky2_read32(hw, B0_IMSK);
2175 imask &= ~Y2_IS_PHY_QLNK;
2176 sky2_write32(hw, B0_IMSK, imask);
2177
2178 /* reset PHY Link Detect */
2179 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2180 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2181 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2182 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2183
2184 sky2_link_up(sky2);
2185}
2186
62335ab0 2187/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2188 * and tx queue is full (stopped).
2189 */
cd28ab6a
SH		 2190static void sky2_tx_timeout(struct net_device *dev)
2191{
2192 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2193 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2194
6c35abae 2195 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2196
ada1db5c
JP		 2197 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2198 sky2->tx_cons, sky2->tx_prod,
2199 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2200 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2201
81906791
SH		 2202 /* can't restart safely under softirq */
2203 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2204}
2205
2206static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2207{
6b1a3aef 2208 struct sky2_port *sky2 = netdev_priv(dev);
2209 struct sky2_hw *hw = sky2->hw;
b628ed98 2210 unsigned port = sky2->port;
6b1a3aef 2211 int err;
2212 u16 ctl, mode;
e07b1aa8 2213 u32 imask;
cd28ab6a 2214
44dde56d 2215 /* MTU size outside the spec */
cd28ab6a
SH		 2216 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2217 return -EINVAL;
2218
44dde56d 2219 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2220 if (new_mtu > ETH_DATA_LEN &&
2221 (hw->chip_id == CHIP_ID_YUKON_FE ||
2222 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2223 return -EINVAL;
2224
44dde56d 2225 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2226 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2227 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2228
6b1a3aef 2229 if (!netif_running(dev)) {
2230 dev->mtu = new_mtu;
2231 return 0;
2232 }
2233
e07b1aa8 2234 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2235 sky2_write32(hw, B0_IMSK, 0);
2236
018d1c66 2237 dev->trans_start = jiffies; /* prevent tx timeout */
2238 netif_stop_queue(dev);
bea3348e 2239 napi_disable(&hw->napi);
018d1c66 2240
e07b1aa8
SH		 2241 synchronize_irq(hw->pdev->irq);
2242
39dbd958 2243 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2244 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2245
2246 ctl = gma_read16(hw, port, GM_GP_CTRL);
2247 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2248 sky2_rx_stop(sky2);
2249 sky2_rx_clean(sky2);
cd28ab6a
SH		 2250
2251 dev->mtu = new_mtu;
14d0263f 2252
6b1a3aef 2253 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2254 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2255
2256 if (dev->mtu > ETH_DATA_LEN)
2257 mode |= GM_SMOD_JUMBO_ENA;
2258
b628ed98 2259 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2260
b628ed98 2261 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2262
200ac492
MM		 2263 err = sky2_alloc_rx_skbs(sky2);
2264 if (!err)
2265 sky2_rx_start(sky2);
2266 else
2267 sky2_rx_clean(sky2);
e07b1aa8 2268 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2269
d1d08d12 2270 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2271 napi_enable(&hw->napi);
2272
1b537565
SH		 2273 if (err)
2274 dev_close(dev);
2275 else {
b628ed98 2276 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2277
1b537565
SH		 2278 netif_wake_queue(dev);
2279 }
2280
cd28ab6a
SH		 2281 return err;
2282}
2283
14d0263f
SH		 2284/* For small just reuse existing skb for next receive */
2285static struct sk_buff *receive_copy(struct sky2_port *sky2,
2286 const struct rx_ring_info *re,
2287 unsigned length)
2288{
2289 struct sk_buff *skb;
2290
89d71a66 2291 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2292 if (likely(skb)) {
14d0263f
SH		 2293 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2294 length, PCI_DMA_FROMDEVICE);
d626f62b 2295 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2296 skb->ip_summed = re->skb->ip_summed;
2297 skb->csum = re->skb->csum;
2298 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2299 length, PCI_DMA_FROMDEVICE);
2300 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2301 skb_put(skb, length);
14d0263f
SH		 2302 }
2303 return skb;
2304}
2305
2306/* Adjust length of skb with fragments to match received data */
2307static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2308 unsigned int length)
2309{
2310 int i, num_frags;
2311 unsigned int size;
2312
2313 /* put header into skb */
2314 size = min(length, hdr_space);
2315 skb->tail += size;
2316 skb->len += size;
2317 length -= size;
2318
2319 num_frags = skb_shinfo(skb)->nr_frags;
2320 for (i = 0; i < num_frags; i++) {
2321 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2322
2323 if (length == 0) {
2324 /* don't need this page */
2325 __free_page(frag->page);
2326 --skb_shinfo(skb)->nr_frags;
2327 } else {
2328 size = min(length, (unsigned) PAGE_SIZE);
2329
2330 frag->size = size;
2331 skb->data_len += size;
2332 skb->truesize += size;
2333 skb->len += size;
2334 length -= size;
2335 }
2336 }
2337}
2338
2339/* Normal packet - take skb from ring element and put in a new one */
2340static struct sk_buff *receive_new(struct sky2_port *sky2,
2341 struct rx_ring_info *re,
2342 unsigned int length)
2343{
3fbd9187 2344 struct sk_buff *skb;
2345 struct rx_ring_info nre;
14d0263f
SH		 2346 unsigned hdr_space = sky2->rx_data_size;
2347
3fbd9187 2348 nre.skb = sky2_rx_alloc(sky2);
2349 if (unlikely(!nre.skb))
2350 goto nobuf;
2351
2352 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2353 goto nomap;
14d0263f
SH		 2354
2355 skb = re->skb;
2356 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2357 prefetch(skb->data);
3fbd9187 2358 *re = nre;
14d0263f
SH		 2359
2360 if (skb_shinfo(skb)->nr_frags)
2361 skb_put_frags(skb, hdr_space, length);
2362 else
489b10c1 2363 skb_put(skb, length);
14d0263f 2364 return skb;
3fbd9187 2365
2366nomap:
2367 dev_kfree_skb(nre.skb);
2368nobuf:
2369 return NULL;
14d0263f
SH		 2370}
2371
cd28ab6a
SH		 2372/*
2373 * Receive one packet.
d571b694 2374 * For larger packets, get new buffer.
cd28ab6a 2375 */
497d7c86 2376static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2377 u16 length, u32 status)
2378{
497d7c86 2379 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2380 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2381 struct sk_buff *skb = NULL;
d6532232
SH		 2382 u16 count = (status & GMR_FS_LEN) >> 16;
2383
2384#ifdef SKY2_VLAN_TAG_USED
2385 /* Account for vlan tag */
2386 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2387 count -= VLAN_HLEN;
2388#endif
cd28ab6a 2389
6c35abae
JP		 2390 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2391 "rx slot %u status 0x%x len %d\n",
2392 sky2->rx_next, status, length);
cd28ab6a 2393
793b883e 2394 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2395 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2396
3b12e014
SH		 2397 /* This chip has hardware problems that generates bogus status.
2398 * So do only marginal checking and expect higher level protocols
2399 * to handle crap frames.
2400 */
2401 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2402 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2403 length != count)
2404 goto okay;
2405
42eeea01 2406 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2407 goto error;
2408
42eeea01 2409 if (!(status & GMR_FS_RX_OK))
2410 goto resubmit;
2411
d6532232
SH		 2412 /* if length reported by DMA does not match PHY, packet was truncated */
2413 if (length != count)
3b12e014 2414 goto len_error;
71749531 2415
3b12e014 2416okay:
14d0263f
SH		 2417 if (length < copybreak)
2418 skb = receive_copy(sky2, re, length);
2419 else
2420 skb = receive_new(sky2, re, length);
90c30335
SH		 2421
2422 dev->stats.rx_dropped += (skb == NULL);
2423
793b883e 2424resubmit:
14d0263f 2425 sky2_rx_submit(sky2, re);
79e57d32 2426
cd28ab6a
SH		 2427 return skb;
2428
3b12e014 2429len_error:
71749531
SH		 2430 /* Truncation of overlength packets
2431 causes PHY length to not match MAC length */
7138a0f5 2432 ++dev->stats.rx_length_errors;
6c35abae
JP		 2433 if (net_ratelimit())
2434 netif_info(sky2, rx_err, dev,
2435 "rx length error: status %#x length %d\n",
2436 status, length);
d6532232 2437 goto resubmit;
71749531 2438
cd28ab6a 2439error:
7138a0f5 2440 ++dev->stats.rx_errors;
b6d77734 2441 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2442 dev->stats.rx_over_errors++;
b6d77734
SH		 2443 goto resubmit;
2444 }
6e15b712 2445
6c35abae
JP		 2446 if (net_ratelimit())
2447 netif_info(sky2, rx_err, dev,
2448 "rx error, status 0x%x length %d\n", status, length);
793b883e
SH		 2449
2450 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2451 dev->stats.rx_length_errors++;
cd28ab6a 2452 if (status & GMR_FS_FRAGMENT)
7138a0f5 2453 dev->stats.rx_frame_errors++;
cd28ab6a 2454 if (status & GMR_FS_CRC_ERR)
7138a0f5 2455 dev->stats.rx_crc_errors++;
79e57d32 2456
793b883e 2457 goto resubmit;
cd28ab6a
SH		 2458}
2459
e07b1aa8
SH		 2460/* Transmit complete */
2461static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2462{
e07b1aa8 2463 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2464
8a0c9228 2465 if (netif_running(dev)) {
e07b1aa8 2466 sky2_tx_complete(sky2, last);
8a0c9228
MM		 2467
2468 /* Wake unless it's detached, and called e.g. from sky2_down() */
2469 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2470 netif_wake_queue(dev);
2471 }
cd28ab6a
SH		 2472}
2473
37e5a243
SH		 2474static inline void sky2_skb_rx(const struct sky2_port *sky2,
2475 u32 status, struct sk_buff *skb)
2476{
2477#ifdef SKY2_VLAN_TAG_USED
2478 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2479 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2480 if (skb->ip_summed == CHECKSUM_NONE)
2481 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2482 else
2483 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2484 vlan_tag, skb);
2485 return;
2486 }
2487#endif
2488 if (skb->ip_summed == CHECKSUM_NONE)
2489 netif_receive_skb(skb);
2490 else
2491 napi_gro_receive(&sky2->hw->napi, skb);
2492}
2493
bf15fe99
SH		 2494static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2495 unsigned packets, unsigned bytes)
2496{
2497 if (packets) {
2498 struct net_device *dev = hw->dev[port];
2499
2500 dev->stats.rx_packets += packets;
2501 dev->stats.rx_bytes += bytes;
2502 dev->last_rx = jiffies;
2503 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2504 }
2505}
2506
375c5688 2507static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2508{
2509 /* If this happens then driver assuming wrong format for chip type */
2510 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2511
2512 /* Both checksum counters are programmed to start at
2513 * the same offset, so unless there is a problem they
2514 * should match. This failure is an early indication that
2515 * hardware receive checksumming won't work.
2516 */
2517 if (likely((u16)(status >> 16) == (u16)status)) {
2518 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2519 skb->ip_summed = CHECKSUM_COMPLETE;
2520 skb->csum = le16_to_cpu(status);
2521 } else {
2522 dev_notice(&sky2->hw->pdev->dev,
2523 "%s: receive checksum problem (status = %#x)\n",
2524 sky2->netdev->name, status);
2525
2526 /* Disable checksum offload */
2527 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2528 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2529 BMU_DIS_RX_CHKSUM);
2530 }
2531}
2532
e07b1aa8 2533/* Process status response ring */
26691830 2534static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2535{
e07b1aa8 2536 int work_done = 0;
bf15fe99
SH		 2537 unsigned int total_bytes[2] = { 0 };
2538 unsigned int total_packets[2] = { 0 };
a8fd6266 2539
af2a58ac 2540 rmb();
26691830 2541 do {
55c9dd35 2542 struct sky2_port *sky2;
13210ce5 2543 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2544 unsigned port;
13210ce5 2545 struct net_device *dev;
cd28ab6a 2546 struct sk_buff *skb;
cd28ab6a
SH		 2547 u32 status;
2548 u16 length;
ab5adecb
SH		 2549 u8 opcode = le->opcode;
2550
2551 if (!(opcode & HW_OWNER))
2552 break;
cd28ab6a 2553
cb5d9547 2554 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2555
ab5adecb 2556 port = le->css & CSS_LINK_BIT;
69161611 2557 dev = hw->dev[port];
13210ce5 2558 sky2 = netdev_priv(dev);
f65b138c
SH		 2559 length = le16_to_cpu(le->length);
2560 status = le32_to_cpu(le->status);
cd28ab6a 2561
ab5adecb
SH		 2562 le->opcode = 0;
2563 switch (opcode & ~HW_OWNER) {
cd28ab6a 2564 case OP_RXSTAT:
bf15fe99
SH		 2565 total_packets[port]++;
2566 total_bytes[port] += length;
90c30335 2567
497d7c86 2568 skb = sky2_receive(dev, length, status);
90c30335 2569 if (!skb)
55c9dd35 2570 break;
13210ce5 2571
69161611 2572 /* This chip reports checksum status differently */
05745c4a 2573 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2574 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2575 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2576 (le->css & CSS_TCPUDPCSOK))
2577 skb->ip_summed = CHECKSUM_UNNECESSARY;
2578 else
2579 skb->ip_summed = CHECKSUM_NONE;
2580 }
2581
13210ce5 2582 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2583
37e5a243 2584 sky2_skb_rx(sky2, status, skb);
13210ce5 2585
22e11703 2586 /* Stop after net poll weight */
13210ce5 2587 if (++work_done >= to_do)
2588 goto exit_loop;
cd28ab6a
SH		 2589 break;
2590
d1f13708 2591#ifdef SKY2_VLAN_TAG_USED
2592 case OP_RXVLAN:
2593 sky2->rx_tag = length;
2594 break;
2595
2596 case OP_RXCHKSVLAN:
2597 sky2->rx_tag = length;
2598 /* fall through */
2599#endif
cd28ab6a 2600 case OP_RXCHKS:
375c5688 2601 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2602 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2603 break;
2604
2605 case OP_TXINDEXLE:
13b97b74 2606 /* TX index reports status for both ports */
f55925d7 2607 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2608 if (hw->dev[1])
2609 sky2_tx_done(hw->dev[1],
2610 ((status >> 24) & 0xff)
2611 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2612 break;
2613
cd28ab6a
SH		 2614 default:
2615 if (net_ratelimit())
ada1db5c 2616 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2617 }
26691830 2618 } while (hw->st_idx != idx);
cd28ab6a 2619
fe2a24df
SH		 2620 /* Fully processed status ring so clear irq */
2621 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2622
13210ce5 2623exit_loop:
bf15fe99
SH		 2624 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2625 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2626
e07b1aa8 2627 return work_done;
cd28ab6a
SH		 2628}
2629
2630static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2631{
2632 struct net_device *dev = hw->dev[port];
2633
3be92a70 2634 if (net_ratelimit())
ada1db5c 2635 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2636
2637 if (status & Y2_IS_PAR_RD1) {
3be92a70 2638 if (net_ratelimit())
ada1db5c 2639 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2640 /* Clear IRQ */
2641 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2642 }
2643
2644 if (status & Y2_IS_PAR_WR1) {
3be92a70 2645 if (net_ratelimit())
ada1db5c 2646 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2647
2648 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2649 }
2650
2651 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2652 if (net_ratelimit())
ada1db5c 2653 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2654 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2655 }
2656
2657 if (status & Y2_IS_PAR_RX1) {
3be92a70 2658 if (net_ratelimit())
ada1db5c 2659 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2660 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2661 }
2662
2663 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2664 if (net_ratelimit())
ada1db5c 2665 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2666 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2667 }
2668}
2669
2670static void sky2_hw_intr(struct sky2_hw *hw)
2671{
555382cb 2672 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2673 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2674 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2675
2676 status &= hwmsk;
cd28ab6a 2677
793b883e 2678 if (status & Y2_IS_TIST_OV)
cd28ab6a 2679 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2680
2681 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2682 u16 pci_err;
2683
a40ccc68 2684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2685 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2686 if (net_ratelimit())
555382cb 2687 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2688 pci_err);
cd28ab6a 2689
b32f40c4 2690 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2691 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2692 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2693 }
2694
2695 if (status & Y2_IS_PCI_EXP) {
d571b694 2696 /* PCI-Express uncorrectable Error occurred */
555382cb 2697 u32 err;
cd28ab6a 2698
a40ccc68 2699 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2700 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2701 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2702 0xfffffffful);
3be92a70 2703 if (net_ratelimit())
555382cb 2704 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2705
7782c8c4 2706 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2707 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2708 }
2709
2710 if (status & Y2_HWE_L1_MASK)
2711 sky2_hw_error(hw, 0, status);
2712 status >>= 8;
2713 if (status & Y2_HWE_L1_MASK)
2714 sky2_hw_error(hw, 1, status);
2715}
2716
2717static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2718{
2719 struct net_device *dev = hw->dev[port];
2720 struct sky2_port *sky2 = netdev_priv(dev);
2721 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2722
6c35abae 2723 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2724
a3caeada
SH		 2725 if (status & GM_IS_RX_CO_OV)
2726 gma_read16(hw, port, GM_RX_IRQ_SRC);
2727
2728 if (status & GM_IS_TX_CO_OV)
2729 gma_read16(hw, port, GM_TX_IRQ_SRC);
2730
cd28ab6a 2731 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2732 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2733 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2734 }
2735
2736 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2737 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2738 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2739 }
cd28ab6a
SH		 2740}
2741
40b01727 2742/* This should never happen it is a bug. */
c119731d 2743static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2744{
2745 struct net_device *dev = hw->dev[port];
c119731d 2746 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2747
ada1db5c 2748 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2749 dev->name, (unsigned) q, (unsigned) idx,
2750 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2751
40b01727 2752 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2753}
cd28ab6a 2754
75e80683
SH		 2755static int sky2_rx_hung(struct net_device *dev)
2756{
2757 struct sky2_port *sky2 = netdev_priv(dev);
2758 struct sky2_hw *hw = sky2->hw;
2759 unsigned port = sky2->port;
2760 unsigned rxq = rxqaddr[port];
2761 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2762 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2763 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2764 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2765
2766 /* If idle and MAC or PCI is stuck */
2767 if (sky2->check.last == dev->last_rx &&
2768 ((mac_rp == sky2->check.mac_rp &&
2769 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2770 /* Check if the PCI RX hang */
2771 (fifo_rp == sky2->check.fifo_rp &&
2772 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2773 netdev_printk(KERN_DEBUG, dev,
2774 "hung mac %d:%d fifo %d (%d:%d)\n",
2775 mac_lev, mac_rp, fifo_lev,
2776 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2777 return 1;
2778 } else {
2779 sky2->check.last = dev->last_rx;
2780 sky2->check.mac_rp = mac_rp;
2781 sky2->check.mac_lev = mac_lev;
2782 sky2->check.fifo_rp = fifo_rp;
2783 sky2->check.fifo_lev = fifo_lev;
2784 return 0;
2785 }
2786}
2787
32c2c300 2788static void sky2_watchdog(unsigned long arg)
d27ed387 2789{
01bd7564 2790 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2791
75e80683 2792 /* Check for lost IRQ once a second */
32c2c300 2793 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2794 napi_schedule(&hw->napi);
75e80683
SH		 2795 } else {
2796 int i, active = 0;
2797
2798 for (i = 0; i < hw->ports; i++) {
bea3348e 2799 struct net_device *dev = hw->dev[i];
75e80683
SH		 2800 if (!netif_running(dev))
2801 continue;
2802 ++active;
2803
2804 /* For chips with Rx FIFO, check if stuck */
39dbd958 2805 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 2806 sky2_rx_hung(dev)) {
ada1db5c 2807 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 2808 schedule_work(&hw->restart_work);
2809 return;
2810 }
2811 }
2812
2813 if (active == 0)
2814 return;
32c2c300 2815 }
01bd7564 2816
75e80683 2817 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2818}
2819
40b01727
SH		 2820/* Hardware/software error handling */
2821static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2822{
40b01727
SH		 2823 if (net_ratelimit())
2824 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2825
1e5f1283
SH		 2826 if (status & Y2_IS_HW_ERR)
2827 sky2_hw_intr(hw);
d257924e 2828
1e5f1283
SH		 2829 if (status & Y2_IS_IRQ_MAC1)
2830 sky2_mac_intr(hw, 0);
cd28ab6a 2831
1e5f1283
SH		 2832 if (status & Y2_IS_IRQ_MAC2)
2833 sky2_mac_intr(hw, 1);
cd28ab6a 2834
1e5f1283 2835 if (status & Y2_IS_CHK_RX1)
c119731d 2836 sky2_le_error(hw, 0, Q_R1);
d257924e 2837
1e5f1283 2838 if (status & Y2_IS_CHK_RX2)
c119731d 2839 sky2_le_error(hw, 1, Q_R2);
d257924e 2840
1e5f1283 2841 if (status & Y2_IS_CHK_TXA1)
c119731d 2842 sky2_le_error(hw, 0, Q_XA1);
d257924e 2843
1e5f1283 2844 if (status & Y2_IS_CHK_TXA2)
c119731d 2845 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2846}
2847
bea3348e 2848static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2849{
bea3348e 2850 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2851 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2852 int work_done = 0;
26691830 2853 u16 idx;
40b01727
SH		 2854
2855 if (unlikely(status & Y2_IS_ERROR))
2856 sky2_err_intr(hw, status);
2857
2858 if (status & Y2_IS_IRQ_PHY1)
2859 sky2_phy_intr(hw, 0);
2860
2861 if (status & Y2_IS_IRQ_PHY2)
2862 sky2_phy_intr(hw, 1);
cd28ab6a 2863
0f5aac70
SH		 2864 if (status & Y2_IS_PHY_QLNK)
2865 sky2_qlink_intr(hw);
2866
26691830
SH		 2867 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2868 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2869
2870 if (work_done >= work_limit)
26691830
SH		 2871 goto done;
2872 }
6f535763 2873
26691830
SH		 2874 napi_complete(napi);
2875 sky2_read32(hw, B0_Y2_SP_LISR);
2876done:
6f535763 2877
bea3348e 2878 return work_done;
e07b1aa8
SH		 2879}
2880
7d12e780 2881static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2882{
2883 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2884 u32 status;
2885
2886 /* Reading this mask interrupts as side effect */
2887 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2888 if (status == 0 || status == ~0)
2889 return IRQ_NONE;
793b883e 2890
e07b1aa8 2891 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2892
2893 napi_schedule(&hw->napi);
793b883e 2894
cd28ab6a
SH		 2895 return IRQ_HANDLED;
2896}
2897
2898#ifdef CONFIG_NET_POLL_CONTROLLER
2899static void sky2_netpoll(struct net_device *dev)
2900{
2901 struct sky2_port *sky2 = netdev_priv(dev);
2902
bea3348e 2903 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2904}
2905#endif
2906
2907/* Chip internal frequency for clock calculations */
05745c4a 2908static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2909{
793b883e 2910 switch (hw->chip_id) {
cd28ab6a 2911 case CHIP_ID_YUKON_EC:
5a5b1ea0 2912 case CHIP_ID_YUKON_EC_U:
93745494 2913 case CHIP_ID_YUKON_EX:
ed4d4161 2914 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2915 case CHIP_ID_YUKON_UL_2:
0f5aac70 2916 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2917 return 125;
2918
cd28ab6a 2919 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2920 return 100;
2921
2922 case CHIP_ID_YUKON_FE_P:
2923 return 50;
2924
2925 case CHIP_ID_YUKON_XL:
2926 return 156;
2927
2928 default:
2929 BUG();
cd28ab6a
SH		 2930 }
2931}
2932
fb17358f 2933static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2934{
fb17358f 2935 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2936}
2937
fb17358f 2938static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2939{
fb17358f 2940 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2941}
2942
fb17358f 2943
e3173832 2944static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2945{
b89165f2 2946 u8 t8;
cd28ab6a 2947
167f53d0 2948 /* Enable all clocks and check for bad PCI access */
b32f40c4 2949 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2950
cd28ab6a 2951 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2952
cd28ab6a 2953 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2954 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2955
2956 switch(hw->chip_id) {
2957 case CHIP_ID_YUKON_XL:
39dbd958 2958 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2959 break;
2960
2961 case CHIP_ID_YUKON_EC_U:
2962 hw->flags = SKY2_HW_GIGABIT
2963 | SKY2_HW_NEWER_PHY
2964 | SKY2_HW_ADV_POWER_CTL;
2965 break;
2966
2967 case CHIP_ID_YUKON_EX:
2968 hw->flags = SKY2_HW_GIGABIT
2969 | SKY2_HW_NEWER_PHY
2970 | SKY2_HW_NEW_LE
2971 | SKY2_HW_ADV_POWER_CTL;
2972
2973 /* New transmit checksum */
2974 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2975 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2976 break;
2977
2978 case CHIP_ID_YUKON_EC:
2979 /* This rev is really old, and requires untested workarounds */
2980 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2981 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2982 return -EOPNOTSUPP;
2983 }
39dbd958 2984 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2985 break;
2986
2987 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2988 break;
2989
05745c4a
SH		 2990 case CHIP_ID_YUKON_FE_P:
2991 hw->flags = SKY2_HW_NEWER_PHY
2992 | SKY2_HW_NEW_LE
2993 | SKY2_HW_AUTO_TX_SUM
2994 | SKY2_HW_ADV_POWER_CTL;
2995 break;
ed4d4161
SH		 2996
2997 case CHIP_ID_YUKON_SUPR:
2998 hw->flags = SKY2_HW_GIGABIT
2999 | SKY2_HW_NEWER_PHY
3000 | SKY2_HW_NEW_LE
3001 | SKY2_HW_AUTO_TX_SUM
3002 | SKY2_HW_ADV_POWER_CTL;
3003 break;
3004
0ce8b98d 3005 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3006 hw->flags = SKY2_HW_GIGABIT
3007 | SKY2_HW_ADV_POWER_CTL;
3008 break;
3009
0f5aac70 3010 case CHIP_ID_YUKON_OPT:
0ce8b98d 3011 hw->flags = SKY2_HW_GIGABIT
b338682d 3012 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3013 | SKY2_HW_ADV_POWER_CTL;
3014 break;
3015
ea76e635 3016 default:
b02a9258
SH		 3017 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3018 hw->chip_id);
cd28ab6a
SH		 3019 return -EOPNOTSUPP;
3020 }
3021
ea76e635
SH		 3022 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3023 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3024 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3025
e3173832
SH		 3026 hw->ports = 1;
3027 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3028 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3029 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3030 ++hw->ports;
3031 }
3032
74a61ebf
MM		 3033 if (sky2_read8(hw, B2_E_0))
3034 hw->flags |= SKY2_HW_RAM_BUFFER;
3035
e3173832
SH		 3036 return 0;
3037}
3038
3039static void sky2_reset(struct sky2_hw *hw)
3040{
555382cb 3041 struct pci_dev *pdev = hw->pdev;
e3173832 3042 u16 status;
555382cb
SH		 3043 int i, cap;
3044 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3045
cd28ab6a 3046 /* disable ASF */
acd12dde 3047 if (hw->chip_id == CHIP_ID_YUKON_EX
3048 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3049 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3050 status = sky2_read16(hw, HCU_CCSR);
3051 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3052 HCU_CCSR_UC_STATE_MSK);
acd12dde 3053 /*
3054 * CPU clock divider shouldn't be used because
3055 * - ASF firmware may malfunction
3056 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3057 */
3058 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3059 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3060 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3061 } else
3062 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3063 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3064
3065 /* do a SW reset */
3066 sky2_write8(hw, B0_CTST, CS_RST_SET);
3067 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3068
ac93a394
SH		 3069 /* allow writes to PCI config */
3070 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3071
cd28ab6a 3072 /* clear PCI errors, if any */
b32f40c4 3073 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3074 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3075 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3076
3077 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3078
555382cb
SH		 3079 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3080 if (cap) {
7782c8c4
SH		 3081 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3082 0xfffffffful);
555382cb
SH		 3083
3084 /* If error bit is stuck on ignore it */
3085 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3086 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3087 else
555382cb
SH		 3088 hwe_mask |= Y2_IS_PCI_EXP;
3089 }
cd28ab6a 3090
ae306cca 3091 sky2_power_on(hw);
a40ccc68 3092 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3093
3094 for (i = 0; i < hw->ports; i++) {
3095 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3096 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3097
ed4d4161
SH		 3098 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3099 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3100 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3101 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3102 | GMC_BYP_RETR_ON);
877c8570
SH		 3103
3104 }
3105
3106 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3107 /* enable MACSec clock gating */
3108 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3109 }
3110
0f5aac70
SH		 3111 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3112 u16 reg;
3113 u32 msk;
3114
3115 if (hw->chip_rev == 0) {
3116 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3117 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3118
3119 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3120 reg = 10;
3121 } else {
3122 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3123 reg = 3;
3124 }
3125
3126 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3127
3128 /* reset PHY Link Detect */
a40ccc68 3129 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3130 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3131 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3132 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3133
3134
3135 /* enable PHY Quick Link */
3136 msk = sky2_read32(hw, B0_IMSK);
3137 msk |= Y2_IS_PHY_QLNK;
3138 sky2_write32(hw, B0_IMSK, msk);
3139
3140 /* check if PSMv2 was running before */
3141 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3142 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3143 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3144 /* restore the PCIe Link Control register */
3145 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3146 }
a40ccc68 3147 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3148
3149 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3150 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3151 }
3152
793b883e
SH		 3153 /* Clear I2C IRQ noise */
3154 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3155
3156 /* turn off hardware timer (unused) */
3157 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3158 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3159
69634ee7
SH		 3160 /* Turn off descriptor polling */
3161 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3162
3163 /* Turn off receive timestamp */
3164 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3165 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3166
3167 /* enable the Tx Arbiters */
3168 for (i = 0; i < hw->ports; i++)
3169 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3170
3171 /* Initialize ram interface */
3172 for (i = 0; i < hw->ports; i++) {
793b883e 3173 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3174
3175 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3176 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3177 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3178 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3179 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3180 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3181 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3182 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3183 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3184 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3185 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3186 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3187 }
3188
555382cb 3189 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3190
cd28ab6a 3191 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3192 sky2_gmac_reset(hw, i);
cd28ab6a 3193
cd28ab6a
SH		 3194 memset(hw->st_le, 0, STATUS_LE_BYTES);
3195 hw->st_idx = 0;
3196
3197 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3198 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3199
3200 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3201 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3202
3203 /* Set the list last index */
793b883e 3204 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3205
290d4de5
SH		 3206 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3207 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3208
290d4de5
SH		 3209 /* set Status-FIFO ISR watermark */
3210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3211 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3212 else
3213 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3214
290d4de5 3215 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3216 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3217 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3218
793b883e 3219 /* enable status unit */
cd28ab6a
SH		 3220 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3221
3222 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3223 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3224 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3225}
3226
af18d8b8
SH		 3227/* Take device down (offline).
3228 * Equivalent to doing dev_stop() but this does not
3229 * inform upper layers of the transistion.
3230 */
3231static void sky2_detach(struct net_device *dev)
3232{
3233 if (netif_running(dev)) {
c36531b9 3234 netif_tx_lock(dev);
af18d8b8 3235 netif_device_detach(dev); /* stop txq */
c36531b9 3236 netif_tx_unlock(dev);
af18d8b8
SH		 3237 sky2_down(dev);
3238 }
3239}
3240
3241/* Bring device back after doing sky2_detach */
3242static int sky2_reattach(struct net_device *dev)
3243{
3244 int err = 0;
3245
3246 if (netif_running(dev)) {
3247 err = sky2_up(dev);
3248 if (err) {
ada1db5c 3249 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3250 dev_close(dev);
3251 } else {
3252 netif_device_attach(dev);
3253 sky2_set_multicast(dev);
3254 }
3255 }
3256
3257 return err;
3258}
3259
81906791
SH		 3260static void sky2_restart(struct work_struct *work)
3261{
3262 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
8a0c9228 3263 u32 imask;
af18d8b8 3264 int i;
81906791 3265
81906791 3266 rtnl_lock();
81906791 3267
8cfcbe99 3268 napi_disable(&hw->napi);
8a0c9228
MM		 3269 synchronize_irq(hw->pdev->irq);
3270 imask = sky2_read32(hw, B0_IMSK);
8cfcbe99 3271 sky2_write32(hw, B0_IMSK, 0);
8a0c9228
MM		 3272
3273 for (i = 0; i < hw->ports; i++) {
3274 struct net_device *dev = hw->dev[i];
3275 struct sky2_port *sky2 = netdev_priv(dev);
3276
3277 if (!netif_running(dev))
3278 continue;
3279
3280 netif_carrier_off(dev);
3281 netif_tx_disable(dev);
3282 sky2_hw_down(sky2);
3283 }
3284
81906791 3285 sky2_reset(hw);
81906791 3286
8a0c9228
MM		 3287 for (i = 0; i < hw->ports; i++) {
3288 struct net_device *dev = hw->dev[i];
3289 struct sky2_port *sky2 = netdev_priv(dev);
3290
3291 if (!netif_running(dev))
3292 continue;
3293
3294 sky2_hw_up(sky2);
3295 netif_wake_queue(dev);
3296 }
3297
3298 sky2_write32(hw, B0_IMSK, imask);
3299 sky2_read32(hw, B0_IMSK);
3300
3301 sky2_read32(hw, B0_Y2_SP_LISR);
3302 napi_enable(&hw->napi);
81906791 3303
81906791
SH		 3304 rtnl_unlock();
3305}
3306
e3173832
SH		 3307static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3308{
3309 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3310}
3311
3312static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3313{
3314 const struct sky2_port *sky2 = netdev_priv(dev);
3315
3316 wol->supported = sky2_wol_supported(sky2->hw);
3317 wol->wolopts = sky2->wol;
3318}
3319
3320static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3321{
3322 struct sky2_port *sky2 = netdev_priv(dev);
3323 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3324
8e95a202
JP		 3325 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3326 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3327 return -EOPNOTSUPP;
3328
3329 sky2->wol = wol->wolopts;
cd28ab6a
SH		 3330 return 0;
3331}
3332
28bd181a 3333static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3334{
b89165f2
SH		 3335 if (sky2_is_copper(hw)) {
3336 u32 modes = SUPPORTED_10baseT_Half
3337 | SUPPORTED_10baseT_Full
3338 | SUPPORTED_100baseT_Half
3339 | SUPPORTED_100baseT_Full
3340 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3341
ea76e635 3342 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3343 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3344 | SUPPORTED_1000baseT_Full;
3345 return modes;
cd28ab6a 3346 } else
b89165f2
SH		 3347 return SUPPORTED_1000baseT_Half
3348 | SUPPORTED_1000baseT_Full
3349 | SUPPORTED_Autoneg
3350 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3351}
3352
793b883e 3353static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3354{
3355 struct sky2_port *sky2 = netdev_priv(dev);
3356 struct sky2_hw *hw = sky2->hw;
3357
3358 ecmd->transceiver = XCVR_INTERNAL;
3359 ecmd->supported = sky2_supported_modes(hw);
3360 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3361 if (sky2_is_copper(hw)) {
cd28ab6a 3362 ecmd->port = PORT_TP;
b89165f2
SH		 3363 ecmd->speed = sky2->speed;
3364 } else {
3365 ecmd->speed = SPEED_1000;
cd28ab6a 3366 ecmd->port = PORT_FIBRE;
b89165f2 3367 }
cd28ab6a
SH		 3368
3369 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3370 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3371 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3372 ecmd->duplex = sky2->duplex;
3373 return 0;
3374}
3375
3376static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3377{
3378 struct sky2_port *sky2 = netdev_priv(dev);
3379 const struct sky2_hw *hw = sky2->hw;
3380 u32 supported = sky2_supported_modes(hw);
3381
3382 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3383 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3384 ecmd->advertising = supported;
3385 sky2->duplex = -1;
3386 sky2->speed = -1;
3387 } else {
3388 u32 setting;
3389
793b883e 3390 switch (ecmd->speed) {
cd28ab6a
SH		 3391 case SPEED_1000:
3392 if (ecmd->duplex == DUPLEX_FULL)
3393 setting = SUPPORTED_1000baseT_Full;
3394 else if (ecmd->duplex == DUPLEX_HALF)
3395 setting = SUPPORTED_1000baseT_Half;
3396 else
3397 return -EINVAL;
3398 break;
3399 case SPEED_100:
3400 if (ecmd->duplex == DUPLEX_FULL)
3401 setting = SUPPORTED_100baseT_Full;
3402 else if (ecmd->duplex == DUPLEX_HALF)
3403 setting = SUPPORTED_100baseT_Half;
3404 else
3405 return -EINVAL;
3406 break;
3407
3408 case SPEED_10:
3409 if (ecmd->duplex == DUPLEX_FULL)
3410 setting = SUPPORTED_10baseT_Full;
3411 else if (ecmd->duplex == DUPLEX_HALF)
3412 setting = SUPPORTED_10baseT_Half;
3413 else
3414 return -EINVAL;
3415 break;
3416 default:
3417 return -EINVAL;
3418 }
3419
3420 if ((setting & supported) == 0)
3421 return -EINVAL;
3422
3423 sky2->speed = ecmd->speed;
3424 sky2->duplex = ecmd->duplex;
0ea065e5 3425 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3426 }
3427
cd28ab6a
SH		 3428 sky2->advertising = ecmd->advertising;
3429
d1b139c0 3430 if (netif_running(dev)) {
1b537565 3431 sky2_phy_reinit(sky2);
d1b139c0
SH		 3432 sky2_set_multicast(dev);
3433 }
cd28ab6a
SH		 3434
3435 return 0;
3436}
3437
3438static void sky2_get_drvinfo(struct net_device *dev,
3439 struct ethtool_drvinfo *info)
3440{
3441 struct sky2_port *sky2 = netdev_priv(dev);
3442
3443 strcpy(info->driver, DRV_NAME);
3444 strcpy(info->version, DRV_VERSION);
3445 strcpy(info->fw_version, "N/A");
3446 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3447}
3448
3449static const struct sky2_stat {
793b883e
SH		 3450 char name[ETH_GSTRING_LEN];
3451 u16 offset;
cd28ab6a
SH		 3452} sky2_stats[] = {
3453 { "tx_bytes", GM_TXO_OK_HI },
3454 { "rx_bytes", GM_RXO_OK_HI },
3455 { "tx_broadcast", GM_TXF_BC_OK },
3456 { "rx_broadcast", GM_RXF_BC_OK },
3457 { "tx_multicast", GM_TXF_MC_OK },
3458 { "rx_multicast", GM_RXF_MC_OK },
3459 { "tx_unicast", GM_TXF_UC_OK },
3460 { "rx_unicast", GM_RXF_UC_OK },
3461 { "tx_mac_pause", GM_TXF_MPAUSE },
3462 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3463 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3464 { "late_collision",GM_TXF_LAT_COL },
3465 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3466 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3467 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3468
d2604540 3469 { "rx_short", GM_RXF_SHT },
cd28ab6a 3470 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3471 { "rx_64_byte_packets", GM_RXF_64B },
3472 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3473 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3474 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3475 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3476 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3477 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3478 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3479 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3480 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3481 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3482
3483 { "tx_64_byte_packets", GM_TXF_64B },
3484 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3485 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3486 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3487 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3488 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3489 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3490 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3491};
3492
cd28ab6a
SH		 3493static u32 sky2_get_rx_csum(struct net_device *dev)
3494{
3495 struct sky2_port *sky2 = netdev_priv(dev);
3496
0ea065e5 3497 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3498}
3499
3500static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3501{
3502 struct sky2_port *sky2 = netdev_priv(dev);
3503
0ea065e5
SH		 3504 if (data)
3505 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3506 else
3507 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3508
cd28ab6a
SH		 3509 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3510 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3511
3512 return 0;
3513}
3514
3515static u32 sky2_get_msglevel(struct net_device *netdev)
3516{
3517 struct sky2_port *sky2 = netdev_priv(netdev);
3518 return sky2->msg_enable;
3519}
3520
9a7ae0a9
SH		 3521static int sky2_nway_reset(struct net_device *dev)
3522{
3523 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3524
0ea065e5 3525 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3526 return -EINVAL;
3527
1b537565 3528 sky2_phy_reinit(sky2);
d1b139c0 3529 sky2_set_multicast(dev);
9a7ae0a9
SH		 3530
3531 return 0;
3532}
3533
793b883e 3534static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3535{
3536 struct sky2_hw *hw = sky2->hw;
3537 unsigned port = sky2->port;
3538 int i;
3539
3540 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3541 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3542 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3543 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3544
793b883e 3545 for (i = 2; i < count; i++)
cd28ab6a
SH		 3546 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3547}
3548
cd28ab6a
SH		 3549static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3550{
3551 struct sky2_port *sky2 = netdev_priv(netdev);
3552 sky2->msg_enable = value;
3553}
3554
b9f2c044 3555static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3556{
b9f2c044
JG		 3557 switch (sset) {
3558 case ETH_SS_STATS:
3559 return ARRAY_SIZE(sky2_stats);
3560 default:
3561 return -EOPNOTSUPP;
3562 }
cd28ab6a
SH		 3563}
3564
3565static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3566 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3567{
3568 struct sky2_port *sky2 = netdev_priv(dev);
3569
793b883e 3570 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3571}
3572
793b883e 3573static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3574{
3575 int i;
3576
3577 switch (stringset) {
3578 case ETH_SS_STATS:
3579 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3580 memcpy(data + i * ETH_GSTRING_LEN,
3581 sky2_stats[i].name, ETH_GSTRING_LEN);
3582 break;
3583 }
3584}
3585
cd28ab6a
SH		 3586static int sky2_set_mac_address(struct net_device *dev, void *p)
3587{
3588 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3589 struct sky2_hw *hw = sky2->hw;
3590 unsigned port = sky2->port;
3591 const struct sockaddr *addr = p;
cd28ab6a
SH		 3592
3593 if (!is_valid_ether_addr(addr->sa_data))
3594 return -EADDRNOTAVAIL;
3595
cd28ab6a 3596 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3597 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3598 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3599 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3600 dev->dev_addr, ETH_ALEN);
1b537565 3601
a8ab1ec0
SH		 3602 /* virtual address for data */
3603 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3604
3605 /* physical address: used for pause frames */
3606 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3607
3608 return 0;
cd28ab6a
SH		 3609}
3610
a052b52f
SH		 3611static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3612{
3613 u32 bit;
3614
3615 bit = ether_crc(ETH_ALEN, addr) & 63;
3616 filter[bit >> 3] |= 1 << (bit & 7);
3617}
3618
cd28ab6a
SH		 3619static void sky2_set_multicast(struct net_device *dev)
3620{
3621 struct sky2_port *sky2 = netdev_priv(dev);
3622 struct sky2_hw *hw = sky2->hw;
3623 unsigned port = sky2->port;
5508590c 3624 struct dev_mc_list *list;
cd28ab6a
SH		 3625 u16 reg;
3626 u8 filter[8];
a052b52f
SH		 3627 int rx_pause;
3628 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3629
a052b52f 3630 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3631 memset(filter, 0, sizeof(filter));
3632
3633 reg = gma_read16(hw, port, GM_RX_CTRL);
3634 reg |= GM_RXCR_UCF_ENA;
3635
d571b694 3636 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3637 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3638 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3639 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3640 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3641 reg &= ~GM_RXCR_MCF_ENA;
3642 else {
cd28ab6a
SH		 3643 reg |= GM_RXCR_MCF_ENA;
3644
a052b52f
SH		 3645 if (rx_pause)
3646 sky2_add_filter(filter, pause_mc_addr);
3647
5508590c 3648 netdev_for_each_mc_addr(list, dev)
a052b52f 3649 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3650 }
3651
cd28ab6a 3652 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3653 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3654 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3655 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3656 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3657 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3658 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3659 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3660
3661 gma_write16(hw, port, GM_RX_CTRL, reg);
3662}
3663
3664/* Can have one global because blinking is controlled by
3665 * ethtool and that is always under RTNL mutex
3666 */
a84d0a3d 3667static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3668{
a84d0a3d
SH		 3669 struct sky2_hw *hw = sky2->hw;
3670 unsigned port = sky2->port;
793b883e 3671
a84d0a3d
SH		 3672 spin_lock_bh(&sky2->phy_lock);
3673 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3674 hw->chip_id == CHIP_ID_YUKON_EX ||
3675 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3676 u16 pg;
793b883e
SH		 3677 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3679
a84d0a3d
SH		 3680 switch (mode) {
3681 case MO_LED_OFF:
3682 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3683 PHY_M_LEDC_LOS_CTRL(8) |
3684 PHY_M_LEDC_INIT_CTRL(8) |
3685 PHY_M_LEDC_STA1_CTRL(8) |
3686 PHY_M_LEDC_STA0_CTRL(8));
3687 break;
3688 case MO_LED_ON:
3689 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3690 PHY_M_LEDC_LOS_CTRL(9) |
3691 PHY_M_LEDC_INIT_CTRL(9) |
3692 PHY_M_LEDC_STA1_CTRL(9) |
3693 PHY_M_LEDC_STA0_CTRL(9));
3694 break;
3695 case MO_LED_BLINK:
3696 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3697 PHY_M_LEDC_LOS_CTRL(0xa) |
3698 PHY_M_LEDC_INIT_CTRL(0xa) |
3699 PHY_M_LEDC_STA1_CTRL(0xa) |
3700 PHY_M_LEDC_STA0_CTRL(0xa));
3701 break;
3702 case MO_LED_NORM:
3703 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3704 PHY_M_LEDC_LOS_CTRL(1) |
3705 PHY_M_LEDC_INIT_CTRL(8) |
3706 PHY_M_LEDC_STA1_CTRL(7) |
3707 PHY_M_LEDC_STA0_CTRL(7));
3708 }
793b883e 3709
a84d0a3d
SH		 3710 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3711 } else
7d2e3cb7 3712 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3713 PHY_M_LED_MO_DUP(mode) |
3714 PHY_M_LED_MO_10(mode) |
3715 PHY_M_LED_MO_100(mode) |
3716 PHY_M_LED_MO_1000(mode) |
3717 PHY_M_LED_MO_RX(mode) |
3718 PHY_M_LED_MO_TX(mode));
3719
3720 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3721}
3722
3723/* blink LED's for finding board */
3724static int sky2_phys_id(struct net_device *dev, u32 data)
3725{
3726 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3727 unsigned int i;
cd28ab6a 3728
a84d0a3d
SH		 3729 if (data == 0)
3730 data = UINT_MAX;
cd28ab6a 3731
a84d0a3d
SH		 3732 for (i = 0; i < data; i++) {
3733 sky2_led(sky2, MO_LED_ON);
3734 if (msleep_interruptible(500))
3735 break;
3736 sky2_led(sky2, MO_LED_OFF);
3737 if (msleep_interruptible(500))
3738 break;
793b883e 3739 }
a84d0a3d 3740 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3741
3742 return 0;
3743}
3744
3745static void sky2_get_pauseparam(struct net_device *dev,
3746 struct ethtool_pauseparam *ecmd)
3747{
3748 struct sky2_port *sky2 = netdev_priv(dev);
3749
16ad91e1
SH		 3750 switch (sky2->flow_mode) {
3751 case FC_NONE:
3752 ecmd->tx_pause = ecmd->rx_pause = 0;
3753 break;
3754 case FC_TX:
3755 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3756 break;
3757 case FC_RX:
3758 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3759 break;
3760 case FC_BOTH:
3761 ecmd->tx_pause = ecmd->rx_pause = 1;
3762 }
3763
0ea065e5
SH		 3764 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3765 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3766}
3767
3768static int sky2_set_pauseparam(struct net_device *dev,
3769 struct ethtool_pauseparam *ecmd)
3770{
3771 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3772
0ea065e5
SH		 3773 if (ecmd->autoneg == AUTONEG_ENABLE)
3774 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3775 else
3776 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3777
16ad91e1 3778 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3779
16ad91e1
SH		 3780 if (netif_running(dev))
3781 sky2_phy_reinit(sky2);
cd28ab6a 3782
2eaba1a2 3783 return 0;
cd28ab6a
SH		 3784}
3785
fb17358f
SH		 3786static int sky2_get_coalesce(struct net_device *dev,
3787 struct ethtool_coalesce *ecmd)
3788{
3789 struct sky2_port *sky2 = netdev_priv(dev);
3790 struct sky2_hw *hw = sky2->hw;
3791
3792 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3793 ecmd->tx_coalesce_usecs = 0;
3794 else {
3795 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3796 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3797 }
3798 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3799
3800 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3801 ecmd->rx_coalesce_usecs = 0;
3802 else {
3803 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3804 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3805 }
3806 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3807
3808 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3809 ecmd->rx_coalesce_usecs_irq = 0;
3810 else {
3811 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3812 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3813 }
3814
3815 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3816
3817 return 0;
3818}
3819
3820/* Note: this affect both ports */
3821static int sky2_set_coalesce(struct net_device *dev,
3822 struct ethtool_coalesce *ecmd)
3823{
3824 struct sky2_port *sky2 = netdev_priv(dev);
3825 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3826 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3827
77b3d6a2
SH		 3828 if (ecmd->tx_coalesce_usecs > tmax ||
3829 ecmd->rx_coalesce_usecs > tmax ||
3830 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3831 return -EINVAL;
3832
ee5f68fe 3833 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3834 return -EINVAL;
ff81fbbe 3835 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3836 return -EINVAL;
ff81fbbe 3837 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3838 return -EINVAL;
3839
3840 if (ecmd->tx_coalesce_usecs == 0)
3841 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3842 else {
3843 sky2_write32(hw, STAT_TX_TIMER_INI,
3844 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3845 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3846 }
3847 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3848
3849 if (ecmd->rx_coalesce_usecs == 0)
3850 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3851 else {
3852 sky2_write32(hw, STAT_LEV_TIMER_INI,
3853 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3854 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3855 }
3856 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3857
3858 if (ecmd->rx_coalesce_usecs_irq == 0)
3859 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3860 else {
d28d4870 3861 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3862 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3863 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3864 }
3865 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3866 return 0;
3867}
3868
793b883e
SH		 3869static void sky2_get_ringparam(struct net_device *dev,
3870 struct ethtool_ringparam *ering)
3871{
3872 struct sky2_port *sky2 = netdev_priv(dev);
3873
3874 ering->rx_max_pending = RX_MAX_PENDING;
3875 ering->rx_mini_max_pending = 0;
3876 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3877 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3878
3879 ering->rx_pending = sky2->rx_pending;
3880 ering->rx_mini_pending = 0;
3881 ering->rx_jumbo_pending = 0;
3882 ering->tx_pending = sky2->tx_pending;
3883}
3884
3885static int sky2_set_ringparam(struct net_device *dev,
3886 struct ethtool_ringparam *ering)
3887{
3888 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3889
3890 if (ering->rx_pending > RX_MAX_PENDING ||
3891 ering->rx_pending < 8 ||
ee5f68fe
SH		 3892 ering->tx_pending < TX_MIN_PENDING ||
3893 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3894 return -EINVAL;
3895
af18d8b8 3896 sky2_detach(dev);
793b883e
SH		 3897
3898 sky2->rx_pending = ering->rx_pending;
3899 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3900 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3901
af18d8b8 3902 return sky2_reattach(dev);
793b883e
SH		 3903}
3904
793b883e
SH		 3905static int sky2_get_regs_len(struct net_device *dev)
3906{
6e4cbb34 3907 return 0x4000;
793b883e
SH		 3908}
3909
c32bbff8
MM		 3910static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3911{
3912 /* This complicated switch statement is to make sure and
3913 * only access regions that are unreserved.
3914 * Some blocks are only valid on dual port cards.
3915 */
3916 switch (b) {
3917 /* second port */
3918 case 5: /* Tx Arbiter 2 */
3919 case 9: /* RX2 */
3920 case 14 ... 15: /* TX2 */
3921 case 17: case 19: /* Ram Buffer 2 */
3922 case 22 ... 23: /* Tx Ram Buffer 2 */
3923 case 25: /* Rx MAC Fifo 1 */
3924 case 27: /* Tx MAC Fifo 2 */
3925 case 31: /* GPHY 2 */
3926 case 40 ... 47: /* Pattern Ram 2 */
3927 case 52: case 54: /* TCP Segmentation 2 */
3928 case 112 ... 116: /* GMAC 2 */
3929 return hw->ports > 1;
3930
3931 case 0: /* Control */
3932 case 2: /* Mac address */
3933 case 4: /* Tx Arbiter 1 */
3934 case 7: /* PCI express reg */
3935 case 8: /* RX1 */
3936 case 12 ... 13: /* TX1 */
3937 case 16: case 18:/* Rx Ram Buffer 1 */
3938 case 20 ... 21: /* Tx Ram Buffer 1 */
3939 case 24: /* Rx MAC Fifo 1 */
3940 case 26: /* Tx MAC Fifo 1 */
3941 case 28 ... 29: /* Descriptor and status unit */
3942 case 30: /* GPHY 1*/
3943 case 32 ... 39: /* Pattern Ram 1 */
3944 case 48: case 50: /* TCP Segmentation 1 */
3945 case 56 ... 60: /* PCI space */
3946 case 80 ... 84: /* GMAC 1 */
3947 return 1;
3948
3949 default:
3950 return 0;
3951 }
3952}
3953
793b883e
SH		 3954/*
3955 * Returns copy of control register region
3ead5db7 3956 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3957 */
3958static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3959 void *p)
3960{
3961 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3962 const void __iomem *io = sky2->hw->regs;
295b54c4 3963 unsigned int b;
793b883e
SH		 3964
3965 regs->version = 1;
793b883e 3966
295b54c4 3967 for (b = 0; b < 128; b++) {
c32bbff8
MM		 3968 /* skip poisonous diagnostic ram region in block 3 */
3969 if (b == 3)
295b54c4 3970 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 3971 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 3972 memcpy_fromio(p, io, 128);
c32bbff8 3973 else
295b54c4 3974 memset(p, 0, 128);
3ead5db7 3975
295b54c4
SH		 3976 p += 128;
3977 io += 128;
3978 }
793b883e 3979}
cd28ab6a 3980
b628ed98
SH		 3981/* In order to do Jumbo packets on these chips, need to turn off the
3982 * transmit store/forward. Therefore checksum offload won't work.
3983 */
3984static int no_tx_offload(struct net_device *dev)
3985{
3986 const struct sky2_port *sky2 = netdev_priv(dev);
3987 const struct sky2_hw *hw = sky2->hw;
3988
69161611 3989 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3990}
3991
3992static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3993{
3994 if (data && no_tx_offload(dev))
3995 return -EINVAL;
3996
3997 return ethtool_op_set_tx_csum(dev, data);
3998}
3999
4000
4001static int sky2_set_tso(struct net_device *dev, u32 data)
4002{
4003 if (data && no_tx_offload(dev))
4004 return -EINVAL;
4005
4006 return ethtool_op_set_tso(dev, data);
4007}
4008
f4331a6d
SH		 4009static int sky2_get_eeprom_len(struct net_device *dev)
4010{
4011 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4012 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4013 u16 reg2;
4014
b32f40c4 4015 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4016 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4017}
4018
1413235c 4019static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4020{
1413235c 4021 unsigned long start = jiffies;
f4331a6d 4022
1413235c
SH		 4023 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4024 /* Can take up to 10.6 ms for write */
4025 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4026 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4027 return -ETIMEDOUT;
4028 }
4029 mdelay(1);
4030 }
167f53d0 4031
1413235c
SH		 4032 return 0;
4033}
167f53d0 4034
1413235c
SH		 4035static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4036 u16 offset, size_t length)
4037{
4038 int rc = 0;
4039
4040 while (length > 0) {
4041 u32 val;
4042
4043 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4044 rc = sky2_vpd_wait(hw, cap, 0);
4045 if (rc)
4046 break;
4047
4048 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4049
4050 memcpy(data, &val, min(sizeof(val), length));
4051 offset += sizeof(u32);
4052 data += sizeof(u32);
4053 length -= sizeof(u32);
4054 }
4055
4056 return rc;
f4331a6d
SH		 4057}
4058
1413235c
SH		 4059static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4060 u16 offset, unsigned int length)
f4331a6d 4061{
1413235c
SH		 4062 unsigned int i;
4063 int rc = 0;
4064
4065 for (i = 0; i < length; i += sizeof(u32)) {
4066 u32 val = *(u32 *)(data + i);
4067
4068 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4069 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4070
4071 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4072 if (rc)
4073 break;
4074 }
4075 return rc;
f4331a6d
SH		 4076}
4077
4078static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4079 u8 *data)
4080{
4081 struct sky2_port *sky2 = netdev_priv(dev);
4082 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4083
4084 if (!cap)
4085 return -EINVAL;
4086
4087 eeprom->magic = SKY2_EEPROM_MAGIC;
4088
1413235c 4089 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4090}
4091
4092static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4093 u8 *data)
4094{
4095 struct sky2_port *sky2 = netdev_priv(dev);
4096 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4097
4098 if (!cap)
4099 return -EINVAL;
4100
4101 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4102 return -EINVAL;
4103
1413235c
SH		 4104 /* Partial writes not supported */
4105 if ((eeprom->offset & 3) || (eeprom->len & 3))
4106 return -EINVAL;
f4331a6d 4107
1413235c 4108 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4109}
4110
4111
7282d491 4112static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4113 .get_settings = sky2_get_settings,
4114 .set_settings = sky2_set_settings,
4115 .get_drvinfo = sky2_get_drvinfo,
4116 .get_wol = sky2_get_wol,
4117 .set_wol = sky2_set_wol,
4118 .get_msglevel = sky2_get_msglevel,
4119 .set_msglevel = sky2_set_msglevel,
4120 .nway_reset = sky2_nway_reset,
4121 .get_regs_len = sky2_get_regs_len,
4122 .get_regs = sky2_get_regs,
4123 .get_link = ethtool_op_get_link,
4124 .get_eeprom_len = sky2_get_eeprom_len,
4125 .get_eeprom = sky2_get_eeprom,
4126 .set_eeprom = sky2_set_eeprom,
f4331a6d 4127 .set_sg = ethtool_op_set_sg,
f4331a6d 4128 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4129 .set_tso = sky2_set_tso,
4130 .get_rx_csum = sky2_get_rx_csum,
4131 .set_rx_csum = sky2_set_rx_csum,
4132 .get_strings = sky2_get_strings,
4133 .get_coalesce = sky2_get_coalesce,
4134 .set_coalesce = sky2_set_coalesce,
4135 .get_ringparam = sky2_get_ringparam,
4136 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4137 .get_pauseparam = sky2_get_pauseparam,
4138 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4139 .phys_id = sky2_phys_id,
b9f2c044 4140 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4141 .get_ethtool_stats = sky2_get_ethtool_stats,
4142};
4143
3cf26753
SH		 4144#ifdef CONFIG_SKY2_DEBUG
4145
4146static struct dentry *sky2_debug;
4147
e4c2abe2
SH		 4148
4149/*
4150 * Read and parse the first part of Vital Product Data
4151 */
4152#define VPD_SIZE 128
4153#define VPD_MAGIC 0x82
4154
4155static const struct vpd_tag {
4156 char tag[2];
4157 char *label;
4158} vpd_tags[] = {
4159 { "PN", "Part Number" },
4160 { "EC", "Engineering Level" },
4161 { "MN", "Manufacturer" },
4162 { "SN", "Serial Number" },
4163 { "YA", "Asset Tag" },
4164 { "VL", "First Error Log Message" },
4165 { "VF", "Second Error Log Message" },
4166 { "VB", "Boot Agent ROM Configuration" },
4167 { "VE", "EFI UNDI Configuration" },
4168};
4169
4170static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4171{
4172 size_t vpd_size;
4173 loff_t offs;
4174 u8 len;
4175 unsigned char *buf;
4176 u16 reg2;
4177
4178 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4179 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4180
4181 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4182 buf = kmalloc(vpd_size, GFP_KERNEL);
4183 if (!buf) {
4184 seq_puts(seq, "no memory!\n");
4185 return;
4186 }
4187
4188 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4189 seq_puts(seq, "VPD read failed\n");
4190 goto out;
4191 }
4192
4193 if (buf[0] != VPD_MAGIC) {
4194 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4195 goto out;
4196 }
4197 len = buf[1];
4198 if (len == 0 || len > vpd_size - 4) {
4199 seq_printf(seq, "Invalid id length: %d\n", len);
4200 goto out;
4201 }
4202
4203 seq_printf(seq, "%.*s\n", len, buf + 3);
4204 offs = len + 3;
4205
4206 while (offs < vpd_size - 4) {
4207 int i;
4208
4209 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4210 break;
4211 len = buf[offs + 2];
4212 if (offs + len + 3 >= vpd_size)
4213 break;
4214
4215 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4216 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4217 seq_printf(seq, " %s: %.*s\n",
4218 vpd_tags[i].label, len, buf + offs + 3);
4219 break;
4220 }
4221 }
4222 offs += len + 3;
4223 }
4224out:
4225 kfree(buf);
4226}
4227
3cf26753
SH		 4228static int sky2_debug_show(struct seq_file *seq, void *v)
4229{
4230 struct net_device *dev = seq->private;
4231 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4232 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4233 unsigned port = sky2->port;
4234 unsigned idx, last;
4235 int sop;
4236
e4c2abe2 4237 sky2_show_vpd(seq, hw);
3cf26753 4238
e4c2abe2 4239 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4240 sky2_read32(hw, B0_ISRC),
4241 sky2_read32(hw, B0_IMSK),
4242 sky2_read32(hw, B0_Y2_SP_ICR));
4243
e4c2abe2
SH		 4244 if (!netif_running(dev)) {
4245 seq_printf(seq, "network not running\n");
4246 return 0;
4247 }
4248
bea3348e 4249 napi_disable(&hw->napi);
3cf26753
SH		 4250 last = sky2_read16(hw, STAT_PUT_IDX);
4251
4252 if (hw->st_idx == last)
4253 seq_puts(seq, "Status ring (empty)\n");
4254 else {
4255 seq_puts(seq, "Status ring\n");
4256 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4257 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4258 const struct sky2_status_le *le = hw->st_le + idx;
4259 seq_printf(seq, "[%d] %#x %d %#x\n",
4260 idx, le->opcode, le->length, le->status);
4261 }
4262 seq_puts(seq, "\n");
4263 }
4264
4265 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4266 sky2->tx_cons, sky2->tx_prod,
4267 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4268 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4269
4270 /* Dump contents of tx ring */
4271 sop = 1;
ee5f68fe
SH		 4272 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4273 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4274 const struct sky2_tx_le *le = sky2->tx_le + idx;
4275 u32 a = le32_to_cpu(le->addr);
4276
4277 if (sop)
4278 seq_printf(seq, "%u:", idx);
4279 sop = 0;
4280
4281 switch(le->opcode & ~HW_OWNER) {
4282 case OP_ADDR64:
4283 seq_printf(seq, " %#x:", a);
4284 break;
4285 case OP_LRGLEN:
4286 seq_printf(seq, " mtu=%d", a);
4287 break;
4288 case OP_VLAN:
4289 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4290 break;
4291 case OP_TCPLISW:
4292 seq_printf(seq, " csum=%#x", a);
4293 break;
4294 case OP_LARGESEND:
4295 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4296 break;
4297 case OP_PACKET:
4298 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4299 break;
4300 case OP_BUFFER:
4301 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4302 break;
4303 default:
4304 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4305 a, le16_to_cpu(le->length));
4306 }
4307
4308 if (le->ctrl & EOP) {
4309 seq_putc(seq, '\n');
4310 sop = 1;
4311 }
4312 }
4313
4314 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4315 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4316 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4317 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4318
d1d08d12 4319 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4320 napi_enable(&hw->napi);
3cf26753
SH		 4321 return 0;
4322}
4323
4324static int sky2_debug_open(struct inode *inode, struct file *file)
4325{
4326 return single_open(file, sky2_debug_show, inode->i_private);
4327}
4328
4329static const struct file_operations sky2_debug_fops = {
4330 .owner = THIS_MODULE,
4331 .open = sky2_debug_open,
4332 .read = seq_read,
4333 .llseek = seq_lseek,
4334 .release = single_release,
4335};
4336
4337/*
4338 * Use network device events to create/remove/rename
4339 * debugfs file entries
4340 */
4341static int sky2_device_event(struct notifier_block *unused,
4342 unsigned long event, void *ptr)
4343{
4344 struct net_device *dev = ptr;
5b296bc9 4345 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4346
1436b301 4347 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4348 return NOTIFY_DONE;
3cf26753 4349
5b296bc9
SH		 4350 switch(event) {
4351 case NETDEV_CHANGENAME:
4352 if (sky2->debugfs) {
4353 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4354 sky2_debug, dev->name);
4355 }
4356 break;
3cf26753 4357
5b296bc9
SH		 4358 case NETDEV_GOING_DOWN:
4359 if (sky2->debugfs) {
ada1db5c 4360 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4361 debugfs_remove(sky2->debugfs);
4362 sky2->debugfs = NULL;
3cf26753 4363 }
5b296bc9
SH		 4364 break;
4365
4366 case NETDEV_UP:
4367 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4368 sky2_debug, dev,
4369 &sky2_debug_fops);
4370 if (IS_ERR(sky2->debugfs))
4371 sky2->debugfs = NULL;
3cf26753
SH		 4372 }
4373
4374 return NOTIFY_DONE;
4375}
4376
4377static struct notifier_block sky2_notifier = {
4378 .notifier_call = sky2_device_event,
4379};
4380
4381
4382static __init void sky2_debug_init(void)
4383{
4384 struct dentry *ent;
4385
4386 ent = debugfs_create_dir("sky2", NULL);
4387 if (!ent || IS_ERR(ent))
4388 return;
4389
4390 sky2_debug = ent;
4391 register_netdevice_notifier(&sky2_notifier);
4392}
4393
4394static __exit void sky2_debug_cleanup(void)
4395{
4396 if (sky2_debug) {
4397 unregister_netdevice_notifier(&sky2_notifier);
4398 debugfs_remove(sky2_debug);
4399 sky2_debug = NULL;
4400 }
4401}
4402
4403#else
4404#define sky2_debug_init()
4405#define sky2_debug_cleanup()
4406#endif
4407
1436b301
SH		 4408/* Two copies of network device operations to handle special case of
4409 not allowing netpoll on second port */
4410static const struct net_device_ops sky2_netdev_ops[2] = {
4411 {
4412 .ndo_open = sky2_up,
4413 .ndo_stop = sky2_down,
00829823 4414 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4415 .ndo_do_ioctl = sky2_ioctl,
4416 .ndo_validate_addr = eth_validate_addr,
4417 .ndo_set_mac_address = sky2_set_mac_address,
4418 .ndo_set_multicast_list = sky2_set_multicast,
4419 .ndo_change_mtu = sky2_change_mtu,
4420 .ndo_tx_timeout = sky2_tx_timeout,
4421#ifdef SKY2_VLAN_TAG_USED
4422 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4423#endif
4424#ifdef CONFIG_NET_POLL_CONTROLLER
4425 .ndo_poll_controller = sky2_netpoll,
4426#endif
4427 },
4428 {
4429 .ndo_open = sky2_up,
4430 .ndo_stop = sky2_down,
00829823 4431 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4432 .ndo_do_ioctl = sky2_ioctl,
4433 .ndo_validate_addr = eth_validate_addr,
4434 .ndo_set_mac_address = sky2_set_mac_address,
4435 .ndo_set_multicast_list = sky2_set_multicast,
4436 .ndo_change_mtu = sky2_change_mtu,
4437 .ndo_tx_timeout = sky2_tx_timeout,
4438#ifdef SKY2_VLAN_TAG_USED
4439 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4440#endif
4441 },
4442};
3cf26753 4443
cd28ab6a
SH		 4444/* Initialize network device */
4445static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4446 unsigned port,
be63a21c 4447 int highmem, int wol)
cd28ab6a
SH		 4448{
4449 struct sky2_port *sky2;
4450 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4451
4452 if (!dev) {
898eb71c 4453 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4454 return NULL;
4455 }
4456
cd28ab6a 4457 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4458 dev->irq = hw->pdev->irq;
cd28ab6a 4459 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4460 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4461 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4462
4463 sky2 = netdev_priv(dev);
4464 sky2->netdev = dev;
4465 sky2->hw = hw;
4466 sky2->msg_enable = netif_msg_init(debug, default_msg);
4467
cd28ab6a 4468 /* Auto speed and flow control */
0ea065e5
SH		 4469 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4470 if (hw->chip_id != CHIP_ID_YUKON_XL)
4471 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4472
16ad91e1
SH		 4473 sky2->flow_mode = FC_BOTH;
4474
cd28ab6a
SH		 4475 sky2->duplex = -1;
4476 sky2->speed = -1;
4477 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4478 sky2->wol = wol;
75d070c5 4479
e07b1aa8 4480 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4481
793b883e 4482 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4483 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4484 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4485
4486 hw->dev[port] = dev;
4487
4488 sky2->port = port;
4489
4a50a876 4490 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4491 if (highmem)
4492 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4493
d1f13708 4494#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4495 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4496 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4497 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4498 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4499 }
d1f13708 4500#endif
4501
cd28ab6a 4502 /* read the mac address */
793b883e 4503 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4504 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4505
cd28ab6a
SH		 4506 return dev;
4507}
4508
28bd181a 4509static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4510{
4511 const struct sky2_port *sky2 = netdev_priv(dev);
4512
6c35abae 4513 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4514}
4515
fb2690a9 4516/* Handle software interrupt used during MSI test */
7d12e780 4517static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4518{
4519 struct sky2_hw *hw = dev_id;
4520 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4521
4522 if (status == 0)
4523 return IRQ_NONE;
4524
4525 if (status & Y2_IS_IRQ_SW) {
ea76e635 4526 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4527 wake_up(&hw->msi_wait);
4528 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4529 }
4530 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4531
4532 return IRQ_HANDLED;
4533}
4534
4535/* Test interrupt path by forcing a a software IRQ */
4536static int __devinit sky2_test_msi(struct sky2_hw *hw)
4537{
4538 struct pci_dev *pdev = hw->pdev;
4539 int err;
4540
bb507fe1 4541 init_waitqueue_head (&hw->msi_wait);
4542
fb2690a9
SH		 4543 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4544
b0a20ded 4545 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4546 if (err) {
b02a9258 4547 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4548 return err;
4549 }
4550
fb2690a9 4551 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4552 sky2_read8(hw, B0_CTST);
fb2690a9 4553
ea76e635 4554 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4555
ea76e635 4556 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4557 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4558 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4559 "switching to INTx mode.\n");
fb2690a9
SH		 4560
4561 err = -EOPNOTSUPP;
4562 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4563 }
4564
4565 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4566 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4567
4568 free_irq(pdev->irq, hw);
4569
4570 return err;
4571}
4572
c7127a34
SH		 4573/* This driver supports yukon2 chipset only */
4574static const char *sky2_name(u8 chipid, char *buf, int sz)
4575{
4576 const char *name[] = {
4577 "XL", /* 0xb3 */
4578 "EC Ultra", /* 0xb4 */
4579 "Extreme", /* 0xb5 */
4580 "EC", /* 0xb6 */
4581 "FE", /* 0xb7 */
4582 "FE+", /* 0xb8 */
4583 "Supreme", /* 0xb9 */
0ce8b98d 4584 "UL 2", /* 0xba */
0f5aac70
SH		 4585 "Unknown", /* 0xbb */
4586 "Optima", /* 0xbc */
c7127a34
SH		 4587 };
4588
dae3a511 4589 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4590 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4591 else
4592 snprintf(buf, sz, "(chip %#x)", chipid);
4593 return buf;
4594}
4595
cd28ab6a
SH		 4596static int __devinit sky2_probe(struct pci_dev *pdev,
4597 const struct pci_device_id *ent)
4598{
7f60c64b 4599 struct net_device *dev;
cd28ab6a 4600 struct sky2_hw *hw;
be63a21c 4601 int err, using_dac = 0, wol_default;
3834507d 4602 u32 reg;
c7127a34 4603 char buf1[16];
cd28ab6a 4604
793b883e
SH		 4605 err = pci_enable_device(pdev);
4606 if (err) {
b02a9258 4607 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4608 goto err_out;
4609 }
4610
6cc90a5a
SH		 4611 /* Get configuration information
4612 * Note: only regular PCI config access once to test for HW issues
4613 * other PCI access through shared memory for speed and to
4614 * avoid MMCONFIG problems.
4615 */
4616 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4617 if (err) {
4618 dev_err(&pdev->dev, "PCI read config failed\n");
4619 goto err_out;
4620 }
4621
4622 if (~reg == 0) {
4623 dev_err(&pdev->dev, "PCI configuration read error\n");
4624 goto err_out;
4625 }
4626
793b883e
SH		 4627 err = pci_request_regions(pdev, DRV_NAME);
4628 if (err) {
b02a9258 4629 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4630 goto err_out_disable;
cd28ab6a
SH		 4631 }
4632
4633 pci_set_master(pdev);
4634
d1f3d4dd 4635 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4636 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4637 using_dac = 1;
6a35528a 4638 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4639 if (err < 0) {
b02a9258
SH		 4640 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4641 "for consistent allocations\n");
d1f3d4dd
SH		 4642 goto err_out_free_regions;
4643 }
d1f3d4dd 4644 } else {
284901a9 4645 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4646 if (err) {
b02a9258 4647 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4648 goto err_out_free_regions;
4649 }
4650 }
d1f3d4dd 4651
3834507d
SH		 4652
4653#ifdef __BIG_ENDIAN
4654 /* The sk98lin vendor driver uses hardware byte swapping but
4655 * this driver uses software swapping.
4656 */
4657 reg &= ~PCI_REV_DESC;
4658 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4659 if (err) {
4660 dev_err(&pdev->dev, "PCI write config failed\n");
4661 goto err_out_free_regions;
4662 }
4663#endif
4664
9d731d77 4665 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4666
cd28ab6a 4667 err = -ENOMEM;
66466797
SH		 4668
4669 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4670 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4671 if (!hw) {
b02a9258 4672 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4673 goto err_out_free_regions;
4674 }
4675
cd28ab6a 4676 hw->pdev = pdev;
66466797 4677 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4678
4679 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4680 if (!hw->regs) {
b02a9258 4681 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4682 goto err_out_free_hw;
4683 }
4684
08c06d8a 4685 /* ring for status responses */
167f53d0 4686 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4687 if (!hw->st_le)
4688 goto err_out_iounmap;
4689
e3173832 4690 err = sky2_init(hw);
cd28ab6a 4691 if (err)
793b883e 4692 goto err_out_iounmap;
cd28ab6a 4693
c844d483
SH		 4694 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4695 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4696
e3173832
SH		 4697 sky2_reset(hw);
4698
be63a21c 4699 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4700 if (!dev) {
4701 err = -ENOMEM;
cd28ab6a 4702 goto err_out_free_pci;
7f60c64b 4703 }
cd28ab6a 4704
9fa1b1f3
SH		 4705 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4706 err = sky2_test_msi(hw);
4707 if (err == -EOPNOTSUPP)
4708 pci_disable_msi(pdev);
4709 else if (err)
4710 goto err_out_free_netdev;
4711 }
4712
793b883e
SH		 4713 err = register_netdev(dev);
4714 if (err) {
b02a9258 4715 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4716 goto err_out_free_netdev;
4717 }
4718
33cb7d33
BP		 4719 netif_carrier_off(dev);
4720
6de16237
SH		 4721 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4722
ea76e635
SH		 4723 err = request_irq(pdev->irq, sky2_intr,
4724 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4725 hw->irq_name, hw);
9fa1b1f3 4726 if (err) {
b02a9258 4727 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4728 goto err_out_unregister;
4729 }
4730 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4731 napi_enable(&hw->napi);
9fa1b1f3 4732
cd28ab6a
SH		 4733 sky2_show_addr(dev);
4734
7f60c64b 4735 if (hw->ports > 1) {
4736 struct net_device *dev1;
4737
ca519274 4738 err = -ENOMEM;
be63a21c 4739 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4740 if (dev1 && (err = register_netdev(dev1)) == 0)
4741 sky2_show_addr(dev1);
4742 else {
b02a9258
SH		 4743 dev_warn(&pdev->dev,
4744 "register of second port failed (%d)\n", err);
cd28ab6a 4745 hw->dev[1] = NULL;
ca519274
SH		 4746 hw->ports = 1;
4747 if (dev1)
4748 free_netdev(dev1);
4749 }
cd28ab6a
SH		 4750 }
4751
32c2c300 4752 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4753 INIT_WORK(&hw->restart_work, sky2_restart);
4754
793b883e 4755 pci_set_drvdata(pdev, hw);
1ae861e6 4756 pdev->d3_delay = 150;
793b883e 4757
cd28ab6a
SH		 4758 return 0;
4759
793b883e 4760err_out_unregister:
ea76e635 4761 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4762 pci_disable_msi(pdev);
793b883e 4763 unregister_netdev(dev);
cd28ab6a
SH		 4764err_out_free_netdev:
4765 free_netdev(dev);
cd28ab6a 4766err_out_free_pci:
793b883e 4767 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4768 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4769err_out_iounmap:
4770 iounmap(hw->regs);
4771err_out_free_hw:
4772 kfree(hw);
4773err_out_free_regions:
4774 pci_release_regions(pdev);
44a1d2e5 4775err_out_disable:
cd28ab6a 4776 pci_disable_device(pdev);
cd28ab6a 4777err_out:
549a68c3 4778 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4779 return err;
4780}
4781
4782static void __devexit sky2_remove(struct pci_dev *pdev)
4783{
793b883e 4784 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4785 int i;
cd28ab6a 4786
793b883e 4787 if (!hw)
cd28ab6a
SH		 4788 return;
4789
32c2c300 4790 del_timer_sync(&hw->watchdog_timer);
6de16237 4791 cancel_work_sync(&hw->restart_work);
d27ed387 4792
b877fe28 4793 for (i = hw->ports-1; i >= 0; --i)
6de16237 4794 unregister_netdev(hw->dev[i]);
81906791 4795
d27ed387 4796 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4797
ae306cca
SH		 4798 sky2_power_aux(hw);
4799
793b883e 4800 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4801 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4802
4803 free_irq(pdev->irq, hw);
ea76e635 4804 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4805 pci_disable_msi(pdev);
793b883e 4806 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4807 pci_release_regions(pdev);
4808 pci_disable_device(pdev);
793b883e 4809
b877fe28 4810 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4811 free_netdev(hw->dev[i]);
4812
cd28ab6a
SH		 4813 iounmap(hw->regs);
4814 kfree(hw);
5afa0a9c 4815
cd28ab6a
SH		 4816 pci_set_drvdata(pdev, NULL);
4817}
4818
cd28ab6a
SH		 4819static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4820{
793b883e 4821 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4822 int i, wol = 0;
cd28ab6a 4823
549a68c3
SH		 4824 if (!hw)
4825 return 0;
4826
063a0b38
SH		 4827 del_timer_sync(&hw->watchdog_timer);
4828 cancel_work_sync(&hw->restart_work);
4829
19720737 4830 rtnl_lock();
f05267e7 4831 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4832 struct net_device *dev = hw->dev[i];
e3173832 4833 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4834
af18d8b8 4835 sky2_detach(dev);
e3173832
SH		 4836
4837 if (sky2->wol)
4838 sky2_wol_init(sky2);
4839
4840 wol |= sky2->wol;
cd28ab6a
SH		 4841 }
4842
5f8ae5c5 4843 device_set_wakeup_enable(&pdev->dev, wol != 0);
4844
8ab8fca2 4845 sky2_write32(hw, B0_IMSK, 0);
6de16237 4846 napi_disable(&hw->napi);
ae306cca 4847 sky2_power_aux(hw);
19720737 4848 rtnl_unlock();
e3173832 4849
d374c1c1 4850 pci_save_state(pdev);
e3173832 4851 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4852 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4853
2ccc99b7 4854 return 0;
cd28ab6a
SH		 4855}
4856
5f8ae5c5 4857#ifdef CONFIG_PM
cd28ab6a
SH		 4858static int sky2_resume(struct pci_dev *pdev)
4859{
793b883e 4860 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4861 int i, err;
cd28ab6a 4862
549a68c3
SH		 4863 if (!hw)
4864 return 0;
4865
f71eb1a2
SH		 4866 err = pci_set_power_state(pdev, PCI_D0);
4867 if (err)
4868 goto out;
ae306cca
SH		 4869
4870 err = pci_restore_state(pdev);
4871 if (err)
4872 goto out;
4873
cd28ab6a 4874 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4875
4876 /* Re-enable all clocks */
a0db28b8 4877 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4878 if (err) {
4879 dev_err(&pdev->dev, "PCI write config failed\n");
4880 goto out;
4881 }
1ad5b4a5 4882
e3173832 4883 sky2_reset(hw);
8ab8fca2 4884 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4885 napi_enable(&hw->napi);
8ab8fca2 4886
af18d8b8 4887 rtnl_lock();
f05267e7 4888 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4889 err = sky2_reattach(hw->dev[i]);
4890 if (err)
4891 goto out;
cd28ab6a 4892 }
af18d8b8 4893 rtnl_unlock();
eb35cf60 4894
ae306cca 4895 return 0;
08c06d8a 4896out:
af18d8b8
SH		 4897 rtnl_unlock();
4898
b02a9258 4899 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4900 pci_disable_device(pdev);
08c06d8a 4901 return err;
cd28ab6a
SH		 4902}
4903#endif
4904
e3173832
SH		 4905static void sky2_shutdown(struct pci_dev *pdev)
4906{
5f8ae5c5 4907 sky2_suspend(pdev, PMSG_SUSPEND);
e3173832
SH		 4908}
4909
cd28ab6a 4910static struct pci_driver sky2_driver = {
793b883e
SH		 4911 .name = DRV_NAME,
4912 .id_table = sky2_id_table,
4913 .probe = sky2_probe,
4914 .remove = __devexit_p(sky2_remove),
cd28ab6a 4915#ifdef CONFIG_PM
793b883e
SH		 4916 .suspend = sky2_suspend,
4917 .resume = sky2_resume,
cd28ab6a 4918#endif
e3173832 4919 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4920};
4921
4922static int __init sky2_init_module(void)
4923{
ada1db5c 4924 pr_info("driver version " DRV_VERSION "\n");
c844d483 4925
3cf26753 4926 sky2_debug_init();
50241c4c 4927 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4928}
4929
4930static void __exit sky2_cleanup_module(void)
4931{
4932 pci_unregister_driver(&sky2_driver);
3cf26753 4933 sky2_debug_cleanup();
cd28ab6a
SH		 4934}
4935
4936module_init(sky2_init_module);
4937module_exit(sky2_cleanup_module);
4938
4939MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4940MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4941MODULE_LICENSE("GPL");
5f4f9dc1 4942MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)