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[BNX2X]: fix slowpath races and locking
[linux-2.6-block.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
bcc52894 54#define DRV_VERSION "1.21"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
f4331a6d
SH		 79#define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
cd28ab6a 101static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
cd28ab6a
SH		 139 { 0 }
140};
793b883e 141
cd28ab6a
SH		 142MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144/* Avoid conditionals by using array */
145static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 147static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 148
92f965e8
SH		 149/* This driver supports yukon2 chipset only */
150static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
93745494 153 "Extreme", /* 0xb5 */
92f965e8
SH		 154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
05745c4a 156 "FE+", /* 0xb8 */
793b883e
SH		 157};
158
d1b139c0
SH		 159static void sky2_set_multicast(struct net_device *dev);
160
af043aa5 161/* Access to PHY via serial interconnect */
ef743d33 162static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 163{
164 int i;
165
166 gma_write16(hw, port, GM_SMI_DATA, val);
167 gma_write16(hw, port, GM_SMI_CTRL,
168 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
169
170 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 171 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
172 if (ctrl == 0xffff)
173 goto io_error;
174
175 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 176 return 0;
af043aa5
SH		 177
178 udelay(10);
cd28ab6a 179 }
ef743d33 180
af043aa5 181 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 182 return -ETIMEDOUT;
af043aa5
SH		 183
184io_error:
185 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
186 return -EIO;
cd28ab6a
SH		 187}
188
ef743d33 189static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 190{
191 int i;
192
793b883e 193 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 194 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
195
196 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 197 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
198 if (ctrl == 0xffff)
199 goto io_error;
200
201 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 202 *val = gma_read16(hw, port, GM_SMI_DATA);
203 return 0;
204 }
205
af043aa5 206 udelay(10);
cd28ab6a
SH		 207 }
208
af043aa5 209 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 210 return -ETIMEDOUT;
af043aa5
SH		 211io_error:
212 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
213 return -EIO;
ef743d33 214}
215
af043aa5 216static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 217{
218 u16 v;
af043aa5 219 __gm_phy_read(hw, port, reg, &v);
ef743d33 220 return v;
cd28ab6a
SH		 221}
222
5afa0a9c 223
ae306cca
SH		 224static void sky2_power_on(struct sky2_hw *hw)
225{
226 /* switch power to VCC (WA for VAUX problem) */
227 sky2_write8(hw, B0_POWER_CTRL,
228 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 229
ae306cca
SH		 230 /* disable Core Clock Division, */
231 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 232
ae306cca
SH		 233 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239 else
240 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 241
ea76e635 242 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 243 u32 reg;
5afa0a9c 244
b32f40c4 245 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 246
b32f40c4 247 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 248 /* set all bits to 0 except bits 15..12 and 8 */
249 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 250 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 251
b32f40c4 252 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 253 /* set all bits to 0 except bits 28 & 27 */
254 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 255 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 256
b32f40c4 257 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 258
259 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
260 reg = sky2_read32(hw, B2_GP_IO);
261 reg |= GLB_GPIO_STAT_RACE_DIS;
262 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 263
264 sky2_read32(hw, B2_GP_IO);
5afa0a9c 265 }
ae306cca 266}
5afa0a9c 267
ae306cca
SH		 268static void sky2_power_aux(struct sky2_hw *hw)
269{
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
272 else
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
278
279 /* switch power to VAUX */
280 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
281 sky2_write8(hw, B0_POWER_CTRL,
282 (PC_VAUX_ENA | PC_VCC_ENA |
283 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 284}
285
d3bcfbeb 286static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 287{
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 292
cd28ab6a
SH		 293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301}
302
16ad91e1
SH		 303/* flow control to advertise bits */
304static const u16 copper_fc_adv[] = {
305 [FC_NONE] = 0,
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
309};
310
311/* flow control to advertise bits when using 1000BaseX */
312static const u16 fiber_fc_adv[] = {
df3fe1f3 313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 317};
318
319/* flow control to GMA disable bits */
320static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
324 [FC_BOTH] = 0,
325};
326
327
cd28ab6a
SH		 328static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
329{
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 332
ea76e635
SH		 333 if (sky2->autoneg == AUTONEG_ENABLE &&
334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
336
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 338 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
340
53419c68 341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 342 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 343 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
345 else
53419c68
SH		 346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 348
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 353 if (sky2_is_copper(hw)) {
05745c4a 354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 357
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
360 u16 spec;
361
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
366 }
cd28ab6a
SH		 367 } else {
368 /* disable energy detect */
369 ctrl &= ~PHY_M_PC_EN_DET_MSK;
370
371 /* enable automatic crossover */
372 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
373
53419c68 374 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 375 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 376 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 377 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 378 ctrl &= ~PHY_M_PC_DSC_MSK;
379 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
380 }
381 }
cd28ab6a
SH		 382 } else {
383 /* workaround for deviation #4.88 (CRC errors) */
384 /* disable Automatic Crossover */
385
386 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 387 }
cd28ab6a 388
b89165f2
SH		 389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
390
391 /* special setup for PHY 88E1112 Fiber */
ea76e635 392 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 393 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 394
b89165f2
SH		 395 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
397 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
398 ctrl &= ~PHY_M_MAC_MD_MSK;
399 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401
402 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 403 /* select page 1 to access Fiber registers */
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 405
406 /* for SFP-module set SIGDET polarity to low */
407 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
408 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 410 }
b89165f2
SH		 411
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 413 }
414
7800fddc 415 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 416 ct1000 = 0;
417 adv = PHY_AN_CSMA;
2eaba1a2 418 reg = 0;
cd28ab6a
SH		 419
420 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 421 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 422 if (sky2->advertising & ADVERTISED_1000baseT_Full)
423 ct1000 |= PHY_M_1000C_AFD;
424 if (sky2->advertising & ADVERTISED_1000baseT_Half)
425 ct1000 |= PHY_M_1000C_AHD;
426 if (sky2->advertising & ADVERTISED_100baseT_Full)
427 adv |= PHY_M_AN_100_FD;
428 if (sky2->advertising & ADVERTISED_100baseT_Half)
429 adv |= PHY_M_AN_100_HD;
430 if (sky2->advertising & ADVERTISED_10baseT_Full)
431 adv |= PHY_M_AN_10_FD;
432 if (sky2->advertising & ADVERTISED_10baseT_Half)
433 adv |= PHY_M_AN_10_HD;
709c6e7b 434
16ad91e1 435 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 436 } else { /* special defines for FIBER (88E1040S only) */
437 if (sky2->advertising & ADVERTISED_1000baseT_Full)
438 adv |= PHY_M_AN_1000X_AFD;
439 if (sky2->advertising & ADVERTISED_1000baseT_Half)
440 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 441
16ad91e1 442 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 443 }
cd28ab6a
SH		 444
445 /* Restart Auto-negotiation */
446 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 } else {
448 /* forced speed/duplex settings */
449 ct1000 = PHY_M_1000C_MSE;
450
2eaba1a2
SH		 451 /* Disable auto update for duplex flow control and speed */
452 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 453
454 switch (sky2->speed) {
455 case SPEED_1000:
456 ctrl |= PHY_CT_SP1000;
2eaba1a2 457 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 458 break;
459 case SPEED_100:
460 ctrl |= PHY_CT_SP100;
2eaba1a2 461 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 462 break;
463 }
464
2eaba1a2
SH		 465 if (sky2->duplex == DUPLEX_FULL) {
466 reg |= GM_GPCR_DUP_FULL;
467 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 468 } else if (sky2->speed < SPEED_1000)
469 sky2->flow_mode = FC_NONE;
2eaba1a2 470
2eaba1a2 471
16ad91e1 472 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 473
474 /* Forward pause packets to GMAC? */
16ad91e1 475 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 476 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
477 else
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 479 }
480
2eaba1a2
SH		 481 gma_write16(hw, port, GM_GP_CTRL, reg);
482
05745c4a 483 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 484 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
485
486 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
487 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
488
489 /* Setup Phy LED's */
490 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
491 ledover = 0;
492
493 switch (hw->chip_id) {
494 case CHIP_ID_YUKON_FE:
495 /* on 88E3082 these bits are at 11..9 (shifted left) */
496 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
497
498 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
499
500 /* delete ACT LED control bits */
501 ctrl &= ~PHY_M_FELP_LED1_MSK;
502 /* change ACT LED control to blink mode */
503 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
504 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
505 break;
506
05745c4a
SH		 507 case CHIP_ID_YUKON_FE_P:
508 /* Enable Link Partner Next Page */
509 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
510 ctrl |= PHY_M_PC_ENA_LIP_NP;
511
512 /* disable Energy Detect and enable scrambler */
513 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
514 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
515
516 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
517 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
518 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
519 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
520
521 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
522 break;
523
cd28ab6a 524 case CHIP_ID_YUKON_XL:
793b883e 525 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 526
527 /* select page 3 to access LED control register */
528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
529
530 /* set LED Function Control register */
ed6d32c7
SH		 531 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
532 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
533 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
534 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
535 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 536
537 /* set Polarity Control register */
538 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 539 (PHY_M_POLC_LS1_P_MIX(4) |
540 PHY_M_POLC_IS0_P_MIX(4) |
541 PHY_M_POLC_LOS_CTRL(2) |
542 PHY_M_POLC_INIT_CTRL(2) |
543 PHY_M_POLC_STA1_CTRL(2) |
544 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 545
546 /* restore page register */
793b883e 547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 548 break;
93745494 549
ed6d32c7 550 case CHIP_ID_YUKON_EC_U:
93745494 551 case CHIP_ID_YUKON_EX:
ed4d4161 552 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 553 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
554
555 /* select page 3 to access LED control register */
556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
557
558 /* set LED Function Control register */
559 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
560 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
561 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
562 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
563 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
564
565 /* set Blink Rate in LED Timer Control Register */
566 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
567 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
568 /* restore page register */
569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
570 break;
cd28ab6a
SH		 571
572 default:
573 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
574 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 575
cd28ab6a 576 /* turn off the Rx LED (LED_RX) */
a84d0a3d 577 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 578 }
579
9467a8fc
SH		 580 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
581 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 582 /* apply fixes in PHY AFE */
ed6d32c7
SH		 583 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
584
977bdf06 585 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 586 gm_phy_write(hw, port, 0x18, 0xaa99);
587 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 588
977bdf06 589 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 590 gm_phy_write(hw, port, 0x18, 0xa204);
591 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 592
593 /* set page register to 0 */
9467a8fc 594 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 595 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
596 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
597 /* apply workaround for integrated resistors calibration */
598 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
599 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 600 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 601 /* no effect on Yukon-XL */
977bdf06 602 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 603
977bdf06
SH		 604 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
605 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 606 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 607 }
cd28ab6a 608
977bdf06
SH		 609 if (ledover)
610 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
611
612 }
2eaba1a2 613
d571b694 614 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 615 if (sky2->autoneg == AUTONEG_ENABLE)
616 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
617 else
618 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
619}
620
d3bcfbeb 621static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
622{
623 u32 reg1;
ff35164e
SH		 624 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
625 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
d3bcfbeb 626
82637e80 627 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 628 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
ff35164e 629 /* Turn on/off phy power saving */
d3bcfbeb 630 if (onoff)
d3bcfbeb 631 reg1 &= ~phy_power[port];
632 else
633 reg1 |= phy_power[port];
634
ff35164e
SH		 635 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
636 reg1 |= coma_mode[port];
637
b32f40c4 638 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 639 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
640 sky2_pci_read32(hw, PCI_DEV_REG1);
167f53d0 641
d3bcfbeb 642 udelay(100);
643}
644
1b537565
SH		 645/* Force a renegotiation */
646static void sky2_phy_reinit(struct sky2_port *sky2)
647{
e07b1aa8 648 spin_lock_bh(&sky2->phy_lock);
1b537565 649 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 650 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 651}
652
e3173832
SH		 653/* Put device in state to listen for Wake On Lan */
654static void sky2_wol_init(struct sky2_port *sky2)
655{
656 struct sky2_hw *hw = sky2->hw;
657 unsigned port = sky2->port;
658 enum flow_control save_mode;
659 u16 ctrl;
660 u32 reg1;
661
662 /* Bring hardware out of reset */
663 sky2_write16(hw, B0_CTST, CS_RST_CLR);
664 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
665
666 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
667 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
668
669 /* Force to 10/100
670 * sky2_reset will re-enable on resume
671 */
672 save_mode = sky2->flow_mode;
673 ctrl = sky2->advertising;
674
675 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
676 sky2->flow_mode = FC_NONE;
677 sky2_phy_power(hw, port, 1);
678 sky2_phy_reinit(sky2);
679
680 sky2->flow_mode = save_mode;
681 sky2->advertising = ctrl;
682
683 /* Set GMAC to no flow control and auto update for speed/duplex */
684 gma_write16(hw, port, GM_GP_CTRL,
685 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
686 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
687
688 /* Set WOL address */
689 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
690 sky2->netdev->dev_addr, ETH_ALEN);
691
692 /* Turn on appropriate WOL control bits */
693 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
694 ctrl = 0;
695 if (sky2->wol & WAKE_PHY)
696 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
697 else
698 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
699
700 if (sky2->wol & WAKE_MAGIC)
701 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
702 else
703 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
704
705 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
706 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
707
708 /* Turn on legacy PCI-Express PME mode */
b32f40c4 709 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 710 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 711 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 712
713 /* block receiver */
714 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
715
716}
717
69161611
SH		 718static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
719{
05745c4a
SH		 720 struct net_device *dev = hw->dev[port];
721
ed4d4161
SH		 722 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
723 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
724 hw->chip_id == CHIP_ID_YUKON_FE_P ||
725 hw->chip_id == CHIP_ID_YUKON_SUPR) {
726 /* Yukon-Extreme B0 and further Extreme devices */
727 /* enable Store & Forward mode for TX */
05745c4a 728
ed4d4161
SH		 729 if (dev->mtu <= ETH_DATA_LEN)
730 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
731 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 732
ed4d4161
SH		 733 else
734 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
735 TX_JUMBO_ENA| TX_STFW_ENA);
736 } else {
737 if (dev->mtu <= ETH_DATA_LEN)
738 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
739 else {
740 /* set Tx GMAC FIFO Almost Empty Threshold */
741 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
742 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 743
ed4d4161
SH		 744 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
745
746 /* Can't do offload because of lack of store/forward */
747 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
748 }
69161611
SH		 749 }
750}
751
cd28ab6a
SH		 752static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
753{
754 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
755 u16 reg;
25cccecc 756 u32 rx_reg;
cd28ab6a
SH		 757 int i;
758 const u8 *addr = hw->dev[port]->dev_addr;
759
f350339c
SH		 760 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
761 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 762
763 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
764
793b883e 765 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 766 /* WA DEV_472 -- looks like crossed wires on port 2 */
767 /* clear GMAC 1 Control reset */
768 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
769 do {
770 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
771 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
772 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
773 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
774 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
775 }
776
793b883e 777 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 778
2eaba1a2
SH		 779 /* Enable Transmit FIFO Underrun */
780 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
781
e07b1aa8 782 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 783 sky2_phy_init(hw, port);
e07b1aa8 784 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 785
786 /* MIB clear */
787 reg = gma_read16(hw, port, GM_PHY_ADDR);
788 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
789
43f2f104
SH		 790 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
791 gma_read16(hw, port, i);
cd28ab6a
SH		 792 gma_write16(hw, port, GM_PHY_ADDR, reg);
793
794 /* transmit control */
795 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
796
797 /* receive control reg: unicast + multicast + no FCS */
798 gma_write16(hw, port, GM_RX_CTRL,
793b883e 799 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 800
801 /* transmit flow control */
802 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
803
804 /* transmit parameter */
805 gma_write16(hw, port, GM_TX_PARAM,
806 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
807 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
808 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
809 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
810
811 /* serial mode register */
812 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 813 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 814
6b1a3aef 815 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 816 reg |= GM_SMOD_JUMBO_ENA;
817
818 gma_write16(hw, port, GM_SERIAL_MODE, reg);
819
cd28ab6a
SH		 820 /* virtual address for data */
821 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
822
793b883e
SH		 823 /* physical address: used for pause frames */
824 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
825
826 /* ignore counter overflows */
cd28ab6a
SH		 827 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
828 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
829 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
830
831 /* Configure Rx MAC FIFO */
832 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 833 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 834 if (hw->chip_id == CHIP_ID_YUKON_EX ||
835 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 836 rx_reg |= GMF_RX_OVER_ON;
69161611 837
25cccecc 838 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 839
798fdd07
SH		 840 if (hw->chip_id == CHIP_ID_YUKON_XL) {
841 /* Hardware errata - clear flush mask */
842 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
843 } else {
844 /* Flush Rx MAC FIFO on any flow control or error */
845 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
846 }
cd28ab6a 847
8df9a876 848 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 849 reg = RX_GMF_FL_THR_DEF + 1;
850 /* Another magic mystery workaround from sk98lin */
851 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
852 hw->chip_rev == CHIP_REV_YU_FE2_A0)
853 reg = 0x178;
854 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 855
856 /* Configure Tx MAC FIFO */
857 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
858 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 859
e0c28116 860 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 861 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 862 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 863 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 864
69161611 865 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 866 }
867
e970d1f8
SH		 868 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
869 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
870 /* disable dynamic watermark */
871 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
872 reg &= ~TX_DYN_WM_ENA;
873 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
874 }
cd28ab6a
SH		 875}
876
67712901
SH		 877/* Assign Ram Buffer allocation to queue */
878static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 879{
67712901
SH		 880 u32 end;
881
882 /* convert from K bytes to qwords used for hw register */
883 start *= 1024/8;
884 space *= 1024/8;
885 end = start + space - 1;
793b883e 886
cd28ab6a
SH		 887 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
888 sky2_write32(hw, RB_ADDR(q, RB_START), start);
889 sky2_write32(hw, RB_ADDR(q, RB_END), end);
890 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
891 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
892
893 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 894 u32 tp = space - space/4;
793b883e 895
1c28f6ba
SH		 896 /* On receive queue's set the thresholds
897 * give receiver priority when > 3/4 full
898 * send pause when down to 2K
899 */
900 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
901 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 902
1c28f6ba
SH		 903 tp = space - 2048/8;
904 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
905 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 906 } else {
907 /* Enable store & forward on Tx queue's because
908 * Tx FIFO is only 1K on Yukon
909 */
910 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
911 }
912
913 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 914 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 915}
916
cd28ab6a 917/* Setup Bus Memory Interface */
af4ed7e6 918static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 919{
920 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
921 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
922 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 923 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 924}
925
cd28ab6a
SH		 926/* Setup prefetch unit registers. This is the interface between
927 * hardware and driver list elements
928 */
8cc048e3 929static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 930 u64 addr, u32 last)
931{
cd28ab6a
SH		 932 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
933 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
934 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
935 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
936 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
937 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 938
939 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 940}
941
793b883e
SH		 942static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
943{
944 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
945
cb5d9547 946 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 947 le->ctrl = 0;
793b883e
SH		 948 return le;
949}
cd28ab6a 950
88f5f0ca
SH		 951static void tx_init(struct sky2_port *sky2)
952{
953 struct sky2_tx_le *le;
954
955 sky2->tx_prod = sky2->tx_cons = 0;
956 sky2->tx_tcpsum = 0;
957 sky2->tx_last_mss = 0;
958
959 le = get_tx_le(sky2);
960 le->addr = 0;
961 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 962}
963
291ea614
SH		 964static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
965 struct sky2_tx_le *le)
966{
967 return sky2->tx_ring + (le - sky2->tx_le);
968}
969
290d4de5
SH		 970/* Update chip's next pointer */
971static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 972{
50432cb5 973 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 974 wmb();
50432cb5
SH		 975 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
976
977 /* Synchronize I/O on since next processor may write to tail */
978 mmiowb();
cd28ab6a
SH		 979}
980
793b883e 981
cd28ab6a
SH		 982static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
983{
984 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 985 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 986 le->ctrl = 0;
cd28ab6a
SH		 987 return le;
988}
989
14d0263f
SH		 990/* Build description to hardware for one receive segment */
991static void sky2_rx_add(struct sky2_port *sky2, u8 op,
992 dma_addr_t map, unsigned len)
cd28ab6a
SH		 993{
994 struct sky2_rx_le *le;
995
86c6887e 996 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 997 le = sky2_next_rx(sky2);
86c6887e 998 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 999 le->opcode = OP_ADDR64 | HW_OWNER;
1000 }
793b883e 1001
cd28ab6a 1002 le = sky2_next_rx(sky2);
734d1868
SH		 1003 le->addr = cpu_to_le32((u32) map);
1004 le->length = cpu_to_le16(len);
14d0263f 1005 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1006}
1007
14d0263f
SH		 1008/* Build description to hardware for one possibly fragmented skb */
1009static void sky2_rx_submit(struct sky2_port *sky2,
1010 const struct rx_ring_info *re)
1011{
1012 int i;
1013
1014 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1015
1016 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1017 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1018}
1019
1020
1021static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1022 unsigned size)
1023{
1024 struct sk_buff *skb = re->skb;
1025 int i;
1026
1027 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1028 pci_unmap_len_set(re, data_size, size);
1029
1030 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1031 re->frag_addr[i] = pci_map_page(pdev,
1032 skb_shinfo(skb)->frags[i].page,
1033 skb_shinfo(skb)->frags[i].page_offset,
1034 skb_shinfo(skb)->frags[i].size,
1035 PCI_DMA_FROMDEVICE);
1036}
1037
1038static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1039{
1040 struct sk_buff *skb = re->skb;
1041 int i;
1042
1043 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1044 PCI_DMA_FROMDEVICE);
1045
1046 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1047 pci_unmap_page(pdev, re->frag_addr[i],
1048 skb_shinfo(skb)->frags[i].size,
1049 PCI_DMA_FROMDEVICE);
1050}
793b883e 1051
cd28ab6a
SH		 1052/* Tell chip where to start receive checksum.
1053 * Actually has two checksums, but set both same to avoid possible byte
1054 * order problems.
1055 */
793b883e 1056static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1057{
ea76e635 1058 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1059
ea76e635
SH		 1060 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1061 le->ctrl = 0;
1062 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1063
ea76e635
SH		 1064 sky2_write32(sky2->hw,
1065 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1066 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1067}
1068
6b1a3aef 1069/*
1070 * The RX Stop command will not work for Yukon-2 if the BMU does not
1071 * reach the end of packet and since we can't make sure that we have
1072 * incoming data, we must reset the BMU while it is not doing a DMA
1073 * transfer. Since it is possible that the RX path is still active,
1074 * the RX RAM buffer will be stopped first, so any possible incoming
1075 * data will not trigger a DMA. After the RAM buffer is stopped, the
1076 * BMU is polled until any DMA in progress is ended and only then it
1077 * will be reset.
1078 */
1079static void sky2_rx_stop(struct sky2_port *sky2)
1080{
1081 struct sky2_hw *hw = sky2->hw;
1082 unsigned rxq = rxqaddr[sky2->port];
1083 int i;
1084
1085 /* disable the RAM Buffer receive queue */
1086 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1087
1088 for (i = 0; i < 0xffff; i++)
1089 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1090 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1091 goto stopped;
1092
1093 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1094 sky2->netdev->name);
1095stopped:
1096 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1097
1098 /* reset the Rx prefetch unit */
1099 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1100 mmiowb();
6b1a3aef 1101}
793b883e 1102
d571b694 1103/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1104static void sky2_rx_clean(struct sky2_port *sky2)
1105{
1106 unsigned i;
1107
1108 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1109 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1110 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1111
1112 if (re->skb) {
14d0263f 1113 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1114 kfree_skb(re->skb);
1115 re->skb = NULL;
1116 }
1117 }
1118}
1119
ef743d33 1120/* Basic MII support */
1121static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1122{
1123 struct mii_ioctl_data *data = if_mii(ifr);
1124 struct sky2_port *sky2 = netdev_priv(dev);
1125 struct sky2_hw *hw = sky2->hw;
1126 int err = -EOPNOTSUPP;
1127
1128 if (!netif_running(dev))
1129 return -ENODEV; /* Phy still in reset */
1130
d89e1343 1131 switch (cmd) {
ef743d33 1132 case SIOCGMIIPHY:
1133 data->phy_id = PHY_ADDR_MARV;
1134
1135 /* fallthru */
1136 case SIOCGMIIREG: {
1137 u16 val = 0;
91c86df5 1138
e07b1aa8 1139 spin_lock_bh(&sky2->phy_lock);
ef743d33 1140 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1141 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1142
ef743d33 1143 data->val_out = val;
1144 break;
1145 }
1146
1147 case SIOCSMIIREG:
1148 if (!capable(CAP_NET_ADMIN))
1149 return -EPERM;
1150
e07b1aa8 1151 spin_lock_bh(&sky2->phy_lock);
ef743d33 1152 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1153 data->val_in);
e07b1aa8 1154 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1155 break;
1156 }
1157 return err;
1158}
1159
d1f13708 1160#ifdef SKY2_VLAN_TAG_USED
1161static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1162{
1163 struct sky2_port *sky2 = netdev_priv(dev);
1164 struct sky2_hw *hw = sky2->hw;
1165 u16 port = sky2->port;
d1f13708 1166
2bb8c262 1167 netif_tx_lock_bh(dev);
bea3348e 1168 napi_disable(&hw->napi);
d1f13708 1169
d1f13708 1170 sky2->vlgrp = grp;
3d4e66f5
SH		 1171 if (grp) {
1172 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1173 RX_VLAN_STRIP_ON);
1174 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1175 TX_VLAN_TAG_ON);
1176 } else {
1177 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1178 RX_VLAN_STRIP_OFF);
1179 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1180 TX_VLAN_TAG_OFF);
1181 }
d1f13708 1182
d1d08d12 1183 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1184 napi_enable(&hw->napi);
2bb8c262 1185 netif_tx_unlock_bh(dev);
d1f13708 1186}
1187#endif
1188
82788c7a 1189/*
14d0263f
SH		 1190 * Allocate an skb for receiving. If the MTU is large enough
1191 * make the skb non-linear with a fragment list of pages.
82788c7a 1192 */
14d0263f 1193static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1194{
1195 struct sk_buff *skb;
14d0263f 1196 int i;
82788c7a 1197
39dbd958 1198 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1199 unsigned char *start;
1200 /*
1201 * Workaround for a bug in FIFO that cause hang
1202 * if the FIFO if the receive buffer is not 64 byte aligned.
1203 * The buffer returned from netdev_alloc_skb is
1204 * aligned except if slab debugging is enabled.
1205 */
1206 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1207 if (!skb)
1208 goto nomem;
1209 start = PTR_ALIGN(skb->data, 8);
1210 skb_reserve(skb, start - skb->data);
1211 } else {
1212 skb = netdev_alloc_skb(sky2->netdev,
1213 sky2->rx_data_size + NET_IP_ALIGN);
1214 if (!skb)
1215 goto nomem;
1216 skb_reserve(skb, NET_IP_ALIGN);
1217 }
14d0263f
SH		 1218
1219 for (i = 0; i < sky2->rx_nfrags; i++) {
1220 struct page *page = alloc_page(GFP_ATOMIC);
1221
1222 if (!page)
1223 goto free_partial;
1224 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1225 }
1226
1227 return skb;
14d0263f
SH		 1228free_partial:
1229 kfree_skb(skb);
1230nomem:
1231 return NULL;
82788c7a
SH		 1232}
1233
55c9dd35
SH		 1234static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1235{
1236 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1237}
1238
cd28ab6a
SH		 1239/*
1240 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1241 * Normal case this ends up creating one list element for skb
1242 * in the receive ring. Worst case if using large MTU and each
1243 * allocation falls on a different 64 bit region, that results
1244 * in 6 list elements per ring entry.
1245 * One element is used for checksum enable/disable, and one
1246 * extra to avoid wrap.
cd28ab6a 1247 */
6b1a3aef 1248static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1249{
6b1a3aef 1250 struct sky2_hw *hw = sky2->hw;
14d0263f 1251 struct rx_ring_info *re;
6b1a3aef 1252 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1253 unsigned i, size, thresh;
cd28ab6a 1254
6b1a3aef 1255 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1256 sky2_qset(hw, rxq);
977bdf06 1257
c3905bc4
SH		 1258 /* On PCI express lowering the watermark gives better performance */
1259 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1260 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1261
1262 /* These chips have no ram buffer?
1263 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1264 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1265 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1266 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1267 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1268
6b1a3aef 1269 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1270
ea76e635
SH		 1271 if (!(hw->flags & SKY2_HW_NEW_LE))
1272 rx_set_checksum(sky2);
14d0263f
SH		 1273
1274 /* Space needed for frame data + headers rounded up */
f957da2a 1275 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1276
1277 /* Stopping point for hardware truncation */
1278 thresh = (size - 8) / sizeof(u32);
1279
5f06eba4 1280 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1281 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1282
5f06eba4
SH		 1283 /* Compute residue after pages */
1284 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1285
5f06eba4
SH		 1286 /* Optimize to handle small packets and headers */
1287 if (size < copybreak)
1288 size = copybreak;
1289 if (size < ETH_HLEN)
1290 size = ETH_HLEN;
14d0263f 1291
14d0263f
SH		 1292 sky2->rx_data_size = size;
1293
1294 /* Fill Rx ring */
793b883e 1295 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1296 re = sky2->rx_ring + i;
cd28ab6a 1297
14d0263f 1298 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1299 if (!re->skb)
1300 goto nomem;
1301
14d0263f
SH		 1302 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1303 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1304 }
1305
a1433ac4
SH		 1306 /*
1307 * The receiver hangs if it receives frames larger than the
1308 * packet buffer. As a workaround, truncate oversize frames, but
1309 * the register is limited to 9 bits, so if you do frames > 2052
1310 * you better get the MTU right!
1311 */
a1433ac4
SH		 1312 if (thresh > 0x1ff)
1313 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1314 else {
1315 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1316 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1317 }
1318
6b1a3aef 1319 /* Tell chip about available buffers */
55c9dd35 1320 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1321 return 0;
1322nomem:
1323 sky2_rx_clean(sky2);
1324 return -ENOMEM;
1325}
1326
1327/* Bring up network interface. */
1328static int sky2_up(struct net_device *dev)
1329{
1330 struct sky2_port *sky2 = netdev_priv(dev);
1331 struct sky2_hw *hw = sky2->hw;
1332 unsigned port = sky2->port;
e0c28116 1333 u32 imask, ramsize;
ee7abb04 1334 int cap, err = -ENOMEM;
843a46f4 1335 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1336
ee7abb04
SH		 1337 /*
1338 * On dual port PCI-X card, there is an problem where status
1339 * can be received out of order due to split transactions
843a46f4 1340 */
ee7abb04
SH		 1341 if (otherdev && netif_running(otherdev) &&
1342 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1343 u16 cmd;
1344
b32f40c4 1345 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1346 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1347 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1348
ee7abb04 1349 }
843a46f4 1350
cd28ab6a
SH		 1351 if (netif_msg_ifup(sky2))
1352 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1353
55d7b4e6
SH		 1354 netif_carrier_off(dev);
1355
cd28ab6a
SH		 1356 /* must be power of 2 */
1357 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1358 TX_RING_SIZE *
1359 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1360 &sky2->tx_le_map);
1361 if (!sky2->tx_le)
1362 goto err_out;
1363
6cdbbdf3 1364 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1365 GFP_KERNEL);
1366 if (!sky2->tx_ring)
1367 goto err_out;
88f5f0ca
SH		 1368
1369 tx_init(sky2);
cd28ab6a
SH		 1370
1371 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1372 &sky2->rx_le_map);
1373 if (!sky2->rx_le)
1374 goto err_out;
1375 memset(sky2->rx_le, 0, RX_LE_BYTES);
1376
291ea614 1377 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1378 GFP_KERNEL);
1379 if (!sky2->rx_ring)
1380 goto err_out;
1381
d3bcfbeb 1382 sky2_phy_power(hw, port, 1);
1383
cd28ab6a
SH		 1384 sky2_mac_init(hw, port);
1385
e0c28116
SH		 1386 /* Register is number of 4K blocks on internal RAM buffer. */
1387 ramsize = sky2_read8(hw, B2_E_0) * 4;
1388 if (ramsize > 0) {
67712901 1389 u32 rxspace;
cd28ab6a 1390
39dbd958 1391 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1392 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1393 if (ramsize < 16)
1394 rxspace = ramsize / 2;
1395 else
1396 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1397
67712901
SH		 1398 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1399 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1400
1401 /* Make sure SyncQ is disabled */
1402 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1403 RB_RST_SET);
1404 }
793b883e 1405
af4ed7e6 1406 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1407
69161611
SH		 1408 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1409 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1410 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1411
977bdf06 1412 /* Set almost empty threshold */
c2716fb4
SH		 1413 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1414 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1415 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1416
6b1a3aef 1417 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1418 TX_RING_SIZE - 1);
cd28ab6a 1419
6b1a3aef 1420 err = sky2_rx_start(sky2);
6de16237 1421 if (err)
cd28ab6a
SH		 1422 goto err_out;
1423
cd28ab6a 1424 /* Enable interrupts from phy/mac for port */
e07b1aa8 1425 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1426 imask |= portirq_msk[port];
e07b1aa8
SH		 1427 sky2_write32(hw, B0_IMSK, imask);
1428
a7bffe72 1429 sky2_set_multicast(dev);
cd28ab6a
SH		 1430 return 0;
1431
1432err_out:
1b537565 1433 if (sky2->rx_le) {
cd28ab6a
SH		 1434 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1435 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1436 sky2->rx_le = NULL;
1437 }
1438 if (sky2->tx_le) {
cd28ab6a
SH		 1439 pci_free_consistent(hw->pdev,
1440 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1441 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1442 sky2->tx_le = NULL;
1443 }
1444 kfree(sky2->tx_ring);
1445 kfree(sky2->rx_ring);
cd28ab6a 1446
1b537565
SH		 1447 sky2->tx_ring = NULL;
1448 sky2->rx_ring = NULL;
cd28ab6a
SH		 1449 return err;
1450}
1451
793b883e
SH		 1452/* Modular subtraction in ring */
1453static inline int tx_dist(unsigned tail, unsigned head)
1454{
cb5d9547 1455 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1456}
cd28ab6a 1457
793b883e
SH		 1458/* Number of list elements available for next tx */
1459static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1460{
793b883e 1461 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1462}
1463
793b883e 1464/* Estimate of number of transmit list elements required */
28bd181a 1465static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1466{
793b883e
SH		 1467 unsigned count;
1468
1469 count = sizeof(dma_addr_t) / sizeof(u32);
1470 count += skb_shinfo(skb)->nr_frags * count;
1471
89114afd 1472 if (skb_is_gso(skb))
793b883e
SH		 1473 ++count;
1474
84fa7933 1475 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1476 ++count;
1477
1478 return count;
cd28ab6a
SH		 1479}
1480
793b883e
SH		 1481/*
1482 * Put one packet in ring for transmit.
1483 * A single packet can generate multiple list elements, and
1484 * the number of ring elements will probably be less than the number
1485 * of list elements used.
1486 */
cd28ab6a
SH		 1487static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1488{
1489 struct sky2_port *sky2 = netdev_priv(dev);
1490 struct sky2_hw *hw = sky2->hw;
d1f13708 1491 struct sky2_tx_le *le = NULL;
6cdbbdf3 1492 struct tx_ring_info *re;
cd28ab6a
SH		 1493 unsigned i, len;
1494 dma_addr_t mapping;
cd28ab6a
SH		 1495 u16 mss;
1496 u8 ctrl;
1497
2bb8c262
SH		 1498 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1499 return NETDEV_TX_BUSY;
cd28ab6a 1500
793b883e 1501 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1502 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1503 dev->name, sky2->tx_prod, skb->len);
1504
cd28ab6a
SH		 1505 len = skb_headlen(skb);
1506 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1507
86c6887e
SH		 1508 /* Send high bits if needed */
1509 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1510 le = get_tx_le(sky2);
86c6887e 1511 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1512 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1513 }
cd28ab6a
SH		 1514
1515 /* Check for TCP Segmentation Offload */
7967168c 1516 mss = skb_shinfo(skb)->gso_size;
793b883e 1517 if (mss != 0) {
ea76e635
SH		 1518
1519 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1520 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1521
1522 if (mss != sky2->tx_last_mss) {
1523 le = get_tx_le(sky2);
1524 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1525
1526 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1527 le->opcode = OP_MSS | HW_OWNER;
1528 else
1529 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1530 sky2->tx_last_mss = mss;
1531 }
cd28ab6a
SH		 1532 }
1533
cd28ab6a 1534 ctrl = 0;
d1f13708 1535#ifdef SKY2_VLAN_TAG_USED
1536 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1537 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1538 if (!le) {
1539 le = get_tx_le(sky2);
f65b138c 1540 le->addr = 0;
d1f13708 1541 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1542 } else
1543 le->opcode |= OP_VLAN;
1544 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1545 ctrl |= INS_VLAN;
1546 }
1547#endif
1548
1549 /* Handle TCP checksum offload */
84fa7933 1550 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1551 /* On Yukon EX (some versions) encoding change. */
ea76e635 1552 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1553 ctrl |= CALSUM; /* auto checksum */
1554 else {
1555 const unsigned offset = skb_transport_offset(skb);
1556 u32 tcpsum;
1557
1558 tcpsum = offset << 16; /* sum start */
1559 tcpsum |= offset + skb->csum_offset; /* sum write */
1560
1561 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1562 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1563 ctrl |= UDPTCP;
1564
1565 if (tcpsum != sky2->tx_tcpsum) {
1566 sky2->tx_tcpsum = tcpsum;
1567
1568 le = get_tx_le(sky2);
1569 le->addr = cpu_to_le32(tcpsum);
1570 le->length = 0; /* initial checksum value */
1571 le->ctrl = 1; /* one packet */
1572 le->opcode = OP_TCPLISW | HW_OWNER;
1573 }
1d179332 1574 }
cd28ab6a
SH		 1575 }
1576
1577 le = get_tx_le(sky2);
f65b138c 1578 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1579 le->length = cpu_to_le16(len);
1580 le->ctrl = ctrl;
793b883e 1581 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1582
291ea614 1583 re = tx_le_re(sky2, le);
cd28ab6a 1584 re->skb = skb;
6cdbbdf3 1585 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1586 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1587
1588 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1589 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1590
1591 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1592 frag->size, PCI_DMA_TODEVICE);
86c6887e
SH		 1593
1594 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1595 le = get_tx_le(sky2);
86c6887e 1596 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1597 le->ctrl = 0;
1598 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1599 }
1600
1601 le = get_tx_le(sky2);
f65b138c 1602 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1603 le->length = cpu_to_le16(frag->size);
1604 le->ctrl = ctrl;
793b883e 1605 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1606
291ea614
SH		 1607 re = tx_le_re(sky2, le);
1608 re->skb = skb;
1609 pci_unmap_addr_set(re, mapaddr, mapping);
1610 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1611 }
6cdbbdf3 1612
cd28ab6a
SH		 1613 le->ctrl |= EOP;
1614
97bda706 1615 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1616 netif_stop_queue(dev);
b19666d9 1617
290d4de5 1618 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1619
cd28ab6a
SH		 1620 dev->trans_start = jiffies;
1621 return NETDEV_TX_OK;
1622}
1623
cd28ab6a 1624/*
793b883e
SH		 1625 * Free ring elements from starting at tx_cons until "done"
1626 *
1627 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1628 * buffers so make sure not to free skb to early.
cd28ab6a 1629 */
d11c13e7 1630static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1631{
d11c13e7 1632 struct net_device *dev = sky2->netdev;
af2a58ac 1633 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1634 unsigned idx;
cd28ab6a 1635
0e3ff6aa 1636 BUG_ON(done >= TX_RING_SIZE);
2224795d 1637
291ea614
SH		 1638 for (idx = sky2->tx_cons; idx != done;
1639 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1640 struct sky2_tx_le *le = sky2->tx_le + idx;
1641 struct tx_ring_info *re = sky2->tx_ring + idx;
1642
1643 switch(le->opcode & ~HW_OWNER) {
1644 case OP_LARGESEND:
1645 case OP_PACKET:
1646 pci_unmap_single(pdev,
1647 pci_unmap_addr(re, mapaddr),
1648 pci_unmap_len(re, maplen),
1649 PCI_DMA_TODEVICE);
af2a58ac 1650 break;
291ea614
SH		 1651 case OP_BUFFER:
1652 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1653 pci_unmap_len(re, maplen),
734d1868 1654 PCI_DMA_TODEVICE);
291ea614
SH		 1655 break;
1656 }
1657
1658 if (le->ctrl & EOP) {
1659 if (unlikely(netif_msg_tx_done(sky2)))
1660 printk(KERN_DEBUG "%s: tx done %u\n",
1661 dev->name, idx);
3cf26753 1662
7138a0f5
SH		 1663 dev->stats.tx_packets++;
1664 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1665
794b2bd2 1666 dev_kfree_skb_any(re->skb);
3cf26753 1667 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1668 }
793b883e 1669 }
793b883e 1670
291ea614 1671 sky2->tx_cons = idx;
50432cb5
SH		 1672 smp_mb();
1673
22e11703 1674 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1675 netif_wake_queue(dev);
cd28ab6a
SH		 1676}
1677
1678/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1679static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1680{
2bb8c262
SH		 1681 struct sky2_port *sky2 = netdev_priv(dev);
1682
1683 netif_tx_lock_bh(dev);
d11c13e7 1684 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1685 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1686}
1687
1688/* Network shutdown */
1689static int sky2_down(struct net_device *dev)
1690{
1691 struct sky2_port *sky2 = netdev_priv(dev);
1692 struct sky2_hw *hw = sky2->hw;
1693 unsigned port = sky2->port;
1694 u16 ctrl;
e07b1aa8 1695 u32 imask;
cd28ab6a 1696
1b537565
SH		 1697 /* Never really got started! */
1698 if (!sky2->tx_le)
1699 return 0;
1700
cd28ab6a
SH		 1701 if (netif_msg_ifdown(sky2))
1702 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1703
018d1c66 1704 /* Stop more packets from being queued */
cd28ab6a
SH		 1705 netif_stop_queue(dev);
1706
ebc646f6
SH		 1707 /* Disable port IRQ */
1708 imask = sky2_read32(hw, B0_IMSK);
1709 imask &= ~portirq_msk[port];
1710 sky2_write32(hw, B0_IMSK, imask);
1711
6de16237
SH		 1712 synchronize_irq(hw->pdev->irq);
1713
d3bcfbeb 1714 sky2_gmac_reset(hw, port);
793b883e 1715
cd28ab6a
SH		 1716 /* Stop transmitter */
1717 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1718 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1719
1720 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1721 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1722
1723 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1724 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1725 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1726
6de16237
SH		 1727 /* Make sure no packets are pending */
1728 napi_synchronize(&hw->napi);
1729
cd28ab6a
SH		 1730 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1731
1732 /* Workaround shared GMAC reset */
793b883e
SH		 1733 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1734 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1735 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1736
1737 /* Disable Force Sync bit and Enable Alloc bit */
1738 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1739 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1740
1741 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1742 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1743 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1744
1745 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1746 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1747 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1748
1749 /* Reset the Tx prefetch units */
1750 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1751 PREF_UNIT_RST_SET);
1752
1753 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1754
6b1a3aef 1755 sky2_rx_stop(sky2);
cd28ab6a
SH		 1756
1757 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1758 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1759
d3bcfbeb 1760 sky2_phy_power(hw, port, 0);
1761
55d7b4e6
SH		 1762 netif_carrier_off(dev);
1763
d571b694 1764 /* turn off LED's */
cd28ab6a
SH		 1765 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1766
2bb8c262 1767 sky2_tx_clean(dev);
cd28ab6a
SH		 1768 sky2_rx_clean(sky2);
1769
1770 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1771 sky2->rx_le, sky2->rx_le_map);
1772 kfree(sky2->rx_ring);
1773
1774 pci_free_consistent(hw->pdev,
1775 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1776 sky2->tx_le, sky2->tx_le_map);
1777 kfree(sky2->tx_ring);
1778
1b537565
SH		 1779 sky2->tx_le = NULL;
1780 sky2->rx_le = NULL;
1781
1782 sky2->rx_ring = NULL;
1783 sky2->tx_ring = NULL;
1784
cd28ab6a
SH		 1785 return 0;
1786}
1787
1788static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1789{
ea76e635 1790 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1791 return SPEED_1000;
1792
05745c4a
SH		 1793 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1794 if (aux & PHY_M_PS_SPEED_100)
1795 return SPEED_100;
1796 else
1797 return SPEED_10;
1798 }
cd28ab6a
SH		 1799
1800 switch (aux & PHY_M_PS_SPEED_MSK) {
1801 case PHY_M_PS_SPEED_1000:
1802 return SPEED_1000;
1803 case PHY_M_PS_SPEED_100:
1804 return SPEED_100;
1805 default:
1806 return SPEED_10;
1807 }
1808}
1809
1810static void sky2_link_up(struct sky2_port *sky2)
1811{
1812 struct sky2_hw *hw = sky2->hw;
1813 unsigned port = sky2->port;
1814 u16 reg;
16ad91e1
SH		 1815 static const char *fc_name[] = {
1816 [FC_NONE] = "none",
1817 [FC_TX] = "tx",
1818 [FC_RX] = "rx",
1819 [FC_BOTH] = "both",
1820 };
cd28ab6a 1821
cd28ab6a 1822 /* enable Rx/Tx */
2eaba1a2 1823 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1824 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1825 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1826
1827 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1828
1829 netif_carrier_on(sky2->netdev);
cd28ab6a 1830
75e80683 1831 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1832
cd28ab6a 1833 /* Turn on link LED */
793b883e 1834 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1835 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1836
1837 if (netif_msg_link(sky2))
1838 printk(KERN_INFO PFX
d571b694 1839 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1840 sky2->netdev->name, sky2->speed,
1841 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1842 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1843}
1844
1845static void sky2_link_down(struct sky2_port *sky2)
1846{
1847 struct sky2_hw *hw = sky2->hw;
1848 unsigned port = sky2->port;
1849 u16 reg;
1850
1851 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1852
1853 reg = gma_read16(hw, port, GM_GP_CTRL);
1854 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1855 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1856
cd28ab6a 1857 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1858
1859 /* Turn on link LED */
1860 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1861
1862 if (netif_msg_link(sky2))
1863 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1864
cd28ab6a
SH		 1865 sky2_phy_init(hw, port);
1866}
1867
16ad91e1
SH		 1868static enum flow_control sky2_flow(int rx, int tx)
1869{
1870 if (rx)
1871 return tx ? FC_BOTH : FC_RX;
1872 else
1873 return tx ? FC_TX : FC_NONE;
1874}
1875
793b883e
SH		 1876static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1877{
1878 struct sky2_hw *hw = sky2->hw;
1879 unsigned port = sky2->port;
da4c1ff4 1880 u16 advert, lpa;
793b883e 1881
da4c1ff4 1882 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1883 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1884 if (lpa & PHY_M_AN_RF) {
1885 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1886 return -1;
1887 }
1888
793b883e
SH		 1889 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1890 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1891 sky2->netdev->name);
1892 return -1;
1893 }
1894
793b883e 1895 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1896 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1897
da4c1ff4
SH		 1898 /* Since the pause result bits seem to in different positions on
1899 * different chips. look at registers.
1900 */
ea76e635 1901 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1902 /* Shift for bits in fiber PHY */
1903 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1904 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1905
1906 if (advert & ADVERTISE_1000XPAUSE)
1907 advert |= ADVERTISE_PAUSE_CAP;
1908 if (advert & ADVERTISE_1000XPSE_ASYM)
1909 advert |= ADVERTISE_PAUSE_ASYM;
1910 if (lpa & LPA_1000XPAUSE)
1911 lpa |= LPA_PAUSE_CAP;
1912 if (lpa & LPA_1000XPAUSE_ASYM)
1913 lpa |= LPA_PAUSE_ASYM;
1914 }
793b883e 1915
da4c1ff4
SH		 1916 sky2->flow_status = FC_NONE;
1917 if (advert & ADVERTISE_PAUSE_CAP) {
1918 if (lpa & LPA_PAUSE_CAP)
1919 sky2->flow_status = FC_BOTH;
1920 else if (advert & ADVERTISE_PAUSE_ASYM)
1921 sky2->flow_status = FC_RX;
1922 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1923 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1924 sky2->flow_status = FC_TX;
1925 }
793b883e 1926
16ad91e1 1927 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1928 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1929 sky2->flow_status = FC_NONE;
2eaba1a2 1930
da4c1ff4 1931 if (sky2->flow_status & FC_TX)
793b883e
SH		 1932 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1933 else
1934 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1935
1936 return 0;
1937}
cd28ab6a 1938
e07b1aa8
SH		 1939/* Interrupt from PHY */
1940static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1941{
e07b1aa8
SH		 1942 struct net_device *dev = hw->dev[port];
1943 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1944 u16 istatus, phystat;
1945
ebc646f6
SH		 1946 if (!netif_running(dev))
1947 return;
1948
e07b1aa8
SH		 1949 spin_lock(&sky2->phy_lock);
1950 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1951 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1952
cd28ab6a
SH		 1953 if (netif_msg_intr(sky2))
1954 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1955 sky2->netdev->name, istatus, phystat);
1956
2eaba1a2 1957 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1958 if (sky2_autoneg_done(sky2, phystat) == 0)
1959 sky2_link_up(sky2);
1960 goto out;
1961 }
cd28ab6a 1962
793b883e
SH		 1963 if (istatus & PHY_M_IS_LSP_CHANGE)
1964 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1965
793b883e
SH		 1966 if (istatus & PHY_M_IS_DUP_CHANGE)
1967 sky2->duplex =
1968 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1969
793b883e
SH		 1970 if (istatus & PHY_M_IS_LST_CHANGE) {
1971 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1972 sky2_link_up(sky2);
793b883e
SH		 1973 else
1974 sky2_link_down(sky2);
cd28ab6a 1975 }
793b883e 1976out:
e07b1aa8 1977 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1978}
1979
62335ab0 1980/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1981 * and tx queue is full (stopped).
1982 */
cd28ab6a
SH		 1983static void sky2_tx_timeout(struct net_device *dev)
1984{
1985 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1986 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1987
1988 if (netif_msg_timer(sky2))
1989 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1990
8f24664d 1991 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1992 dev->name, sky2->tx_cons, sky2->tx_prod,
1993 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1994 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1995
81906791
SH		 1996 /* can't restart safely under softirq */
1997 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1998}
1999
2000static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2001{
6b1a3aef 2002 struct sky2_port *sky2 = netdev_priv(dev);
2003 struct sky2_hw *hw = sky2->hw;
b628ed98 2004 unsigned port = sky2->port;
6b1a3aef 2005 int err;
2006 u16 ctl, mode;
e07b1aa8 2007 u32 imask;
cd28ab6a
SH		 2008
2009 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2010 return -EINVAL;
2011
05745c4a
SH		 2012 if (new_mtu > ETH_DATA_LEN &&
2013 (hw->chip_id == CHIP_ID_YUKON_FE ||
2014 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2015 return -EINVAL;
2016
6b1a3aef 2017 if (!netif_running(dev)) {
2018 dev->mtu = new_mtu;
2019 return 0;
2020 }
2021
e07b1aa8 2022 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2023 sky2_write32(hw, B0_IMSK, 0);
2024
018d1c66 2025 dev->trans_start = jiffies; /* prevent tx timeout */
2026 netif_stop_queue(dev);
bea3348e 2027 napi_disable(&hw->napi);
018d1c66 2028
e07b1aa8
SH		 2029 synchronize_irq(hw->pdev->irq);
2030
39dbd958 2031 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2032 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2033
2034 ctl = gma_read16(hw, port, GM_GP_CTRL);
2035 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2036 sky2_rx_stop(sky2);
2037 sky2_rx_clean(sky2);
cd28ab6a
SH		 2038
2039 dev->mtu = new_mtu;
14d0263f 2040
6b1a3aef 2041 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2042 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2043
2044 if (dev->mtu > ETH_DATA_LEN)
2045 mode |= GM_SMOD_JUMBO_ENA;
2046
b628ed98 2047 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2048
b628ed98 2049 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2050
6b1a3aef 2051 err = sky2_rx_start(sky2);
e07b1aa8 2052 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2053
d1d08d12 2054 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2055 napi_enable(&hw->napi);
2056
1b537565
SH		 2057 if (err)
2058 dev_close(dev);
2059 else {
b628ed98 2060 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2061
1b537565
SH		 2062 netif_wake_queue(dev);
2063 }
2064
cd28ab6a
SH		 2065 return err;
2066}
2067
14d0263f
SH		 2068/* For small just reuse existing skb for next receive */
2069static struct sk_buff *receive_copy(struct sky2_port *sky2,
2070 const struct rx_ring_info *re,
2071 unsigned length)
2072{
2073 struct sk_buff *skb;
2074
2075 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2076 if (likely(skb)) {
2077 skb_reserve(skb, 2);
2078 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2079 length, PCI_DMA_FROMDEVICE);
d626f62b 2080 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2081 skb->ip_summed = re->skb->ip_summed;
2082 skb->csum = re->skb->csum;
2083 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2084 length, PCI_DMA_FROMDEVICE);
2085 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2086 skb_put(skb, length);
14d0263f
SH		 2087 }
2088 return skb;
2089}
2090
2091/* Adjust length of skb with fragments to match received data */
2092static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2093 unsigned int length)
2094{
2095 int i, num_frags;
2096 unsigned int size;
2097
2098 /* put header into skb */
2099 size = min(length, hdr_space);
2100 skb->tail += size;
2101 skb->len += size;
2102 length -= size;
2103
2104 num_frags = skb_shinfo(skb)->nr_frags;
2105 for (i = 0; i < num_frags; i++) {
2106 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2107
2108 if (length == 0) {
2109 /* don't need this page */
2110 __free_page(frag->page);
2111 --skb_shinfo(skb)->nr_frags;
2112 } else {
2113 size = min(length, (unsigned) PAGE_SIZE);
2114
2115 frag->size = size;
2116 skb->data_len += size;
2117 skb->truesize += size;
2118 skb->len += size;
2119 length -= size;
2120 }
2121 }
2122}
2123
2124/* Normal packet - take skb from ring element and put in a new one */
2125static struct sk_buff *receive_new(struct sky2_port *sky2,
2126 struct rx_ring_info *re,
2127 unsigned int length)
2128{
2129 struct sk_buff *skb, *nskb;
2130 unsigned hdr_space = sky2->rx_data_size;
2131
14d0263f
SH		 2132 /* Don't be tricky about reusing pages (yet) */
2133 nskb = sky2_rx_alloc(sky2);
2134 if (unlikely(!nskb))
2135 return NULL;
2136
2137 skb = re->skb;
2138 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2139
2140 prefetch(skb->data);
2141 re->skb = nskb;
2142 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2143
2144 if (skb_shinfo(skb)->nr_frags)
2145 skb_put_frags(skb, hdr_space, length);
2146 else
489b10c1 2147 skb_put(skb, length);
14d0263f
SH		 2148 return skb;
2149}
2150
cd28ab6a
SH		 2151/*
2152 * Receive one packet.
d571b694 2153 * For larger packets, get new buffer.
cd28ab6a 2154 */
497d7c86 2155static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2156 u16 length, u32 status)
2157{
497d7c86 2158 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2159 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2160 struct sk_buff *skb = NULL;
d6532232
SH		 2161 u16 count = (status & GMR_FS_LEN) >> 16;
2162
2163#ifdef SKY2_VLAN_TAG_USED
2164 /* Account for vlan tag */
2165 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2166 count -= VLAN_HLEN;
2167#endif
cd28ab6a
SH		 2168
2169 if (unlikely(netif_msg_rx_status(sky2)))
2170 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2171 dev->name, sky2->rx_next, status, length);
cd28ab6a 2172
793b883e 2173 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2174 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2175
3b12e014
SH		 2176 /* This chip has hardware problems that generates bogus status.
2177 * So do only marginal checking and expect higher level protocols
2178 * to handle crap frames.
2179 */
2180 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2181 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2182 length != count)
2183 goto okay;
2184
42eeea01 2185 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2186 goto error;
2187
42eeea01 2188 if (!(status & GMR_FS_RX_OK))
2189 goto resubmit;
2190
d6532232
SH		 2191 /* if length reported by DMA does not match PHY, packet was truncated */
2192 if (length != count)
3b12e014 2193 goto len_error;
71749531 2194
3b12e014 2195okay:
14d0263f
SH		 2196 if (length < copybreak)
2197 skb = receive_copy(sky2, re, length);
2198 else
2199 skb = receive_new(sky2, re, length);
793b883e 2200resubmit:
14d0263f 2201 sky2_rx_submit(sky2, re);
79e57d32 2202
cd28ab6a
SH		 2203 return skb;
2204
3b12e014 2205len_error:
71749531
SH		 2206 /* Truncation of overlength packets
2207 causes PHY length to not match MAC length */
7138a0f5 2208 ++dev->stats.rx_length_errors;
d6532232 2209 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2210 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2211 dev->name, status, length);
d6532232 2212 goto resubmit;
71749531 2213
cd28ab6a 2214error:
7138a0f5 2215 ++dev->stats.rx_errors;
b6d77734 2216 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2217 dev->stats.rx_over_errors++;
b6d77734
SH		 2218 goto resubmit;
2219 }
6e15b712 2220
3be92a70 2221 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2222 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2223 dev->name, status, length);
793b883e
SH		 2224
2225 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2226 dev->stats.rx_length_errors++;
cd28ab6a 2227 if (status & GMR_FS_FRAGMENT)
7138a0f5 2228 dev->stats.rx_frame_errors++;
cd28ab6a 2229 if (status & GMR_FS_CRC_ERR)
7138a0f5 2230 dev->stats.rx_crc_errors++;
79e57d32 2231
793b883e 2232 goto resubmit;
cd28ab6a
SH		 2233}
2234
e07b1aa8
SH		 2235/* Transmit complete */
2236static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2237{
e07b1aa8 2238 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2239
e07b1aa8 2240 if (netif_running(dev)) {
2bb8c262 2241 netif_tx_lock(dev);
e07b1aa8 2242 sky2_tx_complete(sky2, last);
2bb8c262 2243 netif_tx_unlock(dev);
2224795d 2244 }
cd28ab6a
SH		 2245}
2246
e07b1aa8 2247/* Process status response ring */
26691830 2248static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2249{
e07b1aa8 2250 int work_done = 0;
55c9dd35 2251 unsigned rx[2] = { 0, 0 };
a8fd6266 2252
af2a58ac 2253 rmb();
26691830 2254 do {
55c9dd35 2255 struct sky2_port *sky2;
13210ce5 2256 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2257 unsigned port;
13210ce5 2258 struct net_device *dev;
cd28ab6a 2259 struct sk_buff *skb;
cd28ab6a
SH		 2260 u32 status;
2261 u16 length;
ab5adecb
SH		 2262 u8 opcode = le->opcode;
2263
2264 if (!(opcode & HW_OWNER))
2265 break;
cd28ab6a 2266
cb5d9547 2267 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2268
ab5adecb 2269 port = le->css & CSS_LINK_BIT;
69161611 2270 dev = hw->dev[port];
13210ce5 2271 sky2 = netdev_priv(dev);
f65b138c
SH		 2272 length = le16_to_cpu(le->length);
2273 status = le32_to_cpu(le->status);
cd28ab6a 2274
ab5adecb
SH		 2275 le->opcode = 0;
2276 switch (opcode & ~HW_OWNER) {
cd28ab6a 2277 case OP_RXSTAT:
55c9dd35 2278 ++rx[port];
497d7c86 2279 skb = sky2_receive(dev, length, status);
3225b919 2280 if (unlikely(!skb)) {
7138a0f5 2281 dev->stats.rx_dropped++;
55c9dd35 2282 break;
3225b919 2283 }
13210ce5 2284
69161611 2285 /* This chip reports checksum status differently */
05745c4a 2286 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2287 if (sky2->rx_csum &&
2288 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2289 (le->css & CSS_TCPUDPCSOK))
2290 skb->ip_summed = CHECKSUM_UNNECESSARY;
2291 else
2292 skb->ip_summed = CHECKSUM_NONE;
2293 }
2294
13210ce5 2295 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2296 dev->stats.rx_packets++;
2297 dev->stats.rx_bytes += skb->len;
13210ce5 2298 dev->last_rx = jiffies;
2299
d1f13708 2300#ifdef SKY2_VLAN_TAG_USED
2301 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2302 vlan_hwaccel_receive_skb(skb,
2303 sky2->vlgrp,
2304 be16_to_cpu(sky2->rx_tag));
2305 } else
2306#endif
cd28ab6a 2307 netif_receive_skb(skb);
13210ce5 2308
22e11703 2309 /* Stop after net poll weight */
13210ce5 2310 if (++work_done >= to_do)
2311 goto exit_loop;
cd28ab6a
SH		 2312 break;
2313
d1f13708 2314#ifdef SKY2_VLAN_TAG_USED
2315 case OP_RXVLAN:
2316 sky2->rx_tag = length;
2317 break;
2318
2319 case OP_RXCHKSVLAN:
2320 sky2->rx_tag = length;
2321 /* fall through */
2322#endif
cd28ab6a 2323 case OP_RXCHKS:
87418307
SH		 2324 if (!sky2->rx_csum)
2325 break;
2326
05745c4a
SH		 2327 /* If this happens then driver assuming wrong format */
2328 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2329 if (net_ratelimit())
2330 printk(KERN_NOTICE "%s: unexpected"
2331 " checksum status\n",
2332 dev->name);
69161611 2333 break;
05745c4a 2334 }
69161611 2335
87418307
SH		 2336 /* Both checksum counters are programmed to start at
2337 * the same offset, so unless there is a problem they
2338 * should match. This failure is an early indication that
2339 * hardware receive checksumming won't work.
2340 */
2341 if (likely(status >> 16 == (status & 0xffff))) {
2342 skb = sky2->rx_ring[sky2->rx_next].skb;
2343 skb->ip_summed = CHECKSUM_COMPLETE;
2344 skb->csum = status & 0xffff;
2345 } else {
2346 printk(KERN_NOTICE PFX "%s: hardware receive "
2347 "checksum problem (status = %#x)\n",
2348 dev->name, status);
2349 sky2->rx_csum = 0;
2350 sky2_write32(sky2->hw,
69161611 2351 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2352 BMU_DIS_RX_CHKSUM);
2353 }
cd28ab6a
SH		 2354 break;
2355
2356 case OP_TXINDEXLE:
13b97b74 2357 /* TX index reports status for both ports */
f55925d7
SH		 2358 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2359 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2360 if (hw->dev[1])
2361 sky2_tx_done(hw->dev[1],
2362 ((status >> 24) & 0xff)
2363 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2364 break;
2365
cd28ab6a
SH		 2366 default:
2367 if (net_ratelimit())
793b883e 2368 printk(KERN_WARNING PFX
ab5adecb 2369 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2370 }
26691830 2371 } while (hw->st_idx != idx);
cd28ab6a 2372
fe2a24df
SH		 2373 /* Fully processed status ring so clear irq */
2374 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2375
13210ce5 2376exit_loop:
55c9dd35
SH		 2377 if (rx[0])
2378 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2379
55c9dd35
SH		 2380 if (rx[1])
2381 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2382
e07b1aa8 2383 return work_done;
cd28ab6a
SH		 2384}
2385
2386static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2387{
2388 struct net_device *dev = hw->dev[port];
2389
3be92a70
SH		 2390 if (net_ratelimit())
2391 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2392 dev->name, status);
cd28ab6a
SH		 2393
2394 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2395 if (net_ratelimit())
2396 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2397 dev->name);
cd28ab6a
SH		 2398 /* Clear IRQ */
2399 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2400 }
2401
2402 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2403 if (net_ratelimit())
2404 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2405 dev->name);
cd28ab6a
SH		 2406
2407 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2408 }
2409
2410 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2411 if (net_ratelimit())
2412 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2413 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2414 }
2415
2416 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2417 if (net_ratelimit())
2418 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2419 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2420 }
2421
2422 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2423 if (net_ratelimit())
2424 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2425 dev->name);
cd28ab6a
SH		 2426 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2427 }
2428}
2429
2430static void sky2_hw_intr(struct sky2_hw *hw)
2431{
555382cb 2432 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2433 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2434 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2435
2436 status &= hwmsk;
cd28ab6a 2437
793b883e 2438 if (status & Y2_IS_TIST_OV)
cd28ab6a 2439 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2440
2441 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2442 u16 pci_err;
2443
82637e80 2444 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2445 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2446 if (net_ratelimit())
555382cb 2447 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2448 pci_err);
cd28ab6a 2449
b32f40c4 2450 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2451 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2452 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2453 }
2454
2455 if (status & Y2_IS_PCI_EXP) {
d571b694 2456 /* PCI-Express uncorrectable Error occurred */
555382cb 2457 u32 err;
cd28ab6a 2458
82637e80 2459 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2460 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2461 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2462 0xfffffffful);
3be92a70 2463 if (net_ratelimit())
555382cb 2464 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2465
7782c8c4 2466 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2467 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2468 }
2469
2470 if (status & Y2_HWE_L1_MASK)
2471 sky2_hw_error(hw, 0, status);
2472 status >>= 8;
2473 if (status & Y2_HWE_L1_MASK)
2474 sky2_hw_error(hw, 1, status);
2475}
2476
2477static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2478{
2479 struct net_device *dev = hw->dev[port];
2480 struct sky2_port *sky2 = netdev_priv(dev);
2481 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2482
2483 if (netif_msg_intr(sky2))
2484 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2485 dev->name, status);
2486
a3caeada
SH		 2487 if (status & GM_IS_RX_CO_OV)
2488 gma_read16(hw, port, GM_RX_IRQ_SRC);
2489
2490 if (status & GM_IS_TX_CO_OV)
2491 gma_read16(hw, port, GM_TX_IRQ_SRC);
2492
cd28ab6a 2493 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2494 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2495 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2496 }
2497
2498 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2499 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2500 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2501 }
cd28ab6a
SH		 2502}
2503
40b01727
SH		 2504/* This should never happen it is a bug. */
2505static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2506 u16 q, unsigned ring_size)
d257924e
SH		 2507{
2508 struct net_device *dev = hw->dev[port];
2509 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2510 unsigned idx;
2511 const u64 *le = (q == Q_R1 || q == Q_R2)
2512 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2513
40b01727
SH		 2514 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2515 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2516 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2517 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2518
40b01727 2519 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2520}
cd28ab6a 2521
75e80683
SH		 2522static int sky2_rx_hung(struct net_device *dev)
2523{
2524 struct sky2_port *sky2 = netdev_priv(dev);
2525 struct sky2_hw *hw = sky2->hw;
2526 unsigned port = sky2->port;
2527 unsigned rxq = rxqaddr[port];
2528 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2529 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2530 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2531 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2532
2533 /* If idle and MAC or PCI is stuck */
2534 if (sky2->check.last == dev->last_rx &&
2535 ((mac_rp == sky2->check.mac_rp &&
2536 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2537 /* Check if the PCI RX hang */
2538 (fifo_rp == sky2->check.fifo_rp &&
2539 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2540 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2541 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2542 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2543 return 1;
2544 } else {
2545 sky2->check.last = dev->last_rx;
2546 sky2->check.mac_rp = mac_rp;
2547 sky2->check.mac_lev = mac_lev;
2548 sky2->check.fifo_rp = fifo_rp;
2549 sky2->check.fifo_lev = fifo_lev;
2550 return 0;
2551 }
2552}
2553
32c2c300 2554static void sky2_watchdog(unsigned long arg)
d27ed387 2555{
01bd7564 2556 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2557
75e80683 2558 /* Check for lost IRQ once a second */
32c2c300 2559 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2560 napi_schedule(&hw->napi);
75e80683
SH		 2561 } else {
2562 int i, active = 0;
2563
2564 for (i = 0; i < hw->ports; i++) {
bea3348e 2565 struct net_device *dev = hw->dev[i];
75e80683
SH		 2566 if (!netif_running(dev))
2567 continue;
2568 ++active;
2569
2570 /* For chips with Rx FIFO, check if stuck */
39dbd958 2571 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2572 sky2_rx_hung(dev)) {
2573 pr_info(PFX "%s: receiver hang detected\n",
2574 dev->name);
2575 schedule_work(&hw->restart_work);
2576 return;
2577 }
2578 }
2579
2580 if (active == 0)
2581 return;
32c2c300 2582 }
01bd7564 2583
75e80683 2584 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2585}
2586
40b01727
SH		 2587/* Hardware/software error handling */
2588static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2589{
40b01727
SH		 2590 if (net_ratelimit())
2591 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2592
1e5f1283
SH		 2593 if (status & Y2_IS_HW_ERR)
2594 sky2_hw_intr(hw);
d257924e 2595
1e5f1283
SH		 2596 if (status & Y2_IS_IRQ_MAC1)
2597 sky2_mac_intr(hw, 0);
cd28ab6a 2598
1e5f1283
SH		 2599 if (status & Y2_IS_IRQ_MAC2)
2600 sky2_mac_intr(hw, 1);
cd28ab6a 2601
1e5f1283 2602 if (status & Y2_IS_CHK_RX1)
40b01727 2603 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2604
1e5f1283 2605 if (status & Y2_IS_CHK_RX2)
40b01727 2606 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2607
1e5f1283 2608 if (status & Y2_IS_CHK_TXA1)
40b01727 2609 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2610
1e5f1283 2611 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2612 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2613}
2614
bea3348e 2615static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2616{
bea3348e 2617 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2618 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2619 int work_done = 0;
26691830 2620 u16 idx;
40b01727
SH		 2621
2622 if (unlikely(status & Y2_IS_ERROR))
2623 sky2_err_intr(hw, status);
2624
2625 if (status & Y2_IS_IRQ_PHY1)
2626 sky2_phy_intr(hw, 0);
2627
2628 if (status & Y2_IS_IRQ_PHY2)
2629 sky2_phy_intr(hw, 1);
cd28ab6a 2630
26691830
SH		 2631 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2632 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2633
2634 if (work_done >= work_limit)
26691830
SH		 2635 goto done;
2636 }
6f535763 2637
26691830
SH		 2638 /* Bug/Errata workaround?
2639 * Need to kick the TX irq moderation timer.
2640 */
2641 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2642 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2643 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2644 }
26691830
SH		 2645 napi_complete(napi);
2646 sky2_read32(hw, B0_Y2_SP_LISR);
2647done:
6f535763 2648
bea3348e 2649 return work_done;
e07b1aa8
SH		 2650}
2651
7d12e780 2652static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2653{
2654 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2655 u32 status;
2656
2657 /* Reading this mask interrupts as side effect */
2658 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2659 if (status == 0 || status == ~0)
2660 return IRQ_NONE;
793b883e 2661
e07b1aa8 2662 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2663
2664 napi_schedule(&hw->napi);
793b883e 2665
cd28ab6a
SH		 2666 return IRQ_HANDLED;
2667}
2668
2669#ifdef CONFIG_NET_POLL_CONTROLLER
2670static void sky2_netpoll(struct net_device *dev)
2671{
2672 struct sky2_port *sky2 = netdev_priv(dev);
2673
bea3348e 2674 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2675}
2676#endif
2677
2678/* Chip internal frequency for clock calculations */
05745c4a 2679static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2680{
793b883e 2681 switch (hw->chip_id) {
cd28ab6a 2682 case CHIP_ID_YUKON_EC:
5a5b1ea0 2683 case CHIP_ID_YUKON_EC_U:
93745494 2684 case CHIP_ID_YUKON_EX:
ed4d4161 2685 case CHIP_ID_YUKON_SUPR:
05745c4a
SH		 2686 return 125;
2687
cd28ab6a 2688 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2689 return 100;
2690
2691 case CHIP_ID_YUKON_FE_P:
2692 return 50;
2693
2694 case CHIP_ID_YUKON_XL:
2695 return 156;
2696
2697 default:
2698 BUG();
cd28ab6a
SH		 2699 }
2700}
2701
fb17358f 2702static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2703{
fb17358f 2704 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2705}
2706
fb17358f 2707static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2708{
fb17358f 2709 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2710}
2711
fb17358f 2712
e3173832 2713static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2714{
b89165f2 2715 u8 t8;
cd28ab6a 2716
167f53d0 2717 /* Enable all clocks and check for bad PCI access */
b32f40c4 2718 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2719
cd28ab6a 2720 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2721
cd28ab6a 2722 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2723 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2724
2725 switch(hw->chip_id) {
2726 case CHIP_ID_YUKON_XL:
39dbd958 2727 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2728 break;
2729
2730 case CHIP_ID_YUKON_EC_U:
2731 hw->flags = SKY2_HW_GIGABIT
2732 | SKY2_HW_NEWER_PHY
2733 | SKY2_HW_ADV_POWER_CTL;
2734 break;
2735
2736 case CHIP_ID_YUKON_EX:
2737 hw->flags = SKY2_HW_GIGABIT
2738 | SKY2_HW_NEWER_PHY
2739 | SKY2_HW_NEW_LE
2740 | SKY2_HW_ADV_POWER_CTL;
2741
2742 /* New transmit checksum */
2743 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2744 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2745 break;
2746
2747 case CHIP_ID_YUKON_EC:
2748 /* This rev is really old, and requires untested workarounds */
2749 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2750 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2751 return -EOPNOTSUPP;
2752 }
39dbd958 2753 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2754 break;
2755
2756 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2757 break;
2758
05745c4a
SH		 2759 case CHIP_ID_YUKON_FE_P:
2760 hw->flags = SKY2_HW_NEWER_PHY
2761 | SKY2_HW_NEW_LE
2762 | SKY2_HW_AUTO_TX_SUM
2763 | SKY2_HW_ADV_POWER_CTL;
2764 break;
ed4d4161
SH		 2765
2766 case CHIP_ID_YUKON_SUPR:
2767 hw->flags = SKY2_HW_GIGABIT
2768 | SKY2_HW_NEWER_PHY
2769 | SKY2_HW_NEW_LE
2770 | SKY2_HW_AUTO_TX_SUM
2771 | SKY2_HW_ADV_POWER_CTL;
2772 break;
2773
ea76e635 2774 default:
b02a9258
SH		 2775 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2776 hw->chip_id);
cd28ab6a
SH		 2777 return -EOPNOTSUPP;
2778 }
2779
ea76e635
SH		 2780 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2781 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2782 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2783
290d4de5 2784
e3173832
SH		 2785 hw->ports = 1;
2786 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2787 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2788 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2789 ++hw->ports;
2790 }
2791
2792 return 0;
2793}
2794
2795static void sky2_reset(struct sky2_hw *hw)
2796{
555382cb 2797 struct pci_dev *pdev = hw->pdev;
e3173832 2798 u16 status;
555382cb
SH		 2799 int i, cap;
2800 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2801
cd28ab6a 2802 /* disable ASF */
4f44d8ba
SH		 2803 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2804 status = sky2_read16(hw, HCU_CCSR);
2805 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2806 HCU_CCSR_UC_STATE_MSK);
2807 sky2_write16(hw, HCU_CCSR, status);
2808 } else
2809 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2810 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2811
2812 /* do a SW reset */
2813 sky2_write8(hw, B0_CTST, CS_RST_SET);
2814 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2815
ac93a394
SH		 2816 /* allow writes to PCI config */
2817 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2818
cd28ab6a 2819 /* clear PCI errors, if any */
b32f40c4 2820 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2821 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2822 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2823
2824 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2825
555382cb
SH		 2826 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2827 if (cap) {
7782c8c4
SH		 2828 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2829 0xfffffffful);
555382cb
SH		 2830
2831 /* If error bit is stuck on ignore it */
2832 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2833 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2834 else
555382cb
SH		 2835 hwe_mask |= Y2_IS_PCI_EXP;
2836 }
cd28ab6a 2837
ae306cca 2838 sky2_power_on(hw);
82637e80 2839 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2840
2841 for (i = 0; i < hw->ports; i++) {
2842 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2843 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2844
ed4d4161
SH		 2845 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2846 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2847 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2848 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2849 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2850 }
2851
793b883e
SH		 2852 /* Clear I2C IRQ noise */
2853 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2854
2855 /* turn off hardware timer (unused) */
2856 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2857 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2858
cd28ab6a
SH		 2859 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2860
69634ee7
SH		 2861 /* Turn off descriptor polling */
2862 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2863
2864 /* Turn off receive timestamp */
2865 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2866 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2867
2868 /* enable the Tx Arbiters */
2869 for (i = 0; i < hw->ports; i++)
2870 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2871
2872 /* Initialize ram interface */
2873 for (i = 0; i < hw->ports; i++) {
793b883e 2874 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2875
2876 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2877 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2878 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2879 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2880 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2881 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2882 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2883 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2884 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2885 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2886 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2887 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2888 }
2889
555382cb 2890 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2891
cd28ab6a 2892 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2893 sky2_gmac_reset(hw, i);
cd28ab6a 2894
cd28ab6a
SH		 2895 memset(hw->st_le, 0, STATUS_LE_BYTES);
2896 hw->st_idx = 0;
2897
2898 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2899 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2900
2901 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2902 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2903
2904 /* Set the list last index */
793b883e 2905 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2906
290d4de5
SH		 2907 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2908 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2909
290d4de5
SH		 2910 /* set Status-FIFO ISR watermark */
2911 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2912 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2913 else
2914 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2915
290d4de5 2916 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2917 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2918 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2919
793b883e 2920 /* enable status unit */
cd28ab6a
SH		 2921 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2922
2923 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2924 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2925 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2926}
2927
81906791
SH		 2928static void sky2_restart(struct work_struct *work)
2929{
2930 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2931 struct net_device *dev;
2932 int i, err;
2933
81906791 2934 rtnl_lock();
81906791
SH		 2935 for (i = 0; i < hw->ports; i++) {
2936 dev = hw->dev[i];
2937 if (netif_running(dev))
2938 sky2_down(dev);
2939 }
2940
8cfcbe99
SH		 2941 napi_disable(&hw->napi);
2942 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 2943 sky2_reset(hw);
2944 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2945 napi_enable(&hw->napi);
81906791
SH		 2946
2947 for (i = 0; i < hw->ports; i++) {
2948 dev = hw->dev[i];
2949 if (netif_running(dev)) {
2950 err = sky2_up(dev);
2951 if (err) {
2952 printk(KERN_INFO PFX "%s: could not restart %d\n",
2953 dev->name, err);
2954 dev_close(dev);
2955 }
2956 }
2957 }
2958
81906791
SH		 2959 rtnl_unlock();
2960}
2961
e3173832
SH		 2962static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2963{
2964 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2965}
2966
2967static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2968{
2969 const struct sky2_port *sky2 = netdev_priv(dev);
2970
2971 wol->supported = sky2_wol_supported(sky2->hw);
2972 wol->wolopts = sky2->wol;
2973}
2974
2975static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2976{
2977 struct sky2_port *sky2 = netdev_priv(dev);
2978 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2979
e3173832
SH		 2980 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2981 return -EOPNOTSUPP;
2982
2983 sky2->wol = wol->wolopts;
2984
05745c4a
SH		 2985 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2986 hw->chip_id == CHIP_ID_YUKON_EX ||
2987 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2988 sky2_write32(hw, B0_CTST, sky2->wol
2989 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2990
2991 if (!netif_running(dev))
2992 sky2_wol_init(sky2);
cd28ab6a
SH		 2993 return 0;
2994}
2995
28bd181a 2996static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2997{
b89165f2
SH		 2998 if (sky2_is_copper(hw)) {
2999 u32 modes = SUPPORTED_10baseT_Half
3000 | SUPPORTED_10baseT_Full
3001 | SUPPORTED_100baseT_Half
3002 | SUPPORTED_100baseT_Full
3003 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3004
ea76e635 3005 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3006 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3007 | SUPPORTED_1000baseT_Full;
3008 return modes;
cd28ab6a 3009 } else
b89165f2
SH		 3010 return SUPPORTED_1000baseT_Half
3011 | SUPPORTED_1000baseT_Full
3012 | SUPPORTED_Autoneg
3013 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3014}
3015
793b883e 3016static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3017{
3018 struct sky2_port *sky2 = netdev_priv(dev);
3019 struct sky2_hw *hw = sky2->hw;
3020
3021 ecmd->transceiver = XCVR_INTERNAL;
3022 ecmd->supported = sky2_supported_modes(hw);
3023 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3024 if (sky2_is_copper(hw)) {
cd28ab6a 3025 ecmd->port = PORT_TP;
b89165f2
SH		 3026 ecmd->speed = sky2->speed;
3027 } else {
3028 ecmd->speed = SPEED_1000;
cd28ab6a 3029 ecmd->port = PORT_FIBRE;
b89165f2 3030 }
cd28ab6a
SH		 3031
3032 ecmd->advertising = sky2->advertising;
3033 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3034 ecmd->duplex = sky2->duplex;
3035 return 0;
3036}
3037
3038static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3039{
3040 struct sky2_port *sky2 = netdev_priv(dev);
3041 const struct sky2_hw *hw = sky2->hw;
3042 u32 supported = sky2_supported_modes(hw);
3043
3044 if (ecmd->autoneg == AUTONEG_ENABLE) {
3045 ecmd->advertising = supported;
3046 sky2->duplex = -1;
3047 sky2->speed = -1;
3048 } else {
3049 u32 setting;
3050
793b883e 3051 switch (ecmd->speed) {
cd28ab6a
SH		 3052 case SPEED_1000:
3053 if (ecmd->duplex == DUPLEX_FULL)
3054 setting = SUPPORTED_1000baseT_Full;
3055 else if (ecmd->duplex == DUPLEX_HALF)
3056 setting = SUPPORTED_1000baseT_Half;
3057 else
3058 return -EINVAL;
3059 break;
3060 case SPEED_100:
3061 if (ecmd->duplex == DUPLEX_FULL)
3062 setting = SUPPORTED_100baseT_Full;
3063 else if (ecmd->duplex == DUPLEX_HALF)
3064 setting = SUPPORTED_100baseT_Half;
3065 else
3066 return -EINVAL;
3067 break;
3068
3069 case SPEED_10:
3070 if (ecmd->duplex == DUPLEX_FULL)
3071 setting = SUPPORTED_10baseT_Full;
3072 else if (ecmd->duplex == DUPLEX_HALF)
3073 setting = SUPPORTED_10baseT_Half;
3074 else
3075 return -EINVAL;
3076 break;
3077 default:
3078 return -EINVAL;
3079 }
3080
3081 if ((setting & supported) == 0)
3082 return -EINVAL;
3083
3084 sky2->speed = ecmd->speed;
3085 sky2->duplex = ecmd->duplex;
3086 }
3087
3088 sky2->autoneg = ecmd->autoneg;
3089 sky2->advertising = ecmd->advertising;
3090
d1b139c0 3091 if (netif_running(dev)) {
1b537565 3092 sky2_phy_reinit(sky2);
d1b139c0
SH		 3093 sky2_set_multicast(dev);
3094 }
cd28ab6a
SH		 3095
3096 return 0;
3097}
3098
3099static void sky2_get_drvinfo(struct net_device *dev,
3100 struct ethtool_drvinfo *info)
3101{
3102 struct sky2_port *sky2 = netdev_priv(dev);
3103
3104 strcpy(info->driver, DRV_NAME);
3105 strcpy(info->version, DRV_VERSION);
3106 strcpy(info->fw_version, "N/A");
3107 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3108}
3109
3110static const struct sky2_stat {
793b883e
SH		 3111 char name[ETH_GSTRING_LEN];
3112 u16 offset;
cd28ab6a
SH		 3113} sky2_stats[] = {
3114 { "tx_bytes", GM_TXO_OK_HI },
3115 { "rx_bytes", GM_RXO_OK_HI },
3116 { "tx_broadcast", GM_TXF_BC_OK },
3117 { "rx_broadcast", GM_RXF_BC_OK },
3118 { "tx_multicast", GM_TXF_MC_OK },
3119 { "rx_multicast", GM_RXF_MC_OK },
3120 { "tx_unicast", GM_TXF_UC_OK },
3121 { "rx_unicast", GM_RXF_UC_OK },
3122 { "tx_mac_pause", GM_TXF_MPAUSE },
3123 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3124 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3125 { "late_collision",GM_TXF_LAT_COL },
3126 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3127 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3128 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3129
d2604540 3130 { "rx_short", GM_RXF_SHT },
cd28ab6a 3131 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3132 { "rx_64_byte_packets", GM_RXF_64B },
3133 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3134 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3135 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3136 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3137 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3138 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3139 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3140 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3141 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3142 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3143
3144 { "tx_64_byte_packets", GM_TXF_64B },
3145 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3146 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3147 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3148 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3149 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3150 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3151 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3152};
3153
cd28ab6a
SH		 3154static u32 sky2_get_rx_csum(struct net_device *dev)
3155{
3156 struct sky2_port *sky2 = netdev_priv(dev);
3157
3158 return sky2->rx_csum;
3159}
3160
3161static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3162{
3163 struct sky2_port *sky2 = netdev_priv(dev);
3164
3165 sky2->rx_csum = data;
793b883e 3166
cd28ab6a
SH		 3167 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3168 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3169
3170 return 0;
3171}
3172
3173static u32 sky2_get_msglevel(struct net_device *netdev)
3174{
3175 struct sky2_port *sky2 = netdev_priv(netdev);
3176 return sky2->msg_enable;
3177}
3178
9a7ae0a9
SH		 3179static int sky2_nway_reset(struct net_device *dev)
3180{
3181 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3182
16ad91e1 3183 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3184 return -EINVAL;
3185
1b537565 3186 sky2_phy_reinit(sky2);
d1b139c0 3187 sky2_set_multicast(dev);
9a7ae0a9
SH		 3188
3189 return 0;
3190}
3191
793b883e 3192static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3193{
3194 struct sky2_hw *hw = sky2->hw;
3195 unsigned port = sky2->port;
3196 int i;
3197
3198 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3199 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3200 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3201 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3202
793b883e 3203 for (i = 2; i < count; i++)
cd28ab6a
SH		 3204 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3205}
3206
cd28ab6a
SH		 3207static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3208{
3209 struct sky2_port *sky2 = netdev_priv(netdev);
3210 sky2->msg_enable = value;
3211}
3212
b9f2c044 3213static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3214{
b9f2c044
JG		 3215 switch (sset) {
3216 case ETH_SS_STATS:
3217 return ARRAY_SIZE(sky2_stats);
3218 default:
3219 return -EOPNOTSUPP;
3220 }
cd28ab6a
SH		 3221}
3222
3223static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3224 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3225{
3226 struct sky2_port *sky2 = netdev_priv(dev);
3227
793b883e 3228 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3229}
3230
793b883e 3231static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3232{
3233 int i;
3234
3235 switch (stringset) {
3236 case ETH_SS_STATS:
3237 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3238 memcpy(data + i * ETH_GSTRING_LEN,
3239 sky2_stats[i].name, ETH_GSTRING_LEN);
3240 break;
3241 }
3242}
3243
cd28ab6a
SH		 3244static int sky2_set_mac_address(struct net_device *dev, void *p)
3245{
3246 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3247 struct sky2_hw *hw = sky2->hw;
3248 unsigned port = sky2->port;
3249 const struct sockaddr *addr = p;
cd28ab6a
SH		 3250
3251 if (!is_valid_ether_addr(addr->sa_data))
3252 return -EADDRNOTAVAIL;
3253
cd28ab6a 3254 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3255 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3256 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3257 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3258 dev->dev_addr, ETH_ALEN);
1b537565 3259
a8ab1ec0
SH		 3260 /* virtual address for data */
3261 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3262
3263 /* physical address: used for pause frames */
3264 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3265
3266 return 0;
cd28ab6a
SH		 3267}
3268
a052b52f
SH		 3269static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3270{
3271 u32 bit;
3272
3273 bit = ether_crc(ETH_ALEN, addr) & 63;
3274 filter[bit >> 3] |= 1 << (bit & 7);
3275}
3276
cd28ab6a
SH		 3277static void sky2_set_multicast(struct net_device *dev)
3278{
3279 struct sky2_port *sky2 = netdev_priv(dev);
3280 struct sky2_hw *hw = sky2->hw;
3281 unsigned port = sky2->port;
3282 struct dev_mc_list *list = dev->mc_list;
3283 u16 reg;
3284 u8 filter[8];
a052b52f
SH		 3285 int rx_pause;
3286 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3287
a052b52f 3288 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3289 memset(filter, 0, sizeof(filter));
3290
3291 reg = gma_read16(hw, port, GM_RX_CTRL);
3292 reg |= GM_RXCR_UCF_ENA;
3293
d571b694 3294 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3295 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3296 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3297 memset(filter, 0xff, sizeof(filter));
a052b52f 3298 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3299 reg &= ~GM_RXCR_MCF_ENA;
3300 else {
3301 int i;
3302 reg |= GM_RXCR_MCF_ENA;
3303
a052b52f
SH		 3304 if (rx_pause)
3305 sky2_add_filter(filter, pause_mc_addr);
3306
3307 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3308 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3309 }
3310
cd28ab6a 3311 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3312 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3313 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3314 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3315 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3316 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3317 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3318 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3319
3320 gma_write16(hw, port, GM_RX_CTRL, reg);
3321}
3322
3323/* Can have one global because blinking is controlled by
3324 * ethtool and that is always under RTNL mutex
3325 */
a84d0a3d 3326static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3327{
a84d0a3d
SH		 3328 struct sky2_hw *hw = sky2->hw;
3329 unsigned port = sky2->port;
793b883e 3330
a84d0a3d
SH		 3331 spin_lock_bh(&sky2->phy_lock);
3332 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3333 hw->chip_id == CHIP_ID_YUKON_EX ||
3334 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3335 u16 pg;
793b883e
SH		 3336 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3337 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3338
a84d0a3d
SH		 3339 switch (mode) {
3340 case MO_LED_OFF:
3341 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3342 PHY_M_LEDC_LOS_CTRL(8) |
3343 PHY_M_LEDC_INIT_CTRL(8) |
3344 PHY_M_LEDC_STA1_CTRL(8) |
3345 PHY_M_LEDC_STA0_CTRL(8));
3346 break;
3347 case MO_LED_ON:
3348 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3349 PHY_M_LEDC_LOS_CTRL(9) |
3350 PHY_M_LEDC_INIT_CTRL(9) |
3351 PHY_M_LEDC_STA1_CTRL(9) |
3352 PHY_M_LEDC_STA0_CTRL(9));
3353 break;
3354 case MO_LED_BLINK:
3355 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3356 PHY_M_LEDC_LOS_CTRL(0xa) |
3357 PHY_M_LEDC_INIT_CTRL(0xa) |
3358 PHY_M_LEDC_STA1_CTRL(0xa) |
3359 PHY_M_LEDC_STA0_CTRL(0xa));
3360 break;
3361 case MO_LED_NORM:
3362 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3363 PHY_M_LEDC_LOS_CTRL(1) |
3364 PHY_M_LEDC_INIT_CTRL(8) |
3365 PHY_M_LEDC_STA1_CTRL(7) |
3366 PHY_M_LEDC_STA0_CTRL(7));
3367 }
793b883e 3368
a84d0a3d
SH		 3369 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3370 } else
0efdf262 3371 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3372 PHY_M_LED_MO_DUP(mode) |
3373 PHY_M_LED_MO_10(mode) |
3374 PHY_M_LED_MO_100(mode) |
3375 PHY_M_LED_MO_1000(mode) |
3376 PHY_M_LED_MO_RX(mode) |
3377 PHY_M_LED_MO_TX(mode));
3378
3379 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3380}
3381
3382/* blink LED's for finding board */
3383static int sky2_phys_id(struct net_device *dev, u32 data)
3384{
3385 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3386 unsigned int i;
cd28ab6a 3387
a84d0a3d
SH		 3388 if (data == 0)
3389 data = UINT_MAX;
cd28ab6a 3390
a84d0a3d
SH		 3391 for (i = 0; i < data; i++) {
3392 sky2_led(sky2, MO_LED_ON);
3393 if (msleep_interruptible(500))
3394 break;
3395 sky2_led(sky2, MO_LED_OFF);
3396 if (msleep_interruptible(500))
3397 break;
793b883e 3398 }
a84d0a3d 3399 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3400
3401 return 0;
3402}
3403
3404static void sky2_get_pauseparam(struct net_device *dev,
3405 struct ethtool_pauseparam *ecmd)
3406{
3407 struct sky2_port *sky2 = netdev_priv(dev);
3408
16ad91e1
SH		 3409 switch (sky2->flow_mode) {
3410 case FC_NONE:
3411 ecmd->tx_pause = ecmd->rx_pause = 0;
3412 break;
3413 case FC_TX:
3414 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3415 break;
3416 case FC_RX:
3417 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3418 break;
3419 case FC_BOTH:
3420 ecmd->tx_pause = ecmd->rx_pause = 1;
3421 }
3422
cd28ab6a
SH		 3423 ecmd->autoneg = sky2->autoneg;
3424}
3425
3426static int sky2_set_pauseparam(struct net_device *dev,
3427 struct ethtool_pauseparam *ecmd)
3428{
3429 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3430
3431 sky2->autoneg = ecmd->autoneg;
16ad91e1 3432 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3433
16ad91e1
SH		 3434 if (netif_running(dev))
3435 sky2_phy_reinit(sky2);
cd28ab6a 3436
2eaba1a2 3437 return 0;
cd28ab6a
SH		 3438}
3439
fb17358f
SH		 3440static int sky2_get_coalesce(struct net_device *dev,
3441 struct ethtool_coalesce *ecmd)
3442{
3443 struct sky2_port *sky2 = netdev_priv(dev);
3444 struct sky2_hw *hw = sky2->hw;
3445
3446 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3447 ecmd->tx_coalesce_usecs = 0;
3448 else {
3449 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3450 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3451 }
3452 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3453
3454 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3455 ecmd->rx_coalesce_usecs = 0;
3456 else {
3457 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3458 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3459 }
3460 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3461
3462 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3463 ecmd->rx_coalesce_usecs_irq = 0;
3464 else {
3465 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3466 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3467 }
3468
3469 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3470
3471 return 0;
3472}
3473
3474/* Note: this affect both ports */
3475static int sky2_set_coalesce(struct net_device *dev,
3476 struct ethtool_coalesce *ecmd)
3477{
3478 struct sky2_port *sky2 = netdev_priv(dev);
3479 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3480 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3481
77b3d6a2
SH		 3482 if (ecmd->tx_coalesce_usecs > tmax ||
3483 ecmd->rx_coalesce_usecs > tmax ||
3484 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3485 return -EINVAL;
3486
ff81fbbe 3487 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3488 return -EINVAL;
ff81fbbe 3489 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3490 return -EINVAL;
ff81fbbe 3491 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3492 return -EINVAL;
3493
3494 if (ecmd->tx_coalesce_usecs == 0)
3495 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3496 else {
3497 sky2_write32(hw, STAT_TX_TIMER_INI,
3498 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3499 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3500 }
3501 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3502
3503 if (ecmd->rx_coalesce_usecs == 0)
3504 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3505 else {
3506 sky2_write32(hw, STAT_LEV_TIMER_INI,
3507 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3508 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3509 }
3510 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3511
3512 if (ecmd->rx_coalesce_usecs_irq == 0)
3513 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3514 else {
d28d4870 3515 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3516 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3517 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3518 }
3519 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3520 return 0;
3521}
3522
793b883e
SH		 3523static void sky2_get_ringparam(struct net_device *dev,
3524 struct ethtool_ringparam *ering)
3525{
3526 struct sky2_port *sky2 = netdev_priv(dev);
3527
3528 ering->rx_max_pending = RX_MAX_PENDING;
3529 ering->rx_mini_max_pending = 0;
3530 ering->rx_jumbo_max_pending = 0;
3531 ering->tx_max_pending = TX_RING_SIZE - 1;
3532
3533 ering->rx_pending = sky2->rx_pending;
3534 ering->rx_mini_pending = 0;
3535 ering->rx_jumbo_pending = 0;
3536 ering->tx_pending = sky2->tx_pending;
3537}
3538
3539static int sky2_set_ringparam(struct net_device *dev,
3540 struct ethtool_ringparam *ering)
3541{
3542 struct sky2_port *sky2 = netdev_priv(dev);
3543 int err = 0;
3544
3545 if (ering->rx_pending > RX_MAX_PENDING ||
3546 ering->rx_pending < 8 ||
3547 ering->tx_pending < MAX_SKB_TX_LE ||
3548 ering->tx_pending > TX_RING_SIZE - 1)
3549 return -EINVAL;
3550
3551 if (netif_running(dev))
3552 sky2_down(dev);
3553
3554 sky2->rx_pending = ering->rx_pending;
3555 sky2->tx_pending = ering->tx_pending;
3556
1b537565 3557 if (netif_running(dev)) {
793b883e 3558 err = sky2_up(dev);
1b537565
SH		 3559 if (err)
3560 dev_close(dev);
3561 }
793b883e
SH		 3562
3563 return err;
3564}
3565
793b883e
SH		 3566static int sky2_get_regs_len(struct net_device *dev)
3567{
6e4cbb34 3568 return 0x4000;
793b883e
SH		 3569}
3570
3571/*
3572 * Returns copy of control register region
3ead5db7 3573 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3574 */
3575static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3576 void *p)
3577{
3578 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3579 const void __iomem *io = sky2->hw->regs;
295b54c4 3580 unsigned int b;
793b883e
SH		 3581
3582 regs->version = 1;
793b883e 3583
295b54c4
SH		 3584 for (b = 0; b < 128; b++) {
3585 /* This complicated switch statement is to make sure and
3586 * only access regions that are unreserved.
3587 * Some blocks are only valid on dual port cards.
3588 * and block 3 has some special diagnostic registers that
3589 * are poison.
3590 */
3591 switch (b) {
3592 case 3:
3593 /* skip diagnostic ram region */
3594 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3595 break;
3ead5db7 3596
295b54c4
SH		 3597 /* dual port cards only */
3598 case 5: /* Tx Arbiter 2 */
3599 case 9: /* RX2 */
3600 case 14 ... 15: /* TX2 */
3601 case 17: case 19: /* Ram Buffer 2 */
3602 case 22 ... 23: /* Tx Ram Buffer 2 */
3603 case 25: /* Rx MAC Fifo 1 */
3604 case 27: /* Tx MAC Fifo 2 */
3605 case 31: /* GPHY 2 */
3606 case 40 ... 47: /* Pattern Ram 2 */
3607 case 52: case 54: /* TCP Segmentation 2 */
3608 case 112 ... 116: /* GMAC 2 */
3609 if (sky2->hw->ports == 1)
3610 goto reserved;
3611 /* fall through */
3612 case 0: /* Control */
3613 case 2: /* Mac address */
3614 case 4: /* Tx Arbiter 1 */
3615 case 7: /* PCI express reg */
3616 case 8: /* RX1 */
3617 case 12 ... 13: /* TX1 */
3618 case 16: case 18:/* Rx Ram Buffer 1 */
3619 case 20 ... 21: /* Tx Ram Buffer 1 */
3620 case 24: /* Rx MAC Fifo 1 */
3621 case 26: /* Tx MAC Fifo 1 */
3622 case 28 ... 29: /* Descriptor and status unit */
3623 case 30: /* GPHY 1*/
3624 case 32 ... 39: /* Pattern Ram 1 */
3625 case 48: case 50: /* TCP Segmentation 1 */
3626 case 56 ... 60: /* PCI space */
3627 case 80 ... 84: /* GMAC 1 */
3628 memcpy_fromio(p, io, 128);
3629 break;
3630 default:
3631reserved:
3632 memset(p, 0, 128);
3633 }
3ead5db7 3634
295b54c4
SH		 3635 p += 128;
3636 io += 128;
3637 }
793b883e 3638}
cd28ab6a 3639
b628ed98
SH		 3640/* In order to do Jumbo packets on these chips, need to turn off the
3641 * transmit store/forward. Therefore checksum offload won't work.
3642 */
3643static int no_tx_offload(struct net_device *dev)
3644{
3645 const struct sky2_port *sky2 = netdev_priv(dev);
3646 const struct sky2_hw *hw = sky2->hw;
3647
69161611 3648 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3649}
3650
3651static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3652{
3653 if (data && no_tx_offload(dev))
3654 return -EINVAL;
3655
3656 return ethtool_op_set_tx_csum(dev, data);
3657}
3658
3659
3660static int sky2_set_tso(struct net_device *dev, u32 data)
3661{
3662 if (data && no_tx_offload(dev))
3663 return -EINVAL;
3664
3665 return ethtool_op_set_tso(dev, data);
3666}
3667
f4331a6d
SH		 3668static int sky2_get_eeprom_len(struct net_device *dev)
3669{
3670 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3671 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3672 u16 reg2;
3673
b32f40c4 3674 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3675 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3676}
3677
b32f40c4 3678static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3679{
167f53d0 3680 u32 val;
f4331a6d 3681
b32f40c4 3682 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3683
3684 do {
b32f40c4 3685 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3686 } while (!(offset & PCI_VPD_ADDR_F));
3687
b32f40c4 3688 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3689 return val;
f4331a6d
SH		 3690}
3691
b32f40c4 3692static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3693{
b32f40c4
SH		 3694 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3695 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3696 do {
b32f40c4 3697 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3698 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3699}
3700
3701static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3702 u8 *data)
3703{
3704 struct sky2_port *sky2 = netdev_priv(dev);
3705 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3706 int length = eeprom->len;
3707 u16 offset = eeprom->offset;
3708
3709 if (!cap)
3710 return -EINVAL;
3711
3712 eeprom->magic = SKY2_EEPROM_MAGIC;
3713
3714 while (length > 0) {
b32f40c4 3715 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3716 int n = min_t(int, length, sizeof(val));
3717
3718 memcpy(data, &val, n);
3719 length -= n;
3720 data += n;
3721 offset += n;
3722 }
3723 return 0;
3724}
3725
3726static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3727 u8 *data)
3728{
3729 struct sky2_port *sky2 = netdev_priv(dev);
3730 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3731 int length = eeprom->len;
3732 u16 offset = eeprom->offset;
3733
3734 if (!cap)
3735 return -EINVAL;
3736
3737 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3738 return -EINVAL;
3739
3740 while (length > 0) {
3741 u32 val;
3742 int n = min_t(int, length, sizeof(val));
3743
3744 if (n < sizeof(val))
b32f40c4 3745 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3746 memcpy(&val, data, n);
3747
b32f40c4 3748 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3749
3750 length -= n;
3751 data += n;
3752 offset += n;
3753 }
3754 return 0;
3755}
3756
3757
7282d491 3758static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3759 .get_settings = sky2_get_settings,
3760 .set_settings = sky2_set_settings,
3761 .get_drvinfo = sky2_get_drvinfo,
3762 .get_wol = sky2_get_wol,
3763 .set_wol = sky2_set_wol,
3764 .get_msglevel = sky2_get_msglevel,
3765 .set_msglevel = sky2_set_msglevel,
3766 .nway_reset = sky2_nway_reset,
3767 .get_regs_len = sky2_get_regs_len,
3768 .get_regs = sky2_get_regs,
3769 .get_link = ethtool_op_get_link,
3770 .get_eeprom_len = sky2_get_eeprom_len,
3771 .get_eeprom = sky2_get_eeprom,
3772 .set_eeprom = sky2_set_eeprom,
f4331a6d 3773 .set_sg = ethtool_op_set_sg,
f4331a6d 3774 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3775 .set_tso = sky2_set_tso,
3776 .get_rx_csum = sky2_get_rx_csum,
3777 .set_rx_csum = sky2_set_rx_csum,
3778 .get_strings = sky2_get_strings,
3779 .get_coalesce = sky2_get_coalesce,
3780 .set_coalesce = sky2_set_coalesce,
3781 .get_ringparam = sky2_get_ringparam,
3782 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3783 .get_pauseparam = sky2_get_pauseparam,
3784 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3785 .phys_id = sky2_phys_id,
b9f2c044 3786 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3787 .get_ethtool_stats = sky2_get_ethtool_stats,
3788};
3789
3cf26753
SH		 3790#ifdef CONFIG_SKY2_DEBUG
3791
3792static struct dentry *sky2_debug;
3793
3794static int sky2_debug_show(struct seq_file *seq, void *v)
3795{
3796 struct net_device *dev = seq->private;
3797 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3798 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3799 unsigned port = sky2->port;
3800 unsigned idx, last;
3801 int sop;
3802
3803 if (!netif_running(dev))
3804 return -ENETDOWN;
3805
3806 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3807 sky2_read32(hw, B0_ISRC),
3808 sky2_read32(hw, B0_IMSK),
3809 sky2_read32(hw, B0_Y2_SP_ICR));
3810
bea3348e 3811 napi_disable(&hw->napi);
3cf26753
SH		 3812 last = sky2_read16(hw, STAT_PUT_IDX);
3813
3814 if (hw->st_idx == last)
3815 seq_puts(seq, "Status ring (empty)\n");
3816 else {
3817 seq_puts(seq, "Status ring\n");
3818 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3819 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3820 const struct sky2_status_le *le = hw->st_le + idx;
3821 seq_printf(seq, "[%d] %#x %d %#x\n",
3822 idx, le->opcode, le->length, le->status);
3823 }
3824 seq_puts(seq, "\n");
3825 }
3826
3827 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3828 sky2->tx_cons, sky2->tx_prod,
3829 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3830 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3831
3832 /* Dump contents of tx ring */
3833 sop = 1;
3834 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3835 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3836 const struct sky2_tx_le *le = sky2->tx_le + idx;
3837 u32 a = le32_to_cpu(le->addr);
3838
3839 if (sop)
3840 seq_printf(seq, "%u:", idx);
3841 sop = 0;
3842
3843 switch(le->opcode & ~HW_OWNER) {
3844 case OP_ADDR64:
3845 seq_printf(seq, " %#x:", a);
3846 break;
3847 case OP_LRGLEN:
3848 seq_printf(seq, " mtu=%d", a);
3849 break;
3850 case OP_VLAN:
3851 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3852 break;
3853 case OP_TCPLISW:
3854 seq_printf(seq, " csum=%#x", a);
3855 break;
3856 case OP_LARGESEND:
3857 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3858 break;
3859 case OP_PACKET:
3860 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3861 break;
3862 case OP_BUFFER:
3863 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3864 break;
3865 default:
3866 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3867 a, le16_to_cpu(le->length));
3868 }
3869
3870 if (le->ctrl & EOP) {
3871 seq_putc(seq, '\n');
3872 sop = 1;
3873 }
3874 }
3875
3876 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3877 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3878 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3879 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3880
d1d08d12 3881 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 3882 napi_enable(&hw->napi);
3cf26753
SH		 3883 return 0;
3884}
3885
3886static int sky2_debug_open(struct inode *inode, struct file *file)
3887{
3888 return single_open(file, sky2_debug_show, inode->i_private);
3889}
3890
3891static const struct file_operations sky2_debug_fops = {
3892 .owner = THIS_MODULE,
3893 .open = sky2_debug_open,
3894 .read = seq_read,
3895 .llseek = seq_lseek,
3896 .release = single_release,
3897};
3898
3899/*
3900 * Use network device events to create/remove/rename
3901 * debugfs file entries
3902 */
3903static int sky2_device_event(struct notifier_block *unused,
3904 unsigned long event, void *ptr)
3905{
3906 struct net_device *dev = ptr;
5b296bc9 3907 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3908
5b296bc9
SH		 3909 if (dev->open != sky2_up || !sky2_debug)
3910 return NOTIFY_DONE;
3cf26753 3911
5b296bc9
SH		 3912 switch(event) {
3913 case NETDEV_CHANGENAME:
3914 if (sky2->debugfs) {
3915 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3916 sky2_debug, dev->name);
3917 }
3918 break;
3cf26753 3919
5b296bc9
SH		 3920 case NETDEV_GOING_DOWN:
3921 if (sky2->debugfs) {
3922 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3923 dev->name);
3924 debugfs_remove(sky2->debugfs);
3925 sky2->debugfs = NULL;
3cf26753 3926 }
5b296bc9
SH		 3927 break;
3928
3929 case NETDEV_UP:
3930 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3931 sky2_debug, dev,
3932 &sky2_debug_fops);
3933 if (IS_ERR(sky2->debugfs))
3934 sky2->debugfs = NULL;
3cf26753
SH		 3935 }
3936
3937 return NOTIFY_DONE;
3938}
3939
3940static struct notifier_block sky2_notifier = {
3941 .notifier_call = sky2_device_event,
3942};
3943
3944
3945static __init void sky2_debug_init(void)
3946{
3947 struct dentry *ent;
3948
3949 ent = debugfs_create_dir("sky2", NULL);
3950 if (!ent || IS_ERR(ent))
3951 return;
3952
3953 sky2_debug = ent;
3954 register_netdevice_notifier(&sky2_notifier);
3955}
3956
3957static __exit void sky2_debug_cleanup(void)
3958{
3959 if (sky2_debug) {
3960 unregister_netdevice_notifier(&sky2_notifier);
3961 debugfs_remove(sky2_debug);
3962 sky2_debug = NULL;
3963 }
3964}
3965
3966#else
3967#define sky2_debug_init()
3968#define sky2_debug_cleanup()
3969#endif
3970
3971
cd28ab6a
SH		 3972/* Initialize network device */
3973static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 3974 unsigned port,
be63a21c 3975 int highmem, int wol)
cd28ab6a
SH		 3976{
3977 struct sky2_port *sky2;
3978 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3979
3980 if (!dev) {
898eb71c 3981 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 3982 return NULL;
3983 }
3984
cd28ab6a 3985 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3986 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3987 dev->open = sky2_up;
3988 dev->stop = sky2_down;
ef743d33 3989 dev->do_ioctl = sky2_ioctl;
cd28ab6a 3990 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 3991 dev->set_multicast_list = sky2_set_multicast;
3992 dev->set_mac_address = sky2_set_mac_address;
3993 dev->change_mtu = sky2_change_mtu;
3994 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3995 dev->tx_timeout = sky2_tx_timeout;
3996 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 3997#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 3998 if (port == 0)
3999 dev->poll_controller = sky2_netpoll;
cd28ab6a 4000#endif
cd28ab6a
SH		 4001
4002 sky2 = netdev_priv(dev);
4003 sky2->netdev = dev;
4004 sky2->hw = hw;
4005 sky2->msg_enable = netif_msg_init(debug, default_msg);
4006
cd28ab6a
SH		 4007 /* Auto speed and flow control */
4008 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4009 sky2->flow_mode = FC_BOTH;
4010
cd28ab6a
SH		 4011 sky2->duplex = -1;
4012 sky2->speed = -1;
4013 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4014 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4015 sky2->wol = wol;
75d070c5 4016
e07b1aa8 4017 spin_lock_init(&sky2->phy_lock);
793b883e 4018 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4019 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4020
4021 hw->dev[port] = dev;
4022
4023 sky2->port = port;
4024
4a50a876 4025 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4026 if (highmem)
4027 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4028
d1f13708 4029#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4030 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4031 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4032 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4033 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4034 dev->vlan_rx_register = sky2_vlan_rx_register;
4035 }
d1f13708 4036#endif
4037
cd28ab6a 4038 /* read the mac address */
793b883e 4039 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4040 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4041
cd28ab6a
SH		 4042 return dev;
4043}
4044
28bd181a 4045static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4046{
4047 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4048 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4049
4050 if (netif_msg_probe(sky2))
0795af57
JP		 4051 printk(KERN_INFO PFX "%s: addr %s\n",
4052 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4053}
4054
fb2690a9 4055/* Handle software interrupt used during MSI test */
7d12e780 4056static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4057{
4058 struct sky2_hw *hw = dev_id;
4059 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4060
4061 if (status == 0)
4062 return IRQ_NONE;
4063
4064 if (status & Y2_IS_IRQ_SW) {
ea76e635 4065 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4066 wake_up(&hw->msi_wait);
4067 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4068 }
4069 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4070
4071 return IRQ_HANDLED;
4072}
4073
4074/* Test interrupt path by forcing a a software IRQ */
4075static int __devinit sky2_test_msi(struct sky2_hw *hw)
4076{
4077 struct pci_dev *pdev = hw->pdev;
4078 int err;
4079
bb507fe1 4080 init_waitqueue_head (&hw->msi_wait);
4081
fb2690a9
SH		 4082 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4083
b0a20ded 4084 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4085 if (err) {
b02a9258 4086 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4087 return err;
4088 }
4089
fb2690a9 4090 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4091 sky2_read8(hw, B0_CTST);
fb2690a9 4092
ea76e635 4093 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4094
ea76e635 4095 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4096 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4097 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4098 "switching to INTx mode.\n");
fb2690a9
SH		 4099
4100 err = -EOPNOTSUPP;
4101 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4102 }
4103
4104 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4105 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4106
4107 free_irq(pdev->irq, hw);
4108
4109 return err;
4110}
4111
be63a21c
SH		 4112static int __devinit pci_wake_enabled(struct pci_dev *dev)
4113{
4114 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4115 u16 value;
4116
4117 if (!pm)
4118 return 0;
4119 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4120 return 0;
4121 return value & PCI_PM_CTRL_PME_ENABLE;
4122}
4123
cd28ab6a
SH		 4124static int __devinit sky2_probe(struct pci_dev *pdev,
4125 const struct pci_device_id *ent)
4126{
7f60c64b 4127 struct net_device *dev;
cd28ab6a 4128 struct sky2_hw *hw;
be63a21c 4129 int err, using_dac = 0, wol_default;
cd28ab6a 4130
793b883e
SH		 4131 err = pci_enable_device(pdev);
4132 if (err) {
b02a9258 4133 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4134 goto err_out;
4135 }
4136
793b883e
SH		 4137 err = pci_request_regions(pdev, DRV_NAME);
4138 if (err) {
b02a9258 4139 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4140 goto err_out_disable;
cd28ab6a
SH		 4141 }
4142
4143 pci_set_master(pdev);
4144
d1f3d4dd
SH		 4145 if (sizeof(dma_addr_t) > sizeof(u32) &&
4146 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4147 using_dac = 1;
4148 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4149 if (err < 0) {
b02a9258
SH		 4150 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4151 "for consistent allocations\n");
d1f3d4dd
SH		 4152 goto err_out_free_regions;
4153 }
d1f3d4dd 4154 } else {
cd28ab6a
SH		 4155 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4156 if (err) {
b02a9258 4157 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4158 goto err_out_free_regions;
4159 }
4160 }
d1f3d4dd 4161
be63a21c
SH		 4162 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4163
cd28ab6a 4164 err = -ENOMEM;
6aad85d6 4165 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4166 if (!hw) {
b02a9258 4167 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4168 goto err_out_free_regions;
4169 }
4170
cd28ab6a 4171 hw->pdev = pdev;
cd28ab6a
SH		 4172
4173 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4174 if (!hw->regs) {
b02a9258 4175 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4176 goto err_out_free_hw;
4177 }
4178
56a645cc 4179#ifdef __BIG_ENDIAN
f65b138c
SH		 4180 /* The sk98lin vendor driver uses hardware byte swapping but
4181 * this driver uses software swapping.
4182 */
56a645cc
SH		 4183 {
4184 u32 reg;
b32f40c4 4185 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4186 reg &= ~PCI_REV_DESC;
b32f40c4 4187 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4188 }
4189#endif
4190
08c06d8a 4191 /* ring for status responses */
167f53d0 4192 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4193 if (!hw->st_le)
4194 goto err_out_iounmap;
4195
e3173832 4196 err = sky2_init(hw);
cd28ab6a 4197 if (err)
793b883e 4198 goto err_out_iounmap;
cd28ab6a 4199
b02a9258 4200 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4201 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4202 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4203 hw->chip_id, hw->chip_rev);
cd28ab6a 4204
e3173832
SH		 4205 sky2_reset(hw);
4206
be63a21c 4207 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4208 if (!dev) {
4209 err = -ENOMEM;
cd28ab6a 4210 goto err_out_free_pci;
7f60c64b 4211 }
cd28ab6a 4212
9fa1b1f3
SH		 4213 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4214 err = sky2_test_msi(hw);
4215 if (err == -EOPNOTSUPP)
4216 pci_disable_msi(pdev);
4217 else if (err)
4218 goto err_out_free_netdev;
4219 }
4220
793b883e
SH		 4221 err = register_netdev(dev);
4222 if (err) {
b02a9258 4223 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4224 goto err_out_free_netdev;
4225 }
4226
6de16237
SH		 4227 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4228
ea76e635
SH		 4229 err = request_irq(pdev->irq, sky2_intr,
4230 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4231 dev->name, hw);
9fa1b1f3 4232 if (err) {
b02a9258 4233 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4234 goto err_out_unregister;
4235 }
4236 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4237 napi_enable(&hw->napi);
9fa1b1f3 4238
cd28ab6a
SH		 4239 sky2_show_addr(dev);
4240
7f60c64b 4241 if (hw->ports > 1) {
4242 struct net_device *dev1;
4243
be63a21c 4244 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4245 if (!dev1)
4246 dev_warn(&pdev->dev, "allocation for second device failed\n");
4247 else if ((err = register_netdev(dev1))) {
4248 dev_warn(&pdev->dev,
4249 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4250 hw->dev[1] = NULL;
4251 free_netdev(dev1);
b02a9258
SH		 4252 } else
4253 sky2_show_addr(dev1);
cd28ab6a
SH		 4254 }
4255
32c2c300 4256 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4257 INIT_WORK(&hw->restart_work, sky2_restart);
4258
793b883e
SH		 4259 pci_set_drvdata(pdev, hw);
4260
cd28ab6a
SH		 4261 return 0;
4262
793b883e 4263err_out_unregister:
ea76e635 4264 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4265 pci_disable_msi(pdev);
793b883e 4266 unregister_netdev(dev);
cd28ab6a
SH		 4267err_out_free_netdev:
4268 free_netdev(dev);
cd28ab6a 4269err_out_free_pci:
793b883e 4270 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4271 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4272err_out_iounmap:
4273 iounmap(hw->regs);
4274err_out_free_hw:
4275 kfree(hw);
4276err_out_free_regions:
4277 pci_release_regions(pdev);
44a1d2e5 4278err_out_disable:
cd28ab6a 4279 pci_disable_device(pdev);
cd28ab6a 4280err_out:
549a68c3 4281 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4282 return err;
4283}
4284
4285static void __devexit sky2_remove(struct pci_dev *pdev)
4286{
793b883e 4287 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4288 int i;
cd28ab6a 4289
793b883e 4290 if (!hw)
cd28ab6a
SH		 4291 return;
4292
32c2c300 4293 del_timer_sync(&hw->watchdog_timer);
6de16237 4294 cancel_work_sync(&hw->restart_work);
d27ed387 4295
b877fe28 4296 for (i = hw->ports-1; i >= 0; --i)
6de16237 4297 unregister_netdev(hw->dev[i]);
81906791 4298
d27ed387 4299 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4300
ae306cca
SH		 4301 sky2_power_aux(hw);
4302
cd28ab6a 4303 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4304 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4305 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4306
4307 free_irq(pdev->irq, hw);
ea76e635 4308 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4309 pci_disable_msi(pdev);
793b883e 4310 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4311 pci_release_regions(pdev);
4312 pci_disable_device(pdev);
793b883e 4313
b877fe28 4314 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4315 free_netdev(hw->dev[i]);
4316
cd28ab6a
SH		 4317 iounmap(hw->regs);
4318 kfree(hw);
5afa0a9c 4319
cd28ab6a
SH		 4320 pci_set_drvdata(pdev, NULL);
4321}
4322
4323#ifdef CONFIG_PM
4324static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4325{
793b883e 4326 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4327 int i, wol = 0;
cd28ab6a 4328
549a68c3
SH		 4329 if (!hw)
4330 return 0;
4331
f05267e7 4332 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4333 struct net_device *dev = hw->dev[i];
e3173832 4334 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4335
e3173832 4336 if (netif_running(dev))
5afa0a9c 4337 sky2_down(dev);
e3173832
SH		 4338
4339 if (sky2->wol)
4340 sky2_wol_init(sky2);
4341
4342 wol |= sky2->wol;
cd28ab6a
SH		 4343 }
4344
8ab8fca2 4345 sky2_write32(hw, B0_IMSK, 0);
6de16237 4346 napi_disable(&hw->napi);
ae306cca 4347 sky2_power_aux(hw);
e3173832 4348
d374c1c1 4349 pci_save_state(pdev);
e3173832 4350 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4351 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4352
2ccc99b7 4353 return 0;
cd28ab6a
SH		 4354}
4355
4356static int sky2_resume(struct pci_dev *pdev)
4357{
793b883e 4358 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4359 int i, err;
cd28ab6a 4360
549a68c3
SH		 4361 if (!hw)
4362 return 0;
4363
ae306cca
SH		 4364 err = pci_set_power_state(pdev, PCI_D0);
4365 if (err)
4366 goto out;
4367
4368 err = pci_restore_state(pdev);
4369 if (err)
4370 goto out;
4371
cd28ab6a 4372 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4373
4374 /* Re-enable all clocks */
05745c4a
SH		 4375 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4376 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4377 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4378 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4379
e3173832 4380 sky2_reset(hw);
8ab8fca2 4381 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4382 napi_enable(&hw->napi);
8ab8fca2 4383
f05267e7 4384 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4385 struct net_device *dev = hw->dev[i];
6a5706b9 4386 if (netif_running(dev)) {
08c06d8a
SH		 4387 err = sky2_up(dev);
4388 if (err) {
4389 printk(KERN_ERR PFX "%s: could not up: %d\n",
4390 dev->name, err);
4391 dev_close(dev);
eb35cf60 4392 goto out;
5afa0a9c 4393 }
cd28ab6a
SH		 4394 }
4395 }
eb35cf60 4396
ae306cca 4397 return 0;
08c06d8a 4398out:
b02a9258 4399 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4400 pci_disable_device(pdev);
08c06d8a 4401 return err;
cd28ab6a
SH		 4402}
4403#endif
4404
e3173832
SH		 4405static void sky2_shutdown(struct pci_dev *pdev)
4406{
4407 struct sky2_hw *hw = pci_get_drvdata(pdev);
4408 int i, wol = 0;
4409
549a68c3
SH		 4410 if (!hw)
4411 return;
4412
5c0d6b34 4413 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4414
4415 for (i = 0; i < hw->ports; i++) {
4416 struct net_device *dev = hw->dev[i];
4417 struct sky2_port *sky2 = netdev_priv(dev);
4418
4419 if (sky2->wol) {
4420 wol = 1;
4421 sky2_wol_init(sky2);
4422 }
4423 }
4424
4425 if (wol)
4426 sky2_power_aux(hw);
4427
4428 pci_enable_wake(pdev, PCI_D3hot, wol);
4429 pci_enable_wake(pdev, PCI_D3cold, wol);
4430
4431 pci_disable_device(pdev);
4432 pci_set_power_state(pdev, PCI_D3hot);
4433
4434}
4435
cd28ab6a 4436static struct pci_driver sky2_driver = {
793b883e
SH		 4437 .name = DRV_NAME,
4438 .id_table = sky2_id_table,
4439 .probe = sky2_probe,
4440 .remove = __devexit_p(sky2_remove),
cd28ab6a 4441#ifdef CONFIG_PM
793b883e
SH		 4442 .suspend = sky2_suspend,
4443 .resume = sky2_resume,
cd28ab6a 4444#endif
e3173832 4445 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4446};
4447
4448static int __init sky2_init_module(void)
4449{
3cf26753 4450 sky2_debug_init();
50241c4c 4451 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4452}
4453
4454static void __exit sky2_cleanup_module(void)
4455{
4456 pci_unregister_driver(&sky2_driver);
3cf26753 4457 sky2_debug_cleanup();
cd28ab6a
SH		 4458}
4459
4460module_init(sky2_init_module);
4461module_exit(sky2_cleanup_module);
4462
4463MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4464MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4465MODULE_LICENSE("GPL");
5f4f9dc1 4466MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)