projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] skge: dont allow bad hardware address from ROM
[linux-2.6-block.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
14c85021 28#include <linux/in.h>
baef58b1
SH		 29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
4075400b 40#include <linux/dma-mapping.h>
2cd8e5d3 41#include <linux/mii.h>
baef58b1
SH		 42#include <asm/irq.h>
43
44#include "skge.h"
45
46#define DRV_NAME "skge"
eff4b1fe 47#define DRV_VERSION "1.5"
baef58b1
SH		 48#define PFX DRV_NAME " "
49
50#define DEFAULT_TX_RING_SIZE 128
51#define DEFAULT_RX_RING_SIZE 512
52#define MAX_TX_RING_SIZE 1024
9db96479 53#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 54#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 55#define RX_COPY_THRESHOLD 128
56#define RX_BUF_SIZE 1536
baef58b1
SH		 57#define PHY_RETRIES 1000
58#define ETH_JUMBO_MTU 9000
59#define TX_WATCHDOG (5 * HZ)
60#define NAPI_WEIGHT 64
6abebb53 61#define BLINK_MS 250
baef58b1
SH		 62
63MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
64MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
65MODULE_LICENSE("GPL");
66MODULE_VERSION(DRV_VERSION);
67
68static const u32 default_msg
69 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
70 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
71
72static int debug = -1; /* defaults above */
73module_param(debug, int, 0);
74MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
75
76static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
78 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
80 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1 81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
2d2a3871 82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86f0cd50 87 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
baef58b1
SH		 88 { 0 }
89};
90MODULE_DEVICE_TABLE(pci, skge_id_table);
91
92static int skge_up(struct net_device *dev);
93static int skge_down(struct net_device *dev);
ee294dcd 94static void skge_phy_reset(struct skge_port *skge);
baef58b1 95static void skge_tx_clean(struct skge_port *skge);
2cd8e5d3
SH		 96static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 98static void genesis_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_get_stats(struct skge_port *skge, u64 *data);
100static void yukon_init(struct skge_hw *hw, int port);
baef58b1 101static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 102static void genesis_link_up(struct skge_port *skge);
baef58b1 103
7e676d91 104/* Avoid conditionals by using array */
baef58b1
SH		 105static const int txqaddr[] = { Q_XA1, Q_XA2 };
106static const int rxqaddr[] = { Q_R1, Q_R2 };
107static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
108static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
109
baef58b1
SH		 110static int skge_get_regs_len(struct net_device *dev)
111{
c3f8be96 112 return 0x4000;
baef58b1
SH		 113}
114
115/*
c3f8be96
SH		 116 * Returns copy of whole control register region
117 * Note: skip RAM address register because accessing it will
118 * cause bus hangs!
baef58b1
SH		 119 */
120static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
121 void *p)
122{
123 const struct skge_port *skge = netdev_priv(dev);
baef58b1 124 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 125
126 regs->version = 1;
c3f8be96
SH		 127 memset(p, 0, regs->len);
128 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 129
c3f8be96
SH		 130 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
131 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 132}
133
8f3f8193 134/* Wake on Lan only supported on Yukon chips with rev 1 or above */
baef58b1
SH		 135static int wol_supported(const struct skge_hw *hw)
136{
137 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 138 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 139}
140
141static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
142{
143 struct skge_port *skge = netdev_priv(dev);
144
145 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
146 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
147}
148
149static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
150{
151 struct skge_port *skge = netdev_priv(dev);
152 struct skge_hw *hw = skge->hw;
153
95566065 154 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 155 return -EOPNOTSUPP;
156
157 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
158 return -EOPNOTSUPP;
159
160 skge->wol = wol->wolopts == WAKE_MAGIC;
161
162 if (skge->wol) {
163 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
164
165 skge_write16(hw, WOL_CTRL_STAT,
166 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
167 WOL_CTL_ENA_MAGIC_PKT_UNIT);
168 } else
169 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
170
171 return 0;
172}
173
8f3f8193
SH		 174/* Determine supported/advertised modes based on hardware.
175 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 176 */
177static u32 skge_supported_modes(const struct skge_hw *hw)
178{
179 u32 supported;
180
5e1705dd 181 if (hw->copper) {
31b619c5
SH		 182 supported = SUPPORTED_10baseT_Half
183 | SUPPORTED_10baseT_Full
184 | SUPPORTED_100baseT_Half
185 | SUPPORTED_100baseT_Full
186 | SUPPORTED_1000baseT_Half
187 | SUPPORTED_1000baseT_Full
188 | SUPPORTED_Autoneg| SUPPORTED_TP;
189
190 if (hw->chip_id == CHIP_ID_GENESIS)
191 supported &= ~(SUPPORTED_10baseT_Half
192 | SUPPORTED_10baseT_Full
193 | SUPPORTED_100baseT_Half
194 | SUPPORTED_100baseT_Full);
195
196 else if (hw->chip_id == CHIP_ID_YUKON)
197 supported &= ~SUPPORTED_1000baseT_Half;
198 } else
199 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
200 | SUPPORTED_Autoneg;
201
202 return supported;
203}
baef58b1
SH		 204
205static int skge_get_settings(struct net_device *dev,
206 struct ethtool_cmd *ecmd)
207{
208 struct skge_port *skge = netdev_priv(dev);
209 struct skge_hw *hw = skge->hw;
210
211 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 212 ecmd->supported = skge_supported_modes(hw);
baef58b1 213
5e1705dd 214 if (hw->copper) {
baef58b1
SH		 215 ecmd->port = PORT_TP;
216 ecmd->phy_address = hw->phy_addr;
31b619c5 217 } else
baef58b1 218 ecmd->port = PORT_FIBRE;
baef58b1
SH		 219
220 ecmd->advertising = skge->advertising;
221 ecmd->autoneg = skge->autoneg;
222 ecmd->speed = skge->speed;
223 ecmd->duplex = skge->duplex;
224 return 0;
225}
226
baef58b1
SH		 227static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
228{
229 struct skge_port *skge = netdev_priv(dev);
230 const struct skge_hw *hw = skge->hw;
31b619c5 231 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 232
233 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 234 ecmd->advertising = supported;
235 skge->duplex = -1;
236 skge->speed = -1;
baef58b1 237 } else {
31b619c5
SH		 238 u32 setting;
239
2c668514 240 switch (ecmd->speed) {
baef58b1 241 case SPEED_1000:
31b619c5
SH		 242 if (ecmd->duplex == DUPLEX_FULL)
243 setting = SUPPORTED_1000baseT_Full;
244 else if (ecmd->duplex == DUPLEX_HALF)
245 setting = SUPPORTED_1000baseT_Half;
246 else
247 return -EINVAL;
baef58b1
SH		 248 break;
249 case SPEED_100:
31b619c5
SH		 250 if (ecmd->duplex == DUPLEX_FULL)
251 setting = SUPPORTED_100baseT_Full;
252 else if (ecmd->duplex == DUPLEX_HALF)
253 setting = SUPPORTED_100baseT_Half;
254 else
255 return -EINVAL;
256 break;
257
baef58b1 258 case SPEED_10:
31b619c5
SH		 259 if (ecmd->duplex == DUPLEX_FULL)
260 setting = SUPPORTED_10baseT_Full;
261 else if (ecmd->duplex == DUPLEX_HALF)
262 setting = SUPPORTED_10baseT_Half;
263 else
baef58b1
SH		 264 return -EINVAL;
265 break;
266 default:
267 return -EINVAL;
268 }
31b619c5
SH		 269
270 if ((setting & supported) == 0)
271 return -EINVAL;
272
273 skge->speed = ecmd->speed;
274 skge->duplex = ecmd->duplex;
baef58b1
SH		 275 }
276
277 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 278 skge->advertising = ecmd->advertising;
279
ee294dcd
SH		 280 if (netif_running(dev))
281 skge_phy_reset(skge);
282
baef58b1
SH		 283 return (0);
284}
285
286static void skge_get_drvinfo(struct net_device *dev,
287 struct ethtool_drvinfo *info)
288{
289 struct skge_port *skge = netdev_priv(dev);
290
291 strcpy(info->driver, DRV_NAME);
292 strcpy(info->version, DRV_VERSION);
293 strcpy(info->fw_version, "N/A");
294 strcpy(info->bus_info, pci_name(skge->hw->pdev));
295}
296
297static const struct skge_stat {
298 char name[ETH_GSTRING_LEN];
299 u16 xmac_offset;
300 u16 gma_offset;
301} skge_stats[] = {
302 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
303 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
304
305 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
306 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
307 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
308 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
309 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
310 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
311 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
312 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
313
314 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
315 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
316 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
317 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
318 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
319 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
320
321 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
322 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
323 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
324 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
325 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
326};
327
328static int skge_get_stats_count(struct net_device *dev)
329{
330 return ARRAY_SIZE(skge_stats);
331}
332
333static void skge_get_ethtool_stats(struct net_device *dev,
334 struct ethtool_stats *stats, u64 *data)
335{
336 struct skge_port *skge = netdev_priv(dev);
337
338 if (skge->hw->chip_id == CHIP_ID_GENESIS)
339 genesis_get_stats(skge, data);
340 else
341 yukon_get_stats(skge, data);
342}
343
344/* Use hardware MIB variables for critical path statistics and
345 * transmit feedback not reported at interrupt.
346 * Other errors are accounted for in interrupt handler.
347 */
348static struct net_device_stats *skge_get_stats(struct net_device *dev)
349{
350 struct skge_port *skge = netdev_priv(dev);
351 u64 data[ARRAY_SIZE(skge_stats)];
352
353 if (skge->hw->chip_id == CHIP_ID_GENESIS)
354 genesis_get_stats(skge, data);
355 else
356 yukon_get_stats(skge, data);
357
358 skge->net_stats.tx_bytes = data[0];
359 skge->net_stats.rx_bytes = data[1];
360 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
361 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
4c180fc4 362 skge->net_stats.multicast = data[3] + data[5];
baef58b1
SH		 363 skge->net_stats.collisions = data[10];
364 skge->net_stats.tx_aborted_errors = data[12];
365
366 return &skge->net_stats;
367}
368
369static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
370{
371 int i;
372
95566065 373 switch (stringset) {
baef58b1
SH		 374 case ETH_SS_STATS:
375 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
376 memcpy(data + i * ETH_GSTRING_LEN,
377 skge_stats[i].name, ETH_GSTRING_LEN);
378 break;
379 }
380}
381
382static void skge_get_ring_param(struct net_device *dev,
383 struct ethtool_ringparam *p)
384{
385 struct skge_port *skge = netdev_priv(dev);
386
387 p->rx_max_pending = MAX_RX_RING_SIZE;
388 p->tx_max_pending = MAX_TX_RING_SIZE;
389 p->rx_mini_max_pending = 0;
390 p->rx_jumbo_max_pending = 0;
391
392 p->rx_pending = skge->rx_ring.count;
393 p->tx_pending = skge->tx_ring.count;
394 p->rx_mini_pending = 0;
395 p->rx_jumbo_pending = 0;
396}
397
398static int skge_set_ring_param(struct net_device *dev,
399 struct ethtool_ringparam *p)
400{
401 struct skge_port *skge = netdev_priv(dev);
3b8bb472 402 int err;
baef58b1
SH		 403
404 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 405 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 406 return -EINVAL;
407
408 skge->rx_ring.count = p->rx_pending;
409 skge->tx_ring.count = p->tx_pending;
410
411 if (netif_running(dev)) {
412 skge_down(dev);
3b8bb472
SH		 413 err = skge_up(dev);
414 if (err)
415 dev_close(dev);
baef58b1
SH		 416 }
417
418 return 0;
419}
420
421static u32 skge_get_msglevel(struct net_device *netdev)
422{
423 struct skge_port *skge = netdev_priv(netdev);
424 return skge->msg_enable;
425}
426
427static void skge_set_msglevel(struct net_device *netdev, u32 value)
428{
429 struct skge_port *skge = netdev_priv(netdev);
430 skge->msg_enable = value;
431}
432
433static int skge_nway_reset(struct net_device *dev)
434{
435 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 436
437 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
438 return -EINVAL;
439
ee294dcd 440 skge_phy_reset(skge);
baef58b1
SH		 441 return 0;
442}
443
444static int skge_set_sg(struct net_device *dev, u32 data)
445{
446 struct skge_port *skge = netdev_priv(dev);
447 struct skge_hw *hw = skge->hw;
448
449 if (hw->chip_id == CHIP_ID_GENESIS && data)
450 return -EOPNOTSUPP;
451 return ethtool_op_set_sg(dev, data);
452}
453
454static int skge_set_tx_csum(struct net_device *dev, u32 data)
455{
456 struct skge_port *skge = netdev_priv(dev);
457 struct skge_hw *hw = skge->hw;
458
459 if (hw->chip_id == CHIP_ID_GENESIS && data)
460 return -EOPNOTSUPP;
461
462 return ethtool_op_set_tx_csum(dev, data);
463}
464
465static u32 skge_get_rx_csum(struct net_device *dev)
466{
467 struct skge_port *skge = netdev_priv(dev);
468
469 return skge->rx_csum;
470}
471
472/* Only Yukon supports checksum offload. */
473static int skge_set_rx_csum(struct net_device *dev, u32 data)
474{
475 struct skge_port *skge = netdev_priv(dev);
476
477 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
478 return -EOPNOTSUPP;
479
480 skge->rx_csum = data;
481 return 0;
482}
483
baef58b1
SH		 484static void skge_get_pauseparam(struct net_device *dev,
485 struct ethtool_pauseparam *ecmd)
486{
487 struct skge_port *skge = netdev_priv(dev);
488
489 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
490 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
491 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
492 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
493
494 ecmd->autoneg = skge->autoneg;
495}
496
497static int skge_set_pauseparam(struct net_device *dev,
498 struct ethtool_pauseparam *ecmd)
499{
500 struct skge_port *skge = netdev_priv(dev);
501
502 skge->autoneg = ecmd->autoneg;
503 if (ecmd->rx_pause && ecmd->tx_pause)
504 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 505 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 506 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 507 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 508 skge->flow_control = FLOW_MODE_LOC_SEND;
509 else
510 skge->flow_control = FLOW_MODE_NONE;
511
e8df8554
SH		 512 if (netif_running(dev))
513 skge_phy_reset(skge);
baef58b1
SH		 514 return 0;
515}
516
517/* Chip internal frequency for clock calculations */
518static inline u32 hwkhz(const struct skge_hw *hw)
519{
520 if (hw->chip_id == CHIP_ID_GENESIS)
521 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 522 else
523 return 78215; /* or: 78.125 MHz */
524}
525
8f3f8193 526/* Chip HZ to microseconds */
baef58b1
SH		 527static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
528{
529 return (ticks * 1000) / hwkhz(hw);
530}
531
8f3f8193 532/* Microseconds to chip HZ */
baef58b1
SH		 533static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
534{
535 return hwkhz(hw) * usec / 1000;
536}
537
538static int skge_get_coalesce(struct net_device *dev,
539 struct ethtool_coalesce *ecmd)
540{
541 struct skge_port *skge = netdev_priv(dev);
542 struct skge_hw *hw = skge->hw;
543 int port = skge->port;
544
545 ecmd->rx_coalesce_usecs = 0;
546 ecmd->tx_coalesce_usecs = 0;
547
548 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
549 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
550 u32 msk = skge_read32(hw, B2_IRQM_MSK);
551
552 if (msk & rxirqmask[port])
553 ecmd->rx_coalesce_usecs = delay;
554 if (msk & txirqmask[port])
555 ecmd->tx_coalesce_usecs = delay;
556 }
557
558 return 0;
559}
560
561/* Note: interrupt timer is per board, but can turn on/off per port */
562static int skge_set_coalesce(struct net_device *dev,
563 struct ethtool_coalesce *ecmd)
564{
565 struct skge_port *skge = netdev_priv(dev);
566 struct skge_hw *hw = skge->hw;
567 int port = skge->port;
568 u32 msk = skge_read32(hw, B2_IRQM_MSK);
569 u32 delay = 25;
570
571 if (ecmd->rx_coalesce_usecs == 0)
572 msk &= ~rxirqmask[port];
573 else if (ecmd->rx_coalesce_usecs < 25 ||
574 ecmd->rx_coalesce_usecs > 33333)
575 return -EINVAL;
576 else {
577 msk |= rxirqmask[port];
578 delay = ecmd->rx_coalesce_usecs;
579 }
580
581 if (ecmd->tx_coalesce_usecs == 0)
582 msk &= ~txirqmask[port];
583 else if (ecmd->tx_coalesce_usecs < 25 ||
584 ecmd->tx_coalesce_usecs > 33333)
585 return -EINVAL;
586 else {
587 msk |= txirqmask[port];
588 delay = min(delay, ecmd->rx_coalesce_usecs);
589 }
590
591 skge_write32(hw, B2_IRQM_MSK, msk);
592 if (msk == 0)
593 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
594 else {
595 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
596 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
597 }
598 return 0;
599}
600
6abebb53
SH		 601enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
602static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 603{
6abebb53
SH		 604 struct skge_hw *hw = skge->hw;
605 int port = skge->port;
606
d85b514f 607 mutex_lock(&hw->phy_mutex);
baef58b1 608 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 609 switch (mode) {
610 case LED_MODE_OFF:
611 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
612 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
613 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
614 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
615 break;
baef58b1 616
6abebb53
SH		 617 case LED_MODE_ON:
618 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
619 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 620
6abebb53
SH		 621 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
622 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 623
6abebb53 624 break;
baef58b1 625
6abebb53
SH		 626 case LED_MODE_TST:
627 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
628 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
629 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 630
6abebb53
SH		 631 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
632 break;
633 }
baef58b1 634 } else {
6abebb53
SH		 635 switch (mode) {
636 case LED_MODE_OFF:
637 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
638 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
639 PHY_M_LED_MO_DUP(MO_LED_OFF) |
640 PHY_M_LED_MO_10(MO_LED_OFF) |
641 PHY_M_LED_MO_100(MO_LED_OFF) |
642 PHY_M_LED_MO_1000(MO_LED_OFF) |
643 PHY_M_LED_MO_RX(MO_LED_OFF));
644 break;
645 case LED_MODE_ON:
646 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
647 PHY_M_LED_PULS_DUR(PULS_170MS) |
648 PHY_M_LED_BLINK_RT(BLINK_84MS) |
649 PHY_M_LEDC_TX_CTRL |
650 PHY_M_LEDC_DP_CTRL);
46a60f2d 651
6abebb53
SH		 652 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
653 PHY_M_LED_MO_RX(MO_LED_OFF) |
654 (skge->speed == SPEED_100 ?
655 PHY_M_LED_MO_100(MO_LED_ON) : 0));
656 break;
657 case LED_MODE_TST:
658 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
659 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
660 PHY_M_LED_MO_DUP(MO_LED_ON) |
661 PHY_M_LED_MO_10(MO_LED_ON) |
662 PHY_M_LED_MO_100(MO_LED_ON) |
663 PHY_M_LED_MO_1000(MO_LED_ON) |
664 PHY_M_LED_MO_RX(MO_LED_ON));
665 }
baef58b1 666 }
d85b514f 667 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 668}
669
670/* blink LED's for finding board */
671static int skge_phys_id(struct net_device *dev, u32 data)
672{
673 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 674 unsigned long ms;
675 enum led_mode mode = LED_MODE_TST;
baef58b1 676
95566065 677 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 678 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
679 else
680 ms = data * 1000;
baef58b1 681
6abebb53
SH		 682 while (ms > 0) {
683 skge_led(skge, mode);
684 mode ^= LED_MODE_TST;
baef58b1 685
6abebb53
SH		 686 if (msleep_interruptible(BLINK_MS))
687 break;
688 ms -= BLINK_MS;
689 }
baef58b1 690
6abebb53
SH		 691 /* back to regular LED state */
692 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 693
694 return 0;
695}
696
697static struct ethtool_ops skge_ethtool_ops = {
698 .get_settings = skge_get_settings,
699 .set_settings = skge_set_settings,
700 .get_drvinfo = skge_get_drvinfo,
701 .get_regs_len = skge_get_regs_len,
702 .get_regs = skge_get_regs,
703 .get_wol = skge_get_wol,
704 .set_wol = skge_set_wol,
705 .get_msglevel = skge_get_msglevel,
706 .set_msglevel = skge_set_msglevel,
707 .nway_reset = skge_nway_reset,
708 .get_link = ethtool_op_get_link,
709 .get_ringparam = skge_get_ring_param,
710 .set_ringparam = skge_set_ring_param,
711 .get_pauseparam = skge_get_pauseparam,
712 .set_pauseparam = skge_set_pauseparam,
713 .get_coalesce = skge_get_coalesce,
714 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 715 .get_sg = ethtool_op_get_sg,
716 .set_sg = skge_set_sg,
717 .get_tx_csum = ethtool_op_get_tx_csum,
718 .set_tx_csum = skge_set_tx_csum,
719 .get_rx_csum = skge_get_rx_csum,
720 .set_rx_csum = skge_set_rx_csum,
721 .get_strings = skge_get_strings,
722 .phys_id = skge_phys_id,
723 .get_stats_count = skge_get_stats_count,
724 .get_ethtool_stats = skge_get_ethtool_stats,
56230d53 725 .get_perm_addr = ethtool_op_get_perm_addr,
baef58b1
SH		 726};
727
728/*
729 * Allocate ring elements and chain them together
730 * One-to-one association of board descriptors with ring elements
731 */
c3da1447 732static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 733{
734 struct skge_tx_desc *d;
735 struct skge_element *e;
736 int i;
737
ff7907ae 738 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
baef58b1
SH		 739 if (!ring->start)
740 return -ENOMEM;
741
742 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
743 e->desc = d;
744 if (i == ring->count - 1) {
745 e->next = ring->start;
746 d->next_offset = base;
747 } else {
748 e->next = e + 1;
749 d->next_offset = base + (i+1) * sizeof(*d);
750 }
751 }
752 ring->to_use = ring->to_clean = ring->start;
753
754 return 0;
755}
756
19a33d4e
SH		 757/* Allocate and setup a new buffer for receiving */
758static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
759 struct sk_buff *skb, unsigned int bufsize)
760{
761 struct skge_rx_desc *rd = e->desc;
762 u64 map;
baef58b1
SH		 763
764 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
765 PCI_DMA_FROMDEVICE);
766
767 rd->dma_lo = map;
768 rd->dma_hi = map >> 32;
769 e->skb = skb;
770 rd->csum1_start = ETH_HLEN;
771 rd->csum2_start = ETH_HLEN;
772 rd->csum1 = 0;
773 rd->csum2 = 0;
774
775 wmb();
776
777 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
778 pci_unmap_addr_set(e, mapaddr, map);
779 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 780}
781
19a33d4e
SH		 782/* Resume receiving using existing skb,
783 * Note: DMA address is not changed by chip.
784 * MTU not changed while receiver active.
785 */
5a011447 786static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 787{
788 struct skge_rx_desc *rd = e->desc;
789
790 rd->csum2 = 0;
791 rd->csum2_start = ETH_HLEN;
792
793 wmb();
794
795 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
796}
797
798
799/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 800static void skge_rx_clean(struct skge_port *skge)
801{
802 struct skge_hw *hw = skge->hw;
803 struct skge_ring *ring = &skge->rx_ring;
804 struct skge_element *e;
805
19a33d4e
SH		 806 e = ring->start;
807 do {
baef58b1
SH		 808 struct skge_rx_desc *rd = e->desc;
809 rd->control = 0;
19a33d4e
SH		 810 if (e->skb) {
811 pci_unmap_single(hw->pdev,
812 pci_unmap_addr(e, mapaddr),
813 pci_unmap_len(e, maplen),
814 PCI_DMA_FROMDEVICE);
815 dev_kfree_skb(e->skb);
816 e->skb = NULL;
817 }
818 } while ((e = e->next) != ring->start);
baef58b1
SH		 819}
820
19a33d4e 821
baef58b1 822/* Allocate buffers for receive ring
19a33d4e 823 * For receive: to_clean is next received frame.
baef58b1
SH		 824 */
825static int skge_rx_fill(struct skge_port *skge)
826{
827 struct skge_ring *ring = &skge->rx_ring;
828 struct skge_element *e;
baef58b1 829
19a33d4e
SH		 830 e = ring->start;
831 do {
383181ac 832 struct sk_buff *skb;
baef58b1 833
b5d56ddc 834 skb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_KERNEL);
19a33d4e
SH		 835 if (!skb)
836 return -ENOMEM;
837
383181ac
SH		 838 skb_reserve(skb, NET_IP_ALIGN);
839 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 840 } while ( (e = e->next) != ring->start);
baef58b1 841
19a33d4e
SH		 842 ring->to_clean = ring->start;
843 return 0;
baef58b1
SH		 844}
845
846static void skge_link_up(struct skge_port *skge)
847{
46a60f2d 848 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 849 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
850
baef58b1 851 netif_carrier_on(skge->netdev);
29b4e886 852 netif_wake_queue(skge->netdev);
baef58b1
SH		 853
854 if (netif_msg_link(skge))
855 printk(KERN_INFO PFX
856 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
857 skge->netdev->name, skge->speed,
858 skge->duplex == DUPLEX_FULL ? "full" : "half",
859 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
860 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
861 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
862 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
863 "unknown");
864}
865
866static void skge_link_down(struct skge_port *skge)
867{
54cfb5aa 868 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 869 netif_carrier_off(skge->netdev);
870 netif_stop_queue(skge->netdev);
871
872 if (netif_msg_link(skge))
873 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
874}
875
2cd8e5d3 876static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 877{
878 int i;
baef58b1 879
6b0c1480 880 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 881 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 882
89bf5f23 883 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 884 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 885 goto ready;
0781191c 886 udelay(1);
baef58b1
SH		 887 }
888
2cd8e5d3 889 return -ETIMEDOUT;
89bf5f23 890 ready:
2cd8e5d3 891 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 892
2cd8e5d3
SH		 893 return 0;
894}
895
896static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
897{
898 u16 v = 0;
899 if (__xm_phy_read(hw, port, reg, &v))
900 printk(KERN_WARNING PFX "%s: phy read timed out\n",
901 hw->dev[port]->name);
baef58b1
SH		 902 return v;
903}
904
2cd8e5d3 905static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 906{
907 int i;
908
6b0c1480 909 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 910 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 911 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 912 goto ready;
89bf5f23 913 udelay(1);
baef58b1 914 }
2cd8e5d3 915 return -EIO;
baef58b1
SH		 916
917 ready:
6b0c1480 918 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 919 for (i = 0; i < PHY_RETRIES; i++) {
920 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
921 return 0;
922 udelay(1);
923 }
924 return -ETIMEDOUT;
baef58b1
SH		 925}
926
927static void genesis_init(struct skge_hw *hw)
928{
929 /* set blink source counter */
930 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
931 skge_write8(hw, B2_BSC_CTRL, BSC_START);
932
933 /* configure mac arbiter */
934 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
935
936 /* configure mac arbiter timeout values */
937 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
938 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
939 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
940 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
941
942 skge_write8(hw, B3_MA_RCINI_RX1, 0);
943 skge_write8(hw, B3_MA_RCINI_RX2, 0);
944 skge_write8(hw, B3_MA_RCINI_TX1, 0);
945 skge_write8(hw, B3_MA_RCINI_TX2, 0);
946
947 /* configure packet arbiter timeout */
948 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
949 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
950 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
951 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
952 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
953}
954
955static void genesis_reset(struct skge_hw *hw, int port)
956{
45bada65 957 const u8 zero[8] = { 0 };
baef58b1 958
46a60f2d
SH		 959 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
960
baef58b1 961 /* reset the statistics module */
6b0c1480
SH		 962 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
963 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
964 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
965 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
966 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 967
89bf5f23
SH		 968 /* disable Broadcom PHY IRQ */
969 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 970
45bada65 971 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 972}
973
974
45bada65
SH		 975/* Convert mode to MII values */
976static const u16 phy_pause_map[] = {
977 [FLOW_MODE_NONE] = 0,
978 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
979 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
980 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
981};
982
983
984/* Check status of Broadcom phy link */
985static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 986{
45bada65
SH		 987 struct net_device *dev = hw->dev[port];
988 struct skge_port *skge = netdev_priv(dev);
989 u16 status;
990
991 /* read twice because of latch */
992 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
993 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
994
45bada65
SH		 995 if ((status & PHY_ST_LSYNC) == 0) {
996 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
997 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
998 xm_write16(hw, port, XM_MMU_CMD, cmd);
999 /* dummy read to ensure writing */
1000 (void) xm_read16(hw, port, XM_MMU_CMD);
1001
1002 if (netif_carrier_ok(dev))
1003 skge_link_down(skge);
1004 } else {
1005 if (skge->autoneg == AUTONEG_ENABLE &&
1006 (status & PHY_ST_AN_OVER)) {
1007 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1008 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1009
1010 if (lpa & PHY_B_AN_RF) {
1011 printk(KERN_NOTICE PFX "%s: remote fault\n",
1012 dev->name);
1013 return;
1014 }
1015
1016 /* Check Duplex mismatch */
2c668514 1017 switch (aux & PHY_B_AS_AN_RES_MSK) {
45bada65
SH		 1018 case PHY_B_RES_1000FD:
1019 skge->duplex = DUPLEX_FULL;
1020 break;
1021 case PHY_B_RES_1000HD:
1022 skge->duplex = DUPLEX_HALF;
1023 break;
1024 default:
1025 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1026 dev->name);
1027 return;
1028 }
1029
1030
1031 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1032 switch (aux & PHY_B_AS_PAUSE_MSK) {
1033 case PHY_B_AS_PAUSE_MSK:
1034 skge->flow_control = FLOW_MODE_SYMMETRIC;
1035 break;
1036 case PHY_B_AS_PRR:
1037 skge->flow_control = FLOW_MODE_REM_SEND;
1038 break;
1039 case PHY_B_AS_PRT:
1040 skge->flow_control = FLOW_MODE_LOC_SEND;
1041 break;
1042 default:
1043 skge->flow_control = FLOW_MODE_NONE;
1044 }
1045
1046 skge->speed = SPEED_1000;
1047 }
1048
1049 if (!netif_carrier_ok(dev))
1050 genesis_link_up(skge);
1051 }
1052}
1053
1054/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1055 * Phy on for 100 or 10Mbit operation
1056 */
1057static void bcom_phy_init(struct skge_port *skge, int jumbo)
1058{
1059 struct skge_hw *hw = skge->hw;
1060 int port = skge->port;
baef58b1 1061 int i;
45bada65 1062 u16 id1, r, ext, ctl;
baef58b1
SH		 1063
1064 /* magic workaround patterns for Broadcom */
1065 static const struct {
1066 u16 reg;
1067 u16 val;
1068 } A1hack[] = {
1069 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1070 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1071 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1072 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1073 }, C0hack[] = {
1074 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1075 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1076 };
1077
45bada65
SH		 1078 /* read Id from external PHY (all have the same address) */
1079 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1080
1081 /* Optimize MDIO transfer by suppressing preamble. */
1082 r = xm_read16(hw, port, XM_MMU_CMD);
1083 r |= XM_MMU_NO_PRE;
1084 xm_write16(hw, port, XM_MMU_CMD,r);
1085
2c668514 1086 switch (id1) {
45bada65
SH		 1087 case PHY_BCOM_ID1_C0:
1088 /*
1089 * Workaround BCOM Errata for the C0 type.
1090 * Write magic patterns to reserved registers.
1091 */
1092 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1093 xm_phy_write(hw, port,
1094 C0hack[i].reg, C0hack[i].val);
1095
1096 break;
1097 case PHY_BCOM_ID1_A1:
1098 /*
1099 * Workaround BCOM Errata for the A1 type.
1100 * Write magic patterns to reserved registers.
1101 */
1102 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1103 xm_phy_write(hw, port,
1104 A1hack[i].reg, A1hack[i].val);
1105 break;
1106 }
1107
1108 /*
1109 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1110 * Disable Power Management after reset.
1111 */
1112 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1113 r |= PHY_B_AC_DIS_PM;
1114 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1115
1116 /* Dummy read */
1117 xm_read16(hw, port, XM_ISRC);
1118
1119 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1120 ctl = PHY_CT_SP1000; /* always 1000mbit */
1121
1122 if (skge->autoneg == AUTONEG_ENABLE) {
1123 /*
1124 * Workaround BCOM Errata #1 for the C5 type.
1125 * 1000Base-T Link Acquisition Failure in Slave Mode
1126 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1127 */
1128 u16 adv = PHY_B_1000C_RD;
1129 if (skge->advertising & ADVERTISED_1000baseT_Half)
1130 adv |= PHY_B_1000C_AHD;
1131 if (skge->advertising & ADVERTISED_1000baseT_Full)
1132 adv |= PHY_B_1000C_AFD;
1133 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1134
1135 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1136 } else {
1137 if (skge->duplex == DUPLEX_FULL)
1138 ctl |= PHY_CT_DUP_MD;
1139 /* Force to slave */
1140 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1141 }
1142
1143 /* Set autonegotiation pause parameters */
1144 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1145 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1146
1147 /* Handle Jumbo frames */
1148 if (jumbo) {
1149 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1150 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1151
1152 ext |= PHY_B_PEC_HIGH_LA;
1153
1154 }
1155
1156 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1157 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1158
8f3f8193 1159 /* Use link status change interrupt */
45bada65
SH		 1160 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1161
1162 bcom_check_link(hw, port);
1163}
1164
1165static void genesis_mac_init(struct skge_hw *hw, int port)
1166{
1167 struct net_device *dev = hw->dev[port];
1168 struct skge_port *skge = netdev_priv(dev);
1169 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1170 int i;
1171 u32 r;
1172 const u8 zero[6] = { 0 };
1173
0781191c
SH		 1174 for (i = 0; i < 10; i++) {
1175 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1176 MFF_SET_MAC_RST);
1177 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1178 goto reset_ok;
1179 udelay(1);
1180 }
baef58b1 1181
0781191c
SH		 1182 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1183
1184 reset_ok:
baef58b1 1185 /* Unreset the XMAC. */
6b0c1480 1186 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1187
1188 /*
1189 * Perform additional initialization for external PHYs,
1190 * namely for the 1000baseTX cards that use the XMAC's
1191 * GMII mode.
1192 */
45bada65 1193 /* Take external Phy out of reset */
89bf5f23
SH		 1194 r = skge_read32(hw, B2_GP_IO);
1195 if (port == 0)
1196 r |= GP_DIR_0|GP_IO_0;
1197 else
1198 r |= GP_DIR_2|GP_IO_2;
1199
1200 skge_write32(hw, B2_GP_IO, r);
0781191c 1201
89bf5f23 1202
8f3f8193 1203 /* Enable GMII interface */
89bf5f23
SH		 1204 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1205
45bada65 1206 bcom_phy_init(skge, jumbo);
89bf5f23 1207
45bada65
SH		 1208 /* Set Station Address */
1209 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1210
45bada65
SH		 1211 /* We don't use match addresses so clear */
1212 for (i = 1; i < 16; i++)
1213 xm_outaddr(hw, port, XM_EXM(i), zero);
1214
0781191c
SH		 1215 /* Clear MIB counters */
1216 xm_write16(hw, port, XM_STAT_CMD,
1217 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1218 /* Clear two times according to Errata #3 */
1219 xm_write16(hw, port, XM_STAT_CMD,
1220 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1221
45bada65
SH		 1222 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1223 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1224
1225 /* We don't need the FCS appended to the packet. */
1226 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1227 if (jumbo)
1228 r |= XM_RX_BIG_PK_OK;
89bf5f23 1229
45bada65 1230 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1231 /*
45bada65
SH		 1232 * If in manual half duplex mode the other side might be in
1233 * full duplex mode, so ignore if a carrier extension is not seen
1234 * on frames received
89bf5f23 1235 */
45bada65 1236 r |= XM_RX_DIS_CEXT;
baef58b1 1237 }
45bada65 1238 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1239
baef58b1
SH		 1240
1241 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1242 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1243
1244 /*
1245 * Bump up the transmit threshold. This helps hold off transmit
1246 * underruns when we're blasting traffic from both ports at once.
1247 */
1248 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1249
1250 /*
1251 * Enable the reception of all error frames. This is is
1252 * a necessary evil due to the design of the XMAC. The
1253 * XMAC's receive FIFO is only 8K in size, however jumbo
1254 * frames can be up to 9000 bytes in length. When bad
1255 * frame filtering is enabled, the XMAC's RX FIFO operates
1256 * in 'store and forward' mode. For this to work, the
1257 * entire frame has to fit into the FIFO, but that means
1258 * that jumbo frames larger than 8192 bytes will be
1259 * truncated. Disabling all bad frame filtering causes
1260 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1261 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1262 * RX FIFO as soon as the FIFO threshold is reached.
1263 */
45bada65 1264 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1265
baef58b1
SH		 1266
1267 /*
45bada65
SH		 1268 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1269 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1270 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1271 */
45bada65
SH		 1272 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1273
1274 /*
1275 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1276 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1277 * and 'Octets Tx OK Hi Cnt Ov'.
1278 */
1279 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1280
1281 /* Configure MAC arbiter */
1282 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1283
1284 /* configure timeout values */
1285 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1286 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1287 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1288 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1289
1290 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1291 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1292 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1293 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1294
1295 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1296 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1297 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1298 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1299
1300 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1301 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1302 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1303 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1304
45bada65 1305 if (jumbo) {
baef58b1 1306 /* Enable frame flushing if jumbo frames used */
6b0c1480 1307 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1308 } else {
1309 /* enable timeout timers if normal frames */
1310 skge_write16(hw, B3_PA_CTRL,
45bada65 1311 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1312 }
baef58b1
SH		 1313}
1314
1315static void genesis_stop(struct skge_port *skge)
1316{
1317 struct skge_hw *hw = skge->hw;
1318 int port = skge->port;
89bf5f23 1319 u32 reg;
baef58b1 1320
46a60f2d
SH		 1321 genesis_reset(hw, port);
1322
baef58b1
SH		 1323 /* Clear Tx packet arbiter timeout IRQ */
1324 skge_write16(hw, B3_PA_CTRL,
1325 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1326
1327 /*
8f3f8193 1328 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1329 * terminate if we don't flush the XMAC's transmit FIFO !
1330 */
6b0c1480
SH		 1331 xm_write32(hw, port, XM_MODE,
1332 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1333
1334
1335 /* Reset the MAC */
6b0c1480 1336 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1337
1338 /* For external PHYs there must be special handling */
89bf5f23
SH		 1339 reg = skge_read32(hw, B2_GP_IO);
1340 if (port == 0) {
1341 reg |= GP_DIR_0;
1342 reg &= ~GP_IO_0;
1343 } else {
1344 reg |= GP_DIR_2;
1345 reg &= ~GP_IO_2;
baef58b1 1346 }
89bf5f23
SH		 1347 skge_write32(hw, B2_GP_IO, reg);
1348 skge_read32(hw, B2_GP_IO);
baef58b1 1349
6b0c1480
SH		 1350 xm_write16(hw, port, XM_MMU_CMD,
1351 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1352 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1353
6b0c1480 1354 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1355}
1356
1357
1358static void genesis_get_stats(struct skge_port *skge, u64 *data)
1359{
1360 struct skge_hw *hw = skge->hw;
1361 int port = skge->port;
1362 int i;
1363 unsigned long timeout = jiffies + HZ;
1364
6b0c1480 1365 xm_write16(hw, port,
baef58b1
SH		 1366 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1367
1368 /* wait for update to complete */
6b0c1480 1369 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1370 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1371 if (time_after(jiffies, timeout))
1372 break;
1373 udelay(10);
1374 }
1375
1376 /* special case for 64 bit octet counter */
6b0c1480
SH		 1377 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1378 | xm_read32(hw, port, XM_TXO_OK_LO);
1379 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1380 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1381
1382 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1383 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1384}
1385
1386static void genesis_mac_intr(struct skge_hw *hw, int port)
1387{
1388 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1389 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1390
7e676d91
SH		 1391 if (netif_msg_intr(skge))
1392 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1393 skge->netdev->name, status);
baef58b1
SH		 1394
1395 if (status & XM_IS_TXF_UR) {
6b0c1480 1396 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1397 ++skge->net_stats.tx_fifo_errors;
1398 }
1399 if (status & XM_IS_RXF_OV) {
6b0c1480 1400 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1401 ++skge->net_stats.rx_fifo_errors;
1402 }
1403}
1404
baef58b1
SH		 1405static void genesis_link_up(struct skge_port *skge)
1406{
1407 struct skge_hw *hw = skge->hw;
1408 int port = skge->port;
1409 u16 cmd;
1410 u32 mode, msk;
1411
6b0c1480 1412 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1413
1414 /*
1415 * enabling pause frame reception is required for 1000BT
1416 * because the XMAC is not reset if the link is going down
1417 */
1418 if (skge->flow_control == FLOW_MODE_NONE ||
1419 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1420 /* Disable Pause Frame Reception */
baef58b1
SH		 1421 cmd |= XM_MMU_IGN_PF;
1422 else
1423 /* Enable Pause Frame Reception */
1424 cmd &= ~XM_MMU_IGN_PF;
1425
6b0c1480 1426 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1427
6b0c1480 1428 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1429 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1430 skge->flow_control == FLOW_MODE_LOC_SEND) {
1431 /*
1432 * Configure Pause Frame Generation
1433 * Use internal and external Pause Frame Generation.
1434 * Sending pause frames is edge triggered.
1435 * Send a Pause frame with the maximum pause time if
1436 * internal oder external FIFO full condition occurs.
1437 * Send a zero pause time frame to re-start transmission.
1438 */
1439 /* XM_PAUSE_DA = '010000C28001' (default) */
1440 /* XM_MAC_PTIME = 0xffff (maximum) */
1441 /* remember this value is defined in big endian (!) */
6b0c1480 1442 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1443
1444 mode |= XM_PAUSE_MODE;
6b0c1480 1445 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1446 } else {
1447 /*
1448 * disable pause frame generation is required for 1000BT
1449 * because the XMAC is not reset if the link is going down
1450 */
1451 /* Disable Pause Mode in Mode Register */
1452 mode &= ~XM_PAUSE_MODE;
1453
6b0c1480 1454 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1455 }
1456
6b0c1480 1457 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1458
1459 msk = XM_DEF_MSK;
89bf5f23
SH		 1460 /* disable GP0 interrupt bit for external Phy */
1461 msk |= XM_IS_INP_ASS;
baef58b1 1462
6b0c1480
SH		 1463 xm_write16(hw, port, XM_IMSK, msk);
1464 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1465
1466 /* get MMU Command Reg. */
6b0c1480 1467 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1468 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1469 cmd |= XM_MMU_GMII_FD;
1470
89bf5f23
SH		 1471 /*
1472 * Workaround BCOM Errata (#10523) for all BCom Phys
1473 * Enable Power Management after link up
1474 */
1475 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1476 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1477 & ~PHY_B_AC_DIS_PM);
1478 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1479
1480 /* enable Rx/Tx */
6b0c1480 1481 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1482 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1483 skge_link_up(skge);
1484}
1485
1486
45bada65 1487static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1488{
1489 struct skge_hw *hw = skge->hw;
1490 int port = skge->port;
45bada65
SH		 1491 u16 isrc;
1492
1493 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1494 if (netif_msg_intr(skge))
1495 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1496 skge->netdev->name, isrc);
baef58b1 1497
45bada65
SH		 1498 if (isrc & PHY_B_IS_PSE)
1499 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1500 hw->dev[port]->name);
baef58b1
SH		 1501
1502 /* Workaround BCom Errata:
1503 * enable and disable loopback mode if "NO HCD" occurs.
1504 */
45bada65 1505 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1506 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1507 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1508 ctrl | PHY_CT_LOOP);
6b0c1480 1509 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1510 ctrl & ~PHY_CT_LOOP);
1511 }
1512
45bada65
SH		 1513 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1514 bcom_check_link(hw, port);
baef58b1 1515
baef58b1
SH		 1516}
1517
2cd8e5d3
SH		 1518static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1519{
1520 int i;
1521
1522 gma_write16(hw, port, GM_SMI_DATA, val);
1523 gma_write16(hw, port, GM_SMI_CTRL,
1524 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1525 for (i = 0; i < PHY_RETRIES; i++) {
1526 udelay(1);
1527
1528 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1529 return 0;
1530 }
1531
1532 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1533 hw->dev[port]->name);
1534 return -EIO;
1535}
1536
1537static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1538{
1539 int i;
1540
1541 gma_write16(hw, port, GM_SMI_CTRL,
1542 GM_SMI_CT_PHY_AD(hw->phy_addr)
1543 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1544
1545 for (i = 0; i < PHY_RETRIES; i++) {
1546 udelay(1);
1547 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1548 goto ready;
1549 }
1550
1551 return -ETIMEDOUT;
1552 ready:
1553 *val = gma_read16(hw, port, GM_SMI_DATA);
1554 return 0;
1555}
1556
1557static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1558{
1559 u16 v = 0;
1560 if (__gm_phy_read(hw, port, reg, &v))
1561 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1562 hw->dev[port]->name);
1563 return v;
1564}
1565
8f3f8193 1566/* Marvell Phy Initialization */
baef58b1
SH		 1567static void yukon_init(struct skge_hw *hw, int port)
1568{
1569 struct skge_port *skge = netdev_priv(hw->dev[port]);
1570 u16 ctrl, ct1000, adv;
baef58b1 1571
baef58b1 1572 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1573 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1574
1575 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1576 PHY_M_EC_MAC_S_MSK);
1577 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1578
c506a509 1579 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1580
6b0c1480 1581 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1582 }
1583
6b0c1480 1584 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1585 if (skge->autoneg == AUTONEG_DISABLE)
1586 ctrl &= ~PHY_CT_ANE;
1587
1588 ctrl |= PHY_CT_RESET;
6b0c1480 1589 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1590
1591 ctrl = 0;
1592 ct1000 = 0;
b18f2091 1593 adv = PHY_AN_CSMA;
baef58b1
SH		 1594
1595 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1596 if (hw->copper) {
baef58b1
SH		 1597 if (skge->advertising & ADVERTISED_1000baseT_Full)
1598 ct1000 |= PHY_M_1000C_AFD;
1599 if (skge->advertising & ADVERTISED_1000baseT_Half)
1600 ct1000 |= PHY_M_1000C_AHD;
1601 if (skge->advertising & ADVERTISED_100baseT_Full)
1602 adv |= PHY_M_AN_100_FD;
1603 if (skge->advertising & ADVERTISED_100baseT_Half)
1604 adv |= PHY_M_AN_100_HD;
1605 if (skge->advertising & ADVERTISED_10baseT_Full)
1606 adv |= PHY_M_AN_10_FD;
1607 if (skge->advertising & ADVERTISED_10baseT_Half)
1608 adv |= PHY_M_AN_10_HD;
45bada65 1609 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1610 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1611
45bada65
SH		 1612 /* Set Flow-control capabilities */
1613 adv |= phy_pause_map[skge->flow_control];
1614
baef58b1
SH		 1615 /* Restart Auto-negotiation */
1616 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1617 } else {
1618 /* forced speed/duplex settings */
1619 ct1000 = PHY_M_1000C_MSE;
1620
1621 if (skge->duplex == DUPLEX_FULL)
1622 ctrl |= PHY_CT_DUP_MD;
1623
1624 switch (skge->speed) {
1625 case SPEED_1000:
1626 ctrl |= PHY_CT_SP1000;
1627 break;
1628 case SPEED_100:
1629 ctrl |= PHY_CT_SP100;
1630 break;
1631 }
1632
1633 ctrl |= PHY_CT_RESET;
1634 }
1635
c506a509 1636 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1637
6b0c1480
SH		 1638 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1639 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1640
baef58b1
SH		 1641 /* Enable phy interrupt on autonegotiation complete (or link up) */
1642 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1643 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1644 else
4cde06ed 1645 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1646}
1647
1648static void yukon_reset(struct skge_hw *hw, int port)
1649{
6b0c1480
SH		 1650 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1651 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1652 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1653 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1654 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1655
6b0c1480
SH		 1656 gma_write16(hw, port, GM_RX_CTRL,
1657 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1658 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1659}
1660
c8868611
SH		 1661/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1662static int is_yukon_lite_a0(struct skge_hw *hw)
1663{
1664 u32 reg;
1665 int ret;
1666
1667 if (hw->chip_id != CHIP_ID_YUKON)
1668 return 0;
1669
1670 reg = skge_read32(hw, B2_FAR);
1671 skge_write8(hw, B2_FAR + 3, 0xff);
1672 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1673 skge_write32(hw, B2_FAR, reg);
1674 return ret;
1675}
1676
baef58b1
SH		 1677static void yukon_mac_init(struct skge_hw *hw, int port)
1678{
1679 struct skge_port *skge = netdev_priv(hw->dev[port]);
1680 int i;
1681 u32 reg;
1682 const u8 *addr = hw->dev[port]->dev_addr;
1683
1684 /* WA code for COMA mode -- set PHY reset */
1685 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1686 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1687 reg = skge_read32(hw, B2_GP_IO);
1688 reg |= GP_DIR_9 | GP_IO_9;
1689 skge_write32(hw, B2_GP_IO, reg);
1690 }
baef58b1
SH		 1691
1692 /* hard reset */
6b0c1480
SH		 1693 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1694 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1695
1696 /* WA code for COMA mode -- clear PHY reset */
1697 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1698 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1699 reg = skge_read32(hw, B2_GP_IO);
1700 reg |= GP_DIR_9;
1701 reg &= ~GP_IO_9;
1702 skge_write32(hw, B2_GP_IO, reg);
1703 }
baef58b1
SH		 1704
1705 /* Set hardware config mode */
1706 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1707 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1708 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1709
1710 /* Clear GMC reset */
6b0c1480
SH		 1711 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1712 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1713 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 1714
baef58b1
SH		 1715 if (skge->autoneg == AUTONEG_DISABLE) {
1716 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1717 gma_write16(hw, port, GM_GP_CTRL,
1718 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1719
1720 switch (skge->speed) {
1721 case SPEED_1000:
564f9abb 1722 reg &= ~GM_GPCR_SPEED_100;
baef58b1 1723 reg |= GM_GPCR_SPEED_1000;
564f9abb 1724 break;
baef58b1 1725 case SPEED_100:
564f9abb 1726 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 1727 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 1728 break;
1729 case SPEED_10:
1730 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1731 break;
baef58b1
SH		 1732 }
1733
1734 if (skge->duplex == DUPLEX_FULL)
1735 reg |= GM_GPCR_DUP_FULL;
1736 } else
1737 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 1738
baef58b1
SH		 1739 switch (skge->flow_control) {
1740 case FLOW_MODE_NONE:
6b0c1480 1741 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1742 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1743 break;
1744 case FLOW_MODE_LOC_SEND:
1745 /* disable Rx flow-control */
1746 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1747 }
1748
6b0c1480 1749 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 1750 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1751
baef58b1 1752 yukon_init(hw, port);
baef58b1
SH		 1753
1754 /* MIB clear */
6b0c1480
SH		 1755 reg = gma_read16(hw, port, GM_PHY_ADDR);
1756 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1757
1758 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1759 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1760 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1761
1762 /* transmit control */
6b0c1480 1763 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1764
1765 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1766 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1767 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1768
1769 /* transmit flow control */
6b0c1480 1770 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1771
1772 /* transmit parameter */
6b0c1480 1773 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1774 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1775 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1776 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1777
1778 /* serial mode register */
1779 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1780 if (hw->dev[port]->mtu > 1500)
1781 reg |= GM_SMOD_JUMBO_ENA;
1782
6b0c1480 1783 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1784
1785 /* physical address: used for pause frames */
6b0c1480 1786 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1787 /* virtual address for data */
6b0c1480 1788 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1789
1790 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1791 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1792 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1793 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1794
1795 /* Initialize Mac Fifo */
1796
1797 /* Configure Rx MAC FIFO */
6b0c1480 1798 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 1799 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 1800
1801 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1802 if (is_yukon_lite_a0(hw))
baef58b1 1803 reg &= ~GMF_RX_F_FL_ON;
c8868611 1804
6b0c1480
SH		 1805 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1806 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 1807 /*
1808 * because Pause Packet Truncation in GMAC is not working
1809 * we have to increase the Flush Threshold to 64 bytes
1810 * in order to flush pause packets in Rx FIFO on Yukon-1
1811 */
1812 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 1813
1814 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1815 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1816 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1817}
1818
355ec572
SH		 1819/* Go into power down mode */
1820static void yukon_suspend(struct skge_hw *hw, int port)
1821{
1822 u16 ctrl;
1823
1824 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1825 ctrl |= PHY_M_PC_POL_R_DIS;
1826 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1827
1828 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1829 ctrl |= PHY_CT_RESET;
1830 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1831
1832 /* switch IEEE compatible power down mode on */
1833 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1834 ctrl |= PHY_CT_PDOWN;
1835 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1836}
1837
baef58b1
SH		 1838static void yukon_stop(struct skge_port *skge)
1839{
1840 struct skge_hw *hw = skge->hw;
1841 int port = skge->port;
1842
46a60f2d
SH		 1843 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1844 yukon_reset(hw, port);
baef58b1 1845
6b0c1480
SH		 1846 gma_write16(hw, port, GM_GP_CTRL,
1847 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 1848 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1849 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 1850
355ec572 1851 yukon_suspend(hw, port);
46a60f2d 1852
baef58b1 1853 /* set GPHY Control reset */
46a60f2d
SH		 1854 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1855 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1856}
1857
1858static void yukon_get_stats(struct skge_port *skge, u64 *data)
1859{
1860 struct skge_hw *hw = skge->hw;
1861 int port = skge->port;
1862 int i;
1863
6b0c1480
SH		 1864 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1865 | gma_read32(hw, port, GM_TXO_OK_LO);
1866 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1867 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1868
1869 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1870 data[i] = gma_read32(hw, port,
baef58b1
SH		 1871 skge_stats[i].gma_offset);
1872}
1873
1874static void yukon_mac_intr(struct skge_hw *hw, int port)
1875{
7e676d91
SH		 1876 struct net_device *dev = hw->dev[port];
1877 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1878 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1879
7e676d91
SH		 1880 if (netif_msg_intr(skge))
1881 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1882 dev->name, status);
1883
baef58b1
SH		 1884 if (status & GM_IS_RX_FF_OR) {
1885 ++skge->net_stats.rx_fifo_errors;
d8a09943 1886 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 1887 }
d8a09943 1888
baef58b1
SH		 1889 if (status & GM_IS_TX_FF_UR) {
1890 ++skge->net_stats.tx_fifo_errors;
d8a09943 1891 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 1892 }
1893
1894}
1895
1896static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1897{
95566065 1898 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1899 case PHY_M_PS_SPEED_1000:
1900 return SPEED_1000;
1901 case PHY_M_PS_SPEED_100:
1902 return SPEED_100;
1903 default:
1904 return SPEED_10;
1905 }
1906}
1907
1908static void yukon_link_up(struct skge_port *skge)
1909{
1910 struct skge_hw *hw = skge->hw;
1911 int port = skge->port;
1912 u16 reg;
1913
baef58b1 1914 /* Enable Transmit FIFO Underrun */
46a60f2d 1915 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 1916
6b0c1480 1917 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1918 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1919 reg |= GM_GPCR_DUP_FULL;
1920
1921 /* enable Rx/Tx */
1922 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1923 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1924
4cde06ed 1925 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1926 skge_link_up(skge);
1927}
1928
1929static void yukon_link_down(struct skge_port *skge)
1930{
1931 struct skge_hw *hw = skge->hw;
1932 int port = skge->port;
d8a09943 1933 u16 ctrl;
baef58b1 1934
6b0c1480 1935 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
d8a09943
SH		 1936
1937 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1938 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1939 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 1940
c506a509 1941 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1942 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1943 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1944 gm_phy_read(hw, port,
baef58b1
SH		 1945 PHY_MARV_AUNE_ADV)
1946 | PHY_M_AN_ASP);
1947
1948 }
1949
1950 yukon_reset(hw, port);
1951 skge_link_down(skge);
1952
1953 yukon_init(hw, port);
1954}
1955
1956static void yukon_phy_intr(struct skge_port *skge)
1957{
1958 struct skge_hw *hw = skge->hw;
1959 int port = skge->port;
1960 const char *reason = NULL;
1961 u16 istatus, phystat;
1962
6b0c1480
SH		 1963 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1964 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 1965
1966 if (netif_msg_intr(skge))
1967 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1968 skge->netdev->name, istatus, phystat);
baef58b1
SH		 1969
1970 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1971 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1972 & PHY_M_AN_RF) {
1973 reason = "remote fault";
1974 goto failed;
1975 }
1976
c506a509 1977 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1978 reason = "master/slave fault";
1979 goto failed;
1980 }
1981
1982 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1983 reason = "speed/duplex";
1984 goto failed;
1985 }
1986
1987 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1988 ? DUPLEX_FULL : DUPLEX_HALF;
1989 skge->speed = yukon_speed(hw, phystat);
1990
baef58b1
SH		 1991 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1992 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1993 case PHY_M_PS_PAUSE_MSK:
1994 skge->flow_control = FLOW_MODE_SYMMETRIC;
1995 break;
1996 case PHY_M_PS_RX_P_EN:
1997 skge->flow_control = FLOW_MODE_REM_SEND;
1998 break;
1999 case PHY_M_PS_TX_P_EN:
2000 skge->flow_control = FLOW_MODE_LOC_SEND;
2001 break;
2002 default:
2003 skge->flow_control = FLOW_MODE_NONE;
2004 }
2005
2006 if (skge->flow_control == FLOW_MODE_NONE ||
2007 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2008 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2009 else
6b0c1480 2010 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2011 yukon_link_up(skge);
2012 return;
2013 }
2014
2015 if (istatus & PHY_M_IS_LSP_CHANGE)
2016 skge->speed = yukon_speed(hw, phystat);
2017
2018 if (istatus & PHY_M_IS_DUP_CHANGE)
2019 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2020 if (istatus & PHY_M_IS_LST_CHANGE) {
2021 if (phystat & PHY_M_PS_LINK_UP)
2022 yukon_link_up(skge);
2023 else
2024 yukon_link_down(skge);
2025 }
2026 return;
2027 failed:
2028 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2029 skge->netdev->name, reason);
2030
2031 /* XXX restart autonegotiation? */
2032}
2033
ee294dcd
SH		 2034static void skge_phy_reset(struct skge_port *skge)
2035{
2036 struct skge_hw *hw = skge->hw;
2037 int port = skge->port;
2038
2039 netif_stop_queue(skge->netdev);
2040 netif_carrier_off(skge->netdev);
2041
d85b514f 2042 mutex_lock(&hw->phy_mutex);
ee294dcd
SH		 2043 if (hw->chip_id == CHIP_ID_GENESIS) {
2044 genesis_reset(hw, port);
2045 genesis_mac_init(hw, port);
2046 } else {
2047 yukon_reset(hw, port);
2048 yukon_init(hw, port);
2049 }
d85b514f 2050 mutex_unlock(&hw->phy_mutex);
ee294dcd
SH		 2051}
2052
2cd8e5d3
SH		 2053/* Basic MII support */
2054static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2055{
2056 struct mii_ioctl_data *data = if_mii(ifr);
2057 struct skge_port *skge = netdev_priv(dev);
2058 struct skge_hw *hw = skge->hw;
2059 int err = -EOPNOTSUPP;
2060
2061 if (!netif_running(dev))
2062 return -ENODEV; /* Phy still in reset */
2063
2064 switch(cmd) {
2065 case SIOCGMIIPHY:
2066 data->phy_id = hw->phy_addr;
2067
2068 /* fallthru */
2069 case SIOCGMIIREG: {
2070 u16 val = 0;
d85b514f 2071 mutex_lock(&hw->phy_mutex);
2cd8e5d3
SH		 2072 if (hw->chip_id == CHIP_ID_GENESIS)
2073 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2074 else
2075 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
d85b514f 2076 mutex_unlock(&hw->phy_mutex);
2cd8e5d3
SH		 2077 data->val_out = val;
2078 break;
2079 }
2080
2081 case SIOCSMIIREG:
2082 if (!capable(CAP_NET_ADMIN))
2083 return -EPERM;
2084
d85b514f 2085 mutex_lock(&hw->phy_mutex);
2cd8e5d3
SH		 2086 if (hw->chip_id == CHIP_ID_GENESIS)
2087 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2088 data->val_in);
2089 else
2090 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2091 data->val_in);
d85b514f 2092 mutex_unlock(&hw->phy_mutex);
2cd8e5d3
SH		 2093 break;
2094 }
2095 return err;
2096}
2097
baef58b1
SH		 2098static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2099{
2100 u32 end;
2101
2102 start /= 8;
2103 len /= 8;
2104 end = start + len - 1;
2105
2106 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2107 skge_write32(hw, RB_ADDR(q, RB_START), start);
2108 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2109 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2110 skge_write32(hw, RB_ADDR(q, RB_END), end);
2111
2112 if (q == Q_R1 || q == Q_R2) {
2113 /* Set thresholds on receive queue's */
2114 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2115 start + (2*len)/3);
2116 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2117 start + (len/3));
2118 } else {
2119 /* Enable store & forward on Tx queue's because
2120 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2121 */
2122 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2123 }
2124
2125 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2126}
2127
2128/* Setup Bus Memory Interface */
2129static void skge_qset(struct skge_port *skge, u16 q,
2130 const struct skge_element *e)
2131{
2132 struct skge_hw *hw = skge->hw;
2133 u32 watermark = 0x600;
2134 u64 base = skge->dma + (e->desc - skge->mem);
2135
2136 /* optimization to reduce window on 32bit/33mhz */
2137 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2138 watermark /= 2;
2139
2140 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2141 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2142 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2143 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2144}
2145
2146static int skge_up(struct net_device *dev)
2147{
2148 struct skge_port *skge = netdev_priv(dev);
2149 struct skge_hw *hw = skge->hw;
2150 int port = skge->port;
2151 u32 chunk, ram_addr;
2152 size_t rx_size, tx_size;
2153 int err;
2154
2155 if (netif_msg_ifup(skge))
2156 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2157
19a33d4e 2158 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2159 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2160 else
2161 skge->rx_buf_size = RX_BUF_SIZE;
2162
2163
baef58b1
SH		 2164 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2165 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2166 skge->mem_size = tx_size + rx_size;
2167 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2168 if (!skge->mem)
2169 return -ENOMEM;
2170
c3da1447
SH		 2171 BUG_ON(skge->dma & 7);
2172
2173 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2174 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2175 err = -EINVAL;
2176 goto free_pci_mem;
2177 }
2178
baef58b1
SH		 2179 memset(skge->mem, 0, skge->mem_size);
2180
203babb6
SH		 2181 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2182 if (err)
baef58b1
SH		 2183 goto free_pci_mem;
2184
19a33d4e
SH		 2185 err = skge_rx_fill(skge);
2186 if (err)
baef58b1
SH		 2187 goto free_rx_ring;
2188
203babb6
SH		 2189 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2190 skge->dma + rx_size);
2191 if (err)
baef58b1
SH		 2192 goto free_rx_ring;
2193
8f3f8193 2194 /* Initialize MAC */
d85b514f 2195 mutex_lock(&hw->phy_mutex);
baef58b1
SH		 2196 if (hw->chip_id == CHIP_ID_GENESIS)
2197 genesis_mac_init(hw, port);
2198 else
2199 yukon_mac_init(hw, port);
d85b514f 2200 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 2201
2202 /* Configure RAMbuffers */
981d0377 2203 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2204 ram_addr = hw->ram_offset + 2 * chunk * port;
2205
2206 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2207 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2208
2209 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2210 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2211 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2212
2213 /* Start receiver BMU */
2214 wmb();
2215 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2216 skge_led(skge, LED_MODE_ON);
baef58b1 2217
baef58b1
SH		 2218 return 0;
2219
2220 free_rx_ring:
2221 skge_rx_clean(skge);
2222 kfree(skge->rx_ring.start);
2223 free_pci_mem:
2224 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2225 skge->mem = NULL;
baef58b1
SH		 2226
2227 return err;
2228}
2229
2230static int skge_down(struct net_device *dev)
2231{
2232 struct skge_port *skge = netdev_priv(dev);
2233 struct skge_hw *hw = skge->hw;
2234 int port = skge->port;
2235
7731a4ea
SH		 2236 if (skge->mem == NULL)
2237 return 0;
2238
baef58b1
SH		 2239 if (netif_msg_ifdown(skge))
2240 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2241
2242 netif_stop_queue(dev);
2243
46a60f2d
SH		 2244 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2245 if (hw->chip_id == CHIP_ID_GENESIS)
2246 genesis_stop(skge);
2247 else
2248 yukon_stop(skge);
2249
baef58b1
SH		 2250 /* Stop transmitter */
2251 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2252 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2253 RB_RST_SET|RB_DIS_OP_MD);
2254
baef58b1
SH		 2255
2256 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2257 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2258 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2259
2260 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2261 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2262 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2263
2264 /* Reset PCI FIFO */
2265 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2266 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2267
2268 /* Reset the RAM Buffer async Tx queue */
2269 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2270 /* stop receiver */
2271 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2272 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2273 RB_RST_SET|RB_DIS_OP_MD);
2274 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2275
2276 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2277 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2278 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2279 } else {
6b0c1480
SH		 2280 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2281 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2282 }
2283
6abebb53 2284 skge_led(skge, LED_MODE_OFF);
baef58b1
SH		 2285
2286 skge_tx_clean(skge);
2287 skge_rx_clean(skge);
2288
2289 kfree(skge->rx_ring.start);
2290 kfree(skge->tx_ring.start);
2291 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2292 skge->mem = NULL;
baef58b1
SH		 2293 return 0;
2294}
2295
29b4e886
SH		 2296static inline int skge_avail(const struct skge_ring *ring)
2297{
2298 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2299 + (ring->to_clean - ring->to_use) - 1;
2300}
2301
baef58b1
SH		 2302static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2303{
2304 struct skge_port *skge = netdev_priv(dev);
2305 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2306 struct skge_element *e;
2307 struct skge_tx_desc *td;
2308 int i;
2309 u32 control, len;
2310 u64 map;
7c442fa1 2311 unsigned long flags;
baef58b1
SH		 2312
2313 skb = skb_padto(skb, ETH_ZLEN);
2314 if (!skb)
2315 return NETDEV_TX_OK;
2316
7c442fa1 2317 if (!spin_trylock_irqsave(&skge->tx_lock, flags))
203babb6
SH		 2318 /* Collision - tell upper layer to requeue */
2319 return NETDEV_TX_LOCKED;
baef58b1 2320
29b4e886 2321 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) {
98684a9d 2322 if (!netif_queue_stopped(dev)) {
ee1c8191 2323 netif_stop_queue(dev);
baef58b1 2324
ee1c8191
SH		 2325 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2326 dev->name);
2327 }
7c442fa1 2328 spin_unlock_irqrestore(&skge->tx_lock, flags);
baef58b1
SH		 2329 return NETDEV_TX_BUSY;
2330 }
2331
7c442fa1 2332 e = skge->tx_ring.to_use;
baef58b1 2333 td = e->desc;
7c442fa1 2334 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2335 e->skb = skb;
2336 len = skb_headlen(skb);
2337 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2338 pci_unmap_addr_set(e, mapaddr, map);
2339 pci_unmap_len_set(e, maplen, len);
2340
2341 td->dma_lo = map;
2342 td->dma_hi = map >> 32;
2343
2344 if (skb->ip_summed == CHECKSUM_HW) {
baef58b1
SH		 2345 int offset = skb->h.raw - skb->data;
2346
2347 /* This seems backwards, but it is what the sk98lin
2348 * does. Looks like hardware is wrong?
2349 */
ea182d4a 2350 if (skb->h.ipiph->protocol == IPPROTO_UDP
981d0377 2351 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2352 control = BMU_TCP_CHECK;
2353 else
2354 control = BMU_UDP_CHECK;
2355
2356 td->csum_offs = 0;
2357 td->csum_start = offset;
2358 td->csum_write = offset + skb->csum;
2359 } else
2360 control = BMU_CHECK;
2361
2362 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2363 control |= BMU_EOF| BMU_IRQ_EOF;
2364 else {
2365 struct skge_tx_desc *tf = td;
2366
2367 control |= BMU_STFWD;
2368 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2369 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2370
2371 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2372 frag->size, PCI_DMA_TODEVICE);
2373
2374 e = e->next;
7c442fa1 2375 e->skb = skb;
baef58b1 2376 tf = e->desc;
7c442fa1
SH		 2377 BUG_ON(tf->control & BMU_OWN);
2378
baef58b1
SH		 2379 tf->dma_lo = map;
2380 tf->dma_hi = (u64) map >> 32;
2381 pci_unmap_addr_set(e, mapaddr, map);
2382 pci_unmap_len_set(e, maplen, frag->size);
2383
2384 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2385 }
2386 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2387 }
2388 /* Make sure all the descriptors written */
2389 wmb();
2390 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2391 wmb();
2392
2393 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2394
7c442fa1 2395 if (unlikely(netif_msg_tx_queued(skge)))
0b2d7fea 2396 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
7c442fa1 2397 dev->name, e - skge->tx_ring.start, skb->len);
baef58b1 2398
7c442fa1 2399 skge->tx_ring.to_use = e->next;
9db96479 2400 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
baef58b1
SH		 2401 pr_debug("%s: transmit queue full\n", dev->name);
2402 netif_stop_queue(dev);
2403 }
2404
7c442fa1 2405 spin_unlock_irqrestore(&skge->tx_lock, flags);
baef58b1 2406
c68ce71a
SH		 2407 dev->trans_start = jiffies;
2408
baef58b1
SH		 2409 return NETDEV_TX_OK;
2410}
2411
7c442fa1
SH		 2412
2413/* Free resources associated with this reing element */
2414static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2415 u32 control)
866b4f3e
SH		 2416{
2417 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2418
7c442fa1 2419 BUG_ON(!e->skb);
866b4f3e 2420
7c442fa1
SH		 2421 /* skb header vs. fragment */
2422 if (control & BMU_STF)
866b4f3e 2423 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
7c442fa1
SH		 2424 pci_unmap_len(e, maplen),
2425 PCI_DMA_TODEVICE);
2426 else
2427 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2428 pci_unmap_len(e, maplen),
2429 PCI_DMA_TODEVICE);
866b4f3e 2430
7c442fa1
SH		 2431 if (control & BMU_EOF) {
2432 if (unlikely(netif_msg_tx_done(skge)))
2433 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2434 skge->netdev->name, e - skge->tx_ring.start);
866b4f3e 2435
7c442fa1 2436 dev_kfree_skb_any(e->skb);
baef58b1 2437 }
7c442fa1 2438 e->skb = NULL;
baef58b1
SH		 2439}
2440
7c442fa1 2441/* Free all buffers in transmit ring */
baef58b1
SH		 2442static void skge_tx_clean(struct skge_port *skge)
2443{
7c442fa1
SH		 2444 struct skge_element *e;
2445 unsigned long flags;
baef58b1 2446
7c442fa1
SH		 2447 spin_lock_irqsave(&skge->tx_lock, flags);
2448 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2449 struct skge_tx_desc *td = e->desc;
2450 skge_tx_free(skge, e, td->control);
2451 td->control = 0;
2452 }
2453
2454 skge->tx_ring.to_clean = e;
866b4f3e 2455 netif_wake_queue(skge->netdev);
7c442fa1 2456 spin_unlock_irqrestore(&skge->tx_lock, flags);
baef58b1
SH		 2457}
2458
2459static void skge_tx_timeout(struct net_device *dev)
2460{
2461 struct skge_port *skge = netdev_priv(dev);
2462
2463 if (netif_msg_timer(skge))
2464 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2465
2466 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2467 skge_tx_clean(skge);
2468}
2469
2470static int skge_change_mtu(struct net_device *dev, int new_mtu)
2471{
7731a4ea 2472 int err;
baef58b1 2473
95566065 2474 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2475 return -EINVAL;
2476
7731a4ea
SH		 2477 if (!netif_running(dev)) {
2478 dev->mtu = new_mtu;
2479 return 0;
2480 }
2481
2482 skge_down(dev);
baef58b1 2483
19a33d4e 2484 dev->mtu = new_mtu;
7731a4ea
SH		 2485
2486 err = skge_up(dev);
2487 if (err)
2488 dev_close(dev);
baef58b1
SH		 2489
2490 return err;
2491}
2492
2493static void genesis_set_multicast(struct net_device *dev)
2494{
2495 struct skge_port *skge = netdev_priv(dev);
2496 struct skge_hw *hw = skge->hw;
2497 int port = skge->port;
2498 int i, count = dev->mc_count;
2499 struct dev_mc_list *list = dev->mc_list;
2500 u32 mode;
2501 u8 filter[8];
2502
6b0c1480 2503 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2504 mode |= XM_MD_ENA_HASH;
2505 if (dev->flags & IFF_PROMISC)
2506 mode |= XM_MD_ENA_PROM;
2507 else
2508 mode &= ~XM_MD_ENA_PROM;
2509
2510 if (dev->flags & IFF_ALLMULTI)
2511 memset(filter, 0xff, sizeof(filter));
2512 else {
2513 memset(filter, 0, sizeof(filter));
95566065 2514 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2515 u32 crc, bit;
2516 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2517 bit = ~crc & 0x3f;
baef58b1
SH		 2518 filter[bit/8] |= 1 << (bit%8);
2519 }
2520 }
2521
6b0c1480 2522 xm_write32(hw, port, XM_MODE, mode);
45bada65 2523 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2524}
2525
2526static void yukon_set_multicast(struct net_device *dev)
2527{
2528 struct skge_port *skge = netdev_priv(dev);
2529 struct skge_hw *hw = skge->hw;
2530 int port = skge->port;
2531 struct dev_mc_list *list = dev->mc_list;
2532 u16 reg;
2533 u8 filter[8];
2534
2535 memset(filter, 0, sizeof(filter));
2536
6b0c1480 2537 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2538 reg |= GM_RXCR_UCF_ENA;
2539
8f3f8193 2540 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2541 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2542 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2543 memset(filter, 0xff, sizeof(filter));
2544 else if (dev->mc_count == 0) /* no multicast */
2545 reg &= ~GM_RXCR_MCF_ENA;
2546 else {
2547 int i;
2548 reg |= GM_RXCR_MCF_ENA;
2549
95566065 2550 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2551 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2552 filter[bit/8] |= 1 << (bit%8);
2553 }
2554 }
2555
2556
6b0c1480 2557 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2558 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2559 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2560 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2561 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2562 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2563 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2564 (u16)filter[6] | ((u16)filter[7] << 8));
2565
6b0c1480 2566 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2567}
2568
383181ac
SH		 2569static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2570{
2571 if (hw->chip_id == CHIP_ID_GENESIS)
2572 return status >> XMR_FS_LEN_SHIFT;
2573 else
2574 return status >> GMR_FS_LEN_SHIFT;
2575}
2576
baef58b1
SH		 2577static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2578{
2579 if (hw->chip_id == CHIP_ID_GENESIS)
2580 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2581 else
2582 return (status & GMR_FS_ANY_ERR) ||
2583 (status & GMR_FS_RX_OK) == 0;
2584}
2585
19a33d4e
SH		 2586
2587/* Get receive buffer from descriptor.
2588 * Handles copy of small buffers and reallocation failures
2589 */
2590static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2591 struct skge_element *e,
383181ac 2592 u32 control, u32 status, u16 csum)
19a33d4e 2593{
383181ac
SH		 2594 struct sk_buff *skb;
2595 u16 len = control & BMU_BBC;
2596
2597 if (unlikely(netif_msg_rx_status(skge)))
2598 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2599 skge->netdev->name, e - skge->rx_ring.start,
2600 status, len);
2601
2602 if (len > skge->rx_buf_size)
2603 goto error;
2604
2605 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2606 goto error;
2607
2608 if (bad_phy_status(skge->hw, status))
2609 goto error;
2610
2611 if (phy_length(skge->hw, status) != len)
2612 goto error;
19a33d4e
SH		 2613
2614 if (len < RX_COPY_THRESHOLD) {
b5d56ddc 2615 skb = alloc_skb(len + 2, GFP_ATOMIC);
383181ac
SH		 2616 if (!skb)
2617 goto resubmit;
19a33d4e 2618
383181ac 2619 skb_reserve(skb, 2);
19a33d4e
SH		 2620 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2621 pci_unmap_addr(e, mapaddr),
2622 len, PCI_DMA_FROMDEVICE);
383181ac 2623 memcpy(skb->data, e->skb->data, len);
19a33d4e
SH		 2624 pci_dma_sync_single_for_device(skge->hw->pdev,
2625 pci_unmap_addr(e, mapaddr),
2626 len, PCI_DMA_FROMDEVICE);
19a33d4e 2627 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 2628 } else {
383181ac 2629 struct sk_buff *nskb;
b5d56ddc 2630 nskb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_ATOMIC);
383181ac
SH		 2631 if (!nskb)
2632 goto resubmit;
19a33d4e 2633
901ccefb 2634 skb_reserve(nskb, NET_IP_ALIGN);
19a33d4e
SH		 2635 pci_unmap_single(skge->hw->pdev,
2636 pci_unmap_addr(e, mapaddr),
2637 pci_unmap_len(e, maplen),
2638 PCI_DMA_FROMDEVICE);
2639 skb = e->skb;
383181ac 2640 prefetch(skb->data);
19a33d4e 2641 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 2642 }
383181ac
SH		 2643
2644 skb_put(skb, len);
2645 skb->dev = skge->netdev;
2646 if (skge->rx_csum) {
2647 skb->csum = csum;
2648 skb->ip_summed = CHECKSUM_HW;
2649 }
2650
2651 skb->protocol = eth_type_trans(skb, skge->netdev);
2652
2653 return skb;
2654error:
2655
2656 if (netif_msg_rx_err(skge))
2657 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2658 skge->netdev->name, e - skge->rx_ring.start,
2659 control, status);
2660
2661 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2662 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2663 skge->net_stats.rx_length_errors++;
2664 if (status & XMR_FS_FRA_ERR)
2665 skge->net_stats.rx_frame_errors++;
2666 if (status & XMR_FS_FCS_ERR)
2667 skge->net_stats.rx_crc_errors++;
2668 } else {
2669 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2670 skge->net_stats.rx_length_errors++;
2671 if (status & GMR_FS_FRAGMENT)
2672 skge->net_stats.rx_frame_errors++;
2673 if (status & GMR_FS_CRC_ERR)
2674 skge->net_stats.rx_crc_errors++;
2675 }
2676
2677resubmit:
2678 skge_rx_reuse(e, skge->rx_buf_size);
2679 return NULL;
baef58b1
SH		 2680}
2681
7c442fa1
SH		 2682/* Free all buffers in Tx ring which are no longer owned by device */
2683static void skge_txirq(struct net_device *dev)
00a6cae2 2684{
7c442fa1 2685 struct skge_port *skge = netdev_priv(dev);
00a6cae2 2686 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 2687 struct skge_element *e;
2688
2689 rmb();
00a6cae2
SH		 2690
2691 spin_lock(&skge->tx_lock);
866b4f3e 2692 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
00a6cae2 2693 struct skge_tx_desc *td = e->desc;
00a6cae2 2694
866b4f3e 2695 if (td->control & BMU_OWN)
00a6cae2
SH		 2696 break;
2697
7c442fa1 2698 skge_tx_free(skge, e, td->control);
00a6cae2 2699 }
7c442fa1 2700 skge->tx_ring.to_clean = e;
866b4f3e 2701
7c442fa1
SH		 2702 if (netif_queue_stopped(skge->netdev)
2703 && skge_avail(&skge->tx_ring) > TX_LOW_WATER)
00a6cae2
SH		 2704 netif_wake_queue(skge->netdev);
2705
2706 spin_unlock(&skge->tx_lock);
2707}
19a33d4e 2708
baef58b1
SH		 2709static int skge_poll(struct net_device *dev, int *budget)
2710{
2711 struct skge_port *skge = netdev_priv(dev);
2712 struct skge_hw *hw = skge->hw;
2713 struct skge_ring *ring = &skge->rx_ring;
2714 struct skge_element *e;
00a6cae2
SH		 2715 int to_do = min(dev->quota, *budget);
2716 int work_done = 0;
2717
1631aef1 2718 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 2719 struct skge_rx_desc *rd = e->desc;
19a33d4e 2720 struct sk_buff *skb;
383181ac 2721 u32 control;
baef58b1
SH		 2722
2723 rmb();
2724 control = rd->control;
2725 if (control & BMU_OWN)
2726 break;
2727
20e777a2 2728 skb = skge_rx_get(skge, e, control, rd->status, rd->csum2);
19a33d4e 2729 if (likely(skb)) {
19a33d4e
SH		 2730 dev->last_rx = jiffies;
2731 netif_receive_skb(skb);
baef58b1 2732
19a33d4e 2733 ++work_done;
5a011447 2734 }
baef58b1
SH		 2735 }
2736 ring->to_clean = e;
2737
baef58b1
SH		 2738 /* restart receiver */
2739 wmb();
a9cdab86 2740 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 2741
19a33d4e
SH		 2742 *budget -= work_done;
2743 dev->quota -= work_done;
2744
2745 if (work_done >= to_do)
2746 return 1; /* not done */
baef58b1 2747
cfc3ed79 2748 netif_rx_complete(dev);
c68ce71a 2749
7c442fa1
SH		 2750 spin_lock_irq(&hw->hw_lock);
2751 hw->intr_mask |= rxirqmask[skge->port];
80dd857d 2752 skge_write32(hw, B0_IMSK, hw->intr_mask);
7c442fa1
SH		 2753 mmiowb();
2754 spin_unlock_irq(&hw->hw_lock);
1631aef1 2755
19a33d4e 2756 return 0;
baef58b1
SH		 2757}
2758
f6620cab
SH		 2759/* Parity errors seem to happen when Genesis is connected to a switch
2760 * with no other ports present. Heartbeat error??
2761 */
baef58b1
SH		 2762static void skge_mac_parity(struct skge_hw *hw, int port)
2763{
f6620cab
SH		 2764 struct net_device *dev = hw->dev[port];
2765
2766 if (dev) {
2767 struct skge_port *skge = netdev_priv(dev);
2768 ++skge->net_stats.tx_heartbeat_errors;
2769 }
baef58b1
SH		 2770
2771 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2772 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2773 MFF_CLR_PERR);
2774 else
2775 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2776 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2777 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2778 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2779}
2780
baef58b1
SH		 2781static void skge_mac_intr(struct skge_hw *hw, int port)
2782{
95566065 2783 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2784 genesis_mac_intr(hw, port);
2785 else
2786 yukon_mac_intr(hw, port);
2787}
2788
2789/* Handle device specific framing and timeout interrupts */
2790static void skge_error_irq(struct skge_hw *hw)
2791{
2792 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2793
2794 if (hw->chip_id == CHIP_ID_GENESIS) {
2795 /* clear xmac errors */
2796 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 2797 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 2798 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 2799 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 2800 } else {
2801 /* Timestamp (unused) overflow */
2802 if (hwstatus & IS_IRQ_TIST_OV)
2803 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 2804 }
2805
2806 if (hwstatus & IS_RAM_RD_PAR) {
2807 printk(KERN_ERR PFX "Ram read data parity error\n");
2808 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2809 }
2810
2811 if (hwstatus & IS_RAM_WR_PAR) {
2812 printk(KERN_ERR PFX "Ram write data parity error\n");
2813 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2814 }
2815
2816 if (hwstatus & IS_M1_PAR_ERR)
2817 skge_mac_parity(hw, 0);
2818
2819 if (hwstatus & IS_M2_PAR_ERR)
2820 skge_mac_parity(hw, 1);
2821
b9d64acc
SH		 2822 if (hwstatus & IS_R1_PAR_ERR) {
2823 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2824 hw->dev[0]->name);
baef58b1 2825 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 2826 }
baef58b1 2827
b9d64acc
SH		 2828 if (hwstatus & IS_R2_PAR_ERR) {
2829 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2830 hw->dev[1]->name);
baef58b1 2831 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 2832 }
baef58b1
SH		 2833
2834 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 2835 u16 pci_status, pci_cmd;
2836
2837 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
2838 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
baef58b1 2839
b9d64acc
SH		 2840 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
2841 pci_name(hw->pdev), pci_cmd, pci_status);
2842
2843 /* Write the error bits back to clear them. */
2844 pci_status &= PCI_STATUS_ERROR_BITS;
2845 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2846 pci_write_config_word(hw->pdev, PCI_COMMAND,
2847 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2848 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
2849 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 2850
050ec18a 2851 /* if error still set then just ignore it */
baef58b1
SH		 2852 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2853 if (hwstatus & IS_IRQ_STAT) {
b9d64acc 2854 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
baef58b1
SH		 2855 hw->intr_mask &= ~IS_HW_ERR;
2856 }
2857 }
2858}
2859
2860/*
d85b514f 2861 * Interrupt from PHY are handled in work queue
baef58b1
SH		 2862 * because accessing phy registers requires spin wait which might
2863 * cause excess interrupt latency.
2864 */
d85b514f 2865static void skge_extirq(void *arg)
baef58b1 2866{
d85b514f 2867 struct skge_hw *hw = arg;
baef58b1
SH		 2868 int port;
2869
d85b514f 2870 mutex_lock(&hw->phy_mutex);
cfc3ed79 2871 for (port = 0; port < hw->ports; port++) {
baef58b1 2872 struct net_device *dev = hw->dev[port];
cfc3ed79 2873 struct skge_port *skge = netdev_priv(dev);
baef58b1 2874
cfc3ed79 2875 if (netif_running(dev)) {
baef58b1
SH		 2876 if (hw->chip_id != CHIP_ID_GENESIS)
2877 yukon_phy_intr(skge);
89bf5f23 2878 else
45bada65 2879 bcom_phy_intr(skge);
baef58b1
SH		 2880 }
2881 }
d85b514f 2882 mutex_unlock(&hw->phy_mutex);
baef58b1 2883
7c442fa1 2884 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 2885 hw->intr_mask |= IS_EXT_REG;
2886 skge_write32(hw, B0_IMSK, hw->intr_mask);
7c442fa1 2887 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 2888}
2889
2890static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2891{
2892 struct skge_hw *hw = dev_id;
cfc3ed79 2893 u32 status;
baef58b1 2894
cfc3ed79
SH		 2895 /* Reading this register masks IRQ */
2896 status = skge_read32(hw, B0_SP_ISRC);
2897 if (status == 0)
baef58b1
SH		 2898 return IRQ_NONE;
2899
7c442fa1
SH		 2900 spin_lock(&hw->hw_lock);
2901 status &= hw->intr_mask;
cfc3ed79
SH		 2902 if (status & IS_EXT_REG) {
2903 hw->intr_mask &= ~IS_EXT_REG;
d85b514f 2904 schedule_work(&hw->phy_work);
cfc3ed79
SH		 2905 }
2906
7c442fa1
SH		 2907 if (status & IS_XA1_F) {
2908 skge_write8(hw, Q_ADDR(Q_XA1, Q_CSR), CSR_IRQ_CL_F);
2909 skge_txirq(hw->dev[0]);
baef58b1
SH		 2910 }
2911
7c442fa1
SH		 2912 if (status & IS_R1_F) {
2913 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2914 hw->intr_mask &= ~IS_R1_F;
2915 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 2916 }
2917
7c442fa1
SH		 2918 if (status & IS_PA_TO_TX1)
2919 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 2920
d25f5a67
SH		 2921 if (status & IS_PA_TO_RX1) {
2922 struct skge_port *skge = netdev_priv(hw->dev[0]);
d25f5a67 2923
d25f5a67 2924 ++skge->net_stats.rx_over_errors;
7c442fa1 2925 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 2926 }
2927
d25f5a67 2928
baef58b1
SH		 2929 if (status & IS_MAC1)
2930 skge_mac_intr(hw, 0);
95566065 2931
7c442fa1
SH		 2932 if (hw->dev[1]) {
2933 if (status & IS_XA2_F) {
2934 skge_write8(hw, Q_ADDR(Q_XA2, Q_CSR), CSR_IRQ_CL_F);
2935 skge_txirq(hw->dev[1]);
2936 }
2937
2938 if (status & IS_R2_F) {
2939 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2940 hw->intr_mask &= ~IS_R2_F;
2941 netif_rx_schedule(hw->dev[1]);
2942 }
2943
2944 if (status & IS_PA_TO_RX2) {
2945 struct skge_port *skge = netdev_priv(hw->dev[1]);
2946 ++skge->net_stats.rx_over_errors;
2947 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2948 }
2949
2950 if (status & IS_PA_TO_TX2)
2951 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2952
2953 if (status & IS_MAC2)
2954 skge_mac_intr(hw, 1);
2955 }
baef58b1
SH		 2956
2957 if (status & IS_HW_ERR)
2958 skge_error_irq(hw);
2959
7e676d91 2960 skge_write32(hw, B0_IMSK, hw->intr_mask);
7c442fa1 2961 spin_unlock(&hw->hw_lock);
baef58b1
SH		 2962
2963 return IRQ_HANDLED;
2964}
2965
2966#ifdef CONFIG_NET_POLL_CONTROLLER
2967static void skge_netpoll(struct net_device *dev)
2968{
2969 struct skge_port *skge = netdev_priv(dev);
2970
2971 disable_irq(dev->irq);
2972 skge_intr(dev->irq, skge->hw, NULL);
2973 enable_irq(dev->irq);
2974}
2975#endif
2976
2977static int skge_set_mac_address(struct net_device *dev, void *p)
2978{
2979 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 2980 struct skge_hw *hw = skge->hw;
2981 unsigned port = skge->port;
2982 const struct sockaddr *addr = p;
baef58b1
SH		 2983
2984 if (!is_valid_ether_addr(addr->sa_data))
2985 return -EADDRNOTAVAIL;
2986
d85b514f 2987 mutex_lock(&hw->phy_mutex);
baef58b1 2988 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 2989 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
baef58b1 2990 dev->dev_addr, ETH_ALEN);
c2681dd8 2991 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
baef58b1 2992 dev->dev_addr, ETH_ALEN);
c2681dd8
SH		 2993
2994 if (hw->chip_id == CHIP_ID_GENESIS)
2995 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2996 else {
2997 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2998 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2999 }
d85b514f 3000 mutex_unlock(&hw->phy_mutex);
c2681dd8
SH		 3001
3002 return 0;
baef58b1
SH		 3003}
3004
3005static const struct {
3006 u8 id;
3007 const char *name;
3008} skge_chips[] = {
3009 { CHIP_ID_GENESIS, "Genesis" },
3010 { CHIP_ID_YUKON, "Yukon" },
3011 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3012 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3013};
3014
3015static const char *skge_board_name(const struct skge_hw *hw)
3016{
3017 int i;
3018 static char buf[16];
3019
3020 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3021 if (skge_chips[i].id == hw->chip_id)
3022 return skge_chips[i].name;
3023
3024 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3025 return buf;
3026}
3027
3028
3029/*
3030 * Setup the board data structure, but don't bring up
3031 * the port(s)
3032 */
3033static int skge_reset(struct skge_hw *hw)
3034{
adba9e23 3035 u32 reg;
b9d64acc 3036 u16 ctst, pci_status;
5e1705dd 3037 u8 t8, mac_cfg, pmd_type, phy_type;
981d0377 3038 int i;
baef58b1
SH		 3039
3040 ctst = skge_read16(hw, B0_CTST);
3041
3042 /* do a SW reset */
3043 skge_write8(hw, B0_CTST, CS_RST_SET);
3044 skge_write8(hw, B0_CTST, CS_RST_CLR);
3045
3046 /* clear PCI errors, if any */
b9d64acc
SH		 3047 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3048 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3049
b9d64acc
SH		 3050 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3051 pci_write_config_word(hw->pdev, PCI_STATUS,
3052 pci_status | PCI_STATUS_ERROR_BITS);
3053 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3054 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3055
3056 /* restore CLK_RUN bits (for Yukon-Lite) */
3057 skge_write16(hw, B0_CTST,
3058 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3059
3060 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
5e1705dd
SH		 3061 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3062 pmd_type = skge_read8(hw, B2_PMD_TYP);
3063 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3064
95566065 3065 switch (hw->chip_id) {
baef58b1 3066 case CHIP_ID_GENESIS:
5e1705dd 3067 switch (phy_type) {
baef58b1
SH		 3068 case SK_PHY_BCOM:
3069 hw->phy_addr = PHY_ADDR_BCOM;
3070 break;
3071 default:
3072 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
5e1705dd 3073 pci_name(hw->pdev), phy_type);
baef58b1
SH		 3074 return -EOPNOTSUPP;
3075 }
3076 break;
3077
3078 case CHIP_ID_YUKON:
3079 case CHIP_ID_YUKON_LITE:
3080 case CHIP_ID_YUKON_LP:
5e1705dd
SH		 3081 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3082 hw->copper = 1;
baef58b1
SH		 3083
3084 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3085 break;
3086
3087 default:
3088 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3089 pci_name(hw->pdev), hw->chip_id);
3090 return -EOPNOTSUPP;
3091 }
3092
981d0377
SH		 3093 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3094 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3095 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3096
3097 /* read the adapters RAM size */
3098 t8 = skge_read8(hw, B2_E_0);
3099 if (hw->chip_id == CHIP_ID_GENESIS) {
3100 if (t8 == 3) {
3101 /* special case: 4 x 64k x 36, offset = 0x80000 */
3102 hw->ram_size = 0x100000;
3103 hw->ram_offset = 0x80000;
3104 } else
3105 hw->ram_size = t8 * 512;
3106 }
3107 else if (t8 == 0)
3108 hw->ram_size = 0x20000;
3109 else
3110 hw->ram_size = t8 * 4096;
3111
7c442fa1 3112 spin_lock_init(&hw->hw_lock);
cfc3ed79
SH		 3113 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3114 if (hw->ports > 1)
3115 hw->intr_mask |= IS_PORT_2;
3116
baef58b1
SH		 3117 if (hw->chip_id == CHIP_ID_GENESIS)
3118 genesis_init(hw);
3119 else {
3120 /* switch power to VCC (WA for VAUX problem) */
3121 skge_write8(hw, B0_POWER_CTRL,
3122 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3123
050ec18a
SH		 3124 /* avoid boards with stuck Hardware error bits */
3125 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3126 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3127 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3128 hw->intr_mask &= ~IS_HW_ERR;
3129 }
3130
adba9e23
SH		 3131 /* Clear PHY COMA */
3132 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3133 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3134 reg &= ~PCI_PHY_COMA;
3135 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3136 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3137
3138
981d0377 3139 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3140 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3141 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3142 }
3143 }
3144
3145 /* turn off hardware timer (unused) */
3146 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3147 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3148 skge_write8(hw, B0_LED, LED_STAT_ON);
3149
3150 /* enable the Tx Arbiters */
981d0377 3151 for (i = 0; i < hw->ports; i++)
6b0c1480 3152 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3153
3154 /* Initialize ram interface */
3155 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3156
3157 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3158 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3159 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3160 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3161 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3162 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3163 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3164 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3165 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3166 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3167 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3168 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3169
3170 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3171
3172 /* Set interrupt moderation for Transmit only
3173 * Receive interrupts avoided by NAPI
3174 */
3175 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3176 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3177 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3178
baef58b1
SH		 3179 skge_write32(hw, B0_IMSK, hw->intr_mask);
3180
d85b514f 3181 mutex_lock(&hw->phy_mutex);
981d0377 3182 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3183 if (hw->chip_id == CHIP_ID_GENESIS)
3184 genesis_reset(hw, i);
3185 else
3186 yukon_reset(hw, i);
3187 }
d85b514f 3188 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 3189
3190 return 0;
3191}
3192
3193/* Initialize network device */
981d0377
SH		 3194static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3195 int highmem)
baef58b1
SH		 3196{
3197 struct skge_port *skge;
3198 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3199
3200 if (!dev) {
3201 printk(KERN_ERR "skge etherdev alloc failed");
3202 return NULL;
3203 }
3204
3205 SET_MODULE_OWNER(dev);
3206 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3207 dev->open = skge_up;
3208 dev->stop = skge_down;
2cd8e5d3 3209 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3210 dev->hard_start_xmit = skge_xmit_frame;
3211 dev->get_stats = skge_get_stats;
3212 if (hw->chip_id == CHIP_ID_GENESIS)
3213 dev->set_multicast_list = genesis_set_multicast;
3214 else
3215 dev->set_multicast_list = yukon_set_multicast;
3216
3217 dev->set_mac_address = skge_set_mac_address;
3218 dev->change_mtu = skge_change_mtu;
3219 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3220 dev->tx_timeout = skge_tx_timeout;
3221 dev->watchdog_timeo = TX_WATCHDOG;
3222 dev->poll = skge_poll;
3223 dev->weight = NAPI_WEIGHT;
3224#ifdef CONFIG_NET_POLL_CONTROLLER
3225 dev->poll_controller = skge_netpoll;
3226#endif
3227 dev->irq = hw->pdev->irq;
3228 dev->features = NETIF_F_LLTX;
981d0377
SH		 3229 if (highmem)
3230 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3231
3232 skge = netdev_priv(dev);
3233 skge->netdev = dev;
3234 skge->hw = hw;
3235 skge->msg_enable = netif_msg_init(debug, default_msg);
3236 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3237 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3238
3239 /* Auto speed and flow control */
3240 skge->autoneg = AUTONEG_ENABLE;
3241 skge->flow_control = FLOW_MODE_SYMMETRIC;
3242 skge->duplex = -1;
3243 skge->speed = -1;
31b619c5 3244 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3245
3246 hw->dev[port] = dev;
3247
3248 skge->port = port;
3249
3250 spin_lock_init(&skge->tx_lock);
3251
baef58b1
SH		 3252 if (hw->chip_id != CHIP_ID_GENESIS) {
3253 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3254 skge->rx_csum = 1;
3255 }
3256
3257 /* read the mac address */
3258 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3259 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3260
3261 /* device is off until link detection */
3262 netif_carrier_off(dev);
3263 netif_stop_queue(dev);
3264
3265 return dev;
3266}
3267
3268static void __devinit skge_show_addr(struct net_device *dev)
3269{
3270 const struct skge_port *skge = netdev_priv(dev);
3271
3272 if (netif_msg_probe(skge))
3273 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3274 dev->name,
3275 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3276 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3277}
3278
3279static int __devinit skge_probe(struct pci_dev *pdev,
3280 const struct pci_device_id *ent)
3281{
3282 struct net_device *dev, *dev1;
3283 struct skge_hw *hw;
3284 int err, using_dac = 0;
3285
203babb6
SH		 3286 err = pci_enable_device(pdev);
3287 if (err) {
baef58b1
SH		 3288 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3289 pci_name(pdev));
3290 goto err_out;
3291 }
3292
203babb6
SH		 3293 err = pci_request_regions(pdev, DRV_NAME);
3294 if (err) {
baef58b1
SH		 3295 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3296 pci_name(pdev));
3297 goto err_out_disable_pdev;
3298 }
3299
3300 pci_set_master(pdev);
3301
93aea718 3302 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
baef58b1 3303 using_dac = 1;
77783a78 3304 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
93aea718
SH		 3305 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3306 using_dac = 0;
3307 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3308 }
3309
3310 if (err) {
3311 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3312 pci_name(pdev));
3313 goto err_out_free_regions;
baef58b1
SH		 3314 }
3315
3316#ifdef __BIG_ENDIAN
8f3f8193 3317 /* byte swap descriptors in hardware */
baef58b1
SH		 3318 {
3319 u32 reg;
3320
3321 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3322 reg |= PCI_REV_DESC;
3323 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3324 }
3325#endif
3326
3327 err = -ENOMEM;
7e863061 3328 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1
SH		 3329 if (!hw) {
3330 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3331 pci_name(pdev));
3332 goto err_out_free_regions;
3333 }
3334
baef58b1 3335 hw->pdev = pdev;
d85b514f
SH		 3336 mutex_init(&hw->phy_mutex);
3337 INIT_WORK(&hw->phy_work, skge_extirq, hw);
baef58b1
SH		 3338
3339 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3340 if (!hw->regs) {
3341 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3342 pci_name(pdev));
3343 goto err_out_free_hw;
3344 }
3345
203babb6
SH		 3346 err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw);
3347 if (err) {
baef58b1
SH		 3348 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3349 pci_name(pdev), pdev->irq);
3350 goto err_out_iounmap;
3351 }
3352 pci_set_drvdata(pdev, hw);
3353
3354 err = skge_reset(hw);
3355 if (err)
3356 goto err_out_free_irq;
3357
d7eaee08 3358 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
baef58b1 3359 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3360 skge_board_name(hw), hw->chip_rev);
baef58b1 3361
981d0377 3362 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3363 goto err_out_led_off;
3364
631ae320
SH		 3365 if (!is_valid_ether_addr(dev->dev_addr)) {
3366 printk(KERN_ERR PFX "%s: bad (zero?) ethernet address in rom\n",
3367 pci_name(pdev));
3368 err = -EIO;
3369 goto err_out_free_netdev;
3370 }
3371
3372
203babb6
SH		 3373 err = register_netdev(dev);
3374 if (err) {
baef58b1
SH		 3375 printk(KERN_ERR PFX "%s: cannot register net device\n",
3376 pci_name(pdev));
3377 goto err_out_free_netdev;
3378 }
3379
3380 skge_show_addr(dev);
3381
981d0377 3382 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3383 if (register_netdev(dev1) == 0)
3384 skge_show_addr(dev1);
3385 else {
3386 /* Failure to register second port need not be fatal */
3387 printk(KERN_WARNING PFX "register of second port failed\n");
3388 hw->dev[1] = NULL;
3389 free_netdev(dev1);
3390 }
3391 }
3392
3393 return 0;
3394
3395err_out_free_netdev:
3396 free_netdev(dev);
3397err_out_led_off:
3398 skge_write16(hw, B0_LED, LED_STAT_OFF);
3399err_out_free_irq:
3400 free_irq(pdev->irq, hw);
3401err_out_iounmap:
3402 iounmap(hw->regs);
3403err_out_free_hw:
3404 kfree(hw);
3405err_out_free_regions:
3406 pci_release_regions(pdev);
3407err_out_disable_pdev:
3408 pci_disable_device(pdev);
3409 pci_set_drvdata(pdev, NULL);
3410err_out:
3411 return err;
3412}
3413
3414static void __devexit skge_remove(struct pci_dev *pdev)
3415{
3416 struct skge_hw *hw = pci_get_drvdata(pdev);
3417 struct net_device *dev0, *dev1;
3418
95566065 3419 if (!hw)
baef58b1
SH		 3420 return;
3421
3422 if ((dev1 = hw->dev[1]))
3423 unregister_netdev(dev1);
3424 dev0 = hw->dev[0];
3425 unregister_netdev(dev0);
3426
7c442fa1
SH		 3427 spin_lock_irq(&hw->hw_lock);
3428 hw->intr_mask = 0;
46a60f2d 3429 skge_write32(hw, B0_IMSK, 0);
7c442fa1
SH		 3430 spin_unlock_irq(&hw->hw_lock);
3431
46a60f2d 3432 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3433 skge_write8(hw, B0_CTST, CS_RST_SET);
3434
d85b514f 3435 flush_scheduled_work();
baef58b1
SH		 3436
3437 free_irq(pdev->irq, hw);
3438 pci_release_regions(pdev);
3439 pci_disable_device(pdev);
3440 if (dev1)
3441 free_netdev(dev1);
3442 free_netdev(dev0);
46a60f2d 3443
baef58b1
SH		 3444 iounmap(hw->regs);
3445 kfree(hw);
3446 pci_set_drvdata(pdev, NULL);
3447}
3448
3449#ifdef CONFIG_PM
2a569579 3450static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3451{
3452 struct skge_hw *hw = pci_get_drvdata(pdev);
3453 int i, wol = 0;
3454
95566065 3455 for (i = 0; i < 2; i++) {
baef58b1
SH		 3456 struct net_device *dev = hw->dev[i];
3457
3458 if (dev) {
3459 struct skge_port *skge = netdev_priv(dev);
3460 if (netif_running(dev)) {
3461 netif_carrier_off(dev);
46a60f2d
SH		 3462 if (skge->wol)
3463 netif_stop_queue(dev);
3464 else
3465 skge_down(dev);
baef58b1
SH		 3466 }
3467 netif_device_detach(dev);
3468 wol |= skge->wol;
3469 }
3470 }
3471
3472 pci_save_state(pdev);
2a569579 3473 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3474 pci_disable_device(pdev);
3475 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3476
3477 return 0;
3478}
3479
3480static int skge_resume(struct pci_dev *pdev)
3481{
3482 struct skge_hw *hw = pci_get_drvdata(pdev);
3483 int i;
3484
3485 pci_set_power_state(pdev, PCI_D0);
3486 pci_restore_state(pdev);
3487 pci_enable_wake(pdev, PCI_D0, 0);
3488
3489 skge_reset(hw);
3490
95566065 3491 for (i = 0; i < 2; i++) {
baef58b1
SH		 3492 struct net_device *dev = hw->dev[i];
3493 if (dev) {
3494 netif_device_attach(dev);
edd702e8
SH		 3495 if (netif_running(dev) && skge_up(dev))
3496 dev_close(dev);
baef58b1
SH		 3497 }
3498 }
3499 return 0;
3500}
3501#endif
3502
3503static struct pci_driver skge_driver = {
3504 .name = DRV_NAME,
3505 .id_table = skge_id_table,
3506 .probe = skge_probe,
3507 .remove = __devexit_p(skge_remove),
3508#ifdef CONFIG_PM
3509 .suspend = skge_suspend,
3510 .resume = skge_resume,
3511#endif
3512};
3513
3514static int __init skge_init_module(void)
3515{
3516 return pci_module_init(&skge_driver);
3517}
3518
3519static void __exit skge_cleanup_module(void)
3520{
3521 pci_unregister_driver(&skge_driver);
3522}
3523
3524module_init(skge_init_module);
3525module_exit(skge_cleanup_module);
Linux 6.x block layer and io_uring tree(s)