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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
[linux-2.6-block.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
14c85021 26#include <linux/in.h>
baef58b1
SH		 27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/if_vlan.h>
35#include <linux/ip.h>
36#include <linux/delay.h>
37#include <linux/crc32.h>
4075400b 38#include <linux/dma-mapping.h>
678aa1f6 39#include <linux/debugfs.h>
d43c36dc 40#include <linux/sched.h>
678aa1f6 41#include <linux/seq_file.h>
2cd8e5d3 42#include <linux/mii.h>
baef58b1
SH		 43#include <asm/irq.h>
44
45#include "skge.h"
46
47#define DRV_NAME "skge"
bf9f56d5 48#define DRV_VERSION "1.13"
baef58b1
SH		 49#define PFX DRV_NAME " "
50
51#define DEFAULT_TX_RING_SIZE 128
52#define DEFAULT_RX_RING_SIZE 512
53#define MAX_TX_RING_SIZE 1024
9db96479 54#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 55#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 56#define RX_COPY_THRESHOLD 128
57#define RX_BUF_SIZE 1536
baef58b1
SH		 58#define PHY_RETRIES 1000
59#define ETH_JUMBO_MTU 9000
60#define TX_WATCHDOG (5 * HZ)
61#define NAPI_WEIGHT 64
6abebb53 62#define BLINK_MS 250
501fb72d 63#define LINK_HZ HZ
baef58b1 64
afa151b9
SH		 65#define SKGE_EEPROM_MAGIC 0x9933aabb
66
67
baef58b1 68MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
65ebe634 69MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
baef58b1
SH		 70MODULE_LICENSE("GPL");
71MODULE_VERSION(DRV_VERSION);
72
73static const u32 default_msg
74 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
75 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
76
77static int debug = -1; /* defaults above */
78module_param(debug, int, 0);
79MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
80
81static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 82 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
83 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
84 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
85 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
f19841f5 86 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
2d2a3871 87 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 88 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
89 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
90 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 91 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
f19841f5 92 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
baef58b1
SH		 93 { 0 }
94};
95MODULE_DEVICE_TABLE(pci, skge_id_table);
96
97static int skge_up(struct net_device *dev);
98static int skge_down(struct net_device *dev);
ee294dcd 99static void skge_phy_reset(struct skge_port *skge);
513f533e 100static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 101static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
102static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 103static void genesis_get_stats(struct skge_port *skge, u64 *data);
104static void yukon_get_stats(struct skge_port *skge, u64 *data);
105static void yukon_init(struct skge_hw *hw, int port);
baef58b1 106static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 107static void genesis_link_up(struct skge_port *skge);
f80d032b 108static void skge_set_multicast(struct net_device *dev);
baef58b1 109
7e676d91 110/* Avoid conditionals by using array */
baef58b1
SH		 111static const int txqaddr[] = { Q_XA1, Q_XA2 };
112static const int rxqaddr[] = { Q_R1, Q_R2 };
113static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
114static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
4ebabfcb
SH		 115static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
116static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 117
baef58b1
SH		 118static int skge_get_regs_len(struct net_device *dev)
119{
c3f8be96 120 return 0x4000;
baef58b1
SH		 121}
122
123/*
c3f8be96
SH		 124 * Returns copy of whole control register region
125 * Note: skip RAM address register because accessing it will
126 * cause bus hangs!
baef58b1
SH		 127 */
128static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
129 void *p)
130{
131 const struct skge_port *skge = netdev_priv(dev);
baef58b1 132 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 133
134 regs->version = 1;
c3f8be96
SH		 135 memset(p, 0, regs->len);
136 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 137
c3f8be96
SH		 138 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
139 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 140}
141
8f3f8193 142/* Wake on Lan only supported on Yukon chips with rev 1 or above */
a504e64a 143static u32 wol_supported(const struct skge_hw *hw)
baef58b1 144{
d17ecb23 145 if (hw->chip_id == CHIP_ID_GENESIS)
a504e64a 146 return 0;
d17ecb23
SH		 147
148 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
149 return 0;
150
151 return WAKE_MAGIC | WAKE_PHY;
a504e64a
SH		 152}
153
a504e64a
SH		 154static void skge_wol_init(struct skge_port *skge)
155{
156 struct skge_hw *hw = skge->hw;
157 int port = skge->port;
692412b3 158 u16 ctrl;
a504e64a 159
a504e64a
SH		 160 skge_write16(hw, B0_CTST, CS_RST_CLR);
161 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
162
692412b3
SH		 163 /* Turn on Vaux */
164 skge_write8(hw, B0_POWER_CTRL,
165 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
a504e64a 166
692412b3
SH		 167 /* WA code for COMA mode -- clear PHY reset */
168 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
169 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
170 u32 reg = skge_read32(hw, B2_GP_IO);
171 reg |= GP_DIR_9;
172 reg &= ~GP_IO_9;
173 skge_write32(hw, B2_GP_IO, reg);
174 }
a504e64a 175
692412b3
SH		 176 skge_write32(hw, SK_REG(port, GPHY_CTRL),
177 GPC_DIS_SLEEP |
178 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
179 GPC_ANEG_1 | GPC_RST_SET);
a504e64a 180
692412b3
SH		 181 skge_write32(hw, SK_REG(port, GPHY_CTRL),
182 GPC_DIS_SLEEP |
183 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
184 GPC_ANEG_1 | GPC_RST_CLR);
185
186 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
187
188 /* Force to 10/100 skge_reset will re-enable on resume */
189 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
190 PHY_AN_100FULL | PHY_AN_100HALF |
191 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
192 /* no 1000 HD/FD */
193 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
194 gm_phy_write(hw, port, PHY_MARV_CTRL,
195 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
196 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
a504e64a 197
a504e64a
SH		 198
199 /* Set GMAC to no flow control and auto update for speed/duplex */
200 gma_write16(hw, port, GM_GP_CTRL,
201 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
202 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
203
204 /* Set WOL address */
205 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
206 skge->netdev->dev_addr, ETH_ALEN);
207
208 /* Turn on appropriate WOL control bits */
209 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
210 ctrl = 0;
211 if (skge->wol & WAKE_PHY)
212 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
213 else
214 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
215
216 if (skge->wol & WAKE_MAGIC)
217 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
218 else
a419aef8 219 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
a504e64a
SH		 220
221 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
222 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
223
224 /* block receiver */
225 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 226}
227
228static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
229{
230 struct skge_port *skge = netdev_priv(dev);
231
a504e64a
SH		 232 wol->supported = wol_supported(skge->hw);
233 wol->wolopts = skge->wol;
baef58b1
SH		 234}
235
236static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
237{
238 struct skge_port *skge = netdev_priv(dev);
239 struct skge_hw *hw = skge->hw;
240
8e95a202
JP		 241 if ((wol->wolopts & ~wol_supported(hw)) ||
242 !device_can_wakeup(&hw->pdev->dev))
baef58b1
SH		 243 return -EOPNOTSUPP;
244
a504e64a 245 skge->wol = wol->wolopts;
5177b324
RW		 246
247 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
248
baef58b1
SH		 249 return 0;
250}
251
8f3f8193
SH		 252/* Determine supported/advertised modes based on hardware.
253 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 254 */
255static u32 skge_supported_modes(const struct skge_hw *hw)
256{
257 u32 supported;
258
5e1705dd 259 if (hw->copper) {
31b619c5
SH		 260 supported = SUPPORTED_10baseT_Half
261 | SUPPORTED_10baseT_Full
262 | SUPPORTED_100baseT_Half
263 | SUPPORTED_100baseT_Full
264 | SUPPORTED_1000baseT_Half
265 | SUPPORTED_1000baseT_Full
266 | SUPPORTED_Autoneg| SUPPORTED_TP;
267
268 if (hw->chip_id == CHIP_ID_GENESIS)
269 supported &= ~(SUPPORTED_10baseT_Half
270 | SUPPORTED_10baseT_Full
271 | SUPPORTED_100baseT_Half
272 | SUPPORTED_100baseT_Full);
273
274 else if (hw->chip_id == CHIP_ID_YUKON)
275 supported &= ~SUPPORTED_1000baseT_Half;
276 } else
4b67be99
SH		 277 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
278 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
31b619c5
SH		 279
280 return supported;
281}
baef58b1
SH		 282
283static int skge_get_settings(struct net_device *dev,
284 struct ethtool_cmd *ecmd)
285{
286 struct skge_port *skge = netdev_priv(dev);
287 struct skge_hw *hw = skge->hw;
288
289 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 290 ecmd->supported = skge_supported_modes(hw);
baef58b1 291
5e1705dd 292 if (hw->copper) {
baef58b1
SH		 293 ecmd->port = PORT_TP;
294 ecmd->phy_address = hw->phy_addr;
31b619c5 295 } else
baef58b1 296 ecmd->port = PORT_FIBRE;
baef58b1
SH		 297
298 ecmd->advertising = skge->advertising;
299 ecmd->autoneg = skge->autoneg;
300 ecmd->speed = skge->speed;
301 ecmd->duplex = skge->duplex;
302 return 0;
303}
304
baef58b1
SH		 305static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
306{
307 struct skge_port *skge = netdev_priv(dev);
308 const struct skge_hw *hw = skge->hw;
31b619c5 309 u32 supported = skge_supported_modes(hw);
9ac1353f 310 int err = 0;
baef58b1
SH		 311
312 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 313 ecmd->advertising = supported;
314 skge->duplex = -1;
315 skge->speed = -1;
baef58b1 316 } else {
31b619c5
SH		 317 u32 setting;
318
2c668514 319 switch (ecmd->speed) {
baef58b1 320 case SPEED_1000:
31b619c5
SH		 321 if (ecmd->duplex == DUPLEX_FULL)
322 setting = SUPPORTED_1000baseT_Full;
323 else if (ecmd->duplex == DUPLEX_HALF)
324 setting = SUPPORTED_1000baseT_Half;
325 else
326 return -EINVAL;
baef58b1
SH		 327 break;
328 case SPEED_100:
31b619c5
SH		 329 if (ecmd->duplex == DUPLEX_FULL)
330 setting = SUPPORTED_100baseT_Full;
331 else if (ecmd->duplex == DUPLEX_HALF)
332 setting = SUPPORTED_100baseT_Half;
333 else
334 return -EINVAL;
335 break;
336
baef58b1 337 case SPEED_10:
31b619c5
SH		 338 if (ecmd->duplex == DUPLEX_FULL)
339 setting = SUPPORTED_10baseT_Full;
340 else if (ecmd->duplex == DUPLEX_HALF)
341 setting = SUPPORTED_10baseT_Half;
342 else
baef58b1
SH		 343 return -EINVAL;
344 break;
345 default:
346 return -EINVAL;
347 }
31b619c5
SH		 348
349 if ((setting & supported) == 0)
350 return -EINVAL;
351
352 skge->speed = ecmd->speed;
353 skge->duplex = ecmd->duplex;
baef58b1
SH		 354 }
355
356 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 357 skge->advertising = ecmd->advertising;
358
9ac1353f
XZ		 359 if (netif_running(dev)) {
360 skge_down(dev);
361 err = skge_up(dev);
362 if (err) {
363 dev_close(dev);
364 return err;
365 }
366 }
ee294dcd 367
baef58b1
SH		 368 return (0);
369}
370
371static void skge_get_drvinfo(struct net_device *dev,
372 struct ethtool_drvinfo *info)
373{
374 struct skge_port *skge = netdev_priv(dev);
375
376 strcpy(info->driver, DRV_NAME);
377 strcpy(info->version, DRV_VERSION);
378 strcpy(info->fw_version, "N/A");
379 strcpy(info->bus_info, pci_name(skge->hw->pdev));
380}
381
382static const struct skge_stat {
383 char name[ETH_GSTRING_LEN];
384 u16 xmac_offset;
385 u16 gma_offset;
386} skge_stats[] = {
387 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
388 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
389
390 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
391 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
392 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
393 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
394 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
395 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
396 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
397 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
398
399 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
400 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
401 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
402 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
403 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
404 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
405
406 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
407 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
408 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
409 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
410 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
411};
412
b9f2c044 413static int skge_get_sset_count(struct net_device *dev, int sset)
baef58b1 414{
b9f2c044
JG		 415 switch (sset) {
416 case ETH_SS_STATS:
417 return ARRAY_SIZE(skge_stats);
418 default:
419 return -EOPNOTSUPP;
420 }
baef58b1
SH		 421}
422
423static void skge_get_ethtool_stats(struct net_device *dev,
424 struct ethtool_stats *stats, u64 *data)
425{
426 struct skge_port *skge = netdev_priv(dev);
427
428 if (skge->hw->chip_id == CHIP_ID_GENESIS)
429 genesis_get_stats(skge, data);
430 else
431 yukon_get_stats(skge, data);
432}
433
434/* Use hardware MIB variables for critical path statistics and
435 * transmit feedback not reported at interrupt.
436 * Other errors are accounted for in interrupt handler.
437 */
438static struct net_device_stats *skge_get_stats(struct net_device *dev)
439{
440 struct skge_port *skge = netdev_priv(dev);
441 u64 data[ARRAY_SIZE(skge_stats)];
442
443 if (skge->hw->chip_id == CHIP_ID_GENESIS)
444 genesis_get_stats(skge, data);
445 else
446 yukon_get_stats(skge, data);
447
da00772f
SH		 448 dev->stats.tx_bytes = data[0];
449 dev->stats.rx_bytes = data[1];
450 dev->stats.tx_packets = data[2] + data[4] + data[6];
451 dev->stats.rx_packets = data[3] + data[5] + data[7];
452 dev->stats.multicast = data[3] + data[5];
453 dev->stats.collisions = data[10];
454 dev->stats.tx_aborted_errors = data[12];
baef58b1 455
da00772f 456 return &dev->stats;
baef58b1
SH		 457}
458
459static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
460{
461 int i;
462
95566065 463 switch (stringset) {
baef58b1
SH		 464 case ETH_SS_STATS:
465 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
466 memcpy(data + i * ETH_GSTRING_LEN,
467 skge_stats[i].name, ETH_GSTRING_LEN);
468 break;
469 }
470}
471
472static void skge_get_ring_param(struct net_device *dev,
473 struct ethtool_ringparam *p)
474{
475 struct skge_port *skge = netdev_priv(dev);
476
477 p->rx_max_pending = MAX_RX_RING_SIZE;
478 p->tx_max_pending = MAX_TX_RING_SIZE;
479 p->rx_mini_max_pending = 0;
480 p->rx_jumbo_max_pending = 0;
481
482 p->rx_pending = skge->rx_ring.count;
483 p->tx_pending = skge->tx_ring.count;
484 p->rx_mini_pending = 0;
485 p->rx_jumbo_pending = 0;
486}
487
488static int skge_set_ring_param(struct net_device *dev,
489 struct ethtool_ringparam *p)
490{
491 struct skge_port *skge = netdev_priv(dev);
e824b3eb 492 int err = 0;
baef58b1
SH		 493
494 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 495 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 496 return -EINVAL;
497
498 skge->rx_ring.count = p->rx_pending;
499 skge->tx_ring.count = p->tx_pending;
500
501 if (netif_running(dev)) {
502 skge_down(dev);
3b8bb472
SH		 503 err = skge_up(dev);
504 if (err)
505 dev_close(dev);
baef58b1
SH		 506 }
507
e824b3eb 508 return err;
baef58b1
SH		 509}
510
511static u32 skge_get_msglevel(struct net_device *netdev)
512{
513 struct skge_port *skge = netdev_priv(netdev);
514 return skge->msg_enable;
515}
516
517static void skge_set_msglevel(struct net_device *netdev, u32 value)
518{
519 struct skge_port *skge = netdev_priv(netdev);
520 skge->msg_enable = value;
521}
522
523static int skge_nway_reset(struct net_device *dev)
524{
525 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 526
527 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
528 return -EINVAL;
529
ee294dcd 530 skge_phy_reset(skge);
baef58b1
SH		 531 return 0;
532}
533
534static int skge_set_sg(struct net_device *dev, u32 data)
535{
536 struct skge_port *skge = netdev_priv(dev);
537 struct skge_hw *hw = skge->hw;
538
539 if (hw->chip_id == CHIP_ID_GENESIS && data)
540 return -EOPNOTSUPP;
541 return ethtool_op_set_sg(dev, data);
542}
543
544static int skge_set_tx_csum(struct net_device *dev, u32 data)
545{
546 struct skge_port *skge = netdev_priv(dev);
547 struct skge_hw *hw = skge->hw;
548
549 if (hw->chip_id == CHIP_ID_GENESIS && data)
550 return -EOPNOTSUPP;
551
552 return ethtool_op_set_tx_csum(dev, data);
553}
554
555static u32 skge_get_rx_csum(struct net_device *dev)
556{
557 struct skge_port *skge = netdev_priv(dev);
558
559 return skge->rx_csum;
560}
561
562/* Only Yukon supports checksum offload. */
563static int skge_set_rx_csum(struct net_device *dev, u32 data)
564{
565 struct skge_port *skge = netdev_priv(dev);
566
567 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
568 return -EOPNOTSUPP;
569
570 skge->rx_csum = data;
571 return 0;
572}
573
baef58b1
SH		 574static void skge_get_pauseparam(struct net_device *dev,
575 struct ethtool_pauseparam *ecmd)
576{
577 struct skge_port *skge = netdev_priv(dev);
578
8e95a202
JP		 579 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
580 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
581 ecmd->tx_pause = (ecmd->rx_pause ||
582 (skge->flow_control == FLOW_MODE_LOC_SEND));
baef58b1 583
5d5c8e03 584 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 585}
586
587static int skge_set_pauseparam(struct net_device *dev,
588 struct ethtool_pauseparam *ecmd)
589{
590 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 591 struct ethtool_pauseparam old;
9ac1353f 592 int err = 0;
baef58b1 593
5d5c8e03
SH		 594 skge_get_pauseparam(dev, &old);
595
596 if (ecmd->autoneg != old.autoneg)
597 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
598 else {
599 if (ecmd->rx_pause && ecmd->tx_pause)
600 skge->flow_control = FLOW_MODE_SYMMETRIC;
601 else if (ecmd->rx_pause && !ecmd->tx_pause)
602 skge->flow_control = FLOW_MODE_SYM_OR_REM;
603 else if (!ecmd->rx_pause && ecmd->tx_pause)
604 skge->flow_control = FLOW_MODE_LOC_SEND;
605 else
606 skge->flow_control = FLOW_MODE_NONE;
607 }
baef58b1 608
9ac1353f
XZ		 609 if (netif_running(dev)) {
610 skge_down(dev);
611 err = skge_up(dev);
612 if (err) {
613 dev_close(dev);
614 return err;
615 }
616 }
5d5c8e03 617
baef58b1
SH		 618 return 0;
619}
620
621/* Chip internal frequency for clock calculations */
622static inline u32 hwkhz(const struct skge_hw *hw)
623{
187ff3b8 624 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 625}
626
8f3f8193 627/* Chip HZ to microseconds */
baef58b1
SH		 628static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
629{
630 return (ticks * 1000) / hwkhz(hw);
631}
632
8f3f8193 633/* Microseconds to chip HZ */
baef58b1
SH		 634static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
635{
636 return hwkhz(hw) * usec / 1000;
637}
638
639static int skge_get_coalesce(struct net_device *dev,
640 struct ethtool_coalesce *ecmd)
641{
642 struct skge_port *skge = netdev_priv(dev);
643 struct skge_hw *hw = skge->hw;
644 int port = skge->port;
645
646 ecmd->rx_coalesce_usecs = 0;
647 ecmd->tx_coalesce_usecs = 0;
648
649 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
650 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
651 u32 msk = skge_read32(hw, B2_IRQM_MSK);
652
653 if (msk & rxirqmask[port])
654 ecmd->rx_coalesce_usecs = delay;
655 if (msk & txirqmask[port])
656 ecmd->tx_coalesce_usecs = delay;
657 }
658
659 return 0;
660}
661
662/* Note: interrupt timer is per board, but can turn on/off per port */
663static int skge_set_coalesce(struct net_device *dev,
664 struct ethtool_coalesce *ecmd)
665{
666 struct skge_port *skge = netdev_priv(dev);
667 struct skge_hw *hw = skge->hw;
668 int port = skge->port;
669 u32 msk = skge_read32(hw, B2_IRQM_MSK);
670 u32 delay = 25;
671
672 if (ecmd->rx_coalesce_usecs == 0)
673 msk &= ~rxirqmask[port];
674 else if (ecmd->rx_coalesce_usecs < 25 ||
675 ecmd->rx_coalesce_usecs > 33333)
676 return -EINVAL;
677 else {
678 msk |= rxirqmask[port];
679 delay = ecmd->rx_coalesce_usecs;
680 }
681
682 if (ecmd->tx_coalesce_usecs == 0)
683 msk &= ~txirqmask[port];
684 else if (ecmd->tx_coalesce_usecs < 25 ||
685 ecmd->tx_coalesce_usecs > 33333)
686 return -EINVAL;
687 else {
688 msk |= txirqmask[port];
689 delay = min(delay, ecmd->rx_coalesce_usecs);
690 }
691
692 skge_write32(hw, B2_IRQM_MSK, msk);
693 if (msk == 0)
694 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
695 else {
696 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
697 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
698 }
699 return 0;
700}
701
6abebb53
SH		 702enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
703static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 704{
6abebb53
SH		 705 struct skge_hw *hw = skge->hw;
706 int port = skge->port;
707
9cbe330f 708 spin_lock_bh(&hw->phy_lock);
baef58b1 709 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 710 switch (mode) {
711 case LED_MODE_OFF:
64f6b64d
SH		 712 if (hw->phy_type == SK_PHY_BCOM)
713 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
714 else {
715 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
716 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
717 }
6abebb53
SH		 718 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
719 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
720 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
721 break;
baef58b1 722
6abebb53
SH		 723 case LED_MODE_ON:
724 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
725 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 726
6abebb53
SH		 727 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
728 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 729
6abebb53 730 break;
baef58b1 731
6abebb53
SH		 732 case LED_MODE_TST:
733 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
734 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
735 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 736
64f6b64d
SH		 737 if (hw->phy_type == SK_PHY_BCOM)
738 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
739 else {
740 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
741 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
742 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
743 }
744
6abebb53 745 }
baef58b1 746 } else {
6abebb53
SH		 747 switch (mode) {
748 case LED_MODE_OFF:
749 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
750 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
751 PHY_M_LED_MO_DUP(MO_LED_OFF) |
752 PHY_M_LED_MO_10(MO_LED_OFF) |
753 PHY_M_LED_MO_100(MO_LED_OFF) |
754 PHY_M_LED_MO_1000(MO_LED_OFF) |
755 PHY_M_LED_MO_RX(MO_LED_OFF));
756 break;
757 case LED_MODE_ON:
758 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
759 PHY_M_LED_PULS_DUR(PULS_170MS) |
760 PHY_M_LED_BLINK_RT(BLINK_84MS) |
761 PHY_M_LEDC_TX_CTRL |
762 PHY_M_LEDC_DP_CTRL);
46a60f2d 763
6abebb53
SH		 764 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
765 PHY_M_LED_MO_RX(MO_LED_OFF) |
766 (skge->speed == SPEED_100 ?
767 PHY_M_LED_MO_100(MO_LED_ON) : 0));
768 break;
769 case LED_MODE_TST:
770 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
771 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
772 PHY_M_LED_MO_DUP(MO_LED_ON) |
773 PHY_M_LED_MO_10(MO_LED_ON) |
774 PHY_M_LED_MO_100(MO_LED_ON) |
775 PHY_M_LED_MO_1000(MO_LED_ON) |
776 PHY_M_LED_MO_RX(MO_LED_ON));
777 }
baef58b1 778 }
9cbe330f 779 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 780}
781
782/* blink LED's for finding board */
783static int skge_phys_id(struct net_device *dev, u32 data)
784{
785 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 786 unsigned long ms;
787 enum led_mode mode = LED_MODE_TST;
baef58b1 788
95566065 789 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 790 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
791 else
792 ms = data * 1000;
baef58b1 793
6abebb53
SH		 794 while (ms > 0) {
795 skge_led(skge, mode);
796 mode ^= LED_MODE_TST;
baef58b1 797
6abebb53
SH		 798 if (msleep_interruptible(BLINK_MS))
799 break;
800 ms -= BLINK_MS;
801 }
baef58b1 802
6abebb53
SH		 803 /* back to regular LED state */
804 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 805
806 return 0;
807}
808
afa151b9
SH		 809static int skge_get_eeprom_len(struct net_device *dev)
810{
811 struct skge_port *skge = netdev_priv(dev);
812 u32 reg2;
813
814 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
815 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
816}
817
818static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
819{
820 u32 val;
821
822 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
823
824 do {
825 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
826 } while (!(offset & PCI_VPD_ADDR_F));
827
828 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
829 return val;
830}
831
832static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
833{
834 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
835 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
836 offset | PCI_VPD_ADDR_F);
837
838 do {
839 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
840 } while (offset & PCI_VPD_ADDR_F);
841}
842
843static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
844 u8 *data)
845{
846 struct skge_port *skge = netdev_priv(dev);
847 struct pci_dev *pdev = skge->hw->pdev;
848 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
849 int length = eeprom->len;
850 u16 offset = eeprom->offset;
851
852 if (!cap)
853 return -EINVAL;
854
855 eeprom->magic = SKGE_EEPROM_MAGIC;
856
857 while (length > 0) {
858 u32 val = skge_vpd_read(pdev, cap, offset);
859 int n = min_t(int, length, sizeof(val));
860
861 memcpy(data, &val, n);
862 length -= n;
863 data += n;
864 offset += n;
865 }
866 return 0;
867}
868
869static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
870 u8 *data)
871{
872 struct skge_port *skge = netdev_priv(dev);
873 struct pci_dev *pdev = skge->hw->pdev;
874 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
875 int length = eeprom->len;
876 u16 offset = eeprom->offset;
877
878 if (!cap)
879 return -EINVAL;
880
881 if (eeprom->magic != SKGE_EEPROM_MAGIC)
882 return -EINVAL;
883
884 while (length > 0) {
885 u32 val;
886 int n = min_t(int, length, sizeof(val));
887
888 if (n < sizeof(val))
889 val = skge_vpd_read(pdev, cap, offset);
890 memcpy(&val, data, n);
891
892 skge_vpd_write(pdev, cap, offset, val);
893
894 length -= n;
895 data += n;
896 offset += n;
897 }
898 return 0;
899}
900
7282d491 901static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 902 .get_settings = skge_get_settings,
903 .set_settings = skge_set_settings,
904 .get_drvinfo = skge_get_drvinfo,
905 .get_regs_len = skge_get_regs_len,
906 .get_regs = skge_get_regs,
907 .get_wol = skge_get_wol,
908 .set_wol = skge_set_wol,
909 .get_msglevel = skge_get_msglevel,
910 .set_msglevel = skge_set_msglevel,
911 .nway_reset = skge_nway_reset,
912 .get_link = ethtool_op_get_link,
afa151b9
SH		 913 .get_eeprom_len = skge_get_eeprom_len,
914 .get_eeprom = skge_get_eeprom,
915 .set_eeprom = skge_set_eeprom,
baef58b1
SH		 916 .get_ringparam = skge_get_ring_param,
917 .set_ringparam = skge_set_ring_param,
918 .get_pauseparam = skge_get_pauseparam,
919 .set_pauseparam = skge_set_pauseparam,
920 .get_coalesce = skge_get_coalesce,
921 .set_coalesce = skge_set_coalesce,
baef58b1 922 .set_sg = skge_set_sg,
baef58b1
SH		 923 .set_tx_csum = skge_set_tx_csum,
924 .get_rx_csum = skge_get_rx_csum,
925 .set_rx_csum = skge_set_rx_csum,
926 .get_strings = skge_get_strings,
927 .phys_id = skge_phys_id,
b9f2c044 928 .get_sset_count = skge_get_sset_count,
baef58b1
SH		 929 .get_ethtool_stats = skge_get_ethtool_stats,
930};
931
932/*
933 * Allocate ring elements and chain them together
934 * One-to-one association of board descriptors with ring elements
935 */
c3da1447 936static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 937{
938 struct skge_tx_desc *d;
939 struct skge_element *e;
940 int i;
941
cd861280 942 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
baef58b1
SH		 943 if (!ring->start)
944 return -ENOMEM;
945
946 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
947 e->desc = d;
948 if (i == ring->count - 1) {
949 e->next = ring->start;
950 d->next_offset = base;
951 } else {
952 e->next = e + 1;
953 d->next_offset = base + (i+1) * sizeof(*d);
954 }
955 }
956 ring->to_use = ring->to_clean = ring->start;
957
958 return 0;
959}
960
19a33d4e
SH		 961/* Allocate and setup a new buffer for receiving */
962static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
963 struct sk_buff *skb, unsigned int bufsize)
964{
965 struct skge_rx_desc *rd = e->desc;
966 u64 map;
baef58b1
SH		 967
968 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
969 PCI_DMA_FROMDEVICE);
970
971 rd->dma_lo = map;
972 rd->dma_hi = map >> 32;
973 e->skb = skb;
974 rd->csum1_start = ETH_HLEN;
975 rd->csum2_start = ETH_HLEN;
976 rd->csum1 = 0;
977 rd->csum2 = 0;
978
979 wmb();
980
981 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
982 pci_unmap_addr_set(e, mapaddr, map);
983 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 984}
985
19a33d4e
SH		 986/* Resume receiving using existing skb,
987 * Note: DMA address is not changed by chip.
988 * MTU not changed while receiver active.
989 */
5a011447 990static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 991{
992 struct skge_rx_desc *rd = e->desc;
993
994 rd->csum2 = 0;
995 rd->csum2_start = ETH_HLEN;
996
997 wmb();
998
999 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
1000}
1001
1002
1003/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 1004static void skge_rx_clean(struct skge_port *skge)
1005{
1006 struct skge_hw *hw = skge->hw;
1007 struct skge_ring *ring = &skge->rx_ring;
1008 struct skge_element *e;
1009
19a33d4e
SH		 1010 e = ring->start;
1011 do {
baef58b1
SH		 1012 struct skge_rx_desc *rd = e->desc;
1013 rd->control = 0;
19a33d4e
SH		 1014 if (e->skb) {
1015 pci_unmap_single(hw->pdev,
1016 pci_unmap_addr(e, mapaddr),
1017 pci_unmap_len(e, maplen),
1018 PCI_DMA_FROMDEVICE);
1019 dev_kfree_skb(e->skb);
1020 e->skb = NULL;
1021 }
1022 } while ((e = e->next) != ring->start);
baef58b1
SH		 1023}
1024
19a33d4e 1025
baef58b1 1026/* Allocate buffers for receive ring
19a33d4e 1027 * For receive: to_clean is next received frame.
baef58b1 1028 */
c54f9765 1029static int skge_rx_fill(struct net_device *dev)
baef58b1 1030{
c54f9765 1031 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 1032 struct skge_ring *ring = &skge->rx_ring;
1033 struct skge_element *e;
baef58b1 1034
19a33d4e
SH		 1035 e = ring->start;
1036 do {
383181ac 1037 struct sk_buff *skb;
baef58b1 1038
c54f9765
SH		 1039 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1040 GFP_KERNEL);
19a33d4e
SH		 1041 if (!skb)
1042 return -ENOMEM;
1043
383181ac
SH		 1044 skb_reserve(skb, NET_IP_ALIGN);
1045 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 1046 } while ( (e = e->next) != ring->start);
baef58b1 1047
19a33d4e
SH		 1048 ring->to_clean = ring->start;
1049 return 0;
baef58b1
SH		 1050}
1051
5d5c8e03
SH		 1052static const char *skge_pause(enum pause_status status)
1053{
1054 switch(status) {
1055 case FLOW_STAT_NONE:
1056 return "none";
1057 case FLOW_STAT_REM_SEND:
1058 return "rx only";
1059 case FLOW_STAT_LOC_SEND:
1060 return "tx_only";
1061 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1062 return "both";
1063 default:
1064 return "indeterminated";
1065 }
1066}
1067
1068
baef58b1
SH		 1069static void skge_link_up(struct skge_port *skge)
1070{
46a60f2d 1071 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 1072 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1073
baef58b1 1074 netif_carrier_on(skge->netdev);
29b4e886 1075 netif_wake_queue(skge->netdev);
baef58b1 1076
5d5c8e03 1077 if (netif_msg_link(skge)) {
baef58b1
SH		 1078 printk(KERN_INFO PFX
1079 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1080 skge->netdev->name, skge->speed,
1081 skge->duplex == DUPLEX_FULL ? "full" : "half",
5d5c8e03
SH		 1082 skge_pause(skge->flow_status));
1083 }
baef58b1
SH		 1084}
1085
1086static void skge_link_down(struct skge_port *skge)
1087{
54cfb5aa 1088 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 1089 netif_carrier_off(skge->netdev);
1090 netif_stop_queue(skge->netdev);
1091
1092 if (netif_msg_link(skge))
1093 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
1094}
1095
a1bc9b87
SH		 1096
1097static void xm_link_down(struct skge_hw *hw, int port)
1098{
1099 struct net_device *dev = hw->dev[port];
1100 struct skge_port *skge = netdev_priv(dev);
a1bc9b87 1101
501fb72d 1102 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
a1bc9b87 1103
a1bc9b87
SH		 1104 if (netif_carrier_ok(dev))
1105 skge_link_down(skge);
1106}
1107
2cd8e5d3 1108static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 1109{
1110 int i;
baef58b1 1111
6b0c1480 1112 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 1113 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 1114
64f6b64d
SH		 1115 if (hw->phy_type == SK_PHY_XMAC)
1116 goto ready;
1117
89bf5f23 1118 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 1119 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 1120 goto ready;
0781191c 1121 udelay(1);
baef58b1
SH		 1122 }
1123
2cd8e5d3 1124 return -ETIMEDOUT;
89bf5f23 1125 ready:
2cd8e5d3 1126 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 1127
2cd8e5d3
SH		 1128 return 0;
1129}
1130
1131static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1132{
1133 u16 v = 0;
1134 if (__xm_phy_read(hw, port, reg, &v))
1135 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1136 hw->dev[port]->name);
baef58b1
SH		 1137 return v;
1138}
1139
2cd8e5d3 1140static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1141{
1142 int i;
1143
6b0c1480 1144 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 1145 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 1146 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 1147 goto ready;
89bf5f23 1148 udelay(1);
baef58b1 1149 }
2cd8e5d3 1150 return -EIO;
baef58b1
SH		 1151
1152 ready:
6b0c1480 1153 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 1154 for (i = 0; i < PHY_RETRIES; i++) {
1155 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1156 return 0;
1157 udelay(1);
1158 }
1159 return -ETIMEDOUT;
baef58b1
SH		 1160}
1161
1162static void genesis_init(struct skge_hw *hw)
1163{
1164 /* set blink source counter */
1165 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1166 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1167
1168 /* configure mac arbiter */
1169 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1170
1171 /* configure mac arbiter timeout values */
1172 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1173 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1174 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1175 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1176
1177 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1178 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1179 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1180 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1181
1182 /* configure packet arbiter timeout */
1183 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1184 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1185 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1186 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1187 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1188}
1189
1190static void genesis_reset(struct skge_hw *hw, int port)
1191{
45bada65 1192 const u8 zero[8] = { 0 };
21d7f677 1193 u32 reg;
baef58b1 1194
46a60f2d
SH		 1195 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1196
baef58b1 1197 /* reset the statistics module */
6b0c1480 1198 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
501fb72d 1199 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
6b0c1480
SH		 1200 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1201 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1202 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1203
89bf5f23 1204 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1205 if (hw->phy_type == SK_PHY_BCOM)
1206 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1207
45bada65 1208 xm_outhash(hw, port, XM_HSM, zero);
21d7f677
SH		 1209
1210 /* Flush TX and RX fifo */
1211 reg = xm_read32(hw, port, XM_MODE);
1212 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1213 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
baef58b1
SH		 1214}
1215
1216
45bada65
SH		 1217/* Convert mode to MII values */
1218static const u16 phy_pause_map[] = {
1219 [FLOW_MODE_NONE] = 0,
1220 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1221 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1222 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1223};
1224
4b67be99
SH		 1225/* special defines for FIBER (88E1011S only) */
1226static const u16 fiber_pause_map[] = {
1227 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1228 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1229 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1230 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1231};
1232
45bada65
SH		 1233
1234/* Check status of Broadcom phy link */
1235static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1236{
45bada65
SH		 1237 struct net_device *dev = hw->dev[port];
1238 struct skge_port *skge = netdev_priv(dev);
1239 u16 status;
1240
1241 /* read twice because of latch */
501fb72d 1242 xm_phy_read(hw, port, PHY_BCOM_STAT);
45bada65
SH		 1243 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1244
45bada65 1245 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1246 xm_link_down(hw, port);
64f6b64d
SH		 1247 return;
1248 }
45bada65 1249
64f6b64d
SH		 1250 if (skge->autoneg == AUTONEG_ENABLE) {
1251 u16 lpa, aux;
45bada65 1252
64f6b64d
SH		 1253 if (!(status & PHY_ST_AN_OVER))
1254 return;
45bada65 1255
64f6b64d
SH		 1256 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1257 if (lpa & PHY_B_AN_RF) {
1258 printk(KERN_NOTICE PFX "%s: remote fault\n",
1259 dev->name);
1260 return;
1261 }
45bada65 1262
64f6b64d
SH		 1263 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1264
1265 /* Check Duplex mismatch */
1266 switch (aux & PHY_B_AS_AN_RES_MSK) {
1267 case PHY_B_RES_1000FD:
1268 skge->duplex = DUPLEX_FULL;
1269 break;
1270 case PHY_B_RES_1000HD:
1271 skge->duplex = DUPLEX_HALF;
1272 break;
1273 default:
1274 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1275 dev->name);
1276 return;
45bada65
SH		 1277 }
1278
64f6b64d
SH		 1279 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1280 switch (aux & PHY_B_AS_PAUSE_MSK) {
1281 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1282 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1283 break;
1284 case PHY_B_AS_PRR:
5d5c8e03 1285 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1286 break;
1287 case PHY_B_AS_PRT:
5d5c8e03 1288 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1289 break;
1290 default:
5d5c8e03 1291 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1292 }
1293 skge->speed = SPEED_1000;
45bada65 1294 }
64f6b64d
SH		 1295
1296 if (!netif_carrier_ok(dev))
1297 genesis_link_up(skge);
45bada65
SH		 1298}
1299
1300/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1301 * Phy on for 100 or 10Mbit operation
1302 */
64f6b64d 1303static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1304{
1305 struct skge_hw *hw = skge->hw;
1306 int port = skge->port;
baef58b1 1307 int i;
45bada65 1308 u16 id1, r, ext, ctl;
baef58b1
SH		 1309
1310 /* magic workaround patterns for Broadcom */
1311 static const struct {
1312 u16 reg;
1313 u16 val;
1314 } A1hack[] = {
1315 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1316 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1317 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1318 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1319 }, C0hack[] = {
1320 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1321 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1322 };
1323
45bada65
SH		 1324 /* read Id from external PHY (all have the same address) */
1325 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1326
1327 /* Optimize MDIO transfer by suppressing preamble. */
1328 r = xm_read16(hw, port, XM_MMU_CMD);
1329 r |= XM_MMU_NO_PRE;
1330 xm_write16(hw, port, XM_MMU_CMD,r);
1331
2c668514 1332 switch (id1) {
45bada65
SH		 1333 case PHY_BCOM_ID1_C0:
1334 /*
1335 * Workaround BCOM Errata for the C0 type.
1336 * Write magic patterns to reserved registers.
1337 */
1338 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1339 xm_phy_write(hw, port,
1340 C0hack[i].reg, C0hack[i].val);
1341
1342 break;
1343 case PHY_BCOM_ID1_A1:
1344 /*
1345 * Workaround BCOM Errata for the A1 type.
1346 * Write magic patterns to reserved registers.
1347 */
1348 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1349 xm_phy_write(hw, port,
1350 A1hack[i].reg, A1hack[i].val);
1351 break;
1352 }
1353
1354 /*
1355 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1356 * Disable Power Management after reset.
1357 */
1358 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1359 r |= PHY_B_AC_DIS_PM;
1360 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1361
1362 /* Dummy read */
1363 xm_read16(hw, port, XM_ISRC);
1364
1365 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1366 ctl = PHY_CT_SP1000; /* always 1000mbit */
1367
1368 if (skge->autoneg == AUTONEG_ENABLE) {
1369 /*
1370 * Workaround BCOM Errata #1 for the C5 type.
1371 * 1000Base-T Link Acquisition Failure in Slave Mode
1372 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1373 */
1374 u16 adv = PHY_B_1000C_RD;
1375 if (skge->advertising & ADVERTISED_1000baseT_Half)
1376 adv |= PHY_B_1000C_AHD;
1377 if (skge->advertising & ADVERTISED_1000baseT_Full)
1378 adv |= PHY_B_1000C_AFD;
1379 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1380
1381 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1382 } else {
1383 if (skge->duplex == DUPLEX_FULL)
1384 ctl |= PHY_CT_DUP_MD;
1385 /* Force to slave */
1386 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1387 }
1388
1389 /* Set autonegotiation pause parameters */
1390 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1391 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1392
1393 /* Handle Jumbo frames */
64f6b64d 1394 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1395 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1396 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1397
1398 ext |= PHY_B_PEC_HIGH_LA;
1399
1400 }
1401
1402 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1403 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1404
8f3f8193 1405 /* Use link status change interrupt */
45bada65 1406 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1407}
45bada65 1408
64f6b64d
SH		 1409static void xm_phy_init(struct skge_port *skge)
1410{
1411 struct skge_hw *hw = skge->hw;
1412 int port = skge->port;
1413 u16 ctrl = 0;
1414
1415 if (skge->autoneg == AUTONEG_ENABLE) {
1416 if (skge->advertising & ADVERTISED_1000baseT_Half)
1417 ctrl |= PHY_X_AN_HD;
1418 if (skge->advertising & ADVERTISED_1000baseT_Full)
1419 ctrl |= PHY_X_AN_FD;
1420
4b67be99 1421 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1422
1423 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1424
1425 /* Restart Auto-negotiation */
1426 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1427 } else {
1428 /* Set DuplexMode in Config register */
1429 if (skge->duplex == DUPLEX_FULL)
1430 ctrl |= PHY_CT_DUP_MD;
1431 /*
1432 * Do NOT enable Auto-negotiation here. This would hold
1433 * the link down because no IDLEs are transmitted
1434 */
1435 }
1436
1437 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1438
1439 /* Poll PHY for status changes */
9cbe330f 1440 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
64f6b64d
SH		 1441}
1442
501fb72d 1443static int xm_check_link(struct net_device *dev)
64f6b64d
SH		 1444{
1445 struct skge_port *skge = netdev_priv(dev);
1446 struct skge_hw *hw = skge->hw;
1447 int port = skge->port;
1448 u16 status;
1449
1450 /* read twice because of latch */
501fb72d 1451 xm_phy_read(hw, port, PHY_XMAC_STAT);
64f6b64d
SH		 1452 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1453
1454 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1455 xm_link_down(hw, port);
501fb72d 1456 return 0;
64f6b64d
SH		 1457 }
1458
1459 if (skge->autoneg == AUTONEG_ENABLE) {
1460 u16 lpa, res;
1461
1462 if (!(status & PHY_ST_AN_OVER))
501fb72d 1463 return 0;
64f6b64d
SH		 1464
1465 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1466 if (lpa & PHY_B_AN_RF) {
1467 printk(KERN_NOTICE PFX "%s: remote fault\n",
1468 dev->name);
501fb72d 1469 return 0;
64f6b64d
SH		 1470 }
1471
1472 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1473
1474 /* Check Duplex mismatch */
1475 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1476 case PHY_X_RS_FD:
1477 skge->duplex = DUPLEX_FULL;
1478 break;
1479 case PHY_X_RS_HD:
1480 skge->duplex = DUPLEX_HALF;
1481 break;
1482 default:
1483 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1484 dev->name);
501fb72d 1485 return 0;
64f6b64d
SH		 1486 }
1487
1488 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1489 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1490 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1491 (lpa & PHY_X_P_SYM_MD))
1492 skge->flow_status = FLOW_STAT_SYMMETRIC;
1493 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1494 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1495 /* Enable PAUSE receive, disable PAUSE transmit */
1496 skge->flow_status = FLOW_STAT_REM_SEND;
1497 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1498 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1499 /* Disable PAUSE receive, enable PAUSE transmit */
1500 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1501 else
5d5c8e03 1502 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1503
1504 skge->speed = SPEED_1000;
1505 }
1506
1507 if (!netif_carrier_ok(dev))
1508 genesis_link_up(skge);
501fb72d 1509 return 1;
64f6b64d
SH		 1510}
1511
1512/* Poll to check for link coming up.
501fb72d 1513 *
64f6b64d 1514 * Since internal PHY is wired to a level triggered pin, can't
501fb72d
SH		 1515 * get an interrupt when carrier is detected, need to poll for
1516 * link coming up.
64f6b64d 1517 */
9cbe330f 1518static void xm_link_timer(unsigned long arg)
64f6b64d 1519{
9cbe330f 1520 struct skge_port *skge = (struct skge_port *) arg;
c4028958 1521 struct net_device *dev = skge->netdev;
64f6b64d
SH		 1522 struct skge_hw *hw = skge->hw;
1523 int port = skge->port;
501fb72d
SH		 1524 int i;
1525 unsigned long flags;
64f6b64d
SH		 1526
1527 if (!netif_running(dev))
1528 return;
1529
501fb72d
SH		 1530 spin_lock_irqsave(&hw->phy_lock, flags);
1531
1532 /*
1533 * Verify that the link by checking GPIO register three times.
1534 * This pin has the signal from the link_sync pin connected to it.
1535 */
1536 for (i = 0; i < 3; i++) {
1537 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1538 goto link_down;
1539 }
1540
1541 /* Re-enable interrupt to detect link down */
1542 if (xm_check_link(dev)) {
1543 u16 msk = xm_read16(hw, port, XM_IMSK);
1544 msk &= ~XM_IS_INP_ASS;
1545 xm_write16(hw, port, XM_IMSK, msk);
64f6b64d 1546 xm_read16(hw, port, XM_ISRC);
64f6b64d 1547 } else {
501fb72d
SH		 1548link_down:
1549 mod_timer(&skge->link_timer,
1550 round_jiffies(jiffies + LINK_HZ));
64f6b64d 1551 }
501fb72d 1552 spin_unlock_irqrestore(&hw->phy_lock, flags);
45bada65
SH		 1553}
1554
1555static void genesis_mac_init(struct skge_hw *hw, int port)
1556{
1557 struct net_device *dev = hw->dev[port];
1558 struct skge_port *skge = netdev_priv(dev);
1559 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1560 int i;
1561 u32 r;
1562 const u8 zero[6] = { 0 };
1563
0781191c
SH		 1564 for (i = 0; i < 10; i++) {
1565 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1566 MFF_SET_MAC_RST);
1567 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1568 goto reset_ok;
1569 udelay(1);
1570 }
baef58b1 1571
0781191c
SH		 1572 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1573
1574 reset_ok:
baef58b1 1575 /* Unreset the XMAC. */
6b0c1480 1576 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1577
1578 /*
1579 * Perform additional initialization for external PHYs,
1580 * namely for the 1000baseTX cards that use the XMAC's
1581 * GMII mode.
1582 */
64f6b64d
SH		 1583 if (hw->phy_type != SK_PHY_XMAC) {
1584 /* Take external Phy out of reset */
1585 r = skge_read32(hw, B2_GP_IO);
1586 if (port == 0)
1587 r |= GP_DIR_0|GP_IO_0;
1588 else
1589 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1590
64f6b64d 1591 skge_write32(hw, B2_GP_IO, r);
0781191c 1592
64f6b64d
SH		 1593 /* Enable GMII interface */
1594 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1595 }
89bf5f23 1596
89bf5f23 1597
64f6b64d
SH		 1598 switch(hw->phy_type) {
1599 case SK_PHY_XMAC:
1600 xm_phy_init(skge);
1601 break;
1602 case SK_PHY_BCOM:
1603 bcom_phy_init(skge);
1604 bcom_check_link(hw, port);
1605 }
89bf5f23 1606
45bada65
SH		 1607 /* Set Station Address */
1608 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1609
45bada65
SH		 1610 /* We don't use match addresses so clear */
1611 for (i = 1; i < 16; i++)
1612 xm_outaddr(hw, port, XM_EXM(i), zero);
1613
0781191c
SH		 1614 /* Clear MIB counters */
1615 xm_write16(hw, port, XM_STAT_CMD,
1616 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1617 /* Clear two times according to Errata #3 */
1618 xm_write16(hw, port, XM_STAT_CMD,
1619 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1620
45bada65
SH		 1621 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1622 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1623
1624 /* We don't need the FCS appended to the packet. */
1625 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1626 if (jumbo)
1627 r |= XM_RX_BIG_PK_OK;
89bf5f23 1628
45bada65 1629 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1630 /*
45bada65
SH		 1631 * If in manual half duplex mode the other side might be in
1632 * full duplex mode, so ignore if a carrier extension is not seen
1633 * on frames received
89bf5f23 1634 */
45bada65 1635 r |= XM_RX_DIS_CEXT;
baef58b1 1636 }
45bada65 1637 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1638
baef58b1 1639 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1640 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1641
485982a9
SH		 1642 /* Increase threshold for jumbo frames on dual port */
1643 if (hw->ports > 1 && jumbo)
1644 xm_write16(hw, port, XM_TX_THR, 1020);
1645 else
1646 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1647
1648 /*
1649 * Enable the reception of all error frames. This is is
1650 * a necessary evil due to the design of the XMAC. The
1651 * XMAC's receive FIFO is only 8K in size, however jumbo
1652 * frames can be up to 9000 bytes in length. When bad
1653 * frame filtering is enabled, the XMAC's RX FIFO operates
1654 * in 'store and forward' mode. For this to work, the
1655 * entire frame has to fit into the FIFO, but that means
1656 * that jumbo frames larger than 8192 bytes will be
1657 * truncated. Disabling all bad frame filtering causes
1658 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1659 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1660 * RX FIFO as soon as the FIFO threshold is reached.
1661 */
45bada65 1662 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1663
baef58b1
SH		 1664
1665 /*
45bada65
SH		 1666 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1667 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1668 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1669 */
45bada65
SH		 1670 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1671
1672 /*
1673 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1674 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1675 * and 'Octets Tx OK Hi Cnt Ov'.
1676 */
1677 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1678
1679 /* Configure MAC arbiter */
1680 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1681
1682 /* configure timeout values */
1683 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1684 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1685 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1686 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1687
1688 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1689 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1690 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1691 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1692
1693 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1694 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1695 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1696 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1697
1698 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1699 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1700 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1701 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1702
45bada65 1703 if (jumbo) {
baef58b1 1704 /* Enable frame flushing if jumbo frames used */
6b0c1480 1705 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1706 } else {
1707 /* enable timeout timers if normal frames */
1708 skge_write16(hw, B3_PA_CTRL,
45bada65 1709 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1710 }
baef58b1
SH		 1711}
1712
1713static void genesis_stop(struct skge_port *skge)
1714{
1715 struct skge_hw *hw = skge->hw;
1716 int port = skge->port;
799b21d2 1717 unsigned retries = 1000;
21d7f677
SH		 1718 u16 cmd;
1719
1720 /* Disable Tx and Rx */
1721 cmd = xm_read16(hw, port, XM_MMU_CMD);
1722 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1723 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1724
46a60f2d
SH		 1725 genesis_reset(hw, port);
1726
baef58b1
SH		 1727 /* Clear Tx packet arbiter timeout IRQ */
1728 skge_write16(hw, B3_PA_CTRL,
1729 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1730
baef58b1 1731 /* Reset the MAC */
799b21d2
SH		 1732 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1733 do {
1734 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1735 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1736 break;
1737 } while (--retries > 0);
baef58b1
SH		 1738
1739 /* For external PHYs there must be special handling */
64f6b64d 1740 if (hw->phy_type != SK_PHY_XMAC) {
799b21d2 1741 u32 reg = skge_read32(hw, B2_GP_IO);
64f6b64d
SH		 1742 if (port == 0) {
1743 reg |= GP_DIR_0;
1744 reg &= ~GP_IO_0;
1745 } else {
1746 reg |= GP_DIR_2;
1747 reg &= ~GP_IO_2;
1748 }
1749 skge_write32(hw, B2_GP_IO, reg);
1750 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1751 }
1752
6b0c1480
SH		 1753 xm_write16(hw, port, XM_MMU_CMD,
1754 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1755 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1756
6b0c1480 1757 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1758}
1759
1760
1761static void genesis_get_stats(struct skge_port *skge, u64 *data)
1762{
1763 struct skge_hw *hw = skge->hw;
1764 int port = skge->port;
1765 int i;
1766 unsigned long timeout = jiffies + HZ;
1767
6b0c1480 1768 xm_write16(hw, port,
baef58b1
SH		 1769 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1770
1771 /* wait for update to complete */
6b0c1480 1772 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1773 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1774 if (time_after(jiffies, timeout))
1775 break;
1776 udelay(10);
1777 }
1778
1779 /* special case for 64 bit octet counter */
6b0c1480
SH		 1780 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1781 | xm_read32(hw, port, XM_TXO_OK_LO);
1782 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1783 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1784
1785 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1786 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1787}
1788
1789static void genesis_mac_intr(struct skge_hw *hw, int port)
1790{
da00772f
SH		 1791 struct net_device *dev = hw->dev[port];
1792 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1793 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1794
7e676d91
SH		 1795 if (netif_msg_intr(skge))
1796 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
da00772f 1797 dev->name, status);
baef58b1 1798
501fb72d
SH		 1799 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1800 xm_link_down(hw, port);
1801 mod_timer(&skge->link_timer, jiffies + 1);
1802 }
a1bc9b87 1803
baef58b1 1804 if (status & XM_IS_TXF_UR) {
6b0c1480 1805 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
da00772f 1806 ++dev->stats.tx_fifo_errors;
baef58b1 1807 }
baef58b1
SH		 1808}
1809
baef58b1
SH		 1810static void genesis_link_up(struct skge_port *skge)
1811{
1812 struct skge_hw *hw = skge->hw;
1813 int port = skge->port;
a1bc9b87 1814 u16 cmd, msk;
64f6b64d 1815 u32 mode;
baef58b1 1816
6b0c1480 1817 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1818
1819 /*
1820 * enabling pause frame reception is required for 1000BT
1821 * because the XMAC is not reset if the link is going down
1822 */
5d5c8e03
SH		 1823 if (skge->flow_status == FLOW_STAT_NONE ||
1824 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1825 /* Disable Pause Frame Reception */
baef58b1
SH		 1826 cmd |= XM_MMU_IGN_PF;
1827 else
1828 /* Enable Pause Frame Reception */
1829 cmd &= ~XM_MMU_IGN_PF;
1830
6b0c1480 1831 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1832
6b0c1480 1833 mode = xm_read32(hw, port, XM_MODE);
5d5c8e03
SH		 1834 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1835 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1836 /*
1837 * Configure Pause Frame Generation
1838 * Use internal and external Pause Frame Generation.
1839 * Sending pause frames is edge triggered.
1840 * Send a Pause frame with the maximum pause time if
1841 * internal oder external FIFO full condition occurs.
1842 * Send a zero pause time frame to re-start transmission.
1843 */
1844 /* XM_PAUSE_DA = '010000C28001' (default) */
1845 /* XM_MAC_PTIME = 0xffff (maximum) */
1846 /* remember this value is defined in big endian (!) */
6b0c1480 1847 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1848
1849 mode |= XM_PAUSE_MODE;
6b0c1480 1850 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1851 } else {
1852 /*
1853 * disable pause frame generation is required for 1000BT
1854 * because the XMAC is not reset if the link is going down
1855 */
1856 /* Disable Pause Mode in Mode Register */
1857 mode &= ~XM_PAUSE_MODE;
1858
6b0c1480 1859 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1860 }
1861
6b0c1480 1862 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87 1863
d08b9bdf 1864 /* Turn on detection of Tx underrun */
501fb72d 1865 msk = xm_read16(hw, port, XM_IMSK);
d08b9bdf 1866 msk &= ~XM_IS_TXF_UR;
a1bc9b87 1867 xm_write16(hw, port, XM_IMSK, msk);
501fb72d 1868
6b0c1480 1869 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1870
1871 /* get MMU Command Reg. */
6b0c1480 1872 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1873 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1874 cmd |= XM_MMU_GMII_FD;
1875
89bf5f23
SH		 1876 /*
1877 * Workaround BCOM Errata (#10523) for all BCom Phys
1878 * Enable Power Management after link up
1879 */
64f6b64d
SH		 1880 if (hw->phy_type == SK_PHY_BCOM) {
1881 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1882 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1883 & ~PHY_B_AC_DIS_PM);
1884 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1885 }
baef58b1
SH		 1886
1887 /* enable Rx/Tx */
6b0c1480 1888 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1889 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1890 skge_link_up(skge);
1891}
1892
1893
45bada65 1894static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1895{
1896 struct skge_hw *hw = skge->hw;
1897 int port = skge->port;
45bada65
SH		 1898 u16 isrc;
1899
1900 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1901 if (netif_msg_intr(skge))
1902 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1903 skge->netdev->name, isrc);
baef58b1 1904
45bada65
SH		 1905 if (isrc & PHY_B_IS_PSE)
1906 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1907 hw->dev[port]->name);
baef58b1
SH		 1908
1909 /* Workaround BCom Errata:
1910 * enable and disable loopback mode if "NO HCD" occurs.
1911 */
45bada65 1912 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1913 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1914 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1915 ctrl | PHY_CT_LOOP);
6b0c1480 1916 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1917 ctrl & ~PHY_CT_LOOP);
1918 }
1919
45bada65
SH		 1920 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1921 bcom_check_link(hw, port);
baef58b1 1922
baef58b1
SH		 1923}
1924
2cd8e5d3
SH		 1925static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1926{
1927 int i;
1928
1929 gma_write16(hw, port, GM_SMI_DATA, val);
1930 gma_write16(hw, port, GM_SMI_CTRL,
1931 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1932 for (i = 0; i < PHY_RETRIES; i++) {
1933 udelay(1);
1934
1935 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1936 return 0;
1937 }
1938
1939 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1940 hw->dev[port]->name);
1941 return -EIO;
1942}
1943
1944static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1945{
1946 int i;
1947
1948 gma_write16(hw, port, GM_SMI_CTRL,
1949 GM_SMI_CT_PHY_AD(hw->phy_addr)
1950 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1951
1952 for (i = 0; i < PHY_RETRIES; i++) {
1953 udelay(1);
1954 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1955 goto ready;
1956 }
1957
1958 return -ETIMEDOUT;
1959 ready:
1960 *val = gma_read16(hw, port, GM_SMI_DATA);
1961 return 0;
1962}
1963
1964static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1965{
1966 u16 v = 0;
1967 if (__gm_phy_read(hw, port, reg, &v))
1968 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1969 hw->dev[port]->name);
1970 return v;
1971}
1972
8f3f8193 1973/* Marvell Phy Initialization */
baef58b1
SH		 1974static void yukon_init(struct skge_hw *hw, int port)
1975{
1976 struct skge_port *skge = netdev_priv(hw->dev[port]);
1977 u16 ctrl, ct1000, adv;
baef58b1 1978
baef58b1 1979 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1980 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1981
1982 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1983 PHY_M_EC_MAC_S_MSK);
1984 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1985
c506a509 1986 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1987
6b0c1480 1988 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1989 }
1990
6b0c1480 1991 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1992 if (skge->autoneg == AUTONEG_DISABLE)
1993 ctrl &= ~PHY_CT_ANE;
1994
1995 ctrl |= PHY_CT_RESET;
6b0c1480 1996 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1997
1998 ctrl = 0;
1999 ct1000 = 0;
b18f2091 2000 adv = PHY_AN_CSMA;
baef58b1
SH		 2001
2002 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 2003 if (hw->copper) {
baef58b1
SH		 2004 if (skge->advertising & ADVERTISED_1000baseT_Full)
2005 ct1000 |= PHY_M_1000C_AFD;
2006 if (skge->advertising & ADVERTISED_1000baseT_Half)
2007 ct1000 |= PHY_M_1000C_AHD;
2008 if (skge->advertising & ADVERTISED_100baseT_Full)
2009 adv |= PHY_M_AN_100_FD;
2010 if (skge->advertising & ADVERTISED_100baseT_Half)
2011 adv |= PHY_M_AN_100_HD;
2012 if (skge->advertising & ADVERTISED_10baseT_Full)
2013 adv |= PHY_M_AN_10_FD;
2014 if (skge->advertising & ADVERTISED_10baseT_Half)
2015 adv |= PHY_M_AN_10_HD;
baef58b1 2016
4b67be99
SH		 2017 /* Set Flow-control capabilities */
2018 adv |= phy_pause_map[skge->flow_control];
2019 } else {
2020 if (skge->advertising & ADVERTISED_1000baseT_Full)
2021 adv |= PHY_M_AN_1000X_AFD;
2022 if (skge->advertising & ADVERTISED_1000baseT_Half)
2023 adv |= PHY_M_AN_1000X_AHD;
2024
2025 adv |= fiber_pause_map[skge->flow_control];
2026 }
45bada65 2027
baef58b1
SH		 2028 /* Restart Auto-negotiation */
2029 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2030 } else {
2031 /* forced speed/duplex settings */
2032 ct1000 = PHY_M_1000C_MSE;
2033
2034 if (skge->duplex == DUPLEX_FULL)
2035 ctrl |= PHY_CT_DUP_MD;
2036
2037 switch (skge->speed) {
2038 case SPEED_1000:
2039 ctrl |= PHY_CT_SP1000;
2040 break;
2041 case SPEED_100:
2042 ctrl |= PHY_CT_SP100;
2043 break;
2044 }
2045
2046 ctrl |= PHY_CT_RESET;
2047 }
2048
c506a509 2049 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 2050
6b0c1480
SH		 2051 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2052 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 2053
baef58b1
SH		 2054 /* Enable phy interrupt on autonegotiation complete (or link up) */
2055 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 2056 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 2057 else
4cde06ed 2058 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2059}
2060
2061static void yukon_reset(struct skge_hw *hw, int port)
2062{
6b0c1480
SH		 2063 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2064 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2065 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2066 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2067 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 2068
6b0c1480
SH		 2069 gma_write16(hw, port, GM_RX_CTRL,
2070 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 2071 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2072}
2073
c8868611
SH		 2074/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2075static int is_yukon_lite_a0(struct skge_hw *hw)
2076{
2077 u32 reg;
2078 int ret;
2079
2080 if (hw->chip_id != CHIP_ID_YUKON)
2081 return 0;
2082
2083 reg = skge_read32(hw, B2_FAR);
2084 skge_write8(hw, B2_FAR + 3, 0xff);
2085 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2086 skge_write32(hw, B2_FAR, reg);
2087 return ret;
2088}
2089
baef58b1
SH		 2090static void yukon_mac_init(struct skge_hw *hw, int port)
2091{
2092 struct skge_port *skge = netdev_priv(hw->dev[port]);
2093 int i;
2094 u32 reg;
2095 const u8 *addr = hw->dev[port]->dev_addr;
2096
2097 /* WA code for COMA mode -- set PHY reset */
2098 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2099 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2100 reg = skge_read32(hw, B2_GP_IO);
2101 reg |= GP_DIR_9 | GP_IO_9;
2102 skge_write32(hw, B2_GP_IO, reg);
2103 }
baef58b1
SH		 2104
2105 /* hard reset */
6b0c1480
SH		 2106 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2107 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2108
2109 /* WA code for COMA mode -- clear PHY reset */
2110 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2111 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2112 reg = skge_read32(hw, B2_GP_IO);
2113 reg |= GP_DIR_9;
2114 reg &= ~GP_IO_9;
2115 skge_write32(hw, B2_GP_IO, reg);
2116 }
baef58b1
SH		 2117
2118 /* Set hardware config mode */
2119 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2120 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 2121 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 2122
2123 /* Clear GMC reset */
6b0c1480
SH		 2124 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2125 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2126 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 2127
baef58b1
SH		 2128 if (skge->autoneg == AUTONEG_DISABLE) {
2129 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 2130 gma_write16(hw, port, GM_GP_CTRL,
2131 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 2132
2133 switch (skge->speed) {
2134 case SPEED_1000:
564f9abb 2135 reg &= ~GM_GPCR_SPEED_100;
baef58b1 2136 reg |= GM_GPCR_SPEED_1000;
564f9abb 2137 break;
baef58b1 2138 case SPEED_100:
564f9abb 2139 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 2140 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 2141 break;
2142 case SPEED_10:
2143 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2144 break;
baef58b1
SH		 2145 }
2146
2147 if (skge->duplex == DUPLEX_FULL)
2148 reg |= GM_GPCR_DUP_FULL;
2149 } else
2150 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 2151
baef58b1
SH		 2152 switch (skge->flow_control) {
2153 case FLOW_MODE_NONE:
6b0c1480 2154 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 2155 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2156 break;
2157 case FLOW_MODE_LOC_SEND:
2158 /* disable Rx flow-control */
2159 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 2160 break;
2161 case FLOW_MODE_SYMMETRIC:
2162 case FLOW_MODE_SYM_OR_REM:
2163 /* enable Tx & Rx flow-control */
2164 break;
baef58b1
SH		 2165 }
2166
6b0c1480 2167 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 2168 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2169
baef58b1 2170 yukon_init(hw, port);
baef58b1
SH		 2171
2172 /* MIB clear */
6b0c1480
SH		 2173 reg = gma_read16(hw, port, GM_PHY_ADDR);
2174 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 2175
2176 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 2177 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2178 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 2179
2180 /* transmit control */
6b0c1480 2181 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 2182
2183 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 2184 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 2185 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2186
2187 /* transmit flow control */
6b0c1480 2188 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 2189
2190 /* transmit parameter */
6b0c1480 2191 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 2192 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2193 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2194 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2195
44c7fcce
SH		 2196 /* configure the Serial Mode Register */
2197 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2198 | GM_SMOD_VLAN_ENA
2199 | IPG_DATA_VAL(IPG_DATA_DEF);
2200
2201 if (hw->dev[port]->mtu > ETH_DATA_LEN)
baef58b1
SH		 2202 reg |= GM_SMOD_JUMBO_ENA;
2203
6b0c1480 2204 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2205
2206 /* physical address: used for pause frames */
6b0c1480 2207 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2208 /* virtual address for data */
6b0c1480 2209 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2210
2211 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2212 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2213 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2214 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2215
2216 /* Initialize Mac Fifo */
2217
2218 /* Configure Rx MAC FIFO */
6b0c1480 2219 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2220 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2221
2222 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2223 if (is_yukon_lite_a0(hw))
baef58b1 2224 reg &= ~GMF_RX_F_FL_ON;
c8868611 2225
6b0c1480
SH		 2226 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2227 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2228 /*
2229 * because Pause Packet Truncation in GMAC is not working
2230 * we have to increase the Flush Threshold to 64 bytes
2231 * in order to flush pause packets in Rx FIFO on Yukon-1
2232 */
2233 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2234
2235 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2236 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2237 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2238}
2239
355ec572
SH		 2240/* Go into power down mode */
2241static void yukon_suspend(struct skge_hw *hw, int port)
2242{
2243 u16 ctrl;
2244
2245 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2246 ctrl |= PHY_M_PC_POL_R_DIS;
2247 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2248
2249 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2250 ctrl |= PHY_CT_RESET;
2251 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2252
2253 /* switch IEEE compatible power down mode on */
2254 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2255 ctrl |= PHY_CT_PDOWN;
2256 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2257}
2258
baef58b1
SH		 2259static void yukon_stop(struct skge_port *skge)
2260{
2261 struct skge_hw *hw = skge->hw;
2262 int port = skge->port;
2263
46a60f2d
SH		 2264 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2265 yukon_reset(hw, port);
baef58b1 2266
6b0c1480
SH		 2267 gma_write16(hw, port, GM_GP_CTRL,
2268 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2269 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2270 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2271
355ec572 2272 yukon_suspend(hw, port);
46a60f2d 2273
baef58b1 2274 /* set GPHY Control reset */
46a60f2d
SH		 2275 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2276 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2277}
2278
2279static void yukon_get_stats(struct skge_port *skge, u64 *data)
2280{
2281 struct skge_hw *hw = skge->hw;
2282 int port = skge->port;
2283 int i;
2284
6b0c1480
SH		 2285 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2286 | gma_read32(hw, port, GM_TXO_OK_LO);
2287 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2288 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2289
2290 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2291 data[i] = gma_read32(hw, port,
baef58b1
SH		 2292 skge_stats[i].gma_offset);
2293}
2294
2295static void yukon_mac_intr(struct skge_hw *hw, int port)
2296{
7e676d91
SH		 2297 struct net_device *dev = hw->dev[port];
2298 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2299 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2300
7e676d91
SH		 2301 if (netif_msg_intr(skge))
2302 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2303 dev->name, status);
2304
baef58b1 2305 if (status & GM_IS_RX_FF_OR) {
da00772f 2306 ++dev->stats.rx_fifo_errors;
d8a09943 2307 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2308 }
d8a09943 2309
baef58b1 2310 if (status & GM_IS_TX_FF_UR) {
da00772f 2311 ++dev->stats.tx_fifo_errors;
d8a09943 2312 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2313 }
2314
2315}
2316
2317static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2318{
95566065 2319 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2320 case PHY_M_PS_SPEED_1000:
2321 return SPEED_1000;
2322 case PHY_M_PS_SPEED_100:
2323 return SPEED_100;
2324 default:
2325 return SPEED_10;
2326 }
2327}
2328
2329static void yukon_link_up(struct skge_port *skge)
2330{
2331 struct skge_hw *hw = skge->hw;
2332 int port = skge->port;
2333 u16 reg;
2334
baef58b1 2335 /* Enable Transmit FIFO Underrun */
46a60f2d 2336 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2337
6b0c1480 2338 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2339 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2340 reg |= GM_GPCR_DUP_FULL;
2341
2342 /* enable Rx/Tx */
2343 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2344 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2345
4cde06ed 2346 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2347 skge_link_up(skge);
2348}
2349
2350static void yukon_link_down(struct skge_port *skge)
2351{
2352 struct skge_hw *hw = skge->hw;
2353 int port = skge->port;
d8a09943 2354 u16 ctrl;
baef58b1 2355
d8a09943
SH		 2356 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2357 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2358 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2359
5d5c8e03
SH		 2360 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2361 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2362 ctrl |= PHY_M_AN_ASP;
baef58b1 2363 /* restore Asymmetric Pause bit */
5d5c8e03 2364 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2365 }
2366
baef58b1
SH		 2367 skge_link_down(skge);
2368
2369 yukon_init(hw, port);
2370}
2371
2372static void yukon_phy_intr(struct skge_port *skge)
2373{
2374 struct skge_hw *hw = skge->hw;
2375 int port = skge->port;
2376 const char *reason = NULL;
2377 u16 istatus, phystat;
2378
6b0c1480
SH		 2379 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2380 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 2381
2382 if (netif_msg_intr(skge))
2383 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2384 skge->netdev->name, istatus, phystat);
baef58b1
SH		 2385
2386 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2387 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2388 & PHY_M_AN_RF) {
2389 reason = "remote fault";
2390 goto failed;
2391 }
2392
c506a509 2393 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2394 reason = "master/slave fault";
2395 goto failed;
2396 }
2397
2398 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2399 reason = "speed/duplex";
2400 goto failed;
2401 }
2402
2403 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2404 ? DUPLEX_FULL : DUPLEX_HALF;
2405 skge->speed = yukon_speed(hw, phystat);
2406
baef58b1
SH		 2407 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2408 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2409 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2410 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2411 break;
2412 case PHY_M_PS_RX_P_EN:
5d5c8e03 2413 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2414 break;
2415 case PHY_M_PS_TX_P_EN:
5d5c8e03 2416 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2417 break;
2418 default:
5d5c8e03 2419 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2420 }
2421
5d5c8e03 2422 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2423 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2424 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2425 else
6b0c1480 2426 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2427 yukon_link_up(skge);
2428 return;
2429 }
2430
2431 if (istatus & PHY_M_IS_LSP_CHANGE)
2432 skge->speed = yukon_speed(hw, phystat);
2433
2434 if (istatus & PHY_M_IS_DUP_CHANGE)
2435 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2436 if (istatus & PHY_M_IS_LST_CHANGE) {
2437 if (phystat & PHY_M_PS_LINK_UP)
2438 yukon_link_up(skge);
2439 else
2440 yukon_link_down(skge);
2441 }
2442 return;
2443 failed:
2444 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2445 skge->netdev->name, reason);
2446
2447 /* XXX restart autonegotiation? */
2448}
2449
ee294dcd
SH		 2450static void skge_phy_reset(struct skge_port *skge)
2451{
2452 struct skge_hw *hw = skge->hw;
2453 int port = skge->port;
aae343d4 2454 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2455
2456 netif_stop_queue(skge->netdev);
2457 netif_carrier_off(skge->netdev);
2458
9cbe330f 2459 spin_lock_bh(&hw->phy_lock);
ee294dcd
SH		 2460 if (hw->chip_id == CHIP_ID_GENESIS) {
2461 genesis_reset(hw, port);
2462 genesis_mac_init(hw, port);
2463 } else {
2464 yukon_reset(hw, port);
2465 yukon_init(hw, port);
2466 }
9cbe330f 2467 spin_unlock_bh(&hw->phy_lock);
75814090 2468
f80d032b 2469 skge_set_multicast(dev);
ee294dcd
SH		 2470}
2471
2cd8e5d3
SH		 2472/* Basic MII support */
2473static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2474{
2475 struct mii_ioctl_data *data = if_mii(ifr);
2476 struct skge_port *skge = netdev_priv(dev);
2477 struct skge_hw *hw = skge->hw;
2478 int err = -EOPNOTSUPP;
2479
2480 if (!netif_running(dev))
2481 return -ENODEV; /* Phy still in reset */
2482
2483 switch(cmd) {
2484 case SIOCGMIIPHY:
2485 data->phy_id = hw->phy_addr;
2486
2487 /* fallthru */
2488 case SIOCGMIIREG: {
2489 u16 val = 0;
9cbe330f 2490 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2491 if (hw->chip_id == CHIP_ID_GENESIS)
2492 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2493 else
2494 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
9cbe330f 2495 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2496 data->val_out = val;
2497 break;
2498 }
2499
2500 case SIOCSMIIREG:
9cbe330f 2501 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2502 if (hw->chip_id == CHIP_ID_GENESIS)
2503 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2504 data->val_in);
2505 else
2506 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2507 data->val_in);
9cbe330f 2508 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2509 break;
2510 }
2511 return err;
2512}
2513
279e1dab 2514static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
baef58b1
SH		 2515{
2516 u32 end;
2517
279e1dab
LT		 2518 start /= 8;
2519 len /= 8;
2520 end = start + len - 1;
baef58b1
SH		 2521
2522 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2523 skge_write32(hw, RB_ADDR(q, RB_START), start);
2524 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2525 skge_write32(hw, RB_ADDR(q, RB_RP), start);
279e1dab 2526 skge_write32(hw, RB_ADDR(q, RB_END), end);
baef58b1
SH		 2527
2528 if (q == Q_R1 || q == Q_R2) {
2529 /* Set thresholds on receive queue's */
279e1dab
LT		 2530 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2531 start + (2*len)/3);
2532 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2533 start + (len/3));
2534 } else {
2535 /* Enable store & forward on Tx queue's because
2536 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2537 */
baef58b1 2538 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
279e1dab 2539 }
baef58b1
SH		 2540
2541 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2542}
2543
2544/* Setup Bus Memory Interface */
2545static void skge_qset(struct skge_port *skge, u16 q,
2546 const struct skge_element *e)
2547{
2548 struct skge_hw *hw = skge->hw;
2549 u32 watermark = 0x600;
2550 u64 base = skge->dma + (e->desc - skge->mem);
2551
2552 /* optimization to reduce window on 32bit/33mhz */
2553 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2554 watermark /= 2;
2555
2556 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2557 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2558 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2559 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2560}
2561
2562static int skge_up(struct net_device *dev)
2563{
2564 struct skge_port *skge = netdev_priv(dev);
2565 struct skge_hw *hw = skge->hw;
2566 int port = skge->port;
279e1dab 2567 u32 chunk, ram_addr;
baef58b1
SH		 2568 size_t rx_size, tx_size;
2569 int err;
2570
fae87592
SH		 2571 if (!is_valid_ether_addr(dev->dev_addr))
2572 return -EINVAL;
2573
baef58b1
SH		 2574 if (netif_msg_ifup(skge))
2575 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2576
19a33d4e 2577 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2578 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2579 else
2580 skge->rx_buf_size = RX_BUF_SIZE;
2581
2582
baef58b1
SH		 2583 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2584 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2585 skge->mem_size = tx_size + rx_size;
2586 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2587 if (!skge->mem)
2588 return -ENOMEM;
2589
c3da1447
SH		 2590 BUG_ON(skge->dma & 7);
2591
2592 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
1479d13c 2593 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
c3da1447
SH		 2594 err = -EINVAL;
2595 goto free_pci_mem;
2596 }
2597
baef58b1
SH		 2598 memset(skge->mem, 0, skge->mem_size);
2599
203babb6
SH		 2600 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2601 if (err)
baef58b1
SH		 2602 goto free_pci_mem;
2603
c54f9765 2604 err = skge_rx_fill(dev);
19a33d4e 2605 if (err)
baef58b1
SH		 2606 goto free_rx_ring;
2607
203babb6
SH		 2608 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2609 skge->dma + rx_size);
2610 if (err)
baef58b1
SH		 2611 goto free_rx_ring;
2612
8f3f8193 2613 /* Initialize MAC */
9cbe330f 2614 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2615 if (hw->chip_id == CHIP_ID_GENESIS)
2616 genesis_mac_init(hw, port);
2617 else
2618 yukon_mac_init(hw, port);
9cbe330f 2619 spin_unlock_bh(&hw->phy_lock);
baef58b1 2620
29816d9a
SH		 2621 /* Configure RAMbuffers - equally between ports and tx/rx */
2622 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
279e1dab 2623 ram_addr = hw->ram_offset + 2 * chunk * port;
baef58b1 2624
279e1dab 2625 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
7fb7ac24 2626 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
279e1dab 2627
baef58b1 2628 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
279e1dab 2629 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
baef58b1
SH		 2630 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2631
2632 /* Start receiver BMU */
2633 wmb();
2634 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2635 skge_led(skge, LED_MODE_ON);
baef58b1 2636
4ebabfcb
SH		 2637 spin_lock_irq(&hw->hw_lock);
2638 hw->intr_mask |= portmask[port];
2639 skge_write32(hw, B0_IMSK, hw->intr_mask);
2640 spin_unlock_irq(&hw->hw_lock);
2641
bea3348e 2642 napi_enable(&skge->napi);
baef58b1
SH		 2643 return 0;
2644
2645 free_rx_ring:
2646 skge_rx_clean(skge);
2647 kfree(skge->rx_ring.start);
2648 free_pci_mem:
2649 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2650 skge->mem = NULL;
baef58b1
SH		 2651
2652 return err;
2653}
2654
60b24b51
SH		 2655/* stop receiver */
2656static void skge_rx_stop(struct skge_hw *hw, int port)
2657{
2658 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2659 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2660 RB_RST_SET|RB_DIS_OP_MD);
2661 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2662}
2663
baef58b1
SH		 2664static int skge_down(struct net_device *dev)
2665{
2666 struct skge_port *skge = netdev_priv(dev);
2667 struct skge_hw *hw = skge->hw;
2668 int port = skge->port;
2669
7731a4ea
SH		 2670 if (skge->mem == NULL)
2671 return 0;
2672
baef58b1
SH		 2673 if (netif_msg_ifdown(skge))
2674 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2675
d119b392 2676 netif_tx_disable(dev);
692412b3 2677
64f6b64d 2678 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
9cbe330f 2679 del_timer_sync(&skge->link_timer);
baef58b1 2680
bea3348e 2681 napi_disable(&skge->napi);
692412b3 2682 netif_carrier_off(dev);
4ebabfcb
SH		 2683
2684 spin_lock_irq(&hw->hw_lock);
2685 hw->intr_mask &= ~portmask[port];
2686 skge_write32(hw, B0_IMSK, hw->intr_mask);
2687 spin_unlock_irq(&hw->hw_lock);
2688
46a60f2d
SH		 2689 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2690 if (hw->chip_id == CHIP_ID_GENESIS)
2691 genesis_stop(skge);
2692 else
2693 yukon_stop(skge);
2694
baef58b1
SH		 2695 /* Stop transmitter */
2696 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2697 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2698 RB_RST_SET|RB_DIS_OP_MD);
2699
baef58b1
SH		 2700
2701 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2702 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2703 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2704
2705 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2706 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2707 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2708
2709 /* Reset PCI FIFO */
2710 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2711 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2712
2713 /* Reset the RAM Buffer async Tx queue */
2714 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
60b24b51
SH		 2715
2716 skge_rx_stop(hw, port);
baef58b1
SH		 2717
2718 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2719 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2720 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2721 } else {
6b0c1480
SH		 2722 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2723 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2724 }
2725
6abebb53 2726 skge_led(skge, LED_MODE_OFF);
baef58b1 2727
e3a1b99f 2728 netif_tx_lock_bh(dev);
513f533e 2729 skge_tx_clean(dev);
e3a1b99f
SH		 2730 netif_tx_unlock_bh(dev);
2731
baef58b1
SH		 2732 skge_rx_clean(skge);
2733
2734 kfree(skge->rx_ring.start);
2735 kfree(skge->tx_ring.start);
2736 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2737 skge->mem = NULL;
baef58b1
SH		 2738 return 0;
2739}
2740
29b4e886
SH		 2741static inline int skge_avail(const struct skge_ring *ring)
2742{
992c9623 2743 smp_mb();
29b4e886
SH		 2744 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2745 + (ring->to_clean - ring->to_use) - 1;
2746}
2747
61357325
SH		 2748static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2749 struct net_device *dev)
baef58b1
SH		 2750{
2751 struct skge_port *skge = netdev_priv(dev);
2752 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2753 struct skge_element *e;
2754 struct skge_tx_desc *td;
2755 int i;
2756 u32 control, len;
2757 u64 map;
baef58b1 2758
5b057c6b 2759 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2760 return NETDEV_TX_OK;
2761
513f533e 2762 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2763 return NETDEV_TX_BUSY;
baef58b1 2764
7c442fa1 2765 e = skge->tx_ring.to_use;
baef58b1 2766 td = e->desc;
7c442fa1 2767 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2768 e->skb = skb;
2769 len = skb_headlen(skb);
2770 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2771 pci_unmap_addr_set(e, mapaddr, map);
2772 pci_unmap_len_set(e, maplen, len);
2773
2774 td->dma_lo = map;
2775 td->dma_hi = map >> 32;
2776
84fa7933 2777 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 2778 const int offset = skb_transport_offset(skb);
baef58b1
SH		 2779
2780 /* This seems backwards, but it is what the sk98lin
2781 * does. Looks like hardware is wrong?
2782 */
8e95a202
JP		 2783 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2784 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2785 control = BMU_TCP_CHECK;
2786 else
2787 control = BMU_UDP_CHECK;
2788
2789 td->csum_offs = 0;
2790 td->csum_start = offset;
ff1dcadb 2791 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2792 } else
2793 control = BMU_CHECK;
2794
2795 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2796 control |= BMU_EOF| BMU_IRQ_EOF;
2797 else {
2798 struct skge_tx_desc *tf = td;
2799
2800 control |= BMU_STFWD;
2801 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2802 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2803
2804 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2805 frag->size, PCI_DMA_TODEVICE);
2806
2807 e = e->next;
7c442fa1 2808 e->skb = skb;
baef58b1 2809 tf = e->desc;
7c442fa1
SH		 2810 BUG_ON(tf->control & BMU_OWN);
2811
baef58b1
SH		 2812 tf->dma_lo = map;
2813 tf->dma_hi = (u64) map >> 32;
2814 pci_unmap_addr_set(e, mapaddr, map);
2815 pci_unmap_len_set(e, maplen, frag->size);
2816
2817 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2818 }
2819 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2820 }
2821 /* Make sure all the descriptors written */
2822 wmb();
2823 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2824 wmb();
2825
2826 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2827
7c442fa1 2828 if (unlikely(netif_msg_tx_queued(skge)))
0b2d7fea 2829 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
7c442fa1 2830 dev->name, e - skge->tx_ring.start, skb->len);
baef58b1 2831
7c442fa1 2832 skge->tx_ring.to_use = e->next;
992c9623
SH		 2833 smp_wmb();
2834
9db96479 2835 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
baef58b1
SH		 2836 pr_debug("%s: transmit queue full\n", dev->name);
2837 netif_stop_queue(dev);
2838 }
2839
baef58b1
SH		 2840 return NETDEV_TX_OK;
2841}
2842
7c442fa1
SH		 2843
2844/* Free resources associated with this reing element */
2845static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2846 u32 control)
866b4f3e
SH		 2847{
2848 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2849
7c442fa1
SH		 2850 /* skb header vs. fragment */
2851 if (control & BMU_STF)
866b4f3e 2852 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
7c442fa1
SH		 2853 pci_unmap_len(e, maplen),
2854 PCI_DMA_TODEVICE);
2855 else
2856 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2857 pci_unmap_len(e, maplen),
2858 PCI_DMA_TODEVICE);
866b4f3e 2859
7c442fa1
SH		 2860 if (control & BMU_EOF) {
2861 if (unlikely(netif_msg_tx_done(skge)))
2862 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2863 skge->netdev->name, e - skge->tx_ring.start);
866b4f3e 2864
513f533e 2865 dev_kfree_skb(e->skb);
baef58b1
SH		 2866 }
2867}
2868
7c442fa1 2869/* Free all buffers in transmit ring */
513f533e 2870static void skge_tx_clean(struct net_device *dev)
baef58b1 2871{
513f533e 2872 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2873 struct skge_element *e;
baef58b1 2874
7c442fa1
SH		 2875 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2876 struct skge_tx_desc *td = e->desc;
2877 skge_tx_free(skge, e, td->control);
2878 td->control = 0;
2879 }
2880
2881 skge->tx_ring.to_clean = e;
baef58b1
SH		 2882}
2883
2884static void skge_tx_timeout(struct net_device *dev)
2885{
2886 struct skge_port *skge = netdev_priv(dev);
2887
2888 if (netif_msg_timer(skge))
2889 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2890
2891 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2892 skge_tx_clean(dev);
d119b392 2893 netif_wake_queue(dev);
baef58b1
SH		 2894}
2895
2896static int skge_change_mtu(struct net_device *dev, int new_mtu)
2897{
7731a4ea 2898 int err;
baef58b1 2899
95566065 2900 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2901 return -EINVAL;
2902
7731a4ea
SH		 2903 if (!netif_running(dev)) {
2904 dev->mtu = new_mtu;
2905 return 0;
2906 }
2907
1a8098be 2908 skge_down(dev);
baef58b1 2909
19a33d4e 2910 dev->mtu = new_mtu;
7731a4ea 2911
1a8098be 2912 err = skge_up(dev);
7731a4ea
SH		 2913 if (err)
2914 dev_close(dev);
baef58b1
SH		 2915
2916 return err;
2917}
2918
c4cd29d2
SH		 2919static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2920
2921static void genesis_add_filter(u8 filter[8], const u8 *addr)
2922{
2923 u32 crc, bit;
2924
2925 crc = ether_crc_le(ETH_ALEN, addr);
2926 bit = ~crc & 0x3f;
2927 filter[bit/8] |= 1 << (bit%8);
2928}
2929
baef58b1
SH		 2930static void genesis_set_multicast(struct net_device *dev)
2931{
2932 struct skge_port *skge = netdev_priv(dev);
2933 struct skge_hw *hw = skge->hw;
2934 int port = skge->port;
2935 int i, count = dev->mc_count;
2936 struct dev_mc_list *list = dev->mc_list;
2937 u32 mode;
2938 u8 filter[8];
2939
6b0c1480 2940 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2941 mode |= XM_MD_ENA_HASH;
2942 if (dev->flags & IFF_PROMISC)
2943 mode |= XM_MD_ENA_PROM;
2944 else
2945 mode &= ~XM_MD_ENA_PROM;
2946
2947 if (dev->flags & IFF_ALLMULTI)
2948 memset(filter, 0xff, sizeof(filter));
2949 else {
2950 memset(filter, 0, sizeof(filter));
c4cd29d2 2951
8e95a202
JP		 2952 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2953 skge->flow_status == FLOW_STAT_SYMMETRIC)
c4cd29d2
SH		 2954 genesis_add_filter(filter, pause_mc_addr);
2955
2956 for (i = 0; list && i < count; i++, list = list->next)
2957 genesis_add_filter(filter, list->dmi_addr);
baef58b1
SH		 2958 }
2959
6b0c1480 2960 xm_write32(hw, port, XM_MODE, mode);
45bada65 2961 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2962}
2963
c4cd29d2
SH		 2964static void yukon_add_filter(u8 filter[8], const u8 *addr)
2965{
2966 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2967 filter[bit/8] |= 1 << (bit%8);
2968}
2969
baef58b1
SH		 2970static void yukon_set_multicast(struct net_device *dev)
2971{
2972 struct skge_port *skge = netdev_priv(dev);
2973 struct skge_hw *hw = skge->hw;
2974 int port = skge->port;
2975 struct dev_mc_list *list = dev->mc_list;
8e95a202
JP		 2976 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2977 skge->flow_status == FLOW_STAT_SYMMETRIC);
baef58b1
SH		 2978 u16 reg;
2979 u8 filter[8];
2980
2981 memset(filter, 0, sizeof(filter));
2982
6b0c1480 2983 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2984 reg |= GM_RXCR_UCF_ENA;
2985
8f3f8193 2986 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2987 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2988 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2989 memset(filter, 0xff, sizeof(filter));
c4cd29d2 2990 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
baef58b1
SH		 2991 reg &= ~GM_RXCR_MCF_ENA;
2992 else {
2993 int i;
2994 reg |= GM_RXCR_MCF_ENA;
2995
c4cd29d2
SH		 2996 if (rx_pause)
2997 yukon_add_filter(filter, pause_mc_addr);
2998
2999 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3000 yukon_add_filter(filter, list->dmi_addr);
baef58b1
SH		 3001 }
3002
3003
6b0c1480 3004 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 3005 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 3006 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 3007 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 3008 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 3009 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 3010 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 3011 (u16)filter[6] | ((u16)filter[7] << 8));
3012
6b0c1480 3013 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 3014}
3015
383181ac
SH		 3016static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3017{
3018 if (hw->chip_id == CHIP_ID_GENESIS)
3019 return status >> XMR_FS_LEN_SHIFT;
3020 else
3021 return status >> GMR_FS_LEN_SHIFT;
3022}
3023
baef58b1
SH		 3024static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3025{
3026 if (hw->chip_id == CHIP_ID_GENESIS)
3027 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3028 else
3029 return (status & GMR_FS_ANY_ERR) ||
3030 (status & GMR_FS_RX_OK) == 0;
3031}
3032
f80d032b
SH		 3033static void skge_set_multicast(struct net_device *dev)
3034{
3035 struct skge_port *skge = netdev_priv(dev);
3036 struct skge_hw *hw = skge->hw;
3037
3038 if (hw->chip_id == CHIP_ID_GENESIS)
3039 genesis_set_multicast(dev);
3040 else
3041 yukon_set_multicast(dev);
3042
3043}
3044
19a33d4e
SH		 3045
3046/* Get receive buffer from descriptor.
3047 * Handles copy of small buffers and reallocation failures
3048 */
c54f9765
SH		 3049static struct sk_buff *skge_rx_get(struct net_device *dev,
3050 struct skge_element *e,
3051 u32 control, u32 status, u16 csum)
19a33d4e 3052{
c54f9765 3053 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 3054 struct sk_buff *skb;
3055 u16 len = control & BMU_BBC;
3056
3057 if (unlikely(netif_msg_rx_status(skge)))
3058 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
c54f9765 3059 dev->name, e - skge->rx_ring.start,
383181ac
SH		 3060 status, len);
3061
3062 if (len > skge->rx_buf_size)
3063 goto error;
3064
3065 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3066 goto error;
3067
3068 if (bad_phy_status(skge->hw, status))
3069 goto error;
3070
3071 if (phy_length(skge->hw, status) != len)
3072 goto error;
19a33d4e
SH		 3073
3074 if (len < RX_COPY_THRESHOLD) {
89d71a66 3075 skb = netdev_alloc_skb_ip_align(dev, len);
383181ac
SH		 3076 if (!skb)
3077 goto resubmit;
19a33d4e
SH		 3078
3079 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3080 pci_unmap_addr(e, mapaddr),
3081 len, PCI_DMA_FROMDEVICE);
d626f62b 3082 skb_copy_from_linear_data(e->skb, skb->data, len);
19a33d4e
SH		 3083 pci_dma_sync_single_for_device(skge->hw->pdev,
3084 pci_unmap_addr(e, mapaddr),
3085 len, PCI_DMA_FROMDEVICE);
19a33d4e 3086 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 3087 } else {
383181ac 3088 struct sk_buff *nskb;
89d71a66
ED		 3089
3090 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
383181ac
SH		 3091 if (!nskb)
3092 goto resubmit;
19a33d4e
SH		 3093
3094 pci_unmap_single(skge->hw->pdev,
3095 pci_unmap_addr(e, mapaddr),
3096 pci_unmap_len(e, maplen),
3097 PCI_DMA_FROMDEVICE);
3098 skb = e->skb;
383181ac 3099 prefetch(skb->data);
19a33d4e 3100 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 3101 }
383181ac
SH		 3102
3103 skb_put(skb, len);
383181ac
SH		 3104 if (skge->rx_csum) {
3105 skb->csum = csum;
84fa7933 3106 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 3107 }
3108
c54f9765 3109 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 3110
3111 return skb;
3112error:
3113
3114 if (netif_msg_rx_err(skge))
3115 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
c54f9765 3116 dev->name, e - skge->rx_ring.start,
383181ac
SH		 3117 control, status);
3118
3119 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3120 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
da00772f 3121 dev->stats.rx_length_errors++;
383181ac 3122 if (status & XMR_FS_FRA_ERR)
da00772f 3123 dev->stats.rx_frame_errors++;
383181ac 3124 if (status & XMR_FS_FCS_ERR)
da00772f 3125 dev->stats.rx_crc_errors++;
383181ac
SH		 3126 } else {
3127 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
da00772f 3128 dev->stats.rx_length_errors++;
383181ac 3129 if (status & GMR_FS_FRAGMENT)
da00772f 3130 dev->stats.rx_frame_errors++;
383181ac 3131 if (status & GMR_FS_CRC_ERR)
da00772f 3132 dev->stats.rx_crc_errors++;
383181ac
SH		 3133 }
3134
3135resubmit:
3136 skge_rx_reuse(e, skge->rx_buf_size);
3137 return NULL;
baef58b1
SH		 3138}
3139
7c442fa1 3140/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 3141static void skge_tx_done(struct net_device *dev)
00a6cae2 3142{
7c442fa1 3143 struct skge_port *skge = netdev_priv(dev);
00a6cae2 3144 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 3145 struct skge_element *e;
3146
513f533e 3147 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 3148
866b4f3e 3149 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
992c9623 3150 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
00a6cae2 3151
992c9623 3152 if (control & BMU_OWN)
00a6cae2
SH		 3153 break;
3154
992c9623 3155 skge_tx_free(skge, e, control);
00a6cae2 3156 }
7c442fa1 3157 skge->tx_ring.to_clean = e;
866b4f3e 3158
992c9623
SH		 3159 /* Can run lockless until we need to synchronize to restart queue. */
3160 smp_mb();
3161
3162 if (unlikely(netif_queue_stopped(dev) &&
3163 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3164 netif_tx_lock(dev);
3165 if (unlikely(netif_queue_stopped(dev) &&
3166 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3167 netif_wake_queue(dev);
00a6cae2 3168
992c9623
SH		 3169 }
3170 netif_tx_unlock(dev);
3171 }
00a6cae2 3172}
19a33d4e 3173
bea3348e 3174static int skge_poll(struct napi_struct *napi, int to_do)
baef58b1 3175{
bea3348e
SH		 3176 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3177 struct net_device *dev = skge->netdev;
baef58b1
SH		 3178 struct skge_hw *hw = skge->hw;
3179 struct skge_ring *ring = &skge->rx_ring;
3180 struct skge_element *e;
00a6cae2
SH		 3181 int work_done = 0;
3182
513f533e
SH		 3183 skge_tx_done(dev);
3184
3185 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3186
1631aef1 3187 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 3188 struct skge_rx_desc *rd = e->desc;
19a33d4e 3189 struct sk_buff *skb;
383181ac 3190 u32 control;
baef58b1
SH		 3191
3192 rmb();
3193 control = rd->control;
3194 if (control & BMU_OWN)
3195 break;
3196
c54f9765 3197 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 3198 if (likely(skb)) {
19a33d4e 3199 netif_receive_skb(skb);
baef58b1 3200
19a33d4e 3201 ++work_done;
5a011447 3202 }
baef58b1
SH		 3203 }
3204 ring->to_clean = e;
3205
baef58b1
SH		 3206 /* restart receiver */
3207 wmb();
a9cdab86 3208 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 3209
bea3348e 3210 if (work_done < to_do) {
6ef2977d 3211 unsigned long flags;
f0c88f9c 3212
6ef2977d 3213 spin_lock_irqsave(&hw->hw_lock, flags);
288379f0 3214 __napi_complete(napi);
bea3348e
SH		 3215 hw->intr_mask |= napimask[skge->port];
3216 skge_write32(hw, B0_IMSK, hw->intr_mask);
3217 skge_read32(hw, B0_IMSK);
6ef2977d 3218 spin_unlock_irqrestore(&hw->hw_lock, flags);
bea3348e 3219 }
1631aef1 3220
bea3348e 3221 return work_done;
baef58b1
SH		 3222}
3223
f6620cab
SH		 3224/* Parity errors seem to happen when Genesis is connected to a switch
3225 * with no other ports present. Heartbeat error??
3226 */
baef58b1
SH		 3227static void skge_mac_parity(struct skge_hw *hw, int port)
3228{
f6620cab
SH		 3229 struct net_device *dev = hw->dev[port];
3230
da00772f 3231 ++dev->stats.tx_heartbeat_errors;
baef58b1
SH		 3232
3233 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 3234 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 3235 MFF_CLR_PERR);
3236 else
3237 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 3238 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 3239 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 3240 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3241}
3242
baef58b1
SH		 3243static void skge_mac_intr(struct skge_hw *hw, int port)
3244{
95566065 3245 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 3246 genesis_mac_intr(hw, port);
3247 else
3248 yukon_mac_intr(hw, port);
3249}
3250
3251/* Handle device specific framing and timeout interrupts */
3252static void skge_error_irq(struct skge_hw *hw)
3253{
1479d13c 3254 struct pci_dev *pdev = hw->pdev;
baef58b1
SH		 3255 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3256
3257 if (hw->chip_id == CHIP_ID_GENESIS) {
3258 /* clear xmac errors */
3259 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3260 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3261 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3262 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3263 } else {
3264 /* Timestamp (unused) overflow */
3265 if (hwstatus & IS_IRQ_TIST_OV)
3266 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3267 }
3268
3269 if (hwstatus & IS_RAM_RD_PAR) {
1479d13c 3270 dev_err(&pdev->dev, "Ram read data parity error\n");
baef58b1
SH		 3271 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3272 }
3273
3274 if (hwstatus & IS_RAM_WR_PAR) {
1479d13c 3275 dev_err(&pdev->dev, "Ram write data parity error\n");
baef58b1
SH		 3276 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3277 }
3278
3279 if (hwstatus & IS_M1_PAR_ERR)
3280 skge_mac_parity(hw, 0);
3281
3282 if (hwstatus & IS_M2_PAR_ERR)
3283 skge_mac_parity(hw, 1);
3284
b9d64acc 3285 if (hwstatus & IS_R1_PAR_ERR) {
1479d13c
SH		 3286 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3287 hw->dev[0]->name);
baef58b1 3288 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3289 }
baef58b1 3290
b9d64acc 3291 if (hwstatus & IS_R2_PAR_ERR) {
1479d13c
SH		 3292 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3293 hw->dev[1]->name);
baef58b1 3294 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3295 }
baef58b1
SH		 3296
3297 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3298 u16 pci_status, pci_cmd;
3299
1479d13c
SH		 3300 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3301 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
baef58b1 3302
1479d13c
SH		 3303 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3304 pci_cmd, pci_status);
b9d64acc
SH		 3305
3306 /* Write the error bits back to clear them. */
3307 pci_status &= PCI_STATUS_ERROR_BITS;
3308 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1479d13c 3309 pci_write_config_word(pdev, PCI_COMMAND,
b9d64acc 3310 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
1479d13c 3311 pci_write_config_word(pdev, PCI_STATUS, pci_status);
b9d64acc 3312 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3313
050ec18a 3314 /* if error still set then just ignore it */
baef58b1
SH		 3315 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3316 if (hwstatus & IS_IRQ_STAT) {
1479d13c 3317 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3318 hw->intr_mask &= ~IS_HW_ERR;
3319 }
3320 }
3321}
3322
3323/*
9cbe330f 3324 * Interrupt from PHY are handled in tasklet (softirq)
baef58b1
SH		 3325 * because accessing phy registers requires spin wait which might
3326 * cause excess interrupt latency.
3327 */
9cbe330f 3328static void skge_extirq(unsigned long arg)
baef58b1 3329{
9cbe330f 3330 struct skge_hw *hw = (struct skge_hw *) arg;
baef58b1
SH		 3331 int port;
3332
cfc3ed79 3333 for (port = 0; port < hw->ports; port++) {
baef58b1
SH		 3334 struct net_device *dev = hw->dev[port];
3335
cfc3ed79 3336 if (netif_running(dev)) {
9cbe330f
SH		 3337 struct skge_port *skge = netdev_priv(dev);
3338
3339 spin_lock(&hw->phy_lock);
baef58b1
SH		 3340 if (hw->chip_id != CHIP_ID_GENESIS)
3341 yukon_phy_intr(skge);
64f6b64d 3342 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3343 bcom_phy_intr(skge);
9cbe330f 3344 spin_unlock(&hw->phy_lock);
baef58b1
SH		 3345 }
3346 }
baef58b1 3347
7c442fa1 3348 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3349 hw->intr_mask |= IS_EXT_REG;
3350 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3351 skge_read32(hw, B0_IMSK);
7c442fa1 3352 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3353}
3354
7d12e780 3355static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3356{
3357 struct skge_hw *hw = dev_id;
cfc3ed79 3358 u32 status;
29365c90 3359 int handled = 0;
baef58b1 3360
29365c90 3361 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3362 /* Reading this register masks IRQ */
3363 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3364 if (status == 0 || status == ~0)
29365c90 3365 goto out;
baef58b1 3366
29365c90 3367 handled = 1;
7c442fa1 3368 status &= hw->intr_mask;
cfc3ed79
SH		 3369 if (status & IS_EXT_REG) {
3370 hw->intr_mask &= ~IS_EXT_REG;
9cbe330f 3371 tasklet_schedule(&hw->phy_task);
cfc3ed79
SH		 3372 }
3373
513f533e 3374 if (status & (IS_XA1_F|IS_R1_F)) {
bea3348e 3375 struct skge_port *skge = netdev_priv(hw->dev[0]);
513f533e 3376 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
288379f0 3377 napi_schedule(&skge->napi);
baef58b1
SH		 3378 }
3379
7c442fa1
SH		 3380 if (status & IS_PA_TO_TX1)
3381 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3382
d25f5a67 3383 if (status & IS_PA_TO_RX1) {
da00772f 3384 ++hw->dev[0]->stats.rx_over_errors;
7c442fa1 3385 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3386 }
3387
d25f5a67 3388
baef58b1
SH		 3389 if (status & IS_MAC1)
3390 skge_mac_intr(hw, 0);
95566065 3391
7c442fa1 3392 if (hw->dev[1]) {
bea3348e
SH		 3393 struct skge_port *skge = netdev_priv(hw->dev[1]);
3394
513f533e
SH		 3395 if (status & (IS_XA2_F|IS_R2_F)) {
3396 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
288379f0 3397 napi_schedule(&skge->napi);
7c442fa1
SH		 3398 }
3399
3400 if (status & IS_PA_TO_RX2) {
da00772f 3401 ++hw->dev[1]->stats.rx_over_errors;
7c442fa1
SH		 3402 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3403 }
3404
3405 if (status & IS_PA_TO_TX2)
3406 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3407
3408 if (status & IS_MAC2)
3409 skge_mac_intr(hw, 1);
3410 }
baef58b1
SH		 3411
3412 if (status & IS_HW_ERR)
3413 skge_error_irq(hw);
3414
7e676d91 3415 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3416 skge_read32(hw, B0_IMSK);
29365c90 3417out:
7c442fa1 3418 spin_unlock(&hw->hw_lock);
baef58b1 3419
29365c90 3420 return IRQ_RETVAL(handled);
baef58b1
SH		 3421}
3422
3423#ifdef CONFIG_NET_POLL_CONTROLLER
3424static void skge_netpoll(struct net_device *dev)
3425{
3426 struct skge_port *skge = netdev_priv(dev);
3427
3428 disable_irq(dev->irq);
7d12e780 3429 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3430 enable_irq(dev->irq);
3431}
3432#endif
3433
3434static int skge_set_mac_address(struct net_device *dev, void *p)
3435{
3436 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3437 struct skge_hw *hw = skge->hw;
3438 unsigned port = skge->port;
3439 const struct sockaddr *addr = p;
2eb3e621 3440 u16 ctrl;
baef58b1
SH		 3441
3442 if (!is_valid_ether_addr(addr->sa_data))
3443 return -EADDRNOTAVAIL;
3444
baef58b1 3445 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3446
9cbe330f
SH		 3447 if (!netif_running(dev)) {
3448 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3449 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3450 } else {
3451 /* disable Rx */
3452 spin_lock_bh(&hw->phy_lock);
3453 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3454 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
2eb3e621 3455
9cbe330f
SH		 3456 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3457 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
2eb3e621 3458
2eb3e621
SH		 3459 if (hw->chip_id == CHIP_ID_GENESIS)
3460 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3461 else {
3462 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3463 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3464 }
2eb3e621 3465
9cbe330f
SH		 3466 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3467 spin_unlock_bh(&hw->phy_lock);
3468 }
c2681dd8
SH		 3469
3470 return 0;
baef58b1
SH		 3471}
3472
3473static const struct {
3474 u8 id;
3475 const char *name;
3476} skge_chips[] = {
3477 { CHIP_ID_GENESIS, "Genesis" },
3478 { CHIP_ID_YUKON, "Yukon" },
3479 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3480 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3481};
3482
3483static const char *skge_board_name(const struct skge_hw *hw)
3484{
3485 int i;
3486 static char buf[16];
3487
3488 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3489 if (skge_chips[i].id == hw->chip_id)
3490 return skge_chips[i].name;
3491
3492 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3493 return buf;
3494}
3495
3496
3497/*
3498 * Setup the board data structure, but don't bring up
3499 * the port(s)
3500 */
3501static int skge_reset(struct skge_hw *hw)
3502{
adba9e23 3503 u32 reg;
b9d64acc 3504 u16 ctst, pci_status;
64f6b64d 3505 u8 t8, mac_cfg, pmd_type;
981d0377 3506 int i;
baef58b1
SH		 3507
3508 ctst = skge_read16(hw, B0_CTST);
3509
3510 /* do a SW reset */
3511 skge_write8(hw, B0_CTST, CS_RST_SET);
3512 skge_write8(hw, B0_CTST, CS_RST_CLR);
3513
3514 /* clear PCI errors, if any */
b9d64acc
SH		 3515 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3516 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3517
b9d64acc
SH		 3518 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3519 pci_write_config_word(hw->pdev, PCI_STATUS,
3520 pci_status | PCI_STATUS_ERROR_BITS);
3521 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3522 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3523
3524 /* restore CLK_RUN bits (for Yukon-Lite) */
3525 skge_write16(hw, B0_CTST,
3526 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3527
3528 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3529 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3530 pmd_type = skge_read8(hw, B2_PMD_TYP);
3531 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3532
95566065 3533 switch (hw->chip_id) {
baef58b1 3534 case CHIP_ID_GENESIS:
64f6b64d
SH		 3535 switch (hw->phy_type) {
3536 case SK_PHY_XMAC:
3537 hw->phy_addr = PHY_ADDR_XMAC;
3538 break;
baef58b1
SH		 3539 case SK_PHY_BCOM:
3540 hw->phy_addr = PHY_ADDR_BCOM;
3541 break;
3542 default:
1479d13c
SH		 3543 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3544 hw->phy_type);
baef58b1
SH		 3545 return -EOPNOTSUPP;
3546 }
3547 break;
3548
3549 case CHIP_ID_YUKON:
3550 case CHIP_ID_YUKON_LITE:
3551 case CHIP_ID_YUKON_LP:
64f6b64d 3552 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3553 hw->copper = 1;
baef58b1
SH		 3554
3555 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3556 break;
3557
3558 default:
1479d13c
SH		 3559 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3560 hw->chip_id);
baef58b1
SH		 3561 return -EOPNOTSUPP;
3562 }
3563
981d0377
SH		 3564 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3565 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3566 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3567
3568 /* read the adapters RAM size */
3569 t8 = skge_read8(hw, B2_E_0);
3570 if (hw->chip_id == CHIP_ID_GENESIS) {
3571 if (t8 == 3) {
3572 /* special case: 4 x 64k x 36, offset = 0x80000 */
279e1dab
LT		 3573 hw->ram_size = 0x100000;
3574 hw->ram_offset = 0x80000;
baef58b1
SH		 3575 } else
3576 hw->ram_size = t8 * 512;
279e1dab
LT		 3577 }
3578 else if (t8 == 0)
3579 hw->ram_size = 0x20000;
3580 else
3581 hw->ram_size = t8 * 4096;
baef58b1 3582
4ebabfcb 3583 hw->intr_mask = IS_HW_ERR;
cfc3ed79 3584
4ebabfcb 3585 /* Use PHY IRQ for all but fiber based Genesis board */
64f6b64d
SH		 3586 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3587 hw->intr_mask |= IS_EXT_REG;
3588
baef58b1
SH		 3589 if (hw->chip_id == CHIP_ID_GENESIS)
3590 genesis_init(hw);
3591 else {
3592 /* switch power to VCC (WA for VAUX problem) */
3593 skge_write8(hw, B0_POWER_CTRL,
3594 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3595
050ec18a
SH		 3596 /* avoid boards with stuck Hardware error bits */
3597 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3598 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
1479d13c 3599 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
050ec18a
SH		 3600 hw->intr_mask &= ~IS_HW_ERR;
3601 }
3602
adba9e23
SH		 3603 /* Clear PHY COMA */
3604 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3605 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3606 reg &= ~PCI_PHY_COMA;
3607 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3608 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3609
3610
981d0377 3611 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3612 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3613 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3614 }
3615 }
3616
3617 /* turn off hardware timer (unused) */
3618 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3619 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3620 skge_write8(hw, B0_LED, LED_STAT_ON);
3621
3622 /* enable the Tx Arbiters */
981d0377 3623 for (i = 0; i < hw->ports; i++)
6b0c1480 3624 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3625
3626 /* Initialize ram interface */
3627 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3628
3629 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3630 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3631 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3632 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3633 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3634 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3635 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3636 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3637 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3638 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3639 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3640 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3641
3642 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3643
3644 /* Set interrupt moderation for Transmit only
3645 * Receive interrupts avoided by NAPI
3646 */
3647 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3648 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3649 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3650
baef58b1
SH		 3651 skge_write32(hw, B0_IMSK, hw->intr_mask);
3652
981d0377 3653 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3654 if (hw->chip_id == CHIP_ID_GENESIS)
3655 genesis_reset(hw, i);
3656 else
3657 yukon_reset(hw, i);
3658 }
baef58b1
SH		 3659
3660 return 0;
3661}
3662
678aa1f6
SH		 3663
3664#ifdef CONFIG_SKGE_DEBUG
3665
3666static struct dentry *skge_debug;
3667
3668static int skge_debug_show(struct seq_file *seq, void *v)
3669{
3670 struct net_device *dev = seq->private;
3671 const struct skge_port *skge = netdev_priv(dev);
3672 const struct skge_hw *hw = skge->hw;
3673 const struct skge_element *e;
3674
3675 if (!netif_running(dev))
3676 return -ENETDOWN;
3677
3678 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3679 skge_read32(hw, B0_IMSK));
3680
3681 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3682 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3683 const struct skge_tx_desc *t = e->desc;
3684 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3685 t->control, t->dma_hi, t->dma_lo, t->status,
3686 t->csum_offs, t->csum_write, t->csum_start);
3687 }
3688
3689 seq_printf(seq, "\nRx Ring: \n");
3690 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3691 const struct skge_rx_desc *r = e->desc;
3692
3693 if (r->control & BMU_OWN)
3694 break;
3695
3696 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3697 r->control, r->dma_hi, r->dma_lo, r->status,
3698 r->timestamp, r->csum1, r->csum1_start);
3699 }
3700
3701 return 0;
3702}
3703
3704static int skge_debug_open(struct inode *inode, struct file *file)
3705{
3706 return single_open(file, skge_debug_show, inode->i_private);
3707}
3708
3709static const struct file_operations skge_debug_fops = {
3710 .owner = THIS_MODULE,
3711 .open = skge_debug_open,
3712 .read = seq_read,
3713 .llseek = seq_lseek,
3714 .release = single_release,
3715};
3716
3717/*
3718 * Use network device events to create/remove/rename
3719 * debugfs file entries
3720 */
3721static int skge_device_event(struct notifier_block *unused,
3722 unsigned long event, void *ptr)
3723{
3724 struct net_device *dev = ptr;
3725 struct skge_port *skge;
3726 struct dentry *d;
3727
f80d032b 3728 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
678aa1f6
SH		 3729 goto done;
3730
3731 skge = netdev_priv(dev);
3732 switch(event) {
3733 case NETDEV_CHANGENAME:
3734 if (skge->debugfs) {
3735 d = debugfs_rename(skge_debug, skge->debugfs,
3736 skge_debug, dev->name);
3737 if (d)
3738 skge->debugfs = d;
3739 else {
3740 pr_info(PFX "%s: rename failed\n", dev->name);
3741 debugfs_remove(skge->debugfs);
3742 }
3743 }
3744 break;
3745
3746 case NETDEV_GOING_DOWN:
3747 if (skge->debugfs) {
3748 debugfs_remove(skge->debugfs);
3749 skge->debugfs = NULL;
3750 }
3751 break;
3752
3753 case NETDEV_UP:
3754 d = debugfs_create_file(dev->name, S_IRUGO,
3755 skge_debug, dev,
3756 &skge_debug_fops);
3757 if (!d || IS_ERR(d))
3758 pr_info(PFX "%s: debugfs create failed\n",
3759 dev->name);
3760 else
3761 skge->debugfs = d;
3762 break;
3763 }
3764
3765done:
3766 return NOTIFY_DONE;
3767}
3768
3769static struct notifier_block skge_notifier = {
3770 .notifier_call = skge_device_event,
3771};
3772
3773
3774static __init void skge_debug_init(void)
3775{
3776 struct dentry *ent;
3777
3778 ent = debugfs_create_dir("skge", NULL);
3779 if (!ent || IS_ERR(ent)) {
3780 pr_info(PFX "debugfs create directory failed\n");
3781 return;
3782 }
3783
3784 skge_debug = ent;
3785 register_netdevice_notifier(&skge_notifier);
3786}
3787
3788static __exit void skge_debug_cleanup(void)
3789{
3790 if (skge_debug) {
3791 unregister_netdevice_notifier(&skge_notifier);
3792 debugfs_remove(skge_debug);
3793 skge_debug = NULL;
3794 }
3795}
3796
3797#else
3798#define skge_debug_init()
3799#define skge_debug_cleanup()
3800#endif
3801
f80d032b
SH		 3802static const struct net_device_ops skge_netdev_ops = {
3803 .ndo_open = skge_up,
3804 .ndo_stop = skge_down,
00829823 3805 .ndo_start_xmit = skge_xmit_frame,
f80d032b
SH		 3806 .ndo_do_ioctl = skge_ioctl,
3807 .ndo_get_stats = skge_get_stats,
3808 .ndo_tx_timeout = skge_tx_timeout,
3809 .ndo_change_mtu = skge_change_mtu,
3810 .ndo_validate_addr = eth_validate_addr,
3811 .ndo_set_multicast_list = skge_set_multicast,
3812 .ndo_set_mac_address = skge_set_mac_address,
3813#ifdef CONFIG_NET_POLL_CONTROLLER
3814 .ndo_poll_controller = skge_netpoll,
3815#endif
3816};
3817
3818
baef58b1 3819/* Initialize network device */
981d0377
SH		 3820static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3821 int highmem)
baef58b1
SH		 3822{
3823 struct skge_port *skge;
3824 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3825
3826 if (!dev) {
1479d13c 3827 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
baef58b1
SH		 3828 return NULL;
3829 }
3830
baef58b1 3831 SET_NETDEV_DEV(dev, &hw->pdev->dev);
f80d032b
SH		 3832 dev->netdev_ops = &skge_netdev_ops;
3833 dev->ethtool_ops = &skge_ethtool_ops;
baef58b1 3834 dev->watchdog_timeo = TX_WATCHDOG;
baef58b1 3835 dev->irq = hw->pdev->irq;
513f533e 3836
981d0377
SH		 3837 if (highmem)
3838 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3839
3840 skge = netdev_priv(dev);
bea3348e 3841 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
baef58b1
SH		 3842 skge->netdev = dev;
3843 skge->hw = hw;
3844 skge->msg_enable = netif_msg_init(debug, default_msg);
9cbe330f 3845
baef58b1
SH		 3846 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3847 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3848
3849 /* Auto speed and flow control */
3850 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3851 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3852 skge->duplex = -1;
3853 skge->speed = -1;
31b619c5 3854 skge->advertising = skge_supported_modes(hw);
5b982c5b 3855
7b55a4a3 3856 if (device_can_wakeup(&hw->pdev->dev)) {
5b982c5b 3857 skge->wol = wol_supported(hw) & WAKE_MAGIC;
7b55a4a3
RW		 3858 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3859 }
baef58b1
SH		 3860
3861 hw->dev[port] = dev;
3862
3863 skge->port = port;
3864
64f6b64d 3865 /* Only used for Genesis XMAC */
9cbe330f 3866 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
64f6b64d 3867
baef58b1
SH		 3868 if (hw->chip_id != CHIP_ID_GENESIS) {
3869 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3870 skge->rx_csum = 1;
3871 }
3872
3873 /* read the mac address */
3874 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3875 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3876
3877 /* device is off until link detection */
3878 netif_carrier_off(dev);
3879 netif_stop_queue(dev);
3880
3881 return dev;
3882}
3883
3884static void __devinit skge_show_addr(struct net_device *dev)
3885{
3886 const struct skge_port *skge = netdev_priv(dev);
3887
3888 if (netif_msg_probe(skge))
e174961c
JB		 3889 printk(KERN_INFO PFX "%s: addr %pM\n",
3890 dev->name, dev->dev_addr);
baef58b1
SH		 3891}
3892
3893static int __devinit skge_probe(struct pci_dev *pdev,
3894 const struct pci_device_id *ent)
3895{
3896 struct net_device *dev, *dev1;
3897 struct skge_hw *hw;
3898 int err, using_dac = 0;
3899
203babb6
SH		 3900 err = pci_enable_device(pdev);
3901 if (err) {
1479d13c 3902 dev_err(&pdev->dev, "cannot enable PCI device\n");
baef58b1
SH		 3903 goto err_out;
3904 }
3905
203babb6
SH		 3906 err = pci_request_regions(pdev, DRV_NAME);
3907 if (err) {
1479d13c 3908 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
baef58b1
SH		 3909 goto err_out_disable_pdev;
3910 }
3911
3912 pci_set_master(pdev);
3913
6a35528a 3914 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
baef58b1 3915 using_dac = 1;
6a35528a 3916 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
284901a9 3917 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
93aea718 3918 using_dac = 0;
284901a9 3919 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
93aea718
SH		 3920 }
3921
3922 if (err) {
1479d13c 3923 dev_err(&pdev->dev, "no usable DMA configuration\n");
93aea718 3924 goto err_out_free_regions;
baef58b1
SH		 3925 }
3926
3927#ifdef __BIG_ENDIAN
8f3f8193 3928 /* byte swap descriptors in hardware */
baef58b1
SH		 3929 {
3930 u32 reg;
3931
3932 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3933 reg |= PCI_REV_DESC;
3934 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3935 }
3936#endif
3937
3938 err = -ENOMEM;
415e69e6
MS		 3939 /* space for skge@pci:0000:04:00.0 */
3940 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:" )
3941 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
baef58b1 3942 if (!hw) {
1479d13c 3943 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
baef58b1
SH		 3944 goto err_out_free_regions;
3945 }
415e69e6 3946 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
baef58b1 3947
baef58b1 3948 hw->pdev = pdev;
d38efdd6 3949 spin_lock_init(&hw->hw_lock);
9cbe330f 3950 spin_lock_init(&hw->phy_lock);
164165da 3951 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
baef58b1
SH		 3952
3953 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3954 if (!hw->regs) {
1479d13c 3955 dev_err(&pdev->dev, "cannot map device registers\n");
baef58b1
SH		 3956 goto err_out_free_hw;
3957 }
3958
baef58b1
SH		 3959 err = skge_reset(hw);
3960 if (err)
ccdaa2a9 3961 goto err_out_iounmap;
baef58b1 3962
7c7459d1
GKH		 3963 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3964 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
981d0377 3965 skge_board_name(hw), hw->chip_rev);
baef58b1 3966
ccdaa2a9
SH		 3967 dev = skge_devinit(hw, 0, using_dac);
3968 if (!dev)
baef58b1
SH		 3969 goto err_out_led_off;
3970
fae87592 3971 /* Some motherboards are broken and has zero in ROM. */
1479d13c
SH		 3972 if (!is_valid_ether_addr(dev->dev_addr))
3973 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
631ae320 3974
203babb6
SH		 3975 err = register_netdev(dev);
3976 if (err) {
1479d13c 3977 dev_err(&pdev->dev, "cannot register net device\n");
baef58b1
SH		 3978 goto err_out_free_netdev;
3979 }
3980
415e69e6 3981 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
ccdaa2a9 3982 if (err) {
1479d13c 3983 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
ccdaa2a9
SH		 3984 dev->name, pdev->irq);
3985 goto err_out_unregister;
3986 }
baef58b1
SH		 3987 skge_show_addr(dev);
3988
f1914226
MM		 3989 if (hw->ports > 1) {
3990 dev1 = skge_devinit(hw, 1, using_dac);
3991 if (dev1 && register_netdev(dev1) == 0)
baef58b1
SH		 3992 skge_show_addr(dev1);
3993 else {
3994 /* Failure to register second port need not be fatal */
1479d13c 3995 dev_warn(&pdev->dev, "register of second port failed\n");
baef58b1 3996 hw->dev[1] = NULL;
f1914226
MM		 3997 hw->ports = 1;
3998 if (dev1)
3999 free_netdev(dev1);
baef58b1
SH		 4000 }
4001 }
ccdaa2a9 4002 pci_set_drvdata(pdev, hw);
baef58b1
SH		 4003
4004 return 0;
4005
ccdaa2a9
SH		 4006err_out_unregister:
4007 unregister_netdev(dev);
baef58b1
SH		 4008err_out_free_netdev:
4009 free_netdev(dev);
4010err_out_led_off:
4011 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 4012err_out_iounmap:
4013 iounmap(hw->regs);
4014err_out_free_hw:
4015 kfree(hw);
4016err_out_free_regions:
4017 pci_release_regions(pdev);
4018err_out_disable_pdev:
4019 pci_disable_device(pdev);
4020 pci_set_drvdata(pdev, NULL);
4021err_out:
4022 return err;
4023}
4024
4025static void __devexit skge_remove(struct pci_dev *pdev)
4026{
4027 struct skge_hw *hw = pci_get_drvdata(pdev);
4028 struct net_device *dev0, *dev1;
4029
95566065 4030 if (!hw)
baef58b1
SH		 4031 return;
4032
208491d8
SH		 4033 flush_scheduled_work();
4034
baef58b1
SH		 4035 if ((dev1 = hw->dev[1]))
4036 unregister_netdev(dev1);
4037 dev0 = hw->dev[0];
4038 unregister_netdev(dev0);
4039
9cbe330f
SH		 4040 tasklet_disable(&hw->phy_task);
4041
7c442fa1
SH		 4042 spin_lock_irq(&hw->hw_lock);
4043 hw->intr_mask = 0;
46a60f2d 4044 skge_write32(hw, B0_IMSK, 0);
78bc2186 4045 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 4046 spin_unlock_irq(&hw->hw_lock);
4047
46a60f2d 4048 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 4049 skge_write8(hw, B0_CTST, CS_RST_SET);
4050
baef58b1
SH		 4051 free_irq(pdev->irq, hw);
4052 pci_release_regions(pdev);
4053 pci_disable_device(pdev);
4054 if (dev1)
4055 free_netdev(dev1);
4056 free_netdev(dev0);
46a60f2d 4057
baef58b1
SH		 4058 iounmap(hw->regs);
4059 kfree(hw);
4060 pci_set_drvdata(pdev, NULL);
4061}
4062
4063#ifdef CONFIG_PM
2a569579 4064static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 4065{
4066 struct skge_hw *hw = pci_get_drvdata(pdev);
a504e64a
SH		 4067 int i, err, wol = 0;
4068
e3b7df17
SH		 4069 if (!hw)
4070 return 0;
4071
a504e64a
SH		 4072 err = pci_save_state(pdev);
4073 if (err)
4074 return err;
baef58b1 4075
d38efdd6 4076 for (i = 0; i < hw->ports; i++) {
baef58b1 4077 struct net_device *dev = hw->dev[i];
a504e64a 4078 struct skge_port *skge = netdev_priv(dev);
baef58b1 4079
a504e64a
SH		 4080 if (netif_running(dev))
4081 skge_down(dev);
4082 if (skge->wol)
4083 skge_wol_init(skge);
d38efdd6 4084
a504e64a 4085 wol |= skge->wol;
baef58b1
SH		 4086 }
4087
d38efdd6 4088 skge_write32(hw, B0_IMSK, 0);
5177b324
RW		 4089
4090 pci_prepare_to_sleep(pdev);
baef58b1
SH		 4091
4092 return 0;
4093}
4094
4095static int skge_resume(struct pci_dev *pdev)
4096{
4097 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 4098 int i, err;
baef58b1 4099
e3b7df17
SH		 4100 if (!hw)
4101 return 0;
4102
5177b324 4103 err = pci_back_from_sleep(pdev);
a504e64a
SH		 4104 if (err)
4105 goto out;
4106
4107 err = pci_restore_state(pdev);
4108 if (err)
4109 goto out;
4110
d38efdd6
SH		 4111 err = skge_reset(hw);
4112 if (err)
4113 goto out;
baef58b1 4114
d38efdd6 4115 for (i = 0; i < hw->ports; i++) {
baef58b1 4116 struct net_device *dev = hw->dev[i];
d38efdd6 4117
d38efdd6
SH		 4118 if (netif_running(dev)) {
4119 err = skge_up(dev);
4120
4121 if (err) {
4122 printk(KERN_ERR PFX "%s: could not up: %d\n",
4123 dev->name, err);
edd702e8 4124 dev_close(dev);
d38efdd6
SH		 4125 goto out;
4126 }
baef58b1
SH		 4127 }
4128 }
d38efdd6
SH		 4129out:
4130 return err;
baef58b1
SH		 4131}
4132#endif
4133
692412b3
SH		 4134static void skge_shutdown(struct pci_dev *pdev)
4135{
4136 struct skge_hw *hw = pci_get_drvdata(pdev);
4137 int i, wol = 0;
4138
e3b7df17
SH		 4139 if (!hw)
4140 return;
4141
692412b3
SH		 4142 for (i = 0; i < hw->ports; i++) {
4143 struct net_device *dev = hw->dev[i];
4144 struct skge_port *skge = netdev_priv(dev);
4145
4146 if (skge->wol)
4147 skge_wol_init(skge);
4148 wol |= skge->wol;
4149 }
4150
5177b324
RW		 4151 if (pci_enable_wake(pdev, PCI_D3cold, wol))
4152 pci_enable_wake(pdev, PCI_D3hot, wol);
692412b3
SH		 4153
4154 pci_disable_device(pdev);
4155 pci_set_power_state(pdev, PCI_D3hot);
4156
4157}
4158
baef58b1
SH		 4159static struct pci_driver skge_driver = {
4160 .name = DRV_NAME,
4161 .id_table = skge_id_table,
4162 .probe = skge_probe,
4163 .remove = __devexit_p(skge_remove),
4164#ifdef CONFIG_PM
4165 .suspend = skge_suspend,
4166 .resume = skge_resume,
4167#endif
692412b3 4168 .shutdown = skge_shutdown,
baef58b1
SH		 4169};
4170
4171static int __init skge_init_module(void)
4172{
678aa1f6 4173 skge_debug_init();
29917620 4174 return pci_register_driver(&skge_driver);
baef58b1
SH		 4175}
4176
4177static void __exit skge_cleanup_module(void)
4178{
4179 pci_unregister_driver(&skge_driver);
678aa1f6 4180 skge_debug_cleanup();
baef58b1
SH		 4181}
4182
4183module_init(skge_init_module);
4184module_exit(skge_cleanup_module);
Linux 6.x block layer and io_uring tree(s)