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sis190: hard-code the alignment of tiny packets
[linux-2.6-block.git] / drivers / net / sis190.c
CommitLineData
890e8d0a
FR		 1/*
2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
3
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
7
40292fb0
FR		 8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
9 genuine driver.
890e8d0a
FR		 10
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
17
18 See the file COPYING in this distribution for more information.
19
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/netdevice.h>
43afb949 25#include <linux/rtnetlink.h>
890e8d0a
FR		 26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/pci.h>
29#include <linux/mii.h>
30#include <linux/delay.h>
31#include <linux/crc32.h>
32#include <linux/dma-mapping.h>
33#include <asm/irq.h>
34
35#define net_drv(p, arg...) if (netif_msg_drv(p)) \
36 printk(arg)
37#define net_probe(p, arg...) if (netif_msg_probe(p)) \
38 printk(arg)
39#define net_link(p, arg...) if (netif_msg_link(p)) \
40 printk(arg)
41#define net_intr(p, arg...) if (netif_msg_intr(p)) \
42 printk(arg)
43#define net_tx_err(p, arg...) if (netif_msg_tx_err(p)) \
44 printk(arg)
45
fcb9821d
FR		 46#define PHY_MAX_ADDR 32
47#define PHY_ID_ANY 0x1f
48#define MII_REG_ANY 0x1f
49
bea3348e 50#define DRV_VERSION "1.2"
890e8d0a
FR		 51#define DRV_NAME "sis190"
52#define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
53#define PFX DRV_NAME ": "
54
890e8d0a
FR		 55#define sis190_rx_skb netif_rx
56#define sis190_rx_quota(count, quota) count
890e8d0a
FR		 57
58#define MAC_ADDR_LEN 6
59
bcad5e53
FR		 60#define NUM_TX_DESC 64 /* [8..1024] */
61#define NUM_RX_DESC 64 /* [8..8192] */
890e8d0a
FR		 62#define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
63#define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
64#define RX_BUF_SIZE 1536
8b5641d4 65#define RX_BUF_MASK 0xfff8
890e8d0a
FR		 66
67#define SIS190_REGS_SIZE 0x80
68#define SIS190_TX_TIMEOUT (6*HZ)
69#define SIS190_PHY_TIMEOUT (10*HZ)
70#define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
71 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
72 NETIF_MSG_IFDOWN)
73
74/* Enhanced PHY access register bit definitions */
75#define EhnMIIread 0x0000
76#define EhnMIIwrite 0x0020
77#define EhnMIIdataShift 16
78#define EhnMIIpmdShift 6 /* 7016 only */
79#define EhnMIIregShift 11
80#define EhnMIIreq 0x0010
81#define EhnMIInotDone 0x0010
82
83/* Write/read MMIO register */
84#define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
85#define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
86#define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
87#define SIS_R8(reg) readb (ioaddr + (reg))
88#define SIS_R16(reg) readw (ioaddr + (reg))
89#define SIS_R32(reg) readl (ioaddr + (reg))
90
91#define SIS_PCI_COMMIT() SIS_R32(IntrControl)
92
93enum sis190_registers {
94 TxControl = 0x00,
95 TxDescStartAddr = 0x04,
188f23ba
FR		 96 rsv0 = 0x08, // reserved
97 TxSts = 0x0c, // unused (Control/Status)
890e8d0a
FR		 98 RxControl = 0x10,
99 RxDescStartAddr = 0x14,
188f23ba
FR		 100 rsv1 = 0x18, // reserved
101 RxSts = 0x1c, // unused
890e8d0a
FR		 102 IntrStatus = 0x20,
103 IntrMask = 0x24,
104 IntrControl = 0x28,
188f23ba
FR		 105 IntrTimer = 0x2c, // unused (Interupt Timer)
106 PMControl = 0x30, // unused (Power Mgmt Control/Status)
107 rsv2 = 0x34, // reserved
890e8d0a
FR		 108 ROMControl = 0x38,
109 ROMInterface = 0x3c,
110 StationControl = 0x40,
111 GMIIControl = 0x44,
188f23ba
FR		 112 GIoCR = 0x48, // unused (GMAC IO Compensation)
113 GIoCtrl = 0x4c, // unused (GMAC IO Control)
890e8d0a 114 TxMacControl = 0x50,
188f23ba
FR		 115 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
116 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
117 rsv3 = 0x5c, // reserved
890e8d0a
FR		 118 RxMacControl = 0x60,
119 RxMacAddr = 0x62,
120 RxHashTable = 0x68,
121 // Undocumented = 0x6c,
188f23ba
FR		 122 RxWolCtrl = 0x70,
123 RxWolData = 0x74, // unused (Rx WOL Data Access)
124 RxMPSControl = 0x78, // unused (Rx MPS Control)
125 rsv4 = 0x7c, // reserved
890e8d0a
FR		 126};
127
128enum sis190_register_content {
129 /* IntrStatus */
130 SoftInt = 0x40000000, // unused
131 Timeup = 0x20000000, // unused
132 PauseFrame = 0x00080000, // unused
133 MagicPacket = 0x00040000, // unused
134 WakeupFrame = 0x00020000, // unused
135 LinkChange = 0x00010000,
136 RxQEmpty = 0x00000080,
137 RxQInt = 0x00000040,
138 TxQ1Empty = 0x00000020, // unused
139 TxQ1Int = 0x00000010,
140 TxQ0Empty = 0x00000008, // unused
141 TxQ0Int = 0x00000004,
142 RxHalt = 0x00000002,
143 TxHalt = 0x00000001,
144
890e8d0a
FR		 145 /* {Rx/Tx}CmdBits */
146 CmdReset = 0x10,
147 CmdRxEnb = 0x08, // unused
148 CmdTxEnb = 0x01,
149 RxBufEmpty = 0x01, // unused
150
151 /* Cfg9346Bits */
152 Cfg9346_Lock = 0x00, // unused
153 Cfg9346_Unlock = 0xc0, // unused
154
155 /* RxMacControl */
156 AcceptErr = 0x20, // unused
157 AcceptRunt = 0x10, // unused
158 AcceptBroadcast = 0x0800,
159 AcceptMulticast = 0x0400,
160 AcceptMyPhys = 0x0200,
161 AcceptAllPhys = 0x0100,
162
163 /* RxConfigBits */
164 RxCfgFIFOShift = 13,
165 RxCfgDMAShift = 8, // 0x1a in RxControl ?
166
167 /* TxConfigBits */
168 TxInterFrameGapShift = 24,
169 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
170
890e8d0a
FR		 171 LinkStatus = 0x02, // unused
172 FullDup = 0x01, // unused
173
174 /* TBICSRBit */
175 TBILinkOK = 0x02000000, // unused
176};
177
178struct TxDesc {
3cec93c7
FR		 179 __le32 PSize;
180 __le32 status;
181 __le32 addr;
182 __le32 size;
890e8d0a
FR		 183};
184
185struct RxDesc {
3cec93c7
FR		 186 __le32 PSize;
187 __le32 status;
188 __le32 addr;
189 __le32 size;
890e8d0a
FR		 190};
191
192enum _DescStatusBit {
193 /* _Desc.status */
bcad5e53
FR		 194 OWNbit = 0x80000000, // RXOWN/TXOWN
195 INTbit = 0x40000000, // RXINT/TXINT
196 CRCbit = 0x00020000, // CRCOFF/CRCEN
197 PADbit = 0x00010000, // PREADD/PADEN
890e8d0a 198 /* _Desc.size */
bcad5e53
FR		 199 RingEnd = 0x80000000,
200 /* TxDesc.status */
201 LSEN = 0x08000000, // TSO ? -- FR
202 IPCS = 0x04000000,
203 TCPCS = 0x02000000,
204 UDPCS = 0x01000000,
205 BSTEN = 0x00800000,
206 EXTEN = 0x00400000,
207 DEFEN = 0x00200000,
208 BKFEN = 0x00100000,
209 CRSEN = 0x00080000,
210 COLEN = 0x00040000,
211 THOL3 = 0x30000000,
212 THOL2 = 0x20000000,
213 THOL1 = 0x10000000,
214 THOL0 = 0x00000000,
215 /* RxDesc.status */
216 IPON = 0x20000000,
217 TCPON = 0x10000000,
218 UDPON = 0x08000000,
219 Wakup = 0x00400000,
220 Magic = 0x00200000,
221 Pause = 0x00100000,
222 DEFbit = 0x00200000,
223 BCAST = 0x000c0000,
224 MCAST = 0x00080000,
225 UCAST = 0x00040000,
226 /* RxDesc.PSize */
227 TAGON = 0x80000000,
228 RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
229 ABORT = 0x00800000,
230 SHORT = 0x00400000,
231 LIMIT = 0x00200000,
232 MIIER = 0x00100000,
233 OVRUN = 0x00080000,
234 NIBON = 0x00040000,
235 COLON = 0x00020000,
236 CRCOK = 0x00010000,
890e8d0a 237 RxSizeMask = 0x0000ffff
bcad5e53
FR		 238 /*
239 * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
240 * provide two (unused with Linux) Tx queues. No publically
241 * available documentation alas.
242 */
890e8d0a
FR		 243};
244
40292fb0
FR		 245enum sis190_eeprom_access_register_bits {
246 EECS = 0x00000001, // unused
247 EECLK = 0x00000002, // unused
248 EEDO = 0x00000008, // unused
249 EEDI = 0x00000004, // unused
250 EEREQ = 0x00000080,
251 EEROP = 0x00000200,
252 EEWOP = 0x00000100 // unused
253};
254
830fb7d2
FR		 255/* EEPROM Addresses */
256enum sis190_eeprom_address {
257 EEPROMSignature = 0x00,
258 EEPROMCLK = 0x01, // unused
259 EEPROMInfo = 0x02,
260 EEPROMMACAddr = 0x03
261};
262
900eb9d6
FR		 263enum sis190_feature {
264 F_HAS_RGMII = 1,
c3d6f1f2
FR		 265 F_PHY_88E1111 = 2,
266 F_PHY_BCM5461 = 4
900eb9d6
FR		 267};
268
890e8d0a
FR		 269struct sis190_private {
270 void __iomem *mmio_addr;
271 struct pci_dev *pci_dev;
c4028958 272 struct net_device *dev;
890e8d0a
FR		 273 spinlock_t lock;
274 u32 rx_buf_sz;
275 u32 cur_rx;
276 u32 cur_tx;
277 u32 dirty_rx;
278 u32 dirty_tx;
279 dma_addr_t rx_dma;
280 dma_addr_t tx_dma;
281 struct RxDesc *RxDescRing;
282 struct TxDesc *TxDescRing;
283 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
284 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
285 struct work_struct phy_task;
286 struct timer_list timer;
287 u32 msg_enable;
43afb949 288 struct mii_if_info mii_if;
fcb9821d 289 struct list_head first_phy;
900eb9d6 290 u32 features;
fcb9821d
FR		 291};
292
293struct sis190_phy {
294 struct list_head list;
295 int phy_id;
296 u16 id[2];
297 u16 status;
298 u8 type;
299};
300
301enum sis190_phy_type {
302 UNKNOWN = 0x00,
303 HOME = 0x01,
304 LAN = 0x02,
305 MIX = 0x03
306};
307
308static struct mii_chip_info {
309 const char *name;
310 u16 id[2];
311 unsigned int type;
900eb9d6 312 u32 feature;
fcb9821d 313} mii_chip_table[] = {
c3d6f1f2 314 { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, F_PHY_BCM5461 },
bd7a4448 315 { "Broadcom PHY AC131", { 0x0143, 0xbc70 }, LAN, 0 },
900eb9d6
FR		 316 { "Agere PHY ET1101B", { 0x0282, 0xf010 }, LAN, 0 },
317 { "Marvell PHY 88E1111", { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
318 { "Realtek PHY RTL8201", { 0x0000, 0x8200 }, LAN, 0 },
fcb9821d 319 { NULL, }
890e8d0a
FR		 320};
321
3c6bee1d 322static const struct {
890e8d0a 323 const char *name;
890e8d0a 324} sis_chip_info[] = {
e797637f
FR		 325 { "SiS 190 PCI Fast Ethernet adapter" },
326 { "SiS 191 PCI Gigabit Ethernet adapter" },
890e8d0a
FR		 327};
328
8ee8e922 329static struct pci_device_id sis190_pci_tbl[] = {
890e8d0a 330 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
e797637f 331 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0191), 0, 0, 1 },
890e8d0a
FR		 332 { 0, },
333};
334
335MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
336
337static int rx_copybreak = 200;
338
339static struct {
340 u32 msg_enable;
341} debug = { -1 };
342
343MODULE_DESCRIPTION("SiS sis190 Gigabit Ethernet driver");
344module_param(rx_copybreak, int, 0);
345MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
346module_param_named(debug, debug.msg_enable, int, 0);
347MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
348MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
349MODULE_VERSION(DRV_VERSION);
350MODULE_LICENSE("GPL");
351
352static const u32 sis190_intr_mask =
21461380 353 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt | LinkChange;
890e8d0a
FR		 354
355/*
356 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
357 * The chips use a 64 element hash table based on the Ethernet CRC.
358 */
f71e1309 359static const int multicast_filter_limit = 32;
890e8d0a
FR		 360
361static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
362{
363 unsigned int i;
364
365 SIS_W32(GMIIControl, ctl);
366
367 msleep(1);
368
369 for (i = 0; i < 100; i++) {
370 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
371 break;
372 msleep(1);
373 }
374
7bf3f232 375 if (i > 99)
890e8d0a
FR		 376 printk(KERN_ERR PFX "PHY command failed !\n");
377}
378
9ede109b 379static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
890e8d0a 380{
890e8d0a 381 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
9ede109b 382 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
890e8d0a
FR		 383 (((u32) val) << EhnMIIdataShift));
384}
385
9ede109b 386static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
890e8d0a 387{
890e8d0a 388 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
9ede109b 389 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
890e8d0a
FR		 390
391 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
392}
393
43afb949
FR		 394static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
395{
396 struct sis190_private *tp = netdev_priv(dev);
397
9ede109b 398 mdio_write(tp->mmio_addr, phy_id, reg, val);
43afb949
FR		 399}
400
401static int __mdio_read(struct net_device *dev, int phy_id, int reg)
402{
403 struct sis190_private *tp = netdev_priv(dev);
404
9ede109b 405 return mdio_read(tp->mmio_addr, phy_id, reg);
43afb949
FR		 406}
407
fc10c39d
FR		 408static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
409{
410 mdio_read(ioaddr, phy_id, reg);
411 return mdio_read(ioaddr, phy_id, reg);
412}
413
40292fb0 414static u16 __devinit sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
890e8d0a 415{
40292fb0 416 u16 data = 0xffff;
890e8d0a 417 unsigned int i;
890e8d0a
FR		 418
419 if (!(SIS_R32(ROMControl) & 0x0002))
420 return 0;
421
40292fb0 422 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
890e8d0a
FR		 423
424 for (i = 0; i < 200; i++) {
40292fb0
FR		 425 if (!(SIS_R32(ROMInterface) & EEREQ)) {
426 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
890e8d0a 427 break;
40292fb0 428 }
890e8d0a
FR		 429 msleep(1);
430 }
431
890e8d0a
FR		 432 return data;
433}
434
435static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
436{
437 SIS_W32(IntrMask, 0x00);
438 SIS_W32(IntrStatus, 0xffffffff);
439 SIS_PCI_COMMIT();
440}
441
442static void sis190_asic_down(void __iomem *ioaddr)
443{
444 /* Stop the chip's Tx and Rx DMA processes. */
445
446 SIS_W32(TxControl, 0x1a00);
447 SIS_W32(RxControl, 0x1a00);
448
449 sis190_irq_mask_and_ack(ioaddr);
450}
451
452static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
453{
454 desc->size |= cpu_to_le32(RingEnd);
455}
456
457static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
458{
459 u32 eor = le32_to_cpu(desc->size) & RingEnd;
460
461 desc->PSize = 0x0;
8b5641d4 462 desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
890e8d0a
FR		 463 wmb();
464 desc->status = cpu_to_le32(OWNbit | INTbit);
465}
466
467static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
468 u32 rx_buf_sz)
469{
470 desc->addr = cpu_to_le32(mapping);
471 sis190_give_to_asic(desc, rx_buf_sz);
472}
473
474static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
475{
476 desc->PSize = 0x0;
961994a0 477 desc->addr = cpu_to_le32(0xdeadbeef);
890e8d0a
FR		 478 desc->size &= cpu_to_le32(RingEnd);
479 wmb();
480 desc->status = 0x0;
481}
482
4709aa59
SH		 483static struct sk_buff *sis190_alloc_rx_skb(struct pci_dev *pdev,
484 struct RxDesc *desc, u32 rx_buf_sz)
890e8d0a
FR		 485{
486 struct sk_buff *skb;
890e8d0a
FR		 487
488 skb = dev_alloc_skb(rx_buf_sz);
4709aa59
SH		 489 if (likely(skb)) {
490 dma_addr_t mapping;
890e8d0a 491
4709aa59
SH		 492 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
493 PCI_DMA_FROMDEVICE);
494 sis190_map_to_asic(desc, mapping, rx_buf_sz);
495 } else
496 sis190_make_unusable_by_asic(desc);
890e8d0a 497
4709aa59 498 return skb;
890e8d0a
FR		 499}
500
501static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
502 u32 start, u32 end)
503{
504 u32 cur;
505
506 for (cur = start; cur < end; cur++) {
4709aa59 507 unsigned int i = cur % NUM_RX_DESC;
890e8d0a
FR		 508
509 if (tp->Rx_skbuff[i])
510 continue;
511
4709aa59
SH		 512 tp->Rx_skbuff[i] = sis190_alloc_rx_skb(tp->pci_dev,
513 tp->RxDescRing + i,
514 tp->rx_buf_sz);
515 if (!tp->Rx_skbuff[i])
890e8d0a
FR		 516 break;
517 }
518 return cur - start;
519}
520
521static inline int sis190_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
522 struct RxDesc *desc, int rx_buf_sz)
523{
524 int ret = -1;
525
526 if (pkt_size < rx_copybreak) {
527 struct sk_buff *skb;
528
e3eccad9 529 skb = dev_alloc_skb(pkt_size + 2);
890e8d0a 530 if (skb) {
e3eccad9 531 skb_reserve(skb, 2);
8c7b7faa 532 skb_copy_to_linear_data(skb, sk_buff[0]->data, pkt_size);
890e8d0a
FR		 533 *sk_buff = skb;
534 sis190_give_to_asic(desc, rx_buf_sz);
535 ret = 0;
536 }
537 }
538 return ret;
539}
540
bcad5e53
FR		 541static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
542{
543#define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
544
545 if ((status & CRCOK) && !(status & ErrMask))
546 return 0;
547
548 if (!(status & CRCOK))
549 stats->rx_crc_errors++;
550 else if (status & OVRUN)
551 stats->rx_over_errors++;
552 else if (status & (SHORT | LIMIT))
553 stats->rx_length_errors++;
554 else if (status & (MIIER | NIBON | COLON))
555 stats->rx_frame_errors++;
556
557 stats->rx_errors++;
558 return -1;
559}
560
890e8d0a
FR		 561static int sis190_rx_interrupt(struct net_device *dev,
562 struct sis190_private *tp, void __iomem *ioaddr)
563{
09f75cd7 564 struct net_device_stats *stats = &dev->stats;
890e8d0a
FR		 565 u32 rx_left, cur_rx = tp->cur_rx;
566 u32 delta, count;
567
568 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
569 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
570
571 for (; rx_left > 0; rx_left--, cur_rx++) {
572 unsigned int entry = cur_rx % NUM_RX_DESC;
573 struct RxDesc *desc = tp->RxDescRing + entry;
574 u32 status;
575
961994a0 576 if (le32_to_cpu(desc->status) & OWNbit)
890e8d0a
FR		 577 break;
578
579 status = le32_to_cpu(desc->PSize);
580
581 // net_intr(tp, KERN_INFO "%s: Rx PSize = %08x.\n", dev->name,
582 // status);
583
bcad5e53 584 if (sis190_rx_pkt_err(status, stats) < 0)
890e8d0a 585 sis190_give_to_asic(desc, tp->rx_buf_sz);
bcad5e53 586 else {
890e8d0a
FR		 587 struct sk_buff *skb = tp->Rx_skbuff[entry];
588 int pkt_size = (status & RxSizeMask) - 4;
589 void (*pci_action)(struct pci_dev *, dma_addr_t,
590 size_t, int) = pci_dma_sync_single_for_device;
591
592 if (unlikely(pkt_size > tp->rx_buf_sz)) {
593 net_intr(tp, KERN_INFO
594 "%s: (frag) status = %08x.\n",
595 dev->name, status);
596 stats->rx_dropped++;
597 stats->rx_length_errors++;
598 sis190_give_to_asic(desc, tp->rx_buf_sz);
599 continue;
600 }
601
602 pci_dma_sync_single_for_cpu(tp->pci_dev,
603 le32_to_cpu(desc->addr), tp->rx_buf_sz,
604 PCI_DMA_FROMDEVICE);
605
606 if (sis190_try_rx_copy(&skb, pkt_size, desc,
607 tp->rx_buf_sz)) {
608 pci_action = pci_unmap_single;
609 tp->Rx_skbuff[entry] = NULL;
610 sis190_make_unusable_by_asic(desc);
611 }
612
613 pci_action(tp->pci_dev, le32_to_cpu(desc->addr),
614 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
615
890e8d0a
FR		 616 skb_put(skb, pkt_size);
617 skb->protocol = eth_type_trans(skb, dev);
618
619 sis190_rx_skb(skb);
620
621 dev->last_rx = jiffies;
890e8d0a 622 stats->rx_packets++;
bcad5e53
FR		 623 stats->rx_bytes += pkt_size;
624 if ((status & BCAST) == MCAST)
625 stats->multicast++;
890e8d0a
FR		 626 }
627 }
628 count = cur_rx - tp->cur_rx;
629 tp->cur_rx = cur_rx;
630
631 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
632 if (!delta && count && netif_msg_intr(tp))
633 printk(KERN_INFO "%s: no Rx buffer allocated.\n", dev->name);
634 tp->dirty_rx += delta;
635
636 if (((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx) && netif_msg_intr(tp))
637 printk(KERN_EMERG "%s: Rx buffers exhausted.\n", dev->name);
638
639 return count;
640}
641
642static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
643 struct TxDesc *desc)
644{
645 unsigned int len;
646
647 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
648
649 pci_unmap_single(pdev, le32_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
650
651 memset(desc, 0x00, sizeof(*desc));
652}
653
654static void sis190_tx_interrupt(struct net_device *dev,
655 struct sis190_private *tp, void __iomem *ioaddr)
656{
657 u32 pending, dirty_tx = tp->dirty_tx;
658 /*
659 * It would not be needed if queueing was allowed to be enabled
660 * again too early (hint: think preempt and unclocked smp systems).
661 */
662 unsigned int queue_stopped;
663
664 smp_rmb();
665 pending = tp->cur_tx - dirty_tx;
666 queue_stopped = (pending == NUM_TX_DESC);
667
668 for (; pending; pending--, dirty_tx++) {
669 unsigned int entry = dirty_tx % NUM_TX_DESC;
670 struct TxDesc *txd = tp->TxDescRing + entry;
671 struct sk_buff *skb;
672
673 if (le32_to_cpu(txd->status) & OWNbit)
674 break;
675
676 skb = tp->Tx_skbuff[entry];
677
09f75cd7
JG		 678 dev->stats.tx_packets++;
679 dev->stats.tx_bytes += skb->len;
890e8d0a
FR		 680
681 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
682 tp->Tx_skbuff[entry] = NULL;
683 dev_kfree_skb_irq(skb);
684 }
685
686 if (tp->dirty_tx != dirty_tx) {
687 tp->dirty_tx = dirty_tx;
688 smp_wmb();
689 if (queue_stopped)
690 netif_wake_queue(dev);
691 }
692}
693
694/*
695 * The interrupt handler does all of the Rx thread work and cleans up after
696 * the Tx thread.
697 */
7d12e780 698static irqreturn_t sis190_interrupt(int irq, void *__dev)
890e8d0a
FR		 699{
700 struct net_device *dev = __dev;
701 struct sis190_private *tp = netdev_priv(dev);
702 void __iomem *ioaddr = tp->mmio_addr;
703 unsigned int handled = 0;
704 u32 status;
705
706 status = SIS_R32(IntrStatus);
707
708 if ((status == 0xffffffff) || !status)
709 goto out;
710
711 handled = 1;
712
713 if (unlikely(!netif_running(dev))) {
714 sis190_asic_down(ioaddr);
715 goto out;
716 }
717
718 SIS_W32(IntrStatus, status);
719
720 // net_intr(tp, KERN_INFO "%s: status = %08x.\n", dev->name, status);
721
722 if (status & LinkChange) {
723 net_intr(tp, KERN_INFO "%s: link change.\n", dev->name);
724 schedule_work(&tp->phy_task);
725 }
726
727 if (status & RxQInt)
728 sis190_rx_interrupt(dev, tp, ioaddr);
729
730 if (status & TxQ0Int)
731 sis190_tx_interrupt(dev, tp, ioaddr);
732out:
733 return IRQ_RETVAL(handled);
734}
735
4405d3b5
FR		 736#ifdef CONFIG_NET_POLL_CONTROLLER
737static void sis190_netpoll(struct net_device *dev)
738{
739 struct sis190_private *tp = netdev_priv(dev);
740 struct pci_dev *pdev = tp->pci_dev;
741
742 disable_irq(pdev->irq);
7d12e780 743 sis190_interrupt(pdev->irq, dev);
4405d3b5
FR		 744 enable_irq(pdev->irq);
745}
746#endif
747
890e8d0a
FR		 748static void sis190_free_rx_skb(struct sis190_private *tp,
749 struct sk_buff **sk_buff, struct RxDesc *desc)
750{
751 struct pci_dev *pdev = tp->pci_dev;
752
753 pci_unmap_single(pdev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
754 PCI_DMA_FROMDEVICE);
755 dev_kfree_skb(*sk_buff);
756 *sk_buff = NULL;
757 sis190_make_unusable_by_asic(desc);
758}
759
760static void sis190_rx_clear(struct sis190_private *tp)
761{
762 unsigned int i;
763
764 for (i = 0; i < NUM_RX_DESC; i++) {
765 if (!tp->Rx_skbuff[i])
766 continue;
767 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
768 }
769}
770
771static void sis190_init_ring_indexes(struct sis190_private *tp)
772{
773 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
774}
775
776static int sis190_init_ring(struct net_device *dev)
777{
778 struct sis190_private *tp = netdev_priv(dev);
779
780 sis190_init_ring_indexes(tp);
781
782 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
783 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
784
785 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
786 goto err_rx_clear;
787
788 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
789
790 return 0;
791
792err_rx_clear:
793 sis190_rx_clear(tp);
794 return -ENOMEM;
795}
796
797static void sis190_set_rx_mode(struct net_device *dev)
798{
799 struct sis190_private *tp = netdev_priv(dev);
800 void __iomem *ioaddr = tp->mmio_addr;
801 unsigned long flags;
802 u32 mc_filter[2]; /* Multicast hash filter */
803 u16 rx_mode;
804
805 if (dev->flags & IFF_PROMISC) {
890e8d0a
FR		 806 rx_mode =
807 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
808 AcceptAllPhys;
809 mc_filter[1] = mc_filter[0] = 0xffffffff;
810 } else if ((dev->mc_count > multicast_filter_limit) ||
811 (dev->flags & IFF_ALLMULTI)) {
812 /* Too many to filter perfectly -- accept all multicasts. */
813 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
814 mc_filter[1] = mc_filter[0] = 0xffffffff;
815 } else {
816 struct dev_mc_list *mclist;
817 unsigned int i;
818
819 rx_mode = AcceptBroadcast | AcceptMyPhys;
820 mc_filter[1] = mc_filter[0] = 0;
821 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
822 i++, mclist = mclist->next) {
823 int bit_nr =
8fee5f51 824 ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
890e8d0a
FR		 825 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
826 rx_mode |= AcceptMulticast;
827 }
828 }
829
830 spin_lock_irqsave(&tp->lock, flags);
831
832 SIS_W16(RxMacControl, rx_mode | 0x2);
833 SIS_W32(RxHashTable, mc_filter[0]);
834 SIS_W32(RxHashTable + 4, mc_filter[1]);
835
836 spin_unlock_irqrestore(&tp->lock, flags);
837}
838
839static void sis190_soft_reset(void __iomem *ioaddr)
840{
841 SIS_W32(IntrControl, 0x8000);
842 SIS_PCI_COMMIT();
890e8d0a
FR		 843 SIS_W32(IntrControl, 0x0);
844 sis190_asic_down(ioaddr);
890e8d0a
FR		 845}
846
847static void sis190_hw_start(struct net_device *dev)
848{
849 struct sis190_private *tp = netdev_priv(dev);
850 void __iomem *ioaddr = tp->mmio_addr;
851
852 sis190_soft_reset(ioaddr);
853
854 SIS_W32(TxDescStartAddr, tp->tx_dma);
855 SIS_W32(RxDescStartAddr, tp->rx_dma);
856
857 SIS_W32(IntrStatus, 0xffffffff);
858 SIS_W32(IntrMask, 0x0);
890e8d0a
FR		 859 SIS_W32(GMIIControl, 0x0);
860 SIS_W32(TxMacControl, 0x60);
861 SIS_W16(RxMacControl, 0x02);
862 SIS_W32(RxHashTable, 0x0);
863 SIS_W32(0x6c, 0x0);
188f23ba
FR		 864 SIS_W32(RxWolCtrl, 0x0);
865 SIS_W32(RxWolData, 0x0);
890e8d0a
FR		 866
867 SIS_PCI_COMMIT();
868
869 sis190_set_rx_mode(dev);
870
871 /* Enable all known interrupts by setting the interrupt mask. */
872 SIS_W32(IntrMask, sis190_intr_mask);
873
874 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
875 SIS_W32(RxControl, 0x1a1d);
876
877 netif_start_queue(dev);
878}
879
c4028958 880static void sis190_phy_task(struct work_struct *work)
890e8d0a 881{
c4028958
DH		 882 struct sis190_private *tp =
883 container_of(work, struct sis190_private, phy_task);
884 struct net_device *dev = tp->dev;
890e8d0a 885 void __iomem *ioaddr = tp->mmio_addr;
9ede109b 886 int phy_id = tp->mii_if.phy_id;
890e8d0a
FR		 887 u16 val;
888
43afb949
FR		 889 rtnl_lock();
890
c014f6c8
FR		 891 if (!netif_running(dev))
892 goto out_unlock;
893
9ede109b 894 val = mdio_read(ioaddr, phy_id, MII_BMCR);
890e8d0a
FR		 895 if (val & BMCR_RESET) {
896 // FIXME: needlessly high ? -- FR 02/07/2005
897 mod_timer(&tp->timer, jiffies + HZ/10);
fc10c39d
FR		 898 } else if (!(mdio_read_latched(ioaddr, phy_id, MII_BMSR) &
899 BMSR_ANEGCOMPLETE)) {
890e8d0a
FR		 900 net_link(tp, KERN_WARNING "%s: PHY reset until link up.\n",
901 dev->name);
21461380 902 netif_carrier_off(dev);
9ede109b 903 mdio_write(ioaddr, phy_id, MII_BMCR, val | BMCR_RESET);
890e8d0a
FR		 904 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
905 } else {
906 /* Rejoice ! */
907 struct {
908 int val;
6614a6dc 909 u32 ctl;
890e8d0a 910 const char *msg;
890e8d0a 911 } reg31[] = {
6614a6dc
FR		 912 { LPA_1000XFULL | LPA_SLCT, 0x07000c00 | 0x00001000,
913 "1000 Mbps Full Duplex" },
914 { LPA_1000XHALF | LPA_SLCT, 0x07000c00,
915 "1000 Mbps Half Duplex" },
916 { LPA_100FULL, 0x04000800 | 0x00001000,
917 "100 Mbps Full Duplex" },
918 { LPA_100HALF, 0x04000800,
919 "100 Mbps Half Duplex" },
920 { LPA_10FULL, 0x04000400 | 0x00001000,
921 "10 Mbps Full Duplex" },
922 { LPA_10HALF, 0x04000400,
923 "10 Mbps Half Duplex" },
924 { 0, 0x04000400, "unknown" }
925 }, *p;
8348b4db 926 u16 adv;
890e8d0a 927
9ede109b 928 val = mdio_read(ioaddr, phy_id, 0x1f);
890e8d0a
FR		 929 net_link(tp, KERN_INFO "%s: mii ext = %04x.\n", dev->name, val);
930
9ede109b 931 val = mdio_read(ioaddr, phy_id, MII_LPA);
8348b4db
FR		 932 adv = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
933 net_link(tp, KERN_INFO "%s: mii lpa = %04x adv = %04x.\n",
934 dev->name, val, adv);
935
936 val &= adv;
890e8d0a 937
6614a6dc 938 for (p = reg31; p->val; p++) {
890e8d0a
FR		 939 if ((val & p->val) == p->val)
940 break;
941 }
6614a6dc
FR		 942
943 p->ctl |= SIS_R32(StationControl) & ~0x0f001c00;
944
c3d6f1f2
FR		 945 if ((tp->features & F_HAS_RGMII) &&
946 (tp->features & F_PHY_BCM5461)) {
947 // Set Tx Delay in RGMII mode.
948 mdio_write(ioaddr, phy_id, 0x18, 0xf1c7);
949 udelay(200);
950 mdio_write(ioaddr, phy_id, 0x1c, 0x8c00);
951 p->ctl |= 0x03000000;
952 }
953
6614a6dc
FR		 954 SIS_W32(StationControl, p->ctl);
955
c3d6f1f2
FR		 956 if (tp->features & F_HAS_RGMII) {
957 SIS_W32(RGDelay, 0x0441);
958 SIS_W32(RGDelay, 0x0440);
959 }
960
890e8d0a
FR		 961 net_link(tp, KERN_INFO "%s: link on %s mode.\n", dev->name,
962 p->msg);
963 netif_carrier_on(dev);
964 }
43afb949 965
c014f6c8 966out_unlock:
43afb949 967 rtnl_unlock();
890e8d0a
FR		 968}
969
970static void sis190_phy_timer(unsigned long __opaque)
971{
972 struct net_device *dev = (struct net_device *)__opaque;
973 struct sis190_private *tp = netdev_priv(dev);
974
975 if (likely(netif_running(dev)))
976 schedule_work(&tp->phy_task);
977}
978
979static inline void sis190_delete_timer(struct net_device *dev)
980{
981 struct sis190_private *tp = netdev_priv(dev);
982
983 del_timer_sync(&tp->timer);
984}
985
986static inline void sis190_request_timer(struct net_device *dev)
987{
988 struct sis190_private *tp = netdev_priv(dev);
989 struct timer_list *timer = &tp->timer;
990
991 init_timer(timer);
992 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
993 timer->data = (unsigned long)dev;
994 timer->function = sis190_phy_timer;
995 add_timer(timer);
996}
997
998static void sis190_set_rxbufsize(struct sis190_private *tp,
999 struct net_device *dev)
1000{
1001 unsigned int mtu = dev->mtu;
1002
1003 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
8b5641d4
FR		 1004 /* RxDesc->size has a licence to kill the lower bits */
1005 if (tp->rx_buf_sz & 0x07) {
1006 tp->rx_buf_sz += 8;
1007 tp->rx_buf_sz &= RX_BUF_MASK;
1008 }
890e8d0a
FR		 1009}
1010
1011static int sis190_open(struct net_device *dev)
1012{
1013 struct sis190_private *tp = netdev_priv(dev);
1014 struct pci_dev *pdev = tp->pci_dev;
1015 int rc = -ENOMEM;
1016
1017 sis190_set_rxbufsize(tp, dev);
1018
1019 /*
1020 * Rx and Tx descriptors need 256 bytes alignment.
1021 * pci_alloc_consistent() guarantees a stronger alignment.
1022 */
1023 tp->TxDescRing = pci_alloc_consistent(pdev, TX_RING_BYTES, &tp->tx_dma);
1024 if (!tp->TxDescRing)
1025 goto out;
1026
1027 tp->RxDescRing = pci_alloc_consistent(pdev, RX_RING_BYTES, &tp->rx_dma);
1028 if (!tp->RxDescRing)
1029 goto err_free_tx_0;
1030
1031 rc = sis190_init_ring(dev);
1032 if (rc < 0)
1033 goto err_free_rx_1;
1034
890e8d0a
FR		 1035 sis190_request_timer(dev);
1036
1fb9df5d 1037 rc = request_irq(dev->irq, sis190_interrupt, IRQF_SHARED, dev->name, dev);
890e8d0a
FR		 1038 if (rc < 0)
1039 goto err_release_timer_2;
1040
1041 sis190_hw_start(dev);
1042out:
1043 return rc;
1044
1045err_release_timer_2:
1046 sis190_delete_timer(dev);
1047 sis190_rx_clear(tp);
1048err_free_rx_1:
1049 pci_free_consistent(tp->pci_dev, RX_RING_BYTES, tp->RxDescRing,
1050 tp->rx_dma);
1051err_free_tx_0:
1052 pci_free_consistent(tp->pci_dev, TX_RING_BYTES, tp->TxDescRing,
1053 tp->tx_dma);
1054 goto out;
1055}
1056
1057static void sis190_tx_clear(struct sis190_private *tp)
1058{
1059 unsigned int i;
1060
1061 for (i = 0; i < NUM_TX_DESC; i++) {
1062 struct sk_buff *skb = tp->Tx_skbuff[i];
1063
1064 if (!skb)
1065 continue;
1066
1067 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1068 tp->Tx_skbuff[i] = NULL;
1069 dev_kfree_skb(skb);
1070
09f75cd7 1071 tp->dev->stats.tx_dropped++;
890e8d0a
FR		 1072 }
1073 tp->cur_tx = tp->dirty_tx = 0;
1074}
1075
1076static void sis190_down(struct net_device *dev)
1077{
1078 struct sis190_private *tp = netdev_priv(dev);
1079 void __iomem *ioaddr = tp->mmio_addr;
1080 unsigned int poll_locked = 0;
1081
1082 sis190_delete_timer(dev);
1083
1084 netif_stop_queue(dev);
1085
890e8d0a
FR		 1086 do {
1087 spin_lock_irq(&tp->lock);
1088
1089 sis190_asic_down(ioaddr);
1090
1091 spin_unlock_irq(&tp->lock);
1092
1093 synchronize_irq(dev->irq);
1094
bea3348e 1095 if (!poll_locked)
890e8d0a 1096 poll_locked++;
890e8d0a
FR		 1097
1098 synchronize_sched();
1099
1100 } while (SIS_R32(IntrMask));
1101
1102 sis190_tx_clear(tp);
1103 sis190_rx_clear(tp);
1104}
1105
1106static int sis190_close(struct net_device *dev)
1107{
1108 struct sis190_private *tp = netdev_priv(dev);
1109 struct pci_dev *pdev = tp->pci_dev;
1110
1111 sis190_down(dev);
1112
1113 free_irq(dev->irq, dev);
1114
890e8d0a
FR		 1115 pci_free_consistent(pdev, TX_RING_BYTES, tp->TxDescRing, tp->tx_dma);
1116 pci_free_consistent(pdev, RX_RING_BYTES, tp->RxDescRing, tp->rx_dma);
1117
1118 tp->TxDescRing = NULL;
1119 tp->RxDescRing = NULL;
1120
1121 return 0;
1122}
1123
1124static int sis190_start_xmit(struct sk_buff *skb, struct net_device *dev)
1125{
1126 struct sis190_private *tp = netdev_priv(dev);
1127 void __iomem *ioaddr = tp->mmio_addr;
1128 u32 len, entry, dirty_tx;
1129 struct TxDesc *desc;
1130 dma_addr_t mapping;
1131
1132 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 1133 if (skb_padto(skb, ETH_ZLEN)) {
09f75cd7 1134 dev->stats.tx_dropped++;
890e8d0a
FR		 1135 goto out;
1136 }
1137 len = ETH_ZLEN;
1138 } else {
1139 len = skb->len;
1140 }
1141
1142 entry = tp->cur_tx % NUM_TX_DESC;
1143 desc = tp->TxDescRing + entry;
1144
1145 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1146 netif_stop_queue(dev);
1147 net_tx_err(tp, KERN_ERR PFX
1148 "%s: BUG! Tx Ring full when queue awake!\n",
1149 dev->name);
1150 return NETDEV_TX_BUSY;
1151 }
1152
1153 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1154
1155 tp->Tx_skbuff[entry] = skb;
1156
1157 desc->PSize = cpu_to_le32(len);
1158 desc->addr = cpu_to_le32(mapping);
1159
1160 desc->size = cpu_to_le32(len);
1161 if (entry == (NUM_TX_DESC - 1))
1162 desc->size |= cpu_to_le32(RingEnd);
1163
1164 wmb();
1165
1166 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1167
1168 tp->cur_tx++;
1169
1170 smp_wmb();
1171
1172 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1173
1174 dev->trans_start = jiffies;
1175
1176 dirty_tx = tp->dirty_tx;
1177 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1178 netif_stop_queue(dev);
1179 smp_rmb();
1180 if (dirty_tx != tp->dirty_tx)
1181 netif_wake_queue(dev);
1182 }
1183out:
1184 return NETDEV_TX_OK;
1185}
1186
fcb9821d
FR		 1187static void sis190_free_phy(struct list_head *first_phy)
1188{
1189 struct sis190_phy *cur, *next;
1190
1191 list_for_each_entry_safe(cur, next, first_phy, list) {
1192 kfree(cur);
1193 }
1194}
1195
1196/**
1197 * sis190_default_phy - Select default PHY for sis190 mac.
1198 * @dev: the net device to probe for
1199 *
1200 * Select first detected PHY with link as default.
1201 * If no one is link on, select PHY whose types is HOME as default.
1202 * If HOME doesn't exist, select LAN.
1203 */
1204static u16 sis190_default_phy(struct net_device *dev)
1205{
1206 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1207 struct sis190_private *tp = netdev_priv(dev);
1208 struct mii_if_info *mii_if = &tp->mii_if;
1209 void __iomem *ioaddr = tp->mmio_addr;
1210 u16 status;
1211
1212 phy_home = phy_default = phy_lan = NULL;
1213
1214 list_for_each_entry(phy, &tp->first_phy, list) {
1215 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1216
1217 // Link ON & Not select default PHY & not ghost PHY.
1218 if ((status & BMSR_LSTATUS) &&
1219 !phy_default &&
1220 (phy->type != UNKNOWN)) {
1221 phy_default = phy;
1222 } else {
1223 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1224 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1225 status | BMCR_ANENABLE | BMCR_ISOLATE);
1226 if (phy->type == HOME)
1227 phy_home = phy;
1228 else if (phy->type == LAN)
1229 phy_lan = phy;
1230 }
1231 }
1232
1233 if (!phy_default) {
1234 if (phy_home)
1235 phy_default = phy_home;
1236 else if (phy_lan)
1237 phy_default = phy_lan;
1238 else
1239 phy_default = list_entry(&tp->first_phy,
1240 struct sis190_phy, list);
1241 }
1242
1243 if (mii_if->phy_id != phy_default->phy_id) {
1244 mii_if->phy_id = phy_default->phy_id;
1245 net_probe(tp, KERN_INFO
1246 "%s: Using transceiver at address %d as default.\n",
3690b6c1 1247 pci_name(tp->pci_dev), mii_if->phy_id);
fcb9821d
FR		 1248 }
1249
1250 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1251 status &= (~BMCR_ISOLATE);
1252
1253 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1254 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1255
1256 return status;
1257}
1258
1259static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1260 struct sis190_phy *phy, unsigned int phy_id,
1261 u16 mii_status)
1262{
1263 void __iomem *ioaddr = tp->mmio_addr;
1264 struct mii_chip_info *p;
1265
1266 INIT_LIST_HEAD(&phy->list);
1267 phy->status = mii_status;
1268 phy->phy_id = phy_id;
1269
1270 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1271 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1272
1273 for (p = mii_chip_table; p->type; p++) {
1274 if ((p->id[0] == phy->id[0]) &&
1275 (p->id[1] == (phy->id[1] & 0xfff0))) {
1276 break;
1277 }
1278 }
1279
1280 if (p->id[1]) {
1281 phy->type = (p->type == MIX) ?
1282 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1283 LAN : HOME) : p->type;
900eb9d6 1284 tp->features |= p->feature;
fcb9821d
FR		 1285 } else
1286 phy->type = UNKNOWN;
1287
1288 net_probe(tp, KERN_INFO "%s: %s transceiver at address %d.\n",
3690b6c1
FR		 1289 pci_name(tp->pci_dev),
1290 (phy->type == UNKNOWN) ? "Unknown PHY" : p->name, phy_id);
fcb9821d
FR		 1291}
1292
900eb9d6
FR		 1293static void sis190_mii_probe_88e1111_fixup(struct sis190_private *tp)
1294{
1295 if (tp->features & F_PHY_88E1111) {
1296 void __iomem *ioaddr = tp->mmio_addr;
1297 int phy_id = tp->mii_if.phy_id;
1298 u16 reg[2][2] = {
1299 { 0x808b, 0x0ce1 },
1300 { 0x808f, 0x0c60 }
1301 }, *p;
1302
1303 p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];
1304
1305 mdio_write(ioaddr, phy_id, 0x1b, p[0]);
1306 udelay(200);
1307 mdio_write(ioaddr, phy_id, 0x14, p[1]);
1308 udelay(200);
1309 }
1310}
1311
fcb9821d
FR		 1312/**
1313 * sis190_mii_probe - Probe MII PHY for sis190
1314 * @dev: the net device to probe for
1315 *
1316 * Search for total of 32 possible mii phy addresses.
1317 * Identify and set current phy if found one,
1318 * return error if it failed to found.
1319 */
1320static int __devinit sis190_mii_probe(struct net_device *dev)
1321{
1322 struct sis190_private *tp = netdev_priv(dev);
1323 struct mii_if_info *mii_if = &tp->mii_if;
1324 void __iomem *ioaddr = tp->mmio_addr;
1325 int phy_id;
1326 int rc = 0;
1327
1328 INIT_LIST_HEAD(&tp->first_phy);
1329
1330 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1331 struct sis190_phy *phy;
1332 u16 status;
1333
1334 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1335
1336 // Try next mii if the current one is not accessible.
1337 if (status == 0xffff || status == 0x0000)
1338 continue;
1339
1340 phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1341 if (!phy) {
1342 sis190_free_phy(&tp->first_phy);
1343 rc = -ENOMEM;
1344 goto out;
1345 }
1346
1347 sis190_init_phy(dev, tp, phy, phy_id, status);
1348
1349 list_add(&tp->first_phy, &phy->list);
1350 }
1351
1352 if (list_empty(&tp->first_phy)) {
1353 net_probe(tp, KERN_INFO "%s: No MII transceivers found!\n",
3690b6c1 1354 pci_name(tp->pci_dev));
fcb9821d
FR		 1355 rc = -EIO;
1356 goto out;
1357 }
1358
1359 /* Select default PHY for mac */
1360 sis190_default_phy(dev);
1361
900eb9d6
FR		 1362 sis190_mii_probe_88e1111_fixup(tp);
1363
fcb9821d
FR		 1364 mii_if->dev = dev;
1365 mii_if->mdio_read = __mdio_read;
1366 mii_if->mdio_write = __mdio_write;
1367 mii_if->phy_id_mask = PHY_ID_ANY;
1368 mii_if->reg_num_mask = MII_REG_ANY;
1369out:
1370 return rc;
1371}
1372
c2b75f0c 1373static void sis190_mii_remove(struct net_device *dev)
fcb9821d
FR		 1374{
1375 struct sis190_private *tp = netdev_priv(dev);
1376
1377 sis190_free_phy(&tp->first_phy);
1378}
1379
890e8d0a
FR		 1380static void sis190_release_board(struct pci_dev *pdev)
1381{
1382 struct net_device *dev = pci_get_drvdata(pdev);
1383 struct sis190_private *tp = netdev_priv(dev);
1384
1385 iounmap(tp->mmio_addr);
1386 pci_release_regions(pdev);
1387 pci_disable_device(pdev);
1388 free_netdev(dev);
1389}
1390
1391static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
1392{
1393 struct sis190_private *tp;
1394 struct net_device *dev;
1395 void __iomem *ioaddr;
1396 int rc;
1397
1398 dev = alloc_etherdev(sizeof(*tp));
1399 if (!dev) {
1400 net_drv(&debug, KERN_ERR PFX "unable to alloc new ethernet\n");
1401 rc = -ENOMEM;
1402 goto err_out_0;
1403 }
1404
890e8d0a
FR		 1405 SET_NETDEV_DEV(dev, &pdev->dev);
1406
1407 tp = netdev_priv(dev);
c4028958 1408 tp->dev = dev;
890e8d0a
FR		 1409 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1410
1411 rc = pci_enable_device(pdev);
1412 if (rc < 0) {
1413 net_probe(tp, KERN_ERR "%s: enable failure\n", pci_name(pdev));
1414 goto err_free_dev_1;
1415 }
1416
1417 rc = -ENODEV;
1418
1419 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1420 net_probe(tp, KERN_ERR "%s: region #0 is no MMIO resource.\n",
1421 pci_name(pdev));
1422 goto err_pci_disable_2;
1423 }
1424 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1425 net_probe(tp, KERN_ERR "%s: invalid PCI region size(s).\n",
1426 pci_name(pdev));
1427 goto err_pci_disable_2;
1428 }
1429
1430 rc = pci_request_regions(pdev, DRV_NAME);
1431 if (rc < 0) {
1432 net_probe(tp, KERN_ERR PFX "%s: could not request regions.\n",
1433 pci_name(pdev));
1434 goto err_pci_disable_2;
1435 }
1436
1437 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1438 if (rc < 0) {
1439 net_probe(tp, KERN_ERR "%s: DMA configuration failed.\n",
1440 pci_name(pdev));
1441 goto err_free_res_3;
1442 }
1443
1444 pci_set_master(pdev);
1445
1446 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1447 if (!ioaddr) {
1448 net_probe(tp, KERN_ERR "%s: cannot remap MMIO, aborting\n",
1449 pci_name(pdev));
1450 rc = -EIO;
1451 goto err_free_res_3;
1452 }
1453
1454 tp->pci_dev = pdev;
1455 tp->mmio_addr = ioaddr;
1456
1457 sis190_irq_mask_and_ack(ioaddr);
1458
1459 sis190_soft_reset(ioaddr);
1460out:
1461 return dev;
1462
1463err_free_res_3:
1464 pci_release_regions(pdev);
1465err_pci_disable_2:
1466 pci_disable_device(pdev);
1467err_free_dev_1:
1468 free_netdev(dev);
1469err_out_0:
1470 dev = ERR_PTR(rc);
1471 goto out;
1472}
1473
1474static void sis190_tx_timeout(struct net_device *dev)
1475{
1476 struct sis190_private *tp = netdev_priv(dev);
1477 void __iomem *ioaddr = tp->mmio_addr;
1478 u8 tmp8;
1479
1480 /* Disable Tx, if not already */
1481 tmp8 = SIS_R8(TxControl);
1482 if (tmp8 & CmdTxEnb)
1483 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1484
188f23ba
FR		 1485
1486 net_tx_err(tp, KERN_INFO "%s: Transmit timeout, status %08x %08x.\n",
1487 dev->name, SIS_R32(TxControl), SIS_R32(TxSts));
1488
890e8d0a
FR		 1489 /* Disable interrupts by clearing the interrupt mask. */
1490 SIS_W32(IntrMask, 0x0000);
1491
1492 /* Stop a shared interrupt from scavenging while we are. */
1493 spin_lock_irq(&tp->lock);
1494 sis190_tx_clear(tp);
1495 spin_unlock_irq(&tp->lock);
1496
1497 /* ...and finally, reset everything. */
1498 sis190_hw_start(dev);
1499
1500 netif_wake_queue(dev);
1501}
1502
900eb9d6
FR		 1503static void sis190_set_rgmii(struct sis190_private *tp, u8 reg)
1504{
1505 tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;
1506}
1507
830fb7d2
FR		 1508static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1509 struct net_device *dev)
1510{
1511 struct sis190_private *tp = netdev_priv(dev);
1512 void __iomem *ioaddr = tp->mmio_addr;
1513 u16 sig;
1514 int i;
1515
1516 net_probe(tp, KERN_INFO "%s: Read MAC address from EEPROM\n",
1517 pci_name(pdev));
1518
1519 /* Check to see if there is a sane EEPROM */
1520 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1521
1522 if ((sig == 0xffff) || (sig == 0x0000)) {
1523 net_probe(tp, KERN_INFO "%s: Error EEPROM read %x.\n",
1524 pci_name(pdev), sig);
1525 return -EIO;
1526 }
1527
1528 /* Get MAC address from EEPROM */
1529 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
961994a0 1530 u16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
830fb7d2 1531
961994a0 1532 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(w);
830fb7d2
FR		 1533 }
1534
900eb9d6
FR		 1535 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
1536
830fb7d2
FR		 1537 return 0;
1538}
1539
1540/**
ebc71647 1541 * sis190_get_mac_addr_from_apc - Get MAC address for SiS96x model
830fb7d2
FR		 1542 * @pdev: PCI device
1543 * @dev: network device to get address for
1544 *
ebc71647 1545 * SiS96x model, use APC CMOS RAM to store MAC address.
830fb7d2
FR		 1546 * APC CMOS RAM is accessed through ISA bridge.
1547 * MAC address is read into @net_dev->dev_addr.
1548 */
1549static int __devinit sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1550 struct net_device *dev)
1551{
ebc71647 1552 static const u16 __devinitdata ids[] = { 0x0965, 0x0966, 0x0968 };
830fb7d2
FR		 1553 struct sis190_private *tp = netdev_priv(dev);
1554 struct pci_dev *isa_bridge;
1555 u8 reg, tmp8;
ebc71647 1556 unsigned int i;
830fb7d2
FR		 1557
1558 net_probe(tp, KERN_INFO "%s: Read MAC address from APC.\n",
1559 pci_name(pdev));
1560
ebc71647
FR		 1561 for (i = 0; i < ARRAY_SIZE(ids); i++) {
1562 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, ids[i], NULL);
1563 if (isa_bridge)
1564 break;
1565 }
8eb7ad68 1566
830fb7d2
FR		 1567 if (!isa_bridge) {
1568 net_probe(tp, KERN_INFO "%s: Can not find ISA bridge.\n",
1569 pci_name(pdev));
1570 return -EIO;
1571 }
1572
1573 /* Enable port 78h & 79h to access APC Registers. */
1574 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1575 reg = (tmp8 & ~0x02);
1576 pci_write_config_byte(isa_bridge, 0x48, reg);
1577 udelay(50);
1578 pci_read_config_byte(isa_bridge, 0x48, &reg);
1579
1580 for (i = 0; i < MAC_ADDR_LEN; i++) {
1581 outb(0x9 + i, 0x78);
1582 dev->dev_addr[i] = inb(0x79);
1583 }
1584
1585 outb(0x12, 0x78);
1586 reg = inb(0x79);
1587
900eb9d6
FR		 1588 sis190_set_rgmii(tp, reg);
1589
830fb7d2
FR		 1590 /* Restore the value to ISA Bridge */
1591 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1592 pci_dev_put(isa_bridge);
1593
1594 return 0;
1595}
1596
1597/**
1598 * sis190_init_rxfilter - Initialize the Rx filter
1599 * @dev: network device to initialize
1600 *
1601 * Set receive filter address to our MAC address
1602 * and enable packet filtering.
1603 */
1604static inline void sis190_init_rxfilter(struct net_device *dev)
1605{
1606 struct sis190_private *tp = netdev_priv(dev);
1607 void __iomem *ioaddr = tp->mmio_addr;
1608 u16 ctl;
1609 int i;
1610
1611 ctl = SIS_R16(RxMacControl);
1612 /*
1613 * Disable packet filtering before setting filter.
1614 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1615 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1616 */
1617 SIS_W16(RxMacControl, ctl & ~0x0f00);
1618
1619 for (i = 0; i < MAC_ADDR_LEN; i++)
1620 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1621
1622 SIS_W16(RxMacControl, ctl);
1623 SIS_PCI_COMMIT();
1624}
1625
d785ad74
SL		 1626static int __devinit sis190_get_mac_addr(struct pci_dev *pdev,
1627 struct net_device *dev)
830fb7d2 1628{
563e0ae0
FR		 1629 int rc;
1630
1631 rc = sis190_get_mac_addr_from_eeprom(pdev, dev);
1632 if (rc < 0) {
1633 u8 reg;
830fb7d2 1634
563e0ae0 1635 pci_read_config_byte(pdev, 0x73, &reg);
830fb7d2 1636
563e0ae0
FR		 1637 if (reg & 0x00000001)
1638 rc = sis190_get_mac_addr_from_apc(pdev, dev);
1639 }
1640 return rc;
830fb7d2
FR		 1641}
1642
890e8d0a
FR		 1643static void sis190_set_speed_auto(struct net_device *dev)
1644{
1645 struct sis190_private *tp = netdev_priv(dev);
1646 void __iomem *ioaddr = tp->mmio_addr;
9ede109b 1647 int phy_id = tp->mii_if.phy_id;
890e8d0a
FR		 1648 int val;
1649
1650 net_link(tp, KERN_INFO "%s: Enabling Auto-negotiation.\n", dev->name);
1651
9ede109b 1652 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
890e8d0a
FR		 1653
1654 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1655 // unchanged.
9ede109b 1656 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
890e8d0a
FR		 1657 ADVERTISE_100FULL | ADVERTISE_10FULL |
1658 ADVERTISE_100HALF | ADVERTISE_10HALF);
1659
1660 // Enable 1000 Full Mode.
9ede109b 1661 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
890e8d0a
FR		 1662
1663 // Enable auto-negotiation and restart auto-negotiation.
9ede109b 1664 mdio_write(ioaddr, phy_id, MII_BMCR,
890e8d0a
FR		 1665 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1666}
1667
43afb949
FR		 1668static int sis190_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1669{
1670 struct sis190_private *tp = netdev_priv(dev);
1671
1672 return mii_ethtool_gset(&tp->mii_if, cmd);
1673}
1674
1675static int sis190_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1676{
1677 struct sis190_private *tp = netdev_priv(dev);
1678
1679 return mii_ethtool_sset(&tp->mii_if, cmd);
1680}
1681
890e8d0a
FR		 1682static void sis190_get_drvinfo(struct net_device *dev,
1683 struct ethtool_drvinfo *info)
1684{
1685 struct sis190_private *tp = netdev_priv(dev);
1686
1687 strcpy(info->driver, DRV_NAME);
1688 strcpy(info->version, DRV_VERSION);
1689 strcpy(info->bus_info, pci_name(tp->pci_dev));
1690}
1691
1692static int sis190_get_regs_len(struct net_device *dev)
1693{
1694 return SIS190_REGS_SIZE;
1695}
1696
1697static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1698 void *p)
1699{
1700 struct sis190_private *tp = netdev_priv(dev);
1701 unsigned long flags;
1702
1703 if (regs->len > SIS190_REGS_SIZE)
1704 regs->len = SIS190_REGS_SIZE;
1705
1706 spin_lock_irqsave(&tp->lock, flags);
1707 memcpy_fromio(p, tp->mmio_addr, regs->len);
1708 spin_unlock_irqrestore(&tp->lock, flags);
1709}
1710
43afb949
FR		 1711static int sis190_nway_reset(struct net_device *dev)
1712{
1713 struct sis190_private *tp = netdev_priv(dev);
1714
1715 return mii_nway_restart(&tp->mii_if);
1716}
1717
890e8d0a
FR		 1718static u32 sis190_get_msglevel(struct net_device *dev)
1719{
1720 struct sis190_private *tp = netdev_priv(dev);
1721
1722 return tp->msg_enable;
1723}
1724
1725static void sis190_set_msglevel(struct net_device *dev, u32 value)
1726{
1727 struct sis190_private *tp = netdev_priv(dev);
1728
1729 tp->msg_enable = value;
1730}
1731
7282d491 1732static const struct ethtool_ops sis190_ethtool_ops = {
43afb949
FR		 1733 .get_settings = sis190_get_settings,
1734 .set_settings = sis190_set_settings,
890e8d0a
FR		 1735 .get_drvinfo = sis190_get_drvinfo,
1736 .get_regs_len = sis190_get_regs_len,
1737 .get_regs = sis190_get_regs,
1738 .get_link = ethtool_op_get_link,
1739 .get_msglevel = sis190_get_msglevel,
1740 .set_msglevel = sis190_set_msglevel,
43afb949 1741 .nway_reset = sis190_nway_reset,
890e8d0a
FR		 1742};
1743
43afb949
FR		 1744static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1745{
1746 struct sis190_private *tp = netdev_priv(dev);
1747
1748 return !netif_running(dev) ? -EINVAL :
1749 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1750}
1751
890e8d0a
FR		 1752static int __devinit sis190_init_one(struct pci_dev *pdev,
1753 const struct pci_device_id *ent)
1754{
1755 static int printed_version = 0;
1756 struct sis190_private *tp;
1757 struct net_device *dev;
1758 void __iomem *ioaddr;
830fb7d2 1759 int rc;
0795af57 1760 DECLARE_MAC_BUF(mac);
890e8d0a
FR		 1761
1762 if (!printed_version) {
1763 net_drv(&debug, KERN_INFO SIS190_DRIVER_NAME " loaded.\n");
1764 printed_version = 1;
1765 }
1766
1767 dev = sis190_init_board(pdev);
1768 if (IS_ERR(dev)) {
1769 rc = PTR_ERR(dev);
1770 goto out;
1771 }
1772
10487fbd
FR		 1773 pci_set_drvdata(pdev, dev);
1774
890e8d0a
FR		 1775 tp = netdev_priv(dev);
1776 ioaddr = tp->mmio_addr;
1777
830fb7d2
FR		 1778 rc = sis190_get_mac_addr(pdev, dev);
1779 if (rc < 0)
1780 goto err_release_board;
890e8d0a 1781
830fb7d2 1782 sis190_init_rxfilter(dev);
890e8d0a 1783
c4028958 1784 INIT_WORK(&tp->phy_task, sis190_phy_task);
890e8d0a
FR		 1785
1786 dev->open = sis190_open;
1787 dev->stop = sis190_close;
43afb949 1788 dev->do_ioctl = sis190_ioctl;
890e8d0a
FR		 1789 dev->tx_timeout = sis190_tx_timeout;
1790 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
1791 dev->hard_start_xmit = sis190_start_xmit;
4405d3b5
FR		 1792#ifdef CONFIG_NET_POLL_CONTROLLER
1793 dev->poll_controller = sis190_netpoll;
1794#endif
890e8d0a
FR		 1795 dev->set_multicast_list = sis190_set_rx_mode;
1796 SET_ETHTOOL_OPS(dev, &sis190_ethtool_ops);
1797 dev->irq = pdev->irq;
1798 dev->base_addr = (unsigned long) 0xdead;
1799
1800 spin_lock_init(&tp->lock);
3690b6c1
FR		 1801
1802 rc = sis190_mii_probe(dev);
830fb7d2
FR		 1803 if (rc < 0)
1804 goto err_release_board;
890e8d0a 1805
3690b6c1 1806 rc = register_netdev(dev);
fcb9821d 1807 if (rc < 0)
3690b6c1
FR		 1808 goto err_remove_mii;
1809
890e8d0a 1810 net_probe(tp, KERN_INFO "%s: %s at %p (IRQ: %d), "
0795af57
JP		 1811 "%s\n",
1812 pci_name(pdev), sis_chip_info[ent->driver_data].name,
1813 ioaddr, dev->irq, print_mac(mac, dev->dev_addr));
890e8d0a 1814
900eb9d6
FR		 1815 net_probe(tp, KERN_INFO "%s: %s mode.\n", dev->name,
1816 (tp->features & F_HAS_RGMII) ? "RGMII" : "GMII");
1817
890e8d0a
FR		 1818 netif_carrier_off(dev);
1819
1820 sis190_set_speed_auto(dev);
1821out:
1822 return rc;
830fb7d2 1823
3690b6c1
FR		 1824err_remove_mii:
1825 sis190_mii_remove(dev);
830fb7d2
FR		 1826err_release_board:
1827 sis190_release_board(pdev);
1828 goto out;
890e8d0a
FR		 1829}
1830
1831static void __devexit sis190_remove_one(struct pci_dev *pdev)
1832{
1833 struct net_device *dev = pci_get_drvdata(pdev);
1834
fcb9821d 1835 sis190_mii_remove(dev);
c014f6c8 1836 flush_scheduled_work();
890e8d0a
FR		 1837 unregister_netdev(dev);
1838 sis190_release_board(pdev);
1839 pci_set_drvdata(pdev, NULL);
1840}
1841
1842static struct pci_driver sis190_pci_driver = {
1843 .name = DRV_NAME,
1844 .id_table = sis190_pci_tbl,
1845 .probe = sis190_init_one,
1846 .remove = __devexit_p(sis190_remove_one),
1847};
1848
1849static int __init sis190_init_module(void)
1850{
29917620 1851 return pci_register_driver(&sis190_pci_driver);
890e8d0a
FR		 1852}
1853
1854static void __exit sis190_cleanup_module(void)
1855{
1856 pci_unregister_driver(&sis190_pci_driver);
1857}
1858
1859module_init(sis190_init_module);
1860module_exit(sis190_cleanup_module);
Linux 6.x block layer and io_uring tree(s)