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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-2.6-block.git] / drivers / net / sh_eth.h
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
4a55530f 5 * Copyright (C) 2008-2011 Renesas Solutions Corp.
86a74ff2
NI		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23#ifndef __SH_ETH_H__
24#define __SH_ETH_H__
25
26#include <linux/module.h>
27#include <linux/kernel.h>
28#include <linux/spinlock.h>
86a74ff2
NI		 29#include <linux/netdevice.h>
30#include <linux/phy.h>
31
71557a37
YS		 32#include <asm/sh_eth.h>
33
86a74ff2
NI		 34#define CARDNAME "sh-eth"
35#define TX_TIMEOUT (5*HZ)
b0ca2a21
NI		 36#define TX_RING_SIZE 64 /* Tx ring size */
37#define RX_RING_SIZE 64 /* Rx ring size */
86a74ff2
NI		 38#define ETHERSMALL 60
39#define PKT_BUF_SZ 1538
40
4a55530f
YS		 41enum {
42 /* E-DMAC registers */
43 EDSR = 0,
44 EDMR,
45 EDTRR,
46 EDRRR,
47 EESR,
48 EESIPR,
49 TDLAR,
50 TDFAR,
51 TDFXR,
52 TDFFR,
53 RDLAR,
54 RDFAR,
55 RDFXR,
56 RDFFR,
57 TRSCER,
58 RMFCR,
59 TFTR,
60 FDR,
61 RMCR,
62 EDOCR,
63 TFUCR,
64 RFOCR,
65 FCFTR,
66 RPADIR,
67 TRIMD,
68 RBWAR,
69 TBRAR,
70
71 /* Ether registers */
72 ECMR,
73 ECSR,
74 ECSIPR,
75 PIR,
76 PSR,
77 RDMLR,
78 PIPR,
79 RFLR,
80 IPGR,
81 APR,
82 MPR,
83 PFTCR,
84 PFRCR,
85 RFCR,
86 RFCF,
87 TPAUSER,
88 TPAUSECR,
89 BCFR,
90 BCFRR,
91 GECMR,
92 BCULR,
93 MAHR,
94 MALR,
95 TROCR,
96 CDCR,
97 LCCR,
98 CNDCR,
99 CEFCR,
100 FRECR,
101 TSFRCR,
102 TLFRCR,
103 CERCR,
104 CEECR,
105 MAFCR,
106 RTRATE,
107
108 /* TSU Absolute address */
109 ARSTR,
110 TSU_CTRST,
111 TSU_FWEN0,
112 TSU_FWEN1,
113 TSU_FCM,
114 TSU_BSYSL0,
115 TSU_BSYSL1,
116 TSU_PRISL0,
117 TSU_PRISL1,
118 TSU_FWSL0,
119 TSU_FWSL1,
120 TSU_FWSLC,
121 TSU_QTAG0,
122 TSU_QTAG1,
123 TSU_QTAGM0,
124 TSU_QTAGM1,
125 TSU_FWSR,
126 TSU_FWINMK,
127 TSU_ADQT0,
128 TSU_ADQT1,
129 TSU_VTAG0,
130 TSU_VTAG1,
131 TSU_ADSBSY,
132 TSU_TEN,
133 TSU_POST1,
134 TSU_POST2,
135 TSU_POST3,
136 TSU_POST4,
137 TSU_ADRH0,
138 TSU_ADRL0,
139 TSU_ADRH31,
140 TSU_ADRL31,
141
142 TXNLCR0,
143 TXALCR0,
144 RXNLCR0,
145 RXALCR0,
146 FWNLCR0,
147 FWALCR0,
148 TXNLCR1,
149 TXALCR1,
150 RXNLCR1,
151 RXALCR1,
152 FWNLCR1,
153 FWALCR1,
154
155 /* This value must be written at last. */
156 SH_ETH_MAX_REGISTER_OFFSET,
157};
158
159static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181
182 [ECMR] = 0x0500,
183 [ECSR] = 0x0510,
184 [ECSIPR] = 0x0518,
185 [PIR] = 0x0520,
186 [PSR] = 0x0528,
187 [PIPR] = 0x052c,
188 [RFLR] = 0x0508,
189 [APR] = 0x0554,
190 [MPR] = 0x0558,
191 [PFTCR] = 0x055c,
192 [PFRCR] = 0x0560,
193 [TPAUSER] = 0x0564,
194 [GECMR] = 0x05b0,
195 [BCULR] = 0x05b4,
196 [MAHR] = 0x05c0,
197 [MALR] = 0x05c8,
198 [TROCR] = 0x0700,
199 [CDCR] = 0x0708,
200 [LCCR] = 0x0710,
201 [CEFCR] = 0x0740,
202 [FRECR] = 0x0748,
203 [TSFRCR] = 0x0750,
204 [TLFRCR] = 0x0758,
205 [RFCR] = 0x0760,
206 [CERCR] = 0x0768,
207 [CEECR] = 0x0770,
208 [MAFCR] = 0x0778,
209
4986b996 210 [ARSTR] = 0x0000,
4a55530f
YS		 211 [TSU_CTRST] = 0x0004,
212 [TSU_FWEN0] = 0x0010,
213 [TSU_FWEN1] = 0x0014,
214 [TSU_FCM] = 0x0018,
215 [TSU_BSYSL0] = 0x0020,
216 [TSU_BSYSL1] = 0x0024,
217 [TSU_PRISL0] = 0x0028,
218 [TSU_PRISL1] = 0x002c,
219 [TSU_FWSL0] = 0x0030,
220 [TSU_FWSL1] = 0x0034,
221 [TSU_FWSLC] = 0x0038,
222 [TSU_QTAG0] = 0x0040,
223 [TSU_QTAG1] = 0x0044,
224 [TSU_FWSR] = 0x0050,
225 [TSU_FWINMK] = 0x0054,
226 [TSU_ADQT0] = 0x0048,
227 [TSU_ADQT1] = 0x004c,
228 [TSU_VTAG0] = 0x0058,
229 [TSU_VTAG1] = 0x005c,
230 [TSU_ADSBSY] = 0x0060,
231 [TSU_TEN] = 0x0064,
232 [TSU_POST1] = 0x0070,
233 [TSU_POST2] = 0x0074,
234 [TSU_POST3] = 0x0078,
235 [TSU_POST4] = 0x007c,
236 [TSU_ADRH0] = 0x0100,
237 [TSU_ADRL0] = 0x0104,
238 [TSU_ADRH31] = 0x01f8,
239 [TSU_ADRL31] = 0x01fc,
240
241 [TXNLCR0] = 0x0080,
242 [TXALCR0] = 0x0084,
243 [RXNLCR0] = 0x0088,
244 [RXALCR0] = 0x008c,
245 [FWNLCR0] = 0x0090,
246 [FWALCR0] = 0x0094,
247 [TXNLCR1] = 0x00a0,
248 [TXALCR1] = 0x00a0,
249 [RXNLCR1] = 0x00a8,
250 [RXALCR1] = 0x00ac,
251 [FWNLCR1] = 0x00b0,
252 [FWALCR1] = 0x00b4,
253};
254
255static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
256 [ECMR] = 0x0100,
257 [RFLR] = 0x0108,
258 [ECSR] = 0x0110,
259 [ECSIPR] = 0x0118,
260 [PIR] = 0x0120,
261 [PSR] = 0x0128,
262 [RDMLR] = 0x0140,
263 [IPGR] = 0x0150,
264 [APR] = 0x0154,
265 [MPR] = 0x0158,
266 [TPAUSER] = 0x0164,
267 [RFCF] = 0x0160,
268 [TPAUSECR] = 0x0168,
269 [BCFRR] = 0x016c,
270 [MAHR] = 0x01c0,
271 [MALR] = 0x01c8,
272 [TROCR] = 0x01d0,
273 [CDCR] = 0x01d4,
274 [LCCR] = 0x01d8,
275 [CNDCR] = 0x01dc,
276 [CEFCR] = 0x01e4,
277 [FRECR] = 0x01e8,
278 [TSFRCR] = 0x01ec,
279 [TLFRCR] = 0x01f0,
280 [RFCR] = 0x01f4,
281 [MAFCR] = 0x01f8,
282 [RTRATE] = 0x01fc,
283
284 [EDMR] = 0x0000,
285 [EDTRR] = 0x0008,
286 [EDRRR] = 0x0010,
287 [TDLAR] = 0x0018,
288 [RDLAR] = 0x0020,
289 [EESR] = 0x0028,
290 [EESIPR] = 0x0030,
291 [TRSCER] = 0x0038,
292 [RMFCR] = 0x0040,
293 [TFTR] = 0x0048,
294 [FDR] = 0x0050,
295 [RMCR] = 0x0058,
296 [TFUCR] = 0x0064,
297 [RFOCR] = 0x0068,
298 [FCFTR] = 0x0070,
299 [RPADIR] = 0x0078,
300 [TRIMD] = 0x007c,
301 [RBWAR] = 0x00c8,
302 [RDFAR] = 0x00cc,
303 [TBRAR] = 0x00d4,
304 [TDFAR] = 0x00d8,
305};
306
307static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
308 [ECMR] = 0x0160,
309 [ECSR] = 0x0164,
310 [ECSIPR] = 0x0168,
311 [PIR] = 0x016c,
312 [MAHR] = 0x0170,
313 [MALR] = 0x0174,
314 [RFLR] = 0x0178,
315 [PSR] = 0x017c,
316 [TROCR] = 0x0180,
317 [CDCR] = 0x0184,
318 [LCCR] = 0x0188,
319 [CNDCR] = 0x018c,
320 [CEFCR] = 0x0194,
321 [FRECR] = 0x0198,
322 [TSFRCR] = 0x019c,
323 [TLFRCR] = 0x01a0,
324 [RFCR] = 0x01a4,
325 [MAFCR] = 0x01a8,
326 [IPGR] = 0x01b4,
327 [APR] = 0x01b8,
328 [MPR] = 0x01bc,
329 [TPAUSER] = 0x01c4,
330 [BCFR] = 0x01cc,
331
4986b996 332 [ARSTR] = 0x0000,
4a55530f
YS		 333 [TSU_CTRST] = 0x0004,
334 [TSU_FWEN0] = 0x0010,
335 [TSU_FWEN1] = 0x0014,
336 [TSU_FCM] = 0x0018,
337 [TSU_BSYSL0] = 0x0020,
338 [TSU_BSYSL1] = 0x0024,
339 [TSU_PRISL0] = 0x0028,
340 [TSU_PRISL1] = 0x002c,
341 [TSU_FWSL0] = 0x0030,
342 [TSU_FWSL1] = 0x0034,
343 [TSU_FWSLC] = 0x0038,
344 [TSU_QTAGM0] = 0x0040,
345 [TSU_QTAGM1] = 0x0044,
346 [TSU_ADQT0] = 0x0048,
347 [TSU_ADQT1] = 0x004c,
348 [TSU_FWSR] = 0x0050,
349 [TSU_FWINMK] = 0x0054,
350 [TSU_ADSBSY] = 0x0060,
351 [TSU_TEN] = 0x0064,
352 [TSU_POST1] = 0x0070,
353 [TSU_POST2] = 0x0074,
354 [TSU_POST3] = 0x0078,
355 [TSU_POST4] = 0x007c,
356
357 [TXNLCR0] = 0x0080,
358 [TXALCR0] = 0x0084,
359 [RXNLCR0] = 0x0088,
360 [RXALCR0] = 0x008c,
361 [FWNLCR0] = 0x0090,
362 [FWALCR0] = 0x0094,
363 [TXNLCR1] = 0x00a0,
364 [TXALCR1] = 0x00a0,
365 [RXNLCR1] = 0x00a8,
366 [RXALCR1] = 0x00ac,
367 [FWNLCR1] = 0x00b0,
368 [FWALCR1] = 0x00b4,
369
370 [TSU_ADRH0] = 0x0100,
371 [TSU_ADRL0] = 0x0104,
372 [TSU_ADRL31] = 0x01fc,
373
374};
375
380af9e3
YS		 376/* Driver's parameters */
377#if defined(CONFIG_CPU_SH4)
378#define SH4_SKB_RX_ALIGN 32
379#else
380#define SH2_SH3_SKB_RX_ALIGN 2
381#endif
382
b0ca2a21
NI		 383/*
384 * Register's bits
385 */
386#ifdef CONFIG_CPU_SUBTYPE_SH7763
387/* EDSR */
388enum EDSR_BIT {
389 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
390};
391#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
392
393/* GECMR */
394enum GECMR_BIT {
395 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
396};
397#endif
86a74ff2
NI		 398
399/* EDMR */
400enum DMAC_M_BIT {
380af9e3 401 EDMR_EL = 0x40, /* Litte endian */
b0ca2a21 402 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
c5ed5368
YS		 403 EDMR_SRST_GETHER = 0x03,
404 EDMR_SRST_ETHER = 0x01,
86a74ff2
NI		 405};
406
407/* EDTRR */
408enum DMAC_T_BIT {
c5ed5368
YS		 409 EDTRR_TRNS_GETHER = 0x03,
410 EDTRR_TRNS_ETHER = 0x01,
86a74ff2
NI		 411};
412
413/* EDRRR*/
414enum EDRRR_R_BIT {
415 EDRRR_R = 0x01,
416};
417
418/* TPAUSER */
419enum TPAUSER_BIT {
420 TPAUSER_TPAUSE = 0x0000ffff,
421 TPAUSER_UNLIMITED = 0,
422};
423
424/* BCFR */
425enum BCFR_BIT {
426 BCFR_RPAUSE = 0x0000ffff,
427 BCFR_UNLIMITED = 0,
428};
429
430/* PIR */
431enum PIR_BIT {
432 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
433};
434
435/* PSR */
436enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
437
438/* EESR */
439enum EESR_BIT {
380af9e3
YS		 440 EESR_TWB1 = 0x80000000,
441 EESR_TWB = 0x40000000, /* same as TWB0 */
442 EESR_TC1 = 0x20000000,
443 EESR_TUC = 0x10000000,
444 EESR_ROC = 0x08000000,
445 EESR_TABT = 0x04000000,
446 EESR_RABT = 0x02000000,
447 EESR_RFRMER = 0x01000000, /* same as RFCOF */
448 EESR_ADE = 0x00800000,
449 EESR_ECI = 0x00400000,
450 EESR_FTC = 0x00200000, /* same as TC or TC0 */
451 EESR_TDE = 0x00100000,
452 EESR_TFE = 0x00080000, /* same as TFUF */
453 EESR_FRC = 0x00040000, /* same as FR */
454 EESR_RDE = 0x00020000,
455 EESR_RFE = 0x00010000,
456 EESR_CND = 0x00000800,
457 EESR_DLC = 0x00000400,
458 EESR_CD = 0x00000200,
459 EESR_RTO = 0x00000100,
460 EESR_RMAF = 0x00000080,
461 EESR_CEEF = 0x00000040,
462 EESR_CELF = 0x00000020,
463 EESR_RRF = 0x00000010,
464 EESR_RTLF = 0x00000008,
465 EESR_RTSF = 0x00000004,
466 EESR_PRE = 0x00000002,
467 EESR_CERF = 0x00000001,
468};
469
470#define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
471 EESR_RTO)
472#define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \
473 EESR_RDE | EESR_RFRMER | EESR_ADE | \
474 EESR_TFE | EESR_TDE | EESR_ECI)
475#define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
476 EESR_TFE)
86a74ff2
NI		 477
478/* EESIPR */
479enum DMAC_IM_BIT {
480 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
481 DMAC_M_RABT = 0x02000000,
482 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
483 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
484 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
485 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
486 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
487 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
488 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
489 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
490 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
491 DMAC_M_RINT1 = 0x00000001,
492};
493
494/* Receive descriptor bit */
495enum RD_STS_BIT {
b0ca2a21
NI		 496 RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
497 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
86a74ff2
NI		 498 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
499 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
500 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
501 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
502 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
503 RD_RFS1 = 0x00000001,
504};
b0ca2a21
NI		 505#define RDF1ST RD_RFP1
506#define RDFEND RD_RFP0
507#define RD_RFP (RD_RFP1|RD_RFP0)
86a74ff2
NI		 508
509/* FCFTR */
510enum FCFTR_BIT {
511 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
512 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
513 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
514};
380af9e3
YS		 515#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
516#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
86a74ff2
NI		 517
518/* Transfer descriptor bit */
519enum TD_STS_BIT {
b0ca2a21
NI		 520 TD_TACT = 0x80000000,
521 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
86a74ff2
NI		 522 TD_TFP0 = 0x10000000,
523};
524#define TDF1ST TD_TFP1
525#define TDFEND TD_TFP0
526#define TD_TFP (TD_TFP1|TD_TFP0)
527
528/* RMCR */
380af9e3
YS		 529#define DEFAULT_RMCR_VALUE 0x00000000
530
86a74ff2
NI		 531/* ECMR */
532enum FELIC_MODE_BIT {
b0ca2a21
NI		 533 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
534 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
86a74ff2
NI		 535 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
536 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
537 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
65ac8851 538 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
380af9e3 539 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
86a74ff2
NI		 540};
541
542/* ECSR */
543enum ECSR_STATUS_BIT {
b0ca2a21 544 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
b0ca2a21 545 ECSR_LCHNG = 0x04,
86a74ff2
NI		 546 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
547};
548
380af9e3
YS		 549#define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
550 ECSR_ICD | ECSIPR_MPDIP)
b0ca2a21 551
86a74ff2
NI		 552/* ECSIPR */
553enum ECSIPR_STATUS_MASK_BIT {
b0ca2a21 554 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
b0ca2a21 555 ECSIPR_LCHNGIP = 0x04,
86a74ff2
NI		 556 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
557};
558
380af9e3
YS		 559#define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
560 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
b0ca2a21 561
86a74ff2
NI		 562/* APR */
563enum APR_BIT {
564 APR_AP = 0x00000001,
565};
566
567/* MPR */
568enum MPR_BIT {
569 MPR_MP = 0x00000001,
570};
571
572/* TRSCER */
573enum DESC_I_BIT {
574 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
575 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
576 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
577 DESC_I_RINT1 = 0x0001,
578};
579
580/* RPADIR */
581enum RPADIR_BIT {
582 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
583 RPADIR_PADR = 0x0003f,
584};
585
b0ca2a21
NI		 586/* RFLR */
587#define RFLR_VALUE 0x1000
588
86a74ff2 589/* FDR */
380af9e3
YS		 590#define DEFAULT_FDR_INIT 0x00000707
591
86a74ff2
NI		 592enum phy_offsets {
593 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
594 PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
595 PHY_16 = 16,
596};
597
598/* PHY_CTRL */
599enum PHY_CTRL_BIT {
600 PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
601 PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
602 PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
603};
604#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
605
606/* PHY_STAT */
607enum PHY_STAT_BIT {
608 PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
609 PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
610 PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
611 PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
612};
613
614/* PHY_ANA */
615enum PHY_ANA_BIT {
616 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
617 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
618 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
b0ca2a21 619 PHY_A_SEL = 0x001e,
86a74ff2
NI		 620};
621/* PHY_ANL */
622enum PHY_ANL_BIT {
623 PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
624 PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
625 PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
626 PHY_L_SEL = 0x001f,
627};
628
629/* PHY_ANE */
630enum PHY_ANE_BIT {
631 PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
632 PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
633};
634
635/* DM9161 */
636enum PHY_16_BIT {
637 PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
638 PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
639 PHY_16_TXselect = 0x0400,
640 PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
641 PHY_16_Force100LNK = 0x0080,
642 PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
643 PHY_16_RPDCTR_EN = 0x0010,
644 PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
645 PHY_16_Sleepmode = 0x0002,
646 PHY_16_RemoteLoopOut = 0x0001,
647};
648
649#define POST_RX 0x08
650#define POST_FW 0x04
651#define POST0_RX (POST_RX)
652#define POST0_FW (POST_FW)
653#define POST1_RX (POST_RX >> 2)
654#define POST1_FW (POST_FW >> 2)
655#define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
656
657/* ARSTR */
658enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
659
660/* TSU_FWEN0 */
661enum TSU_FWEN0_BIT {
662 TSU_FWEN0_0 = 0x00000001,
663};
664
665/* TSU_ADSBSY */
666enum TSU_ADSBSY_BIT {
667 TSU_ADSBSY_0 = 0x00000001,
668};
669
670/* TSU_TEN */
671enum TSU_TEN_BIT {
672 TSU_TEN_0 = 0x80000000,
673};
674
675/* TSU_FWSL0 */
676enum TSU_FWSL0_BIT {
677 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
678 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
679 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
680};
681
682/* TSU_FWSLC */
683enum TSU_FWSLC_BIT {
684 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
685 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
686 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
687 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
688 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
689};
690
691/*
692 * The sh ether Tx buffer descriptors.
693 * This structure should be 20 bytes.
694 */
695struct sh_eth_txdesc {
696 u32 status; /* TD0 */
697#if defined(CONFIG_CPU_LITTLE_ENDIAN)
698 u16 pad0; /* TD1 */
699 u16 buffer_length; /* TD1 */
700#else
701 u16 buffer_length; /* TD1 */
702 u16 pad0; /* TD1 */
703#endif
704 u32 addr; /* TD2 */
705 u32 pad1; /* padding data */
71557a37 706} __attribute__((aligned(2), packed));
86a74ff2
NI		 707
708/*
709 * The sh ether Rx buffer descriptors.
710 * This structure should be 20 bytes.
711 */
712struct sh_eth_rxdesc {
713 u32 status; /* RD0 */
714#if defined(CONFIG_CPU_LITTLE_ENDIAN)
715 u16 frame_length; /* RD1 */
716 u16 buffer_length; /* RD1 */
717#else
718 u16 buffer_length; /* RD1 */
719 u16 frame_length; /* RD1 */
720#endif
721 u32 addr; /* RD2 */
722 u32 pad0; /* padding data */
71557a37 723} __attribute__((aligned(2), packed));
86a74ff2 724
380af9e3
YS		 725/* This structure is used by each CPU dependency handling. */
726struct sh_eth_cpu_data {
727 /* optional functions */
728 void (*chip_reset)(struct net_device *ndev);
729 void (*set_duplex)(struct net_device *ndev);
730 void (*set_rate)(struct net_device *ndev);
731
732 /* mandatory initialize value */
733 unsigned long eesipr_value;
734
735 /* optional initialize value */
736 unsigned long ecsr_value;
737 unsigned long ecsipr_value;
738 unsigned long fdr_value;
739 unsigned long fcftr_value;
740 unsigned long rpadir_value;
741 unsigned long rmcr_value;
742
743 /* interrupt checking mask */
744 unsigned long tx_check;
745 unsigned long eesr_err_check;
746 unsigned long tx_error_check;
747
748 /* hardware features */
749 unsigned no_psr:1; /* EtherC DO NOT have PSR */
750 unsigned apr:1; /* EtherC have APR */
751 unsigned mpr:1; /* EtherC have MPR */
752 unsigned tpauser:1; /* EtherC have TPAUSER */
753 unsigned bculr:1; /* EtherC have BCULR */
4986b996 754 unsigned tsu:1; /* EtherC have TSU */
380af9e3
YS		 755 unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
756 unsigned rpadir:1; /* E-DMAC have RPADIR */
757 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
758 unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
759};
760
86a74ff2 761struct sh_eth_private {
bcd5149d 762 struct platform_device *pdev;
380af9e3 763 struct sh_eth_cpu_data *cd;
4a55530f
YS		 764 const u16 *reg_offset;
765 void __iomem *tsu_addr;
86a74ff2
NI		 766 dma_addr_t rx_desc_dma;
767 dma_addr_t tx_desc_dma;
768 struct sh_eth_rxdesc *rx_ring;
769 struct sh_eth_txdesc *tx_ring;
770 struct sk_buff **rx_skbuff;
771 struct sk_buff **tx_skbuff;
772 struct net_device_stats stats;
773 struct timer_list timer;
774 spinlock_t lock;
775 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
776 u32 cur_tx, dirty_tx;
777 u32 rx_buf_sz; /* Based on MTU+slack. */
71557a37 778 int edmac_endian;
86a74ff2
NI		 779 /* MII transceiver section. */
780 u32 phy_id; /* PHY ID */
781 struct mii_bus *mii_bus; /* MDIO bus control */
782 struct phy_device *phydev; /* PHY device control */
783 enum phy_state link;
e47c9052 784 phy_interface_t phy_interface;
86a74ff2
NI		 785 int msg_enable;
786 int speed;
787 int duplex;
788 u32 rx_int_var, tx_int_var; /* interrupt control variables */
789 char post_rx; /* POST receive */
790 char post_fw; /* POST forward */
791 struct net_device_stats tsu_stats; /* TSU forward status */
4923576b
YS		 792
793 unsigned no_ether_link:1;
794 unsigned ether_link_active_low:1;
86a74ff2
NI		 795};
796
380af9e3 797static inline void sh_eth_soft_swap(char *src, int len)
86a74ff2
NI		 798{
799#ifdef __LITTLE_ENDIAN__
800 u32 *p = (u32 *)src;
801 u32 *maxp;
802 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
803
804 for (; p < maxp; p++)
805 *p = swab32(*p);
806#endif
807}
380af9e3 808
4a55530f
YS		 809static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
810 int enum_index)
811{
812 struct sh_eth_private *mdp = netdev_priv(ndev);
813
814 writel(data, ndev->base_addr + mdp->reg_offset[enum_index]);
815}
816
817static inline unsigned long sh_eth_read(struct net_device *ndev,
818 int enum_index)
819{
820 struct sh_eth_private *mdp = netdev_priv(ndev);
821
822 return readl(ndev->base_addr + mdp->reg_offset[enum_index]);
823}
824
825static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
826 unsigned long data, int enum_index)
827{
828 writel(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
829}
830
831static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
832 int enum_index)
833{
834 return readl(mdp->tsu_addr + mdp->reg_offset[enum_index]);
835}
836
380af9e3 837#endif /* #ifndef __SH_ETH_H__ */
Linux 6.x block layer and io_uring tree(s)