Commit | Line | Data |
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86a74ff2 NI |
1 | /* |
2 | * SuperH Ethernet device driver | |
3 | * | |
b0ca2a21 | 4 | * Copyright (C) 2006-2008 Nobuhiro Iwamatsu |
86a74ff2 NI |
5 | * Copyright (C) 2008 Renesas Solutions Corp. |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | * | |
19 | * The full GNU General Public License is included in this distribution in | |
20 | * the file called "COPYING". | |
21 | */ | |
22 | ||
23 | #include <linux/version.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/mdio-bitbang.h> | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/phy.h> | |
32 | #include <linux/cache.h> | |
33 | #include <linux/io.h> | |
34 | ||
35 | #include "sh_eth.h" | |
36 | ||
37 | /* | |
38 | * Program the hardware MAC address from dev->dev_addr. | |
39 | */ | |
40 | static void update_mac_address(struct net_device *ndev) | |
41 | { | |
42 | u32 ioaddr = ndev->base_addr; | |
43 | ||
44 | ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | | |
45 | (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), | |
46 | ioaddr + MAHR); | |
47 | ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), | |
48 | ioaddr + MALR); | |
49 | } | |
50 | ||
51 | /* | |
52 | * Get MAC address from SuperH MAC address register | |
53 | * | |
54 | * SuperH's Ethernet device doesn't have 'ROM' to MAC address. | |
55 | * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). | |
56 | * When you want use this device, you must set MAC address in bootloader. | |
57 | * | |
58 | */ | |
59 | static void read_mac_address(struct net_device *ndev) | |
60 | { | |
61 | u32 ioaddr = ndev->base_addr; | |
62 | ||
63 | ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24); | |
64 | ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF; | |
65 | ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF; | |
66 | ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF); | |
67 | ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF; | |
68 | ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF); | |
69 | } | |
70 | ||
71 | struct bb_info { | |
72 | struct mdiobb_ctrl ctrl; | |
73 | u32 addr; | |
74 | u32 mmd_msk;/* MMD */ | |
75 | u32 mdo_msk; | |
76 | u32 mdi_msk; | |
77 | u32 mdc_msk; | |
78 | }; | |
79 | ||
80 | /* PHY bit set */ | |
81 | static void bb_set(u32 addr, u32 msk) | |
82 | { | |
83 | ctrl_outl(ctrl_inl(addr) | msk, addr); | |
84 | } | |
85 | ||
86 | /* PHY bit clear */ | |
87 | static void bb_clr(u32 addr, u32 msk) | |
88 | { | |
89 | ctrl_outl((ctrl_inl(addr) & ~msk), addr); | |
90 | } | |
91 | ||
92 | /* PHY bit read */ | |
93 | static int bb_read(u32 addr, u32 msk) | |
94 | { | |
95 | return (ctrl_inl(addr) & msk) != 0; | |
96 | } | |
97 | ||
98 | /* Data I/O pin control */ | |
99 | static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) | |
100 | { | |
101 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); | |
102 | if (bit) | |
103 | bb_set(bitbang->addr, bitbang->mmd_msk); | |
104 | else | |
105 | bb_clr(bitbang->addr, bitbang->mmd_msk); | |
106 | } | |
107 | ||
108 | /* Set bit data*/ | |
109 | static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) | |
110 | { | |
111 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); | |
112 | ||
113 | if (bit) | |
114 | bb_set(bitbang->addr, bitbang->mdo_msk); | |
115 | else | |
116 | bb_clr(bitbang->addr, bitbang->mdo_msk); | |
117 | } | |
118 | ||
119 | /* Get bit data*/ | |
120 | static int sh_get_mdio(struct mdiobb_ctrl *ctrl) | |
121 | { | |
122 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); | |
123 | return bb_read(bitbang->addr, bitbang->mdi_msk); | |
124 | } | |
125 | ||
126 | /* MDC pin control */ | |
127 | static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) | |
128 | { | |
129 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); | |
130 | ||
131 | if (bit) | |
132 | bb_set(bitbang->addr, bitbang->mdc_msk); | |
133 | else | |
134 | bb_clr(bitbang->addr, bitbang->mdc_msk); | |
135 | } | |
136 | ||
137 | /* mdio bus control struct */ | |
138 | static struct mdiobb_ops bb_ops = { | |
139 | .owner = THIS_MODULE, | |
140 | .set_mdc = sh_mdc_ctrl, | |
141 | .set_mdio_dir = sh_mmd_ctrl, | |
142 | .set_mdio_data = sh_set_mdio, | |
143 | .get_mdio_data = sh_get_mdio, | |
144 | }; | |
145 | ||
b0ca2a21 | 146 | /* Chip Reset */ |
86a74ff2 NI |
147 | static void sh_eth_reset(struct net_device *ndev) |
148 | { | |
149 | u32 ioaddr = ndev->base_addr; | |
150 | ||
b0ca2a21 NI |
151 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
152 | int cnt = 100; | |
153 | ||
154 | ctrl_outl(EDSR_ENALL, ioaddr + EDSR); | |
155 | ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR); | |
156 | while (cnt > 0) { | |
157 | if (!(ctrl_inl(ioaddr + EDMR) & 0x3)) | |
158 | break; | |
159 | mdelay(1); | |
160 | cnt--; | |
161 | } | |
162 | if (cnt < 0) | |
163 | printk(KERN_ERR "Device reset fail\n"); | |
164 | ||
165 | /* Table Init */ | |
166 | ctrl_outl(0x0, ioaddr + TDLAR); | |
167 | ctrl_outl(0x0, ioaddr + TDFAR); | |
168 | ctrl_outl(0x0, ioaddr + TDFXR); | |
169 | ctrl_outl(0x0, ioaddr + TDFFR); | |
170 | ctrl_outl(0x0, ioaddr + RDLAR); | |
171 | ctrl_outl(0x0, ioaddr + RDFAR); | |
172 | ctrl_outl(0x0, ioaddr + RDFXR); | |
173 | ctrl_outl(0x0, ioaddr + RDFFR); | |
174 | #else | |
86a74ff2 NI |
175 | ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR); |
176 | mdelay(3); | |
177 | ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR); | |
b0ca2a21 | 178 | #endif |
86a74ff2 NI |
179 | } |
180 | ||
181 | /* free skb and descriptor buffer */ | |
182 | static void sh_eth_ring_free(struct net_device *ndev) | |
183 | { | |
184 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
185 | int i; | |
186 | ||
187 | /* Free Rx skb ringbuffer */ | |
188 | if (mdp->rx_skbuff) { | |
189 | for (i = 0; i < RX_RING_SIZE; i++) { | |
190 | if (mdp->rx_skbuff[i]) | |
191 | dev_kfree_skb(mdp->rx_skbuff[i]); | |
192 | } | |
193 | } | |
194 | kfree(mdp->rx_skbuff); | |
195 | ||
196 | /* Free Tx skb ringbuffer */ | |
197 | if (mdp->tx_skbuff) { | |
198 | for (i = 0; i < TX_RING_SIZE; i++) { | |
199 | if (mdp->tx_skbuff[i]) | |
200 | dev_kfree_skb(mdp->tx_skbuff[i]); | |
201 | } | |
202 | } | |
203 | kfree(mdp->tx_skbuff); | |
204 | } | |
205 | ||
206 | /* format skb and descriptor buffer */ | |
207 | static void sh_eth_ring_format(struct net_device *ndev) | |
208 | { | |
b0ca2a21 | 209 | u32 ioaddr = ndev->base_addr, reserve = 0; |
86a74ff2 NI |
210 | struct sh_eth_private *mdp = netdev_priv(ndev); |
211 | int i; | |
212 | struct sk_buff *skb; | |
213 | struct sh_eth_rxdesc *rxdesc = NULL; | |
214 | struct sh_eth_txdesc *txdesc = NULL; | |
215 | int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE; | |
216 | int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE; | |
217 | ||
218 | mdp->cur_rx = mdp->cur_tx = 0; | |
219 | mdp->dirty_rx = mdp->dirty_tx = 0; | |
220 | ||
221 | memset(mdp->rx_ring, 0, rx_ringsize); | |
222 | ||
223 | /* build Rx ring buffer */ | |
224 | for (i = 0; i < RX_RING_SIZE; i++) { | |
225 | /* skb */ | |
226 | mdp->rx_skbuff[i] = NULL; | |
227 | skb = dev_alloc_skb(mdp->rx_buf_sz); | |
228 | mdp->rx_skbuff[i] = skb; | |
229 | if (skb == NULL) | |
230 | break; | |
b0ca2a21 NI |
231 | skb->dev = ndev; /* Mark as being used by this device. */ |
232 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) | |
233 | reserve = SH7763_SKB_ALIGN | |
234 | - ((uint32_t)skb->data & (SH7763_SKB_ALIGN-1)); | |
235 | if (reserve) | |
236 | skb_reserve(skb, reserve); | |
237 | #else | |
86a74ff2 | 238 | skb_reserve(skb, RX_OFFSET); |
b0ca2a21 | 239 | #endif |
86a74ff2 NI |
240 | /* RX descriptor */ |
241 | rxdesc = &mdp->rx_ring[i]; | |
242 | rxdesc->addr = (u32)skb->data & ~0x3UL; | |
243 | rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); | |
244 | ||
245 | /* The size of the buffer is 16 byte boundary. */ | |
246 | rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F; | |
b0ca2a21 NI |
247 | /* Rx descriptor address set */ |
248 | if (i == 0) { | |
249 | ctrl_outl((u32)rxdesc, ioaddr + RDLAR); | |
250 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) | |
251 | ctrl_outl((u32)rxdesc, ioaddr + RDFAR); | |
252 | #endif | |
253 | } | |
86a74ff2 NI |
254 | } |
255 | ||
b0ca2a21 NI |
256 | /* Rx descriptor address set */ |
257 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) | |
258 | ctrl_outl((u32)rxdesc, ioaddr + RDFXR); | |
259 | ctrl_outl(0x1, ioaddr + RDFFR); | |
260 | #endif | |
261 | ||
86a74ff2 NI |
262 | mdp->dirty_rx = (u32) (i - RX_RING_SIZE); |
263 | ||
264 | /* Mark the last entry as wrapping the ring. */ | |
b0ca2a21 | 265 | rxdesc->status |= cpu_to_le32(RD_RDEL); |
86a74ff2 NI |
266 | |
267 | memset(mdp->tx_ring, 0, tx_ringsize); | |
268 | ||
269 | /* build Tx ring buffer */ | |
270 | for (i = 0; i < TX_RING_SIZE; i++) { | |
271 | mdp->tx_skbuff[i] = NULL; | |
272 | txdesc = &mdp->tx_ring[i]; | |
273 | txdesc->status = cpu_to_le32(TD_TFP); | |
274 | txdesc->buffer_length = 0; | |
b0ca2a21 NI |
275 | if (i == 0) { |
276 | /* Rx descriptor address set */ | |
277 | ctrl_outl((u32)txdesc, ioaddr + TDLAR); | |
278 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) | |
279 | ctrl_outl((u32)txdesc, ioaddr + TDFAR); | |
280 | #endif | |
281 | } | |
86a74ff2 NI |
282 | } |
283 | ||
b0ca2a21 NI |
284 | /* Rx descriptor address set */ |
285 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) | |
286 | ctrl_outl((u32)txdesc, ioaddr + TDFXR); | |
287 | ctrl_outl(0x1, ioaddr + TDFFR); | |
288 | #endif | |
289 | ||
86a74ff2 NI |
290 | txdesc->status |= cpu_to_le32(TD_TDLE); |
291 | } | |
292 | ||
293 | /* Get skb and descriptor buffer */ | |
294 | static int sh_eth_ring_init(struct net_device *ndev) | |
295 | { | |
296 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
297 | int rx_ringsize, tx_ringsize, ret = 0; | |
298 | ||
299 | /* | |
300 | * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the | |
301 | * card needs room to do 8 byte alignment, +2 so we can reserve | |
302 | * the first 2 bytes, and +16 gets room for the status word from the | |
303 | * card. | |
304 | */ | |
305 | mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : | |
306 | (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); | |
307 | ||
308 | /* Allocate RX and TX skb rings */ | |
309 | mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE, | |
310 | GFP_KERNEL); | |
311 | if (!mdp->rx_skbuff) { | |
312 | printk(KERN_ERR "%s: Cannot allocate Rx skb\n", ndev->name); | |
313 | ret = -ENOMEM; | |
314 | return ret; | |
315 | } | |
316 | ||
317 | mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE, | |
318 | GFP_KERNEL); | |
319 | if (!mdp->tx_skbuff) { | |
320 | printk(KERN_ERR "%s: Cannot allocate Tx skb\n", ndev->name); | |
321 | ret = -ENOMEM; | |
322 | goto skb_ring_free; | |
323 | } | |
324 | ||
325 | /* Allocate all Rx descriptors. */ | |
326 | rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE; | |
327 | mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, | |
328 | GFP_KERNEL); | |
329 | ||
330 | if (!mdp->rx_ring) { | |
331 | printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n", | |
332 | ndev->name, rx_ringsize); | |
333 | ret = -ENOMEM; | |
334 | goto desc_ring_free; | |
335 | } | |
336 | ||
337 | mdp->dirty_rx = 0; | |
338 | ||
339 | /* Allocate all Tx descriptors. */ | |
340 | tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE; | |
341 | mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, | |
342 | GFP_KERNEL); | |
343 | if (!mdp->tx_ring) { | |
344 | printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", | |
345 | ndev->name, tx_ringsize); | |
346 | ret = -ENOMEM; | |
347 | goto desc_ring_free; | |
348 | } | |
349 | return ret; | |
350 | ||
351 | desc_ring_free: | |
352 | /* free DMA buffer */ | |
353 | dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); | |
354 | ||
355 | skb_ring_free: | |
356 | /* Free Rx and Tx skb ring buffer */ | |
357 | sh_eth_ring_free(ndev); | |
358 | ||
359 | return ret; | |
360 | } | |
361 | ||
362 | static int sh_eth_dev_init(struct net_device *ndev) | |
363 | { | |
364 | int ret = 0; | |
365 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
366 | u32 ioaddr = ndev->base_addr; | |
367 | u_int32_t rx_int_var, tx_int_var; | |
368 | u32 val; | |
369 | ||
370 | /* Soft Reset */ | |
371 | sh_eth_reset(ndev); | |
372 | ||
b0ca2a21 NI |
373 | /* Descriptor format */ |
374 | sh_eth_ring_format(ndev); | |
375 | ctrl_outl(RPADIR_INIT, ioaddr + RPADIR); | |
86a74ff2 NI |
376 | |
377 | /* all sh_eth int mask */ | |
378 | ctrl_outl(0, ioaddr + EESIPR); | |
379 | ||
b0ca2a21 NI |
380 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
381 | ctrl_outl(EDMR_EL, ioaddr + EDMR); | |
382 | #else | |
86a74ff2 | 383 | ctrl_outl(0, ioaddr + EDMR); /* Endian change */ |
b0ca2a21 | 384 | #endif |
86a74ff2 | 385 | |
b0ca2a21 | 386 | /* FIFO size set */ |
86a74ff2 NI |
387 | ctrl_outl((FIFO_SIZE_T | FIFO_SIZE_R), ioaddr + FDR); |
388 | ctrl_outl(0, ioaddr + TFTR); | |
389 | ||
b0ca2a21 | 390 | /* Frame recv control */ |
0caa1166 | 391 | ctrl_outl(0, ioaddr + RMCR); |
86a74ff2 NI |
392 | |
393 | rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5; | |
394 | tx_int_var = mdp->tx_int_var = DESC_I_TINT2; | |
395 | ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER); | |
396 | ||
b0ca2a21 NI |
397 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
398 | /* Burst sycle set */ | |
399 | ctrl_outl(0x800, ioaddr + BCULR); | |
400 | #endif | |
401 | ||
86a74ff2 | 402 | ctrl_outl((FIFO_F_D_RFF | FIFO_F_D_RFD), ioaddr + FCFTR); |
86a74ff2 | 403 | |
b0ca2a21 NI |
404 | #if !defined(CONFIG_CPU_SUBTYPE_SH7763) |
405 | ctrl_outl(0, ioaddr + TRIMD); | |
406 | #endif | |
86a74ff2 | 407 | |
b0ca2a21 NI |
408 | /* Recv frame limit set register */ |
409 | ctrl_outl(RFLR_VALUE, ioaddr + RFLR); | |
86a74ff2 NI |
410 | |
411 | ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR); | |
412 | ctrl_outl((DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff), ioaddr + EESIPR); | |
413 | ||
414 | /* PAUSE Prohibition */ | |
415 | val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) | | |
416 | ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; | |
417 | ||
418 | ctrl_outl(val, ioaddr + ECMR); | |
b0ca2a21 NI |
419 | |
420 | /* E-MAC Status Register clear */ | |
421 | ctrl_outl(ECSR_INIT, ioaddr + ECSR); | |
422 | ||
423 | /* E-MAC Interrupt Enable register */ | |
424 | ctrl_outl(ECSIPR_INIT, ioaddr + ECSIPR); | |
86a74ff2 NI |
425 | |
426 | /* Set MAC address */ | |
427 | update_mac_address(ndev); | |
428 | ||
429 | /* mask reset */ | |
b0ca2a21 | 430 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7763) |
86a74ff2 NI |
431 | ctrl_outl(APR_AP, ioaddr + APR); |
432 | ctrl_outl(MPR_MP, ioaddr + MPR); | |
433 | ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER); | |
b0ca2a21 NI |
434 | #endif |
435 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) | |
86a74ff2 NI |
436 | ctrl_outl(BCFR_UNLIMITED, ioaddr + BCFR); |
437 | #endif | |
b0ca2a21 | 438 | |
86a74ff2 NI |
439 | /* Setting the Rx mode will start the Rx process. */ |
440 | ctrl_outl(EDRRR_R, ioaddr + EDRRR); | |
441 | ||
442 | netif_start_queue(ndev); | |
443 | ||
444 | return ret; | |
445 | } | |
446 | ||
447 | /* free Tx skb function */ | |
448 | static int sh_eth_txfree(struct net_device *ndev) | |
449 | { | |
450 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
451 | struct sh_eth_txdesc *txdesc; | |
452 | int freeNum = 0; | |
453 | int entry = 0; | |
454 | ||
455 | for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { | |
456 | entry = mdp->dirty_tx % TX_RING_SIZE; | |
457 | txdesc = &mdp->tx_ring[entry]; | |
458 | if (txdesc->status & cpu_to_le32(TD_TACT)) | |
459 | break; | |
460 | /* Free the original skb. */ | |
461 | if (mdp->tx_skbuff[entry]) { | |
462 | dev_kfree_skb_irq(mdp->tx_skbuff[entry]); | |
463 | mdp->tx_skbuff[entry] = NULL; | |
464 | freeNum++; | |
465 | } | |
466 | txdesc->status = cpu_to_le32(TD_TFP); | |
467 | if (entry >= TX_RING_SIZE - 1) | |
468 | txdesc->status |= cpu_to_le32(TD_TDLE); | |
469 | ||
470 | mdp->stats.tx_packets++; | |
471 | mdp->stats.tx_bytes += txdesc->buffer_length; | |
472 | } | |
473 | return freeNum; | |
474 | } | |
475 | ||
476 | /* Packet receive function */ | |
477 | static int sh_eth_rx(struct net_device *ndev) | |
478 | { | |
479 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
480 | struct sh_eth_rxdesc *rxdesc; | |
481 | ||
482 | int entry = mdp->cur_rx % RX_RING_SIZE; | |
483 | int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx; | |
484 | struct sk_buff *skb; | |
485 | u16 pkt_len = 0; | |
b0ca2a21 | 486 | u32 desc_status, reserve = 0; |
86a74ff2 NI |
487 | |
488 | rxdesc = &mdp->rx_ring[entry]; | |
489 | while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { | |
490 | desc_status = le32_to_cpu(rxdesc->status); | |
491 | pkt_len = rxdesc->frame_length; | |
492 | ||
493 | if (--boguscnt < 0) | |
494 | break; | |
495 | ||
496 | if (!(desc_status & RDFEND)) | |
497 | mdp->stats.rx_length_errors++; | |
498 | ||
499 | if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | | |
500 | RD_RFS5 | RD_RFS6 | RD_RFS10)) { | |
501 | mdp->stats.rx_errors++; | |
502 | if (desc_status & RD_RFS1) | |
503 | mdp->stats.rx_crc_errors++; | |
504 | if (desc_status & RD_RFS2) | |
505 | mdp->stats.rx_frame_errors++; | |
506 | if (desc_status & RD_RFS3) | |
507 | mdp->stats.rx_length_errors++; | |
508 | if (desc_status & RD_RFS4) | |
509 | mdp->stats.rx_length_errors++; | |
510 | if (desc_status & RD_RFS6) | |
511 | mdp->stats.rx_missed_errors++; | |
512 | if (desc_status & RD_RFS10) | |
513 | mdp->stats.rx_over_errors++; | |
514 | } else { | |
515 | swaps((char *)(rxdesc->addr & ~0x3), pkt_len + 2); | |
516 | skb = mdp->rx_skbuff[entry]; | |
517 | mdp->rx_skbuff[entry] = NULL; | |
518 | skb_put(skb, pkt_len); | |
519 | skb->protocol = eth_type_trans(skb, ndev); | |
520 | netif_rx(skb); | |
521 | ndev->last_rx = jiffies; | |
522 | mdp->stats.rx_packets++; | |
523 | mdp->stats.rx_bytes += pkt_len; | |
524 | } | |
525 | rxdesc->status |= cpu_to_le32(RD_RACT); | |
526 | entry = (++mdp->cur_rx) % RX_RING_SIZE; | |
527 | } | |
528 | ||
529 | /* Refill the Rx ring buffers. */ | |
530 | for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { | |
531 | entry = mdp->dirty_rx % RX_RING_SIZE; | |
532 | rxdesc = &mdp->rx_ring[entry]; | |
b0ca2a21 NI |
533 | /* The size of the buffer is 16 byte boundary. */ |
534 | rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F; | |
535 | ||
86a74ff2 NI |
536 | if (mdp->rx_skbuff[entry] == NULL) { |
537 | skb = dev_alloc_skb(mdp->rx_buf_sz); | |
538 | mdp->rx_skbuff[entry] = skb; | |
539 | if (skb == NULL) | |
540 | break; /* Better luck next round. */ | |
541 | skb->dev = ndev; | |
b0ca2a21 NI |
542 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
543 | reserve = SH7763_SKB_ALIGN | |
544 | - ((uint32_t)skb->data & (SH7763_SKB_ALIGN-1)); | |
545 | if (reserve) | |
546 | skb_reserve(skb, reserve); | |
547 | #else | |
86a74ff2 | 548 | skb_reserve(skb, RX_OFFSET); |
b0ca2a21 NI |
549 | #endif |
550 | skb->ip_summed = CHECKSUM_NONE; | |
86a74ff2 NI |
551 | rxdesc->addr = (u32)skb->data & ~0x3UL; |
552 | } | |
86a74ff2 NI |
553 | if (entry >= RX_RING_SIZE - 1) |
554 | rxdesc->status |= | |
b0ca2a21 | 555 | cpu_to_le32(RD_RACT | RD_RFP | RD_RDEL); |
86a74ff2 NI |
556 | else |
557 | rxdesc->status |= | |
b0ca2a21 | 558 | cpu_to_le32(RD_RACT | RD_RFP); |
86a74ff2 NI |
559 | } |
560 | ||
561 | /* Restart Rx engine if stopped. */ | |
562 | /* If we don't need to check status, don't. -KDU */ | |
b0ca2a21 NI |
563 | if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R)) |
564 | ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR); | |
86a74ff2 NI |
565 | |
566 | return 0; | |
567 | } | |
568 | ||
569 | /* error control function */ | |
570 | static void sh_eth_error(struct net_device *ndev, int intr_status) | |
571 | { | |
572 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
573 | u32 ioaddr = ndev->base_addr; | |
574 | u32 felic_stat; | |
575 | ||
576 | if (intr_status & EESR_ECI) { | |
577 | felic_stat = ctrl_inl(ioaddr + ECSR); | |
578 | ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */ | |
579 | if (felic_stat & ECSR_ICD) | |
580 | mdp->stats.tx_carrier_errors++; | |
581 | if (felic_stat & ECSR_LCHNG) { | |
582 | /* Link Changed */ | |
583 | u32 link_stat = (ctrl_inl(ioaddr + PSR)); | |
584 | if (!(link_stat & PHY_ST_LINK)) { | |
585 | /* Link Down : disable tx and rx */ | |
586 | ctrl_outl(ctrl_inl(ioaddr + ECMR) & | |
587 | ~(ECMR_RE | ECMR_TE), ioaddr + ECMR); | |
588 | } else { | |
589 | /* Link Up */ | |
590 | ctrl_outl(ctrl_inl(ioaddr + EESIPR) & | |
591 | ~DMAC_M_ECI, ioaddr + EESIPR); | |
592 | /*clear int */ | |
593 | ctrl_outl(ctrl_inl(ioaddr + ECSR), | |
594 | ioaddr + ECSR); | |
595 | ctrl_outl(ctrl_inl(ioaddr + EESIPR) | | |
596 | DMAC_M_ECI, ioaddr + EESIPR); | |
597 | /* enable tx and rx */ | |
598 | ctrl_outl(ctrl_inl(ioaddr + ECMR) | | |
599 | (ECMR_RE | ECMR_TE), ioaddr + ECMR); | |
600 | } | |
601 | } | |
602 | } | |
603 | ||
604 | if (intr_status & EESR_TWB) { | |
605 | /* Write buck end. unused write back interrupt */ | |
606 | if (intr_status & EESR_TABT) /* Transmit Abort int */ | |
607 | mdp->stats.tx_aborted_errors++; | |
608 | } | |
609 | ||
610 | if (intr_status & EESR_RABT) { | |
611 | /* Receive Abort int */ | |
612 | if (intr_status & EESR_RFRMER) { | |
613 | /* Receive Frame Overflow int */ | |
614 | mdp->stats.rx_frame_errors++; | |
615 | printk(KERN_ERR "Receive Frame Overflow\n"); | |
616 | } | |
617 | } | |
b0ca2a21 | 618 | #if !defined(CONFIG_CPU_SUBTYPE_SH7763) |
86a74ff2 NI |
619 | if (intr_status & EESR_ADE) { |
620 | if (intr_status & EESR_TDE) { | |
621 | if (intr_status & EESR_TFE) | |
622 | mdp->stats.tx_fifo_errors++; | |
623 | } | |
624 | } | |
b0ca2a21 | 625 | #endif |
86a74ff2 NI |
626 | |
627 | if (intr_status & EESR_RDE) { | |
628 | /* Receive Descriptor Empty int */ | |
629 | mdp->stats.rx_over_errors++; | |
630 | ||
631 | if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R) | |
632 | ctrl_outl(EDRRR_R, ioaddr + EDRRR); | |
633 | printk(KERN_ERR "Receive Descriptor Empty\n"); | |
634 | } | |
635 | if (intr_status & EESR_RFE) { | |
636 | /* Receive FIFO Overflow int */ | |
637 | mdp->stats.rx_fifo_errors++; | |
638 | printk(KERN_ERR "Receive FIFO Overflow\n"); | |
639 | } | |
b0ca2a21 NI |
640 | if (intr_status & (EESR_TWB | EESR_TABT | |
641 | #if !defined(CONFIG_CPU_SUBTYPE_SH7763) | |
642 | EESR_ADE | | |
643 | #endif | |
644 | EESR_TDE | EESR_TFE)) { | |
86a74ff2 NI |
645 | /* Tx error */ |
646 | u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR); | |
647 | /* dmesg */ | |
648 | printk(KERN_ERR "%s:TX error. status=%8.8x cur_tx=%8.8x ", | |
649 | ndev->name, intr_status, mdp->cur_tx); | |
650 | printk(KERN_ERR "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", | |
651 | mdp->dirty_tx, (u32) ndev->state, edtrr); | |
652 | /* dirty buffer free */ | |
653 | sh_eth_txfree(ndev); | |
654 | ||
655 | /* SH7712 BUG */ | |
656 | if (edtrr ^ EDTRR_TRNS) { | |
657 | /* tx dma start */ | |
658 | ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR); | |
659 | } | |
660 | /* wakeup */ | |
661 | netif_wake_queue(ndev); | |
662 | } | |
663 | } | |
664 | ||
665 | static irqreturn_t sh_eth_interrupt(int irq, void *netdev) | |
666 | { | |
667 | struct net_device *ndev = netdev; | |
668 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
669 | u32 ioaddr, boguscnt = RX_RING_SIZE; | |
670 | u32 intr_status = 0; | |
671 | ||
672 | ioaddr = ndev->base_addr; | |
673 | spin_lock(&mdp->lock); | |
674 | ||
b0ca2a21 | 675 | /* Get interrpt stat */ |
86a74ff2 NI |
676 | intr_status = ctrl_inl(ioaddr + EESR); |
677 | /* Clear interrupt */ | |
678 | ctrl_outl(intr_status, ioaddr + EESR); | |
679 | ||
b0ca2a21 NI |
680 | if (intr_status & (EESR_FRC | /* Frame recv*/ |
681 | EESR_RMAF | /* Multi cast address recv*/ | |
682 | EESR_RRF | /* Bit frame recv */ | |
683 | EESR_RTLF | /* Long frame recv*/ | |
684 | EESR_RTSF | /* short frame recv */ | |
685 | EESR_PRE | /* PHY-LSI recv error */ | |
686 | EESR_CERF)){ /* recv frame CRC error */ | |
86a74ff2 | 687 | sh_eth_rx(ndev); |
b0ca2a21 | 688 | } |
86a74ff2 | 689 | |
b0ca2a21 NI |
690 | /* Tx Check */ |
691 | if (intr_status & TX_CHECK) { | |
86a74ff2 NI |
692 | sh_eth_txfree(ndev); |
693 | netif_wake_queue(ndev); | |
694 | } | |
695 | ||
696 | if (intr_status & EESR_ERR_CHECK) | |
697 | sh_eth_error(ndev, intr_status); | |
698 | ||
699 | if (--boguscnt < 0) { | |
700 | printk(KERN_WARNING | |
701 | "%s: Too much work at interrupt, status=0x%4.4x.\n", | |
702 | ndev->name, intr_status); | |
703 | } | |
704 | ||
705 | spin_unlock(&mdp->lock); | |
706 | ||
707 | return IRQ_HANDLED; | |
708 | } | |
709 | ||
710 | static void sh_eth_timer(unsigned long data) | |
711 | { | |
712 | struct net_device *ndev = (struct net_device *)data; | |
713 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
714 | ||
715 | mod_timer(&mdp->timer, jiffies + (10 * HZ)); | |
716 | } | |
717 | ||
718 | /* PHY state control function */ | |
719 | static void sh_eth_adjust_link(struct net_device *ndev) | |
720 | { | |
721 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
722 | struct phy_device *phydev = mdp->phydev; | |
723 | u32 ioaddr = ndev->base_addr; | |
724 | int new_state = 0; | |
725 | ||
726 | if (phydev->link != PHY_DOWN) { | |
727 | if (phydev->duplex != mdp->duplex) { | |
728 | new_state = 1; | |
729 | mdp->duplex = phydev->duplex; | |
b0ca2a21 NI |
730 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
731 | if (mdp->duplex) { /* FULL */ | |
732 | ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, | |
733 | ioaddr + ECMR); | |
734 | } else { /* Half */ | |
735 | ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, | |
736 | ioaddr + ECMR); | |
737 | } | |
738 | #endif | |
86a74ff2 NI |
739 | } |
740 | ||
741 | if (phydev->speed != mdp->speed) { | |
742 | new_state = 1; | |
743 | mdp->speed = phydev->speed; | |
b0ca2a21 NI |
744 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
745 | switch (mdp->speed) { | |
746 | case 10: /* 10BASE */ | |
747 | ctrl_outl(GECMR_10, ioaddr + GECMR); break; | |
748 | case 100:/* 100BASE */ | |
749 | ctrl_outl(GECMR_100, ioaddr + GECMR); break; | |
750 | case 1000: /* 1000BASE */ | |
751 | ctrl_outl(GECMR_1000, ioaddr + GECMR); break; | |
752 | default: | |
753 | break; | |
754 | } | |
755 | #endif | |
86a74ff2 NI |
756 | } |
757 | if (mdp->link == PHY_DOWN) { | |
758 | ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF) | |
759 | | ECMR_DM, ioaddr + ECMR); | |
760 | new_state = 1; | |
761 | mdp->link = phydev->link; | |
86a74ff2 NI |
762 | } |
763 | } else if (mdp->link) { | |
764 | new_state = 1; | |
765 | mdp->link = PHY_DOWN; | |
766 | mdp->speed = 0; | |
767 | mdp->duplex = -1; | |
86a74ff2 NI |
768 | } |
769 | ||
770 | if (new_state) | |
771 | phy_print_status(phydev); | |
772 | } | |
773 | ||
774 | /* PHY init function */ | |
775 | static int sh_eth_phy_init(struct net_device *ndev) | |
776 | { | |
777 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
778 | char phy_id[BUS_ID_SIZE]; | |
779 | struct phy_device *phydev = NULL; | |
780 | ||
781 | snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, | |
782 | mdp->mii_bus->id , mdp->phy_id); | |
783 | ||
784 | mdp->link = PHY_DOWN; | |
785 | mdp->speed = 0; | |
786 | mdp->duplex = -1; | |
787 | ||
788 | /* Try connect to PHY */ | |
789 | phydev = phy_connect(ndev, phy_id, &sh_eth_adjust_link, | |
790 | 0, PHY_INTERFACE_MODE_MII); | |
791 | if (IS_ERR(phydev)) { | |
792 | dev_err(&ndev->dev, "phy_connect failed\n"); | |
793 | return PTR_ERR(phydev); | |
794 | } | |
795 | dev_info(&ndev->dev, "attached phy %i to driver %s\n", | |
796 | phydev->addr, phydev->drv->name); | |
797 | ||
798 | mdp->phydev = phydev; | |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
803 | /* PHY control start function */ | |
804 | static int sh_eth_phy_start(struct net_device *ndev) | |
805 | { | |
806 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
807 | int ret; | |
808 | ||
809 | ret = sh_eth_phy_init(ndev); | |
810 | if (ret) | |
811 | return ret; | |
812 | ||
813 | /* reset phy - this also wakes it from PDOWN */ | |
814 | phy_write(mdp->phydev, MII_BMCR, BMCR_RESET); | |
815 | phy_start(mdp->phydev); | |
816 | ||
817 | return 0; | |
818 | } | |
819 | ||
820 | /* network device open function */ | |
821 | static int sh_eth_open(struct net_device *ndev) | |
822 | { | |
823 | int ret = 0; | |
824 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
825 | ||
826 | ret = request_irq(ndev->irq, &sh_eth_interrupt, 0, ndev->name, ndev); | |
827 | if (ret) { | |
828 | printk(KERN_ERR "Can not assign IRQ number to %s\n", CARDNAME); | |
829 | return ret; | |
830 | } | |
831 | ||
832 | /* Descriptor set */ | |
833 | ret = sh_eth_ring_init(ndev); | |
834 | if (ret) | |
835 | goto out_free_irq; | |
836 | ||
837 | /* device init */ | |
838 | ret = sh_eth_dev_init(ndev); | |
839 | if (ret) | |
840 | goto out_free_irq; | |
841 | ||
842 | /* PHY control start*/ | |
843 | ret = sh_eth_phy_start(ndev); | |
844 | if (ret) | |
845 | goto out_free_irq; | |
846 | ||
847 | /* Set the timer to check for link beat. */ | |
848 | init_timer(&mdp->timer); | |
849 | mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */ | |
b0ca2a21 | 850 | setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev); |
86a74ff2 NI |
851 | |
852 | return ret; | |
853 | ||
854 | out_free_irq: | |
855 | free_irq(ndev->irq, ndev); | |
856 | return ret; | |
857 | } | |
858 | ||
859 | /* Timeout function */ | |
860 | static void sh_eth_tx_timeout(struct net_device *ndev) | |
861 | { | |
862 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
863 | u32 ioaddr = ndev->base_addr; | |
864 | struct sh_eth_rxdesc *rxdesc; | |
865 | int i; | |
866 | ||
867 | netif_stop_queue(ndev); | |
868 | ||
869 | /* worning message out. */ | |
870 | printk(KERN_WARNING "%s: transmit timed out, status %8.8x," | |
871 | " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR)); | |
872 | ||
873 | /* tx_errors count up */ | |
874 | mdp->stats.tx_errors++; | |
875 | ||
876 | /* timer off */ | |
877 | del_timer_sync(&mdp->timer); | |
878 | ||
879 | /* Free all the skbuffs in the Rx queue. */ | |
880 | for (i = 0; i < RX_RING_SIZE; i++) { | |
881 | rxdesc = &mdp->rx_ring[i]; | |
882 | rxdesc->status = 0; | |
883 | rxdesc->addr = 0xBADF00D0; | |
884 | if (mdp->rx_skbuff[i]) | |
885 | dev_kfree_skb(mdp->rx_skbuff[i]); | |
886 | mdp->rx_skbuff[i] = NULL; | |
887 | } | |
888 | for (i = 0; i < TX_RING_SIZE; i++) { | |
889 | if (mdp->tx_skbuff[i]) | |
890 | dev_kfree_skb(mdp->tx_skbuff[i]); | |
891 | mdp->tx_skbuff[i] = NULL; | |
892 | } | |
893 | ||
894 | /* device init */ | |
895 | sh_eth_dev_init(ndev); | |
896 | ||
897 | /* timer on */ | |
898 | mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */ | |
899 | add_timer(&mdp->timer); | |
900 | } | |
901 | ||
902 | /* Packet transmit function */ | |
903 | static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |
904 | { | |
905 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
906 | struct sh_eth_txdesc *txdesc; | |
907 | u32 entry; | |
908 | int flags; | |
909 | ||
910 | spin_lock_irqsave(&mdp->lock, flags); | |
911 | if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) { | |
912 | if (!sh_eth_txfree(ndev)) { | |
913 | netif_stop_queue(ndev); | |
914 | spin_unlock_irqrestore(&mdp->lock, flags); | |
915 | return 1; | |
916 | } | |
917 | } | |
918 | spin_unlock_irqrestore(&mdp->lock, flags); | |
919 | ||
920 | entry = mdp->cur_tx % TX_RING_SIZE; | |
921 | mdp->tx_skbuff[entry] = skb; | |
922 | txdesc = &mdp->tx_ring[entry]; | |
923 | txdesc->addr = (u32)(skb->data); | |
924 | /* soft swap. */ | |
925 | swaps((char *)(txdesc->addr & ~0x3), skb->len + 2); | |
926 | /* write back */ | |
927 | __flush_purge_region(skb->data, skb->len); | |
928 | if (skb->len < ETHERSMALL) | |
929 | txdesc->buffer_length = ETHERSMALL; | |
930 | else | |
931 | txdesc->buffer_length = skb->len; | |
932 | ||
933 | if (entry >= TX_RING_SIZE - 1) | |
934 | txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); | |
935 | else | |
936 | txdesc->status |= cpu_to_le32(TD_TACT); | |
937 | ||
938 | mdp->cur_tx++; | |
939 | ||
b0ca2a21 NI |
940 | if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS)) |
941 | ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR); | |
942 | ||
86a74ff2 NI |
943 | ndev->trans_start = jiffies; |
944 | ||
945 | return 0; | |
946 | } | |
947 | ||
948 | /* device close function */ | |
949 | static int sh_eth_close(struct net_device *ndev) | |
950 | { | |
951 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
952 | u32 ioaddr = ndev->base_addr; | |
953 | int ringsize; | |
954 | ||
955 | netif_stop_queue(ndev); | |
956 | ||
957 | /* Disable interrupts by clearing the interrupt mask. */ | |
958 | ctrl_outl(0x0000, ioaddr + EESIPR); | |
959 | ||
960 | /* Stop the chip's Tx and Rx processes. */ | |
961 | ctrl_outl(0, ioaddr + EDTRR); | |
962 | ctrl_outl(0, ioaddr + EDRRR); | |
963 | ||
964 | /* PHY Disconnect */ | |
965 | if (mdp->phydev) { | |
966 | phy_stop(mdp->phydev); | |
967 | phy_disconnect(mdp->phydev); | |
968 | } | |
969 | ||
970 | free_irq(ndev->irq, ndev); | |
971 | ||
972 | del_timer_sync(&mdp->timer); | |
973 | ||
974 | /* Free all the skbuffs in the Rx queue. */ | |
975 | sh_eth_ring_free(ndev); | |
976 | ||
977 | /* free DMA buffer */ | |
978 | ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE; | |
979 | dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma); | |
980 | ||
981 | /* free DMA buffer */ | |
982 | ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE; | |
983 | dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma); | |
984 | ||
985 | return 0; | |
986 | } | |
987 | ||
988 | static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) | |
989 | { | |
990 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
991 | u32 ioaddr = ndev->base_addr; | |
992 | ||
993 | mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR); | |
994 | ctrl_outl(0, ioaddr + TROCR); /* (write clear) */ | |
995 | mdp->stats.collisions += ctrl_inl(ioaddr + CDCR); | |
996 | ctrl_outl(0, ioaddr + CDCR); /* (write clear) */ | |
997 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR); | |
998 | ctrl_outl(0, ioaddr + LCCR); /* (write clear) */ | |
b0ca2a21 NI |
999 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
1000 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */ | |
1001 | ctrl_outl(0, ioaddr + CERCR); /* (write clear) */ | |
1002 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */ | |
1003 | ctrl_outl(0, ioaddr + CEECR); /* (write clear) */ | |
1004 | #else | |
86a74ff2 NI |
1005 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR); |
1006 | ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */ | |
b0ca2a21 | 1007 | #endif |
86a74ff2 NI |
1008 | return &mdp->stats; |
1009 | } | |
1010 | ||
1011 | /* ioctl to device funciotn*/ | |
1012 | static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, | |
1013 | int cmd) | |
1014 | { | |
1015 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1016 | struct phy_device *phydev = mdp->phydev; | |
1017 | ||
1018 | if (!netif_running(ndev)) | |
1019 | return -EINVAL; | |
1020 | ||
1021 | if (!phydev) | |
1022 | return -ENODEV; | |
1023 | ||
1024 | return phy_mii_ioctl(phydev, if_mii(rq), cmd); | |
1025 | } | |
1026 | ||
1027 | ||
1028 | /* Multicast reception directions set */ | |
1029 | static void sh_eth_set_multicast_list(struct net_device *ndev) | |
1030 | { | |
1031 | u32 ioaddr = ndev->base_addr; | |
1032 | ||
1033 | if (ndev->flags & IFF_PROMISC) { | |
1034 | /* Set promiscuous. */ | |
1035 | ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM, | |
1036 | ioaddr + ECMR); | |
1037 | } else { | |
1038 | /* Normal, unicast/broadcast-only mode. */ | |
1039 | ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT, | |
1040 | ioaddr + ECMR); | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | /* SuperH's TSU register init function */ | |
1045 | static void sh_eth_tsu_init(u32 ioaddr) | |
1046 | { | |
1047 | ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */ | |
1048 | ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */ | |
1049 | ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */ | |
1050 | ctrl_outl(0xc, ioaddr + TSU_BSYSL0); | |
1051 | ctrl_outl(0xc, ioaddr + TSU_BSYSL1); | |
1052 | ctrl_outl(0, ioaddr + TSU_PRISL0); | |
1053 | ctrl_outl(0, ioaddr + TSU_PRISL1); | |
1054 | ctrl_outl(0, ioaddr + TSU_FWSL0); | |
1055 | ctrl_outl(0, ioaddr + TSU_FWSL1); | |
1056 | ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC); | |
b0ca2a21 NI |
1057 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
1058 | ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */ | |
1059 | ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */ | |
1060 | #else | |
86a74ff2 NI |
1061 | ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */ |
1062 | ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */ | |
b0ca2a21 | 1063 | #endif |
86a74ff2 NI |
1064 | ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */ |
1065 | ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */ | |
1066 | ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */ | |
1067 | ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */ | |
1068 | ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */ | |
1069 | ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */ | |
1070 | ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */ | |
1071 | } | |
1072 | ||
1073 | /* MDIO bus release function */ | |
1074 | static int sh_mdio_release(struct net_device *ndev) | |
1075 | { | |
1076 | struct mii_bus *bus = dev_get_drvdata(&ndev->dev); | |
1077 | ||
1078 | /* unregister mdio bus */ | |
1079 | mdiobus_unregister(bus); | |
1080 | ||
1081 | /* remove mdio bus info from net_device */ | |
1082 | dev_set_drvdata(&ndev->dev, NULL); | |
1083 | ||
1084 | /* free bitbang info */ | |
1085 | free_mdio_bitbang(bus); | |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | ||
1090 | /* MDIO bus init function */ | |
1091 | static int sh_mdio_init(struct net_device *ndev, int id) | |
1092 | { | |
1093 | int ret, i; | |
1094 | struct bb_info *bitbang; | |
1095 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1096 | ||
1097 | /* create bit control struct for PHY */ | |
1098 | bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL); | |
1099 | if (!bitbang) { | |
1100 | ret = -ENOMEM; | |
1101 | goto out; | |
1102 | } | |
1103 | ||
1104 | /* bitbang init */ | |
1105 | bitbang->addr = ndev->base_addr + PIR; | |
1106 | bitbang->mdi_msk = 0x08; | |
1107 | bitbang->mdo_msk = 0x04; | |
1108 | bitbang->mmd_msk = 0x02;/* MMD */ | |
1109 | bitbang->mdc_msk = 0x01; | |
1110 | bitbang->ctrl.ops = &bb_ops; | |
1111 | ||
1112 | /* MII contorller setting */ | |
1113 | mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); | |
1114 | if (!mdp->mii_bus) { | |
1115 | ret = -ENOMEM; | |
1116 | goto out_free_bitbang; | |
1117 | } | |
1118 | ||
1119 | /* Hook up MII support for ethtool */ | |
1120 | mdp->mii_bus->name = "sh_mii"; | |
1121 | mdp->mii_bus->dev = &ndev->dev; | |
0caa1166 | 1122 | mdp->mii_bus->id[0] = id; |
86a74ff2 NI |
1123 | |
1124 | /* PHY IRQ */ | |
1125 | mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
1126 | if (!mdp->mii_bus->irq) { | |
1127 | ret = -ENOMEM; | |
1128 | goto out_free_bus; | |
1129 | } | |
1130 | ||
1131 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
1132 | mdp->mii_bus->irq[i] = PHY_POLL; | |
1133 | ||
1134 | /* regist mdio bus */ | |
1135 | ret = mdiobus_register(mdp->mii_bus); | |
1136 | if (ret) | |
1137 | goto out_free_irq; | |
1138 | ||
1139 | dev_set_drvdata(&ndev->dev, mdp->mii_bus); | |
1140 | ||
1141 | return 0; | |
1142 | ||
1143 | out_free_irq: | |
1144 | kfree(mdp->mii_bus->irq); | |
1145 | ||
1146 | out_free_bus: | |
1147 | kfree(mdp->mii_bus); | |
1148 | ||
1149 | out_free_bitbang: | |
1150 | kfree(bitbang); | |
1151 | ||
1152 | out: | |
1153 | return ret; | |
1154 | } | |
1155 | ||
1156 | static int sh_eth_drv_probe(struct platform_device *pdev) | |
1157 | { | |
1158 | int ret, i, devno = 0; | |
1159 | struct resource *res; | |
1160 | struct net_device *ndev = NULL; | |
1161 | struct sh_eth_private *mdp; | |
1162 | ||
1163 | /* get base addr */ | |
1164 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1165 | if (unlikely(res == NULL)) { | |
1166 | dev_err(&pdev->dev, "invalid resource\n"); | |
1167 | ret = -EINVAL; | |
1168 | goto out; | |
1169 | } | |
1170 | ||
1171 | ndev = alloc_etherdev(sizeof(struct sh_eth_private)); | |
1172 | if (!ndev) { | |
1173 | printk(KERN_ERR "%s: could not allocate device.\n", CARDNAME); | |
1174 | ret = -ENOMEM; | |
1175 | goto out; | |
1176 | } | |
1177 | ||
1178 | /* The sh Ether-specific entries in the device structure. */ | |
1179 | ndev->base_addr = res->start; | |
1180 | devno = pdev->id; | |
1181 | if (devno < 0) | |
1182 | devno = 0; | |
1183 | ||
1184 | ndev->dma = -1; | |
1185 | ndev->irq = platform_get_irq(pdev, 0); | |
1186 | if (ndev->irq < 0) { | |
1187 | ret = -ENODEV; | |
1188 | goto out_release; | |
1189 | } | |
1190 | ||
1191 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1192 | ||
1193 | /* Fill in the fields of the device structure with ethernet values. */ | |
1194 | ether_setup(ndev); | |
1195 | ||
1196 | mdp = netdev_priv(ndev); | |
1197 | spin_lock_init(&mdp->lock); | |
1198 | ||
1199 | /* get PHY ID */ | |
1200 | mdp->phy_id = (int)pdev->dev.platform_data; | |
1201 | ||
1202 | /* set function */ | |
1203 | ndev->open = sh_eth_open; | |
1204 | ndev->hard_start_xmit = sh_eth_start_xmit; | |
1205 | ndev->stop = sh_eth_close; | |
1206 | ndev->get_stats = sh_eth_get_stats; | |
1207 | ndev->set_multicast_list = sh_eth_set_multicast_list; | |
1208 | ndev->do_ioctl = sh_eth_do_ioctl; | |
1209 | ndev->tx_timeout = sh_eth_tx_timeout; | |
1210 | ndev->watchdog_timeo = TX_TIMEOUT; | |
1211 | ||
1212 | mdp->post_rx = POST_RX >> (devno << 1); | |
1213 | mdp->post_fw = POST_FW >> (devno << 1); | |
1214 | ||
1215 | /* read and set MAC address */ | |
1216 | read_mac_address(ndev); | |
1217 | ||
1218 | /* First device only init */ | |
1219 | if (!devno) { | |
1220 | /* reset device */ | |
b0ca2a21 | 1221 | ctrl_outl(ARSTR_ARSTR, ARSTR); |
86a74ff2 NI |
1222 | mdelay(1); |
1223 | ||
1224 | /* TSU init (Init only)*/ | |
1225 | sh_eth_tsu_init(SH_TSU_ADDR); | |
1226 | } | |
1227 | ||
1228 | /* network device register */ | |
1229 | ret = register_netdev(ndev); | |
1230 | if (ret) | |
1231 | goto out_release; | |
1232 | ||
1233 | /* mdio bus init */ | |
1234 | ret = sh_mdio_init(ndev, pdev->id); | |
1235 | if (ret) | |
1236 | goto out_unregister; | |
1237 | ||
1238 | /* pritnt device infomation */ | |
1239 | printk(KERN_INFO "%s: %s at 0x%x, ", | |
1240 | ndev->name, CARDNAME, (u32) ndev->base_addr); | |
1241 | ||
1242 | for (i = 0; i < 5; i++) | |
b0ca2a21 NI |
1243 | printk(KERN_INFO "%02X:", ndev->dev_addr[i]); |
1244 | printk(KERN_INFO "%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq); | |
86a74ff2 NI |
1245 | |
1246 | platform_set_drvdata(pdev, ndev); | |
1247 | ||
1248 | return ret; | |
1249 | ||
1250 | out_unregister: | |
1251 | unregister_netdev(ndev); | |
1252 | ||
1253 | out_release: | |
1254 | /* net_dev free */ | |
1255 | if (ndev) | |
1256 | free_netdev(ndev); | |
1257 | ||
1258 | out: | |
1259 | return ret; | |
1260 | } | |
1261 | ||
1262 | static int sh_eth_drv_remove(struct platform_device *pdev) | |
1263 | { | |
1264 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1265 | ||
1266 | sh_mdio_release(ndev); | |
1267 | unregister_netdev(ndev); | |
1268 | flush_scheduled_work(); | |
1269 | ||
1270 | free_netdev(ndev); | |
1271 | platform_set_drvdata(pdev, NULL); | |
1272 | ||
1273 | return 0; | |
1274 | } | |
1275 | ||
1276 | static struct platform_driver sh_eth_driver = { | |
1277 | .probe = sh_eth_drv_probe, | |
1278 | .remove = sh_eth_drv_remove, | |
1279 | .driver = { | |
1280 | .name = CARDNAME, | |
1281 | }, | |
1282 | }; | |
1283 | ||
1284 | static int __init sh_eth_init(void) | |
1285 | { | |
1286 | return platform_driver_register(&sh_eth_driver); | |
1287 | } | |
1288 | ||
1289 | static void __exit sh_eth_cleanup(void) | |
1290 | { | |
1291 | platform_driver_unregister(&sh_eth_driver); | |
1292 | } | |
1293 | ||
1294 | module_init(sh_eth_init); | |
1295 | module_exit(sh_eth_cleanup); | |
1296 | ||
1297 | MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); | |
1298 | MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); | |
1299 | MODULE_LICENSE("GPL v2"); |