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8ceee660 | 1 | /**************************************************************************** |
177dfcd8 BH |
2 | * Driver for Solarflare Solarstorm network controllers and boards |
3 | * Copyright 2007-2008 Solarflare Communications Inc. | |
8ceee660 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
11 | #include <linux/seq_file.h> | |
12 | #include "efx.h" | |
8ceee660 BH |
13 | #include "mdio_10g.h" |
14 | #include "falcon.h" | |
15 | #include "phy.h" | |
16 | #include "falcon_hwdefs.h" | |
17 | #include "boards.h" | |
e6fa2eb7 BH |
18 | #include "workarounds.h" |
19 | #include "selftest.h" | |
8ceee660 | 20 | |
e6fa2eb7 BH |
21 | /* We expect these MMDs to be in the package. SFT9001 also has a |
22 | * clause 22 extension MMD, but since it doesn't have all the generic | |
23 | * MMD registers it is pointless to include it here. | |
24 | */ | |
27dd2cac BH |
25 | #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PMAPMD | \ |
26 | MDIO_MMDREG_DEVS_PCS | \ | |
04cc8cac BH |
27 | MDIO_MMDREG_DEVS_PHYXS | \ |
28 | MDIO_MMDREG_DEVS_AN) | |
8ceee660 | 29 | |
e6fa2eb7 BH |
30 | #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ |
31 | (1 << LOOPBACK_PCS) | \ | |
32 | (1 << LOOPBACK_PMAPMD) | \ | |
33 | (1 << LOOPBACK_NETWORK)) | |
34 | ||
35 | #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \ | |
36 | (1 << LOOPBACK_PHYXS) | \ | |
37 | (1 << LOOPBACK_PCS) | \ | |
38 | (1 << LOOPBACK_PMAPMD) | \ | |
39 | (1 << LOOPBACK_NETWORK)) | |
3273c2e8 | 40 | |
8ceee660 BH |
41 | /* We complain if we fail to see the link partner as 10G capable this many |
42 | * times in a row (must be > 1 as sampling the autoneg. registers is racy) | |
43 | */ | |
44 | #define MAX_BAD_LP_TRIES (5) | |
45 | ||
e6fa2eb7 BH |
46 | /* LASI Control */ |
47 | #define PMA_PMD_LASI_CTRL 36866 | |
48 | #define PMA_PMD_LASI_STATUS 36869 | |
49 | #define PMA_PMD_LS_ALARM_LBN 0 | |
50 | #define PMA_PMD_LS_ALARM_WIDTH 1 | |
51 | #define PMA_PMD_TX_ALARM_LBN 1 | |
52 | #define PMA_PMD_TX_ALARM_WIDTH 1 | |
53 | #define PMA_PMD_RX_ALARM_LBN 2 | |
54 | #define PMA_PMD_RX_ALARM_WIDTH 1 | |
55 | #define PMA_PMD_AN_ALARM_LBN 3 | |
56 | #define PMA_PMD_AN_ALARM_WIDTH 1 | |
57 | ||
8ceee660 | 58 | /* Extended control register */ |
e6fa2eb7 BH |
59 | #define PMA_PMD_XCONTROL_REG 49152 |
60 | #define PMA_PMD_EXT_GMII_EN_LBN 1 | |
61 | #define PMA_PMD_EXT_GMII_EN_WIDTH 1 | |
62 | #define PMA_PMD_EXT_CLK_OUT_LBN 2 | |
63 | #define PMA_PMD_EXT_CLK_OUT_WIDTH 1 | |
64 | #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */ | |
65 | #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1 | |
66 | #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */ | |
67 | #define PMA_PMD_EXT_CLK312_WIDTH 1 | |
68 | #define PMA_PMD_EXT_LPOWER_LBN 12 | |
69 | #define PMA_PMD_EXT_LPOWER_WIDTH 1 | |
70 | #define PMA_PMD_EXT_SSR_LBN 15 | |
71 | #define PMA_PMD_EXT_SSR_WIDTH 1 | |
8ceee660 BH |
72 | |
73 | /* extended status register */ | |
e6fa2eb7 | 74 | #define PMA_PMD_XSTATUS_REG 49153 |
8ceee660 BH |
75 | #define PMA_PMD_XSTAT_FLP_LBN (12) |
76 | ||
77 | /* LED control register */ | |
e6fa2eb7 | 78 | #define PMA_PMD_LED_CTRL_REG 49159 |
8ceee660 BH |
79 | #define PMA_PMA_LED_ACTIVITY_LBN (3) |
80 | ||
81 | /* LED function override register */ | |
e6fa2eb7 | 82 | #define PMA_PMD_LED_OVERR_REG 49161 |
8ceee660 BH |
83 | /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/ |
84 | #define PMA_PMD_LED_LINK_LBN (0) | |
85 | #define PMA_PMD_LED_SPEED_LBN (2) | |
86 | #define PMA_PMD_LED_TX_LBN (4) | |
87 | #define PMA_PMD_LED_RX_LBN (6) | |
88 | /* Override settings */ | |
89 | #define PMA_PMD_LED_AUTO (0) /* H/W control */ | |
90 | #define PMA_PMD_LED_ON (1) | |
91 | #define PMA_PMD_LED_OFF (2) | |
92 | #define PMA_PMD_LED_FLASH (3) | |
04cc8cac | 93 | #define PMA_PMD_LED_MASK 3 |
8ceee660 BH |
94 | /* All LEDs under hardware control */ |
95 | #define PMA_PMD_LED_FULL_AUTO (0) | |
96 | /* Green and Amber under hardware control, Red off */ | |
97 | #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) | |
98 | ||
e6fa2eb7 BH |
99 | #define PMA_PMD_SPEED_ENABLE_REG 49192 |
100 | #define PMA_PMD_100TX_ADV_LBN 1 | |
101 | #define PMA_PMD_100TX_ADV_WIDTH 1 | |
102 | #define PMA_PMD_1000T_ADV_LBN 2 | |
103 | #define PMA_PMD_1000T_ADV_WIDTH 1 | |
104 | #define PMA_PMD_10000T_ADV_LBN 3 | |
105 | #define PMA_PMD_10000T_ADV_WIDTH 1 | |
106 | #define PMA_PMD_SPEED_LBN 4 | |
107 | #define PMA_PMD_SPEED_WIDTH 4 | |
108 | ||
307505e9 BH |
109 | /* Cable diagnostics - SFT9001 only */ |
110 | #define PMA_PMD_CDIAG_CTRL_REG 49213 | |
111 | #define CDIAG_CTRL_IMMED_LBN 15 | |
112 | #define CDIAG_CTRL_BRK_LINK_LBN 12 | |
113 | #define CDIAG_CTRL_IN_PROG_LBN 11 | |
114 | #define CDIAG_CTRL_LEN_UNIT_LBN 10 | |
115 | #define CDIAG_CTRL_LEN_METRES 1 | |
116 | #define PMA_PMD_CDIAG_RES_REG 49174 | |
117 | #define CDIAG_RES_A_LBN 12 | |
118 | #define CDIAG_RES_B_LBN 8 | |
119 | #define CDIAG_RES_C_LBN 4 | |
120 | #define CDIAG_RES_D_LBN 0 | |
121 | #define CDIAG_RES_WIDTH 4 | |
122 | #define CDIAG_RES_OPEN 2 | |
123 | #define CDIAG_RES_OK 1 | |
124 | #define CDIAG_RES_INVALID 0 | |
125 | /* Set of 4 registers for pairs A-D */ | |
126 | #define PMA_PMD_CDIAG_LEN_REG 49175 | |
127 | ||
e6fa2eb7 BH |
128 | /* Serdes control registers - SFT9001 only */ |
129 | #define PMA_PMD_CSERDES_CTRL_REG 64258 | |
130 | /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */ | |
131 | #define PMA_PMD_CSERDES_DEFAULT 0x000f | |
132 | ||
133 | /* Misc register defines - SFX7101 only */ | |
134 | #define PCS_CLOCK_CTRL_REG 55297 | |
8ceee660 BH |
135 | #define PLL312_RST_N_LBN 2 |
136 | ||
e6fa2eb7 | 137 | #define PCS_SOFT_RST2_REG 55302 |
8ceee660 BH |
138 | #define SERDES_RST_N_LBN 13 |
139 | #define XGXS_RST_N_LBN 12 | |
140 | ||
e6fa2eb7 | 141 | #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */ |
8ceee660 BH |
142 | #define CLK312_EN_LBN 3 |
143 | ||
3273c2e8 | 144 | /* PHYXS registers */ |
e6fa2eb7 BH |
145 | #define PHYXS_XCONTROL_REG 49152 |
146 | #define PHYXS_RESET_LBN 15 | |
147 | #define PHYXS_RESET_WIDTH 1 | |
148 | ||
3273c2e8 BH |
149 | #define PHYXS_TEST1 (49162) |
150 | #define LOOPBACK_NEAR_LBN (8) | |
151 | #define LOOPBACK_NEAR_WIDTH (1) | |
152 | ||
e6fa2eb7 BH |
153 | #define PCS_10GBASET_STAT1 32 |
154 | #define PCS_10GBASET_BLKLK_LBN 0 | |
155 | #define PCS_10GBASET_BLKLK_WIDTH 1 | |
156 | ||
8ceee660 | 157 | /* Boot status register */ |
e6fa2eb7 | 158 | #define PCS_BOOT_STATUS_REG 53248 |
8ceee660 BH |
159 | #define PCS_BOOT_FATAL_ERR_LBN (0) |
160 | #define PCS_BOOT_PROGRESS_LBN (1) | |
161 | #define PCS_BOOT_PROGRESS_WIDTH (2) | |
162 | #define PCS_BOOT_COMPLETE_LBN (3) | |
e6fa2eb7 | 163 | |
8ceee660 BH |
164 | #define PCS_BOOT_MAX_DELAY (100) |
165 | #define PCS_BOOT_POLL_DELAY (10) | |
166 | ||
e6fa2eb7 BH |
167 | /* 100M/1G PHY registers */ |
168 | #define GPHY_XCONTROL_REG 49152 | |
169 | #define GPHY_ISOLATE_LBN 10 | |
170 | #define GPHY_ISOLATE_WIDTH 1 | |
171 | #define GPHY_DUPLEX_LBN 8 | |
172 | #define GPHY_DUPLEX_WIDTH 1 | |
173 | #define GPHY_LOOPBACK_NEAR_LBN 14 | |
174 | #define GPHY_LOOPBACK_NEAR_WIDTH 1 | |
175 | ||
176 | #define C22EXT_STATUS_REG 49153 | |
177 | #define C22EXT_STATUS_LINK_LBN 2 | |
178 | #define C22EXT_STATUS_LINK_WIDTH 1 | |
179 | ||
180 | #define C22EXT_MSTSLV_REG 49162 | |
181 | #define C22EXT_MSTSLV_1000_HD_LBN 10 | |
182 | #define C22EXT_MSTSLV_1000_HD_WIDTH 1 | |
183 | #define C22EXT_MSTSLV_1000_FD_LBN 11 | |
184 | #define C22EXT_MSTSLV_1000_FD_WIDTH 1 | |
185 | ||
8ceee660 BH |
186 | /* Time to wait between powering down the LNPGA and turning off the power |
187 | * rails */ | |
188 | #define LNPGA_PDOWN_WAIT (HZ / 5) | |
189 | ||
190 | static int crc_error_reset_threshold = 100; | |
191 | module_param(crc_error_reset_threshold, int, 0644); | |
192 | MODULE_PARM_DESC(crc_error_reset_threshold, | |
193 | "Max number of CRC errors before XAUI reset"); | |
194 | ||
195 | struct tenxpress_phy_data { | |
3273c2e8 | 196 | enum efx_loopback_mode loopback_mode; |
8ceee660 | 197 | atomic_t bad_crc_count; |
f8b87c17 | 198 | enum efx_phy_mode phy_mode; |
8ceee660 BH |
199 | int bad_lp_tries; |
200 | }; | |
201 | ||
8ceee660 BH |
202 | void tenxpress_crc_err(struct efx_nic *efx) |
203 | { | |
204 | struct tenxpress_phy_data *phy_data = efx->phy_data; | |
205 | if (phy_data != NULL) | |
206 | atomic_inc(&phy_data->bad_crc_count); | |
207 | } | |
208 | ||
e6fa2eb7 BH |
209 | static ssize_t show_phy_short_reach(struct device *dev, |
210 | struct device_attribute *attr, char *buf) | |
211 | { | |
212 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
213 | int reg; | |
214 | ||
215 | reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
216 | MDIO_PMAPMD_10GBT_TXPWR); | |
217 | return sprintf(buf, "%d\n", | |
218 | !!(reg & (1 << MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN))); | |
219 | } | |
220 | ||
221 | static ssize_t set_phy_short_reach(struct device *dev, | |
222 | struct device_attribute *attr, | |
223 | const char *buf, size_t count) | |
224 | { | |
225 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
226 | ||
227 | rtnl_lock(); | |
228 | mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
229 | MDIO_PMAPMD_10GBT_TXPWR, | |
230 | MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN, | |
231 | count != 0 && *buf != '0'); | |
232 | efx_reconfigure_port(efx); | |
233 | rtnl_unlock(); | |
234 | ||
235 | return count; | |
236 | } | |
237 | ||
238 | static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach, | |
239 | set_phy_short_reach); | |
240 | ||
8ceee660 BH |
241 | /* Check that the C166 has booted successfully */ |
242 | static int tenxpress_phy_check(struct efx_nic *efx) | |
243 | { | |
244 | int phy_id = efx->mii.phy_id; | |
245 | int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY; | |
246 | int boot_stat; | |
247 | ||
248 | /* Wait for the boot to complete (or not) */ | |
249 | while (count) { | |
250 | boot_stat = mdio_clause45_read(efx, phy_id, | |
251 | MDIO_MMD_PCS, | |
252 | PCS_BOOT_STATUS_REG); | |
253 | if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN)) | |
254 | break; | |
255 | count--; | |
256 | udelay(PCS_BOOT_POLL_DELAY); | |
257 | } | |
258 | ||
259 | if (!count) { | |
260 | EFX_ERR(efx, "%s: PHY boot timed out. Last status " | |
261 | "%x\n", __func__, | |
262 | (boot_stat >> PCS_BOOT_PROGRESS_LBN) & | |
263 | ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1)); | |
264 | return -ETIMEDOUT; | |
265 | } | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
8ceee660 BH |
270 | static int tenxpress_init(struct efx_nic *efx) |
271 | { | |
e6fa2eb7 BH |
272 | int phy_id = efx->mii.phy_id; |
273 | int reg; | |
274 | int rc; | |
8ceee660 | 275 | |
e6fa2eb7 BH |
276 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
277 | /* Enable 312.5 MHz clock */ | |
278 | mdio_clause45_write(efx, phy_id, | |
279 | MDIO_MMD_PCS, PCS_TEST_SELECT_REG, | |
280 | 1 << CLK312_EN_LBN); | |
281 | } else { | |
282 | /* Enable 312.5 MHz clock and GMII */ | |
283 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, | |
284 | PMA_PMD_XCONTROL_REG); | |
285 | reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | | |
286 | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | | |
287 | (1 << PMA_PMD_EXT_CLK312_LBN)); | |
288 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, | |
289 | PMA_PMD_XCONTROL_REG, reg); | |
290 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, | |
291 | GPHY_XCONTROL_REG, GPHY_ISOLATE_LBN, | |
292 | false); | |
293 | } | |
8ceee660 BH |
294 | |
295 | rc = tenxpress_phy_check(efx); | |
296 | if (rc < 0) | |
297 | return rc; | |
298 | ||
299 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ | |
e6fa2eb7 BH |
300 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
301 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD, | |
302 | PMA_PMD_LED_CTRL_REG, | |
303 | PMA_PMA_LED_ACTIVITY_LBN, | |
304 | true); | |
305 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, | |
306 | PMA_PMD_LED_OVERR_REG, PMA_PMD_LED_DEFAULT); | |
307 | } | |
8ceee660 BH |
308 | |
309 | return rc; | |
310 | } | |
311 | ||
312 | static int tenxpress_phy_init(struct efx_nic *efx) | |
313 | { | |
314 | struct tenxpress_phy_data *phy_data; | |
315 | int rc = 0; | |
316 | ||
317 | phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); | |
9b7bfc4c BH |
318 | if (!phy_data) |
319 | return -ENOMEM; | |
8ceee660 | 320 | efx->phy_data = phy_data; |
f8b87c17 | 321 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 | 322 | |
e6fa2eb7 BH |
323 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { |
324 | if (efx->phy_type == PHY_TYPE_SFT9001A) { | |
325 | int reg; | |
326 | reg = mdio_clause45_read(efx, efx->mii.phy_id, | |
327 | MDIO_MMD_PMAPMD, | |
328 | PMA_PMD_XCONTROL_REG); | |
329 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); | |
330 | mdio_clause45_write(efx, efx->mii.phy_id, | |
331 | MDIO_MMD_PMAPMD, | |
332 | PMA_PMD_XCONTROL_REG, reg); | |
333 | mdelay(200); | |
334 | } | |
8ceee660 | 335 | |
e6fa2eb7 BH |
336 | rc = mdio_clause45_wait_reset_mmds(efx, |
337 | TENXPRESS_REQUIRED_DEVS); | |
338 | if (rc < 0) | |
339 | goto fail; | |
340 | ||
341 | rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); | |
342 | if (rc < 0) | |
343 | goto fail; | |
344 | } | |
8ceee660 BH |
345 | |
346 | rc = tenxpress_init(efx); | |
347 | if (rc < 0) | |
348 | goto fail; | |
349 | ||
e6fa2eb7 BH |
350 | if (efx->phy_type == PHY_TYPE_SFT9001B) { |
351 | rc = device_create_file(&efx->pci_dev->dev, | |
352 | &dev_attr_phy_short_reach); | |
353 | if (rc) | |
354 | goto fail; | |
355 | } | |
356 | ||
8ceee660 BH |
357 | schedule_timeout_uninterruptible(HZ / 5); /* 200ms */ |
358 | ||
e6fa2eb7 | 359 | /* Let XGXS and SerDes out of reset */ |
8ceee660 BH |
360 | falcon_reset_xaui(efx); |
361 | ||
362 | return 0; | |
363 | ||
364 | fail: | |
365 | kfree(efx->phy_data); | |
366 | efx->phy_data = NULL; | |
367 | return rc; | |
368 | } | |
369 | ||
e6fa2eb7 BH |
370 | /* Perform a "special software reset" on the PHY. The caller is |
371 | * responsible for saving and restoring the PHY hardware registers | |
372 | * properly, and masking/unmasking LASI */ | |
3273c2e8 BH |
373 | static int tenxpress_special_reset(struct efx_nic *efx) |
374 | { | |
375 | int rc, reg; | |
376 | ||
c8fcc49c BH |
377 | /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so |
378 | * a special software reset can glitch the XGMAC sufficiently for stats | |
e6fa2eb7 | 379 | * requests to fail. Since we don't often special_reset, just lock. */ |
c8fcc49c | 380 | spin_lock(&efx->stats_lock); |
3273c2e8 BH |
381 | |
382 | /* Initiate reset */ | |
383 | reg = mdio_clause45_read(efx, efx->mii.phy_id, | |
e6fa2eb7 | 384 | MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
3273c2e8 BH |
385 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
386 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
e6fa2eb7 | 387 | PMA_PMD_XCONTROL_REG, reg); |
3273c2e8 | 388 | |
c8fcc49c | 389 | mdelay(200); |
3273c2e8 BH |
390 | |
391 | /* Wait for the blocks to come out of reset */ | |
392 | rc = mdio_clause45_wait_reset_mmds(efx, | |
393 | TENXPRESS_REQUIRED_DEVS); | |
394 | if (rc < 0) | |
c8fcc49c | 395 | goto unlock; |
3273c2e8 BH |
396 | |
397 | /* Try and reconfigure the device */ | |
398 | rc = tenxpress_init(efx); | |
399 | if (rc < 0) | |
c8fcc49c | 400 | goto unlock; |
3273c2e8 | 401 | |
e6fa2eb7 BH |
402 | /* Wait for the XGXS state machine to churn */ |
403 | mdelay(10); | |
c8fcc49c BH |
404 | unlock: |
405 | spin_unlock(&efx->stats_lock); | |
406 | return rc; | |
3273c2e8 BH |
407 | } |
408 | ||
e6fa2eb7 | 409 | static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) |
8ceee660 BH |
410 | { |
411 | struct tenxpress_phy_data *pd = efx->phy_data; | |
04cc8cac BH |
412 | int phy_id = efx->mii.phy_id; |
413 | bool bad_lp; | |
8ceee660 BH |
414 | int reg; |
415 | ||
04cc8cac BH |
416 | if (link_ok) { |
417 | bad_lp = false; | |
418 | } else { | |
419 | /* Check that AN has started but not completed. */ | |
420 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, | |
421 | MDIO_AN_STATUS); | |
422 | if (!(reg & (1 << MDIO_AN_STATUS_LP_AN_CAP_LBN))) | |
423 | return; /* LP status is unknown */ | |
424 | bad_lp = !(reg & (1 << MDIO_AN_STATUS_AN_DONE_LBN)); | |
425 | if (bad_lp) | |
426 | pd->bad_lp_tries++; | |
427 | } | |
428 | ||
8ceee660 | 429 | /* Nothing to do if all is well and was previously so. */ |
04cc8cac | 430 | if (!pd->bad_lp_tries) |
8ceee660 BH |
431 | return; |
432 | ||
04cc8cac BH |
433 | /* Use the RX (red) LED as an error indicator once we've seen AN |
434 | * failure several times in a row, and also log a message. */ | |
435 | if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { | |
436 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, | |
437 | PMA_PMD_LED_OVERR_REG); | |
438 | reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); | |
439 | if (!bad_lp) { | |
440 | reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; | |
441 | } else { | |
442 | reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN; | |
443 | EFX_ERR(efx, "appears to be plugged into a port" | |
444 | " that is not 10GBASE-T capable. The PHY" | |
445 | " supports 10GBASE-T ONLY, so no link can" | |
446 | " be established\n"); | |
447 | } | |
448 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, | |
449 | PMA_PMD_LED_OVERR_REG, reg); | |
450 | pd->bad_lp_tries = bad_lp; | |
8ceee660 | 451 | } |
8ceee660 BH |
452 | } |
453 | ||
e6fa2eb7 | 454 | static bool sfx7101_link_ok(struct efx_nic *efx) |
8ceee660 | 455 | { |
e6fa2eb7 BH |
456 | return mdio_clause45_links_ok(efx, |
457 | MDIO_MMDREG_DEVS_PMAPMD | | |
458 | MDIO_MMDREG_DEVS_PCS | | |
459 | MDIO_MMDREG_DEVS_PHYXS); | |
460 | } | |
461 | ||
462 | static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
463 | { | |
464 | int phy_id = efx->mii.phy_id; | |
465 | u32 reg; | |
466 | ||
caa8d8bb | 467 | if (efx_phy_mode_disabled(efx->phy_mode)) |
e6fa2eb7 | 468 | return false; |
caa8d8bb BH |
469 | else if (efx->loopback_mode == LOOPBACK_GPHY) |
470 | return true; | |
e6fa2eb7 | 471 | else if (efx->loopback_mode) |
04cc8cac BH |
472 | return mdio_clause45_links_ok(efx, |
473 | MDIO_MMDREG_DEVS_PMAPMD | | |
04cc8cac | 474 | MDIO_MMDREG_DEVS_PHYXS); |
e6fa2eb7 BH |
475 | |
476 | /* We must use the same definition of link state as LASI, | |
477 | * otherwise we can miss a link state transition | |
478 | */ | |
479 | if (ecmd->speed == 10000) { | |
480 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS, | |
481 | PCS_10GBASET_STAT1); | |
482 | return reg & (1 << PCS_10GBASET_BLKLK_LBN); | |
483 | } else { | |
484 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, | |
485 | C22EXT_STATUS_REG); | |
486 | return reg & (1 << C22EXT_STATUS_LINK_LBN); | |
487 | } | |
8ceee660 BH |
488 | } |
489 | ||
e6fa2eb7 | 490 | static void tenxpress_ext_loopback(struct efx_nic *efx) |
3273c2e8 BH |
491 | { |
492 | int phy_id = efx->mii.phy_id; | |
3273c2e8 | 493 | |
e6fa2eb7 BH |
494 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS, |
495 | PHYXS_TEST1, LOOPBACK_NEAR_LBN, | |
496 | efx->loopback_mode == LOOPBACK_PHYXS); | |
497 | if (efx->phy_type != PHY_TYPE_SFX7101) | |
498 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, | |
499 | GPHY_XCONTROL_REG, | |
500 | GPHY_LOOPBACK_NEAR_LBN, | |
501 | efx->loopback_mode == LOOPBACK_GPHY); | |
502 | } | |
503 | ||
504 | static void tenxpress_low_power(struct efx_nic *efx) | |
505 | { | |
506 | int phy_id = efx->mii.phy_id; | |
507 | ||
508 | if (efx->phy_type == PHY_TYPE_SFX7101) | |
509 | mdio_clause45_set_mmds_lpower( | |
510 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), | |
511 | TENXPRESS_REQUIRED_DEVS); | |
3273c2e8 | 512 | else |
e6fa2eb7 BH |
513 | mdio_clause45_set_flag( |
514 | efx, phy_id, MDIO_MMD_PMAPMD, | |
515 | PMA_PMD_XCONTROL_REG, PMA_PMD_EXT_LPOWER_LBN, | |
516 | !!(efx->phy_mode & PHY_MODE_LOW_POWER)); | |
3273c2e8 BH |
517 | } |
518 | ||
8ceee660 BH |
519 | static void tenxpress_phy_reconfigure(struct efx_nic *efx) |
520 | { | |
3273c2e8 | 521 | struct tenxpress_phy_data *phy_data = efx->phy_data; |
e6fa2eb7 BH |
522 | struct ethtool_cmd ecmd; |
523 | bool phy_mode_change, loop_reset, loop_toggle, loopback; | |
3273c2e8 | 524 | |
e6fa2eb7 | 525 | if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) { |
f8b87c17 | 526 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 | 527 | return; |
f8b87c17 | 528 | } |
8ceee660 | 529 | |
e6fa2eb7 BH |
530 | tenxpress_low_power(efx); |
531 | ||
532 | phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL && | |
533 | phy_data->phy_mode != PHY_MODE_NORMAL); | |
534 | loopback = LOOPBACK_MASK(efx) & efx->phy_op->loopbacks; | |
535 | loop_toggle = LOOPBACK_CHANGED(phy_data, efx, efx->phy_op->loopbacks); | |
536 | loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) || | |
537 | LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY)); | |
538 | ||
539 | if (loop_reset || loop_toggle || loopback || phy_mode_change) { | |
540 | int rc; | |
541 | ||
542 | efx->phy_op->get_settings(efx, &ecmd); | |
543 | ||
544 | if (loop_reset || phy_mode_change) { | |
545 | tenxpress_special_reset(efx); | |
546 | ||
547 | /* Reset XAUI if we were in 10G, and are staying | |
548 | * in 10G. If we're moving into and out of 10G | |
549 | * then xaui will be reset anyway */ | |
550 | if (EFX_IS10G(efx)) | |
551 | falcon_reset_xaui(efx); | |
552 | } | |
553 | ||
554 | if (efx->phy_type != PHY_TYPE_SFX7101) { | |
555 | /* Only change autoneg once, on coming out or | |
556 | * going into loopback */ | |
557 | if (loop_toggle) | |
558 | ecmd.autoneg = !loopback; | |
559 | if (loopback) { | |
560 | ecmd.duplex = DUPLEX_FULL; | |
561 | if (efx->loopback_mode == LOOPBACK_GPHY) | |
562 | ecmd.speed = SPEED_1000; | |
563 | else | |
564 | ecmd.speed = SPEED_10000; | |
565 | } | |
566 | } | |
567 | ||
568 | rc = efx->phy_op->set_settings(efx, &ecmd); | |
569 | WARN_ON(rc); | |
3273c2e8 BH |
570 | } |
571 | ||
572 | mdio_clause45_transmit_disable(efx); | |
573 | mdio_clause45_phy_reconfigure(efx); | |
e6fa2eb7 | 574 | tenxpress_ext_loopback(efx); |
3273c2e8 | 575 | |
3273c2e8 | 576 | phy_data->loopback_mode = efx->loopback_mode; |
f8b87c17 | 577 | phy_data->phy_mode = efx->phy_mode; |
e6fa2eb7 BH |
578 | |
579 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
580 | efx->link_speed = 10000; | |
581 | efx->link_fd = true; | |
582 | efx->link_up = sfx7101_link_ok(efx); | |
583 | } else { | |
584 | efx->phy_op->get_settings(efx, &ecmd); | |
585 | efx->link_speed = ecmd.speed; | |
586 | efx->link_fd = ecmd.duplex == DUPLEX_FULL; | |
587 | efx->link_up = sft9001_link_ok(efx, &ecmd); | |
588 | } | |
04cc8cac | 589 | efx->link_fc = mdio_clause45_get_pause(efx); |
8ceee660 BH |
590 | } |
591 | ||
8ceee660 | 592 | /* Poll PHY for interrupt */ |
766ca0fa | 593 | static void tenxpress_phy_poll(struct efx_nic *efx) |
8ceee660 BH |
594 | { |
595 | struct tenxpress_phy_data *phy_data = efx->phy_data; | |
766ca0fa BH |
596 | bool change = false, link_ok; |
597 | unsigned link_fc; | |
8ceee660 | 598 | |
e6fa2eb7 BH |
599 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
600 | link_ok = sfx7101_link_ok(efx); | |
601 | if (link_ok != efx->link_up) { | |
602 | change = true; | |
603 | } else { | |
604 | link_fc = mdio_clause45_get_pause(efx); | |
605 | if (link_fc != efx->link_fc) | |
606 | change = true; | |
607 | } | |
608 | sfx7101_check_bad_lp(efx, link_ok); | |
caa8d8bb BH |
609 | } else if (efx->loopback_mode) { |
610 | bool link_ok = sft9001_link_ok(efx, NULL); | |
611 | if (link_ok != efx->link_up) | |
612 | change = true; | |
766ca0fa | 613 | } else { |
e6fa2eb7 BH |
614 | u32 status = mdio_clause45_read(efx, efx->mii.phy_id, |
615 | MDIO_MMD_PMAPMD, | |
616 | PMA_PMD_LASI_STATUS); | |
617 | if (status & (1 << PMA_PMD_LS_ALARM_LBN)) | |
766ca0fa BH |
618 | change = true; |
619 | } | |
8ceee660 | 620 | |
766ca0fa | 621 | if (change) |
177dfcd8 | 622 | falcon_sim_phy_event(efx); |
8ceee660 | 623 | |
f8b87c17 | 624 | if (phy_data->phy_mode != PHY_MODE_NORMAL) |
766ca0fa | 625 | return; |
8ceee660 | 626 | |
e6fa2eb7 BH |
627 | if (EFX_WORKAROUND_10750(efx) && |
628 | atomic_read(&phy_data->bad_crc_count) > crc_error_reset_threshold) { | |
8ceee660 BH |
629 | EFX_ERR(efx, "Resetting XAUI due to too many CRC errors\n"); |
630 | falcon_reset_xaui(efx); | |
631 | atomic_set(&phy_data->bad_crc_count, 0); | |
632 | } | |
8ceee660 BH |
633 | } |
634 | ||
635 | static void tenxpress_phy_fini(struct efx_nic *efx) | |
636 | { | |
637 | int reg; | |
638 | ||
2a7e637d | 639 | if (efx->phy_type == PHY_TYPE_SFT9001B) |
e6fa2eb7 BH |
640 | device_remove_file(&efx->pci_dev->dev, |
641 | &dev_attr_phy_short_reach); | |
2a7e637d BH |
642 | |
643 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
e6fa2eb7 BH |
644 | /* Power down the LNPGA */ |
645 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); | |
646 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
647 | PMA_PMD_XCONTROL_REG, reg); | |
648 | ||
649 | /* Waiting here ensures that the board fini, which can turn | |
650 | * off the power to the PHY, won't get run until the LNPGA | |
651 | * powerdown has been given long enough to complete. */ | |
652 | schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */ | |
653 | } | |
8ceee660 BH |
654 | |
655 | kfree(efx->phy_data); | |
656 | efx->phy_data = NULL; | |
657 | } | |
658 | ||
659 | ||
660 | /* Set the RX and TX LEDs and Link LED flashing. The other LEDs | |
661 | * (which probably aren't wired anyway) are left in AUTO mode */ | |
dc8cfa55 | 662 | void tenxpress_phy_blink(struct efx_nic *efx, bool blink) |
8ceee660 BH |
663 | { |
664 | int reg; | |
665 | ||
666 | if (blink) | |
667 | reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) | | |
668 | (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) | | |
669 | (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN); | |
670 | else | |
671 | reg = PMA_PMD_LED_DEFAULT; | |
672 | ||
673 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
674 | PMA_PMD_LED_OVERR_REG, reg); | |
675 | } | |
676 | ||
307505e9 | 677 | static const char *const sfx7101_test_names[] = { |
1796721a BH |
678 | "bist" |
679 | }; | |
680 | ||
681 | static int | |
307505e9 | 682 | sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
8c8661e4 | 683 | { |
1796721a BH |
684 | int rc; |
685 | ||
686 | if (!(flags & ETH_TEST_FL_OFFLINE)) | |
687 | return 0; | |
688 | ||
8c8661e4 | 689 | /* BIST is automatically run after a special software reset */ |
1796721a BH |
690 | rc = tenxpress_special_reset(efx); |
691 | results[0] = rc ? -1 : 1; | |
692 | return rc; | |
8c8661e4 BH |
693 | } |
694 | ||
307505e9 BH |
695 | static const char *const sft9001_test_names[] = { |
696 | "bist", | |
697 | "cable.pairA.status", | |
698 | "cable.pairB.status", | |
699 | "cable.pairC.status", | |
700 | "cable.pairD.status", | |
701 | "cable.pairA.length", | |
702 | "cable.pairB.length", | |
703 | "cable.pairC.length", | |
704 | "cable.pairD.length", | |
705 | }; | |
706 | ||
707 | static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) | |
708 | { | |
709 | struct ethtool_cmd ecmd; | |
710 | int phy_id = efx->mii.phy_id; | |
711 | int rc = 0, rc2, i, res_reg; | |
712 | ||
713 | if (!(flags & ETH_TEST_FL_OFFLINE)) | |
714 | return 0; | |
715 | ||
716 | efx->phy_op->get_settings(efx, &ecmd); | |
717 | ||
718 | /* Initialise cable diagnostic results to unknown failure */ | |
719 | for (i = 1; i < 9; ++i) | |
720 | results[i] = -1; | |
721 | ||
722 | /* Run cable diagnostics; wait up to 5 seconds for them to complete. | |
723 | * A cable fault is not a self-test failure, but a timeout is. */ | |
724 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, | |
725 | PMA_PMD_CDIAG_CTRL_REG, | |
726 | (1 << CDIAG_CTRL_IMMED_LBN) | | |
727 | (1 << CDIAG_CTRL_BRK_LINK_LBN) | | |
728 | (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN)); | |
729 | i = 0; | |
730 | while (mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, | |
731 | PMA_PMD_CDIAG_CTRL_REG) & | |
732 | (1 << CDIAG_CTRL_IN_PROG_LBN)) { | |
733 | if (++i == 50) { | |
734 | rc = -ETIMEDOUT; | |
735 | goto reset; | |
736 | } | |
737 | msleep(100); | |
738 | } | |
739 | res_reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
740 | PMA_PMD_CDIAG_RES_REG); | |
741 | for (i = 0; i < 4; i++) { | |
742 | int pair_res = | |
743 | (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) | |
744 | & ((1 << CDIAG_RES_WIDTH) - 1); | |
745 | int len_reg = mdio_clause45_read(efx, efx->mii.phy_id, | |
746 | MDIO_MMD_PMAPMD, | |
747 | PMA_PMD_CDIAG_LEN_REG + i); | |
748 | if (pair_res == CDIAG_RES_OK) | |
749 | results[1 + i] = 1; | |
750 | else if (pair_res == CDIAG_RES_INVALID) | |
751 | results[1 + i] = -1; | |
752 | else | |
753 | results[1 + i] = -pair_res; | |
754 | if (pair_res != CDIAG_RES_INVALID && | |
755 | pair_res != CDIAG_RES_OPEN && | |
756 | len_reg != 0xffff) | |
757 | results[5 + i] = len_reg; | |
758 | } | |
759 | ||
760 | /* We must reset to exit cable diagnostic mode. The BIST will | |
761 | * also run when we do this. */ | |
762 | reset: | |
763 | rc2 = tenxpress_special_reset(efx); | |
764 | results[0] = rc2 ? -1 : 1; | |
765 | if (!rc) | |
766 | rc = rc2; | |
767 | ||
768 | rc2 = efx->phy_op->set_settings(efx, &ecmd); | |
769 | if (!rc) | |
770 | rc = rc2; | |
771 | ||
772 | return rc; | |
773 | } | |
774 | ||
04cc8cac BH |
775 | static u32 tenxpress_get_xnp_lpa(struct efx_nic *efx) |
776 | { | |
777 | int phy = efx->mii.phy_id; | |
778 | u32 lpa = 0; | |
779 | int reg; | |
780 | ||
e6fa2eb7 BH |
781 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
782 | reg = mdio_clause45_read(efx, phy, MDIO_MMD_C22EXT, | |
783 | C22EXT_MSTSLV_REG); | |
784 | if (reg & (1 << C22EXT_MSTSLV_1000_HD_LBN)) | |
785 | lpa |= ADVERTISED_1000baseT_Half; | |
786 | if (reg & (1 << C22EXT_MSTSLV_1000_FD_LBN)) | |
787 | lpa |= ADVERTISED_1000baseT_Full; | |
788 | } | |
04cc8cac BH |
789 | reg = mdio_clause45_read(efx, phy, MDIO_MMD_AN, MDIO_AN_10GBT_STATUS); |
790 | if (reg & (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN)) | |
791 | lpa |= ADVERTISED_10000baseT_Full; | |
792 | return lpa; | |
793 | } | |
794 | ||
e6fa2eb7 | 795 | static void sfx7101_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
04cc8cac BH |
796 | { |
797 | mdio_clause45_get_settings_ext(efx, ecmd, ADVERTISED_10000baseT_Full, | |
798 | tenxpress_get_xnp_lpa(efx)); | |
799 | ecmd->supported |= SUPPORTED_10000baseT_Full; | |
800 | ecmd->advertising |= ADVERTISED_10000baseT_Full; | |
801 | } | |
802 | ||
e6fa2eb7 BH |
803 | static void sft9001_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
804 | { | |
805 | int phy_id = efx->mii.phy_id; | |
806 | u32 xnp_adv = 0; | |
807 | int reg; | |
808 | ||
809 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, | |
810 | PMA_PMD_SPEED_ENABLE_REG); | |
811 | if (EFX_WORKAROUND_13204(efx) && (reg & (1 << PMA_PMD_100TX_ADV_LBN))) | |
812 | xnp_adv |= ADVERTISED_100baseT_Full; | |
813 | if (reg & (1 << PMA_PMD_1000T_ADV_LBN)) | |
814 | xnp_adv |= ADVERTISED_1000baseT_Full; | |
815 | if (reg & (1 << PMA_PMD_10000T_ADV_LBN)) | |
816 | xnp_adv |= ADVERTISED_10000baseT_Full; | |
817 | ||
818 | mdio_clause45_get_settings_ext(efx, ecmd, xnp_adv, | |
819 | tenxpress_get_xnp_lpa(efx)); | |
820 | ||
821 | ecmd->supported |= (SUPPORTED_100baseT_Half | | |
822 | SUPPORTED_100baseT_Full | | |
823 | SUPPORTED_1000baseT_Full); | |
824 | ||
825 | /* Use the vendor defined C22ext register for duplex settings */ | |
826 | if (ecmd->speed != SPEED_10000 && !ecmd->autoneg) { | |
827 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, | |
828 | GPHY_XCONTROL_REG); | |
829 | ecmd->duplex = (reg & (1 << GPHY_DUPLEX_LBN) ? | |
830 | DUPLEX_FULL : DUPLEX_HALF); | |
831 | } | |
832 | } | |
833 | ||
834 | static int sft9001_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
835 | { | |
836 | int phy_id = efx->mii.phy_id; | |
837 | int rc; | |
838 | ||
839 | rc = mdio_clause45_set_settings(efx, ecmd); | |
840 | if (rc) | |
841 | return rc; | |
842 | ||
843 | if (ecmd->speed != SPEED_10000 && !ecmd->autoneg) | |
844 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, | |
845 | GPHY_XCONTROL_REG, GPHY_DUPLEX_LBN, | |
846 | ecmd->duplex == DUPLEX_FULL); | |
847 | ||
848 | return rc; | |
849 | } | |
850 | ||
851 | static bool sft9001_set_xnp_advertise(struct efx_nic *efx, u32 advertising) | |
852 | { | |
853 | int phy = efx->mii.phy_id; | |
854 | int reg = mdio_clause45_read(efx, phy, MDIO_MMD_PMAPMD, | |
855 | PMA_PMD_SPEED_ENABLE_REG); | |
856 | bool enabled; | |
857 | ||
858 | reg &= ~((1 << 2) | (1 << 3)); | |
859 | if (EFX_WORKAROUND_13204(efx) && | |
860 | (advertising & ADVERTISED_100baseT_Full)) | |
861 | reg |= 1 << PMA_PMD_100TX_ADV_LBN; | |
862 | if (advertising & ADVERTISED_1000baseT_Full) | |
863 | reg |= 1 << PMA_PMD_1000T_ADV_LBN; | |
864 | if (advertising & ADVERTISED_10000baseT_Full) | |
865 | reg |= 1 << PMA_PMD_10000T_ADV_LBN; | |
866 | mdio_clause45_write(efx, phy, MDIO_MMD_PMAPMD, | |
867 | PMA_PMD_SPEED_ENABLE_REG, reg); | |
868 | ||
869 | enabled = (advertising & | |
870 | (ADVERTISED_1000baseT_Half | | |
871 | ADVERTISED_1000baseT_Full | | |
872 | ADVERTISED_10000baseT_Full)); | |
873 | if (EFX_WORKAROUND_13204(efx)) | |
874 | enabled |= (advertising & ADVERTISED_100baseT_Full); | |
875 | return enabled; | |
876 | } | |
877 | ||
878 | struct efx_phy_operations falcon_sfx7101_phy_ops = { | |
177dfcd8 | 879 | .macs = EFX_XMAC, |
8ceee660 BH |
880 | .init = tenxpress_phy_init, |
881 | .reconfigure = tenxpress_phy_reconfigure, | |
766ca0fa | 882 | .poll = tenxpress_phy_poll, |
8ceee660 | 883 | .fini = tenxpress_phy_fini, |
766ca0fa | 884 | .clear_interrupt = efx_port_dummy_op_void, |
e6fa2eb7 | 885 | .get_settings = sfx7101_get_settings, |
177dfcd8 | 886 | .set_settings = mdio_clause45_set_settings, |
307505e9 BH |
887 | .num_tests = ARRAY_SIZE(sfx7101_test_names), |
888 | .test_names = sfx7101_test_names, | |
889 | .run_tests = sfx7101_run_tests, | |
8ceee660 | 890 | .mmds = TENXPRESS_REQUIRED_DEVS, |
e6fa2eb7 BH |
891 | .loopbacks = SFX7101_LOOPBACKS, |
892 | }; | |
893 | ||
894 | struct efx_phy_operations falcon_sft9001_phy_ops = { | |
895 | .macs = EFX_GMAC | EFX_XMAC, | |
896 | .init = tenxpress_phy_init, | |
897 | .reconfigure = tenxpress_phy_reconfigure, | |
898 | .poll = tenxpress_phy_poll, | |
899 | .fini = tenxpress_phy_fini, | |
900 | .clear_interrupt = efx_port_dummy_op_void, | |
e6fa2eb7 BH |
901 | .get_settings = sft9001_get_settings, |
902 | .set_settings = sft9001_set_settings, | |
903 | .set_xnp_advertise = sft9001_set_xnp_advertise, | |
307505e9 BH |
904 | .num_tests = ARRAY_SIZE(sft9001_test_names), |
905 | .test_names = sft9001_test_names, | |
906 | .run_tests = sft9001_run_tests, | |
e6fa2eb7 BH |
907 | .mmds = TENXPRESS_REQUIRED_DEVS, |
908 | .loopbacks = SFT9001_LOOPBACKS, | |
8ceee660 | 909 | }; |