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1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | /* Common definitions for all Efx net driver code */ | |
12 | ||
13 | #ifndef EFX_NET_DRIVER_H | |
14 | #define EFX_NET_DRIVER_H | |
15 | ||
16 | #include <linux/version.h> | |
17 | #include <linux/netdevice.h> | |
18 | #include <linux/etherdevice.h> | |
19 | #include <linux/ethtool.h> | |
20 | #include <linux/if_vlan.h> | |
21 | #include <linux/timer.h> | |
22 | #include <linux/mii.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/device.h> | |
26 | #include <linux/highmem.h> | |
27 | #include <linux/workqueue.h> | |
28 | #include <linux/inet_lro.h> | |
37b5a603 | 29 | #include <linux/i2c.h> |
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30 | |
31 | #include "enum.h" | |
32 | #include "bitfield.h" | |
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33 | |
34 | #define EFX_MAX_LRO_DESCRIPTORS 8 | |
35 | #define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS | |
36 | ||
37 | /************************************************************************** | |
38 | * | |
39 | * Build definitions | |
40 | * | |
41 | **************************************************************************/ | |
42 | #ifndef EFX_DRIVER_NAME | |
43 | #define EFX_DRIVER_NAME "sfc" | |
44 | #endif | |
8757a5f7 | 45 | #define EFX_DRIVER_VERSION "2.2" |
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46 | |
47 | #ifdef EFX_ENABLE_DEBUG | |
48 | #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) | |
49 | #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) | |
50 | #else | |
51 | #define EFX_BUG_ON_PARANOID(x) do {} while (0) | |
52 | #define EFX_WARN_ON_PARANOID(x) do {} while (0) | |
53 | #endif | |
54 | ||
8ceee660 BH |
55 | /* Un-rate-limited logging */ |
56 | #define EFX_ERR(efx, fmt, args...) \ | |
55668611 | 57 | dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args) |
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58 | |
59 | #define EFX_INFO(efx, fmt, args...) \ | |
55668611 | 60 | dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args) |
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61 | |
62 | #ifdef EFX_ENABLE_DEBUG | |
63 | #define EFX_LOG(efx, fmt, args...) \ | |
55668611 | 64 | dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args) |
8ceee660 BH |
65 | #else |
66 | #define EFX_LOG(efx, fmt, args...) \ | |
55668611 | 67 | dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args) |
8ceee660 BH |
68 | #endif |
69 | ||
70 | #define EFX_TRACE(efx, fmt, args...) do {} while (0) | |
71 | ||
72 | #define EFX_REGDUMP(efx, fmt, args...) do {} while (0) | |
73 | ||
74 | /* Rate-limited logging */ | |
75 | #define EFX_ERR_RL(efx, fmt, args...) \ | |
76 | do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0) | |
77 | ||
78 | #define EFX_INFO_RL(efx, fmt, args...) \ | |
79 | do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0) | |
80 | ||
81 | #define EFX_LOG_RL(efx, fmt, args...) \ | |
82 | do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0) | |
83 | ||
8ceee660 BH |
84 | /************************************************************************** |
85 | * | |
86 | * Efx data structures | |
87 | * | |
88 | **************************************************************************/ | |
89 | ||
90 | #define EFX_MAX_CHANNELS 32 | |
91 | #define EFX_MAX_TX_QUEUES 1 | |
92 | #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS | |
93 | ||
94 | /** | |
95 | * struct efx_special_buffer - An Efx special buffer | |
96 | * @addr: CPU base address of the buffer | |
97 | * @dma_addr: DMA base address of the buffer | |
98 | * @len: Buffer length, in bytes | |
99 | * @index: Buffer index within controller;s buffer table | |
100 | * @entries: Number of buffer table entries | |
101 | * | |
102 | * Special buffers are used for the event queues and the TX and RX | |
103 | * descriptor queues for each channel. They are *not* used for the | |
104 | * actual transmit and receive buffers. | |
105 | * | |
106 | * Note that for Falcon, TX and RX descriptor queues live in host memory. | |
107 | * Allocation and freeing procedures must take this into account. | |
108 | */ | |
109 | struct efx_special_buffer { | |
110 | void *addr; | |
111 | dma_addr_t dma_addr; | |
112 | unsigned int len; | |
113 | int index; | |
114 | int entries; | |
115 | }; | |
116 | ||
117 | /** | |
118 | * struct efx_tx_buffer - An Efx TX buffer | |
119 | * @skb: The associated socket buffer. | |
120 | * Set only on the final fragment of a packet; %NULL for all other | |
121 | * fragments. When this fragment completes, then we can free this | |
122 | * skb. | |
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123 | * @tsoh: The associated TSO header structure, or %NULL if this |
124 | * buffer is not a TSO header. | |
8ceee660 BH |
125 | * @dma_addr: DMA address of the fragment. |
126 | * @len: Length of this fragment. | |
127 | * This field is zero when the queue slot is empty. | |
128 | * @continuation: True if this fragment is not the end of a packet. | |
129 | * @unmap_single: True if pci_unmap_single should be used. | |
130 | * @unmap_addr: DMA address to unmap | |
131 | * @unmap_len: Length of this fragment to unmap | |
132 | */ | |
133 | struct efx_tx_buffer { | |
134 | const struct sk_buff *skb; | |
b9b39b62 | 135 | struct efx_tso_header *tsoh; |
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136 | dma_addr_t dma_addr; |
137 | unsigned short len; | |
138 | unsigned char continuation; | |
139 | unsigned char unmap_single; | |
140 | dma_addr_t unmap_addr; | |
141 | unsigned short unmap_len; | |
142 | }; | |
143 | ||
144 | /** | |
145 | * struct efx_tx_queue - An Efx TX queue | |
146 | * | |
147 | * This is a ring buffer of TX fragments. | |
148 | * Since the TX completion path always executes on the same | |
149 | * CPU and the xmit path can operate on different CPUs, | |
150 | * performance is increased by ensuring that the completion | |
151 | * path and the xmit path operate on different cache lines. | |
152 | * This is particularly important if the xmit path is always | |
153 | * executing on one CPU which is different from the completion | |
154 | * path. There is also a cache line for members which are | |
155 | * read but not written on the fast path. | |
156 | * | |
157 | * @efx: The associated Efx NIC | |
158 | * @queue: DMA queue number | |
159 | * @used: Queue is used by net driver | |
160 | * @channel: The associated channel | |
161 | * @buffer: The software buffer ring | |
162 | * @txd: The hardware descriptor ring | |
163 | * @read_count: Current read pointer. | |
164 | * This is the number of buffers that have been removed from both rings. | |
165 | * @stopped: Stopped flag. | |
166 | * Set if this TX queue is currently stopping its port. | |
167 | * @insert_count: Current insert pointer | |
168 | * This is the number of buffers that have been added to the | |
169 | * software ring. | |
170 | * @write_count: Current write pointer | |
171 | * This is the number of buffers that have been added to the | |
172 | * hardware ring. | |
173 | * @old_read_count: The value of read_count when last checked. | |
174 | * This is here for performance reasons. The xmit path will | |
175 | * only get the up-to-date value of read_count if this | |
176 | * variable indicates that the queue is full. This is to | |
177 | * avoid cache-line ping-pong between the xmit path and the | |
178 | * completion path. | |
b9b39b62 BH |
179 | * @tso_headers_free: A list of TSO headers allocated for this TX queue |
180 | * that are not in use, and so available for new TSO sends. The list | |
181 | * is protected by the TX queue lock. | |
182 | * @tso_bursts: Number of times TSO xmit invoked by kernel | |
183 | * @tso_long_headers: Number of packets with headers too long for standard | |
184 | * blocks | |
185 | * @tso_packets: Number of packets via the TSO xmit path | |
8ceee660 BH |
186 | */ |
187 | struct efx_tx_queue { | |
188 | /* Members which don't change on the fast path */ | |
189 | struct efx_nic *efx ____cacheline_aligned_in_smp; | |
190 | int queue; | |
191 | int used; | |
192 | struct efx_channel *channel; | |
193 | struct efx_nic *nic; | |
194 | struct efx_tx_buffer *buffer; | |
195 | struct efx_special_buffer txd; | |
196 | ||
197 | /* Members used mainly on the completion path */ | |
198 | unsigned int read_count ____cacheline_aligned_in_smp; | |
199 | int stopped; | |
200 | ||
201 | /* Members used only on the xmit path */ | |
202 | unsigned int insert_count ____cacheline_aligned_in_smp; | |
203 | unsigned int write_count; | |
204 | unsigned int old_read_count; | |
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205 | struct efx_tso_header *tso_headers_free; |
206 | unsigned int tso_bursts; | |
207 | unsigned int tso_long_headers; | |
208 | unsigned int tso_packets; | |
8ceee660 BH |
209 | }; |
210 | ||
211 | /** | |
212 | * struct efx_rx_buffer - An Efx RX data buffer | |
213 | * @dma_addr: DMA base address of the buffer | |
214 | * @skb: The associated socket buffer, if any. | |
215 | * If both this and page are %NULL, the buffer slot is currently free. | |
216 | * @page: The associated page buffer, if any. | |
217 | * If both this and skb are %NULL, the buffer slot is currently free. | |
218 | * @data: Pointer to ethernet header | |
219 | * @len: Buffer length, in bytes. | |
220 | * @unmap_addr: DMA address to unmap | |
221 | */ | |
222 | struct efx_rx_buffer { | |
223 | dma_addr_t dma_addr; | |
224 | struct sk_buff *skb; | |
225 | struct page *page; | |
226 | char *data; | |
227 | unsigned int len; | |
228 | dma_addr_t unmap_addr; | |
229 | }; | |
230 | ||
231 | /** | |
232 | * struct efx_rx_queue - An Efx RX queue | |
233 | * @efx: The associated Efx NIC | |
234 | * @queue: DMA queue number | |
235 | * @used: Queue is used by net driver | |
236 | * @channel: The associated channel | |
237 | * @buffer: The software buffer ring | |
238 | * @rxd: The hardware descriptor ring | |
239 | * @added_count: Number of buffers added to the receive queue. | |
240 | * @notified_count: Number of buffers given to NIC (<= @added_count). | |
241 | * @removed_count: Number of buffers removed from the receive queue. | |
242 | * @add_lock: Receive queue descriptor add spin lock. | |
243 | * This lock must be held in order to add buffers to the RX | |
244 | * descriptor ring (rxd and buffer) and to update added_count (but | |
245 | * not removed_count). | |
246 | * @max_fill: RX descriptor maximum fill level (<= ring size) | |
247 | * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill | |
248 | * (<= @max_fill) | |
249 | * @fast_fill_limit: The level to which a fast fill will fill | |
250 | * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill) | |
251 | * @min_fill: RX descriptor minimum non-zero fill level. | |
252 | * This records the minimum fill level observed when a ring | |
253 | * refill was triggered. | |
254 | * @min_overfill: RX descriptor minimum overflow fill level. | |
255 | * This records the minimum fill level at which RX queue | |
256 | * overflow was observed. It should never be set. | |
257 | * @alloc_page_count: RX allocation strategy counter. | |
258 | * @alloc_skb_count: RX allocation strategy counter. | |
259 | * @work: Descriptor push work thread | |
260 | * @buf_page: Page for next RX buffer. | |
261 | * We can use a single page for multiple RX buffers. This tracks | |
262 | * the remaining space in the allocation. | |
263 | * @buf_dma_addr: Page's DMA address. | |
264 | * @buf_data: Page's host address. | |
265 | */ | |
266 | struct efx_rx_queue { | |
267 | struct efx_nic *efx; | |
268 | int queue; | |
269 | int used; | |
270 | struct efx_channel *channel; | |
271 | struct efx_rx_buffer *buffer; | |
272 | struct efx_special_buffer rxd; | |
273 | ||
274 | int added_count; | |
275 | int notified_count; | |
276 | int removed_count; | |
277 | spinlock_t add_lock; | |
278 | unsigned int max_fill; | |
279 | unsigned int fast_fill_trigger; | |
280 | unsigned int fast_fill_limit; | |
281 | unsigned int min_fill; | |
282 | unsigned int min_overfill; | |
283 | unsigned int alloc_page_count; | |
284 | unsigned int alloc_skb_count; | |
285 | struct delayed_work work; | |
286 | unsigned int slow_fill_count; | |
287 | ||
288 | struct page *buf_page; | |
289 | dma_addr_t buf_dma_addr; | |
290 | char *buf_data; | |
291 | }; | |
292 | ||
293 | /** | |
294 | * struct efx_buffer - An Efx general-purpose buffer | |
295 | * @addr: host base address of the buffer | |
296 | * @dma_addr: DMA base address of the buffer | |
297 | * @len: Buffer length, in bytes | |
298 | * | |
299 | * Falcon uses these buffers for its interrupt status registers and | |
300 | * MAC stats dumps. | |
301 | */ | |
302 | struct efx_buffer { | |
303 | void *addr; | |
304 | dma_addr_t dma_addr; | |
305 | unsigned int len; | |
306 | }; | |
307 | ||
308 | ||
309 | /* Flags for channel->used_flags */ | |
310 | #define EFX_USED_BY_RX 1 | |
311 | #define EFX_USED_BY_TX 2 | |
312 | #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX) | |
313 | ||
314 | enum efx_rx_alloc_method { | |
315 | RX_ALLOC_METHOD_AUTO = 0, | |
316 | RX_ALLOC_METHOD_SKB = 1, | |
317 | RX_ALLOC_METHOD_PAGE = 2, | |
318 | }; | |
319 | ||
320 | /** | |
321 | * struct efx_channel - An Efx channel | |
322 | * | |
323 | * A channel comprises an event queue, at least one TX queue, at least | |
324 | * one RX queue, and an associated tasklet for processing the event | |
325 | * queue. | |
326 | * | |
327 | * @efx: Associated Efx NIC | |
328 | * @evqnum: Event queue number | |
329 | * @channel: Channel instance number | |
330 | * @used_flags: Channel is used by net driver | |
331 | * @enabled: Channel enabled indicator | |
332 | * @irq: IRQ number (MSI and MSI-X only) | |
333 | * @has_interrupt: Channel has an interrupt | |
334 | * @irq_moderation: IRQ moderation value (in us) | |
335 | * @napi_dev: Net device used with NAPI | |
336 | * @napi_str: NAPI control structure | |
337 | * @reset_work: Scheduled reset work thread | |
338 | * @work_pending: Is work pending via NAPI? | |
339 | * @eventq: Event queue buffer | |
340 | * @eventq_read_ptr: Event queue read pointer | |
341 | * @last_eventq_read_ptr: Last event queue read pointer value. | |
342 | * @eventq_magic: Event queue magic value for driver-generated test events | |
343 | * @lro_mgr: LRO state | |
344 | * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors | |
345 | * and diagnostic counters | |
346 | * @rx_alloc_push_pages: RX allocation method currently in use for pushing | |
347 | * descriptors | |
348 | * @rx_alloc_pop_pages: RX allocation method currently in use for popping | |
349 | * descriptors | |
350 | * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors | |
351 | * @n_rx_ip_frag_err: Count of RX IP fragment errors | |
352 | * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors | |
353 | * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors | |
354 | * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors | |
355 | * @n_rx_overlength: Count of RX_OVERLENGTH errors | |
356 | * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun | |
357 | */ | |
358 | struct efx_channel { | |
359 | struct efx_nic *efx; | |
360 | int evqnum; | |
361 | int channel; | |
362 | int used_flags; | |
363 | int enabled; | |
364 | int irq; | |
365 | unsigned int has_interrupt; | |
366 | unsigned int irq_moderation; | |
367 | struct net_device *napi_dev; | |
368 | struct napi_struct napi_str; | |
369 | struct work_struct reset_work; | |
370 | int work_pending; | |
371 | struct efx_special_buffer eventq; | |
372 | unsigned int eventq_read_ptr; | |
373 | unsigned int last_eventq_read_ptr; | |
374 | unsigned int eventq_magic; | |
375 | ||
376 | struct net_lro_mgr lro_mgr; | |
377 | int rx_alloc_level; | |
378 | int rx_alloc_push_pages; | |
379 | int rx_alloc_pop_pages; | |
380 | ||
381 | unsigned n_rx_tobe_disc; | |
382 | unsigned n_rx_ip_frag_err; | |
383 | unsigned n_rx_ip_hdr_chksum_err; | |
384 | unsigned n_rx_tcp_udp_chksum_err; | |
385 | unsigned n_rx_frm_trunc; | |
386 | unsigned n_rx_overlength; | |
387 | unsigned n_skbuff_leaks; | |
388 | ||
389 | /* Used to pipeline received packets in order to optimise memory | |
390 | * access with prefetches. | |
391 | */ | |
392 | struct efx_rx_buffer *rx_pkt; | |
393 | int rx_pkt_csummed; | |
394 | ||
395 | }; | |
396 | ||
397 | /** | |
398 | * struct efx_blinker - S/W LED blinking context | |
399 | * @led_num: LED ID (board-specific meaning) | |
400 | * @state: Current state - on or off | |
401 | * @resubmit: Timer resubmission flag | |
402 | * @timer: Control timer for blinking | |
403 | */ | |
404 | struct efx_blinker { | |
405 | int led_num; | |
406 | int state; | |
407 | int resubmit; | |
408 | struct timer_list timer; | |
409 | }; | |
410 | ||
411 | ||
412 | /** | |
413 | * struct efx_board - board information | |
414 | * @type: Board model type | |
415 | * @major: Major rev. ('A', 'B' ...) | |
416 | * @minor: Minor rev. (0, 1, ...) | |
417 | * @init: Initialisation function | |
418 | * @init_leds: Sets up board LEDs | |
419 | * @set_fault_led: Turns the fault LED on or off | |
420 | * @blink: Starts/stops blinking | |
37b5a603 | 421 | * @fini: Cleanup function |
8ceee660 | 422 | * @blinker: used to blink LEDs in software |
37b5a603 BH |
423 | * @hwmon_client: I2C client for hardware monitor |
424 | * @ioexp_client: I2C client for power/port control | |
8ceee660 BH |
425 | */ |
426 | struct efx_board { | |
427 | int type; | |
428 | int major; | |
429 | int minor; | |
430 | int (*init) (struct efx_nic *nic); | |
431 | /* As the LEDs are typically attached to the PHY, LEDs | |
432 | * have a separate init callback that happens later than | |
433 | * board init. */ | |
434 | int (*init_leds)(struct efx_nic *efx); | |
435 | void (*set_fault_led) (struct efx_nic *efx, int state); | |
436 | void (*blink) (struct efx_nic *efx, int start); | |
37b5a603 | 437 | void (*fini) (struct efx_nic *nic); |
8ceee660 | 438 | struct efx_blinker blinker; |
37b5a603 | 439 | struct i2c_client *hwmon_client, *ioexp_client; |
8ceee660 BH |
440 | }; |
441 | ||
3273c2e8 BH |
442 | #define STRING_TABLE_LOOKUP(val, member) \ |
443 | member ## _names[val] | |
444 | ||
8ceee660 BH |
445 | enum efx_int_mode { |
446 | /* Be careful if altering to correct macro below */ | |
447 | EFX_INT_MODE_MSIX = 0, | |
448 | EFX_INT_MODE_MSI = 1, | |
449 | EFX_INT_MODE_LEGACY = 2, | |
450 | EFX_INT_MODE_MAX /* Insert any new items before this */ | |
451 | }; | |
452 | #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) | |
453 | ||
454 | enum phy_type { | |
455 | PHY_TYPE_NONE = 0, | |
456 | PHY_TYPE_CX4_RTMR = 1, | |
457 | PHY_TYPE_1G_ALASKA = 2, | |
458 | PHY_TYPE_10XPRESS = 3, | |
459 | PHY_TYPE_XFP = 4, | |
460 | PHY_TYPE_PM8358 = 6, | |
461 | PHY_TYPE_MAX /* Insert any new items before this */ | |
462 | }; | |
463 | ||
464 | #define PHY_ADDR_INVALID 0xff | |
465 | ||
466 | enum nic_state { | |
467 | STATE_INIT = 0, | |
468 | STATE_RUNNING = 1, | |
469 | STATE_FINI = 2, | |
470 | STATE_RESETTING = 3, /* rtnl_lock always held */ | |
471 | STATE_DISABLED = 4, | |
472 | STATE_MAX, | |
473 | }; | |
474 | ||
475 | /* | |
476 | * Alignment of page-allocated RX buffers | |
477 | * | |
478 | * Controls the number of bytes inserted at the start of an RX buffer. | |
479 | * This is the equivalent of NET_IP_ALIGN [which controls the alignment | |
480 | * of the skb->head for hardware DMA]. | |
481 | */ | |
482 | #if defined(__i386__) || defined(__x86_64__) | |
483 | #define EFX_PAGE_IP_ALIGN 0 | |
484 | #else | |
485 | #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN | |
486 | #endif | |
487 | ||
488 | /* | |
489 | * Alignment of the skb->head which wraps a page-allocated RX buffer | |
490 | * | |
491 | * The skb allocated to wrap an rx_buffer can have this alignment. Since | |
492 | * the data is memcpy'd from the rx_buf, it does not need to be equal to | |
493 | * EFX_PAGE_IP_ALIGN. | |
494 | */ | |
495 | #define EFX_PAGE_SKB_ALIGN 2 | |
496 | ||
497 | /* Forward declaration */ | |
498 | struct efx_nic; | |
499 | ||
500 | /* Pseudo bit-mask flow control field */ | |
501 | enum efx_fc_type { | |
502 | EFX_FC_RX = 1, | |
503 | EFX_FC_TX = 2, | |
504 | EFX_FC_AUTO = 4, | |
505 | }; | |
506 | ||
507 | /** | |
508 | * struct efx_phy_operations - Efx PHY operations table | |
509 | * @init: Initialise PHY | |
510 | * @fini: Shut down PHY | |
511 | * @reconfigure: Reconfigure PHY (e.g. for new link parameters) | |
512 | * @clear_interrupt: Clear down interrupt | |
513 | * @blink: Blink LEDs | |
514 | * @check_hw: Check hardware | |
515 | * @reset_xaui: Reset XAUI side of PHY for (software sequenced reset) | |
516 | * @mmds: MMD presence mask | |
3273c2e8 | 517 | * @loopbacks: Supported loopback modes mask |
8ceee660 BH |
518 | */ |
519 | struct efx_phy_operations { | |
520 | int (*init) (struct efx_nic *efx); | |
521 | void (*fini) (struct efx_nic *efx); | |
522 | void (*reconfigure) (struct efx_nic *efx); | |
523 | void (*clear_interrupt) (struct efx_nic *efx); | |
524 | int (*check_hw) (struct efx_nic *efx); | |
525 | void (*reset_xaui) (struct efx_nic *efx); | |
526 | int mmds; | |
3273c2e8 | 527 | unsigned loopbacks; |
8ceee660 BH |
528 | }; |
529 | ||
530 | /* | |
531 | * Efx extended statistics | |
532 | * | |
533 | * Not all statistics are provided by all supported MACs. The purpose | |
534 | * is this structure is to contain the raw statistics provided by each | |
535 | * MAC. | |
536 | */ | |
537 | struct efx_mac_stats { | |
538 | u64 tx_bytes; | |
539 | u64 tx_good_bytes; | |
540 | u64 tx_bad_bytes; | |
541 | unsigned long tx_packets; | |
542 | unsigned long tx_bad; | |
543 | unsigned long tx_pause; | |
544 | unsigned long tx_control; | |
545 | unsigned long tx_unicast; | |
546 | unsigned long tx_multicast; | |
547 | unsigned long tx_broadcast; | |
548 | unsigned long tx_lt64; | |
549 | unsigned long tx_64; | |
550 | unsigned long tx_65_to_127; | |
551 | unsigned long tx_128_to_255; | |
552 | unsigned long tx_256_to_511; | |
553 | unsigned long tx_512_to_1023; | |
554 | unsigned long tx_1024_to_15xx; | |
555 | unsigned long tx_15xx_to_jumbo; | |
556 | unsigned long tx_gtjumbo; | |
557 | unsigned long tx_collision; | |
558 | unsigned long tx_single_collision; | |
559 | unsigned long tx_multiple_collision; | |
560 | unsigned long tx_excessive_collision; | |
561 | unsigned long tx_deferred; | |
562 | unsigned long tx_late_collision; | |
563 | unsigned long tx_excessive_deferred; | |
564 | unsigned long tx_non_tcpudp; | |
565 | unsigned long tx_mac_src_error; | |
566 | unsigned long tx_ip_src_error; | |
567 | u64 rx_bytes; | |
568 | u64 rx_good_bytes; | |
569 | u64 rx_bad_bytes; | |
570 | unsigned long rx_packets; | |
571 | unsigned long rx_good; | |
572 | unsigned long rx_bad; | |
573 | unsigned long rx_pause; | |
574 | unsigned long rx_control; | |
575 | unsigned long rx_unicast; | |
576 | unsigned long rx_multicast; | |
577 | unsigned long rx_broadcast; | |
578 | unsigned long rx_lt64; | |
579 | unsigned long rx_64; | |
580 | unsigned long rx_65_to_127; | |
581 | unsigned long rx_128_to_255; | |
582 | unsigned long rx_256_to_511; | |
583 | unsigned long rx_512_to_1023; | |
584 | unsigned long rx_1024_to_15xx; | |
585 | unsigned long rx_15xx_to_jumbo; | |
586 | unsigned long rx_gtjumbo; | |
587 | unsigned long rx_bad_lt64; | |
588 | unsigned long rx_bad_64_to_15xx; | |
589 | unsigned long rx_bad_15xx_to_jumbo; | |
590 | unsigned long rx_bad_gtjumbo; | |
591 | unsigned long rx_overflow; | |
592 | unsigned long rx_missed; | |
593 | unsigned long rx_false_carrier; | |
594 | unsigned long rx_symbol_error; | |
595 | unsigned long rx_align_error; | |
596 | unsigned long rx_length_error; | |
597 | unsigned long rx_internal_error; | |
598 | unsigned long rx_good_lt64; | |
599 | }; | |
600 | ||
601 | /* Number of bits used in a multicast filter hash address */ | |
602 | #define EFX_MCAST_HASH_BITS 8 | |
603 | ||
604 | /* Number of (single-bit) entries in a multicast filter hash */ | |
605 | #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) | |
606 | ||
607 | /* An Efx multicast filter hash */ | |
608 | union efx_multicast_hash { | |
609 | u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; | |
610 | efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; | |
611 | }; | |
612 | ||
613 | /** | |
614 | * struct efx_nic - an Efx NIC | |
615 | * @name: Device name (net device name or bus id before net device registered) | |
616 | * @pci_dev: The PCI device | |
617 | * @type: Controller type attributes | |
618 | * @legacy_irq: IRQ number | |
619 | * @workqueue: Workqueue for resets, port reconfigures and the HW monitor | |
620 | * @reset_work: Scheduled reset workitem | |
621 | * @monitor_work: Hardware monitor workitem | |
622 | * @membase_phys: Memory BAR value as physical address | |
623 | * @membase: Memory BAR value | |
624 | * @biu_lock: BIU (bus interface unit) lock | |
625 | * @interrupt_mode: Interrupt mode | |
37b5a603 | 626 | * @i2c_adap: I2C adapter |
8ceee660 BH |
627 | * @board_info: Board-level information |
628 | * @state: Device state flag. Serialised by the rtnl_lock. | |
629 | * @reset_pending: Pending reset method (normally RESET_TYPE_NONE) | |
630 | * @tx_queue: TX DMA queues | |
631 | * @rx_queue: RX DMA queues | |
632 | * @channel: Channels | |
633 | * @rss_queues: Number of RSS queues | |
634 | * @rx_buffer_len: RX buffer length | |
635 | * @rx_buffer_order: Order (log2) of number of pages for each RX buffer | |
636 | * @irq_status: Interrupt status buffer | |
637 | * @last_irq_cpu: Last CPU to handle interrupt. | |
638 | * This register is written with the SMP processor ID whenever an | |
639 | * interrupt is handled. It is used by falcon_test_interrupt() | |
640 | * to verify that an interrupt has occurred. | |
641 | * @n_rx_nodesc_drop_cnt: RX no descriptor drop count | |
642 | * @nic_data: Hardware dependant state | |
643 | * @mac_lock: MAC access lock. Protects @port_enabled, efx_monitor() and | |
644 | * efx_reconfigure_port() | |
645 | * @port_enabled: Port enabled indicator. | |
646 | * Serialises efx_stop_all(), efx_start_all() and efx_monitor() and | |
647 | * efx_reconfigure_work with kernel interfaces. Safe to read under any | |
648 | * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must | |
649 | * be held to modify it. | |
650 | * @port_initialized: Port initialized? | |
651 | * @net_dev: Operating system network device. Consider holding the rtnl lock | |
652 | * @rx_checksum_enabled: RX checksumming enabled | |
653 | * @netif_stop_count: Port stop count | |
654 | * @netif_stop_lock: Port stop lock | |
655 | * @mac_stats: MAC statistics. These include all statistics the MACs | |
656 | * can provide. Generic code converts these into a standard | |
657 | * &struct net_device_stats. | |
658 | * @stats_buffer: DMA buffer for statistics | |
659 | * @stats_lock: Statistics update lock | |
660 | * @mac_address: Permanent MAC address | |
661 | * @phy_type: PHY type | |
662 | * @phy_lock: PHY access lock | |
663 | * @phy_op: PHY interface | |
664 | * @phy_data: PHY private data (including PHY-specific stats) | |
665 | * @mii: PHY interface | |
3273c2e8 | 666 | * @tx_disabled: PHY transmitter turned off |
8ceee660 BH |
667 | * @link_up: Link status |
668 | * @link_options: Link options (MII/GMII format) | |
669 | * @n_link_state_changes: Number of times the link has changed state | |
670 | * @promiscuous: Promiscuous flag. Protected by netif_tx_lock. | |
671 | * @multicast_hash: Multicast hash table | |
672 | * @flow_control: Flow control flags - separate RX/TX so can't use link_options | |
673 | * @reconfigure_work: work item for dealing with PHY events | |
3273c2e8 BH |
674 | * @loopback_mode: Loopback status |
675 | * @loopback_modes: Supported loopback mode bitmask | |
676 | * @loopback_selftest: Offline self-test private state | |
8ceee660 BH |
677 | * |
678 | * The @priv field of the corresponding &struct net_device points to | |
679 | * this. | |
680 | */ | |
681 | struct efx_nic { | |
682 | char name[IFNAMSIZ]; | |
683 | struct pci_dev *pci_dev; | |
684 | const struct efx_nic_type *type; | |
685 | int legacy_irq; | |
686 | struct workqueue_struct *workqueue; | |
687 | struct work_struct reset_work; | |
688 | struct delayed_work monitor_work; | |
086ea356 | 689 | resource_size_t membase_phys; |
8ceee660 BH |
690 | void __iomem *membase; |
691 | spinlock_t biu_lock; | |
692 | enum efx_int_mode interrupt_mode; | |
693 | ||
37b5a603 | 694 | struct i2c_adapter i2c_adap; |
8ceee660 BH |
695 | struct efx_board board_info; |
696 | ||
697 | enum nic_state state; | |
698 | enum reset_type reset_pending; | |
699 | ||
700 | struct efx_tx_queue tx_queue[EFX_MAX_TX_QUEUES]; | |
701 | struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES]; | |
702 | struct efx_channel channel[EFX_MAX_CHANNELS]; | |
703 | ||
704 | int rss_queues; | |
705 | unsigned int rx_buffer_len; | |
706 | unsigned int rx_buffer_order; | |
707 | ||
708 | struct efx_buffer irq_status; | |
709 | volatile signed int last_irq_cpu; | |
710 | ||
711 | unsigned n_rx_nodesc_drop_cnt; | |
712 | ||
5daab96d | 713 | struct falcon_nic_data *nic_data; |
8ceee660 BH |
714 | |
715 | struct mutex mac_lock; | |
716 | int port_enabled; | |
717 | ||
718 | int port_initialized; | |
719 | struct net_device *net_dev; | |
720 | int rx_checksum_enabled; | |
721 | ||
722 | atomic_t netif_stop_count; | |
723 | spinlock_t netif_stop_lock; | |
724 | ||
725 | struct efx_mac_stats mac_stats; | |
726 | struct efx_buffer stats_buffer; | |
727 | spinlock_t stats_lock; | |
728 | ||
729 | unsigned char mac_address[ETH_ALEN]; | |
730 | ||
731 | enum phy_type phy_type; | |
732 | spinlock_t phy_lock; | |
733 | struct efx_phy_operations *phy_op; | |
734 | void *phy_data; | |
735 | struct mii_if_info mii; | |
3273c2e8 | 736 | unsigned tx_disabled; |
8ceee660 BH |
737 | |
738 | int link_up; | |
739 | unsigned int link_options; | |
740 | unsigned int n_link_state_changes; | |
741 | ||
742 | int promiscuous; | |
743 | union efx_multicast_hash multicast_hash; | |
744 | enum efx_fc_type flow_control; | |
745 | struct work_struct reconfigure_work; | |
746 | ||
747 | atomic_t rx_reset; | |
3273c2e8 BH |
748 | enum efx_loopback_mode loopback_mode; |
749 | unsigned int loopback_modes; | |
750 | ||
751 | void *loopback_selftest; | |
8ceee660 BH |
752 | }; |
753 | ||
55668611 BH |
754 | static inline int efx_dev_registered(struct efx_nic *efx) |
755 | { | |
756 | return efx->net_dev->reg_state == NETREG_REGISTERED; | |
757 | } | |
758 | ||
759 | /* Net device name, for inclusion in log messages if it has been registered. | |
760 | * Use efx->name not efx->net_dev->name so that races with (un)registration | |
761 | * are harmless. | |
762 | */ | |
763 | static inline const char *efx_dev_name(struct efx_nic *efx) | |
764 | { | |
765 | return efx_dev_registered(efx) ? efx->name : ""; | |
766 | } | |
767 | ||
8ceee660 BH |
768 | /** |
769 | * struct efx_nic_type - Efx device type definition | |
770 | * @mem_bar: Memory BAR number | |
771 | * @mem_map_size: Memory BAR mapped size | |
772 | * @txd_ptr_tbl_base: TX descriptor ring base address | |
773 | * @rxd_ptr_tbl_base: RX descriptor ring base address | |
774 | * @buf_tbl_base: Buffer table base address | |
775 | * @evq_ptr_tbl_base: Event queue pointer table base address | |
776 | * @evq_rptr_tbl_base: Event queue read-pointer table base address | |
777 | * @txd_ring_mask: TX descriptor ring size - 1 (must be a power of two - 1) | |
778 | * @rxd_ring_mask: RX descriptor ring size - 1 (must be a power of two - 1) | |
779 | * @evq_size: Event queue size (must be a power of two) | |
780 | * @max_dma_mask: Maximum possible DMA mask | |
781 | * @tx_dma_mask: TX DMA mask | |
782 | * @bug5391_mask: Address mask for bug 5391 workaround | |
783 | * @rx_xoff_thresh: RX FIFO XOFF watermark (bytes) | |
784 | * @rx_xon_thresh: RX FIFO XON watermark (bytes) | |
785 | * @rx_buffer_padding: Padding added to each RX buffer | |
786 | * @max_interrupt_mode: Highest capability interrupt mode supported | |
787 | * from &enum efx_init_mode. | |
788 | * @phys_addr_channels: Number of channels with physically addressed | |
789 | * descriptors | |
790 | */ | |
791 | struct efx_nic_type { | |
792 | unsigned int mem_bar; | |
793 | unsigned int mem_map_size; | |
794 | unsigned int txd_ptr_tbl_base; | |
795 | unsigned int rxd_ptr_tbl_base; | |
796 | unsigned int buf_tbl_base; | |
797 | unsigned int evq_ptr_tbl_base; | |
798 | unsigned int evq_rptr_tbl_base; | |
799 | ||
800 | unsigned int txd_ring_mask; | |
801 | unsigned int rxd_ring_mask; | |
802 | unsigned int evq_size; | |
9bbd7d9a | 803 | u64 max_dma_mask; |
8ceee660 BH |
804 | unsigned int tx_dma_mask; |
805 | unsigned bug5391_mask; | |
806 | ||
807 | int rx_xoff_thresh; | |
808 | int rx_xon_thresh; | |
809 | unsigned int rx_buffer_padding; | |
810 | unsigned int max_interrupt_mode; | |
811 | unsigned int phys_addr_channels; | |
812 | }; | |
813 | ||
814 | /************************************************************************** | |
815 | * | |
816 | * Prototypes and inline functions | |
817 | * | |
818 | *************************************************************************/ | |
819 | ||
820 | /* Iterate over all used channels */ | |
821 | #define efx_for_each_channel(_channel, _efx) \ | |
822 | for (_channel = &_efx->channel[0]; \ | |
823 | _channel < &_efx->channel[EFX_MAX_CHANNELS]; \ | |
824 | _channel++) \ | |
825 | if (!_channel->used_flags) \ | |
826 | continue; \ | |
827 | else | |
828 | ||
829 | /* Iterate over all used channels with interrupts */ | |
830 | #define efx_for_each_channel_with_interrupt(_channel, _efx) \ | |
831 | for (_channel = &_efx->channel[0]; \ | |
832 | _channel < &_efx->channel[EFX_MAX_CHANNELS]; \ | |
833 | _channel++) \ | |
834 | if (!(_channel->used_flags && _channel->has_interrupt)) \ | |
835 | continue; \ | |
836 | else | |
837 | ||
838 | /* Iterate over all used TX queues */ | |
839 | #define efx_for_each_tx_queue(_tx_queue, _efx) \ | |
840 | for (_tx_queue = &_efx->tx_queue[0]; \ | |
841 | _tx_queue < &_efx->tx_queue[EFX_MAX_TX_QUEUES]; \ | |
842 | _tx_queue++) \ | |
843 | if (!_tx_queue->used) \ | |
844 | continue; \ | |
845 | else | |
846 | ||
847 | /* Iterate over all TX queues belonging to a channel */ | |
848 | #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ | |
849 | for (_tx_queue = &_channel->efx->tx_queue[0]; \ | |
850 | _tx_queue < &_channel->efx->tx_queue[EFX_MAX_TX_QUEUES]; \ | |
851 | _tx_queue++) \ | |
852 | if ((!_tx_queue->used) || \ | |
853 | (_tx_queue->channel != _channel)) \ | |
854 | continue; \ | |
855 | else | |
856 | ||
857 | /* Iterate over all used RX queues */ | |
858 | #define efx_for_each_rx_queue(_rx_queue, _efx) \ | |
859 | for (_rx_queue = &_efx->rx_queue[0]; \ | |
860 | _rx_queue < &_efx->rx_queue[EFX_MAX_RX_QUEUES]; \ | |
861 | _rx_queue++) \ | |
862 | if (!_rx_queue->used) \ | |
863 | continue; \ | |
864 | else | |
865 | ||
866 | /* Iterate over all RX queues belonging to a channel */ | |
867 | #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ | |
868 | for (_rx_queue = &_channel->efx->rx_queue[0]; \ | |
869 | _rx_queue < &_channel->efx->rx_queue[EFX_MAX_RX_QUEUES]; \ | |
870 | _rx_queue++) \ | |
871 | if ((!_rx_queue->used) || \ | |
872 | (_rx_queue->channel != _channel)) \ | |
873 | continue; \ | |
874 | else | |
875 | ||
876 | /* Returns a pointer to the specified receive buffer in the RX | |
877 | * descriptor queue. | |
878 | */ | |
879 | static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, | |
880 | unsigned int index) | |
881 | { | |
882 | return (&rx_queue->buffer[index]); | |
883 | } | |
884 | ||
885 | /* Set bit in a little-endian bitfield */ | |
886 | static inline void set_bit_le(int nr, unsigned char *addr) | |
887 | { | |
888 | addr[nr / 8] |= (1 << (nr % 8)); | |
889 | } | |
890 | ||
891 | /* Clear bit in a little-endian bitfield */ | |
892 | static inline void clear_bit_le(int nr, unsigned char *addr) | |
893 | { | |
894 | addr[nr / 8] &= ~(1 << (nr % 8)); | |
895 | } | |
896 | ||
897 | ||
898 | /** | |
899 | * EFX_MAX_FRAME_LEN - calculate maximum frame length | |
900 | * | |
901 | * This calculates the maximum frame length that will be used for a | |
902 | * given MTU. The frame length will be equal to the MTU plus a | |
903 | * constant amount of header space and padding. This is the quantity | |
904 | * that the net driver will program into the MAC as the maximum frame | |
905 | * length. | |
906 | * | |
907 | * The 10G MAC used in Falcon requires 8-byte alignment on the frame | |
908 | * length, so we round up to the nearest 8. | |
909 | */ | |
910 | #define EFX_MAX_FRAME_LEN(mtu) \ | |
911 | ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */) + 7) & ~7) | |
912 | ||
913 | ||
914 | #endif /* EFX_NET_DRIVER_H */ |