[linux-2.6-block.git] / drivers / net / sfc / falcon_xmac.c

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2005-2006 Fen Systems Ltd.
 * Copyright 2006-2008 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#include <linux/delay.h>
#include "net_driver.h"
#include "efx.h"
#include "falcon.h"
#include "falcon_hwdefs.h"
#include "falcon_io.h"
#include "mac.h"
#include "gmii.h"
#include "mdio_10g.h"
#include "phy.h"
#include "boards.h"
#include "workarounds.h"

/**************************************************************************
 *
 * MAC register access
 *
 **************************************************************************/

/* Offset of an XMAC register within Falcon */
#define FALCON_XMAC_REG(mac_reg)					\
	(FALCON_XMAC_REGBANK + ((mac_reg) * FALCON_XMAC_REG_SIZE))

void falcon_xmac_writel(struct efx_nic *efx,
			 efx_dword_t *value, unsigned int mac_reg)
{
	efx_oword_t temp;

	EFX_POPULATE_OWORD_1(temp, MAC_DATA, EFX_DWORD_FIELD(*value, MAC_DATA));
	falcon_write(efx, &temp, FALCON_XMAC_REG(mac_reg));
}

void falcon_xmac_readl(struct efx_nic *efx,
		       efx_dword_t *value, unsigned int mac_reg)
{
	efx_oword_t temp;

	falcon_read(efx, &temp, FALCON_XMAC_REG(mac_reg));
	EFX_POPULATE_DWORD_1(*value, MAC_DATA, EFX_OWORD_FIELD(temp, MAC_DATA));
}

/**************************************************************************
 *
 * MAC operations
 *
 *************************************************************************/
static int falcon_reset_xmac(struct efx_nic *efx)
{
	efx_dword_t reg;
	int count;

	EFX_POPULATE_DWORD_1(reg, XM_CORE_RST, 1);
	falcon_xmac_writel(efx, &reg, XM_GLB_CFG_REG_MAC);

	for (count = 0; count < 10000; count++) {	/* wait upto 100ms */
		falcon_xmac_readl(efx, &reg, XM_GLB_CFG_REG_MAC);
		if (EFX_DWORD_FIELD(reg, XM_CORE_RST) == 0)
			return 0;
		udelay(10);
	}

	/* This often fails when DSP is disabled, ignore it */
	if (sfe4001_phy_flash_cfg != 0)
		return 0;

	EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
	return -ETIMEDOUT;
}

/* Configure the XAUI driver that is an output from Falcon */
static void falcon_setup_xaui(struct efx_nic *efx)
{
	efx_dword_t sdctl, txdrv;

	/* Move the XAUI into low power, unless there is no PHY, in
	 * which case the XAUI will have to drive a cable. */
	if (efx->phy_type == PHY_TYPE_NONE)
		return;

	falcon_xmac_readl(efx, &sdctl, XX_SD_CTL_REG_MAC);
	EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_DWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_DWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_DWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_DWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
	falcon_xmac_writel(efx, &sdctl, XX_SD_CTL_REG_MAC);

	EFX_POPULATE_DWORD_8(txdrv,
			     XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
			     XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
			     XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
			     XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
			     XX_DTXD, XX_TXDRV_DTX_DEFAULT,
			     XX_DTXC, XX_TXDRV_DTX_DEFAULT,
			     XX_DTXB, XX_TXDRV_DTX_DEFAULT,
			     XX_DTXA, XX_TXDRV_DTX_DEFAULT);
	falcon_xmac_writel(efx, &txdrv, XX_TXDRV_CTL_REG_MAC);
}

static void falcon_hold_xaui_in_rst(struct efx_nic *efx)
{
	efx_dword_t reg;

	EFX_ZERO_DWORD(reg);
	EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 1);
	EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 1);
	EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 1);
	EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 1);
	EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 1);
	EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 1);
	EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 1);
	EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 1);
	EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 1);
	EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 1);
	EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
	EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1);
	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
	udelay(10);
}

static int _falcon_reset_xaui_a(struct efx_nic *efx)
{
	efx_dword_t reg;

	falcon_hold_xaui_in_rst(efx);
	falcon_xmac_readl(efx, &reg, XX_PWR_RST_REG_MAC);

	/* Follow the RAMBUS XAUI data reset sequencing
	 * Channels A and B first: power down, reset PLL, reset, clear
	 */
	EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 0);
	EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 0);
	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
	udelay(10);

	EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 0);
	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
	udelay(10);

	EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 0);
	EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 0);
	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
	udelay(10);

	/* Channels C and D: power down, reset PLL, reset, clear */
	EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 0);
	EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 0);
	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
	udelay(10);

	EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 0);
	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
	udelay(10);

	EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 0);
	EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 0);
	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
	udelay(10);

	/* Setup XAUI */
	falcon_setup_xaui(efx);
	udelay(10);

	/* Take XGXS out of reset */
	EFX_ZERO_DWORD(reg);
	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
	udelay(10);

	return 0;
}

static int _falcon_reset_xaui_b(struct efx_nic *efx)
{
	efx_dword_t reg;
	int count;

	EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);

	/* Give some time for the link to establish */
	for (count = 0; count < 1000; count++) { /* wait upto 10ms */
		falcon_xmac_readl(efx, &reg, XX_PWR_RST_REG_MAC);
		if (EFX_DWORD_FIELD(reg, XX_RST_XX_EN) == 0) {
			falcon_setup_xaui(efx);
			return 0;
		}
		udelay(10);
	}
	EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
	return -ETIMEDOUT;
}

int falcon_reset_xaui(struct efx_nic *efx)
{
	int rc;

	if (EFX_WORKAROUND_9388(efx)) {
		falcon_hold_xaui_in_rst(efx);
		efx->phy_op->reset_xaui(efx);
		rc = _falcon_reset_xaui_a(efx);
	} else {
		rc = _falcon_reset_xaui_b(efx);
	}
	return rc;
}

static int falcon_xgmii_status(struct efx_nic *efx)
{
	efx_dword_t reg;

	if (FALCON_REV(efx) < FALCON_REV_B0)
		return 1;

	/* The ISR latches, so clear it and re-read */
	falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0);
	falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0);

	if (EFX_DWORD_FIELD(reg, XM_LCLFLT) ||
	    EFX_DWORD_FIELD(reg, XM_RMTFLT)) {
		EFX_INFO(efx, "MGT_INT: "EFX_DWORD_FMT"\n", EFX_DWORD_VAL(reg));
		return 0;
	}

	return 1;
}

static void falcon_mask_status_intr(struct efx_nic *efx, int enable)
{
	efx_dword_t reg;

	if (FALCON_REV(efx) < FALCON_REV_B0)
		return;

	/* Flush the ISR */
	if (enable)
		falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0);

	EFX_POPULATE_DWORD_2(reg,
			     XM_MSK_RMTFLT, !enable,
			     XM_MSK_LCLFLT, !enable);
	falcon_xmac_writel(efx, &reg, XM_MGT_INT_MSK_REG_MAC_B0);
}

int falcon_init_xmac(struct efx_nic *efx)
{
	int rc;

	/* Initialize the PHY first so the clock is around */
	rc = efx->phy_op->init(efx);
	if (rc)
		goto fail1;

	rc = falcon_reset_xaui(efx);
	if (rc)
		goto fail2;

	/* Wait again. Give the PHY and MAC time to come back */
	schedule_timeout_uninterruptible(HZ / 10);

	rc = falcon_reset_xmac(efx);
	if (rc)
		goto fail2;

	falcon_mask_status_intr(efx, 1);
	return 0;

 fail2:
	efx->phy_op->fini(efx);
 fail1:
	return rc;
}

int falcon_xaui_link_ok(struct efx_nic *efx)
{
	efx_dword_t reg;
	int align_done, sync_status, link_ok = 0;

	/* Read link status */
	falcon_xmac_readl(efx, &reg, XX_CORE_STAT_REG_MAC);

	align_done = EFX_DWORD_FIELD(reg, XX_ALIGN_DONE);
	sync_status = EFX_DWORD_FIELD(reg, XX_SYNC_STAT);
	if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
		link_ok = 1;

	/* Clear link status ready for next read */
	EFX_SET_DWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
	EFX_SET_DWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
	EFX_SET_DWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
	falcon_xmac_writel(efx, &reg, XX_CORE_STAT_REG_MAC);

	/* If the link is up, then check the phy side of the xaui link
	 * (error conditions from the wire side propoagate back through
	 * the phy to the xaui side). */
	if (efx->link_up && link_ok) {
		int has_phyxs = efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS);
		if (has_phyxs)
			link_ok = mdio_clause45_phyxgxs_lane_sync(efx);
	}

	/* If the PHY and XAUI links are up, then check the mac's xgmii
	 * fault state */
	if (efx->link_up && link_ok)
		link_ok = falcon_xgmii_status(efx);

	return link_ok;
}

static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
{
	unsigned int max_frame_len;
	efx_dword_t reg;
	int rx_fc = (efx->flow_control & EFX_FC_RX) ? 1 : 0;

	/* Configure MAC  - cut-thru mode is hard wired on */
	EFX_POPULATE_DWORD_3(reg,
			     XM_RX_JUMBO_MODE, 1,
			     XM_TX_STAT_EN, 1,
			     XM_RX_STAT_EN, 1);
	falcon_xmac_writel(efx, &reg, XM_GLB_CFG_REG_MAC);

	/* Configure TX */
	EFX_POPULATE_DWORD_6(reg,
			     XM_TXEN, 1,
			     XM_TX_PRMBL, 1,
			     XM_AUTO_PAD, 1,
			     XM_TXCRC, 1,
			     XM_FCNTL, 1,
			     XM_IPG, 0x3);
	falcon_xmac_writel(efx, &reg, XM_TX_CFG_REG_MAC);

	/* Configure RX */
	EFX_POPULATE_DWORD_5(reg,
			     XM_RXEN, 1,
			     XM_AUTO_DEPAD, 0,
			     XM_ACPT_ALL_MCAST, 1,
			     XM_ACPT_ALL_UCAST, efx->promiscuous,
			     XM_PASS_CRC_ERR, 1);
	falcon_xmac_writel(efx, &reg, XM_RX_CFG_REG_MAC);

	/* Set frame length */
	max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
	EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
	falcon_xmac_writel(efx, &reg, XM_RX_PARAM_REG_MAC);
	EFX_POPULATE_DWORD_2(reg,
			     XM_MAX_TX_FRM_SIZE, max_frame_len,
			     XM_TX_JUMBO_MODE, 1);
	falcon_xmac_writel(efx, &reg, XM_TX_PARAM_REG_MAC);

	EFX_POPULATE_DWORD_2(reg,
			     XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
			     XM_DIS_FCNTL, rx_fc ? 0 : 1);
	falcon_xmac_writel(efx, &reg, XM_FC_REG_MAC);

	/* Set MAC address */
	EFX_POPULATE_DWORD_4(reg,
			     XM_ADR_0, efx->net_dev->dev_addr[0],
			     XM_ADR_1, efx->net_dev->dev_addr[1],
			     XM_ADR_2, efx->net_dev->dev_addr[2],
			     XM_ADR_3, efx->net_dev->dev_addr[3]);
	falcon_xmac_writel(efx, &reg, XM_ADR_LO_REG_MAC);
	EFX_POPULATE_DWORD_2(reg,
			     XM_ADR_4, efx->net_dev->dev_addr[4],
			     XM_ADR_5, efx->net_dev->dev_addr[5]);
	falcon_xmac_writel(efx, &reg, XM_ADR_HI_REG_MAC);
}

/* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
 * to come back up. Bash it until it comes back up */
static int falcon_check_xaui_link_up(struct efx_nic *efx)
{
	int max_tries, tries;
	tries = EFX_WORKAROUND_5147(efx) ? 5 : 1;
	max_tries = tries;

	if (efx->phy_type == PHY_TYPE_NONE)
		return 0;

	while (tries) {
		if (falcon_xaui_link_ok(efx))
			return 1;

		EFX_LOG(efx, "%s Clobbering XAUI (%d tries left).\n",
			__func__, tries);
		(void) falcon_reset_xaui(efx);
		udelay(200);
		tries--;
	}

	EFX_ERR(efx, "Failed to bring XAUI link back up in %d tries!\n",
		max_tries);
	return 0;
}

void falcon_reconfigure_xmac(struct efx_nic *efx)
{
	int xaui_link_ok;

	falcon_mask_status_intr(efx, 0);

	falcon_deconfigure_mac_wrapper(efx);
	efx->phy_op->reconfigure(efx);
	falcon_reconfigure_xmac_core(efx);
	falcon_reconfigure_mac_wrapper(efx);

	/* Ensure XAUI link is up */
	xaui_link_ok = falcon_check_xaui_link_up(efx);

	if (xaui_link_ok && efx->link_up)
		falcon_mask_status_intr(efx, 1);
}

void falcon_fini_xmac(struct efx_nic *efx)
{
	/* Isolate the MAC - PHY */
	falcon_deconfigure_mac_wrapper(efx);

	/* Potentially power down the PHY */
	efx->phy_op->fini(efx);
}

void falcon_update_stats_xmac(struct efx_nic *efx)
{
	struct efx_mac_stats *mac_stats = &efx->mac_stats;
	int rc;

	rc = falcon_dma_stats(efx, XgDmaDone_offset);
	if (rc)
		return;

	/* Update MAC stats from DMAed values */
	FALCON_STAT(efx, XgRxOctets, rx_bytes);
	FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
	FALCON_STAT(efx, XgRxPkts, rx_packets);
	FALCON_STAT(efx, XgRxPktsOK, rx_good);
	FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
	FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
	FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
	FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
	FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
	FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
	FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
	FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
	FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
	FALCON_STAT(efx, XgRxAlignError, rx_align_error);
	FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
	FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
	FALCON_STAT(efx, XgRxControlPkts, rx_control);
	FALCON_STAT(efx, XgRxPausePkts, rx_pause);
	FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
	FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
	FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
	FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
	FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
	FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
	FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
	FALCON_STAT(efx, XgRxLengthError, rx_length_error);
	FALCON_STAT(efx, XgTxPkts, tx_packets);
	FALCON_STAT(efx, XgTxOctets, tx_bytes);
	FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
	FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
	FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
	FALCON_STAT(efx, XgTxControlPkts, tx_control);
	FALCON_STAT(efx, XgTxPausePkts, tx_pause);
	FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
	FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
	FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
	FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
	FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
	FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
	FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
	FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
	FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
	FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
	FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
	FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);

	/* Update derived statistics */
	mac_stats->tx_good_bytes =
		(mac_stats->tx_bytes - mac_stats->tx_bad_bytes);
	mac_stats->rx_bad_bytes =
		(mac_stats->rx_bytes - mac_stats->rx_good_bytes);
}

int falcon_check_xmac(struct efx_nic *efx)
{
	unsigned xaui_link_ok;
	int rc;

	falcon_mask_status_intr(efx, 0);
	xaui_link_ok = falcon_xaui_link_ok(efx);

	if (EFX_WORKAROUND_5147(efx) && !xaui_link_ok)
		(void) falcon_reset_xaui(efx);

	/* Call the PHY check_hw routine */
	rc = efx->phy_op->check_hw(efx);

	/* Unmask interrupt if everything was (and still is) ok */
	if (xaui_link_ok && efx->link_up)
		falcon_mask_status_intr(efx, 1);

	return rc;
}

/* Simulate a PHY event */
void falcon_xmac_sim_phy_event(struct efx_nic *efx)
{
	efx_qword_t phy_event;

	EFX_POPULATE_QWORD_2(phy_event,
			     EV_CODE, GLOBAL_EV_DECODE,
			     XG_PHY_INTR, 1);
	falcon_generate_event(&efx->channel[0], &phy_event);
}

int falcon_xmac_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
{
	mdio_clause45_get_settings(efx, ecmd);
	ecmd->transceiver = XCVR_INTERNAL;
	ecmd->phy_address = efx->mii.phy_id;
	ecmd->autoneg = AUTONEG_DISABLE;
	ecmd->duplex = DUPLEX_FULL;
	return 0;
}

int falcon_xmac_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
{
	if (ecmd->transceiver != XCVR_INTERNAL)
		return -EINVAL;
	if (ecmd->autoneg != AUTONEG_DISABLE)
		return -EINVAL;
	if (ecmd->duplex != DUPLEX_FULL)
		return -EINVAL;

	return mdio_clause45_set_settings(efx, ecmd);
}


int falcon_xmac_set_pause(struct efx_nic *efx, enum efx_fc_type flow_control)
{
	int reset;

	if (flow_control & EFX_FC_AUTO) {
		EFX_LOG(efx, "10G does not support flow control "
			"autonegotiation\n");
		return -EINVAL;
	}

	if ((flow_control & EFX_FC_TX) && !(flow_control & EFX_FC_RX))
		return -EINVAL;

	/* TX flow control may automatically turn itself off if the
	 * link partner (intermittently) stops responding to pause
	 * frames. There isn't any indication that this has happened,
	 * so the best we do is leave it up to the user to spot this
	 * and fix it be cycling transmit flow control on this end. */
	reset = ((flow_control & EFX_FC_TX) &&
		 !(efx->flow_control & EFX_FC_TX));
	if (EFX_WORKAROUND_11482(efx) && reset) {
		if (FALCON_REV(efx) >= FALCON_REV_B0) {
			/* Recover by resetting the EM block */
			if (efx->link_up)
				falcon_drain_tx_fifo(efx);
		} else {
			/* Schedule a reset to recover */
			efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
		}
	}

	efx->flow_control = flow_control;

	return 0;
}
Commit	Line	Data
8ceee660 BH	1	/****************************************************************************
	2	* Driver for Solarflare Solarstorm network controllers and boards
	3	* Copyright 2005-2006 Fen Systems Ltd.
	4	* Copyright 2006-2008 Solarflare Communications Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation, incorporated herein by reference.
	9	*/
	10
	11	#include <linux/delay.h>
	12	#include "net_driver.h"
	13	#include "efx.h"
	14	#include "falcon.h"
	15	#include "falcon_hwdefs.h"
	16	#include "falcon_io.h"
	17	#include "mac.h"
	18	#include "gmii.h"
	19	#include "mdio_10g.h"
	20	#include "phy.h"
	21	#include "boards.h"
	22	#include "workarounds.h"
	23
	24	/**************************************************************************
	25	*
	26	* MAC register access
	27	*
	28	**************************************************************************/
	29
	30	/* Offset of an XMAC register within Falcon */
	31	#define FALCON_XMAC_REG(mac_reg) \
	32	(FALCON_XMAC_REGBANK + ((mac_reg) * FALCON_XMAC_REG_SIZE))
	33
	34	void falcon_xmac_writel(struct efx_nic *efx,
e52eddae	35	efx_dword_t *value, unsigned int mac_reg)
8ceee660 BH	36	{
	37	efx_oword_t temp;
	38
	39	EFX_POPULATE_OWORD_1(temp, MAC_DATA, EFX_DWORD_FIELD(*value, MAC_DATA));
	40	falcon_write(efx, &temp, FALCON_XMAC_REG(mac_reg));
	41	}
	42
	43	void falcon_xmac_readl(struct efx_nic *efx,
	44	efx_dword_t *value, unsigned int mac_reg)
	45	{
	46	efx_oword_t temp;
	47
	48	falcon_read(efx, &temp, FALCON_XMAC_REG(mac_reg));
	49	EFX_POPULATE_DWORD_1(*value, MAC_DATA, EFX_OWORD_FIELD(temp, MAC_DATA));
	50	}
	51
	52	/**************************************************************************
	53	*
	54	* MAC operations
	55	*
	56	*************************************************************************/
	57	static int falcon_reset_xmac(struct efx_nic *efx)
	58	{
	59	efx_dword_t reg;
	60	int count;
	61
	62	EFX_POPULATE_DWORD_1(reg, XM_CORE_RST, 1);
	63	falcon_xmac_writel(efx, &reg, XM_GLB_CFG_REG_MAC);
	64
	65	for (count = 0; count < 10000; count++) { /* wait upto 100ms */
	66	falcon_xmac_readl(efx, &reg, XM_GLB_CFG_REG_MAC);
	67	if (EFX_DWORD_FIELD(reg, XM_CORE_RST) == 0)
	68	return 0;
	69	udelay(10);
	70	}
	71
75f2d3ea BH	72	/* This often fails when DSP is disabled, ignore it */
	73	if (sfe4001_phy_flash_cfg != 0)
	74	return 0;
	75
8ceee660 BH	76	EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
	77	return -ETIMEDOUT;
	78	}
	79
	80	/* Configure the XAUI driver that is an output from Falcon */
	81	static void falcon_setup_xaui(struct efx_nic *efx)
	82	{
	83	efx_dword_t sdctl, txdrv;
	84
	85	/* Move the XAUI into low power, unless there is no PHY, in
	86	* which case the XAUI will have to drive a cable. */
	87	if (efx->phy_type == PHY_TYPE_NONE)
	88	return;
	89
	90	falcon_xmac_readl(efx, &sdctl, XX_SD_CTL_REG_MAC);
	91	EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
	92	EFX_SET_DWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
	93	EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
	94	EFX_SET_DWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
	95	EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
	96	EFX_SET_DWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
	97	EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
	98	EFX_SET_DWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
	99	falcon_xmac_writel(efx, &sdctl, XX_SD_CTL_REG_MAC);
	100
	101	EFX_POPULATE_DWORD_8(txdrv,
	102	XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
	103	XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
	104	XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
	105	XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
	106	XX_DTXD, XX_TXDRV_DTX_DEFAULT,
	107	XX_DTXC, XX_TXDRV_DTX_DEFAULT,
	108	XX_DTXB, XX_TXDRV_DTX_DEFAULT,
	109	XX_DTXA, XX_TXDRV_DTX_DEFAULT);
	110	falcon_xmac_writel(efx, &txdrv, XX_TXDRV_CTL_REG_MAC);
	111	}
	112
	113	static void falcon_hold_xaui_in_rst(struct efx_nic *efx)
	114	{
	115	efx_dword_t reg;
	116
	117	EFX_ZERO_DWORD(reg);
	118	EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 1);
	119	EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 1);
	120	EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 1);
	121	EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 1);
	122	EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 1);
	123	EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 1);
	124	EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 1);
	125	EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 1);
	126	EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 1);
	127	EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 1);
	128	EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
	129	EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1);
	130	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
	131	udelay(10);
	132	}
	133
	134	static int _falcon_reset_xaui_a(struct efx_nic *efx)
	135	{
	136	efx_dword_t reg;
	137
	138	falcon_hold_xaui_in_rst(efx);
	139	falcon_xmac_readl(efx, &reg, XX_PWR_RST_REG_MAC);
140
141	/* Follow the RAMBUS XAUI data reset sequencing
142	* Channels A and B first: power down, reset PLL, reset, clear
143	*/
144	EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 0);
145	EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 0);
146	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
147	udelay(10);
148
149	EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 0);
150	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
151	udelay(10);
152
153	EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 0);
154	EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 0);
155	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
156	udelay(10);
157
158	/* Channels C and D: power down, reset PLL, reset, clear */
159	EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 0);
160	EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 0);
161	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
162	udelay(10);
163
164	EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 0);
165	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
166	udelay(10);
167
168	EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 0);
169	EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 0);
170	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
171	udelay(10);
172
173	/* Setup XAUI */
174	falcon_setup_xaui(efx);
175	udelay(10);
176
177	/* Take XGXS out of reset */
178	EFX_ZERO_DWORD(reg);
179	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
180	udelay(10);
181
182	return 0;
183	}
184
185	static int _falcon_reset_xaui_b(struct efx_nic *efx)
186	{
187	efx_dword_t reg;
188	int count;
189
190	EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
191	falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
192
193	/* Give some time for the link to establish */
194	for (count = 0; count < 1000; count++) { /* wait upto 10ms */
195	falcon_xmac_readl(efx, &reg, XX_PWR_RST_REG_MAC);
196	if (EFX_DWORD_FIELD(reg, XX_RST_XX_EN) == 0) {
197	falcon_setup_xaui(efx);
198	return 0;
199	}
200	udelay(10);
201	}
202	EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
203	return -ETIMEDOUT;
204	}
205
206	int falcon_reset_xaui(struct efx_nic *efx)
207	{
208	int rc;
209
210	if (EFX_WORKAROUND_9388(efx)) {
211	falcon_hold_xaui_in_rst(efx);
212	efx->phy_op->reset_xaui(efx);
213	rc = _falcon_reset_xaui_a(efx);
214	} else {
215	rc = _falcon_reset_xaui_b(efx);
216	}
217	return rc;
218	}
219
220	static int falcon_xgmii_status(struct efx_nic *efx)
221	{
222	efx_dword_t reg;
223
224	if (FALCON_REV(efx) < FALCON_REV_B0)
225	return 1;
226
227	/* The ISR latches, so clear it and re-read */
228	falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0);
229	falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0);
e52eddae	230
8ceee660 BH	231	if (EFX_DWORD_FIELD(reg, XM_LCLFLT) \|\|
	232	EFX_DWORD_FIELD(reg, XM_RMTFLT)) {
	233	EFX_INFO(efx, "MGT_INT: "EFX_DWORD_FMT"\n", EFX_DWORD_VAL(reg));
	234	return 0;
	235	}
	236
	237	return 1;
	238	}
	239
	240	static void falcon_mask_status_intr(struct efx_nic *efx, int enable)
	241	{
	242	efx_dword_t reg;
	243
	244	if (FALCON_REV(efx) < FALCON_REV_B0)
	245	return;
	246
	247	/* Flush the ISR */
	248	if (enable)
	249	falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0);
	250
	251	EFX_POPULATE_DWORD_2(reg,
	252	XM_MSK_RMTFLT, !enable,
	253	XM_MSK_LCLFLT, !enable);
	254	falcon_xmac_writel(efx, &reg, XM_MGT_INT_MSK_REG_MAC_B0);
	255	}
	256
	257	int falcon_init_xmac(struct efx_nic *efx)
	258	{
	259	int rc;
	260
	261	/* Initialize the PHY first so the clock is around */
	262	rc = efx->phy_op->init(efx);
	263	if (rc)
	264	goto fail1;
	265
	266	rc = falcon_reset_xaui(efx);
	267	if (rc)
	268	goto fail2;
	269
	270	/* Wait again. Give the PHY and MAC time to come back */
	271	schedule_timeout_uninterruptible(HZ / 10);
	272
	273	rc = falcon_reset_xmac(efx);
	274	if (rc)
	275	goto fail2;
	276
	277	falcon_mask_status_intr(efx, 1);
	278	return 0;
	279
	280	fail2:
	281	efx->phy_op->fini(efx);
	282	fail1:
	283	return rc;
	284	}
	285
	286	int falcon_xaui_link_ok(struct efx_nic *efx)
	287	{
	288	efx_dword_t reg;
	289	int align_done, sync_status, link_ok = 0;
	290
	291	/* Read link status */
	292	falcon_xmac_readl(efx, &reg, XX_CORE_STAT_REG_MAC);
	293
	294	align_done = EFX_DWORD_FIELD(reg, XX_ALIGN_DONE);
295	sync_status = EFX_DWORD_FIELD(reg, XX_SYNC_STAT);
296	if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
297	link_ok = 1;
298
299	/* Clear link status ready for next read */
300	EFX_SET_DWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
301	EFX_SET_DWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
302	EFX_SET_DWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
303	falcon_xmac_writel(efx, &reg, XX_CORE_STAT_REG_MAC);
304
305	/* If the link is up, then check the phy side of the xaui link
306	* (error conditions from the wire side propoagate back through
307	* the phy to the xaui side). */
308	if (efx->link_up && link_ok) {
309	int has_phyxs = efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS);
310	if (has_phyxs)
311	link_ok = mdio_clause45_phyxgxs_lane_sync(efx);
312	}
313
314	/* If the PHY and XAUI links are up, then check the mac's xgmii
315	* fault state */
316	if (efx->link_up && link_ok)
317	link_ok = falcon_xgmii_status(efx);
318
319	return link_ok;
320	}
321
322	static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
323	{
324	unsigned int max_frame_len;
325	efx_dword_t reg;
326	int rx_fc = (efx->flow_control & EFX_FC_RX) ? 1 : 0;
327
328	/* Configure MAC - cut-thru mode is hard wired on */
329	EFX_POPULATE_DWORD_3(reg,
330	XM_RX_JUMBO_MODE, 1,
331	XM_TX_STAT_EN, 1,
332	XM_RX_STAT_EN, 1);
333	falcon_xmac_writel(efx, &reg, XM_GLB_CFG_REG_MAC);
334
335	/* Configure TX */
336	EFX_POPULATE_DWORD_6(reg,
337	XM_TXEN, 1,
338	XM_TX_PRMBL, 1,
339	XM_AUTO_PAD, 1,
340	XM_TXCRC, 1,
341	XM_FCNTL, 1,
342	XM_IPG, 0x3);
343	falcon_xmac_writel(efx, &reg, XM_TX_CFG_REG_MAC);
344
345	/* Configure RX */
346	EFX_POPULATE_DWORD_5(reg,
347	XM_RXEN, 1,
348	XM_AUTO_DEPAD, 0,
349	XM_ACPT_ALL_MCAST, 1,
350	XM_ACPT_ALL_UCAST, efx->promiscuous,
351	XM_PASS_CRC_ERR, 1);
352	falcon_xmac_writel(efx, &reg, XM_RX_CFG_REG_MAC);
353
354	/* Set frame length */
355	max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
356	EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
357	falcon_xmac_writel(efx, &reg, XM_RX_PARAM_REG_MAC);
358	EFX_POPULATE_DWORD_2(reg,
359	XM_MAX_TX_FRM_SIZE, max_frame_len,
360	XM_TX_JUMBO_MODE, 1);
361	falcon_xmac_writel(efx, &reg, XM_TX_PARAM_REG_MAC);
362
363	EFX_POPULATE_DWORD_2(reg,
364	XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
365	XM_DIS_FCNTL, rx_fc ? 0 : 1);
366	falcon_xmac_writel(efx, &reg, XM_FC_REG_MAC);
367
368	/* Set MAC address */
369	EFX_POPULATE_DWORD_4(reg,
370	XM_ADR_0, efx->net_dev->dev_addr[0],
371	XM_ADR_1, efx->net_dev->dev_addr[1],
372	XM_ADR_2, efx->net_dev->dev_addr[2],
373	XM_ADR_3, efx->net_dev->dev_addr[3]);
374	falcon_xmac_writel(efx, &reg, XM_ADR_LO_REG_MAC);
375	EFX_POPULATE_DWORD_2(reg,
376	XM_ADR_4, efx->net_dev->dev_addr[4],
377	XM_ADR_5, efx->net_dev->dev_addr[5]);
378	falcon_xmac_writel(efx, &reg, XM_ADR_HI_REG_MAC);
379	}
380
381	/* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
382	* to come back up. Bash it until it comes back up */
383	static int falcon_check_xaui_link_up(struct efx_nic *efx)
384	{
385	int max_tries, tries;
386	tries = EFX_WORKAROUND_5147(efx) ? 5 : 1;
387	max_tries = tries;
388
389	if (efx->phy_type == PHY_TYPE_NONE)
390	return 0;
391
392	while (tries) {
393	if (falcon_xaui_link_ok(efx))
394	return 1;
395
396	EFX_LOG(efx, "%s Clobbering XAUI (%d tries left).\n",
397	__func__, tries);
398	(void) falcon_reset_xaui(efx);
399	udelay(200);
400	tries--;
401	}
402
403	EFX_ERR(efx, "Failed to bring XAUI link back up in %d tries!\n",
404	max_tries);
405	return 0;
406	}
407
408	void falcon_reconfigure_xmac(struct efx_nic *efx)
409	{
410	int xaui_link_ok;
411
412	falcon_mask_status_intr(efx, 0);
413
414	falcon_deconfigure_mac_wrapper(efx);
415	efx->phy_op->reconfigure(efx);
416	falcon_reconfigure_xmac_core(efx);
417	falcon_reconfigure_mac_wrapper(efx);
418
419	/* Ensure XAUI link is up */
420	xaui_link_ok = falcon_check_xaui_link_up(efx);
421
422	if (xaui_link_ok && efx->link_up)
423	falcon_mask_status_intr(efx, 1);
424	}
425
426	void falcon_fini_xmac(struct efx_nic *efx)
427	{
428	/* Isolate the MAC - PHY */
429	falcon_deconfigure_mac_wrapper(efx);
430
431	/* Potentially power down the PHY */
432	efx->phy_op->fini(efx);
433	}
434
435	void falcon_update_stats_xmac(struct efx_nic *efx)
436	{
437	struct efx_mac_stats *mac_stats = &efx->mac_stats;
438	int rc;
439
440	rc = falcon_dma_stats(efx, XgDmaDone_offset);
441	if (rc)
442	return;
443
444	/* Update MAC stats from DMAed values */
445	FALCON_STAT(efx, XgRxOctets, rx_bytes);
446	FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
447	FALCON_STAT(efx, XgRxPkts, rx_packets);
448	FALCON_STAT(efx, XgRxPktsOK, rx_good);
449	FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
450	FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
451	FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
452	FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
453	FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
454	FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
455	FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
456	FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
457	FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
458	FALCON_STAT(efx, XgRxAlignError, rx_align_error);
459	FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
460	FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
461	FALCON_STAT(efx, XgRxControlPkts, rx_control);
462	FALCON_STAT(efx, XgRxPausePkts, rx_pause);
463	FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
464	FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
465	FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
466	FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
467	FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
468	FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
469	FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
470	FALCON_STAT(efx, XgRxLengthError, rx_length_error);
471	FALCON_STAT(efx, XgTxPkts, tx_packets);
472	FALCON_STAT(efx, XgTxOctets, tx_bytes);
473	FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
474	FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
475	FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
476	FALCON_STAT(efx, XgTxControlPkts, tx_control);
477	FALCON_STAT(efx, XgTxPausePkts, tx_pause);
478	FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
479	FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
480	FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
481	FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
482	FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
483	FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
484	FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
485	FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
486	FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
487	FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
488	FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
489	FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
490
491	/* Update derived statistics */
492	mac_stats->tx_good_bytes =
493	(mac_stats->tx_bytes - mac_stats->tx_bad_bytes);
494	mac_stats->rx_bad_bytes =
495	(mac_stats->rx_bytes - mac_stats->rx_good_bytes);
496	}
497
8ceee660 BH	498	int falcon_check_xmac(struct efx_nic *efx)
	499	{
	500	unsigned xaui_link_ok;
	501	int rc;
	502
	503	falcon_mask_status_intr(efx, 0);
	504	xaui_link_ok = falcon_xaui_link_ok(efx);
	505
	506	if (EFX_WORKAROUND_5147(efx) && !xaui_link_ok)
	507	(void) falcon_reset_xaui(efx);
	508
	509	/* Call the PHY check_hw routine */
	510	rc = efx->phy_op->check_hw(efx);
	511
	512	/* Unmask interrupt if everything was (and still is) ok */
	513	if (xaui_link_ok && efx->link_up)
	514	falcon_mask_status_intr(efx, 1);
	515
	516	return rc;
	517	}
	518
	519	/* Simulate a PHY event */
	520	void falcon_xmac_sim_phy_event(struct efx_nic *efx)
	521	{
	522	efx_qword_t phy_event;
	523
	524	EFX_POPULATE_QWORD_2(phy_event,
	525	EV_CODE, GLOBAL_EV_DECODE,
	526	XG_PHY_INTR, 1);
	527	falcon_generate_event(&efx->channel[0], &phy_event);
	528	}
	529
	530	int falcon_xmac_get_settings(struct efx_nic efx, struct ethtool_cmd ecmd)
	531	{
	532	mdio_clause45_get_settings(efx, ecmd);
	533	ecmd->transceiver = XCVR_INTERNAL;
	534	ecmd->phy_address = efx->mii.phy_id;
	535	ecmd->autoneg = AUTONEG_DISABLE;
	536	ecmd->duplex = DUPLEX_FULL;
	537	return 0;
	538	}
	539
	540	int falcon_xmac_set_settings(struct efx_nic efx, struct ethtool_cmd ecmd)
	541	{
	542	if (ecmd->transceiver != XCVR_INTERNAL)
	543	return -EINVAL;
	544	if (ecmd->autoneg != AUTONEG_DISABLE)
	545	return -EINVAL;
	546	if (ecmd->duplex != DUPLEX_FULL)
	547	return -EINVAL;
	548
	549	return mdio_clause45_set_settings(efx, ecmd);
	550	}
	551
	552
	553	int falcon_xmac_set_pause(struct efx_nic *efx, enum efx_fc_type flow_control)
	554	{
	555	int reset;
	556
	557	if (flow_control & EFX_FC_AUTO) {
	558	EFX_LOG(efx, "10G does not support flow control "
	559	"autonegotiation\n");
	560	return -EINVAL;
	561	}
562
563	if ((flow_control & EFX_FC_TX) && !(flow_control & EFX_FC_RX))
564	return -EINVAL;
565
566	/* TX flow control may automatically turn itself off if the
567	* link partner (intermittently) stops responding to pause
568	* frames. There isn't any indication that this has happened,
569	* so the best we do is leave it up to the user to spot this
570	* and fix it be cycling transmit flow control on this end. */
571	reset = ((flow_control & EFX_FC_TX) &&
572	!(efx->flow_control & EFX_FC_TX));
573	if (EFX_WORKAROUND_11482(efx) && reset) {
574	if (FALCON_REV(efx) >= FALCON_REV_B0) {
575	/* Recover by resetting the EM block */
576	if (efx->link_up)
577	falcon_drain_tx_fifo(efx);
578	} else {
579	/* Schedule a reset to recover */
580	efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
581	}
582	}
583
584	efx->flow_control = flow_control;
585
586	return 0;
587	}