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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2006-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #ifndef EFX_FALCON_HWDEFS_H | |
12 | #define EFX_FALCON_HWDEFS_H | |
13 | ||
14 | /* | |
15 | * Falcon hardware value definitions. | |
16 | * Falcon is the internal codename for the SFC4000 controller that is | |
17 | * present in SFE400X evaluation boards | |
18 | */ | |
19 | ||
20 | /************************************************************************** | |
21 | * | |
22 | * Falcon registers | |
23 | * | |
24 | ************************************************************************** | |
25 | */ | |
26 | ||
27 | /* Address region register */ | |
28 | #define ADR_REGION_REG_KER 0x00 | |
29 | #define ADR_REGION0_LBN 0 | |
30 | #define ADR_REGION0_WIDTH 18 | |
31 | #define ADR_REGION1_LBN 32 | |
32 | #define ADR_REGION1_WIDTH 18 | |
33 | #define ADR_REGION2_LBN 64 | |
34 | #define ADR_REGION2_WIDTH 18 | |
35 | #define ADR_REGION3_LBN 96 | |
36 | #define ADR_REGION3_WIDTH 18 | |
37 | ||
38 | /* Interrupt enable register */ | |
39 | #define INT_EN_REG_KER 0x0010 | |
40 | #define KER_INT_KER_LBN 3 | |
41 | #define KER_INT_KER_WIDTH 1 | |
42 | #define DRV_INT_EN_KER_LBN 0 | |
43 | #define DRV_INT_EN_KER_WIDTH 1 | |
44 | ||
45 | /* Interrupt status address register */ | |
46 | #define INT_ADR_REG_KER 0x0030 | |
47 | #define NORM_INT_VEC_DIS_KER_LBN 64 | |
48 | #define NORM_INT_VEC_DIS_KER_WIDTH 1 | |
49 | #define INT_ADR_KER_LBN 0 | |
50 | #define INT_ADR_KER_WIDTH EFX_DMA_TYPE_WIDTH(64) /* not 46 for this one */ | |
51 | ||
52 | /* Interrupt status register (B0 only) */ | |
53 | #define INT_ISR0_B0 0x90 | |
54 | #define INT_ISR1_B0 0xA0 | |
55 | ||
56 | /* Interrupt acknowledge register (A0/A1 only) */ | |
57 | #define INT_ACK_REG_KER_A1 0x0050 | |
58 | #define INT_ACK_DUMMY_DATA_LBN 0 | |
59 | #define INT_ACK_DUMMY_DATA_WIDTH 32 | |
60 | ||
61 | /* Interrupt acknowledge work-around register (A0/A1 only )*/ | |
62 | #define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 0x0070 | |
63 | ||
64 | /* SPI host command register */ | |
65 | #define EE_SPI_HCMD_REG_KER 0x0100 | |
66 | #define EE_SPI_HCMD_CMD_EN_LBN 31 | |
67 | #define EE_SPI_HCMD_CMD_EN_WIDTH 1 | |
68 | #define EE_WR_TIMER_ACTIVE_LBN 28 | |
69 | #define EE_WR_TIMER_ACTIVE_WIDTH 1 | |
70 | #define EE_SPI_HCMD_SF_SEL_LBN 24 | |
71 | #define EE_SPI_HCMD_SF_SEL_WIDTH 1 | |
72 | #define EE_SPI_EEPROM 0 | |
73 | #define EE_SPI_FLASH 1 | |
74 | #define EE_SPI_HCMD_DABCNT_LBN 16 | |
75 | #define EE_SPI_HCMD_DABCNT_WIDTH 5 | |
76 | #define EE_SPI_HCMD_READ_LBN 15 | |
77 | #define EE_SPI_HCMD_READ_WIDTH 1 | |
78 | #define EE_SPI_READ 1 | |
79 | #define EE_SPI_WRITE 0 | |
80 | #define EE_SPI_HCMD_DUBCNT_LBN 12 | |
81 | #define EE_SPI_HCMD_DUBCNT_WIDTH 2 | |
82 | #define EE_SPI_HCMD_ADBCNT_LBN 8 | |
83 | #define EE_SPI_HCMD_ADBCNT_WIDTH 2 | |
84 | #define EE_SPI_HCMD_ENC_LBN 0 | |
85 | #define EE_SPI_HCMD_ENC_WIDTH 8 | |
86 | ||
87 | /* SPI host address register */ | |
88 | #define EE_SPI_HADR_REG_KER 0x0110 | |
89 | #define EE_SPI_HADR_ADR_LBN 0 | |
90 | #define EE_SPI_HADR_ADR_WIDTH 24 | |
91 | ||
92 | /* SPI host data register */ | |
93 | #define EE_SPI_HDATA_REG_KER 0x0120 | |
94 | ||
4a5b504d BH |
95 | /* SPI/VPD config register */ |
96 | #define EE_VPD_CFG_REG_KER 0x0140 | |
97 | #define EE_VPD_EN_LBN 0 | |
98 | #define EE_VPD_EN_WIDTH 1 | |
99 | #define EE_VPD_EN_AD9_MODE_LBN 1 | |
100 | #define EE_VPD_EN_AD9_MODE_WIDTH 1 | |
101 | #define EE_EE_CLOCK_DIV_LBN 112 | |
102 | #define EE_EE_CLOCK_DIV_WIDTH 7 | |
103 | #define EE_SF_CLOCK_DIV_LBN 120 | |
104 | #define EE_SF_CLOCK_DIV_WIDTH 7 | |
105 | ||
8ceee660 BH |
106 | /* PCIE CORE ACCESS REG */ |
107 | #define PCIE_CORE_ADDR_PCIE_DEVICE_CTRL_STAT 0x68 | |
108 | #define PCIE_CORE_ADDR_PCIE_LINK_CTRL_STAT 0x70 | |
109 | #define PCIE_CORE_ADDR_ACK_RPL_TIMER 0x700 | |
110 | #define PCIE_CORE_ADDR_ACK_FREQ 0x70C | |
111 | ||
112 | /* NIC status register */ | |
113 | #define NIC_STAT_REG 0x0200 | |
177dfcd8 BH |
114 | #define EE_STRAP_EN_LBN 31 |
115 | #define EE_STRAP_EN_WIDTH 1 | |
116 | #define EE_STRAP_OVR_LBN 24 | |
117 | #define EE_STRAP_OVR_WIDTH 4 | |
8ceee660 BH |
118 | #define ONCHIP_SRAM_LBN 16 |
119 | #define ONCHIP_SRAM_WIDTH 1 | |
120 | #define SF_PRST_LBN 9 | |
121 | #define SF_PRST_WIDTH 1 | |
122 | #define EE_PRST_LBN 8 | |
123 | #define EE_PRST_WIDTH 1 | |
177dfcd8 BH |
124 | #define STRAP_PINS_LBN 0 |
125 | #define STRAP_PINS_WIDTH 3 | |
8ceee660 BH |
126 | /* These bit definitions are extrapolated from the list of numerical |
127 | * values for STRAP_PINS. | |
128 | */ | |
129 | #define STRAP_10G_LBN 2 | |
130 | #define STRAP_10G_WIDTH 1 | |
131 | #define STRAP_PCIE_LBN 0 | |
132 | #define STRAP_PCIE_WIDTH 1 | |
133 | ||
4a5b504d BH |
134 | #define BOOTED_USING_NVDEVICE_LBN 3 |
135 | #define BOOTED_USING_NVDEVICE_WIDTH 1 | |
136 | ||
8ceee660 BH |
137 | /* GPIO control register */ |
138 | #define GPIO_CTL_REG_KER 0x0210 | |
6f158d5f BH |
139 | #define GPIO_USE_NIC_CLK_LBN (30) |
140 | #define GPIO_USE_NIC_CLK_WIDTH (1) | |
8ceee660 BH |
141 | #define GPIO_OUTPUTS_LBN (16) |
142 | #define GPIO_OUTPUTS_WIDTH (4) | |
143 | #define GPIO_INPUTS_LBN (8) | |
144 | #define GPIO_DIRECTION_LBN (24) | |
145 | #define GPIO_DIRECTION_WIDTH (4) | |
146 | #define GPIO_DIRECTION_OUT (1) | |
147 | #define GPIO_SRAM_SLEEP (1 << 1) | |
148 | ||
149 | #define GPIO3_OEN_LBN (GPIO_DIRECTION_LBN + 3) | |
150 | #define GPIO3_OEN_WIDTH 1 | |
151 | #define GPIO2_OEN_LBN (GPIO_DIRECTION_LBN + 2) | |
152 | #define GPIO2_OEN_WIDTH 1 | |
153 | #define GPIO1_OEN_LBN (GPIO_DIRECTION_LBN + 1) | |
154 | #define GPIO1_OEN_WIDTH 1 | |
155 | #define GPIO0_OEN_LBN (GPIO_DIRECTION_LBN + 0) | |
156 | #define GPIO0_OEN_WIDTH 1 | |
157 | ||
158 | #define GPIO3_OUT_LBN (GPIO_OUTPUTS_LBN + 3) | |
159 | #define GPIO3_OUT_WIDTH 1 | |
160 | #define GPIO2_OUT_LBN (GPIO_OUTPUTS_LBN + 2) | |
161 | #define GPIO2_OUT_WIDTH 1 | |
162 | #define GPIO1_OUT_LBN (GPIO_OUTPUTS_LBN + 1) | |
163 | #define GPIO1_OUT_WIDTH 1 | |
164 | #define GPIO0_OUT_LBN (GPIO_OUTPUTS_LBN + 0) | |
165 | #define GPIO0_OUT_WIDTH 1 | |
166 | ||
167 | #define GPIO3_IN_LBN (GPIO_INPUTS_LBN + 3) | |
168 | #define GPIO3_IN_WIDTH 1 | |
169 | #define GPIO2_IN_WIDTH 1 | |
170 | #define GPIO1_IN_WIDTH 1 | |
171 | #define GPIO0_IN_LBN (GPIO_INPUTS_LBN + 0) | |
172 | #define GPIO0_IN_WIDTH 1 | |
173 | ||
174 | /* Global control register */ | |
175 | #define GLB_CTL_REG_KER 0x0220 | |
176 | #define EXT_PHY_RST_CTL_LBN 63 | |
177 | #define EXT_PHY_RST_CTL_WIDTH 1 | |
178 | #define PCIE_SD_RST_CTL_LBN 61 | |
179 | #define PCIE_SD_RST_CTL_WIDTH 1 | |
180 | ||
181 | #define PCIE_NSTCK_RST_CTL_LBN 58 | |
182 | #define PCIE_NSTCK_RST_CTL_WIDTH 1 | |
183 | #define PCIE_CORE_RST_CTL_LBN 57 | |
184 | #define PCIE_CORE_RST_CTL_WIDTH 1 | |
185 | #define EE_RST_CTL_LBN 49 | |
186 | #define EE_RST_CTL_WIDTH 1 | |
187 | #define RST_XGRX_LBN 24 | |
188 | #define RST_XGRX_WIDTH 1 | |
189 | #define RST_XGTX_LBN 23 | |
190 | #define RST_XGTX_WIDTH 1 | |
191 | #define RST_EM_LBN 22 | |
192 | #define RST_EM_WIDTH 1 | |
193 | #define EXT_PHY_RST_DUR_LBN 1 | |
194 | #define EXT_PHY_RST_DUR_WIDTH 3 | |
195 | #define SWRST_LBN 0 | |
196 | #define SWRST_WIDTH 1 | |
197 | #define INCLUDE_IN_RESET 0 | |
198 | #define EXCLUDE_FROM_RESET 1 | |
199 | ||
200 | /* Fatal interrupt register */ | |
201 | #define FATAL_INTR_REG_KER 0x0230 | |
202 | #define RBUF_OWN_INT_KER_EN_LBN 39 | |
203 | #define RBUF_OWN_INT_KER_EN_WIDTH 1 | |
204 | #define TBUF_OWN_INT_KER_EN_LBN 38 | |
205 | #define TBUF_OWN_INT_KER_EN_WIDTH 1 | |
206 | #define ILL_ADR_INT_KER_EN_LBN 33 | |
207 | #define ILL_ADR_INT_KER_EN_WIDTH 1 | |
208 | #define MEM_PERR_INT_KER_LBN 8 | |
209 | #define MEM_PERR_INT_KER_WIDTH 1 | |
210 | #define INT_KER_ERROR_LBN 0 | |
211 | #define INT_KER_ERROR_WIDTH 12 | |
212 | ||
213 | #define DP_CTRL_REG 0x250 | |
214 | #define FLS_EVQ_ID_LBN 0 | |
215 | #define FLS_EVQ_ID_WIDTH 11 | |
216 | ||
217 | #define MEM_STAT_REG_KER 0x260 | |
218 | ||
219 | /* Debug probe register */ | |
220 | #define DEBUG_BLK_SEL_MISC 7 | |
221 | #define DEBUG_BLK_SEL_SERDES 6 | |
222 | #define DEBUG_BLK_SEL_EM 5 | |
223 | #define DEBUG_BLK_SEL_SR 4 | |
224 | #define DEBUG_BLK_SEL_EV 3 | |
225 | #define DEBUG_BLK_SEL_RX 2 | |
226 | #define DEBUG_BLK_SEL_TX 1 | |
227 | #define DEBUG_BLK_SEL_BIU 0 | |
228 | ||
229 | /* FPGA build version */ | |
230 | #define ALTERA_BUILD_REG_KER 0x0300 | |
231 | #define VER_ALL_LBN 0 | |
232 | #define VER_ALL_WIDTH 32 | |
233 | ||
234 | /* Spare EEPROM bits register (flash 0x390) */ | |
235 | #define SPARE_REG_KER 0x310 | |
236 | #define MEM_PERR_EN_TX_DATA_LBN 72 | |
237 | #define MEM_PERR_EN_TX_DATA_WIDTH 2 | |
238 | ||
239 | /* Timer table for kernel access */ | |
240 | #define TIMER_CMD_REG_KER 0x420 | |
241 | #define TIMER_MODE_LBN 12 | |
242 | #define TIMER_MODE_WIDTH 2 | |
243 | #define TIMER_MODE_DIS 0 | |
244 | #define TIMER_MODE_INT_HLDOFF 2 | |
245 | #define TIMER_VAL_LBN 0 | |
246 | #define TIMER_VAL_WIDTH 12 | |
247 | ||
248 | /* Driver generated event register */ | |
249 | #define DRV_EV_REG_KER 0x440 | |
250 | #define DRV_EV_QID_LBN 64 | |
251 | #define DRV_EV_QID_WIDTH 12 | |
252 | #define DRV_EV_DATA_LBN 0 | |
253 | #define DRV_EV_DATA_WIDTH 64 | |
254 | ||
255 | /* Buffer table configuration register */ | |
256 | #define BUF_TBL_CFG_REG_KER 0x600 | |
257 | #define BUF_TBL_MODE_LBN 3 | |
258 | #define BUF_TBL_MODE_WIDTH 1 | |
259 | #define BUF_TBL_MODE_HALF 0 | |
260 | #define BUF_TBL_MODE_FULL 1 | |
261 | ||
262 | /* SRAM receive descriptor cache configuration register */ | |
263 | #define SRM_RX_DC_CFG_REG_KER 0x610 | |
264 | #define SRM_RX_DC_BASE_ADR_LBN 0 | |
265 | #define SRM_RX_DC_BASE_ADR_WIDTH 21 | |
266 | ||
267 | /* SRAM transmit descriptor cache configuration register */ | |
268 | #define SRM_TX_DC_CFG_REG_KER 0x620 | |
269 | #define SRM_TX_DC_BASE_ADR_LBN 0 | |
270 | #define SRM_TX_DC_BASE_ADR_WIDTH 21 | |
271 | ||
272 | /* SRAM configuration register */ | |
273 | #define SRM_CFG_REG_KER 0x630 | |
274 | #define SRAM_OOB_BT_INIT_EN_LBN 3 | |
275 | #define SRAM_OOB_BT_INIT_EN_WIDTH 1 | |
276 | #define SRM_NUM_BANKS_AND_BANK_SIZE_LBN 0 | |
277 | #define SRM_NUM_BANKS_AND_BANK_SIZE_WIDTH 3 | |
278 | #define SRM_NB_BSZ_1BANKS_2M 0 | |
279 | #define SRM_NB_BSZ_1BANKS_4M 1 | |
280 | #define SRM_NB_BSZ_1BANKS_8M 2 | |
281 | #define SRM_NB_BSZ_DEFAULT 3 /* char driver will set the default */ | |
282 | #define SRM_NB_BSZ_2BANKS_4M 4 | |
283 | #define SRM_NB_BSZ_2BANKS_8M 5 | |
284 | #define SRM_NB_BSZ_2BANKS_16M 6 | |
285 | #define SRM_NB_BSZ_RESERVED 7 | |
286 | ||
287 | /* Special buffer table update register */ | |
288 | #define BUF_TBL_UPD_REG_KER 0x0650 | |
289 | #define BUF_UPD_CMD_LBN 63 | |
290 | #define BUF_UPD_CMD_WIDTH 1 | |
291 | #define BUF_CLR_CMD_LBN 62 | |
292 | #define BUF_CLR_CMD_WIDTH 1 | |
293 | #define BUF_CLR_END_ID_LBN 32 | |
294 | #define BUF_CLR_END_ID_WIDTH 20 | |
295 | #define BUF_CLR_START_ID_LBN 0 | |
296 | #define BUF_CLR_START_ID_WIDTH 20 | |
297 | ||
298 | /* Receive configuration register */ | |
299 | #define RX_CFG_REG_KER 0x800 | |
300 | ||
301 | /* B0 */ | |
302 | #define RX_INGR_EN_B0_LBN 47 | |
303 | #define RX_INGR_EN_B0_WIDTH 1 | |
304 | #define RX_DESC_PUSH_EN_B0_LBN 43 | |
305 | #define RX_DESC_PUSH_EN_B0_WIDTH 1 | |
306 | #define RX_XON_TX_TH_B0_LBN 33 | |
307 | #define RX_XON_TX_TH_B0_WIDTH 5 | |
308 | #define RX_XOFF_TX_TH_B0_LBN 28 | |
309 | #define RX_XOFF_TX_TH_B0_WIDTH 5 | |
310 | #define RX_USR_BUF_SIZE_B0_LBN 19 | |
311 | #define RX_USR_BUF_SIZE_B0_WIDTH 9 | |
312 | #define RX_XON_MAC_TH_B0_LBN 10 | |
313 | #define RX_XON_MAC_TH_B0_WIDTH 9 | |
314 | #define RX_XOFF_MAC_TH_B0_LBN 1 | |
315 | #define RX_XOFF_MAC_TH_B0_WIDTH 9 | |
316 | #define RX_XOFF_MAC_EN_B0_LBN 0 | |
317 | #define RX_XOFF_MAC_EN_B0_WIDTH 1 | |
318 | ||
319 | /* A1 */ | |
320 | #define RX_DESC_PUSH_EN_A1_LBN 35 | |
321 | #define RX_DESC_PUSH_EN_A1_WIDTH 1 | |
322 | #define RX_XON_TX_TH_A1_LBN 25 | |
323 | #define RX_XON_TX_TH_A1_WIDTH 5 | |
324 | #define RX_XOFF_TX_TH_A1_LBN 20 | |
325 | #define RX_XOFF_TX_TH_A1_WIDTH 5 | |
326 | #define RX_USR_BUF_SIZE_A1_LBN 11 | |
327 | #define RX_USR_BUF_SIZE_A1_WIDTH 9 | |
328 | #define RX_XON_MAC_TH_A1_LBN 6 | |
329 | #define RX_XON_MAC_TH_A1_WIDTH 5 | |
330 | #define RX_XOFF_MAC_TH_A1_LBN 1 | |
331 | #define RX_XOFF_MAC_TH_A1_WIDTH 5 | |
332 | #define RX_XOFF_MAC_EN_A1_LBN 0 | |
333 | #define RX_XOFF_MAC_EN_A1_WIDTH 1 | |
334 | ||
335 | /* Receive filter control register */ | |
336 | #define RX_FILTER_CTL_REG 0x810 | |
337 | #define UDP_FULL_SRCH_LIMIT_LBN 32 | |
338 | #define UDP_FULL_SRCH_LIMIT_WIDTH 8 | |
339 | #define NUM_KER_LBN 24 | |
340 | #define NUM_KER_WIDTH 2 | |
341 | #define UDP_WILD_SRCH_LIMIT_LBN 16 | |
342 | #define UDP_WILD_SRCH_LIMIT_WIDTH 8 | |
343 | #define TCP_WILD_SRCH_LIMIT_LBN 8 | |
344 | #define TCP_WILD_SRCH_LIMIT_WIDTH 8 | |
345 | #define TCP_FULL_SRCH_LIMIT_LBN 0 | |
346 | #define TCP_FULL_SRCH_LIMIT_WIDTH 8 | |
347 | ||
348 | /* RX queue flush register */ | |
349 | #define RX_FLUSH_DESCQ_REG_KER 0x0820 | |
350 | #define RX_FLUSH_DESCQ_CMD_LBN 24 | |
351 | #define RX_FLUSH_DESCQ_CMD_WIDTH 1 | |
352 | #define RX_FLUSH_DESCQ_LBN 0 | |
353 | #define RX_FLUSH_DESCQ_WIDTH 12 | |
354 | ||
355 | /* Receive descriptor update register */ | |
356 | #define RX_DESC_UPD_REG_KER_DWORD (0x830 + 12) | |
357 | #define RX_DESC_WPTR_DWORD_LBN 0 | |
358 | #define RX_DESC_WPTR_DWORD_WIDTH 12 | |
359 | ||
360 | /* Receive descriptor cache configuration register */ | |
361 | #define RX_DC_CFG_REG_KER 0x840 | |
362 | #define RX_DC_SIZE_LBN 0 | |
363 | #define RX_DC_SIZE_WIDTH 2 | |
364 | ||
365 | #define RX_DC_PF_WM_REG_KER 0x850 | |
366 | #define RX_DC_PF_LWM_LBN 0 | |
367 | #define RX_DC_PF_LWM_WIDTH 6 | |
368 | ||
369 | /* RX no descriptor drop counter */ | |
370 | #define RX_NODESC_DROP_REG_KER 0x880 | |
371 | #define RX_NODESC_DROP_CNT_LBN 0 | |
372 | #define RX_NODESC_DROP_CNT_WIDTH 16 | |
373 | ||
374 | /* RX black magic register */ | |
375 | #define RX_SELF_RST_REG_KER 0x890 | |
376 | #define RX_ISCSI_DIS_LBN 17 | |
377 | #define RX_ISCSI_DIS_WIDTH 1 | |
378 | #define RX_NODESC_WAIT_DIS_LBN 9 | |
379 | #define RX_NODESC_WAIT_DIS_WIDTH 1 | |
380 | #define RX_RECOVERY_EN_LBN 8 | |
381 | #define RX_RECOVERY_EN_WIDTH 1 | |
382 | ||
383 | /* TX queue flush register */ | |
384 | #define TX_FLUSH_DESCQ_REG_KER 0x0a00 | |
385 | #define TX_FLUSH_DESCQ_CMD_LBN 12 | |
386 | #define TX_FLUSH_DESCQ_CMD_WIDTH 1 | |
387 | #define TX_FLUSH_DESCQ_LBN 0 | |
388 | #define TX_FLUSH_DESCQ_WIDTH 12 | |
389 | ||
390 | /* Transmit descriptor update register */ | |
391 | #define TX_DESC_UPD_REG_KER_DWORD (0xa10 + 12) | |
392 | #define TX_DESC_WPTR_DWORD_LBN 0 | |
393 | #define TX_DESC_WPTR_DWORD_WIDTH 12 | |
394 | ||
395 | /* Transmit descriptor cache configuration register */ | |
396 | #define TX_DC_CFG_REG_KER 0xa20 | |
397 | #define TX_DC_SIZE_LBN 0 | |
398 | #define TX_DC_SIZE_WIDTH 2 | |
399 | ||
400 | /* Transmit checksum configuration register (A0/A1 only) */ | |
401 | #define TX_CHKSM_CFG_REG_KER_A1 0xa30 | |
402 | ||
403 | /* Transmit configuration register */ | |
404 | #define TX_CFG_REG_KER 0xa50 | |
405 | #define TX_NO_EOP_DISC_EN_LBN 5 | |
406 | #define TX_NO_EOP_DISC_EN_WIDTH 1 | |
407 | ||
408 | /* Transmit configuration register 2 */ | |
409 | #define TX_CFG2_REG_KER 0xa80 | |
410 | #define TX_CSR_PUSH_EN_LBN 89 | |
411 | #define TX_CSR_PUSH_EN_WIDTH 1 | |
412 | #define TX_RX_SPACER_LBN 64 | |
413 | #define TX_RX_SPACER_WIDTH 8 | |
414 | #define TX_SW_EV_EN_LBN 59 | |
415 | #define TX_SW_EV_EN_WIDTH 1 | |
416 | #define TX_RX_SPACER_EN_LBN 57 | |
417 | #define TX_RX_SPACER_EN_WIDTH 1 | |
418 | #define TX_PREF_THRESHOLD_LBN 19 | |
419 | #define TX_PREF_THRESHOLD_WIDTH 2 | |
420 | #define TX_ONE_PKT_PER_Q_LBN 18 | |
421 | #define TX_ONE_PKT_PER_Q_WIDTH 1 | |
422 | #define TX_DIS_NON_IP_EV_LBN 17 | |
423 | #define TX_DIS_NON_IP_EV_WIDTH 1 | |
424 | #define TX_FLUSH_MIN_LEN_EN_B0_LBN 7 | |
425 | #define TX_FLUSH_MIN_LEN_EN_B0_WIDTH 1 | |
426 | ||
427 | /* PHY management transmit data register */ | |
428 | #define MD_TXD_REG_KER 0xc00 | |
429 | #define MD_TXD_LBN 0 | |
430 | #define MD_TXD_WIDTH 16 | |
431 | ||
432 | /* PHY management receive data register */ | |
433 | #define MD_RXD_REG_KER 0xc10 | |
434 | #define MD_RXD_LBN 0 | |
435 | #define MD_RXD_WIDTH 16 | |
436 | ||
437 | /* PHY management configuration & status register */ | |
438 | #define MD_CS_REG_KER 0xc20 | |
439 | #define MD_GC_LBN 4 | |
440 | #define MD_GC_WIDTH 1 | |
441 | #define MD_RIC_LBN 2 | |
442 | #define MD_RIC_WIDTH 1 | |
443 | #define MD_RDC_LBN 1 | |
444 | #define MD_RDC_WIDTH 1 | |
445 | #define MD_WRC_LBN 0 | |
446 | #define MD_WRC_WIDTH 1 | |
447 | ||
448 | /* PHY management PHY address register */ | |
449 | #define MD_PHY_ADR_REG_KER 0xc30 | |
450 | #define MD_PHY_ADR_LBN 0 | |
451 | #define MD_PHY_ADR_WIDTH 16 | |
452 | ||
453 | /* PHY management ID register */ | |
454 | #define MD_ID_REG_KER 0xc40 | |
455 | #define MD_PRT_ADR_LBN 11 | |
456 | #define MD_PRT_ADR_WIDTH 5 | |
457 | #define MD_DEV_ADR_LBN 6 | |
458 | #define MD_DEV_ADR_WIDTH 5 | |
8ceee660 BH |
459 | |
460 | /* PHY management status & mask register (DWORD read only) */ | |
461 | #define MD_STAT_REG_KER 0xc50 | |
462 | #define MD_BSERR_LBN 2 | |
463 | #define MD_BSERR_WIDTH 1 | |
464 | #define MD_LNFL_LBN 1 | |
465 | #define MD_LNFL_WIDTH 1 | |
466 | #define MD_BSY_LBN 0 | |
467 | #define MD_BSY_WIDTH 1 | |
468 | ||
469 | /* Port 0 and 1 MAC stats registers */ | |
470 | #define MAC0_STAT_DMA_REG_KER 0xc60 | |
471 | #define MAC_STAT_DMA_CMD_LBN 48 | |
472 | #define MAC_STAT_DMA_CMD_WIDTH 1 | |
473 | #define MAC_STAT_DMA_ADR_LBN 0 | |
474 | #define MAC_STAT_DMA_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46) | |
475 | ||
476 | /* Port 0 and 1 MAC control registers */ | |
477 | #define MAC0_CTRL_REG_KER 0xc80 | |
478 | #define MAC_XOFF_VAL_LBN 16 | |
479 | #define MAC_XOFF_VAL_WIDTH 16 | |
480 | #define TXFIFO_DRAIN_EN_B0_LBN 7 | |
481 | #define TXFIFO_DRAIN_EN_B0_WIDTH 1 | |
482 | #define MAC_BCAD_ACPT_LBN 4 | |
483 | #define MAC_BCAD_ACPT_WIDTH 1 | |
484 | #define MAC_UC_PROM_LBN 3 | |
485 | #define MAC_UC_PROM_WIDTH 1 | |
486 | #define MAC_LINK_STATUS_LBN 2 | |
487 | #define MAC_LINK_STATUS_WIDTH 1 | |
488 | #define MAC_SPEED_LBN 0 | |
489 | #define MAC_SPEED_WIDTH 2 | |
490 | ||
491 | /* 10G XAUI XGXS default values */ | |
492 | #define XX_TXDRV_DEQ_DEFAULT 0xe /* deq=.6 */ | |
493 | #define XX_TXDRV_DTX_DEFAULT 0x5 /* 1.25 */ | |
494 | #define XX_SD_CTL_DRV_DEFAULT 0 /* 20mA */ | |
495 | ||
496 | /* Multicast address hash table */ | |
497 | #define MAC_MCAST_HASH_REG0_KER 0xca0 | |
498 | #define MAC_MCAST_HASH_REG1_KER 0xcb0 | |
499 | ||
177dfcd8 BH |
500 | /* GMAC configuration register 1 */ |
501 | #define GM_CFG1_REG 0xe00 | |
502 | #define GM_SW_RST_LBN 31 | |
503 | #define GM_SW_RST_WIDTH 1 | |
504 | #define GM_LOOP_LBN 8 | |
505 | #define GM_LOOP_WIDTH 1 | |
506 | #define GM_RX_FC_EN_LBN 5 | |
507 | #define GM_RX_FC_EN_WIDTH 1 | |
508 | #define GM_TX_FC_EN_LBN 4 | |
509 | #define GM_TX_FC_EN_WIDTH 1 | |
510 | #define GM_RX_EN_LBN 2 | |
511 | #define GM_RX_EN_WIDTH 1 | |
512 | #define GM_TX_EN_LBN 0 | |
513 | #define GM_TX_EN_WIDTH 1 | |
514 | ||
515 | /* GMAC configuration register 2 */ | |
516 | #define GM_CFG2_REG 0xe10 | |
517 | #define GM_PAMBL_LEN_LBN 12 | |
518 | #define GM_PAMBL_LEN_WIDTH 4 | |
519 | #define GM_IF_MODE_LBN 8 | |
520 | #define GM_IF_MODE_WIDTH 2 | |
521 | #define GM_LEN_CHK_LBN 4 | |
522 | #define GM_LEN_CHK_WIDTH 1 | |
523 | #define GM_PAD_CRC_EN_LBN 2 | |
524 | #define GM_PAD_CRC_EN_WIDTH 1 | |
525 | #define GM_FD_LBN 0 | |
526 | #define GM_FD_WIDTH 1 | |
527 | ||
528 | /* GMAC maximum frame length register */ | |
529 | #define GM_MAX_FLEN_REG 0xe40 | |
530 | #define GM_MAX_FLEN_LBN 0 | |
531 | #define GM_MAX_FLEN_WIDTH 16 | |
532 | ||
533 | /* GMAC station address register 1 */ | |
534 | #define GM_ADR1_REG 0xf00 | |
535 | #define GM_HWADDR_5_LBN 24 | |
536 | #define GM_HWADDR_5_WIDTH 8 | |
537 | #define GM_HWADDR_4_LBN 16 | |
538 | #define GM_HWADDR_4_WIDTH 8 | |
539 | #define GM_HWADDR_3_LBN 8 | |
540 | #define GM_HWADDR_3_WIDTH 8 | |
541 | #define GM_HWADDR_2_LBN 0 | |
542 | #define GM_HWADDR_2_WIDTH 8 | |
543 | ||
544 | /* GMAC station address register 2 */ | |
545 | #define GM_ADR2_REG 0xf10 | |
546 | #define GM_HWADDR_1_LBN 24 | |
547 | #define GM_HWADDR_1_WIDTH 8 | |
548 | #define GM_HWADDR_0_LBN 16 | |
549 | #define GM_HWADDR_0_WIDTH 8 | |
550 | ||
551 | /* GMAC FIFO configuration register 0 */ | |
552 | #define GMF_CFG0_REG 0xf20 | |
553 | #define GMF_FTFENREQ_LBN 12 | |
554 | #define GMF_FTFENREQ_WIDTH 1 | |
555 | #define GMF_STFENREQ_LBN 11 | |
556 | #define GMF_STFENREQ_WIDTH 1 | |
557 | #define GMF_FRFENREQ_LBN 10 | |
558 | #define GMF_FRFENREQ_WIDTH 1 | |
559 | #define GMF_SRFENREQ_LBN 9 | |
560 | #define GMF_SRFENREQ_WIDTH 1 | |
561 | #define GMF_WTMENREQ_LBN 8 | |
562 | #define GMF_WTMENREQ_WIDTH 1 | |
563 | ||
564 | /* GMAC FIFO configuration register 1 */ | |
565 | #define GMF_CFG1_REG 0xf30 | |
566 | #define GMF_CFGFRTH_LBN 16 | |
567 | #define GMF_CFGFRTH_WIDTH 5 | |
568 | #define GMF_CFGXOFFRTX_LBN 0 | |
569 | #define GMF_CFGXOFFRTX_WIDTH 16 | |
570 | ||
571 | /* GMAC FIFO configuration register 2 */ | |
572 | #define GMF_CFG2_REG 0xf40 | |
573 | #define GMF_CFGHWM_LBN 16 | |
574 | #define GMF_CFGHWM_WIDTH 6 | |
575 | #define GMF_CFGLWM_LBN 0 | |
576 | #define GMF_CFGLWM_WIDTH 6 | |
577 | ||
578 | /* GMAC FIFO configuration register 3 */ | |
579 | #define GMF_CFG3_REG 0xf50 | |
580 | #define GMF_CFGHWMFT_LBN 16 | |
581 | #define GMF_CFGHWMFT_WIDTH 6 | |
582 | #define GMF_CFGFTTH_LBN 0 | |
583 | #define GMF_CFGFTTH_WIDTH 6 | |
584 | ||
585 | /* GMAC FIFO configuration register 4 */ | |
586 | #define GMF_CFG4_REG 0xf60 | |
587 | #define GMF_HSTFLTRFRM_PAUSE_LBN 12 | |
588 | #define GMF_HSTFLTRFRM_PAUSE_WIDTH 12 | |
589 | ||
590 | /* GMAC FIFO configuration register 5 */ | |
591 | #define GMF_CFG5_REG 0xf70 | |
592 | #define GMF_CFGHDPLX_LBN 22 | |
593 | #define GMF_CFGHDPLX_WIDTH 1 | |
594 | #define GMF_CFGBYTMODE_LBN 19 | |
595 | #define GMF_CFGBYTMODE_WIDTH 1 | |
596 | #define GMF_HSTDRPLT64_LBN 18 | |
597 | #define GMF_HSTDRPLT64_WIDTH 1 | |
598 | #define GMF_HSTFLTRFRMDC_PAUSE_LBN 12 | |
599 | #define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1 | |
600 | ||
8ceee660 | 601 | /* XGMAC address register low */ |
c1e5fcc9 | 602 | #define XM_ADR_LO_REG 0x1200 |
8ceee660 BH |
603 | #define XM_ADR_3_LBN 24 |
604 | #define XM_ADR_3_WIDTH 8 | |
605 | #define XM_ADR_2_LBN 16 | |
606 | #define XM_ADR_2_WIDTH 8 | |
607 | #define XM_ADR_1_LBN 8 | |
608 | #define XM_ADR_1_WIDTH 8 | |
609 | #define XM_ADR_0_LBN 0 | |
610 | #define XM_ADR_0_WIDTH 8 | |
611 | ||
612 | /* XGMAC address register high */ | |
c1e5fcc9 | 613 | #define XM_ADR_HI_REG 0x1210 |
8ceee660 BH |
614 | #define XM_ADR_5_LBN 8 |
615 | #define XM_ADR_5_WIDTH 8 | |
616 | #define XM_ADR_4_LBN 0 | |
617 | #define XM_ADR_4_WIDTH 8 | |
618 | ||
619 | /* XGMAC global configuration */ | |
c1e5fcc9 | 620 | #define XM_GLB_CFG_REG 0x1220 |
8ceee660 BH |
621 | #define XM_RX_STAT_EN_LBN 11 |
622 | #define XM_RX_STAT_EN_WIDTH 1 | |
623 | #define XM_TX_STAT_EN_LBN 10 | |
624 | #define XM_TX_STAT_EN_WIDTH 1 | |
625 | #define XM_RX_JUMBO_MODE_LBN 6 | |
626 | #define XM_RX_JUMBO_MODE_WIDTH 1 | |
627 | #define XM_INTCLR_MODE_LBN 3 | |
628 | #define XM_INTCLR_MODE_WIDTH 1 | |
629 | #define XM_CORE_RST_LBN 0 | |
630 | #define XM_CORE_RST_WIDTH 1 | |
631 | ||
632 | /* XGMAC transmit configuration */ | |
c1e5fcc9 | 633 | #define XM_TX_CFG_REG 0x1230 |
8ceee660 BH |
634 | #define XM_IPG_LBN 16 |
635 | #define XM_IPG_WIDTH 4 | |
636 | #define XM_FCNTL_LBN 10 | |
637 | #define XM_FCNTL_WIDTH 1 | |
638 | #define XM_TXCRC_LBN 8 | |
639 | #define XM_TXCRC_WIDTH 1 | |
640 | #define XM_AUTO_PAD_LBN 5 | |
641 | #define XM_AUTO_PAD_WIDTH 1 | |
642 | #define XM_TX_PRMBL_LBN 2 | |
643 | #define XM_TX_PRMBL_WIDTH 1 | |
644 | #define XM_TXEN_LBN 1 | |
645 | #define XM_TXEN_WIDTH 1 | |
646 | ||
647 | /* XGMAC receive configuration */ | |
c1e5fcc9 | 648 | #define XM_RX_CFG_REG 0x1240 |
8ceee660 BH |
649 | #define XM_PASS_CRC_ERR_LBN 25 |
650 | #define XM_PASS_CRC_ERR_WIDTH 1 | |
651 | #define XM_ACPT_ALL_MCAST_LBN 11 | |
652 | #define XM_ACPT_ALL_MCAST_WIDTH 1 | |
653 | #define XM_ACPT_ALL_UCAST_LBN 9 | |
654 | #define XM_ACPT_ALL_UCAST_WIDTH 1 | |
655 | #define XM_AUTO_DEPAD_LBN 8 | |
656 | #define XM_AUTO_DEPAD_WIDTH 1 | |
657 | #define XM_RXEN_LBN 1 | |
658 | #define XM_RXEN_WIDTH 1 | |
659 | ||
660 | /* XGMAC management interrupt mask register */ | |
c1e5fcc9 | 661 | #define XM_MGT_INT_MSK_REG_B0 0x1250 |
8ceee660 BH |
662 | #define XM_MSK_PRMBLE_ERR_LBN 2 |
663 | #define XM_MSK_PRMBLE_ERR_WIDTH 1 | |
664 | #define XM_MSK_RMTFLT_LBN 1 | |
665 | #define XM_MSK_RMTFLT_WIDTH 1 | |
666 | #define XM_MSK_LCLFLT_LBN 0 | |
667 | #define XM_MSK_LCLFLT_WIDTH 1 | |
668 | ||
669 | /* XGMAC flow control register */ | |
c1e5fcc9 | 670 | #define XM_FC_REG 0x1270 |
8ceee660 BH |
671 | #define XM_PAUSE_TIME_LBN 16 |
672 | #define XM_PAUSE_TIME_WIDTH 16 | |
673 | #define XM_DIS_FCNTL_LBN 0 | |
674 | #define XM_DIS_FCNTL_WIDTH 1 | |
675 | ||
676 | /* XGMAC pause time count register */ | |
c1e5fcc9 | 677 | #define XM_PAUSE_TIME_REG 0x1290 |
8ceee660 BH |
678 | |
679 | /* XGMAC transmit parameter register */ | |
c1e5fcc9 | 680 | #define XM_TX_PARAM_REG 0x012d0 |
8ceee660 BH |
681 | #define XM_TX_JUMBO_MODE_LBN 31 |
682 | #define XM_TX_JUMBO_MODE_WIDTH 1 | |
683 | #define XM_MAX_TX_FRM_SIZE_LBN 16 | |
684 | #define XM_MAX_TX_FRM_SIZE_WIDTH 14 | |
685 | ||
686 | /* XGMAC receive parameter register */ | |
c1e5fcc9 | 687 | #define XM_RX_PARAM_REG 0x12e0 |
8ceee660 BH |
688 | #define XM_MAX_RX_FRM_SIZE_LBN 0 |
689 | #define XM_MAX_RX_FRM_SIZE_WIDTH 14 | |
690 | ||
691 | /* XGMAC management interrupt status register */ | |
c1e5fcc9 | 692 | #define XM_MGT_INT_REG_B0 0x12f0 |
8ceee660 BH |
693 | #define XM_PRMBLE_ERR 2 |
694 | #define XM_PRMBLE_WIDTH 1 | |
695 | #define XM_RMTFLT_LBN 1 | |
696 | #define XM_RMTFLT_WIDTH 1 | |
697 | #define XM_LCLFLT_LBN 0 | |
698 | #define XM_LCLFLT_WIDTH 1 | |
699 | ||
700 | /* XGXS/XAUI powerdown/reset register */ | |
c1e5fcc9 | 701 | #define XX_PWR_RST_REG 0x1300 |
8ceee660 | 702 | |
d4ec09ac BH |
703 | #define XX_SD_RST_ACT_LBN 16 |
704 | #define XX_SD_RST_ACT_WIDTH 1 | |
8ceee660 BH |
705 | #define XX_PWRDND_EN_LBN 15 |
706 | #define XX_PWRDND_EN_WIDTH 1 | |
707 | #define XX_PWRDNC_EN_LBN 14 | |
708 | #define XX_PWRDNC_EN_WIDTH 1 | |
709 | #define XX_PWRDNB_EN_LBN 13 | |
710 | #define XX_PWRDNB_EN_WIDTH 1 | |
711 | #define XX_PWRDNA_EN_LBN 12 | |
712 | #define XX_PWRDNA_EN_WIDTH 1 | |
713 | #define XX_RSTPLLCD_EN_LBN 9 | |
714 | #define XX_RSTPLLCD_EN_WIDTH 1 | |
715 | #define XX_RSTPLLAB_EN_LBN 8 | |
716 | #define XX_RSTPLLAB_EN_WIDTH 1 | |
717 | #define XX_RESETD_EN_LBN 7 | |
718 | #define XX_RESETD_EN_WIDTH 1 | |
719 | #define XX_RESETC_EN_LBN 6 | |
720 | #define XX_RESETC_EN_WIDTH 1 | |
721 | #define XX_RESETB_EN_LBN 5 | |
722 | #define XX_RESETB_EN_WIDTH 1 | |
723 | #define XX_RESETA_EN_LBN 4 | |
724 | #define XX_RESETA_EN_WIDTH 1 | |
725 | #define XX_RSTXGXSRX_EN_LBN 2 | |
726 | #define XX_RSTXGXSRX_EN_WIDTH 1 | |
727 | #define XX_RSTXGXSTX_EN_LBN 1 | |
728 | #define XX_RSTXGXSTX_EN_WIDTH 1 | |
729 | #define XX_RST_XX_EN_LBN 0 | |
730 | #define XX_RST_XX_EN_WIDTH 1 | |
731 | ||
732 | /* XGXS/XAUI powerdown/reset control register */ | |
c1e5fcc9 | 733 | #define XX_SD_CTL_REG 0x1310 |
8ceee660 BH |
734 | #define XX_HIDRVD_LBN 15 |
735 | #define XX_HIDRVD_WIDTH 1 | |
736 | #define XX_LODRVD_LBN 14 | |
737 | #define XX_LODRVD_WIDTH 1 | |
738 | #define XX_HIDRVC_LBN 13 | |
739 | #define XX_HIDRVC_WIDTH 1 | |
740 | #define XX_LODRVC_LBN 12 | |
741 | #define XX_LODRVC_WIDTH 1 | |
742 | #define XX_HIDRVB_LBN 11 | |
743 | #define XX_HIDRVB_WIDTH 1 | |
744 | #define XX_LODRVB_LBN 10 | |
745 | #define XX_LODRVB_WIDTH 1 | |
746 | #define XX_HIDRVA_LBN 9 | |
747 | #define XX_HIDRVA_WIDTH 1 | |
748 | #define XX_LODRVA_LBN 8 | |
749 | #define XX_LODRVA_WIDTH 1 | |
3273c2e8 BH |
750 | #define XX_LPBKD_LBN 3 |
751 | #define XX_LPBKD_WIDTH 1 | |
752 | #define XX_LPBKC_LBN 2 | |
753 | #define XX_LPBKC_WIDTH 1 | |
754 | #define XX_LPBKB_LBN 1 | |
755 | #define XX_LPBKB_WIDTH 1 | |
756 | #define XX_LPBKA_LBN 0 | |
757 | #define XX_LPBKA_WIDTH 1 | |
8ceee660 | 758 | |
c1e5fcc9 | 759 | #define XX_TXDRV_CTL_REG 0x1320 |
8ceee660 BH |
760 | #define XX_DEQD_LBN 28 |
761 | #define XX_DEQD_WIDTH 4 | |
762 | #define XX_DEQC_LBN 24 | |
763 | #define XX_DEQC_WIDTH 4 | |
764 | #define XX_DEQB_LBN 20 | |
765 | #define XX_DEQB_WIDTH 4 | |
766 | #define XX_DEQA_LBN 16 | |
767 | #define XX_DEQA_WIDTH 4 | |
768 | #define XX_DTXD_LBN 12 | |
769 | #define XX_DTXD_WIDTH 4 | |
770 | #define XX_DTXC_LBN 8 | |
771 | #define XX_DTXC_WIDTH 4 | |
772 | #define XX_DTXB_LBN 4 | |
773 | #define XX_DTXB_WIDTH 4 | |
774 | #define XX_DTXA_LBN 0 | |
775 | #define XX_DTXA_WIDTH 4 | |
776 | ||
777 | /* XAUI XGXS core status register */ | |
c1e5fcc9 | 778 | #define XX_CORE_STAT_REG 0x1360 |
3273c2e8 BH |
779 | #define XX_FORCE_SIG_LBN 24 |
780 | #define XX_FORCE_SIG_WIDTH 8 | |
781 | #define XX_FORCE_SIG_DECODE_FORCED 0xff | |
782 | #define XX_XGXS_LB_EN_LBN 23 | |
783 | #define XX_XGXS_LB_EN_WIDTH 1 | |
784 | #define XX_XGMII_LB_EN_LBN 22 | |
785 | #define XX_XGMII_LB_EN_WIDTH 1 | |
8ceee660 BH |
786 | #define XX_ALIGN_DONE_LBN 20 |
787 | #define XX_ALIGN_DONE_WIDTH 1 | |
788 | #define XX_SYNC_STAT_LBN 16 | |
789 | #define XX_SYNC_STAT_WIDTH 4 | |
790 | #define XX_SYNC_STAT_DECODE_SYNCED 0xf | |
791 | #define XX_COMMA_DET_LBN 12 | |
792 | #define XX_COMMA_DET_WIDTH 4 | |
793 | #define XX_COMMA_DET_DECODE_DETECTED 0xf | |
794 | #define XX_COMMA_DET_RESET 0xf | |
795 | #define XX_CHARERR_LBN 4 | |
796 | #define XX_CHARERR_WIDTH 4 | |
797 | #define XX_CHARERR_RESET 0xf | |
798 | #define XX_DISPERR_LBN 0 | |
799 | #define XX_DISPERR_WIDTH 4 | |
800 | #define XX_DISPERR_RESET 0xf | |
801 | ||
802 | /* Receive filter table */ | |
803 | #define RX_FILTER_TBL0 0xF00000 | |
804 | ||
805 | /* Receive descriptor pointer table */ | |
806 | #define RX_DESC_PTR_TBL_KER_A1 0x11800 | |
807 | #define RX_DESC_PTR_TBL_KER_B0 0xF40000 | |
808 | #define RX_DESC_PTR_TBL_KER_P0 0x900 | |
809 | #define RX_ISCSI_DDIG_EN_LBN 88 | |
810 | #define RX_ISCSI_DDIG_EN_WIDTH 1 | |
811 | #define RX_ISCSI_HDIG_EN_LBN 87 | |
812 | #define RX_ISCSI_HDIG_EN_WIDTH 1 | |
813 | #define RX_DESCQ_BUF_BASE_ID_LBN 36 | |
814 | #define RX_DESCQ_BUF_BASE_ID_WIDTH 20 | |
815 | #define RX_DESCQ_EVQ_ID_LBN 24 | |
816 | #define RX_DESCQ_EVQ_ID_WIDTH 12 | |
817 | #define RX_DESCQ_OWNER_ID_LBN 10 | |
818 | #define RX_DESCQ_OWNER_ID_WIDTH 14 | |
819 | #define RX_DESCQ_LABEL_LBN 5 | |
820 | #define RX_DESCQ_LABEL_WIDTH 5 | |
821 | #define RX_DESCQ_SIZE_LBN 3 | |
822 | #define RX_DESCQ_SIZE_WIDTH 2 | |
823 | #define RX_DESCQ_SIZE_4K 3 | |
824 | #define RX_DESCQ_SIZE_2K 2 | |
825 | #define RX_DESCQ_SIZE_1K 1 | |
826 | #define RX_DESCQ_SIZE_512 0 | |
827 | #define RX_DESCQ_TYPE_LBN 2 | |
828 | #define RX_DESCQ_TYPE_WIDTH 1 | |
829 | #define RX_DESCQ_JUMBO_LBN 1 | |
830 | #define RX_DESCQ_JUMBO_WIDTH 1 | |
831 | #define RX_DESCQ_EN_LBN 0 | |
832 | #define RX_DESCQ_EN_WIDTH 1 | |
833 | ||
834 | /* Transmit descriptor pointer table */ | |
835 | #define TX_DESC_PTR_TBL_KER_A1 0x11900 | |
836 | #define TX_DESC_PTR_TBL_KER_B0 0xF50000 | |
837 | #define TX_DESC_PTR_TBL_KER_P0 0xa40 | |
838 | #define TX_NON_IP_DROP_DIS_B0_LBN 91 | |
839 | #define TX_NON_IP_DROP_DIS_B0_WIDTH 1 | |
840 | #define TX_IP_CHKSM_DIS_B0_LBN 90 | |
841 | #define TX_IP_CHKSM_DIS_B0_WIDTH 1 | |
842 | #define TX_TCP_CHKSM_DIS_B0_LBN 89 | |
843 | #define TX_TCP_CHKSM_DIS_B0_WIDTH 1 | |
844 | #define TX_DESCQ_EN_LBN 88 | |
845 | #define TX_DESCQ_EN_WIDTH 1 | |
846 | #define TX_ISCSI_DDIG_EN_LBN 87 | |
847 | #define TX_ISCSI_DDIG_EN_WIDTH 1 | |
848 | #define TX_ISCSI_HDIG_EN_LBN 86 | |
849 | #define TX_ISCSI_HDIG_EN_WIDTH 1 | |
850 | #define TX_DESCQ_BUF_BASE_ID_LBN 36 | |
851 | #define TX_DESCQ_BUF_BASE_ID_WIDTH 20 | |
852 | #define TX_DESCQ_EVQ_ID_LBN 24 | |
853 | #define TX_DESCQ_EVQ_ID_WIDTH 12 | |
854 | #define TX_DESCQ_OWNER_ID_LBN 10 | |
855 | #define TX_DESCQ_OWNER_ID_WIDTH 14 | |
856 | #define TX_DESCQ_LABEL_LBN 5 | |
857 | #define TX_DESCQ_LABEL_WIDTH 5 | |
858 | #define TX_DESCQ_SIZE_LBN 3 | |
859 | #define TX_DESCQ_SIZE_WIDTH 2 | |
860 | #define TX_DESCQ_SIZE_4K 3 | |
861 | #define TX_DESCQ_SIZE_2K 2 | |
862 | #define TX_DESCQ_SIZE_1K 1 | |
863 | #define TX_DESCQ_SIZE_512 0 | |
864 | #define TX_DESCQ_TYPE_LBN 1 | |
865 | #define TX_DESCQ_TYPE_WIDTH 2 | |
866 | ||
867 | /* Event queue pointer */ | |
868 | #define EVQ_PTR_TBL_KER_A1 0x11a00 | |
869 | #define EVQ_PTR_TBL_KER_B0 0xf60000 | |
870 | #define EVQ_PTR_TBL_KER_P0 0x500 | |
871 | #define EVQ_EN_LBN 23 | |
872 | #define EVQ_EN_WIDTH 1 | |
873 | #define EVQ_SIZE_LBN 20 | |
874 | #define EVQ_SIZE_WIDTH 3 | |
875 | #define EVQ_SIZE_32K 6 | |
876 | #define EVQ_SIZE_16K 5 | |
877 | #define EVQ_SIZE_8K 4 | |
878 | #define EVQ_SIZE_4K 3 | |
879 | #define EVQ_SIZE_2K 2 | |
880 | #define EVQ_SIZE_1K 1 | |
881 | #define EVQ_SIZE_512 0 | |
882 | #define EVQ_BUF_BASE_ID_LBN 0 | |
883 | #define EVQ_BUF_BASE_ID_WIDTH 20 | |
884 | ||
885 | /* Event queue read pointer */ | |
886 | #define EVQ_RPTR_REG_KER_A1 0x11b00 | |
887 | #define EVQ_RPTR_REG_KER_B0 0xfa0000 | |
888 | #define EVQ_RPTR_REG_KER_DWORD (EVQ_RPTR_REG_KER + 0) | |
889 | #define EVQ_RPTR_DWORD_LBN 0 | |
890 | #define EVQ_RPTR_DWORD_WIDTH 14 | |
891 | ||
892 | /* RSS indirection table */ | |
893 | #define RX_RSS_INDIR_TBL_B0 0xFB0000 | |
894 | #define RX_RSS_INDIR_ENT_B0_LBN 0 | |
895 | #define RX_RSS_INDIR_ENT_B0_WIDTH 6 | |
896 | ||
897 | /* Special buffer descriptors (full-mode) */ | |
898 | #define BUF_FULL_TBL_KER_A1 0x8000 | |
899 | #define BUF_FULL_TBL_KER_B0 0x800000 | |
900 | #define IP_DAT_BUF_SIZE_LBN 50 | |
901 | #define IP_DAT_BUF_SIZE_WIDTH 1 | |
902 | #define IP_DAT_BUF_SIZE_8K 1 | |
903 | #define IP_DAT_BUF_SIZE_4K 0 | |
904 | #define BUF_ADR_REGION_LBN 48 | |
905 | #define BUF_ADR_REGION_WIDTH 2 | |
906 | #define BUF_ADR_FBUF_LBN 14 | |
907 | #define BUF_ADR_FBUF_WIDTH 34 | |
908 | #define BUF_OWNER_ID_FBUF_LBN 0 | |
909 | #define BUF_OWNER_ID_FBUF_WIDTH 14 | |
910 | ||
911 | /* Transmit descriptor */ | |
912 | #define TX_KER_PORT_LBN 63 | |
913 | #define TX_KER_PORT_WIDTH 1 | |
914 | #define TX_KER_CONT_LBN 62 | |
915 | #define TX_KER_CONT_WIDTH 1 | |
916 | #define TX_KER_BYTE_CNT_LBN 48 | |
917 | #define TX_KER_BYTE_CNT_WIDTH 14 | |
918 | #define TX_KER_BUF_REGION_LBN 46 | |
919 | #define TX_KER_BUF_REGION_WIDTH 2 | |
920 | #define TX_KER_BUF_REGION0_DECODE 0 | |
921 | #define TX_KER_BUF_REGION1_DECODE 1 | |
922 | #define TX_KER_BUF_REGION2_DECODE 2 | |
923 | #define TX_KER_BUF_REGION3_DECODE 3 | |
924 | #define TX_KER_BUF_ADR_LBN 0 | |
925 | #define TX_KER_BUF_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46) | |
926 | ||
927 | /* Receive descriptor */ | |
928 | #define RX_KER_BUF_SIZE_LBN 48 | |
929 | #define RX_KER_BUF_SIZE_WIDTH 14 | |
930 | #define RX_KER_BUF_REGION_LBN 46 | |
931 | #define RX_KER_BUF_REGION_WIDTH 2 | |
932 | #define RX_KER_BUF_REGION0_DECODE 0 | |
933 | #define RX_KER_BUF_REGION1_DECODE 1 | |
934 | #define RX_KER_BUF_REGION2_DECODE 2 | |
935 | #define RX_KER_BUF_REGION3_DECODE 3 | |
936 | #define RX_KER_BUF_ADR_LBN 0 | |
937 | #define RX_KER_BUF_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46) | |
938 | ||
939 | /************************************************************************** | |
940 | * | |
941 | * Falcon events | |
942 | * | |
943 | ************************************************************************** | |
944 | */ | |
945 | ||
946 | /* Event queue entries */ | |
947 | #define EV_CODE_LBN 60 | |
948 | #define EV_CODE_WIDTH 4 | |
949 | #define RX_IP_EV_DECODE 0 | |
950 | #define TX_IP_EV_DECODE 2 | |
951 | #define DRIVER_EV_DECODE 5 | |
952 | #define GLOBAL_EV_DECODE 6 | |
953 | #define DRV_GEN_EV_DECODE 7 | |
954 | #define WHOLE_EVENT_LBN 0 | |
955 | #define WHOLE_EVENT_WIDTH 64 | |
956 | ||
957 | /* Receive events */ | |
958 | #define RX_EV_PKT_OK_LBN 56 | |
959 | #define RX_EV_PKT_OK_WIDTH 1 | |
960 | #define RX_EV_PAUSE_FRM_ERR_LBN 55 | |
961 | #define RX_EV_PAUSE_FRM_ERR_WIDTH 1 | |
962 | #define RX_EV_BUF_OWNER_ID_ERR_LBN 54 | |
963 | #define RX_EV_BUF_OWNER_ID_ERR_WIDTH 1 | |
964 | #define RX_EV_IF_FRAG_ERR_LBN 53 | |
965 | #define RX_EV_IF_FRAG_ERR_WIDTH 1 | |
966 | #define RX_EV_IP_HDR_CHKSUM_ERR_LBN 52 | |
967 | #define RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1 | |
968 | #define RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51 | |
969 | #define RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1 | |
970 | #define RX_EV_ETH_CRC_ERR_LBN 50 | |
971 | #define RX_EV_ETH_CRC_ERR_WIDTH 1 | |
972 | #define RX_EV_FRM_TRUNC_LBN 49 | |
973 | #define RX_EV_FRM_TRUNC_WIDTH 1 | |
974 | #define RX_EV_DRIB_NIB_LBN 48 | |
975 | #define RX_EV_DRIB_NIB_WIDTH 1 | |
976 | #define RX_EV_TOBE_DISC_LBN 47 | |
977 | #define RX_EV_TOBE_DISC_WIDTH 1 | |
978 | #define RX_EV_PKT_TYPE_LBN 44 | |
979 | #define RX_EV_PKT_TYPE_WIDTH 3 | |
980 | #define RX_EV_PKT_TYPE_ETH_DECODE 0 | |
981 | #define RX_EV_PKT_TYPE_LLC_DECODE 1 | |
982 | #define RX_EV_PKT_TYPE_JUMBO_DECODE 2 | |
983 | #define RX_EV_PKT_TYPE_VLAN_DECODE 3 | |
984 | #define RX_EV_PKT_TYPE_VLAN_LLC_DECODE 4 | |
985 | #define RX_EV_PKT_TYPE_VLAN_JUMBO_DECODE 5 | |
986 | #define RX_EV_HDR_TYPE_LBN 42 | |
987 | #define RX_EV_HDR_TYPE_WIDTH 2 | |
988 | #define RX_EV_HDR_TYPE_TCP_IPV4_DECODE 0 | |
989 | #define RX_EV_HDR_TYPE_UDP_IPV4_DECODE 1 | |
990 | #define RX_EV_HDR_TYPE_OTHER_IP_DECODE 2 | |
991 | #define RX_EV_HDR_TYPE_NON_IP_DECODE 3 | |
992 | #define RX_EV_HDR_TYPE_HAS_CHECKSUMS(hdr_type) \ | |
993 | ((hdr_type) <= RX_EV_HDR_TYPE_UDP_IPV4_DECODE) | |
994 | #define RX_EV_MCAST_HASH_MATCH_LBN 40 | |
995 | #define RX_EV_MCAST_HASH_MATCH_WIDTH 1 | |
996 | #define RX_EV_MCAST_PKT_LBN 39 | |
997 | #define RX_EV_MCAST_PKT_WIDTH 1 | |
998 | #define RX_EV_Q_LABEL_LBN 32 | |
999 | #define RX_EV_Q_LABEL_WIDTH 5 | |
1000 | #define RX_EV_JUMBO_CONT_LBN 31 | |
1001 | #define RX_EV_JUMBO_CONT_WIDTH 1 | |
1002 | #define RX_EV_BYTE_CNT_LBN 16 | |
1003 | #define RX_EV_BYTE_CNT_WIDTH 14 | |
1004 | #define RX_EV_SOP_LBN 15 | |
1005 | #define RX_EV_SOP_WIDTH 1 | |
1006 | #define RX_EV_DESC_PTR_LBN 0 | |
1007 | #define RX_EV_DESC_PTR_WIDTH 12 | |
1008 | ||
1009 | /* Transmit events */ | |
1010 | #define TX_EV_PKT_ERR_LBN 38 | |
1011 | #define TX_EV_PKT_ERR_WIDTH 1 | |
1012 | #define TX_EV_Q_LABEL_LBN 32 | |
1013 | #define TX_EV_Q_LABEL_WIDTH 5 | |
1014 | #define TX_EV_WQ_FF_FULL_LBN 15 | |
1015 | #define TX_EV_WQ_FF_FULL_WIDTH 1 | |
1016 | #define TX_EV_COMP_LBN 12 | |
1017 | #define TX_EV_COMP_WIDTH 1 | |
1018 | #define TX_EV_DESC_PTR_LBN 0 | |
1019 | #define TX_EV_DESC_PTR_WIDTH 12 | |
1020 | ||
1021 | /* Driver events */ | |
1022 | #define DRIVER_EV_SUB_CODE_LBN 56 | |
1023 | #define DRIVER_EV_SUB_CODE_WIDTH 4 | |
1024 | #define DRIVER_EV_SUB_DATA_LBN 0 | |
1025 | #define DRIVER_EV_SUB_DATA_WIDTH 14 | |
1026 | #define TX_DESCQ_FLS_DONE_EV_DECODE 0 | |
1027 | #define RX_DESCQ_FLS_DONE_EV_DECODE 1 | |
1028 | #define EVQ_INIT_DONE_EV_DECODE 2 | |
1029 | #define EVQ_NOT_EN_EV_DECODE 3 | |
1030 | #define RX_DESCQ_FLSFF_OVFL_EV_DECODE 4 | |
1031 | #define SRM_UPD_DONE_EV_DECODE 5 | |
1032 | #define WAKE_UP_EV_DECODE 6 | |
1033 | #define TX_PKT_NON_TCP_UDP_DECODE 9 | |
1034 | #define TIMER_EV_DECODE 10 | |
1035 | #define RX_RECOVERY_EV_DECODE 11 | |
1036 | #define RX_DSC_ERROR_EV_DECODE 14 | |
1037 | #define TX_DSC_ERROR_EV_DECODE 15 | |
1038 | #define DRIVER_EV_TX_DESCQ_ID_LBN 0 | |
1039 | #define DRIVER_EV_TX_DESCQ_ID_WIDTH 12 | |
1040 | #define DRIVER_EV_RX_FLUSH_FAIL_LBN 12 | |
1041 | #define DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1 | |
1042 | #define DRIVER_EV_RX_DESCQ_ID_LBN 0 | |
1043 | #define DRIVER_EV_RX_DESCQ_ID_WIDTH 12 | |
1044 | #define SRM_CLR_EV_DECODE 0 | |
1045 | #define SRM_UPD_EV_DECODE 1 | |
1046 | #define SRM_ILLCLR_EV_DECODE 2 | |
1047 | ||
1048 | /* Global events */ | |
1049 | #define RX_RECOVERY_B0_LBN 12 | |
1050 | #define RX_RECOVERY_B0_WIDTH 1 | |
1051 | #define XG_MNT_INTR_B0_LBN 11 | |
1052 | #define XG_MNT_INTR_B0_WIDTH 1 | |
1053 | #define RX_RECOVERY_A1_LBN 11 | |
1054 | #define RX_RECOVERY_A1_WIDTH 1 | |
766ca0fa BH |
1055 | #define XFP_PHY_INTR_LBN 10 |
1056 | #define XFP_PHY_INTR_WIDTH 1 | |
8ceee660 BH |
1057 | #define XG_PHY_INTR_LBN 9 |
1058 | #define XG_PHY_INTR_WIDTH 1 | |
1059 | #define G_PHY1_INTR_LBN 8 | |
1060 | #define G_PHY1_INTR_WIDTH 1 | |
1061 | #define G_PHY0_INTR_LBN 7 | |
1062 | #define G_PHY0_INTR_WIDTH 1 | |
1063 | ||
1064 | /* Driver-generated test events */ | |
1065 | #define EVQ_MAGIC_LBN 0 | |
1066 | #define EVQ_MAGIC_WIDTH 32 | |
1067 | ||
1068 | /************************************************************************** | |
1069 | * | |
1070 | * Falcon MAC stats | |
1071 | * | |
1072 | ************************************************************************** | |
1073 | * | |
1074 | */ | |
177dfcd8 | 1075 | |
8ceee660 | 1076 | #define GRxGoodOct_offset 0x0 |
177dfcd8 | 1077 | #define GRxGoodOct_WIDTH 48 |
8ceee660 | 1078 | #define GRxBadOct_offset 0x8 |
177dfcd8 | 1079 | #define GRxBadOct_WIDTH 48 |
8ceee660 | 1080 | #define GRxMissPkt_offset 0x10 |
177dfcd8 | 1081 | #define GRxMissPkt_WIDTH 32 |
8ceee660 | 1082 | #define GRxFalseCRS_offset 0x14 |
177dfcd8 | 1083 | #define GRxFalseCRS_WIDTH 32 |
8ceee660 | 1084 | #define GRxPausePkt_offset 0x18 |
177dfcd8 | 1085 | #define GRxPausePkt_WIDTH 32 |
8ceee660 | 1086 | #define GRxBadPkt_offset 0x1C |
177dfcd8 | 1087 | #define GRxBadPkt_WIDTH 32 |
8ceee660 | 1088 | #define GRxUcastPkt_offset 0x20 |
177dfcd8 | 1089 | #define GRxUcastPkt_WIDTH 32 |
8ceee660 | 1090 | #define GRxMcastPkt_offset 0x24 |
177dfcd8 | 1091 | #define GRxMcastPkt_WIDTH 32 |
8ceee660 | 1092 | #define GRxBcastPkt_offset 0x28 |
177dfcd8 | 1093 | #define GRxBcastPkt_WIDTH 32 |
8ceee660 | 1094 | #define GRxGoodLt64Pkt_offset 0x2C |
177dfcd8 | 1095 | #define GRxGoodLt64Pkt_WIDTH 32 |
8ceee660 | 1096 | #define GRxBadLt64Pkt_offset 0x30 |
177dfcd8 | 1097 | #define GRxBadLt64Pkt_WIDTH 32 |
8ceee660 | 1098 | #define GRx64Pkt_offset 0x34 |
177dfcd8 | 1099 | #define GRx64Pkt_WIDTH 32 |
8ceee660 | 1100 | #define GRx65to127Pkt_offset 0x38 |
177dfcd8 | 1101 | #define GRx65to127Pkt_WIDTH 32 |
8ceee660 | 1102 | #define GRx128to255Pkt_offset 0x3C |
177dfcd8 | 1103 | #define GRx128to255Pkt_WIDTH 32 |
8ceee660 | 1104 | #define GRx256to511Pkt_offset 0x40 |
177dfcd8 | 1105 | #define GRx256to511Pkt_WIDTH 32 |
8ceee660 | 1106 | #define GRx512to1023Pkt_offset 0x44 |
177dfcd8 | 1107 | #define GRx512to1023Pkt_WIDTH 32 |
8ceee660 | 1108 | #define GRx1024to15xxPkt_offset 0x48 |
177dfcd8 | 1109 | #define GRx1024to15xxPkt_WIDTH 32 |
8ceee660 | 1110 | #define GRx15xxtoJumboPkt_offset 0x4C |
177dfcd8 | 1111 | #define GRx15xxtoJumboPkt_WIDTH 32 |
8ceee660 | 1112 | #define GRxGtJumboPkt_offset 0x50 |
177dfcd8 | 1113 | #define GRxGtJumboPkt_WIDTH 32 |
8ceee660 | 1114 | #define GRxFcsErr64to15xxPkt_offset 0x54 |
177dfcd8 | 1115 | #define GRxFcsErr64to15xxPkt_WIDTH 32 |
8ceee660 | 1116 | #define GRxFcsErr15xxtoJumboPkt_offset 0x58 |
177dfcd8 | 1117 | #define GRxFcsErr15xxtoJumboPkt_WIDTH 32 |
8ceee660 | 1118 | #define GRxFcsErrGtJumboPkt_offset 0x5C |
177dfcd8 | 1119 | #define GRxFcsErrGtJumboPkt_WIDTH 32 |
8ceee660 | 1120 | #define GTxGoodBadOct_offset 0x80 |
177dfcd8 | 1121 | #define GTxGoodBadOct_WIDTH 48 |
8ceee660 | 1122 | #define GTxGoodOct_offset 0x88 |
177dfcd8 | 1123 | #define GTxGoodOct_WIDTH 48 |
8ceee660 | 1124 | #define GTxSglColPkt_offset 0x90 |
177dfcd8 | 1125 | #define GTxSglColPkt_WIDTH 32 |
8ceee660 | 1126 | #define GTxMultColPkt_offset 0x94 |
177dfcd8 | 1127 | #define GTxMultColPkt_WIDTH 32 |
8ceee660 | 1128 | #define GTxExColPkt_offset 0x98 |
177dfcd8 | 1129 | #define GTxExColPkt_WIDTH 32 |
8ceee660 | 1130 | #define GTxDefPkt_offset 0x9C |
177dfcd8 | 1131 | #define GTxDefPkt_WIDTH 32 |
8ceee660 | 1132 | #define GTxLateCol_offset 0xA0 |
177dfcd8 | 1133 | #define GTxLateCol_WIDTH 32 |
8ceee660 | 1134 | #define GTxExDefPkt_offset 0xA4 |
177dfcd8 | 1135 | #define GTxExDefPkt_WIDTH 32 |
8ceee660 | 1136 | #define GTxPausePkt_offset 0xA8 |
177dfcd8 | 1137 | #define GTxPausePkt_WIDTH 32 |
8ceee660 | 1138 | #define GTxBadPkt_offset 0xAC |
177dfcd8 | 1139 | #define GTxBadPkt_WIDTH 32 |
8ceee660 | 1140 | #define GTxUcastPkt_offset 0xB0 |
177dfcd8 | 1141 | #define GTxUcastPkt_WIDTH 32 |
8ceee660 | 1142 | #define GTxMcastPkt_offset 0xB4 |
177dfcd8 | 1143 | #define GTxMcastPkt_WIDTH 32 |
8ceee660 | 1144 | #define GTxBcastPkt_offset 0xB8 |
177dfcd8 | 1145 | #define GTxBcastPkt_WIDTH 32 |
8ceee660 | 1146 | #define GTxLt64Pkt_offset 0xBC |
177dfcd8 | 1147 | #define GTxLt64Pkt_WIDTH 32 |
8ceee660 | 1148 | #define GTx64Pkt_offset 0xC0 |
177dfcd8 | 1149 | #define GTx64Pkt_WIDTH 32 |
8ceee660 | 1150 | #define GTx65to127Pkt_offset 0xC4 |
177dfcd8 | 1151 | #define GTx65to127Pkt_WIDTH 32 |
8ceee660 | 1152 | #define GTx128to255Pkt_offset 0xC8 |
177dfcd8 | 1153 | #define GTx128to255Pkt_WIDTH 32 |
8ceee660 | 1154 | #define GTx256to511Pkt_offset 0xCC |
177dfcd8 | 1155 | #define GTx256to511Pkt_WIDTH 32 |
8ceee660 | 1156 | #define GTx512to1023Pkt_offset 0xD0 |
177dfcd8 | 1157 | #define GTx512to1023Pkt_WIDTH 32 |
8ceee660 | 1158 | #define GTx1024to15xxPkt_offset 0xD4 |
177dfcd8 | 1159 | #define GTx1024to15xxPkt_WIDTH 32 |
8ceee660 | 1160 | #define GTx15xxtoJumboPkt_offset 0xD8 |
177dfcd8 | 1161 | #define GTx15xxtoJumboPkt_WIDTH 32 |
8ceee660 | 1162 | #define GTxGtJumboPkt_offset 0xDC |
177dfcd8 | 1163 | #define GTxGtJumboPkt_WIDTH 32 |
8ceee660 | 1164 | #define GTxNonTcpUdpPkt_offset 0xE0 |
177dfcd8 | 1165 | #define GTxNonTcpUdpPkt_WIDTH 16 |
8ceee660 | 1166 | #define GTxMacSrcErrPkt_offset 0xE4 |
177dfcd8 | 1167 | #define GTxMacSrcErrPkt_WIDTH 16 |
8ceee660 | 1168 | #define GTxIpSrcErrPkt_offset 0xE8 |
177dfcd8 | 1169 | #define GTxIpSrcErrPkt_WIDTH 16 |
8ceee660 | 1170 | #define GDmaDone_offset 0xEC |
177dfcd8 | 1171 | #define GDmaDone_WIDTH 32 |
8ceee660 BH |
1172 | |
1173 | #define XgRxOctets_offset 0x0 | |
1174 | #define XgRxOctets_WIDTH 48 | |
1175 | #define XgRxOctetsOK_offset 0x8 | |
1176 | #define XgRxOctetsOK_WIDTH 48 | |
1177 | #define XgRxPkts_offset 0x10 | |
1178 | #define XgRxPkts_WIDTH 32 | |
1179 | #define XgRxPktsOK_offset 0x14 | |
1180 | #define XgRxPktsOK_WIDTH 32 | |
1181 | #define XgRxBroadcastPkts_offset 0x18 | |
1182 | #define XgRxBroadcastPkts_WIDTH 32 | |
1183 | #define XgRxMulticastPkts_offset 0x1C | |
1184 | #define XgRxMulticastPkts_WIDTH 32 | |
1185 | #define XgRxUnicastPkts_offset 0x20 | |
1186 | #define XgRxUnicastPkts_WIDTH 32 | |
1187 | #define XgRxUndersizePkts_offset 0x24 | |
1188 | #define XgRxUndersizePkts_WIDTH 32 | |
1189 | #define XgRxOversizePkts_offset 0x28 | |
1190 | #define XgRxOversizePkts_WIDTH 32 | |
1191 | #define XgRxJabberPkts_offset 0x2C | |
1192 | #define XgRxJabberPkts_WIDTH 32 | |
1193 | #define XgRxUndersizeFCSerrorPkts_offset 0x30 | |
1194 | #define XgRxUndersizeFCSerrorPkts_WIDTH 32 | |
1195 | #define XgRxDropEvents_offset 0x34 | |
1196 | #define XgRxDropEvents_WIDTH 32 | |
1197 | #define XgRxFCSerrorPkts_offset 0x38 | |
1198 | #define XgRxFCSerrorPkts_WIDTH 32 | |
1199 | #define XgRxAlignError_offset 0x3C | |
1200 | #define XgRxAlignError_WIDTH 32 | |
1201 | #define XgRxSymbolError_offset 0x40 | |
1202 | #define XgRxSymbolError_WIDTH 32 | |
1203 | #define XgRxInternalMACError_offset 0x44 | |
1204 | #define XgRxInternalMACError_WIDTH 32 | |
1205 | #define XgRxControlPkts_offset 0x48 | |
1206 | #define XgRxControlPkts_WIDTH 32 | |
1207 | #define XgRxPausePkts_offset 0x4C | |
1208 | #define XgRxPausePkts_WIDTH 32 | |
1209 | #define XgRxPkts64Octets_offset 0x50 | |
1210 | #define XgRxPkts64Octets_WIDTH 32 | |
1211 | #define XgRxPkts65to127Octets_offset 0x54 | |
1212 | #define XgRxPkts65to127Octets_WIDTH 32 | |
1213 | #define XgRxPkts128to255Octets_offset 0x58 | |
1214 | #define XgRxPkts128to255Octets_WIDTH 32 | |
1215 | #define XgRxPkts256to511Octets_offset 0x5C | |
1216 | #define XgRxPkts256to511Octets_WIDTH 32 | |
1217 | #define XgRxPkts512to1023Octets_offset 0x60 | |
1218 | #define XgRxPkts512to1023Octets_WIDTH 32 | |
1219 | #define XgRxPkts1024to15xxOctets_offset 0x64 | |
1220 | #define XgRxPkts1024to15xxOctets_WIDTH 32 | |
1221 | #define XgRxPkts15xxtoMaxOctets_offset 0x68 | |
1222 | #define XgRxPkts15xxtoMaxOctets_WIDTH 32 | |
1223 | #define XgRxLengthError_offset 0x6C | |
1224 | #define XgRxLengthError_WIDTH 32 | |
1225 | #define XgTxPkts_offset 0x80 | |
1226 | #define XgTxPkts_WIDTH 32 | |
1227 | #define XgTxOctets_offset 0x88 | |
1228 | #define XgTxOctets_WIDTH 48 | |
1229 | #define XgTxMulticastPkts_offset 0x90 | |
1230 | #define XgTxMulticastPkts_WIDTH 32 | |
1231 | #define XgTxBroadcastPkts_offset 0x94 | |
1232 | #define XgTxBroadcastPkts_WIDTH 32 | |
1233 | #define XgTxUnicastPkts_offset 0x98 | |
1234 | #define XgTxUnicastPkts_WIDTH 32 | |
1235 | #define XgTxControlPkts_offset 0x9C | |
1236 | #define XgTxControlPkts_WIDTH 32 | |
1237 | #define XgTxPausePkts_offset 0xA0 | |
1238 | #define XgTxPausePkts_WIDTH 32 | |
1239 | #define XgTxPkts64Octets_offset 0xA4 | |
1240 | #define XgTxPkts64Octets_WIDTH 32 | |
1241 | #define XgTxPkts65to127Octets_offset 0xA8 | |
1242 | #define XgTxPkts65to127Octets_WIDTH 32 | |
1243 | #define XgTxPkts128to255Octets_offset 0xAC | |
1244 | #define XgTxPkts128to255Octets_WIDTH 32 | |
1245 | #define XgTxPkts256to511Octets_offset 0xB0 | |
1246 | #define XgTxPkts256to511Octets_WIDTH 32 | |
1247 | #define XgTxPkts512to1023Octets_offset 0xB4 | |
1248 | #define XgTxPkts512to1023Octets_WIDTH 32 | |
1249 | #define XgTxPkts1024to15xxOctets_offset 0xB8 | |
1250 | #define XgTxPkts1024to15xxOctets_WIDTH 32 | |
1251 | #define XgTxPkts1519toMaxOctets_offset 0xBC | |
1252 | #define XgTxPkts1519toMaxOctets_WIDTH 32 | |
1253 | #define XgTxUndersizePkts_offset 0xC0 | |
1254 | #define XgTxUndersizePkts_WIDTH 32 | |
1255 | #define XgTxOversizePkts_offset 0xC4 | |
1256 | #define XgTxOversizePkts_WIDTH 32 | |
1257 | #define XgTxNonTcpUdpPkt_offset 0xC8 | |
1258 | #define XgTxNonTcpUdpPkt_WIDTH 16 | |
1259 | #define XgTxMacSrcErrPkt_offset 0xCC | |
1260 | #define XgTxMacSrcErrPkt_WIDTH 16 | |
1261 | #define XgTxIpSrcErrPkt_offset 0xD0 | |
1262 | #define XgTxIpSrcErrPkt_WIDTH 16 | |
1263 | #define XgDmaDone_offset 0xD4 | |
1264 | ||
1265 | #define FALCON_STATS_NOT_DONE 0x00000000 | |
1266 | #define FALCON_STATS_DONE 0xffffffff | |
1267 | ||
1268 | /* Interrupt status register bits */ | |
1269 | #define FATAL_INT_LBN 64 | |
1270 | #define FATAL_INT_WIDTH 1 | |
1271 | #define INT_EVQS_LBN 40 | |
1272 | #define INT_EVQS_WIDTH 4 | |
1273 | ||
1274 | /************************************************************************** | |
1275 | * | |
1276 | * Falcon non-volatile configuration | |
1277 | * | |
1278 | ************************************************************************** | |
1279 | */ | |
1280 | ||
1281 | /* Board configuration v2 (v1 is obsolete; later versions are compatible) */ | |
1282 | struct falcon_nvconfig_board_v2 { | |
1283 | __le16 nports; | |
1284 | u8 port0_phy_addr; | |
1285 | u8 port0_phy_type; | |
1286 | u8 port1_phy_addr; | |
1287 | u8 port1_phy_type; | |
1288 | __le16 asic_sub_revision; | |
1289 | __le16 board_revision; | |
24c28edc | 1290 | } __packed; |
8ceee660 | 1291 | |
4a5b504d BH |
1292 | /* Board configuration v3 extra information */ |
1293 | struct falcon_nvconfig_board_v3 { | |
1294 | __le32 spi_device_type[2]; | |
1295 | } __packed; | |
1296 | ||
1297 | /* Bit numbers for spi_device_type */ | |
1298 | #define SPI_DEV_TYPE_SIZE_LBN 0 | |
1299 | #define SPI_DEV_TYPE_SIZE_WIDTH 5 | |
1300 | #define SPI_DEV_TYPE_ADDR_LEN_LBN 6 | |
1301 | #define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2 | |
1302 | #define SPI_DEV_TYPE_ERASE_CMD_LBN 8 | |
1303 | #define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8 | |
1304 | #define SPI_DEV_TYPE_ERASE_SIZE_LBN 16 | |
1305 | #define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5 | |
1306 | #define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24 | |
1307 | #define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5 | |
a515089c BH |
1308 | #define SPI_DEV_TYPE_FIELD(type, field) \ |
1309 | (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field))) | |
4a5b504d | 1310 | |
8c8661e4 | 1311 | #define NVCONFIG_OFFSET 0x300 |
8c8661e4 | 1312 | |
8ceee660 BH |
1313 | #define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C |
1314 | struct falcon_nvconfig { | |
1315 | efx_oword_t ee_vpd_cfg_reg; /* 0x300 */ | |
1316 | u8 mac_address[2][8]; /* 0x310 */ | |
1317 | efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */ | |
1318 | efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */ | |
1319 | efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */ | |
1320 | efx_oword_t hw_init_reg; /* 0x350 */ | |
1321 | efx_oword_t nic_stat_reg; /* 0x360 */ | |
1322 | efx_oword_t glb_ctl_reg; /* 0x370 */ | |
1323 | efx_oword_t srm_cfg_reg; /* 0x380 */ | |
1324 | efx_oword_t spare_reg; /* 0x390 */ | |
1325 | __le16 board_magic_num; /* 0x3A0 */ | |
1326 | __le16 board_struct_ver; | |
1327 | __le16 board_checksum; | |
1328 | struct falcon_nvconfig_board_v2 board_v2; | |
4a5b504d BH |
1329 | efx_oword_t ee_base_page_reg; /* 0x3B0 */ |
1330 | struct falcon_nvconfig_board_v3 board_v3; | |
24c28edc | 1331 | } __packed; |
8ceee660 BH |
1332 | |
1333 | #endif /* EFX_FALCON_HWDEFS_H */ |