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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2006-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/seq_file.h> | |
37b5a603 | 16 | #include <linux/i2c.h> |
f31a45d2 | 17 | #include <linux/mii.h> |
8ceee660 BH |
18 | #include "net_driver.h" |
19 | #include "bitfield.h" | |
20 | #include "efx.h" | |
21 | #include "mac.h" | |
8ceee660 BH |
22 | #include "spi.h" |
23 | #include "falcon.h" | |
3e6c4538 | 24 | #include "regs.h" |
12d00cad | 25 | #include "io.h" |
8ceee660 BH |
26 | #include "mdio_10g.h" |
27 | #include "phy.h" | |
8ceee660 BH |
28 | #include "workarounds.h" |
29 | ||
8986352a | 30 | /* Hardware control for SFC4000 (aka Falcon). */ |
8ceee660 | 31 | |
8ceee660 BH |
32 | /************************************************************************** |
33 | * | |
34 | * Configurable values | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
8ceee660 BH |
39 | /* This is set to 16 for a good reason. In summary, if larger than |
40 | * 16, the descriptor cache holds more than a default socket | |
41 | * buffer's worth of packets (for UDP we can only have at most one | |
42 | * socket buffer's worth outstanding). This combined with the fact | |
43 | * that we only get 1 TX event per descriptor cache means the NIC | |
44 | * goes idle. | |
45 | */ | |
46 | #define TX_DC_ENTRIES 16 | |
46e1ac0f | 47 | #define TX_DC_ENTRIES_ORDER 1 |
8ceee660 BH |
48 | #define TX_DC_BASE 0x130000 |
49 | ||
50 | #define RX_DC_ENTRIES 64 | |
46e1ac0f | 51 | #define RX_DC_ENTRIES_ORDER 3 |
8ceee660 BH |
52 | #define RX_DC_BASE 0x100000 |
53 | ||
2f7f5730 BH |
54 | static const unsigned int |
55 | /* "Large" EEPROM device: Atmel AT25640 or similar | |
56 | * 8 KB, 16-bit address, 32 B write block */ | |
57 | large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) | |
58 | | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
59 | | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), | |
60 | /* Default flash device: Atmel AT25F1024 | |
61 | * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ | |
62 | default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) | |
63 | | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
64 | | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) | |
65 | | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) | |
66 | | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); | |
67 | ||
8ceee660 BH |
68 | /* RX FIFO XOFF watermark |
69 | * | |
70 | * When the amount of the RX FIFO increases used increases past this | |
71 | * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A) | |
72 | * This also has an effect on RX/TX arbitration | |
73 | */ | |
74 | static int rx_xoff_thresh_bytes = -1; | |
75 | module_param(rx_xoff_thresh_bytes, int, 0644); | |
76 | MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold"); | |
77 | ||
78 | /* RX FIFO XON watermark | |
79 | * | |
80 | * When the amount of the RX FIFO used decreases below this | |
81 | * watermark send XON. Only used if TX flow control is enabled (ethtool -A) | |
82 | * This also has an effect on RX/TX arbitration | |
83 | */ | |
84 | static int rx_xon_thresh_bytes = -1; | |
85 | module_param(rx_xon_thresh_bytes, int, 0644); | |
86 | MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold"); | |
87 | ||
2c3c3d02 BH |
88 | /* If FALCON_MAX_INT_ERRORS internal errors occur within |
89 | * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and | |
90 | * disable it. | |
91 | */ | |
92 | #define FALCON_INT_ERROR_EXPIRE 3600 | |
93 | #define FALCON_MAX_INT_ERRORS 5 | |
8ceee660 | 94 | |
6bc5d3a9 BH |
95 | /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times |
96 | */ | |
97 | #define FALCON_FLUSH_INTERVAL 10 | |
98 | #define FALCON_FLUSH_POLL_COUNT 100 | |
8ceee660 BH |
99 | |
100 | /************************************************************************** | |
101 | * | |
102 | * Falcon constants | |
103 | * | |
104 | ************************************************************************** | |
105 | */ | |
106 | ||
8ceee660 BH |
107 | /* Size and alignment of special buffers (4KB) */ |
108 | #define FALCON_BUF_SIZE 4096 | |
109 | ||
127e6e10 BH |
110 | /* Depth of RX flush request fifo */ |
111 | #define FALCON_RX_FLUSH_COUNT 4 | |
112 | ||
8ceee660 | 113 | #define FALCON_IS_DUAL_FUNC(efx) \ |
daeda630 | 114 | (efx_nic_rev(efx) < EFX_REV_FALCON_B0) |
8ceee660 BH |
115 | |
116 | /************************************************************************** | |
117 | * | |
118 | * Falcon hardware access | |
119 | * | |
120 | **************************************************************************/ | |
121 | ||
12d00cad BH |
122 | static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value, |
123 | unsigned int index) | |
124 | { | |
125 | efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base, | |
126 | value, index); | |
127 | } | |
128 | ||
8ceee660 BH |
129 | /* Read the current event from the event queue */ |
130 | static inline efx_qword_t *falcon_event(struct efx_channel *channel, | |
131 | unsigned int index) | |
132 | { | |
133 | return (((efx_qword_t *) (channel->eventq.addr)) + index); | |
134 | } | |
135 | ||
136 | /* See if an event is present | |
137 | * | |
138 | * We check both the high and low dword of the event for all ones. We | |
139 | * wrote all ones when we cleared the event, and no valid event can | |
140 | * have all ones in either its high or low dwords. This approach is | |
141 | * robust against reordering. | |
142 | * | |
143 | * Note that using a single 64-bit comparison is incorrect; even | |
144 | * though the CPU read will be atomic, the DMA write may not be. | |
145 | */ | |
146 | static inline int falcon_event_present(efx_qword_t *event) | |
147 | { | |
148 | return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | | |
149 | EFX_DWORD_IS_ALL_ONES(event->dword[1]))); | |
150 | } | |
151 | ||
152 | /************************************************************************** | |
153 | * | |
154 | * I2C bus - this is a bit-bashing interface using GPIO pins | |
155 | * Note that it uses the output enables to tristate the outputs | |
156 | * SDA is the data pin and SCL is the clock | |
157 | * | |
158 | ************************************************************************** | |
159 | */ | |
37b5a603 | 160 | static void falcon_setsda(void *data, int state) |
8ceee660 | 161 | { |
37b5a603 | 162 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
163 | efx_oword_t reg; |
164 | ||
12d00cad | 165 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 166 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); |
12d00cad | 167 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
8ceee660 BH |
168 | } |
169 | ||
37b5a603 | 170 | static void falcon_setscl(void *data, int state) |
8ceee660 | 171 | { |
37b5a603 | 172 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
173 | efx_oword_t reg; |
174 | ||
12d00cad | 175 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 176 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); |
12d00cad | 177 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
37b5a603 BH |
178 | } |
179 | ||
180 | static int falcon_getsda(void *data) | |
181 | { | |
182 | struct efx_nic *efx = (struct efx_nic *)data; | |
183 | efx_oword_t reg; | |
184 | ||
12d00cad | 185 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 186 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); |
8ceee660 BH |
187 | } |
188 | ||
37b5a603 | 189 | static int falcon_getscl(void *data) |
8ceee660 | 190 | { |
37b5a603 | 191 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
192 | efx_oword_t reg; |
193 | ||
12d00cad | 194 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 195 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); |
8ceee660 BH |
196 | } |
197 | ||
37b5a603 BH |
198 | static struct i2c_algo_bit_data falcon_i2c_bit_operations = { |
199 | .setsda = falcon_setsda, | |
200 | .setscl = falcon_setscl, | |
8ceee660 BH |
201 | .getsda = falcon_getsda, |
202 | .getscl = falcon_getscl, | |
62c78329 | 203 | .udelay = 5, |
9dadae68 BH |
204 | /* Wait up to 50 ms for slave to let us pull SCL high */ |
205 | .timeout = DIV_ROUND_UP(HZ, 20), | |
8ceee660 BH |
206 | }; |
207 | ||
208 | /************************************************************************** | |
209 | * | |
210 | * Falcon special buffer handling | |
211 | * Special buffers are used for event queues and the TX and RX | |
212 | * descriptor rings. | |
213 | * | |
214 | *************************************************************************/ | |
215 | ||
216 | /* | |
217 | * Initialise a Falcon special buffer | |
218 | * | |
219 | * This will define a buffer (previously allocated via | |
220 | * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing | |
221 | * it to be used for event queues, descriptor rings etc. | |
222 | */ | |
bc3c90a2 | 223 | static void |
8ceee660 BH |
224 | falcon_init_special_buffer(struct efx_nic *efx, |
225 | struct efx_special_buffer *buffer) | |
226 | { | |
227 | efx_qword_t buf_desc; | |
228 | int index; | |
229 | dma_addr_t dma_addr; | |
230 | int i; | |
231 | ||
232 | EFX_BUG_ON_PARANOID(!buffer->addr); | |
233 | ||
234 | /* Write buffer descriptors to NIC */ | |
235 | for (i = 0; i < buffer->entries; i++) { | |
236 | index = buffer->index + i; | |
237 | dma_addr = buffer->dma_addr + (i * 4096); | |
238 | EFX_LOG(efx, "mapping special buffer %d at %llx\n", | |
239 | index, (unsigned long long)dma_addr); | |
3e6c4538 BH |
240 | EFX_POPULATE_QWORD_3(buf_desc, |
241 | FRF_AZ_BUF_ADR_REGION, 0, | |
242 | FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12, | |
243 | FRF_AZ_BUF_OWNER_ID_FBUF, 0); | |
12d00cad | 244 | falcon_write_buf_tbl(efx, &buf_desc, index); |
8ceee660 | 245 | } |
8ceee660 BH |
246 | } |
247 | ||
248 | /* Unmaps a buffer from Falcon and clears the buffer table entries */ | |
249 | static void | |
250 | falcon_fini_special_buffer(struct efx_nic *efx, | |
251 | struct efx_special_buffer *buffer) | |
252 | { | |
253 | efx_oword_t buf_tbl_upd; | |
254 | unsigned int start = buffer->index; | |
255 | unsigned int end = (buffer->index + buffer->entries - 1); | |
256 | ||
257 | if (!buffer->entries) | |
258 | return; | |
259 | ||
260 | EFX_LOG(efx, "unmapping special buffers %d-%d\n", | |
261 | buffer->index, buffer->index + buffer->entries - 1); | |
262 | ||
263 | EFX_POPULATE_OWORD_4(buf_tbl_upd, | |
3e6c4538 BH |
264 | FRF_AZ_BUF_UPD_CMD, 0, |
265 | FRF_AZ_BUF_CLR_CMD, 1, | |
266 | FRF_AZ_BUF_CLR_END_ID, end, | |
267 | FRF_AZ_BUF_CLR_START_ID, start); | |
12d00cad | 268 | efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD); |
8ceee660 BH |
269 | } |
270 | ||
271 | /* | |
272 | * Allocate a new Falcon special buffer | |
273 | * | |
274 | * This allocates memory for a new buffer, clears it and allocates a | |
275 | * new buffer ID range. It does not write into Falcon's buffer table. | |
276 | * | |
277 | * This call will allocate 4KB buffers, since Falcon can't use 8KB | |
278 | * buffers for event queues and descriptor rings. | |
279 | */ | |
280 | static int falcon_alloc_special_buffer(struct efx_nic *efx, | |
281 | struct efx_special_buffer *buffer, | |
282 | unsigned int len) | |
283 | { | |
8ceee660 BH |
284 | len = ALIGN(len, FALCON_BUF_SIZE); |
285 | ||
286 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, | |
287 | &buffer->dma_addr); | |
288 | if (!buffer->addr) | |
289 | return -ENOMEM; | |
290 | buffer->len = len; | |
291 | buffer->entries = len / FALCON_BUF_SIZE; | |
292 | BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1)); | |
293 | ||
294 | /* All zeros is a potentially valid event so memset to 0xff */ | |
295 | memset(buffer->addr, 0xff, len); | |
296 | ||
297 | /* Select new buffer ID */ | |
0484e0db BH |
298 | buffer->index = efx->next_buffer_table; |
299 | efx->next_buffer_table += buffer->entries; | |
8ceee660 BH |
300 | |
301 | EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x " | |
9c8976a1 | 302 | "(virt %p phys %llx)\n", buffer->index, |
8ceee660 | 303 | buffer->index + buffer->entries - 1, |
9c8976a1 JSR |
304 | (u64)buffer->dma_addr, len, |
305 | buffer->addr, (u64)virt_to_phys(buffer->addr)); | |
8ceee660 BH |
306 | |
307 | return 0; | |
308 | } | |
309 | ||
310 | static void falcon_free_special_buffer(struct efx_nic *efx, | |
311 | struct efx_special_buffer *buffer) | |
312 | { | |
313 | if (!buffer->addr) | |
314 | return; | |
315 | ||
316 | EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x " | |
9c8976a1 | 317 | "(virt %p phys %llx)\n", buffer->index, |
8ceee660 | 318 | buffer->index + buffer->entries - 1, |
9c8976a1 JSR |
319 | (u64)buffer->dma_addr, buffer->len, |
320 | buffer->addr, (u64)virt_to_phys(buffer->addr)); | |
8ceee660 BH |
321 | |
322 | pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr, | |
323 | buffer->dma_addr); | |
324 | buffer->addr = NULL; | |
325 | buffer->entries = 0; | |
326 | } | |
327 | ||
328 | /************************************************************************** | |
329 | * | |
330 | * Falcon generic buffer handling | |
331 | * These buffers are used for interrupt status and MAC stats | |
332 | * | |
333 | **************************************************************************/ | |
334 | ||
335 | static int falcon_alloc_buffer(struct efx_nic *efx, | |
336 | struct efx_buffer *buffer, unsigned int len) | |
337 | { | |
338 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, | |
339 | &buffer->dma_addr); | |
340 | if (!buffer->addr) | |
341 | return -ENOMEM; | |
342 | buffer->len = len; | |
343 | memset(buffer->addr, 0, len); | |
344 | return 0; | |
345 | } | |
346 | ||
347 | static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) | |
348 | { | |
349 | if (buffer->addr) { | |
350 | pci_free_consistent(efx->pci_dev, buffer->len, | |
351 | buffer->addr, buffer->dma_addr); | |
352 | buffer->addr = NULL; | |
353 | } | |
354 | } | |
355 | ||
356 | /************************************************************************** | |
357 | * | |
358 | * Falcon TX path | |
359 | * | |
360 | **************************************************************************/ | |
361 | ||
362 | /* Returns a pointer to the specified transmit descriptor in the TX | |
363 | * descriptor queue belonging to the specified channel. | |
364 | */ | |
365 | static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue, | |
366 | unsigned int index) | |
367 | { | |
368 | return (((efx_qword_t *) (tx_queue->txd.addr)) + index); | |
369 | } | |
370 | ||
371 | /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ | |
372 | static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue) | |
373 | { | |
374 | unsigned write_ptr; | |
375 | efx_dword_t reg; | |
376 | ||
3ffeabdd | 377 | write_ptr = tx_queue->write_count & EFX_TXQ_MASK; |
3e6c4538 | 378 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); |
12d00cad BH |
379 | efx_writed_page(tx_queue->efx, ®, |
380 | FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue); | |
8ceee660 BH |
381 | } |
382 | ||
383 | ||
384 | /* For each entry inserted into the software descriptor ring, create a | |
385 | * descriptor in the hardware TX descriptor ring (in host memory), and | |
386 | * write a doorbell. | |
387 | */ | |
388 | void falcon_push_buffers(struct efx_tx_queue *tx_queue) | |
389 | { | |
390 | ||
391 | struct efx_tx_buffer *buffer; | |
392 | efx_qword_t *txd; | |
393 | unsigned write_ptr; | |
394 | ||
395 | BUG_ON(tx_queue->write_count == tx_queue->insert_count); | |
396 | ||
397 | do { | |
3ffeabdd | 398 | write_ptr = tx_queue->write_count & EFX_TXQ_MASK; |
8ceee660 BH |
399 | buffer = &tx_queue->buffer[write_ptr]; |
400 | txd = falcon_tx_desc(tx_queue, write_ptr); | |
401 | ++tx_queue->write_count; | |
402 | ||
403 | /* Create TX descriptor ring entry */ | |
3e6c4538 BH |
404 | EFX_POPULATE_QWORD_4(*txd, |
405 | FSF_AZ_TX_KER_CONT, buffer->continuation, | |
406 | FSF_AZ_TX_KER_BYTE_COUNT, buffer->len, | |
407 | FSF_AZ_TX_KER_BUF_REGION, 0, | |
408 | FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr); | |
8ceee660 BH |
409 | } while (tx_queue->write_count != tx_queue->insert_count); |
410 | ||
411 | wmb(); /* Ensure descriptors are written before they are fetched */ | |
412 | falcon_notify_tx_desc(tx_queue); | |
413 | } | |
414 | ||
415 | /* Allocate hardware resources for a TX queue */ | |
416 | int falcon_probe_tx(struct efx_tx_queue *tx_queue) | |
417 | { | |
418 | struct efx_nic *efx = tx_queue->efx; | |
3ffeabdd BH |
419 | BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 || |
420 | EFX_TXQ_SIZE & EFX_TXQ_MASK); | |
8ceee660 | 421 | return falcon_alloc_special_buffer(efx, &tx_queue->txd, |
3ffeabdd | 422 | EFX_TXQ_SIZE * sizeof(efx_qword_t)); |
8ceee660 BH |
423 | } |
424 | ||
bc3c90a2 | 425 | void falcon_init_tx(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
426 | { |
427 | efx_oword_t tx_desc_ptr; | |
428 | struct efx_nic *efx = tx_queue->efx; | |
8ceee660 | 429 | |
127e6e10 | 430 | tx_queue->flushed = FLUSH_NONE; |
6bc5d3a9 | 431 | |
8ceee660 | 432 | /* Pin TX descriptor ring */ |
bc3c90a2 | 433 | falcon_init_special_buffer(efx, &tx_queue->txd); |
8ceee660 BH |
434 | |
435 | /* Push TX descriptor ring to card */ | |
436 | EFX_POPULATE_OWORD_10(tx_desc_ptr, | |
3e6c4538 BH |
437 | FRF_AZ_TX_DESCQ_EN, 1, |
438 | FRF_AZ_TX_ISCSI_DDIG_EN, 0, | |
439 | FRF_AZ_TX_ISCSI_HDIG_EN, 0, | |
440 | FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index, | |
441 | FRF_AZ_TX_DESCQ_EVQ_ID, | |
442 | tx_queue->channel->channel, | |
443 | FRF_AZ_TX_DESCQ_OWNER_ID, 0, | |
444 | FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue, | |
3ffeabdd BH |
445 | FRF_AZ_TX_DESCQ_SIZE, |
446 | __ffs(tx_queue->txd.entries), | |
3e6c4538 BH |
447 | FRF_AZ_TX_DESCQ_TYPE, 0, |
448 | FRF_BZ_TX_NON_IP_DROP_DIS, 1); | |
8ceee660 | 449 | |
daeda630 | 450 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
60ac1065 | 451 | int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM; |
3e6c4538 BH |
452 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum); |
453 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS, | |
454 | !csum); | |
8ceee660 BH |
455 | } |
456 | ||
12d00cad BH |
457 | efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, |
458 | tx_queue->queue); | |
8ceee660 | 459 | |
daeda630 | 460 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { |
8ceee660 BH |
461 | efx_oword_t reg; |
462 | ||
60ac1065 BH |
463 | /* Only 128 bits in this register */ |
464 | BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128); | |
8ceee660 | 465 | |
12d00cad | 466 | efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG); |
60ac1065 | 467 | if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM) |
8ceee660 BH |
468 | clear_bit_le(tx_queue->queue, (void *)®); |
469 | else | |
470 | set_bit_le(tx_queue->queue, (void *)®); | |
12d00cad | 471 | efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG); |
8ceee660 | 472 | } |
8ceee660 BH |
473 | } |
474 | ||
6bc5d3a9 | 475 | static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
476 | { |
477 | struct efx_nic *efx = tx_queue->efx; | |
8ceee660 | 478 | efx_oword_t tx_flush_descq; |
8ceee660 | 479 | |
127e6e10 BH |
480 | tx_queue->flushed = FLUSH_PENDING; |
481 | ||
8ceee660 BH |
482 | /* Post a flush command */ |
483 | EFX_POPULATE_OWORD_2(tx_flush_descq, | |
3e6c4538 BH |
484 | FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, |
485 | FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue); | |
12d00cad | 486 | efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ); |
8ceee660 BH |
487 | } |
488 | ||
489 | void falcon_fini_tx(struct efx_tx_queue *tx_queue) | |
490 | { | |
491 | struct efx_nic *efx = tx_queue->efx; | |
492 | efx_oword_t tx_desc_ptr; | |
493 | ||
6bc5d3a9 | 494 | /* The queue should have been flushed */ |
127e6e10 | 495 | WARN_ON(tx_queue->flushed != FLUSH_DONE); |
8ceee660 BH |
496 | |
497 | /* Remove TX descriptor ring from card */ | |
498 | EFX_ZERO_OWORD(tx_desc_ptr); | |
12d00cad BH |
499 | efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, |
500 | tx_queue->queue); | |
8ceee660 BH |
501 | |
502 | /* Unpin TX descriptor ring */ | |
503 | falcon_fini_special_buffer(efx, &tx_queue->txd); | |
504 | } | |
505 | ||
506 | /* Free buffers backing TX queue */ | |
507 | void falcon_remove_tx(struct efx_tx_queue *tx_queue) | |
508 | { | |
509 | falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd); | |
510 | } | |
511 | ||
512 | /************************************************************************** | |
513 | * | |
514 | * Falcon RX path | |
515 | * | |
516 | **************************************************************************/ | |
517 | ||
518 | /* Returns a pointer to the specified descriptor in the RX descriptor queue */ | |
519 | static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue, | |
520 | unsigned int index) | |
521 | { | |
522 | return (((efx_qword_t *) (rx_queue->rxd.addr)) + index); | |
523 | } | |
524 | ||
525 | /* This creates an entry in the RX descriptor queue */ | |
526 | static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue, | |
527 | unsigned index) | |
528 | { | |
529 | struct efx_rx_buffer *rx_buf; | |
530 | efx_qword_t *rxd; | |
531 | ||
532 | rxd = falcon_rx_desc(rx_queue, index); | |
533 | rx_buf = efx_rx_buffer(rx_queue, index); | |
534 | EFX_POPULATE_QWORD_3(*rxd, | |
3e6c4538 | 535 | FSF_AZ_RX_KER_BUF_SIZE, |
8ceee660 BH |
536 | rx_buf->len - |
537 | rx_queue->efx->type->rx_buffer_padding, | |
3e6c4538 BH |
538 | FSF_AZ_RX_KER_BUF_REGION, 0, |
539 | FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); | |
8ceee660 BH |
540 | } |
541 | ||
542 | /* This writes to the RX_DESC_WPTR register for the specified receive | |
543 | * descriptor ring. | |
544 | */ | |
545 | void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue) | |
546 | { | |
547 | efx_dword_t reg; | |
548 | unsigned write_ptr; | |
549 | ||
550 | while (rx_queue->notified_count != rx_queue->added_count) { | |
551 | falcon_build_rx_desc(rx_queue, | |
552 | rx_queue->notified_count & | |
3ffeabdd | 553 | EFX_RXQ_MASK); |
8ceee660 BH |
554 | ++rx_queue->notified_count; |
555 | } | |
556 | ||
557 | wmb(); | |
3ffeabdd | 558 | write_ptr = rx_queue->added_count & EFX_RXQ_MASK; |
3e6c4538 | 559 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); |
12d00cad BH |
560 | efx_writed_page(rx_queue->efx, ®, |
561 | FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue); | |
8ceee660 BH |
562 | } |
563 | ||
564 | int falcon_probe_rx(struct efx_rx_queue *rx_queue) | |
565 | { | |
566 | struct efx_nic *efx = rx_queue->efx; | |
3ffeabdd BH |
567 | BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 || |
568 | EFX_RXQ_SIZE & EFX_RXQ_MASK); | |
8ceee660 | 569 | return falcon_alloc_special_buffer(efx, &rx_queue->rxd, |
3ffeabdd | 570 | EFX_RXQ_SIZE * sizeof(efx_qword_t)); |
8ceee660 BH |
571 | } |
572 | ||
bc3c90a2 | 573 | void falcon_init_rx(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
574 | { |
575 | efx_oword_t rx_desc_ptr; | |
576 | struct efx_nic *efx = rx_queue->efx; | |
daeda630 | 577 | bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0; |
dc8cfa55 | 578 | bool iscsi_digest_en = is_b0; |
8ceee660 BH |
579 | |
580 | EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n", | |
581 | rx_queue->queue, rx_queue->rxd.index, | |
582 | rx_queue->rxd.index + rx_queue->rxd.entries - 1); | |
583 | ||
127e6e10 | 584 | rx_queue->flushed = FLUSH_NONE; |
6bc5d3a9 | 585 | |
8ceee660 | 586 | /* Pin RX descriptor ring */ |
bc3c90a2 | 587 | falcon_init_special_buffer(efx, &rx_queue->rxd); |
8ceee660 BH |
588 | |
589 | /* Push RX descriptor ring to card */ | |
590 | EFX_POPULATE_OWORD_10(rx_desc_ptr, | |
3e6c4538 BH |
591 | FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en, |
592 | FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en, | |
593 | FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index, | |
594 | FRF_AZ_RX_DESCQ_EVQ_ID, | |
595 | rx_queue->channel->channel, | |
596 | FRF_AZ_RX_DESCQ_OWNER_ID, 0, | |
597 | FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue, | |
3ffeabdd BH |
598 | FRF_AZ_RX_DESCQ_SIZE, |
599 | __ffs(rx_queue->rxd.entries), | |
3e6c4538 | 600 | FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ , |
8ceee660 | 601 | /* For >=B0 this is scatter so disable */ |
3e6c4538 BH |
602 | FRF_AZ_RX_DESCQ_JUMBO, !is_b0, |
603 | FRF_AZ_RX_DESCQ_EN, 1); | |
12d00cad BH |
604 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, |
605 | rx_queue->queue); | |
8ceee660 BH |
606 | } |
607 | ||
6bc5d3a9 | 608 | static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
609 | { |
610 | struct efx_nic *efx = rx_queue->efx; | |
8ceee660 BH |
611 | efx_oword_t rx_flush_descq; |
612 | ||
127e6e10 BH |
613 | rx_queue->flushed = FLUSH_PENDING; |
614 | ||
8ceee660 BH |
615 | /* Post a flush command */ |
616 | EFX_POPULATE_OWORD_2(rx_flush_descq, | |
3e6c4538 BH |
617 | FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, |
618 | FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue); | |
12d00cad | 619 | efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ); |
8ceee660 BH |
620 | } |
621 | ||
622 | void falcon_fini_rx(struct efx_rx_queue *rx_queue) | |
623 | { | |
624 | efx_oword_t rx_desc_ptr; | |
625 | struct efx_nic *efx = rx_queue->efx; | |
8ceee660 | 626 | |
6bc5d3a9 | 627 | /* The queue should already have been flushed */ |
127e6e10 | 628 | WARN_ON(rx_queue->flushed != FLUSH_DONE); |
8ceee660 BH |
629 | |
630 | /* Remove RX descriptor ring from card */ | |
631 | EFX_ZERO_OWORD(rx_desc_ptr); | |
12d00cad BH |
632 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, |
633 | rx_queue->queue); | |
8ceee660 BH |
634 | |
635 | /* Unpin RX descriptor ring */ | |
636 | falcon_fini_special_buffer(efx, &rx_queue->rxd); | |
637 | } | |
638 | ||
639 | /* Free buffers backing RX queue */ | |
640 | void falcon_remove_rx(struct efx_rx_queue *rx_queue) | |
641 | { | |
642 | falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd); | |
643 | } | |
644 | ||
645 | /************************************************************************** | |
646 | * | |
647 | * Falcon event queue processing | |
648 | * Event queues are processed by per-channel tasklets. | |
649 | * | |
650 | **************************************************************************/ | |
651 | ||
652 | /* Update a channel's event queue's read pointer (RPTR) register | |
653 | * | |
654 | * This writes the EVQ_RPTR_REG register for the specified channel's | |
655 | * event queue. | |
656 | * | |
657 | * Note that EVQ_RPTR_REG contains the index of the "last read" event, | |
658 | * whereas channel->eventq_read_ptr contains the index of the "next to | |
659 | * read" event. | |
660 | */ | |
661 | void falcon_eventq_read_ack(struct efx_channel *channel) | |
662 | { | |
663 | efx_dword_t reg; | |
664 | struct efx_nic *efx = channel->efx; | |
665 | ||
3e6c4538 | 666 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr); |
12d00cad | 667 | efx_writed_table(efx, ®, efx->type->evq_rptr_tbl_base, |
d3074025 | 668 | channel->channel); |
8ceee660 BH |
669 | } |
670 | ||
671 | /* Use HW to insert a SW defined event */ | |
672 | void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event) | |
673 | { | |
674 | efx_oword_t drv_ev_reg; | |
675 | ||
3e6c4538 BH |
676 | BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 || |
677 | FRF_AZ_DRV_EV_DATA_WIDTH != 64); | |
678 | drv_ev_reg.u32[0] = event->u32[0]; | |
679 | drv_ev_reg.u32[1] = event->u32[1]; | |
680 | drv_ev_reg.u32[2] = 0; | |
681 | drv_ev_reg.u32[3] = 0; | |
682 | EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel); | |
12d00cad | 683 | efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV); |
8ceee660 BH |
684 | } |
685 | ||
686 | /* Handle a transmit completion event | |
687 | * | |
688 | * Falcon batches TX completion events; the message we receive is of | |
689 | * the form "complete all TX events up to this index". | |
690 | */ | |
4d566063 BH |
691 | static void falcon_handle_tx_event(struct efx_channel *channel, |
692 | efx_qword_t *event) | |
8ceee660 BH |
693 | { |
694 | unsigned int tx_ev_desc_ptr; | |
695 | unsigned int tx_ev_q_label; | |
696 | struct efx_tx_queue *tx_queue; | |
697 | struct efx_nic *efx = channel->efx; | |
698 | ||
3e6c4538 | 699 | if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) { |
8ceee660 | 700 | /* Transmit completion */ |
3e6c4538 BH |
701 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR); |
702 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); | |
8ceee660 | 703 | tx_queue = &efx->tx_queue[tx_ev_q_label]; |
6fb70fd1 BH |
704 | channel->irq_mod_score += |
705 | (tx_ev_desc_ptr - tx_queue->read_count) & | |
3ffeabdd | 706 | EFX_TXQ_MASK; |
8ceee660 | 707 | efx_xmit_done(tx_queue, tx_ev_desc_ptr); |
3e6c4538 | 708 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) { |
8ceee660 | 709 | /* Rewrite the FIFO write pointer */ |
3e6c4538 | 710 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); |
8ceee660 BH |
711 | tx_queue = &efx->tx_queue[tx_ev_q_label]; |
712 | ||
55668611 | 713 | if (efx_dev_registered(efx)) |
8ceee660 BH |
714 | netif_tx_lock(efx->net_dev); |
715 | falcon_notify_tx_desc(tx_queue); | |
55668611 | 716 | if (efx_dev_registered(efx)) |
8ceee660 | 717 | netif_tx_unlock(efx->net_dev); |
3e6c4538 | 718 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) && |
8ceee660 BH |
719 | EFX_WORKAROUND_10727(efx)) { |
720 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); | |
721 | } else { | |
722 | EFX_ERR(efx, "channel %d unexpected TX event " | |
723 | EFX_QWORD_FMT"\n", channel->channel, | |
724 | EFX_QWORD_VAL(*event)); | |
725 | } | |
726 | } | |
727 | ||
8ceee660 BH |
728 | /* Detect errors included in the rx_evt_pkt_ok bit. */ |
729 | static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue, | |
730 | const efx_qword_t *event, | |
dc8cfa55 BH |
731 | bool *rx_ev_pkt_ok, |
732 | bool *discard) | |
8ceee660 BH |
733 | { |
734 | struct efx_nic *efx = rx_queue->efx; | |
dc8cfa55 BH |
735 | bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err; |
736 | bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err; | |
737 | bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc; | |
738 | bool rx_ev_other_err, rx_ev_pause_frm; | |
739 | bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt; | |
740 | unsigned rx_ev_pkt_type; | |
8ceee660 | 741 | |
3e6c4538 BH |
742 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); |
743 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); | |
744 | rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC); | |
745 | rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE); | |
8ceee660 | 746 | rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event, |
3e6c4538 BH |
747 | FSF_AZ_RX_EV_BUF_OWNER_ID_ERR); |
748 | rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR); | |
8ceee660 | 749 | rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event, |
3e6c4538 | 750 | FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR); |
8ceee660 | 751 | rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event, |
3e6c4538 BH |
752 | FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR); |
753 | rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR); | |
754 | rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC); | |
daeda630 | 755 | rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ? |
3e6c4538 BH |
756 | 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB)); |
757 | rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR); | |
8ceee660 BH |
758 | |
759 | /* Every error apart from tobe_disc and pause_frm */ | |
760 | rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err | | |
761 | rx_ev_buf_owner_id_err | rx_ev_eth_crc_err | | |
762 | rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err); | |
763 | ||
50050877 BH |
764 | /* Count errors that are not in MAC stats. Ignore expected |
765 | * checksum errors during self-test. */ | |
8ceee660 BH |
766 | if (rx_ev_frm_trunc) |
767 | ++rx_queue->channel->n_rx_frm_trunc; | |
768 | else if (rx_ev_tobe_disc) | |
769 | ++rx_queue->channel->n_rx_tobe_disc; | |
50050877 BH |
770 | else if (!efx->loopback_selftest) { |
771 | if (rx_ev_ip_hdr_chksum_err) | |
772 | ++rx_queue->channel->n_rx_ip_hdr_chksum_err; | |
773 | else if (rx_ev_tcp_udp_chksum_err) | |
774 | ++rx_queue->channel->n_rx_tcp_udp_chksum_err; | |
775 | } | |
8ceee660 BH |
776 | if (rx_ev_ip_frag_err) |
777 | ++rx_queue->channel->n_rx_ip_frag_err; | |
778 | ||
779 | /* The frame must be discarded if any of these are true. */ | |
780 | *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib | | |
781 | rx_ev_tobe_disc | rx_ev_pause_frm); | |
782 | ||
783 | /* TOBE_DISC is expected on unicast mismatches; don't print out an | |
784 | * error message. FRM_TRUNC indicates RXDP dropped the packet due | |
785 | * to a FIFO overflow. | |
786 | */ | |
787 | #ifdef EFX_ENABLE_DEBUG | |
788 | if (rx_ev_other_err) { | |
789 | EFX_INFO_RL(efx, " RX queue %d unexpected RX event " | |
5b39fe30 | 790 | EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n", |
8ceee660 BH |
791 | rx_queue->queue, EFX_QWORD_VAL(*event), |
792 | rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "", | |
793 | rx_ev_ip_hdr_chksum_err ? | |
794 | " [IP_HDR_CHKSUM_ERR]" : "", | |
795 | rx_ev_tcp_udp_chksum_err ? | |
796 | " [TCP_UDP_CHKSUM_ERR]" : "", | |
797 | rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "", | |
798 | rx_ev_frm_trunc ? " [FRM_TRUNC]" : "", | |
799 | rx_ev_drib_nib ? " [DRIB_NIB]" : "", | |
800 | rx_ev_tobe_disc ? " [TOBE_DISC]" : "", | |
5b39fe30 | 801 | rx_ev_pause_frm ? " [PAUSE]" : ""); |
8ceee660 BH |
802 | } |
803 | #endif | |
8ceee660 BH |
804 | } |
805 | ||
806 | /* Handle receive events that are not in-order. */ | |
807 | static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue, | |
808 | unsigned index) | |
809 | { | |
810 | struct efx_nic *efx = rx_queue->efx; | |
811 | unsigned expected, dropped; | |
812 | ||
3ffeabdd BH |
813 | expected = rx_queue->removed_count & EFX_RXQ_MASK; |
814 | dropped = (index - expected) & EFX_RXQ_MASK; | |
8ceee660 BH |
815 | EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n", |
816 | dropped, index, expected); | |
817 | ||
818 | efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ? | |
819 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
820 | } | |
821 | ||
822 | /* Handle a packet received event | |
823 | * | |
824 | * Falcon silicon gives a "discard" flag if it's a unicast packet with the | |
825 | * wrong destination address | |
826 | * Also "is multicast" and "matches multicast filter" flags can be used to | |
827 | * discard non-matching multicast packets. | |
828 | */ | |
42cbe2d7 BH |
829 | static void falcon_handle_rx_event(struct efx_channel *channel, |
830 | const efx_qword_t *event) | |
8ceee660 | 831 | { |
42cbe2d7 | 832 | unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt; |
dc8cfa55 | 833 | unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt; |
8ceee660 | 834 | unsigned expected_ptr; |
dc8cfa55 | 835 | bool rx_ev_pkt_ok, discard = false, checksummed; |
8ceee660 BH |
836 | struct efx_rx_queue *rx_queue; |
837 | struct efx_nic *efx = channel->efx; | |
838 | ||
839 | /* Basic packet information */ | |
3e6c4538 BH |
840 | rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT); |
841 | rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK); | |
842 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); | |
843 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT)); | |
844 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1); | |
845 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) != | |
846 | channel->channel); | |
8ceee660 | 847 | |
42cbe2d7 | 848 | rx_queue = &efx->rx_queue[channel->channel]; |
8ceee660 | 849 | |
3e6c4538 | 850 | rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR); |
3ffeabdd | 851 | expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK; |
42cbe2d7 | 852 | if (unlikely(rx_ev_desc_ptr != expected_ptr)) |
8ceee660 | 853 | falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr); |
8ceee660 BH |
854 | |
855 | if (likely(rx_ev_pkt_ok)) { | |
856 | /* If packet is marked as OK and packet type is TCP/IPv4 or | |
857 | * UDP/IPv4, then we can rely on the hardware checksum. | |
858 | */ | |
3e6c4538 | 859 | checksummed = |
9c1bbbaf BH |
860 | efx->rx_checksum_enabled && |
861 | (rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP || | |
862 | rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP); | |
8ceee660 BH |
863 | } else { |
864 | falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, | |
5b39fe30 | 865 | &discard); |
dc8cfa55 | 866 | checksummed = false; |
8ceee660 BH |
867 | } |
868 | ||
869 | /* Detect multicast packets that didn't match the filter */ | |
3e6c4538 | 870 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); |
8ceee660 BH |
871 | if (rx_ev_mcast_pkt) { |
872 | unsigned int rx_ev_mcast_hash_match = | |
3e6c4538 | 873 | EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH); |
8ceee660 BH |
874 | |
875 | if (unlikely(!rx_ev_mcast_hash_match)) | |
dc8cfa55 | 876 | discard = true; |
8ceee660 BH |
877 | } |
878 | ||
6fb70fd1 BH |
879 | channel->irq_mod_score += 2; |
880 | ||
8ceee660 BH |
881 | /* Handle received packet */ |
882 | efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt, | |
883 | checksummed, discard); | |
8ceee660 BH |
884 | } |
885 | ||
886 | /* Global events are basically PHY events */ | |
887 | static void falcon_handle_global_event(struct efx_channel *channel, | |
888 | efx_qword_t *event) | |
889 | { | |
890 | struct efx_nic *efx = channel->efx; | |
766ca0fa | 891 | bool handled = false; |
8ceee660 | 892 | |
3e6c4538 BH |
893 | if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) || |
894 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) || | |
895 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) { | |
fdaa9aed | 896 | /* Ignored */ |
766ca0fa BH |
897 | handled = true; |
898 | } | |
8ceee660 | 899 | |
daeda630 | 900 | if ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) && |
3e6c4538 | 901 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) { |
9007b9fa | 902 | efx->xmac_poll_required = true; |
dc8cfa55 | 903 | handled = true; |
8ceee660 BH |
904 | } |
905 | ||
daeda630 | 906 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? |
3e6c4538 BH |
907 | EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) : |
908 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) { | |
8ceee660 BH |
909 | EFX_ERR(efx, "channel %d seen global RX_RESET " |
910 | "event. Resetting.\n", channel->channel); | |
911 | ||
912 | atomic_inc(&efx->rx_reset); | |
913 | efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ? | |
914 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
dc8cfa55 | 915 | handled = true; |
8ceee660 BH |
916 | } |
917 | ||
918 | if (!handled) | |
919 | EFX_ERR(efx, "channel %d unknown global event " | |
920 | EFX_QWORD_FMT "\n", channel->channel, | |
921 | EFX_QWORD_VAL(*event)); | |
922 | } | |
923 | ||
924 | static void falcon_handle_driver_event(struct efx_channel *channel, | |
925 | efx_qword_t *event) | |
926 | { | |
927 | struct efx_nic *efx = channel->efx; | |
928 | unsigned int ev_sub_code; | |
929 | unsigned int ev_sub_data; | |
930 | ||
3e6c4538 BH |
931 | ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE); |
932 | ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); | |
8ceee660 BH |
933 | |
934 | switch (ev_sub_code) { | |
3e6c4538 | 935 | case FSE_AZ_TX_DESCQ_FLS_DONE_EV: |
8ceee660 BH |
936 | EFX_TRACE(efx, "channel %d TXQ %d flushed\n", |
937 | channel->channel, ev_sub_data); | |
938 | break; | |
3e6c4538 | 939 | case FSE_AZ_RX_DESCQ_FLS_DONE_EV: |
8ceee660 BH |
940 | EFX_TRACE(efx, "channel %d RXQ %d flushed\n", |
941 | channel->channel, ev_sub_data); | |
942 | break; | |
3e6c4538 | 943 | case FSE_AZ_EVQ_INIT_DONE_EV: |
8ceee660 BH |
944 | EFX_LOG(efx, "channel %d EVQ %d initialised\n", |
945 | channel->channel, ev_sub_data); | |
946 | break; | |
3e6c4538 | 947 | case FSE_AZ_SRM_UPD_DONE_EV: |
8ceee660 BH |
948 | EFX_TRACE(efx, "channel %d SRAM update done\n", |
949 | channel->channel); | |
950 | break; | |
3e6c4538 | 951 | case FSE_AZ_WAKE_UP_EV: |
8ceee660 BH |
952 | EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n", |
953 | channel->channel, ev_sub_data); | |
954 | break; | |
3e6c4538 | 955 | case FSE_AZ_TIMER_EV: |
8ceee660 BH |
956 | EFX_TRACE(efx, "channel %d RX queue %d timer expired\n", |
957 | channel->channel, ev_sub_data); | |
958 | break; | |
3e6c4538 | 959 | case FSE_AA_RX_RECOVER_EV: |
8ceee660 BH |
960 | EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. " |
961 | "Resetting.\n", channel->channel); | |
05e3ec04 | 962 | atomic_inc(&efx->rx_reset); |
8ceee660 BH |
963 | efx_schedule_reset(efx, |
964 | EFX_WORKAROUND_6555(efx) ? | |
965 | RESET_TYPE_RX_RECOVERY : | |
966 | RESET_TYPE_DISABLE); | |
967 | break; | |
3e6c4538 | 968 | case FSE_BZ_RX_DSC_ERROR_EV: |
8ceee660 BH |
969 | EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error." |
970 | " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data); | |
971 | efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH); | |
972 | break; | |
3e6c4538 | 973 | case FSE_BZ_TX_DSC_ERROR_EV: |
8ceee660 BH |
974 | EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error." |
975 | " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data); | |
976 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); | |
977 | break; | |
978 | default: | |
979 | EFX_TRACE(efx, "channel %d unknown driver event code %d " | |
980 | "data %04x\n", channel->channel, ev_sub_code, | |
981 | ev_sub_data); | |
982 | break; | |
983 | } | |
984 | } | |
985 | ||
42cbe2d7 | 986 | int falcon_process_eventq(struct efx_channel *channel, int rx_quota) |
8ceee660 BH |
987 | { |
988 | unsigned int read_ptr; | |
989 | efx_qword_t event, *p_event; | |
990 | int ev_code; | |
42cbe2d7 | 991 | int rx_packets = 0; |
8ceee660 BH |
992 | |
993 | read_ptr = channel->eventq_read_ptr; | |
994 | ||
995 | do { | |
996 | p_event = falcon_event(channel, read_ptr); | |
997 | event = *p_event; | |
998 | ||
999 | if (!falcon_event_present(&event)) | |
1000 | /* End of events */ | |
1001 | break; | |
1002 | ||
1003 | EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n", | |
1004 | channel->channel, EFX_QWORD_VAL(event)); | |
1005 | ||
1006 | /* Clear this event by marking it all ones */ | |
1007 | EFX_SET_QWORD(*p_event); | |
1008 | ||
3e6c4538 | 1009 | ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE); |
8ceee660 BH |
1010 | |
1011 | switch (ev_code) { | |
3e6c4538 | 1012 | case FSE_AZ_EV_CODE_RX_EV: |
42cbe2d7 BH |
1013 | falcon_handle_rx_event(channel, &event); |
1014 | ++rx_packets; | |
8ceee660 | 1015 | break; |
3e6c4538 | 1016 | case FSE_AZ_EV_CODE_TX_EV: |
8ceee660 BH |
1017 | falcon_handle_tx_event(channel, &event); |
1018 | break; | |
3e6c4538 BH |
1019 | case FSE_AZ_EV_CODE_DRV_GEN_EV: |
1020 | channel->eventq_magic = EFX_QWORD_FIELD( | |
1021 | event, FSF_AZ_DRV_GEN_EV_MAGIC); | |
8ceee660 BH |
1022 | EFX_LOG(channel->efx, "channel %d received generated " |
1023 | "event "EFX_QWORD_FMT"\n", channel->channel, | |
1024 | EFX_QWORD_VAL(event)); | |
1025 | break; | |
3e6c4538 | 1026 | case FSE_AZ_EV_CODE_GLOBAL_EV: |
8ceee660 BH |
1027 | falcon_handle_global_event(channel, &event); |
1028 | break; | |
3e6c4538 | 1029 | case FSE_AZ_EV_CODE_DRIVER_EV: |
8ceee660 BH |
1030 | falcon_handle_driver_event(channel, &event); |
1031 | break; | |
1032 | default: | |
1033 | EFX_ERR(channel->efx, "channel %d unknown event type %d" | |
1034 | " (data " EFX_QWORD_FMT ")\n", channel->channel, | |
1035 | ev_code, EFX_QWORD_VAL(event)); | |
1036 | } | |
1037 | ||
1038 | /* Increment read pointer */ | |
3ffeabdd | 1039 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; |
8ceee660 | 1040 | |
42cbe2d7 | 1041 | } while (rx_packets < rx_quota); |
8ceee660 BH |
1042 | |
1043 | channel->eventq_read_ptr = read_ptr; | |
42cbe2d7 | 1044 | return rx_packets; |
8ceee660 BH |
1045 | } |
1046 | ||
1047 | void falcon_set_int_moderation(struct efx_channel *channel) | |
1048 | { | |
1049 | efx_dword_t timer_cmd; | |
1050 | struct efx_nic *efx = channel->efx; | |
1051 | ||
1052 | /* Set timer register */ | |
1053 | if (channel->irq_moderation) { | |
8ceee660 | 1054 | EFX_POPULATE_DWORD_2(timer_cmd, |
3e6c4538 BH |
1055 | FRF_AB_TC_TIMER_MODE, |
1056 | FFE_BB_TIMER_MODE_INT_HLDOFF, | |
1057 | FRF_AB_TC_TIMER_VAL, | |
0d86ebd8 | 1058 | channel->irq_moderation - 1); |
8ceee660 BH |
1059 | } else { |
1060 | EFX_POPULATE_DWORD_2(timer_cmd, | |
3e6c4538 BH |
1061 | FRF_AB_TC_TIMER_MODE, |
1062 | FFE_BB_TIMER_MODE_DIS, | |
1063 | FRF_AB_TC_TIMER_VAL, 0); | |
8ceee660 | 1064 | } |
3e6c4538 | 1065 | BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); |
12d00cad BH |
1066 | efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, |
1067 | channel->channel); | |
8ceee660 BH |
1068 | |
1069 | } | |
1070 | ||
1071 | /* Allocate buffer table entries for event queue */ | |
1072 | int falcon_probe_eventq(struct efx_channel *channel) | |
1073 | { | |
1074 | struct efx_nic *efx = channel->efx; | |
3ffeabdd BH |
1075 | BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 || |
1076 | EFX_EVQ_SIZE & EFX_EVQ_MASK); | |
1077 | return falcon_alloc_special_buffer(efx, &channel->eventq, | |
1078 | EFX_EVQ_SIZE * sizeof(efx_qword_t)); | |
8ceee660 BH |
1079 | } |
1080 | ||
bc3c90a2 | 1081 | void falcon_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
1082 | { |
1083 | efx_oword_t evq_ptr; | |
1084 | struct efx_nic *efx = channel->efx; | |
8ceee660 BH |
1085 | |
1086 | EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n", | |
1087 | channel->channel, channel->eventq.index, | |
1088 | channel->eventq.index + channel->eventq.entries - 1); | |
1089 | ||
1090 | /* Pin event queue buffer */ | |
bc3c90a2 | 1091 | falcon_init_special_buffer(efx, &channel->eventq); |
8ceee660 BH |
1092 | |
1093 | /* Fill event queue with all ones (i.e. empty events) */ | |
1094 | memset(channel->eventq.addr, 0xff, channel->eventq.len); | |
1095 | ||
1096 | /* Push event queue to card */ | |
1097 | EFX_POPULATE_OWORD_3(evq_ptr, | |
3e6c4538 | 1098 | FRF_AZ_EVQ_EN, 1, |
3ffeabdd | 1099 | FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries), |
3e6c4538 | 1100 | FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index); |
12d00cad BH |
1101 | efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base, |
1102 | channel->channel); | |
8ceee660 BH |
1103 | |
1104 | falcon_set_int_moderation(channel); | |
8ceee660 BH |
1105 | } |
1106 | ||
1107 | void falcon_fini_eventq(struct efx_channel *channel) | |
1108 | { | |
1109 | efx_oword_t eventq_ptr; | |
1110 | struct efx_nic *efx = channel->efx; | |
1111 | ||
1112 | /* Remove event queue from card */ | |
1113 | EFX_ZERO_OWORD(eventq_ptr); | |
12d00cad BH |
1114 | efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base, |
1115 | channel->channel); | |
8ceee660 BH |
1116 | |
1117 | /* Unpin event queue */ | |
1118 | falcon_fini_special_buffer(efx, &channel->eventq); | |
1119 | } | |
1120 | ||
1121 | /* Free buffers backing event queue */ | |
1122 | void falcon_remove_eventq(struct efx_channel *channel) | |
1123 | { | |
1124 | falcon_free_special_buffer(channel->efx, &channel->eventq); | |
1125 | } | |
1126 | ||
1127 | ||
1128 | /* Generates a test event on the event queue. A subsequent call to | |
1129 | * process_eventq() should pick up the event and place the value of | |
1130 | * "magic" into channel->eventq_magic; | |
1131 | */ | |
1132 | void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic) | |
1133 | { | |
1134 | efx_qword_t test_event; | |
1135 | ||
3e6c4538 BH |
1136 | EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE, |
1137 | FSE_AZ_EV_CODE_DRV_GEN_EV, | |
1138 | FSF_AZ_DRV_GEN_EV_MAGIC, magic); | |
8ceee660 BH |
1139 | falcon_generate_event(channel, &test_event); |
1140 | } | |
1141 | ||
6bc5d3a9 BH |
1142 | /************************************************************************** |
1143 | * | |
1144 | * Flush handling | |
1145 | * | |
1146 | **************************************************************************/ | |
1147 | ||
1148 | ||
1149 | static void falcon_poll_flush_events(struct efx_nic *efx) | |
1150 | { | |
1151 | struct efx_channel *channel = &efx->channel[0]; | |
1152 | struct efx_tx_queue *tx_queue; | |
1153 | struct efx_rx_queue *rx_queue; | |
4720bc6c | 1154 | unsigned int read_ptr = channel->eventq_read_ptr; |
3ffeabdd | 1155 | unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK; |
6bc5d3a9 | 1156 | |
4720bc6c | 1157 | do { |
6bc5d3a9 BH |
1158 | efx_qword_t *event = falcon_event(channel, read_ptr); |
1159 | int ev_code, ev_sub_code, ev_queue; | |
1160 | bool ev_failed; | |
4720bc6c | 1161 | |
6bc5d3a9 BH |
1162 | if (!falcon_event_present(event)) |
1163 | break; | |
1164 | ||
3e6c4538 BH |
1165 | ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE); |
1166 | ev_sub_code = EFX_QWORD_FIELD(*event, | |
1167 | FSF_AZ_DRIVER_EV_SUBCODE); | |
1168 | if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && | |
1169 | ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) { | |
6bc5d3a9 | 1170 | ev_queue = EFX_QWORD_FIELD(*event, |
3e6c4538 | 1171 | FSF_AZ_DRIVER_EV_SUBDATA); |
6bc5d3a9 BH |
1172 | if (ev_queue < EFX_TX_QUEUE_COUNT) { |
1173 | tx_queue = efx->tx_queue + ev_queue; | |
127e6e10 | 1174 | tx_queue->flushed = FLUSH_DONE; |
6bc5d3a9 | 1175 | } |
3e6c4538 BH |
1176 | } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && |
1177 | ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) { | |
1178 | ev_queue = EFX_QWORD_FIELD( | |
1179 | *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); | |
1180 | ev_failed = EFX_QWORD_FIELD( | |
1181 | *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); | |
6bc5d3a9 BH |
1182 | if (ev_queue < efx->n_rx_queues) { |
1183 | rx_queue = efx->rx_queue + ev_queue; | |
127e6e10 BH |
1184 | rx_queue->flushed = |
1185 | ev_failed ? FLUSH_FAILED : FLUSH_DONE; | |
6bc5d3a9 | 1186 | } |
6bc5d3a9 BH |
1187 | } |
1188 | ||
127e6e10 BH |
1189 | /* We're about to destroy the queue anyway, so |
1190 | * it's ok to throw away every non-flush event */ | |
1191 | EFX_SET_QWORD(*event); | |
1192 | ||
3ffeabdd | 1193 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; |
4720bc6c | 1194 | } while (read_ptr != end_ptr); |
127e6e10 BH |
1195 | |
1196 | channel->eventq_read_ptr = read_ptr; | |
1197 | } | |
1198 | ||
1199 | static void falcon_prepare_flush(struct efx_nic *efx) | |
1200 | { | |
1201 | falcon_deconfigure_mac_wrapper(efx); | |
1202 | ||
1203 | /* Wait for the tx and rx fifo's to get to the next packet boundary | |
1204 | * (~1ms without back-pressure), then to drain the remainder of the | |
1205 | * fifo's at data path speeds (negligible), with a healthy margin. */ | |
1206 | msleep(10); | |
6bc5d3a9 BH |
1207 | } |
1208 | ||
1209 | /* Handle tx and rx flushes at the same time, since they run in | |
1210 | * parallel in the hardware and there's no reason for us to | |
1211 | * serialise them */ | |
1212 | int falcon_flush_queues(struct efx_nic *efx) | |
1213 | { | |
1214 | struct efx_rx_queue *rx_queue; | |
1215 | struct efx_tx_queue *tx_queue; | |
127e6e10 | 1216 | int i, tx_pending, rx_pending; |
6bc5d3a9 | 1217 | |
127e6e10 BH |
1218 | falcon_prepare_flush(efx); |
1219 | ||
1220 | /* Flush all tx queues in parallel */ | |
1221 | efx_for_each_tx_queue(tx_queue, efx) | |
6bc5d3a9 | 1222 | falcon_flush_tx_queue(tx_queue); |
6bc5d3a9 | 1223 | |
127e6e10 BH |
1224 | /* The hardware supports four concurrent rx flushes, each of which may |
1225 | * need to be retried if there is an outstanding descriptor fetch */ | |
6bc5d3a9 | 1226 | for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) { |
127e6e10 BH |
1227 | rx_pending = tx_pending = 0; |
1228 | efx_for_each_rx_queue(rx_queue, efx) { | |
1229 | if (rx_queue->flushed == FLUSH_PENDING) | |
1230 | ++rx_pending; | |
1231 | } | |
1232 | efx_for_each_rx_queue(rx_queue, efx) { | |
1233 | if (rx_pending == FALCON_RX_FLUSH_COUNT) | |
1234 | break; | |
1235 | if (rx_queue->flushed == FLUSH_FAILED || | |
1236 | rx_queue->flushed == FLUSH_NONE) { | |
1237 | falcon_flush_rx_queue(rx_queue); | |
1238 | ++rx_pending; | |
1239 | } | |
1240 | } | |
1241 | efx_for_each_tx_queue(tx_queue, efx) { | |
1242 | if (tx_queue->flushed != FLUSH_DONE) | |
1243 | ++tx_pending; | |
1244 | } | |
6bc5d3a9 | 1245 | |
127e6e10 | 1246 | if (rx_pending == 0 && tx_pending == 0) |
6bc5d3a9 | 1247 | return 0; |
127e6e10 BH |
1248 | |
1249 | msleep(FALCON_FLUSH_INTERVAL); | |
1250 | falcon_poll_flush_events(efx); | |
6bc5d3a9 BH |
1251 | } |
1252 | ||
1253 | /* Mark the queues as all flushed. We're going to return failure | |
127e6e10 | 1254 | * leading to a reset, or fake up success anyway */ |
6bc5d3a9 | 1255 | efx_for_each_tx_queue(tx_queue, efx) { |
127e6e10 | 1256 | if (tx_queue->flushed != FLUSH_DONE) |
6bc5d3a9 BH |
1257 | EFX_ERR(efx, "tx queue %d flush command timed out\n", |
1258 | tx_queue->queue); | |
127e6e10 | 1259 | tx_queue->flushed = FLUSH_DONE; |
6bc5d3a9 BH |
1260 | } |
1261 | efx_for_each_rx_queue(rx_queue, efx) { | |
127e6e10 | 1262 | if (rx_queue->flushed != FLUSH_DONE) |
6bc5d3a9 BH |
1263 | EFX_ERR(efx, "rx queue %d flush command timed out\n", |
1264 | rx_queue->queue); | |
127e6e10 | 1265 | rx_queue->flushed = FLUSH_DONE; |
6bc5d3a9 BH |
1266 | } |
1267 | ||
1268 | if (EFX_WORKAROUND_7803(efx)) | |
1269 | return 0; | |
1270 | ||
1271 | return -ETIMEDOUT; | |
1272 | } | |
8ceee660 BH |
1273 | |
1274 | /************************************************************************** | |
1275 | * | |
1276 | * Falcon hardware interrupts | |
1277 | * The hardware interrupt handler does very little work; all the event | |
1278 | * queue processing is carried out by per-channel tasklets. | |
1279 | * | |
1280 | **************************************************************************/ | |
1281 | ||
1282 | /* Enable/disable/generate Falcon interrupts */ | |
1283 | static inline void falcon_interrupts(struct efx_nic *efx, int enabled, | |
1284 | int force) | |
1285 | { | |
1286 | efx_oword_t int_en_reg_ker; | |
1287 | ||
1288 | EFX_POPULATE_OWORD_2(int_en_reg_ker, | |
3e6c4538 BH |
1289 | FRF_AZ_KER_INT_KER, force, |
1290 | FRF_AZ_DRV_INT_EN_KER, enabled); | |
12d00cad | 1291 | efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); |
8ceee660 BH |
1292 | } |
1293 | ||
1294 | void falcon_enable_interrupts(struct efx_nic *efx) | |
1295 | { | |
1296 | efx_oword_t int_adr_reg_ker; | |
1297 | struct efx_channel *channel; | |
1298 | ||
1299 | EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr)); | |
1300 | wmb(); /* Ensure interrupt vector is clear before interrupts enabled */ | |
1301 | ||
1302 | /* Program address */ | |
1303 | EFX_POPULATE_OWORD_2(int_adr_reg_ker, | |
3e6c4538 BH |
1304 | FRF_AZ_NORM_INT_VEC_DIS_KER, |
1305 | EFX_INT_MODE_USE_MSI(efx), | |
1306 | FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); | |
12d00cad | 1307 | efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER); |
8ceee660 BH |
1308 | |
1309 | /* Enable interrupts */ | |
1310 | falcon_interrupts(efx, 1, 0); | |
1311 | ||
1312 | /* Force processing of all the channels to get the EVQ RPTRs up to | |
1313 | date */ | |
64ee3120 | 1314 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1315 | efx_schedule_channel(channel); |
1316 | } | |
1317 | ||
1318 | void falcon_disable_interrupts(struct efx_nic *efx) | |
1319 | { | |
1320 | /* Disable interrupts */ | |
1321 | falcon_interrupts(efx, 0, 0); | |
1322 | } | |
1323 | ||
1324 | /* Generate a Falcon test interrupt | |
1325 | * Interrupt must already have been enabled, otherwise nasty things | |
1326 | * may happen. | |
1327 | */ | |
1328 | void falcon_generate_interrupt(struct efx_nic *efx) | |
1329 | { | |
1330 | falcon_interrupts(efx, 1, 1); | |
1331 | } | |
1332 | ||
1333 | /* Acknowledge a legacy interrupt from Falcon | |
1334 | * | |
1335 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. | |
1336 | * | |
1337 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the | |
1338 | * BIU. Interrupt acknowledge is read sensitive so must write instead | |
1339 | * (then read to ensure the BIU collector is flushed) | |
1340 | * | |
1341 | * NB most hardware supports MSI interrupts | |
1342 | */ | |
1343 | static inline void falcon_irq_ack_a1(struct efx_nic *efx) | |
1344 | { | |
1345 | efx_dword_t reg; | |
1346 | ||
3e6c4538 | 1347 | EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); |
12d00cad BH |
1348 | efx_writed(efx, ®, FR_AA_INT_ACK_KER); |
1349 | efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); | |
8ceee660 BH |
1350 | } |
1351 | ||
1352 | /* Process a fatal interrupt | |
1353 | * Disable bus mastering ASAP and schedule a reset | |
1354 | */ | |
1355 | static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx) | |
1356 | { | |
1357 | struct falcon_nic_data *nic_data = efx->nic_data; | |
d3208b5e | 1358 | efx_oword_t *int_ker = efx->irq_status.addr; |
8ceee660 BH |
1359 | efx_oword_t fatal_intr; |
1360 | int error, mem_perr; | |
8ceee660 | 1361 | |
12d00cad | 1362 | efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER); |
3e6c4538 | 1363 | error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR); |
8ceee660 BH |
1364 | |
1365 | EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status " | |
1366 | EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), | |
1367 | EFX_OWORD_VAL(fatal_intr), | |
1368 | error ? "disabling bus mastering" : "no recognised error"); | |
1369 | if (error == 0) | |
1370 | goto out; | |
1371 | ||
1372 | /* If this is a memory parity error dump which blocks are offending */ | |
3e6c4538 | 1373 | mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER); |
8ceee660 BH |
1374 | if (mem_perr) { |
1375 | efx_oword_t reg; | |
12d00cad | 1376 | efx_reado(efx, ®, FR_AZ_MEM_STAT); |
8ceee660 BH |
1377 | EFX_ERR(efx, "SYSTEM ERROR: memory parity error " |
1378 | EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg)); | |
1379 | } | |
1380 | ||
0a62f1a6 | 1381 | /* Disable both devices */ |
ef1bba28 | 1382 | pci_clear_master(efx->pci_dev); |
8ceee660 | 1383 | if (FALCON_IS_DUAL_FUNC(efx)) |
ef1bba28 | 1384 | pci_clear_master(nic_data->pci_dev2); |
0a62f1a6 | 1385 | falcon_disable_interrupts(efx); |
8ceee660 | 1386 | |
2c3c3d02 | 1387 | /* Count errors and reset or disable the NIC accordingly */ |
0484e0db BH |
1388 | if (efx->int_error_count == 0 || |
1389 | time_after(jiffies, efx->int_error_expire)) { | |
1390 | efx->int_error_count = 0; | |
1391 | efx->int_error_expire = | |
2c3c3d02 BH |
1392 | jiffies + FALCON_INT_ERROR_EXPIRE * HZ; |
1393 | } | |
0484e0db | 1394 | if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) { |
8ceee660 BH |
1395 | EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n"); |
1396 | efx_schedule_reset(efx, RESET_TYPE_INT_ERROR); | |
1397 | } else { | |
1398 | EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen." | |
1399 | "NIC will be disabled\n"); | |
1400 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1401 | } | |
1402 | out: | |
1403 | return IRQ_HANDLED; | |
1404 | } | |
1405 | ||
1406 | /* Handle a legacy interrupt from Falcon | |
1407 | * Acknowledges the interrupt and schedule event queue processing. | |
1408 | */ | |
1409 | static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id) | |
1410 | { | |
d3208b5e BH |
1411 | struct efx_nic *efx = dev_id; |
1412 | efx_oword_t *int_ker = efx->irq_status.addr; | |
a9de9a74 | 1413 | irqreturn_t result = IRQ_NONE; |
8ceee660 BH |
1414 | struct efx_channel *channel; |
1415 | efx_dword_t reg; | |
1416 | u32 queues; | |
1417 | int syserr; | |
1418 | ||
1419 | /* Read the ISR which also ACKs the interrupts */ | |
12d00cad | 1420 | efx_readd(efx, ®, FR_BZ_INT_ISR0); |
8ceee660 BH |
1421 | queues = EFX_EXTRACT_DWORD(reg, 0, 31); |
1422 | ||
1423 | /* Check to see if we have a serious error condition */ | |
3e6c4538 | 1424 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
8ceee660 BH |
1425 | if (unlikely(syserr)) |
1426 | return falcon_fatal_interrupt(efx); | |
1427 | ||
8ceee660 | 1428 | /* Schedule processing of any interrupting queues */ |
a9de9a74 BH |
1429 | efx_for_each_channel(channel, efx) { |
1430 | if ((queues & 1) || | |
1431 | falcon_event_present( | |
1432 | falcon_event(channel, channel->eventq_read_ptr))) { | |
8ceee660 | 1433 | efx_schedule_channel(channel); |
a9de9a74 BH |
1434 | result = IRQ_HANDLED; |
1435 | } | |
8ceee660 BH |
1436 | queues >>= 1; |
1437 | } | |
1438 | ||
a9de9a74 BH |
1439 | if (result == IRQ_HANDLED) { |
1440 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1441 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", | |
1442 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); | |
1443 | } | |
1444 | ||
1445 | return result; | |
8ceee660 BH |
1446 | } |
1447 | ||
1448 | ||
1449 | static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) | |
1450 | { | |
d3208b5e BH |
1451 | struct efx_nic *efx = dev_id; |
1452 | efx_oword_t *int_ker = efx->irq_status.addr; | |
8ceee660 BH |
1453 | struct efx_channel *channel; |
1454 | int syserr; | |
1455 | int queues; | |
1456 | ||
1457 | /* Check to see if this is our interrupt. If it isn't, we | |
1458 | * exit without having touched the hardware. | |
1459 | */ | |
1460 | if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { | |
1461 | EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq, | |
1462 | raw_smp_processor_id()); | |
1463 | return IRQ_NONE; | |
1464 | } | |
1465 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1466 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
1467 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
1468 | ||
1469 | /* Check to see if we have a serious error condition */ | |
3e6c4538 | 1470 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
8ceee660 BH |
1471 | if (unlikely(syserr)) |
1472 | return falcon_fatal_interrupt(efx); | |
1473 | ||
1474 | /* Determine interrupting queues, clear interrupt status | |
1475 | * register and acknowledge the device interrupt. | |
1476 | */ | |
1477 | BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS); | |
1478 | queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS); | |
1479 | EFX_ZERO_OWORD(*int_ker); | |
1480 | wmb(); /* Ensure the vector is cleared before interrupt ack */ | |
1481 | falcon_irq_ack_a1(efx); | |
1482 | ||
1483 | /* Schedule processing of any interrupting queues */ | |
1484 | channel = &efx->channel[0]; | |
1485 | while (queues) { | |
1486 | if (queues & 0x01) | |
1487 | efx_schedule_channel(channel); | |
1488 | channel++; | |
1489 | queues >>= 1; | |
1490 | } | |
1491 | ||
1492 | return IRQ_HANDLED; | |
1493 | } | |
1494 | ||
1495 | /* Handle an MSI interrupt from Falcon | |
1496 | * | |
1497 | * Handle an MSI hardware interrupt. This routine schedules event | |
1498 | * queue processing. No interrupt acknowledgement cycle is necessary. | |
1499 | * Also, we never need to check that the interrupt is for us, since | |
1500 | * MSI interrupts cannot be shared. | |
1501 | */ | |
1502 | static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id) | |
1503 | { | |
d3208b5e | 1504 | struct efx_channel *channel = dev_id; |
8ceee660 | 1505 | struct efx_nic *efx = channel->efx; |
d3208b5e | 1506 | efx_oword_t *int_ker = efx->irq_status.addr; |
8ceee660 BH |
1507 | int syserr; |
1508 | ||
1509 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1510 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
1511 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
1512 | ||
1513 | /* Check to see if we have a serious error condition */ | |
1514 | syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT); | |
1515 | if (unlikely(syserr)) | |
1516 | return falcon_fatal_interrupt(efx); | |
1517 | ||
1518 | /* Schedule processing of the channel */ | |
1519 | efx_schedule_channel(channel); | |
1520 | ||
1521 | return IRQ_HANDLED; | |
1522 | } | |
1523 | ||
1524 | ||
1525 | /* Setup RSS indirection table. | |
1526 | * This maps from the hash value of the packet to RXQ | |
1527 | */ | |
1528 | static void falcon_setup_rss_indir_table(struct efx_nic *efx) | |
1529 | { | |
1530 | int i = 0; | |
1531 | unsigned long offset; | |
1532 | efx_dword_t dword; | |
1533 | ||
daeda630 | 1534 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) |
8ceee660 BH |
1535 | return; |
1536 | ||
3e6c4538 BH |
1537 | for (offset = FR_BZ_RX_INDIRECTION_TBL; |
1538 | offset < FR_BZ_RX_INDIRECTION_TBL + 0x800; | |
8ceee660 | 1539 | offset += 0x10) { |
3e6c4538 | 1540 | EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, |
8831da7b | 1541 | i % efx->n_rx_queues); |
12d00cad | 1542 | efx_writed(efx, &dword, offset); |
8ceee660 BH |
1543 | i++; |
1544 | } | |
1545 | } | |
1546 | ||
1547 | /* Hook interrupt handler(s) | |
1548 | * Try MSI and then legacy interrupts. | |
1549 | */ | |
1550 | int falcon_init_interrupt(struct efx_nic *efx) | |
1551 | { | |
1552 | struct efx_channel *channel; | |
1553 | int rc; | |
1554 | ||
1555 | if (!EFX_INT_MODE_USE_MSI(efx)) { | |
1556 | irq_handler_t handler; | |
daeda630 | 1557 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
8ceee660 BH |
1558 | handler = falcon_legacy_interrupt_b0; |
1559 | else | |
1560 | handler = falcon_legacy_interrupt_a1; | |
1561 | ||
1562 | rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED, | |
1563 | efx->name, efx); | |
1564 | if (rc) { | |
1565 | EFX_ERR(efx, "failed to hook legacy IRQ %d\n", | |
1566 | efx->pci_dev->irq); | |
1567 | goto fail1; | |
1568 | } | |
1569 | return 0; | |
1570 | } | |
1571 | ||
1572 | /* Hook MSI or MSI-X interrupt */ | |
64ee3120 | 1573 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1574 | rc = request_irq(channel->irq, falcon_msi_interrupt, |
1575 | IRQF_PROBE_SHARED, /* Not shared */ | |
56536e9c | 1576 | channel->name, channel); |
8ceee660 BH |
1577 | if (rc) { |
1578 | EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq); | |
1579 | goto fail2; | |
1580 | } | |
1581 | } | |
1582 | ||
1583 | return 0; | |
1584 | ||
1585 | fail2: | |
64ee3120 | 1586 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1587 | free_irq(channel->irq, channel); |
1588 | fail1: | |
1589 | return rc; | |
1590 | } | |
1591 | ||
1592 | void falcon_fini_interrupt(struct efx_nic *efx) | |
1593 | { | |
1594 | struct efx_channel *channel; | |
1595 | efx_oword_t reg; | |
1596 | ||
1597 | /* Disable MSI/MSI-X interrupts */ | |
64ee3120 | 1598 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1599 | if (channel->irq) |
1600 | free_irq(channel->irq, channel); | |
b3475645 | 1601 | } |
8ceee660 BH |
1602 | |
1603 | /* ACK legacy interrupt */ | |
daeda630 | 1604 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
12d00cad | 1605 | efx_reado(efx, ®, FR_BZ_INT_ISR0); |
8ceee660 BH |
1606 | else |
1607 | falcon_irq_ack_a1(efx); | |
1608 | ||
1609 | /* Disable legacy interrupt */ | |
1610 | if (efx->legacy_irq) | |
1611 | free_irq(efx->legacy_irq, efx); | |
1612 | } | |
1613 | ||
1614 | /************************************************************************** | |
1615 | * | |
1616 | * EEPROM/flash | |
1617 | * | |
1618 | ************************************************************************** | |
1619 | */ | |
1620 | ||
23d30f02 | 1621 | #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) |
8ceee660 | 1622 | |
be4ea89c BH |
1623 | static int falcon_spi_poll(struct efx_nic *efx) |
1624 | { | |
1625 | efx_oword_t reg; | |
12d00cad | 1626 | efx_reado(efx, ®, FR_AB_EE_SPI_HCMD); |
3e6c4538 | 1627 | return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; |
be4ea89c BH |
1628 | } |
1629 | ||
8ceee660 BH |
1630 | /* Wait for SPI command completion */ |
1631 | static int falcon_spi_wait(struct efx_nic *efx) | |
1632 | { | |
be4ea89c BH |
1633 | /* Most commands will finish quickly, so we start polling at |
1634 | * very short intervals. Sometimes the command may have to | |
1635 | * wait for VPD or expansion ROM access outside of our | |
1636 | * control, so we allow up to 100 ms. */ | |
1637 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); | |
1638 | int i; | |
1639 | ||
1640 | for (i = 0; i < 10; i++) { | |
1641 | if (!falcon_spi_poll(efx)) | |
1642 | return 0; | |
1643 | udelay(10); | |
1644 | } | |
8ceee660 | 1645 | |
4a5b504d | 1646 | for (;;) { |
be4ea89c | 1647 | if (!falcon_spi_poll(efx)) |
8ceee660 | 1648 | return 0; |
4a5b504d BH |
1649 | if (time_after_eq(jiffies, timeout)) { |
1650 | EFX_ERR(efx, "timed out waiting for SPI\n"); | |
1651 | return -ETIMEDOUT; | |
1652 | } | |
be4ea89c | 1653 | schedule_timeout_uninterruptible(1); |
4a5b504d | 1654 | } |
8ceee660 BH |
1655 | } |
1656 | ||
f4150724 BH |
1657 | int falcon_spi_cmd(const struct efx_spi_device *spi, |
1658 | unsigned int command, int address, | |
23d30f02 | 1659 | const void *in, void *out, size_t len) |
8ceee660 | 1660 | { |
4a5b504d BH |
1661 | struct efx_nic *efx = spi->efx; |
1662 | bool addressed = (address >= 0); | |
1663 | bool reading = (out != NULL); | |
8ceee660 BH |
1664 | efx_oword_t reg; |
1665 | int rc; | |
1666 | ||
4a5b504d BH |
1667 | /* Input validation */ |
1668 | if (len > FALCON_SPI_MAX_LEN) | |
1669 | return -EINVAL; | |
f4150724 | 1670 | BUG_ON(!mutex_is_locked(&efx->spi_lock)); |
8ceee660 | 1671 | |
be4ea89c BH |
1672 | /* Check that previous command is not still running */ |
1673 | rc = falcon_spi_poll(efx); | |
8ceee660 BH |
1674 | if (rc) |
1675 | return rc; | |
1676 | ||
4a5b504d BH |
1677 | /* Program address register, if we have an address */ |
1678 | if (addressed) { | |
3e6c4538 | 1679 | EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); |
12d00cad | 1680 | efx_writeo(efx, ®, FR_AB_EE_SPI_HADR); |
4a5b504d BH |
1681 | } |
1682 | ||
1683 | /* Program data register, if we have data */ | |
1684 | if (in != NULL) { | |
1685 | memcpy(®, in, len); | |
12d00cad | 1686 | efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d | 1687 | } |
8ceee660 | 1688 | |
4a5b504d | 1689 | /* Issue read/write command */ |
8ceee660 | 1690 | EFX_POPULATE_OWORD_7(reg, |
3e6c4538 BH |
1691 | FRF_AB_EE_SPI_HCMD_CMD_EN, 1, |
1692 | FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, | |
1693 | FRF_AB_EE_SPI_HCMD_DABCNT, len, | |
1694 | FRF_AB_EE_SPI_HCMD_READ, reading, | |
1695 | FRF_AB_EE_SPI_HCMD_DUBCNT, 0, | |
1696 | FRF_AB_EE_SPI_HCMD_ADBCNT, | |
4a5b504d | 1697 | (addressed ? spi->addr_len : 0), |
3e6c4538 | 1698 | FRF_AB_EE_SPI_HCMD_ENC, command); |
12d00cad | 1699 | efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD); |
8ceee660 | 1700 | |
4a5b504d | 1701 | /* Wait for read/write to complete */ |
8ceee660 BH |
1702 | rc = falcon_spi_wait(efx); |
1703 | if (rc) | |
1704 | return rc; | |
1705 | ||
1706 | /* Read data */ | |
4a5b504d | 1707 | if (out != NULL) { |
12d00cad | 1708 | efx_reado(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d BH |
1709 | memcpy(out, ®, len); |
1710 | } | |
1711 | ||
8ceee660 BH |
1712 | return 0; |
1713 | } | |
1714 | ||
23d30f02 BH |
1715 | static size_t |
1716 | falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start) | |
4a5b504d BH |
1717 | { |
1718 | return min(FALCON_SPI_MAX_LEN, | |
1719 | (spi->block_size - (start & (spi->block_size - 1)))); | |
1720 | } | |
1721 | ||
1722 | static inline u8 | |
1723 | efx_spi_munge_command(const struct efx_spi_device *spi, | |
1724 | const u8 command, const unsigned int address) | |
1725 | { | |
1726 | return command | (((address >> 8) & spi->munge_address) << 3); | |
1727 | } | |
1728 | ||
be4ea89c BH |
1729 | /* Wait up to 10 ms for buffered write completion */ |
1730 | int falcon_spi_wait_write(const struct efx_spi_device *spi) | |
4a5b504d | 1731 | { |
be4ea89c BH |
1732 | struct efx_nic *efx = spi->efx; |
1733 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); | |
4a5b504d | 1734 | u8 status; |
be4ea89c | 1735 | int rc; |
4a5b504d | 1736 | |
be4ea89c | 1737 | for (;;) { |
4a5b504d BH |
1738 | rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL, |
1739 | &status, sizeof(status)); | |
1740 | if (rc) | |
1741 | return rc; | |
1742 | if (!(status & SPI_STATUS_NRDY)) | |
1743 | return 0; | |
be4ea89c BH |
1744 | if (time_after_eq(jiffies, timeout)) { |
1745 | EFX_ERR(efx, "SPI write timeout on device %d" | |
1746 | " last status=0x%02x\n", | |
1747 | spi->device_id, status); | |
1748 | return -ETIMEDOUT; | |
1749 | } | |
1750 | schedule_timeout_uninterruptible(1); | |
4a5b504d | 1751 | } |
4a5b504d BH |
1752 | } |
1753 | ||
1754 | int falcon_spi_read(const struct efx_spi_device *spi, loff_t start, | |
1755 | size_t len, size_t *retlen, u8 *buffer) | |
1756 | { | |
23d30f02 BH |
1757 | size_t block_len, pos = 0; |
1758 | unsigned int command; | |
4a5b504d BH |
1759 | int rc = 0; |
1760 | ||
1761 | while (pos < len) { | |
23d30f02 | 1762 | block_len = min(len - pos, FALCON_SPI_MAX_LEN); |
4a5b504d BH |
1763 | |
1764 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
1765 | rc = falcon_spi_cmd(spi, command, start + pos, NULL, | |
1766 | buffer + pos, block_len); | |
1767 | if (rc) | |
1768 | break; | |
1769 | pos += block_len; | |
1770 | ||
1771 | /* Avoid locking up the system */ | |
1772 | cond_resched(); | |
1773 | if (signal_pending(current)) { | |
1774 | rc = -EINTR; | |
1775 | break; | |
1776 | } | |
1777 | } | |
1778 | ||
1779 | if (retlen) | |
1780 | *retlen = pos; | |
1781 | return rc; | |
1782 | } | |
1783 | ||
1784 | int falcon_spi_write(const struct efx_spi_device *spi, loff_t start, | |
1785 | size_t len, size_t *retlen, const u8 *buffer) | |
1786 | { | |
1787 | u8 verify_buffer[FALCON_SPI_MAX_LEN]; | |
23d30f02 BH |
1788 | size_t block_len, pos = 0; |
1789 | unsigned int command; | |
4a5b504d BH |
1790 | int rc = 0; |
1791 | ||
1792 | while (pos < len) { | |
1793 | rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0); | |
1794 | if (rc) | |
1795 | break; | |
1796 | ||
23d30f02 | 1797 | block_len = min(len - pos, |
4a5b504d BH |
1798 | falcon_spi_write_limit(spi, start + pos)); |
1799 | command = efx_spi_munge_command(spi, SPI_WRITE, start + pos); | |
1800 | rc = falcon_spi_cmd(spi, command, start + pos, | |
1801 | buffer + pos, NULL, block_len); | |
1802 | if (rc) | |
1803 | break; | |
1804 | ||
be4ea89c | 1805 | rc = falcon_spi_wait_write(spi); |
4a5b504d BH |
1806 | if (rc) |
1807 | break; | |
1808 | ||
1809 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
1810 | rc = falcon_spi_cmd(spi, command, start + pos, | |
1811 | NULL, verify_buffer, block_len); | |
1812 | if (memcmp(verify_buffer, buffer + pos, block_len)) { | |
1813 | rc = -EIO; | |
1814 | break; | |
1815 | } | |
1816 | ||
1817 | pos += block_len; | |
1818 | ||
1819 | /* Avoid locking up the system */ | |
1820 | cond_resched(); | |
1821 | if (signal_pending(current)) { | |
1822 | rc = -EINTR; | |
1823 | break; | |
1824 | } | |
1825 | } | |
1826 | ||
1827 | if (retlen) | |
1828 | *retlen = pos; | |
1829 | return rc; | |
1830 | } | |
1831 | ||
8ceee660 BH |
1832 | /************************************************************************** |
1833 | * | |
1834 | * MAC wrapper | |
1835 | * | |
1836 | ************************************************************************** | |
1837 | */ | |
177dfcd8 BH |
1838 | |
1839 | static int falcon_reset_macs(struct efx_nic *efx) | |
8ceee660 | 1840 | { |
177dfcd8 | 1841 | efx_oword_t reg; |
8ceee660 BH |
1842 | int count; |
1843 | ||
daeda630 | 1844 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { |
177dfcd8 BH |
1845 | /* It's not safe to use GLB_CTL_REG to reset the |
1846 | * macs, so instead use the internal MAC resets | |
1847 | */ | |
1848 | if (!EFX_IS10G(efx)) { | |
3e6c4538 | 1849 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1); |
12d00cad | 1850 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
177dfcd8 BH |
1851 | udelay(1000); |
1852 | ||
3e6c4538 | 1853 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0); |
12d00cad | 1854 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
177dfcd8 BH |
1855 | udelay(1000); |
1856 | return 0; | |
1857 | } else { | |
3e6c4538 | 1858 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); |
12d00cad | 1859 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); |
177dfcd8 BH |
1860 | |
1861 | for (count = 0; count < 10000; count++) { | |
12d00cad | 1862 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); |
3e6c4538 BH |
1863 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == |
1864 | 0) | |
177dfcd8 BH |
1865 | return 0; |
1866 | udelay(10); | |
1867 | } | |
8ceee660 | 1868 | |
177dfcd8 BH |
1869 | EFX_ERR(efx, "timed out waiting for XMAC core reset\n"); |
1870 | return -ETIMEDOUT; | |
1871 | } | |
1872 | } | |
8ceee660 BH |
1873 | |
1874 | /* MAC stats will fail whilst the TX fifo is draining. Serialise | |
1875 | * the drain sequence with the statistics fetch */ | |
55edc6e6 | 1876 | falcon_stop_nic_stats(efx); |
8ceee660 | 1877 | |
12d00cad | 1878 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
3e6c4538 | 1879 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1); |
12d00cad | 1880 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
8ceee660 | 1881 | |
12d00cad | 1882 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
1883 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); |
1884 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); | |
1885 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); | |
12d00cad | 1886 | efx_writeo(efx, ®, FR_AB_GLB_CTL); |
8ceee660 BH |
1887 | |
1888 | count = 0; | |
1889 | while (1) { | |
12d00cad | 1890 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
1891 | if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && |
1892 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && | |
1893 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { | |
8ceee660 BH |
1894 | EFX_LOG(efx, "Completed MAC reset after %d loops\n", |
1895 | count); | |
1896 | break; | |
1897 | } | |
1898 | if (count > 20) { | |
1899 | EFX_ERR(efx, "MAC reset failed\n"); | |
1900 | break; | |
1901 | } | |
1902 | count++; | |
1903 | udelay(10); | |
1904 | } | |
1905 | ||
8ceee660 BH |
1906 | /* If we've reset the EM block and the link is up, then |
1907 | * we'll have to kick the XAUI link so the PHY can recover */ | |
eb50c0d6 | 1908 | if (efx->link_state.up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx)) |
8ceee660 | 1909 | falcon_reset_xaui(efx); |
177dfcd8 | 1910 | |
55edc6e6 BH |
1911 | falcon_start_nic_stats(efx); |
1912 | ||
177dfcd8 BH |
1913 | return 0; |
1914 | } | |
1915 | ||
1916 | void falcon_drain_tx_fifo(struct efx_nic *efx) | |
1917 | { | |
1918 | efx_oword_t reg; | |
1919 | ||
daeda630 | 1920 | if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) || |
177dfcd8 BH |
1921 | (efx->loopback_mode != LOOPBACK_NONE)) |
1922 | return; | |
1923 | ||
12d00cad | 1924 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
177dfcd8 | 1925 | /* There is no point in draining more than once */ |
3e6c4538 | 1926 | if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) |
177dfcd8 BH |
1927 | return; |
1928 | ||
1929 | falcon_reset_macs(efx); | |
8ceee660 BH |
1930 | } |
1931 | ||
1932 | void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) | |
1933 | { | |
177dfcd8 | 1934 | efx_oword_t reg; |
8ceee660 | 1935 | |
daeda630 | 1936 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) |
8ceee660 BH |
1937 | return; |
1938 | ||
1939 | /* Isolate the MAC -> RX */ | |
12d00cad | 1940 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
3e6c4538 | 1941 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); |
12d00cad | 1942 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 | 1943 | |
eb50c0d6 | 1944 | if (!efx->link_state.up) |
8ceee660 BH |
1945 | falcon_drain_tx_fifo(efx); |
1946 | } | |
1947 | ||
1948 | void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) | |
1949 | { | |
eb50c0d6 | 1950 | struct efx_link_state *link_state = &efx->link_state; |
8ceee660 BH |
1951 | efx_oword_t reg; |
1952 | int link_speed; | |
dc8cfa55 | 1953 | bool tx_fc; |
8ceee660 | 1954 | |
eb50c0d6 | 1955 | switch (link_state->speed) { |
f31a45d2 BH |
1956 | case 10000: link_speed = 3; break; |
1957 | case 1000: link_speed = 2; break; | |
1958 | case 100: link_speed = 1; break; | |
1959 | default: link_speed = 0; break; | |
1960 | } | |
8ceee660 BH |
1961 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work |
1962 | * as advertised. Disable to ensure packets are not | |
1963 | * indefinitely held and TX queue can be flushed at any point | |
1964 | * while the link is down. */ | |
1965 | EFX_POPULATE_OWORD_5(reg, | |
3e6c4538 BH |
1966 | FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, |
1967 | FRF_AB_MAC_BCAD_ACPT, 1, | |
1968 | FRF_AB_MAC_UC_PROM, efx->promiscuous, | |
1969 | FRF_AB_MAC_LINK_STATUS, 1, /* always set */ | |
1970 | FRF_AB_MAC_SPEED, link_speed); | |
8ceee660 BH |
1971 | /* On B0, MAC backpressure can be disabled and packets get |
1972 | * discarded. */ | |
daeda630 | 1973 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
3e6c4538 | 1974 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, |
eb50c0d6 | 1975 | !link_state->up); |
8ceee660 BH |
1976 | } |
1977 | ||
12d00cad | 1978 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
8ceee660 BH |
1979 | |
1980 | /* Restore the multicast hash registers. */ | |
8be4f3e6 | 1981 | falcon_push_multicast_hash(efx); |
8ceee660 BH |
1982 | |
1983 | /* Transmission of pause frames when RX crosses the threshold is | |
1984 | * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL. | |
1985 | * Action on receipt of pause frames is controller by XM_DIS_FCNTL */ | |
eb50c0d6 | 1986 | tx_fc = !!(efx->link_state.fc & EFX_FC_TX); |
12d00cad | 1987 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
3e6c4538 | 1988 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc); |
8ceee660 BH |
1989 | |
1990 | /* Unisolate the MAC -> RX */ | |
daeda630 | 1991 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
3e6c4538 | 1992 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); |
12d00cad | 1993 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 BH |
1994 | } |
1995 | ||
55edc6e6 | 1996 | static void falcon_stats_request(struct efx_nic *efx) |
8ceee660 | 1997 | { |
55edc6e6 | 1998 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 1999 | efx_oword_t reg; |
8ceee660 | 2000 | |
55edc6e6 BH |
2001 | WARN_ON(nic_data->stats_pending); |
2002 | WARN_ON(nic_data->stats_disable_count); | |
8ceee660 | 2003 | |
55edc6e6 BH |
2004 | if (nic_data->stats_dma_done == NULL) |
2005 | return; /* no mac selected */ | |
8ceee660 | 2006 | |
55edc6e6 BH |
2007 | *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE; |
2008 | nic_data->stats_pending = true; | |
8ceee660 BH |
2009 | wmb(); /* ensure done flag is clear */ |
2010 | ||
2011 | /* Initiate DMA transfer of stats */ | |
2012 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2013 | FRF_AB_MAC_STAT_DMA_CMD, 1, |
2014 | FRF_AB_MAC_STAT_DMA_ADR, | |
8ceee660 | 2015 | efx->stats_buffer.dma_addr); |
12d00cad | 2016 | efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA); |
8ceee660 | 2017 | |
55edc6e6 BH |
2018 | mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2)); |
2019 | } | |
2020 | ||
2021 | static void falcon_stats_complete(struct efx_nic *efx) | |
2022 | { | |
2023 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2024 | ||
2025 | if (!nic_data->stats_pending) | |
2026 | return; | |
2027 | ||
2028 | nic_data->stats_pending = 0; | |
2029 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) { | |
2030 | rmb(); /* read the done flag before the stats */ | |
2031 | efx->mac_op->update_stats(efx); | |
2032 | } else { | |
2033 | EFX_ERR(efx, "timed out waiting for statistics\n"); | |
8ceee660 | 2034 | } |
55edc6e6 | 2035 | } |
8ceee660 | 2036 | |
55edc6e6 BH |
2037 | static void falcon_stats_timer_func(unsigned long context) |
2038 | { | |
2039 | struct efx_nic *efx = (struct efx_nic *)context; | |
2040 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2041 | ||
2042 | spin_lock(&efx->stats_lock); | |
2043 | ||
2044 | falcon_stats_complete(efx); | |
2045 | if (nic_data->stats_disable_count == 0) | |
2046 | falcon_stats_request(efx); | |
2047 | ||
2048 | spin_unlock(&efx->stats_lock); | |
8ceee660 BH |
2049 | } |
2050 | ||
fdaa9aed SH |
2051 | static bool falcon_loopback_link_poll(struct efx_nic *efx) |
2052 | { | |
2053 | struct efx_link_state old_state = efx->link_state; | |
2054 | ||
2055 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
2056 | WARN_ON(!LOOPBACK_INTERNAL(efx)); | |
2057 | ||
2058 | efx->link_state.fd = true; | |
2059 | efx->link_state.fc = efx->wanted_fc; | |
2060 | efx->link_state.up = true; | |
2061 | ||
2062 | if (efx->loopback_mode == LOOPBACK_GMAC) | |
2063 | efx->link_state.speed = 1000; | |
2064 | else | |
2065 | efx->link_state.speed = 10000; | |
2066 | ||
2067 | return !efx_link_state_equal(&efx->link_state, &old_state); | |
2068 | } | |
2069 | ||
8ceee660 BH |
2070 | /************************************************************************** |
2071 | * | |
2072 | * PHY access via GMII | |
2073 | * | |
2074 | ************************************************************************** | |
2075 | */ | |
2076 | ||
8ceee660 BH |
2077 | /* Wait for GMII access to complete */ |
2078 | static int falcon_gmii_wait(struct efx_nic *efx) | |
2079 | { | |
80cb9a0f | 2080 | efx_oword_t md_stat; |
8ceee660 BH |
2081 | int count; |
2082 | ||
177dfcd8 BH |
2083 | /* wait upto 50ms - taken max from datasheet */ |
2084 | for (count = 0; count < 5000; count++) { | |
80cb9a0f BH |
2085 | efx_reado(efx, &md_stat, FR_AB_MD_STAT); |
2086 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { | |
2087 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || | |
2088 | EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { | |
8ceee660 | 2089 | EFX_ERR(efx, "error from GMII access " |
80cb9a0f BH |
2090 | EFX_OWORD_FMT"\n", |
2091 | EFX_OWORD_VAL(md_stat)); | |
8ceee660 BH |
2092 | return -EIO; |
2093 | } | |
2094 | return 0; | |
2095 | } | |
2096 | udelay(10); | |
2097 | } | |
2098 | EFX_ERR(efx, "timed out waiting for GMII\n"); | |
2099 | return -ETIMEDOUT; | |
2100 | } | |
2101 | ||
68e7f45e BH |
2102 | /* Write an MDIO register of a PHY connected to Falcon. */ |
2103 | static int falcon_mdio_write(struct net_device *net_dev, | |
2104 | int prtad, int devad, u16 addr, u16 value) | |
8ceee660 | 2105 | { |
767e468c | 2106 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2107 | efx_oword_t reg; |
68e7f45e | 2108 | int rc; |
8ceee660 | 2109 | |
68e7f45e BH |
2110 | EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n", |
2111 | prtad, devad, addr, value); | |
8ceee660 | 2112 | |
ab867461 | 2113 | mutex_lock(&efx->mdio_lock); |
8ceee660 | 2114 | |
68e7f45e BH |
2115 | /* Check MDIO not currently being accessed */ |
2116 | rc = falcon_gmii_wait(efx); | |
2117 | if (rc) | |
8ceee660 BH |
2118 | goto out; |
2119 | ||
2120 | /* Write the address/ID register */ | |
3e6c4538 | 2121 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 2122 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 2123 | |
3e6c4538 BH |
2124 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
2125 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 2126 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
2127 | |
2128 | /* Write data */ | |
3e6c4538 | 2129 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); |
12d00cad | 2130 | efx_writeo(efx, ®, FR_AB_MD_TXD); |
8ceee660 BH |
2131 | |
2132 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2133 | FRF_AB_MD_WRC, 1, |
2134 | FRF_AB_MD_GC, 0); | |
12d00cad | 2135 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2136 | |
2137 | /* Wait for data to be written */ | |
68e7f45e BH |
2138 | rc = falcon_gmii_wait(efx); |
2139 | if (rc) { | |
8ceee660 BH |
2140 | /* Abort the write operation */ |
2141 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2142 | FRF_AB_MD_WRC, 0, |
2143 | FRF_AB_MD_GC, 1); | |
12d00cad | 2144 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2145 | udelay(10); |
2146 | } | |
2147 | ||
ab867461 SH |
2148 | out: |
2149 | mutex_unlock(&efx->mdio_lock); | |
68e7f45e | 2150 | return rc; |
8ceee660 BH |
2151 | } |
2152 | ||
68e7f45e BH |
2153 | /* Read an MDIO register of a PHY connected to Falcon. */ |
2154 | static int falcon_mdio_read(struct net_device *net_dev, | |
2155 | int prtad, int devad, u16 addr) | |
8ceee660 | 2156 | { |
767e468c | 2157 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2158 | efx_oword_t reg; |
68e7f45e | 2159 | int rc; |
8ceee660 | 2160 | |
ab867461 | 2161 | mutex_lock(&efx->mdio_lock); |
8ceee660 | 2162 | |
68e7f45e BH |
2163 | /* Check MDIO not currently being accessed */ |
2164 | rc = falcon_gmii_wait(efx); | |
2165 | if (rc) | |
8ceee660 BH |
2166 | goto out; |
2167 | ||
3e6c4538 | 2168 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 2169 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 2170 | |
3e6c4538 BH |
2171 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
2172 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 2173 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
2174 | |
2175 | /* Request data to be read */ | |
3e6c4538 | 2176 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); |
12d00cad | 2177 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2178 | |
2179 | /* Wait for data to become available */ | |
68e7f45e BH |
2180 | rc = falcon_gmii_wait(efx); |
2181 | if (rc == 0) { | |
12d00cad | 2182 | efx_reado(efx, ®, FR_AB_MD_RXD); |
3e6c4538 | 2183 | rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); |
68e7f45e BH |
2184 | EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n", |
2185 | prtad, devad, addr, rc); | |
8ceee660 BH |
2186 | } else { |
2187 | /* Abort the read operation */ | |
2188 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2189 | FRF_AB_MD_RIC, 0, |
2190 | FRF_AB_MD_GC, 1); | |
12d00cad | 2191 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 | 2192 | |
68e7f45e BH |
2193 | EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n", |
2194 | prtad, devad, addr, rc); | |
8ceee660 BH |
2195 | } |
2196 | ||
ab867461 SH |
2197 | out: |
2198 | mutex_unlock(&efx->mdio_lock); | |
68e7f45e | 2199 | return rc; |
8ceee660 BH |
2200 | } |
2201 | ||
26deba50 SH |
2202 | static void falcon_clock_mac(struct efx_nic *efx) |
2203 | { | |
2204 | unsigned strap_val; | |
2205 | efx_oword_t nic_stat; | |
2206 | ||
2207 | /* Configure the NIC generated MAC clock correctly */ | |
2208 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
2209 | strap_val = EFX_IS10G(efx) ? 5 : 3; | |
daeda630 | 2210 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
26deba50 SH |
2211 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1); |
2212 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val); | |
2213 | efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT); | |
2214 | } else { | |
2215 | /* Falcon A1 does not support 1G/10G speed switching | |
2216 | * and must not be used with a PHY that does. */ | |
2217 | BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) != | |
2218 | strap_val); | |
2219 | } | |
2220 | } | |
2221 | ||
177dfcd8 BH |
2222 | int falcon_switch_mac(struct efx_nic *efx) |
2223 | { | |
2224 | struct efx_mac_operations *old_mac_op = efx->mac_op; | |
55edc6e6 BH |
2225 | struct falcon_nic_data *nic_data = efx->nic_data; |
2226 | unsigned int stats_done_offset; | |
1974cc20 BH |
2227 | int rc = 0; |
2228 | ||
2229 | /* Don't try to fetch MAC stats while we're switching MACs */ | |
55edc6e6 | 2230 | falcon_stop_nic_stats(efx); |
177dfcd8 | 2231 | |
0cc12838 | 2232 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
177dfcd8 BH |
2233 | efx->mac_op = (EFX_IS10G(efx) ? |
2234 | &falcon_xmac_operations : &falcon_gmac_operations); | |
177dfcd8 | 2235 | |
55edc6e6 BH |
2236 | if (EFX_IS10G(efx)) |
2237 | stats_done_offset = XgDmaDone_offset; | |
2238 | else | |
2239 | stats_done_offset = GDmaDone_offset; | |
2240 | nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset; | |
2241 | ||
0cc12838 | 2242 | if (old_mac_op == efx->mac_op) |
1974cc20 | 2243 | goto out; |
177dfcd8 | 2244 | |
26deba50 SH |
2245 | falcon_clock_mac(efx); |
2246 | ||
177dfcd8 | 2247 | EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G'); |
0cc12838 | 2248 | /* Not all macs support a mac-level link state */ |
9007b9fa | 2249 | efx->xmac_poll_required = false; |
0cc12838 | 2250 | |
1974cc20 BH |
2251 | rc = falcon_reset_macs(efx); |
2252 | out: | |
55edc6e6 | 2253 | falcon_start_nic_stats(efx); |
1974cc20 | 2254 | return rc; |
177dfcd8 BH |
2255 | } |
2256 | ||
8ceee660 BH |
2257 | /* This call is responsible for hooking in the MAC and PHY operations */ |
2258 | int falcon_probe_port(struct efx_nic *efx) | |
2259 | { | |
2260 | int rc; | |
2261 | ||
96c45726 BH |
2262 | switch (efx->phy_type) { |
2263 | case PHY_TYPE_SFX7101: | |
2264 | efx->phy_op = &falcon_sfx7101_phy_ops; | |
2265 | break; | |
2266 | case PHY_TYPE_SFT9001A: | |
2267 | case PHY_TYPE_SFT9001B: | |
2268 | efx->phy_op = &falcon_sft9001_phy_ops; | |
2269 | break; | |
2270 | case PHY_TYPE_QT2022C2: | |
2271 | case PHY_TYPE_QT2025C: | |
b37b62fe | 2272 | efx->phy_op = &falcon_qt202x_phy_ops; |
96c45726 BH |
2273 | break; |
2274 | default: | |
2275 | EFX_ERR(efx, "Unknown PHY type %d\n", | |
2276 | efx->phy_type); | |
2277 | return -ENODEV; | |
2278 | } | |
2279 | ||
2280 | if (efx->phy_op->macs & EFX_XMAC) | |
2281 | efx->loopback_modes |= ((1 << LOOPBACK_XGMII) | | |
2282 | (1 << LOOPBACK_XGXS) | | |
2283 | (1 << LOOPBACK_XAUI)); | |
2284 | if (efx->phy_op->macs & EFX_GMAC) | |
2285 | efx->loopback_modes |= (1 << LOOPBACK_GMAC); | |
2286 | efx->loopback_modes |= efx->phy_op->loopbacks; | |
8ceee660 | 2287 | |
68e7f45e BH |
2288 | /* Set up MDIO structure for PHY */ |
2289 | efx->mdio.mmds = efx->phy_op->mmds; | |
2290 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
2291 | efx->mdio.mdio_read = falcon_mdio_read; | |
2292 | efx->mdio.mdio_write = falcon_mdio_write; | |
8ceee660 | 2293 | |
b895d73e SH |
2294 | /* Initial assumption */ |
2295 | efx->link_state.speed = 10000; | |
2296 | efx->link_state.fd = true; | |
2297 | ||
8ceee660 | 2298 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ |
daeda630 | 2299 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
04cc8cac | 2300 | efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; |
8ceee660 | 2301 | else |
04cc8cac | 2302 | efx->wanted_fc = EFX_FC_RX; |
8ceee660 BH |
2303 | |
2304 | /* Allocate buffer for stats */ | |
2305 | rc = falcon_alloc_buffer(efx, &efx->stats_buffer, | |
2306 | FALCON_MAC_STATS_SIZE); | |
2307 | if (rc) | |
2308 | return rc; | |
9c8976a1 JSR |
2309 | EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n", |
2310 | (u64)efx->stats_buffer.dma_addr, | |
8ceee660 | 2311 | efx->stats_buffer.addr, |
9c8976a1 | 2312 | (u64)virt_to_phys(efx->stats_buffer.addr)); |
8ceee660 BH |
2313 | |
2314 | return 0; | |
2315 | } | |
2316 | ||
2317 | void falcon_remove_port(struct efx_nic *efx) | |
2318 | { | |
2319 | falcon_free_buffer(efx, &efx->stats_buffer); | |
2320 | } | |
2321 | ||
2322 | /************************************************************************** | |
2323 | * | |
2324 | * Multicast filtering | |
2325 | * | |
2326 | ************************************************************************** | |
2327 | */ | |
2328 | ||
8be4f3e6 | 2329 | void falcon_push_multicast_hash(struct efx_nic *efx) |
8ceee660 BH |
2330 | { |
2331 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
2332 | ||
8be4f3e6 | 2333 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 2334 | |
12d00cad BH |
2335 | efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); |
2336 | efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); | |
8ceee660 BH |
2337 | } |
2338 | ||
8c8661e4 BH |
2339 | |
2340 | /************************************************************************** | |
2341 | * | |
2342 | * Falcon test code | |
2343 | * | |
2344 | **************************************************************************/ | |
2345 | ||
2346 | int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) | |
2347 | { | |
2348 | struct falcon_nvconfig *nvconfig; | |
2349 | struct efx_spi_device *spi; | |
2350 | void *region; | |
2351 | int rc, magic_num, struct_ver; | |
2352 | __le16 *word, *limit; | |
2353 | u32 csum; | |
2354 | ||
2f7f5730 BH |
2355 | spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom; |
2356 | if (!spi) | |
2357 | return -EINVAL; | |
2358 | ||
0a95f563 | 2359 | region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); |
8c8661e4 BH |
2360 | if (!region) |
2361 | return -ENOMEM; | |
3e6c4538 | 2362 | nvconfig = region + FALCON_NVCONFIG_OFFSET; |
8c8661e4 | 2363 | |
f4150724 | 2364 | mutex_lock(&efx->spi_lock); |
0a95f563 | 2365 | rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region); |
f4150724 | 2366 | mutex_unlock(&efx->spi_lock); |
8c8661e4 BH |
2367 | if (rc) { |
2368 | EFX_ERR(efx, "Failed to read %s\n", | |
2369 | efx->spi_flash ? "flash" : "EEPROM"); | |
2370 | rc = -EIO; | |
2371 | goto out; | |
2372 | } | |
2373 | ||
2374 | magic_num = le16_to_cpu(nvconfig->board_magic_num); | |
2375 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); | |
2376 | ||
2377 | rc = -EINVAL; | |
3e6c4538 | 2378 | if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { |
8c8661e4 BH |
2379 | EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num); |
2380 | goto out; | |
2381 | } | |
2382 | if (struct_ver < 2) { | |
2383 | EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver); | |
2384 | goto out; | |
2385 | } else if (struct_ver < 4) { | |
2386 | word = &nvconfig->board_magic_num; | |
2387 | limit = (__le16 *) (nvconfig + 1); | |
2388 | } else { | |
2389 | word = region; | |
0a95f563 | 2390 | limit = region + FALCON_NVCONFIG_END; |
8c8661e4 BH |
2391 | } |
2392 | for (csum = 0; word < limit; ++word) | |
2393 | csum += le16_to_cpu(*word); | |
2394 | ||
2395 | if (~csum & 0xffff) { | |
2396 | EFX_ERR(efx, "NVRAM has incorrect checksum\n"); | |
2397 | goto out; | |
2398 | } | |
2399 | ||
2400 | rc = 0; | |
2401 | if (nvconfig_out) | |
2402 | memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); | |
2403 | ||
2404 | out: | |
2405 | kfree(region); | |
2406 | return rc; | |
2407 | } | |
2408 | ||
2409 | /* Registers tested in the falcon register test */ | |
2410 | static struct { | |
2411 | unsigned address; | |
2412 | efx_oword_t mask; | |
2413 | } efx_test_registers[] = { | |
3e6c4538 | 2414 | { FR_AZ_ADR_REGION, |
8c8661e4 | 2415 | EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) }, |
3e6c4538 | 2416 | { FR_AZ_RX_CFG, |
8c8661e4 | 2417 | EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, |
3e6c4538 | 2418 | { FR_AZ_TX_CFG, |
8c8661e4 | 2419 | EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2420 | { FR_AZ_TX_RESERVED, |
8c8661e4 | 2421 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, |
3e6c4538 | 2422 | { FR_AB_MAC_CTRL, |
8c8661e4 | 2423 | EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2424 | { FR_AZ_SRM_TX_DC_CFG, |
8c8661e4 | 2425 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2426 | { FR_AZ_RX_DC_CFG, |
8c8661e4 | 2427 | EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2428 | { FR_AZ_RX_DC_PF_WM, |
8c8661e4 | 2429 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2430 | { FR_BZ_DP_CTRL, |
8c8661e4 | 2431 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2432 | { FR_AB_GM_CFG2, |
177dfcd8 | 2433 | EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2434 | { FR_AB_GMF_CFG0, |
177dfcd8 | 2435 | EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2436 | { FR_AB_XM_GLB_CFG, |
8c8661e4 | 2437 | EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2438 | { FR_AB_XM_TX_CFG, |
8c8661e4 | 2439 | EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2440 | { FR_AB_XM_RX_CFG, |
8c8661e4 | 2441 | EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2442 | { FR_AB_XM_RX_PARAM, |
8c8661e4 | 2443 | EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2444 | { FR_AB_XM_FC, |
8c8661e4 | 2445 | EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2446 | { FR_AB_XM_ADR_LO, |
8c8661e4 | 2447 | EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2448 | { FR_AB_XX_SD_CTL, |
8c8661e4 BH |
2449 | EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, |
2450 | }; | |
2451 | ||
2452 | static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b, | |
2453 | const efx_oword_t *mask) | |
2454 | { | |
2455 | return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) || | |
2456 | ((a->u64[1] ^ b->u64[1]) & mask->u64[1]); | |
2457 | } | |
2458 | ||
2459 | int falcon_test_registers(struct efx_nic *efx) | |
2460 | { | |
2461 | unsigned address = 0, i, j; | |
2462 | efx_oword_t mask, imask, original, reg, buf; | |
2463 | ||
2464 | /* Falcon should be in loopback to isolate the XMAC from the PHY */ | |
2465 | WARN_ON(!LOOPBACK_INTERNAL(efx)); | |
2466 | ||
2467 | for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) { | |
2468 | address = efx_test_registers[i].address; | |
2469 | mask = imask = efx_test_registers[i].mask; | |
2470 | EFX_INVERT_OWORD(imask); | |
2471 | ||
12d00cad | 2472 | efx_reado(efx, &original, address); |
8c8661e4 BH |
2473 | |
2474 | /* bit sweep on and off */ | |
2475 | for (j = 0; j < 128; j++) { | |
2476 | if (!EFX_EXTRACT_OWORD32(mask, j, j)) | |
2477 | continue; | |
2478 | ||
2479 | /* Test this testable bit can be set in isolation */ | |
2480 | EFX_AND_OWORD(reg, original, mask); | |
2481 | EFX_SET_OWORD32(reg, j, j, 1); | |
2482 | ||
12d00cad BH |
2483 | efx_writeo(efx, ®, address); |
2484 | efx_reado(efx, &buf, address); | |
8c8661e4 BH |
2485 | |
2486 | if (efx_masked_compare_oword(®, &buf, &mask)) | |
2487 | goto fail; | |
2488 | ||
2489 | /* Test this testable bit can be cleared in isolation */ | |
2490 | EFX_OR_OWORD(reg, original, mask); | |
2491 | EFX_SET_OWORD32(reg, j, j, 0); | |
2492 | ||
12d00cad BH |
2493 | efx_writeo(efx, ®, address); |
2494 | efx_reado(efx, &buf, address); | |
8c8661e4 BH |
2495 | |
2496 | if (efx_masked_compare_oword(®, &buf, &mask)) | |
2497 | goto fail; | |
2498 | } | |
2499 | ||
12d00cad | 2500 | efx_writeo(efx, &original, address); |
8c8661e4 BH |
2501 | } |
2502 | ||
2503 | return 0; | |
2504 | ||
2505 | fail: | |
2506 | EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT | |
2507 | " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg), | |
2508 | EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask)); | |
2509 | return -EIO; | |
2510 | } | |
2511 | ||
8ceee660 BH |
2512 | /************************************************************************** |
2513 | * | |
2514 | * Device reset | |
2515 | * | |
2516 | ************************************************************************** | |
2517 | */ | |
2518 | ||
2519 | /* Resets NIC to known state. This routine must be called in process | |
2520 | * context and is allowed to sleep. */ | |
2521 | int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) | |
2522 | { | |
2523 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2524 | efx_oword_t glb_ctl_reg_ker; | |
2525 | int rc; | |
2526 | ||
c459302d | 2527 | EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method)); |
8ceee660 BH |
2528 | |
2529 | /* Initiate device reset */ | |
2530 | if (method == RESET_TYPE_WORLD) { | |
2531 | rc = pci_save_state(efx->pci_dev); | |
2532 | if (rc) { | |
2533 | EFX_ERR(efx, "failed to backup PCI state of primary " | |
2534 | "function prior to hardware reset\n"); | |
2535 | goto fail1; | |
2536 | } | |
2537 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2538 | rc = pci_save_state(nic_data->pci_dev2); | |
2539 | if (rc) { | |
2540 | EFX_ERR(efx, "failed to backup PCI state of " | |
2541 | "secondary function prior to " | |
2542 | "hardware reset\n"); | |
2543 | goto fail2; | |
2544 | } | |
2545 | } | |
2546 | ||
2547 | EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, | |
3e6c4538 BH |
2548 | FRF_AB_EXT_PHY_RST_DUR, |
2549 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
2550 | FRF_AB_SWRST, 1); | |
8ceee660 | 2551 | } else { |
8ceee660 | 2552 | EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, |
3e6c4538 BH |
2553 | /* exclude PHY from "invisible" reset */ |
2554 | FRF_AB_EXT_PHY_RST_CTL, | |
2555 | method == RESET_TYPE_INVISIBLE, | |
2556 | /* exclude EEPROM/flash and PCIe */ | |
2557 | FRF_AB_PCIE_CORE_RST_CTL, 1, | |
2558 | FRF_AB_PCIE_NSTKY_RST_CTL, 1, | |
2559 | FRF_AB_PCIE_SD_RST_CTL, 1, | |
2560 | FRF_AB_EE_RST_CTL, 1, | |
2561 | FRF_AB_EXT_PHY_RST_DUR, | |
2562 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
2563 | FRF_AB_SWRST, 1); | |
2564 | } | |
12d00cad | 2565 | efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
8ceee660 BH |
2566 | |
2567 | EFX_LOG(efx, "waiting for hardware reset\n"); | |
2568 | schedule_timeout_uninterruptible(HZ / 20); | |
2569 | ||
2570 | /* Restore PCI configuration if needed */ | |
2571 | if (method == RESET_TYPE_WORLD) { | |
2572 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2573 | rc = pci_restore_state(nic_data->pci_dev2); | |
2574 | if (rc) { | |
2575 | EFX_ERR(efx, "failed to restore PCI config for " | |
2576 | "the secondary function\n"); | |
2577 | goto fail3; | |
2578 | } | |
2579 | } | |
2580 | rc = pci_restore_state(efx->pci_dev); | |
2581 | if (rc) { | |
2582 | EFX_ERR(efx, "failed to restore PCI config for the " | |
2583 | "primary function\n"); | |
2584 | goto fail4; | |
2585 | } | |
2586 | EFX_LOG(efx, "successfully restored PCI config\n"); | |
2587 | } | |
2588 | ||
2589 | /* Assert that reset complete */ | |
12d00cad | 2590 | efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
3e6c4538 | 2591 | if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { |
8ceee660 BH |
2592 | rc = -ETIMEDOUT; |
2593 | EFX_ERR(efx, "timed out waiting for hardware reset\n"); | |
2594 | goto fail5; | |
2595 | } | |
2596 | EFX_LOG(efx, "hardware reset complete\n"); | |
2597 | ||
2598 | return 0; | |
2599 | ||
2600 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ | |
2601 | fail2: | |
2602 | fail3: | |
2603 | pci_restore_state(efx->pci_dev); | |
2604 | fail1: | |
2605 | fail4: | |
2606 | fail5: | |
2607 | return rc; | |
2608 | } | |
2609 | ||
fe75820b BH |
2610 | void falcon_monitor(struct efx_nic *efx) |
2611 | { | |
fdaa9aed | 2612 | bool link_changed; |
fe75820b BH |
2613 | int rc; |
2614 | ||
fdaa9aed SH |
2615 | BUG_ON(!mutex_is_locked(&efx->mac_lock)); |
2616 | ||
fe75820b BH |
2617 | rc = falcon_board(efx)->type->monitor(efx); |
2618 | if (rc) { | |
2619 | EFX_ERR(efx, "Board sensor %s; shutting down PHY\n", | |
2620 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
2621 | efx->phy_mode |= PHY_MODE_LOW_POWER; | |
fdaa9aed | 2622 | __efx_reconfigure_port(efx); |
fe75820b | 2623 | } |
fdaa9aed SH |
2624 | |
2625 | if (LOOPBACK_INTERNAL(efx)) | |
2626 | link_changed = falcon_loopback_link_poll(efx); | |
2627 | else | |
2628 | link_changed = efx->phy_op->poll(efx); | |
2629 | ||
2630 | if (link_changed) { | |
2631 | falcon_stop_nic_stats(efx); | |
2632 | falcon_deconfigure_mac_wrapper(efx); | |
2633 | ||
2634 | falcon_switch_mac(efx); | |
2635 | efx->mac_op->reconfigure(efx); | |
2636 | ||
2637 | falcon_start_nic_stats(efx); | |
2638 | ||
2639 | efx_link_status_changed(efx); | |
2640 | } | |
2641 | ||
9007b9fa BH |
2642 | if (EFX_IS10G(efx)) |
2643 | falcon_poll_xmac(efx); | |
fe75820b BH |
2644 | } |
2645 | ||
8ceee660 BH |
2646 | /* Zeroes out the SRAM contents. This routine must be called in |
2647 | * process context and is allowed to sleep. | |
2648 | */ | |
2649 | static int falcon_reset_sram(struct efx_nic *efx) | |
2650 | { | |
2651 | efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; | |
2652 | int count; | |
2653 | ||
2654 | /* Set the SRAM wake/sleep GPIO appropriately. */ | |
12d00cad | 2655 | efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
3e6c4538 BH |
2656 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); |
2657 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); | |
12d00cad | 2658 | efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
8ceee660 BH |
2659 | |
2660 | /* Initiate SRAM reset */ | |
2661 | EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, | |
3e6c4538 BH |
2662 | FRF_AZ_SRM_INIT_EN, 1, |
2663 | FRF_AZ_SRM_NB_SZ, 0); | |
12d00cad | 2664 | efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
8ceee660 BH |
2665 | |
2666 | /* Wait for SRAM reset to complete */ | |
2667 | count = 0; | |
2668 | do { | |
2669 | EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count); | |
2670 | ||
2671 | /* SRAM reset is slow; expect around 16ms */ | |
2672 | schedule_timeout_uninterruptible(HZ / 50); | |
2673 | ||
2674 | /* Check for reset complete */ | |
12d00cad | 2675 | efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
3e6c4538 | 2676 | if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { |
8ceee660 BH |
2677 | EFX_LOG(efx, "SRAM reset complete\n"); |
2678 | ||
2679 | return 0; | |
2680 | } | |
2681 | } while (++count < 20); /* wait upto 0.4 sec */ | |
2682 | ||
2683 | EFX_ERR(efx, "timed out waiting for SRAM reset\n"); | |
2684 | return -ETIMEDOUT; | |
2685 | } | |
2686 | ||
4a5b504d BH |
2687 | static int falcon_spi_device_init(struct efx_nic *efx, |
2688 | struct efx_spi_device **spi_device_ret, | |
2689 | unsigned int device_id, u32 device_type) | |
2690 | { | |
2691 | struct efx_spi_device *spi_device; | |
2692 | ||
2693 | if (device_type != 0) { | |
0c53d8c8 | 2694 | spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL); |
4a5b504d BH |
2695 | if (!spi_device) |
2696 | return -ENOMEM; | |
2697 | spi_device->device_id = device_id; | |
2698 | spi_device->size = | |
2699 | 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); | |
2700 | spi_device->addr_len = | |
2701 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); | |
2702 | spi_device->munge_address = (spi_device->size == 1 << 9 && | |
2703 | spi_device->addr_len == 1); | |
f4150724 BH |
2704 | spi_device->erase_command = |
2705 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); | |
2706 | spi_device->erase_size = | |
2707 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
2708 | SPI_DEV_TYPE_ERASE_SIZE); | |
4a5b504d BH |
2709 | spi_device->block_size = |
2710 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
2711 | SPI_DEV_TYPE_BLOCK_SIZE); | |
2712 | ||
2713 | spi_device->efx = efx; | |
2714 | } else { | |
2715 | spi_device = NULL; | |
2716 | } | |
2717 | ||
2718 | kfree(*spi_device_ret); | |
2719 | *spi_device_ret = spi_device; | |
2720 | return 0; | |
2721 | } | |
2722 | ||
2723 | ||
2724 | static void falcon_remove_spi_devices(struct efx_nic *efx) | |
2725 | { | |
2726 | kfree(efx->spi_eeprom); | |
2727 | efx->spi_eeprom = NULL; | |
2728 | kfree(efx->spi_flash); | |
2729 | efx->spi_flash = NULL; | |
2730 | } | |
2731 | ||
8ceee660 BH |
2732 | /* Extract non-volatile configuration */ |
2733 | static int falcon_probe_nvconfig(struct efx_nic *efx) | |
2734 | { | |
2735 | struct falcon_nvconfig *nvconfig; | |
8c8661e4 | 2736 | int board_rev; |
8ceee660 BH |
2737 | int rc; |
2738 | ||
8ceee660 | 2739 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); |
4a5b504d BH |
2740 | if (!nvconfig) |
2741 | return -ENOMEM; | |
8ceee660 | 2742 | |
8c8661e4 BH |
2743 | rc = falcon_read_nvram(efx, nvconfig); |
2744 | if (rc == -EINVAL) { | |
2745 | EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n"); | |
8ceee660 | 2746 | efx->phy_type = PHY_TYPE_NONE; |
68e7f45e | 2747 | efx->mdio.prtad = MDIO_PRTAD_NONE; |
8ceee660 | 2748 | board_rev = 0; |
8c8661e4 BH |
2749 | rc = 0; |
2750 | } else if (rc) { | |
2751 | goto fail1; | |
8ceee660 BH |
2752 | } else { |
2753 | struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2; | |
4a5b504d | 2754 | struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3; |
8ceee660 BH |
2755 | |
2756 | efx->phy_type = v2->port0_phy_type; | |
68e7f45e | 2757 | efx->mdio.prtad = v2->port0_phy_addr; |
8ceee660 | 2758 | board_rev = le16_to_cpu(v2->board_revision); |
4a5b504d | 2759 | |
8c8661e4 | 2760 | if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { |
3e6c4538 BH |
2761 | rc = falcon_spi_device_init( |
2762 | efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH, | |
2763 | le32_to_cpu(v3->spi_device_type | |
2764 | [FFE_AB_SPI_DEVICE_FLASH])); | |
4a5b504d BH |
2765 | if (rc) |
2766 | goto fail2; | |
3e6c4538 BH |
2767 | rc = falcon_spi_device_init( |
2768 | efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, | |
2769 | le32_to_cpu(v3->spi_device_type | |
2770 | [FFE_AB_SPI_DEVICE_EEPROM])); | |
4a5b504d BH |
2771 | if (rc) |
2772 | goto fail2; | |
2773 | } | |
8ceee660 BH |
2774 | } |
2775 | ||
8c8661e4 BH |
2776 | /* Read the MAC addresses */ |
2777 | memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN); | |
2778 | ||
68e7f45e | 2779 | EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad); |
8ceee660 | 2780 | |
3473a5b1 | 2781 | falcon_probe_board(efx, board_rev); |
8ceee660 | 2782 | |
4a5b504d BH |
2783 | kfree(nvconfig); |
2784 | return 0; | |
2785 | ||
2786 | fail2: | |
2787 | falcon_remove_spi_devices(efx); | |
2788 | fail1: | |
8ceee660 BH |
2789 | kfree(nvconfig); |
2790 | return rc; | |
2791 | } | |
2792 | ||
2793 | /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port | |
2794 | * count, port speed). Set workaround and feature flags accordingly. | |
2795 | */ | |
2796 | static int falcon_probe_nic_variant(struct efx_nic *efx) | |
2797 | { | |
2798 | efx_oword_t altera_build; | |
177dfcd8 | 2799 | efx_oword_t nic_stat; |
8ceee660 | 2800 | |
12d00cad | 2801 | efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD); |
3e6c4538 | 2802 | if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) { |
8ceee660 BH |
2803 | EFX_ERR(efx, "Falcon FPGA not supported\n"); |
2804 | return -ENODEV; | |
2805 | } | |
2806 | ||
12d00cad | 2807 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
177dfcd8 | 2808 | |
daeda630 BH |
2809 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { |
2810 | u8 pci_rev = efx->pci_dev->revision; | |
8ceee660 | 2811 | |
daeda630 BH |
2812 | if ((pci_rev == 0xff) || (pci_rev == 0)) { |
2813 | EFX_ERR(efx, "Falcon rev A0 not supported\n"); | |
2814 | return -ENODEV; | |
2815 | } | |
b895d73e SH |
2816 | if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) { |
2817 | EFX_ERR(efx, "Falcon rev A1 1G not supported\n"); | |
2818 | return -ENODEV; | |
2819 | } | |
3e6c4538 | 2820 | if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { |
8ceee660 BH |
2821 | EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n"); |
2822 | return -ENODEV; | |
2823 | } | |
8ceee660 BH |
2824 | } |
2825 | ||
2826 | return 0; | |
2827 | } | |
2828 | ||
4a5b504d BH |
2829 | /* Probe all SPI devices on the NIC */ |
2830 | static void falcon_probe_spi_devices(struct efx_nic *efx) | |
2831 | { | |
2832 | efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; | |
2f7f5730 | 2833 | int boot_dev; |
4a5b504d | 2834 | |
12d00cad BH |
2835 | efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); |
2836 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
2837 | efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); | |
4a5b504d | 2838 | |
3e6c4538 BH |
2839 | if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { |
2840 | boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? | |
2841 | FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); | |
2f7f5730 | 2842 | EFX_LOG(efx, "Booted from %s\n", |
3e6c4538 | 2843 | boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM"); |
2f7f5730 BH |
2844 | } else { |
2845 | /* Disable VPD and set clock dividers to safe | |
2846 | * values for initial programming. */ | |
2847 | boot_dev = -1; | |
2848 | EFX_LOG(efx, "Booted from internal ASIC settings;" | |
2849 | " setting SPI config\n"); | |
3e6c4538 | 2850 | EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, |
2f7f5730 | 2851 | /* 125 MHz / 7 ~= 20 MHz */ |
3e6c4538 | 2852 | FRF_AB_EE_SF_CLOCK_DIV, 7, |
2f7f5730 | 2853 | /* 125 MHz / 63 ~= 2 MHz */ |
3e6c4538 | 2854 | FRF_AB_EE_EE_CLOCK_DIV, 63); |
12d00cad | 2855 | efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
4a5b504d BH |
2856 | } |
2857 | ||
3e6c4538 BH |
2858 | if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) |
2859 | falcon_spi_device_init(efx, &efx->spi_flash, | |
2860 | FFE_AB_SPI_DEVICE_FLASH, | |
2f7f5730 | 2861 | default_flash_type); |
3e6c4538 BH |
2862 | if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) |
2863 | falcon_spi_device_init(efx, &efx->spi_eeprom, | |
2864 | FFE_AB_SPI_DEVICE_EEPROM, | |
2f7f5730 | 2865 | large_eeprom_type); |
4a5b504d BH |
2866 | } |
2867 | ||
8ceee660 BH |
2868 | int falcon_probe_nic(struct efx_nic *efx) |
2869 | { | |
2870 | struct falcon_nic_data *nic_data; | |
e775fb93 | 2871 | struct falcon_board *board; |
8ceee660 BH |
2872 | int rc; |
2873 | ||
8ceee660 BH |
2874 | /* Allocate storage for hardware specific data */ |
2875 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | |
88c59425 BH |
2876 | if (!nic_data) |
2877 | return -ENOMEM; | |
5daab96d | 2878 | efx->nic_data = nic_data; |
8ceee660 BH |
2879 | |
2880 | /* Determine number of ports etc. */ | |
2881 | rc = falcon_probe_nic_variant(efx); | |
2882 | if (rc) | |
2883 | goto fail1; | |
2884 | ||
2885 | /* Probe secondary function if expected */ | |
2886 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2887 | struct pci_dev *dev = pci_dev_get(efx->pci_dev); | |
2888 | ||
2889 | while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID, | |
2890 | dev))) { | |
2891 | if (dev->bus == efx->pci_dev->bus && | |
2892 | dev->devfn == efx->pci_dev->devfn + 1) { | |
2893 | nic_data->pci_dev2 = dev; | |
2894 | break; | |
2895 | } | |
2896 | } | |
2897 | if (!nic_data->pci_dev2) { | |
2898 | EFX_ERR(efx, "failed to find secondary function\n"); | |
2899 | rc = -ENODEV; | |
2900 | goto fail2; | |
2901 | } | |
2902 | } | |
2903 | ||
2904 | /* Now we can reset the NIC */ | |
2905 | rc = falcon_reset_hw(efx, RESET_TYPE_ALL); | |
2906 | if (rc) { | |
2907 | EFX_ERR(efx, "failed to reset NIC\n"); | |
2908 | goto fail3; | |
2909 | } | |
2910 | ||
2911 | /* Allocate memory for INT_KER */ | |
2912 | rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); | |
2913 | if (rc) | |
2914 | goto fail4; | |
2915 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
2916 | ||
9c8976a1 JSR |
2917 | EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n", |
2918 | (u64)efx->irq_status.dma_addr, | |
2919 | efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr)); | |
8ceee660 | 2920 | |
4a5b504d BH |
2921 | falcon_probe_spi_devices(efx); |
2922 | ||
8ceee660 BH |
2923 | /* Read in the non-volatile configuration */ |
2924 | rc = falcon_probe_nvconfig(efx); | |
2925 | if (rc) | |
2926 | goto fail5; | |
2927 | ||
37b5a603 | 2928 | /* Initialise I2C adapter */ |
e775fb93 BH |
2929 | board = falcon_board(efx); |
2930 | board->i2c_adap.owner = THIS_MODULE; | |
2931 | board->i2c_data = falcon_i2c_bit_operations; | |
2932 | board->i2c_data.data = efx; | |
2933 | board->i2c_adap.algo_data = &board->i2c_data; | |
2934 | board->i2c_adap.dev.parent = &efx->pci_dev->dev; | |
2935 | strlcpy(board->i2c_adap.name, "SFC4000 GPIO", | |
2936 | sizeof(board->i2c_adap.name)); | |
2937 | rc = i2c_bit_add_bus(&board->i2c_adap); | |
37b5a603 BH |
2938 | if (rc) |
2939 | goto fail5; | |
2940 | ||
44838a44 | 2941 | rc = falcon_board(efx)->type->init(efx); |
278c0621 BH |
2942 | if (rc) { |
2943 | EFX_ERR(efx, "failed to initialise board\n"); | |
2944 | goto fail6; | |
2945 | } | |
2946 | ||
55edc6e6 BH |
2947 | nic_data->stats_disable_count = 1; |
2948 | setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func, | |
2949 | (unsigned long)efx); | |
2950 | ||
8ceee660 BH |
2951 | return 0; |
2952 | ||
278c0621 | 2953 | fail6: |
e775fb93 BH |
2954 | BUG_ON(i2c_del_adapter(&board->i2c_adap)); |
2955 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); | |
8ceee660 | 2956 | fail5: |
4a5b504d | 2957 | falcon_remove_spi_devices(efx); |
8ceee660 BH |
2958 | falcon_free_buffer(efx, &efx->irq_status); |
2959 | fail4: | |
8ceee660 BH |
2960 | fail3: |
2961 | if (nic_data->pci_dev2) { | |
2962 | pci_dev_put(nic_data->pci_dev2); | |
2963 | nic_data->pci_dev2 = NULL; | |
2964 | } | |
2965 | fail2: | |
8ceee660 BH |
2966 | fail1: |
2967 | kfree(efx->nic_data); | |
2968 | return rc; | |
2969 | } | |
2970 | ||
56241ceb BH |
2971 | static void falcon_init_rx_cfg(struct efx_nic *efx) |
2972 | { | |
2973 | /* Prior to Siena the RX DMA engine will split each frame at | |
2974 | * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to | |
2975 | * be so large that that never happens. */ | |
2976 | const unsigned huge_buf_size = (3 * 4096) >> 5; | |
2977 | /* RX control FIFO thresholds (32 entries) */ | |
2978 | const unsigned ctrl_xon_thr = 20; | |
2979 | const unsigned ctrl_xoff_thr = 25; | |
2980 | /* RX data FIFO thresholds (256-byte units; size varies) */ | |
625b4514 BH |
2981 | int data_xon_thr = rx_xon_thresh_bytes >> 8; |
2982 | int data_xoff_thr = rx_xoff_thresh_bytes >> 8; | |
56241ceb BH |
2983 | efx_oword_t reg; |
2984 | ||
12d00cad | 2985 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
daeda630 | 2986 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { |
625b4514 BH |
2987 | /* Data FIFO size is 5.5K */ |
2988 | if (data_xon_thr < 0) | |
2989 | data_xon_thr = 512 >> 8; | |
2990 | if (data_xoff_thr < 0) | |
2991 | data_xoff_thr = 2048 >> 8; | |
3e6c4538 BH |
2992 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); |
2993 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, | |
2994 | huge_buf_size); | |
2995 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr); | |
2996 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr); | |
2997 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); | |
2998 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
56241ceb | 2999 | } else { |
625b4514 BH |
3000 | /* Data FIFO size is 80K; register fields moved */ |
3001 | if (data_xon_thr < 0) | |
3002 | data_xon_thr = 27648 >> 8; /* ~3*max MTU */ | |
3003 | if (data_xoff_thr < 0) | |
3004 | data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */ | |
3e6c4538 BH |
3005 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); |
3006 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, | |
3007 | huge_buf_size); | |
3008 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr); | |
3009 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr); | |
3010 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); | |
3011 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
3012 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); | |
56241ceb | 3013 | } |
12d00cad | 3014 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
56241ceb BH |
3015 | } |
3016 | ||
8ceee660 BH |
3017 | /* This call performs hardware-specific global initialisation, such as |
3018 | * defining the descriptor cache sizes and number of RSS channels. | |
3019 | * It does not set up any buffers, descriptor rings or event queues. | |
3020 | */ | |
3021 | int falcon_init_nic(struct efx_nic *efx) | |
3022 | { | |
8ceee660 | 3023 | efx_oword_t temp; |
8ceee660 BH |
3024 | int rc; |
3025 | ||
8ceee660 | 3026 | /* Use on-chip SRAM */ |
12d00cad | 3027 | efx_reado(efx, &temp, FR_AB_NIC_STAT); |
3e6c4538 | 3028 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); |
12d00cad | 3029 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); |
8ceee660 | 3030 | |
6f158d5f | 3031 | /* Set the source of the GMAC clock */ |
daeda630 | 3032 | if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) { |
12d00cad | 3033 | efx_reado(efx, &temp, FR_AB_GPIO_CTL); |
3e6c4538 | 3034 | EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true); |
12d00cad | 3035 | efx_writeo(efx, &temp, FR_AB_GPIO_CTL); |
6f158d5f BH |
3036 | } |
3037 | ||
26deba50 SH |
3038 | /* Select the correct MAC */ |
3039 | falcon_clock_mac(efx); | |
3040 | ||
8ceee660 BH |
3041 | rc = falcon_reset_sram(efx); |
3042 | if (rc) | |
3043 | return rc; | |
3044 | ||
3045 | /* Set positions of descriptor caches in SRAM. */ | |
3e6c4538 | 3046 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8); |
12d00cad | 3047 | efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG); |
3e6c4538 | 3048 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8); |
12d00cad | 3049 | efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG); |
8ceee660 BH |
3050 | |
3051 | /* Set TX descriptor cache size. */ | |
46e1ac0f | 3052 | BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER)); |
3e6c4538 | 3053 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER); |
12d00cad | 3054 | efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG); |
8ceee660 BH |
3055 | |
3056 | /* Set RX descriptor cache size. Set low watermark to size-8, as | |
3057 | * this allows most efficient prefetching. | |
3058 | */ | |
46e1ac0f | 3059 | BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER)); |
3e6c4538 | 3060 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER); |
12d00cad | 3061 | efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG); |
3e6c4538 | 3062 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8); |
12d00cad | 3063 | efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM); |
8ceee660 BH |
3064 | |
3065 | /* Clear the parity enables on the TX data fifos as | |
3066 | * they produce false parity errors because of timing issues | |
3067 | */ | |
3068 | if (EFX_WORKAROUND_5129(efx)) { | |
12d00cad | 3069 | efx_reado(efx, &temp, FR_AZ_CSR_SPARE); |
3e6c4538 | 3070 | EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); |
12d00cad | 3071 | efx_writeo(efx, &temp, FR_AZ_CSR_SPARE); |
8ceee660 BH |
3072 | } |
3073 | ||
3074 | /* Enable all the genuinely fatal interrupts. (They are still | |
3075 | * masked by the overall interrupt mask, controlled by | |
3076 | * falcon_interrupts()). | |
3077 | * | |
3078 | * Note: All other fatal interrupts are enabled | |
3079 | */ | |
3080 | EFX_POPULATE_OWORD_3(temp, | |
3e6c4538 BH |
3081 | FRF_AZ_ILL_ADR_INT_KER_EN, 1, |
3082 | FRF_AZ_RBUF_OWN_INT_KER_EN, 1, | |
3083 | FRF_AZ_TBUF_OWN_INT_KER_EN, 1); | |
8ceee660 | 3084 | EFX_INVERT_OWORD(temp); |
12d00cad | 3085 | efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER); |
8ceee660 | 3086 | |
8ceee660 | 3087 | if (EFX_WORKAROUND_7244(efx)) { |
12d00cad | 3088 | efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); |
3e6c4538 BH |
3089 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); |
3090 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); | |
3091 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); | |
3092 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); | |
12d00cad | 3093 | efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); |
8ceee660 | 3094 | } |
8ceee660 BH |
3095 | |
3096 | falcon_setup_rss_indir_table(efx); | |
3097 | ||
3e6c4538 | 3098 | /* XXX This is documented only for Falcon A0/A1 */ |
8ceee660 BH |
3099 | /* Setup RX. Wait for descriptor is broken and must |
3100 | * be disabled. RXDP recovery shouldn't be needed, but is. | |
3101 | */ | |
12d00cad | 3102 | efx_reado(efx, &temp, FR_AA_RX_SELF_RST); |
3e6c4538 BH |
3103 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); |
3104 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); | |
8ceee660 | 3105 | if (EFX_WORKAROUND_5583(efx)) |
3e6c4538 | 3106 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); |
12d00cad | 3107 | efx_writeo(efx, &temp, FR_AA_RX_SELF_RST); |
8ceee660 BH |
3108 | |
3109 | /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be | |
3110 | * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. | |
3111 | */ | |
12d00cad | 3112 | efx_reado(efx, &temp, FR_AZ_TX_RESERVED); |
3e6c4538 BH |
3113 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe); |
3114 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1); | |
3115 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1); | |
3116 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0); | |
3117 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1); | |
8ceee660 | 3118 | /* Enable SW_EV to inherit in char driver - assume harmless here */ |
3e6c4538 | 3119 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1); |
8ceee660 | 3120 | /* Prefetch threshold 2 => fetch when descriptor cache half empty */ |
3e6c4538 | 3121 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2); |
8ceee660 | 3122 | /* Squash TX of packets of 16 bytes or less */ |
daeda630 | 3123 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
3e6c4538 | 3124 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); |
12d00cad | 3125 | efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); |
8ceee660 BH |
3126 | |
3127 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 | |
3128 | * descriptors (which is bad). | |
3129 | */ | |
12d00cad | 3130 | efx_reado(efx, &temp, FR_AZ_TX_CFG); |
3e6c4538 | 3131 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); |
12d00cad | 3132 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); |
8ceee660 | 3133 | |
56241ceb | 3134 | falcon_init_rx_cfg(efx); |
8ceee660 BH |
3135 | |
3136 | /* Set destination of both TX and RX Flush events */ | |
daeda630 | 3137 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
3e6c4538 | 3138 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); |
12d00cad | 3139 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); |
8ceee660 BH |
3140 | } |
3141 | ||
3142 | return 0; | |
3143 | } | |
3144 | ||
3145 | void falcon_remove_nic(struct efx_nic *efx) | |
3146 | { | |
3147 | struct falcon_nic_data *nic_data = efx->nic_data; | |
e775fb93 | 3148 | struct falcon_board *board = falcon_board(efx); |
37b5a603 BH |
3149 | int rc; |
3150 | ||
44838a44 | 3151 | board->type->fini(efx); |
278c0621 | 3152 | |
8c870379 | 3153 | /* Remove I2C adapter and clear it in preparation for a retry */ |
e775fb93 | 3154 | rc = i2c_del_adapter(&board->i2c_adap); |
37b5a603 | 3155 | BUG_ON(rc); |
e775fb93 | 3156 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); |
8ceee660 | 3157 | |
4a5b504d | 3158 | falcon_remove_spi_devices(efx); |
8ceee660 BH |
3159 | falcon_free_buffer(efx, &efx->irq_status); |
3160 | ||
91ad757c | 3161 | falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 BH |
3162 | |
3163 | /* Release the second function after the reset */ | |
3164 | if (nic_data->pci_dev2) { | |
3165 | pci_dev_put(nic_data->pci_dev2); | |
3166 | nic_data->pci_dev2 = NULL; | |
3167 | } | |
3168 | ||
3169 | /* Tear down the private nic state */ | |
3170 | kfree(efx->nic_data); | |
3171 | efx->nic_data = NULL; | |
3172 | } | |
3173 | ||
3174 | void falcon_update_nic_stats(struct efx_nic *efx) | |
3175 | { | |
55edc6e6 | 3176 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 BH |
3177 | efx_oword_t cnt; |
3178 | ||
55edc6e6 BH |
3179 | if (nic_data->stats_disable_count) |
3180 | return; | |
3181 | ||
12d00cad | 3182 | efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); |
3e6c4538 BH |
3183 | efx->n_rx_nodesc_drop_cnt += |
3184 | EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); | |
55edc6e6 BH |
3185 | |
3186 | if (nic_data->stats_pending && | |
3187 | *nic_data->stats_dma_done == FALCON_STATS_DONE) { | |
3188 | nic_data->stats_pending = false; | |
3189 | rmb(); /* read the done flag before the stats */ | |
3190 | efx->mac_op->update_stats(efx); | |
3191 | } | |
3192 | } | |
3193 | ||
3194 | void falcon_start_nic_stats(struct efx_nic *efx) | |
3195 | { | |
3196 | struct falcon_nic_data *nic_data = efx->nic_data; | |
3197 | ||
3198 | spin_lock_bh(&efx->stats_lock); | |
3199 | if (--nic_data->stats_disable_count == 0) | |
3200 | falcon_stats_request(efx); | |
3201 | spin_unlock_bh(&efx->stats_lock); | |
3202 | } | |
3203 | ||
3204 | void falcon_stop_nic_stats(struct efx_nic *efx) | |
3205 | { | |
3206 | struct falcon_nic_data *nic_data = efx->nic_data; | |
3207 | int i; | |
3208 | ||
3209 | might_sleep(); | |
3210 | ||
3211 | spin_lock_bh(&efx->stats_lock); | |
3212 | ++nic_data->stats_disable_count; | |
3213 | spin_unlock_bh(&efx->stats_lock); | |
3214 | ||
3215 | del_timer_sync(&nic_data->stats_timer); | |
3216 | ||
3217 | /* Wait enough time for the most recent transfer to | |
3218 | * complete. */ | |
3219 | for (i = 0; i < 4 && nic_data->stats_pending; i++) { | |
3220 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) | |
3221 | break; | |
3222 | msleep(1); | |
3223 | } | |
3224 | ||
3225 | spin_lock_bh(&efx->stats_lock); | |
3226 | falcon_stats_complete(efx); | |
3227 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
3228 | } |
3229 | ||
3230 | /************************************************************************** | |
3231 | * | |
3232 | * Revision-dependent attributes used by efx.c | |
3233 | * | |
3234 | ************************************************************************** | |
3235 | */ | |
3236 | ||
daeda630 | 3237 | struct efx_nic_type falcon_a1_nic_type = { |
b895d73e SH |
3238 | .default_mac_ops = &falcon_xmac_operations, |
3239 | ||
daeda630 | 3240 | .revision = EFX_REV_FALCON_A1, |
8ceee660 | 3241 | .mem_map_size = 0x20000, |
3e6c4538 BH |
3242 | .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, |
3243 | .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, | |
3244 | .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, | |
3245 | .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, | |
3246 | .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, | |
6d51d307 | 3247 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 BH |
3248 | .rx_buffer_padding = 0x24, |
3249 | .max_interrupt_mode = EFX_INT_MODE_MSI, | |
3250 | .phys_addr_channels = 4, | |
3251 | }; | |
3252 | ||
daeda630 | 3253 | struct efx_nic_type falcon_b0_nic_type = { |
b895d73e SH |
3254 | .default_mac_ops = &falcon_xmac_operations, |
3255 | ||
daeda630 | 3256 | .revision = EFX_REV_FALCON_B0, |
8ceee660 BH |
3257 | /* Map everything up to and including the RSS indirection |
3258 | * table. Don't map MSI-X table, MSI-X PBA since Linux | |
3259 | * requires that they not be mapped. */ | |
3e6c4538 BH |
3260 | .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL + |
3261 | FR_BZ_RX_INDIRECTION_TBL_STEP * | |
3262 | FR_BZ_RX_INDIRECTION_TBL_ROWS), | |
3263 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, | |
3264 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
3265 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
3266 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
3267 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
6d51d307 | 3268 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 BH |
3269 | .rx_buffer_padding = 0, |
3270 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
3271 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
3272 | * interrupt handler only supports 32 | |
3273 | * channels */ | |
3274 | }; | |
3275 |