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sfc: Move CPU counting for RSS into a separate function, efx_wanted_rx_queues()
[linux-2.6-block.git] / drivers / net / sfc / falcon.c
CommitLineData
8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/seq_file.h>
37b5a603
BH		 16#include <linux/i2c.h>
17#include <linux/i2c-algo-bit.h>
8ceee660
BH		 18#include "net_driver.h"
19#include "bitfield.h"
20#include "efx.h"
21#include "mac.h"
22#include "gmii.h"
23#include "spi.h"
24#include "falcon.h"
25#include "falcon_hwdefs.h"
26#include "falcon_io.h"
27#include "mdio_10g.h"
28#include "phy.h"
29#include "boards.h"
30#include "workarounds.h"
31
32/* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
35 */
36
37/**
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
37b5a603 41 * @i2c_data: Operations and state for I2C bit-bashing algorithm
8ceee660
BH		 42 */
43struct falcon_nic_data {
44 unsigned next_buffer_table;
45 struct pci_dev *pci_dev2;
37b5a603 46 struct i2c_algo_bit_data i2c_data;
8ceee660
BH		 47};
48
49/**************************************************************************
50 *
51 * Configurable values
52 *
53 **************************************************************************
54 */
55
56static int disable_dma_stats;
57
58/* This is set to 16 for a good reason. In summary, if larger than
59 * 16, the descriptor cache holds more than a default socket
60 * buffer's worth of packets (for UDP we can only have at most one
61 * socket buffer's worth outstanding). This combined with the fact
62 * that we only get 1 TX event per descriptor cache means the NIC
63 * goes idle.
64 */
65#define TX_DC_ENTRIES 16
66#define TX_DC_ENTRIES_ORDER 0
67#define TX_DC_BASE 0x130000
68
69#define RX_DC_ENTRIES 64
70#define RX_DC_ENTRIES_ORDER 2
71#define RX_DC_BASE 0x100000
72
73/* RX FIFO XOFF watermark
74 *
75 * When the amount of the RX FIFO increases used increases past this
76 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
77 * This also has an effect on RX/TX arbitration
78 */
79static int rx_xoff_thresh_bytes = -1;
80module_param(rx_xoff_thresh_bytes, int, 0644);
81MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
82
83/* RX FIFO XON watermark
84 *
85 * When the amount of the RX FIFO used decreases below this
86 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
87 * This also has an effect on RX/TX arbitration
88 */
89static int rx_xon_thresh_bytes = -1;
90module_param(rx_xon_thresh_bytes, int, 0644);
91MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
92
93/* TX descriptor ring size - min 512 max 4k */
94#define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
95#define FALCON_TXD_RING_SIZE 1024
96#define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
97
98/* RX descriptor ring size - min 512 max 4k */
99#define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
100#define FALCON_RXD_RING_SIZE 1024
101#define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
102
103/* Event queue size - max 32k */
104#define FALCON_EVQ_ORDER EVQ_SIZE_4K
105#define FALCON_EVQ_SIZE 4096
106#define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
107
108/* Max number of internal errors. After this resets will not be performed */
109#define FALCON_MAX_INT_ERRORS 4
110
111/* Maximum period that we wait for flush events. If the flush event
112 * doesn't arrive in this period of time then we check if the queue
113 * was disabled anyway. */
114#define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
115
116/**************************************************************************
117 *
118 * Falcon constants
119 *
120 **************************************************************************
121 */
122
9bbd7d9a
BH		 123/* DMA address mask */
124#define FALCON_DMA_MASK DMA_BIT_MASK(46)
8ceee660
BH		 125
126/* TX DMA length mask (13-bit) */
127#define FALCON_TX_DMA_MASK (4096 - 1)
128
129/* Size and alignment of special buffers (4KB) */
130#define FALCON_BUF_SIZE 4096
131
132/* Dummy SRAM size code */
133#define SRM_NB_BSZ_ONCHIP_ONLY (-1)
134
135/* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
136#define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
137#define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
138#define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
139#define PCI_EXP_LNKSTA_LNK_WID 0x3f0
140#define PCI_EXP_LNKSTA_LNK_WID_LBN 4
141
142#define FALCON_IS_DUAL_FUNC(efx) \
55668611 143 (falcon_rev(efx) < FALCON_REV_B0)
8ceee660
BH		 144
145/**************************************************************************
146 *
147 * Falcon hardware access
148 *
149 **************************************************************************/
150
151/* Read the current event from the event queue */
152static inline efx_qword_t *falcon_event(struct efx_channel *channel,
153 unsigned int index)
154{
155 return (((efx_qword_t *) (channel->eventq.addr)) + index);
156}
157
158/* See if an event is present
159 *
160 * We check both the high and low dword of the event for all ones. We
161 * wrote all ones when we cleared the event, and no valid event can
162 * have all ones in either its high or low dwords. This approach is
163 * robust against reordering.
164 *
165 * Note that using a single 64-bit comparison is incorrect; even
166 * though the CPU read will be atomic, the DMA write may not be.
167 */
168static inline int falcon_event_present(efx_qword_t *event)
169{
170 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
171 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
172}
173
174/**************************************************************************
175 *
176 * I2C bus - this is a bit-bashing interface using GPIO pins
177 * Note that it uses the output enables to tristate the outputs
178 * SDA is the data pin and SCL is the clock
179 *
180 **************************************************************************
181 */
37b5a603 182static void falcon_setsda(void *data, int state)
8ceee660 183{
37b5a603 184 struct efx_nic *efx = (struct efx_nic *)data;
8ceee660
BH		 185 efx_oword_t reg;
186
37b5a603
BH		 187 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
188 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
189 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
8ceee660
BH		 190}
191
37b5a603 192static void falcon_setscl(void *data, int state)
8ceee660 193{
37b5a603 194 struct efx_nic *efx = (struct efx_nic *)data;
8ceee660
BH		 195 efx_oword_t reg;
196
37b5a603
BH		 197 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
198 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
199 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
200}
201
202static int falcon_getsda(void *data)
203{
204 struct efx_nic *efx = (struct efx_nic *)data;
205 efx_oword_t reg;
206
207 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
8ceee660
BH		 208 return EFX_OWORD_FIELD(reg, GPIO3_IN);
209}
210
37b5a603 211static int falcon_getscl(void *data)
8ceee660 212{
37b5a603 213 struct efx_nic *efx = (struct efx_nic *)data;
8ceee660
BH		 214 efx_oword_t reg;
215
37b5a603
BH		 216 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
217 return EFX_OWORD_FIELD(reg, GPIO0_IN);
8ceee660
BH		 218}
219
37b5a603
BH		 220static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
221 .setsda = falcon_setsda,
222 .setscl = falcon_setscl,
8ceee660
BH		 223 .getsda = falcon_getsda,
224 .getscl = falcon_getscl,
62c78329 225 .udelay = 5,
9dadae68
BH		 226 /* Wait up to 50 ms for slave to let us pull SCL high */
227 .timeout = DIV_ROUND_UP(HZ, 20),
8ceee660
BH		 228};
229
230/**************************************************************************
231 *
232 * Falcon special buffer handling
233 * Special buffers are used for event queues and the TX and RX
234 * descriptor rings.
235 *
236 *************************************************************************/
237
238/*
239 * Initialise a Falcon special buffer
240 *
241 * This will define a buffer (previously allocated via
242 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
243 * it to be used for event queues, descriptor rings etc.
244 */
245static int
246falcon_init_special_buffer(struct efx_nic *efx,
247 struct efx_special_buffer *buffer)
248{
249 efx_qword_t buf_desc;
250 int index;
251 dma_addr_t dma_addr;
252 int i;
253
254 EFX_BUG_ON_PARANOID(!buffer->addr);
255
256 /* Write buffer descriptors to NIC */
257 for (i = 0; i < buffer->entries; i++) {
258 index = buffer->index + i;
259 dma_addr = buffer->dma_addr + (i * 4096);
260 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
261 index, (unsigned long long)dma_addr);
262 EFX_POPULATE_QWORD_4(buf_desc,
263 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
264 BUF_ADR_REGION, 0,
265 BUF_ADR_FBUF, (dma_addr >> 12),
266 BUF_OWNER_ID_FBUF, 0);
267 falcon_write_sram(efx, &buf_desc, index);
268 }
269
270 return 0;
271}
272
273/* Unmaps a buffer from Falcon and clears the buffer table entries */
274static void
275falcon_fini_special_buffer(struct efx_nic *efx,
276 struct efx_special_buffer *buffer)
277{
278 efx_oword_t buf_tbl_upd;
279 unsigned int start = buffer->index;
280 unsigned int end = (buffer->index + buffer->entries - 1);
281
282 if (!buffer->entries)
283 return;
284
285 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
286 buffer->index, buffer->index + buffer->entries - 1);
287
288 EFX_POPULATE_OWORD_4(buf_tbl_upd,
289 BUF_UPD_CMD, 0,
290 BUF_CLR_CMD, 1,
291 BUF_CLR_END_ID, end,
292 BUF_CLR_START_ID, start);
293 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
294}
295
296/*
297 * Allocate a new Falcon special buffer
298 *
299 * This allocates memory for a new buffer, clears it and allocates a
300 * new buffer ID range. It does not write into Falcon's buffer table.
301 *
302 * This call will allocate 4KB buffers, since Falcon can't use 8KB
303 * buffers for event queues and descriptor rings.
304 */
305static int falcon_alloc_special_buffer(struct efx_nic *efx,
306 struct efx_special_buffer *buffer,
307 unsigned int len)
308{
309 struct falcon_nic_data *nic_data = efx->nic_data;
310
311 len = ALIGN(len, FALCON_BUF_SIZE);
312
313 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
314 &buffer->dma_addr);
315 if (!buffer->addr)
316 return -ENOMEM;
317 buffer->len = len;
318 buffer->entries = len / FALCON_BUF_SIZE;
319 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
320
321 /* All zeros is a potentially valid event so memset to 0xff */
322 memset(buffer->addr, 0xff, len);
323
324 /* Select new buffer ID */
325 buffer->index = nic_data->next_buffer_table;
326 nic_data->next_buffer_table += buffer->entries;
327
328 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
329 "(virt %p phys %lx)\n", buffer->index,
330 buffer->index + buffer->entries - 1,
331 (unsigned long long)buffer->dma_addr, len,
332 buffer->addr, virt_to_phys(buffer->addr));
333
334 return 0;
335}
336
337static void falcon_free_special_buffer(struct efx_nic *efx,
338 struct efx_special_buffer *buffer)
339{
340 if (!buffer->addr)
341 return;
342
343 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
344 "(virt %p phys %lx)\n", buffer->index,
345 buffer->index + buffer->entries - 1,
346 (unsigned long long)buffer->dma_addr, buffer->len,
347 buffer->addr, virt_to_phys(buffer->addr));
348
349 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
350 buffer->dma_addr);
351 buffer->addr = NULL;
352 buffer->entries = 0;
353}
354
355/**************************************************************************
356 *
357 * Falcon generic buffer handling
358 * These buffers are used for interrupt status and MAC stats
359 *
360 **************************************************************************/
361
362static int falcon_alloc_buffer(struct efx_nic *efx,
363 struct efx_buffer *buffer, unsigned int len)
364{
365 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
366 &buffer->dma_addr);
367 if (!buffer->addr)
368 return -ENOMEM;
369 buffer->len = len;
370 memset(buffer->addr, 0, len);
371 return 0;
372}
373
374static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
375{
376 if (buffer->addr) {
377 pci_free_consistent(efx->pci_dev, buffer->len,
378 buffer->addr, buffer->dma_addr);
379 buffer->addr = NULL;
380 }
381}
382
383/**************************************************************************
384 *
385 * Falcon TX path
386 *
387 **************************************************************************/
388
389/* Returns a pointer to the specified transmit descriptor in the TX
390 * descriptor queue belonging to the specified channel.
391 */
392static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
393 unsigned int index)
394{
395 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
396}
397
398/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
399static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
400{
401 unsigned write_ptr;
402 efx_dword_t reg;
403
404 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
405 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
406 falcon_writel_page(tx_queue->efx, &reg,
407 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
408}
409
410
411/* For each entry inserted into the software descriptor ring, create a
412 * descriptor in the hardware TX descriptor ring (in host memory), and
413 * write a doorbell.
414 */
415void falcon_push_buffers(struct efx_tx_queue *tx_queue)
416{
417
418 struct efx_tx_buffer *buffer;
419 efx_qword_t *txd;
420 unsigned write_ptr;
421
422 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
423
424 do {
425 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
426 buffer = &tx_queue->buffer[write_ptr];
427 txd = falcon_tx_desc(tx_queue, write_ptr);
428 ++tx_queue->write_count;
429
430 /* Create TX descriptor ring entry */
431 EFX_POPULATE_QWORD_5(*txd,
432 TX_KER_PORT, 0,
433 TX_KER_CONT, buffer->continuation,
434 TX_KER_BYTE_CNT, buffer->len,
435 TX_KER_BUF_REGION, 0,
436 TX_KER_BUF_ADR, buffer->dma_addr);
437 } while (tx_queue->write_count != tx_queue->insert_count);
438
439 wmb(); /* Ensure descriptors are written before they are fetched */
440 falcon_notify_tx_desc(tx_queue);
441}
442
443/* Allocate hardware resources for a TX queue */
444int falcon_probe_tx(struct efx_tx_queue *tx_queue)
445{
446 struct efx_nic *efx = tx_queue->efx;
447 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
448 FALCON_TXD_RING_SIZE *
449 sizeof(efx_qword_t));
450}
451
452int falcon_init_tx(struct efx_tx_queue *tx_queue)
453{
454 efx_oword_t tx_desc_ptr;
455 struct efx_nic *efx = tx_queue->efx;
456 int rc;
457
458 /* Pin TX descriptor ring */
459 rc = falcon_init_special_buffer(efx, &tx_queue->txd);
460 if (rc)
461 return rc;
462
463 /* Push TX descriptor ring to card */
464 EFX_POPULATE_OWORD_10(tx_desc_ptr,
465 TX_DESCQ_EN, 1,
466 TX_ISCSI_DDIG_EN, 0,
467 TX_ISCSI_HDIG_EN, 0,
468 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
469 TX_DESCQ_EVQ_ID, tx_queue->channel->evqnum,
470 TX_DESCQ_OWNER_ID, 0,
471 TX_DESCQ_LABEL, tx_queue->queue,
472 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
473 TX_DESCQ_TYPE, 0,
474 TX_NON_IP_DROP_DIS_B0, 1);
475
55668611 476 if (falcon_rev(efx) >= FALCON_REV_B0) {
60ac1065
BH		 477 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
478 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
479 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
8ceee660
BH		 480 }
481
482 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
483 tx_queue->queue);
484
55668611 485 if (falcon_rev(efx) < FALCON_REV_B0) {
8ceee660
BH		 486 efx_oword_t reg;
487
60ac1065
BH		 488 /* Only 128 bits in this register */
489 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
8ceee660
BH		 490
491 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
60ac1065 492 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
8ceee660
BH		 493 clear_bit_le(tx_queue->queue, (void *)&reg);
494 else
495 set_bit_le(tx_queue->queue, (void *)&reg);
496 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
497 }
498
499 return 0;
500}
501
502static int falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
503{
504 struct efx_nic *efx = tx_queue->efx;
505 struct efx_channel *channel = &efx->channel[0];
506 efx_oword_t tx_flush_descq;
507 unsigned int read_ptr, i;
508
509 /* Post a flush command */
510 EFX_POPULATE_OWORD_2(tx_flush_descq,
511 TX_FLUSH_DESCQ_CMD, 1,
512 TX_FLUSH_DESCQ, tx_queue->queue);
513 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
514 msleep(FALCON_FLUSH_TIMEOUT);
515
516 if (EFX_WORKAROUND_7803(efx))
517 return 0;
518
519 /* Look for a flush completed event */
520 read_ptr = channel->eventq_read_ptr;
521 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
522 efx_qword_t *event = falcon_event(channel, read_ptr);
523 int ev_code, ev_sub_code, ev_queue;
524 if (!falcon_event_present(event))
525 break;
526
527 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
528 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
529 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_TX_DESCQ_ID);
530 if ((ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) &&
531 (ev_queue == tx_queue->queue)) {
532 EFX_LOG(efx, "tx queue %d flush command succesful\n",
533 tx_queue->queue);
534 return 0;
535 }
536
537 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
538 }
539
540 if (EFX_WORKAROUND_11557(efx)) {
541 efx_oword_t reg;
dc8cfa55 542 bool enabled;
8ceee660
BH		 543
544 falcon_read_table(efx, &reg, efx->type->txd_ptr_tbl_base,
545 tx_queue->queue);
546 enabled = EFX_OWORD_FIELD(reg, TX_DESCQ_EN);
547 if (!enabled) {
548 EFX_LOG(efx, "tx queue %d disabled without a "
549 "flush event seen\n", tx_queue->queue);
550 return 0;
551 }
552 }
553
554 EFX_ERR(efx, "tx queue %d flush command timed out\n", tx_queue->queue);
555 return -ETIMEDOUT;
556}
557
558void falcon_fini_tx(struct efx_tx_queue *tx_queue)
559{
560 struct efx_nic *efx = tx_queue->efx;
561 efx_oword_t tx_desc_ptr;
562
563 /* Stop the hardware using the queue */
564 if (falcon_flush_tx_queue(tx_queue))
565 EFX_ERR(efx, "failed to flush tx queue %d\n", tx_queue->queue);
566
567 /* Remove TX descriptor ring from card */
568 EFX_ZERO_OWORD(tx_desc_ptr);
569 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
570 tx_queue->queue);
571
572 /* Unpin TX descriptor ring */
573 falcon_fini_special_buffer(efx, &tx_queue->txd);
574}
575
576/* Free buffers backing TX queue */
577void falcon_remove_tx(struct efx_tx_queue *tx_queue)
578{
579 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
580}
581
582/**************************************************************************
583 *
584 * Falcon RX path
585 *
586 **************************************************************************/
587
588/* Returns a pointer to the specified descriptor in the RX descriptor queue */
589static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
590 unsigned int index)
591{
592 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
593}
594
595/* This creates an entry in the RX descriptor queue */
596static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
597 unsigned index)
598{
599 struct efx_rx_buffer *rx_buf;
600 efx_qword_t *rxd;
601
602 rxd = falcon_rx_desc(rx_queue, index);
603 rx_buf = efx_rx_buffer(rx_queue, index);
604 EFX_POPULATE_QWORD_3(*rxd,
605 RX_KER_BUF_SIZE,
606 rx_buf->len -
607 rx_queue->efx->type->rx_buffer_padding,
608 RX_KER_BUF_REGION, 0,
609 RX_KER_BUF_ADR, rx_buf->dma_addr);
610}
611
612/* This writes to the RX_DESC_WPTR register for the specified receive
613 * descriptor ring.
614 */
615void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
616{
617 efx_dword_t reg;
618 unsigned write_ptr;
619
620 while (rx_queue->notified_count != rx_queue->added_count) {
621 falcon_build_rx_desc(rx_queue,
622 rx_queue->notified_count &
623 FALCON_RXD_RING_MASK);
624 ++rx_queue->notified_count;
625 }
626
627 wmb();
628 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
629 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
630 falcon_writel_page(rx_queue->efx, &reg,
631 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
632}
633
634int falcon_probe_rx(struct efx_rx_queue *rx_queue)
635{
636 struct efx_nic *efx = rx_queue->efx;
637 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
638 FALCON_RXD_RING_SIZE *
639 sizeof(efx_qword_t));
640}
641
642int falcon_init_rx(struct efx_rx_queue *rx_queue)
643{
644 efx_oword_t rx_desc_ptr;
645 struct efx_nic *efx = rx_queue->efx;
646 int rc;
dc8cfa55
BH		 647 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
648 bool iscsi_digest_en = is_b0;
8ceee660
BH		 649
650 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
651 rx_queue->queue, rx_queue->rxd.index,
652 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
653
654 /* Pin RX descriptor ring */
655 rc = falcon_init_special_buffer(efx, &rx_queue->rxd);
656 if (rc)
657 return rc;
658
659 /* Push RX descriptor ring to card */
660 EFX_POPULATE_OWORD_10(rx_desc_ptr,
661 RX_ISCSI_DDIG_EN, iscsi_digest_en,
662 RX_ISCSI_HDIG_EN, iscsi_digest_en,
663 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
664 RX_DESCQ_EVQ_ID, rx_queue->channel->evqnum,
665 RX_DESCQ_OWNER_ID, 0,
666 RX_DESCQ_LABEL, rx_queue->queue,
667 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
668 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
669 /* For >=B0 this is scatter so disable */
670 RX_DESCQ_JUMBO, !is_b0,
671 RX_DESCQ_EN, 1);
672 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
673 rx_queue->queue);
674 return 0;
675}
676
677static int falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
678{
679 struct efx_nic *efx = rx_queue->efx;
680 struct efx_channel *channel = &efx->channel[0];
681 unsigned int read_ptr, i;
682 efx_oword_t rx_flush_descq;
683
684 /* Post a flush command */
685 EFX_POPULATE_OWORD_2(rx_flush_descq,
686 RX_FLUSH_DESCQ_CMD, 1,
687 RX_FLUSH_DESCQ, rx_queue->queue);
688 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
689 msleep(FALCON_FLUSH_TIMEOUT);
690
691 if (EFX_WORKAROUND_7803(efx))
692 return 0;
693
694 /* Look for a flush completed event */
695 read_ptr = channel->eventq_read_ptr;
696 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
697 efx_qword_t *event = falcon_event(channel, read_ptr);
dc8cfa55
BH		 698 int ev_code, ev_sub_code, ev_queue;
699 bool ev_failed;
8ceee660
BH		 700 if (!falcon_event_present(event))
701 break;
702
703 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
704 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
705 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_DESCQ_ID);
706 ev_failed = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_FLUSH_FAIL);
707
708 if ((ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) &&
709 (ev_queue == rx_queue->queue)) {
710 if (ev_failed) {
711 EFX_INFO(efx, "rx queue %d flush command "
712 "failed\n", rx_queue->queue);
713 return -EAGAIN;
714 } else {
715 EFX_LOG(efx, "rx queue %d flush command "
716 "succesful\n", rx_queue->queue);
717 return 0;
718 }
719 }
720
721 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
722 }
723
724 if (EFX_WORKAROUND_11557(efx)) {
725 efx_oword_t reg;
dc8cfa55 726 bool enabled;
8ceee660
BH		 727
728 falcon_read_table(efx, &reg, efx->type->rxd_ptr_tbl_base,
729 rx_queue->queue);
730 enabled = EFX_OWORD_FIELD(reg, RX_DESCQ_EN);
731 if (!enabled) {
732 EFX_LOG(efx, "rx queue %d disabled without a "
733 "flush event seen\n", rx_queue->queue);
734 return 0;
735 }
736 }
737
738 EFX_ERR(efx, "rx queue %d flush command timed out\n", rx_queue->queue);
739 return -ETIMEDOUT;
740}
741
742void falcon_fini_rx(struct efx_rx_queue *rx_queue)
743{
744 efx_oword_t rx_desc_ptr;
745 struct efx_nic *efx = rx_queue->efx;
746 int i, rc;
747
748 /* Try and flush the rx queue. This may need to be repeated */
749 for (i = 0; i < 5; i++) {
750 rc = falcon_flush_rx_queue(rx_queue);
751 if (rc == -EAGAIN)
752 continue;
753 break;
754 }
23bdfdd3 755 if (rc) {
8ceee660 756 EFX_ERR(efx, "failed to flush rx queue %d\n", rx_queue->queue);
23bdfdd3
SH		 757 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
758 }
8ceee660
BH		 759
760 /* Remove RX descriptor ring from card */
761 EFX_ZERO_OWORD(rx_desc_ptr);
762 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
763 rx_queue->queue);
764
765 /* Unpin RX descriptor ring */
766 falcon_fini_special_buffer(efx, &rx_queue->rxd);
767}
768
769/* Free buffers backing RX queue */
770void falcon_remove_rx(struct efx_rx_queue *rx_queue)
771{
772 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
773}
774
775/**************************************************************************
776 *
777 * Falcon event queue processing
778 * Event queues are processed by per-channel tasklets.
779 *
780 **************************************************************************/
781
782/* Update a channel's event queue's read pointer (RPTR) register
783 *
784 * This writes the EVQ_RPTR_REG register for the specified channel's
785 * event queue.
786 *
787 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
788 * whereas channel->eventq_read_ptr contains the index of the "next to
789 * read" event.
790 */
791void falcon_eventq_read_ack(struct efx_channel *channel)
792{
793 efx_dword_t reg;
794 struct efx_nic *efx = channel->efx;
795
796 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
797 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
798 channel->evqnum);
799}
800
801/* Use HW to insert a SW defined event */
802void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
803{
804 efx_oword_t drv_ev_reg;
805
806 EFX_POPULATE_OWORD_2(drv_ev_reg,
807 DRV_EV_QID, channel->evqnum,
808 DRV_EV_DATA,
809 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
810 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
811}
812
813/* Handle a transmit completion event
814 *
815 * Falcon batches TX completion events; the message we receive is of
816 * the form "complete all TX events up to this index".
817 */
4d566063
BH		 818static void falcon_handle_tx_event(struct efx_channel *channel,
819 efx_qword_t *event)
8ceee660
BH		 820{
821 unsigned int tx_ev_desc_ptr;
822 unsigned int tx_ev_q_label;
823 struct efx_tx_queue *tx_queue;
824 struct efx_nic *efx = channel->efx;
825
826 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
827 /* Transmit completion */
828 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
829 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
830 tx_queue = &efx->tx_queue[tx_ev_q_label];
831 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
832 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
833 /* Rewrite the FIFO write pointer */
834 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
835 tx_queue = &efx->tx_queue[tx_ev_q_label];
836
55668611 837 if (efx_dev_registered(efx))
8ceee660
BH		 838 netif_tx_lock(efx->net_dev);
839 falcon_notify_tx_desc(tx_queue);
55668611 840 if (efx_dev_registered(efx))
8ceee660
BH		 841 netif_tx_unlock(efx->net_dev);
842 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
843 EFX_WORKAROUND_10727(efx)) {
844 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
845 } else {
846 EFX_ERR(efx, "channel %d unexpected TX event "
847 EFX_QWORD_FMT"\n", channel->channel,
848 EFX_QWORD_VAL(*event));
849 }
850}
851
8ceee660
BH		 852/* Detect errors included in the rx_evt_pkt_ok bit. */
853static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
854 const efx_qword_t *event,
dc8cfa55
BH		 855 bool *rx_ev_pkt_ok,
856 bool *discard)
8ceee660
BH		 857{
858 struct efx_nic *efx = rx_queue->efx;
dc8cfa55
BH		 859 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
860 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
861 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
862 bool rx_ev_other_err, rx_ev_pause_frm;
863 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
864 unsigned rx_ev_pkt_type;
8ceee660
BH		 865
866 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
867 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
868 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
869 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
870 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
871 RX_EV_BUF_OWNER_ID_ERR);
872 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
873 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
874 RX_EV_IP_HDR_CHKSUM_ERR);
875 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
876 RX_EV_TCP_UDP_CHKSUM_ERR);
877 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
878 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
55668611 879 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
8ceee660
BH		 880 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
881 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
882
883 /* Every error apart from tobe_disc and pause_frm */
884 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
885 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
886 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
887
8ceee660
BH		 888 /* Count errors that are not in MAC stats. */
889 if (rx_ev_frm_trunc)
890 ++rx_queue->channel->n_rx_frm_trunc;
891 else if (rx_ev_tobe_disc)
892 ++rx_queue->channel->n_rx_tobe_disc;
893 else if (rx_ev_ip_hdr_chksum_err)
894 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
895 else if (rx_ev_tcp_udp_chksum_err)
896 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
897 if (rx_ev_ip_frag_err)
898 ++rx_queue->channel->n_rx_ip_frag_err;
899
900 /* The frame must be discarded if any of these are true. */
901 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
902 rx_ev_tobe_disc | rx_ev_pause_frm);
903
904 /* TOBE_DISC is expected on unicast mismatches; don't print out an
905 * error message. FRM_TRUNC indicates RXDP dropped the packet due
906 * to a FIFO overflow.
907 */
908#ifdef EFX_ENABLE_DEBUG
909 if (rx_ev_other_err) {
910 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
5b39fe30 911 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
8ceee660
BH		 912 rx_queue->queue, EFX_QWORD_VAL(*event),
913 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
914 rx_ev_ip_hdr_chksum_err ?
915 " [IP_HDR_CHKSUM_ERR]" : "",
916 rx_ev_tcp_udp_chksum_err ?
917 " [TCP_UDP_CHKSUM_ERR]" : "",
918 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
919 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
920 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
921 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
5b39fe30 922 rx_ev_pause_frm ? " [PAUSE]" : "");
8ceee660
BH		 923 }
924#endif
925
926 if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
927 efx->phy_type == PHY_TYPE_10XPRESS))
928 tenxpress_crc_err(efx);
929}
930
931/* Handle receive events that are not in-order. */
932static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
933 unsigned index)
934{
935 struct efx_nic *efx = rx_queue->efx;
936 unsigned expected, dropped;
937
938 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
939 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
940 FALCON_RXD_RING_MASK);
941 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
942 dropped, index, expected);
943
944 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
945 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
946}
947
948/* Handle a packet received event
949 *
950 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
951 * wrong destination address
952 * Also "is multicast" and "matches multicast filter" flags can be used to
953 * discard non-matching multicast packets.
954 */
4d566063
BH		 955static int falcon_handle_rx_event(struct efx_channel *channel,
956 const efx_qword_t *event)
8ceee660
BH		 957{
958 unsigned int rx_ev_q_label, rx_ev_desc_ptr, rx_ev_byte_cnt;
dc8cfa55 959 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
8ceee660 960 unsigned expected_ptr;
dc8cfa55 961 bool rx_ev_pkt_ok, discard = false, checksummed;
8ceee660
BH		 962 struct efx_rx_queue *rx_queue;
963 struct efx_nic *efx = channel->efx;
964
965 /* Basic packet information */
966 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
967 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
968 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
969 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
970 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
971
972 rx_ev_q_label = EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL);
973 rx_queue = &efx->rx_queue[rx_ev_q_label];
974
975 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
976 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
977 if (unlikely(rx_ev_desc_ptr != expected_ptr)) {
978 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
979 return rx_ev_q_label;
980 }
981
982 if (likely(rx_ev_pkt_ok)) {
983 /* If packet is marked as OK and packet type is TCP/IPv4 or
984 * UDP/IPv4, then we can rely on the hardware checksum.
985 */
986 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
987 } else {
988 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
5b39fe30 989 &discard);
dc8cfa55 990 checksummed = false;
8ceee660
BH		 991 }
992
993 /* Detect multicast packets that didn't match the filter */
994 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
995 if (rx_ev_mcast_pkt) {
996 unsigned int rx_ev_mcast_hash_match =
997 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
998
999 if (unlikely(!rx_ev_mcast_hash_match))
dc8cfa55 1000 discard = true;
8ceee660
BH		 1001 }
1002
1003 /* Handle received packet */
1004 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
1005 checksummed, discard);
1006
1007 return rx_ev_q_label;
1008}
1009
1010/* Global events are basically PHY events */
1011static void falcon_handle_global_event(struct efx_channel *channel,
1012 efx_qword_t *event)
1013{
1014 struct efx_nic *efx = channel->efx;
dc8cfa55 1015 bool is_phy_event = false, handled = false;
8ceee660
BH		 1016
1017 /* Check for interrupt on either port. Some boards have a
1018 * single PHY wired to the interrupt line for port 1. */
1019 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
1020 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
1021 EFX_QWORD_FIELD(*event, XG_PHY_INTR))
dc8cfa55 1022 is_phy_event = true;
8ceee660 1023
55668611 1024 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
8ceee660 1025 EFX_OWORD_FIELD(*event, XG_MNT_INTR_B0))
dc8cfa55 1026 is_phy_event = true;
8ceee660
BH		 1027
1028 if (is_phy_event) {
1029 efx->phy_op->clear_interrupt(efx);
1030 queue_work(efx->workqueue, &efx->reconfigure_work);
dc8cfa55 1031 handled = true;
8ceee660
BH		 1032 }
1033
1034 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
1035 EFX_ERR(efx, "channel %d seen global RX_RESET "
1036 "event. Resetting.\n", channel->channel);
1037
1038 atomic_inc(&efx->rx_reset);
1039 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1040 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
dc8cfa55 1041 handled = true;
8ceee660
BH		 1042 }
1043
1044 if (!handled)
1045 EFX_ERR(efx, "channel %d unknown global event "
1046 EFX_QWORD_FMT "\n", channel->channel,
1047 EFX_QWORD_VAL(*event));
1048}
1049
1050static void falcon_handle_driver_event(struct efx_channel *channel,
1051 efx_qword_t *event)
1052{
1053 struct efx_nic *efx = channel->efx;
1054 unsigned int ev_sub_code;
1055 unsigned int ev_sub_data;
1056
1057 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1058 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
1059
1060 switch (ev_sub_code) {
1061 case TX_DESCQ_FLS_DONE_EV_DECODE:
1062 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
1063 channel->channel, ev_sub_data);
1064 break;
1065 case RX_DESCQ_FLS_DONE_EV_DECODE:
1066 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
1067 channel->channel, ev_sub_data);
1068 break;
1069 case EVQ_INIT_DONE_EV_DECODE:
1070 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
1071 channel->channel, ev_sub_data);
1072 break;
1073 case SRM_UPD_DONE_EV_DECODE:
1074 EFX_TRACE(efx, "channel %d SRAM update done\n",
1075 channel->channel);
1076 break;
1077 case WAKE_UP_EV_DECODE:
1078 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
1079 channel->channel, ev_sub_data);
1080 break;
1081 case TIMER_EV_DECODE:
1082 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
1083 channel->channel, ev_sub_data);
1084 break;
1085 case RX_RECOVERY_EV_DECODE:
1086 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
1087 "Resetting.\n", channel->channel);
05e3ec04 1088 atomic_inc(&efx->rx_reset);
8ceee660
BH		 1089 efx_schedule_reset(efx,
1090 EFX_WORKAROUND_6555(efx) ?
1091 RESET_TYPE_RX_RECOVERY :
1092 RESET_TYPE_DISABLE);
1093 break;
1094 case RX_DSC_ERROR_EV_DECODE:
1095 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
1096 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1097 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1098 break;
1099 case TX_DSC_ERROR_EV_DECODE:
1100 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1101 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1102 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1103 break;
1104 default:
1105 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1106 "data %04x\n", channel->channel, ev_sub_code,
1107 ev_sub_data);
1108 break;
1109 }
1110}
1111
1112int falcon_process_eventq(struct efx_channel *channel, int *rx_quota)
1113{
1114 unsigned int read_ptr;
1115 efx_qword_t event, *p_event;
1116 int ev_code;
1117 int rxq;
1118 int rxdmaqs = 0;
1119
1120 read_ptr = channel->eventq_read_ptr;
1121
1122 do {
1123 p_event = falcon_event(channel, read_ptr);
1124 event = *p_event;
1125
1126 if (!falcon_event_present(&event))
1127 /* End of events */
1128 break;
1129
1130 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1131 channel->channel, EFX_QWORD_VAL(event));
1132
1133 /* Clear this event by marking it all ones */
1134 EFX_SET_QWORD(*p_event);
1135
1136 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1137
1138 switch (ev_code) {
1139 case RX_IP_EV_DECODE:
1140 rxq = falcon_handle_rx_event(channel, &event);
1141 rxdmaqs |= (1 << rxq);
1142 (*rx_quota)--;
1143 break;
1144 case TX_IP_EV_DECODE:
1145 falcon_handle_tx_event(channel, &event);
1146 break;
1147 case DRV_GEN_EV_DECODE:
1148 channel->eventq_magic
1149 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1150 EFX_LOG(channel->efx, "channel %d received generated "
1151 "event "EFX_QWORD_FMT"\n", channel->channel,
1152 EFX_QWORD_VAL(event));
1153 break;
1154 case GLOBAL_EV_DECODE:
1155 falcon_handle_global_event(channel, &event);
1156 break;
1157 case DRIVER_EV_DECODE:
1158 falcon_handle_driver_event(channel, &event);
1159 break;
1160 default:
1161 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1162 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1163 ev_code, EFX_QWORD_VAL(event));
1164 }
1165
1166 /* Increment read pointer */
1167 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1168
1169 } while (*rx_quota);
1170
1171 channel->eventq_read_ptr = read_ptr;
1172 return rxdmaqs;
1173}
1174
1175void falcon_set_int_moderation(struct efx_channel *channel)
1176{
1177 efx_dword_t timer_cmd;
1178 struct efx_nic *efx = channel->efx;
1179
1180 /* Set timer register */
1181 if (channel->irq_moderation) {
1182 /* Round to resolution supported by hardware. The value we
1183 * program is based at 0. So actual interrupt moderation
1184 * achieved is ((x + 1) * res).
1185 */
1186 unsigned int res = 5;
1187 channel->irq_moderation -= (channel->irq_moderation % res);
1188 if (channel->irq_moderation < res)
1189 channel->irq_moderation = res;
1190 EFX_POPULATE_DWORD_2(timer_cmd,
1191 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1192 TIMER_VAL,
1193 (channel->irq_moderation / res) - 1);
1194 } else {
1195 EFX_POPULATE_DWORD_2(timer_cmd,
1196 TIMER_MODE, TIMER_MODE_DIS,
1197 TIMER_VAL, 0);
1198 }
1199 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1200 channel->evqnum);
1201
1202}
1203
1204/* Allocate buffer table entries for event queue */
1205int falcon_probe_eventq(struct efx_channel *channel)
1206{
1207 struct efx_nic *efx = channel->efx;
1208 unsigned int evq_size;
1209
1210 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1211 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1212}
1213
1214int falcon_init_eventq(struct efx_channel *channel)
1215{
1216 efx_oword_t evq_ptr;
1217 struct efx_nic *efx = channel->efx;
1218 int rc;
1219
1220 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1221 channel->channel, channel->eventq.index,
1222 channel->eventq.index + channel->eventq.entries - 1);
1223
1224 /* Pin event queue buffer */
1225 rc = falcon_init_special_buffer(efx, &channel->eventq);
1226 if (rc)
1227 return rc;
1228
1229 /* Fill event queue with all ones (i.e. empty events) */
1230 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1231
1232 /* Push event queue to card */
1233 EFX_POPULATE_OWORD_3(evq_ptr,
1234 EVQ_EN, 1,
1235 EVQ_SIZE, FALCON_EVQ_ORDER,
1236 EVQ_BUF_BASE_ID, channel->eventq.index);
1237 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1238 channel->evqnum);
1239
1240 falcon_set_int_moderation(channel);
1241
1242 return 0;
1243}
1244
1245void falcon_fini_eventq(struct efx_channel *channel)
1246{
1247 efx_oword_t eventq_ptr;
1248 struct efx_nic *efx = channel->efx;
1249
1250 /* Remove event queue from card */
1251 EFX_ZERO_OWORD(eventq_ptr);
1252 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1253 channel->evqnum);
1254
1255 /* Unpin event queue */
1256 falcon_fini_special_buffer(efx, &channel->eventq);
1257}
1258
1259/* Free buffers backing event queue */
1260void falcon_remove_eventq(struct efx_channel *channel)
1261{
1262 falcon_free_special_buffer(channel->efx, &channel->eventq);
1263}
1264
1265
1266/* Generates a test event on the event queue. A subsequent call to
1267 * process_eventq() should pick up the event and place the value of
1268 * "magic" into channel->eventq_magic;
1269 */
1270void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1271{
1272 efx_qword_t test_event;
1273
1274 EFX_POPULATE_QWORD_2(test_event,
1275 EV_CODE, DRV_GEN_EV_DECODE,
1276 EVQ_MAGIC, magic);
1277 falcon_generate_event(channel, &test_event);
1278}
1279
1280
1281/**************************************************************************
1282 *
1283 * Falcon hardware interrupts
1284 * The hardware interrupt handler does very little work; all the event
1285 * queue processing is carried out by per-channel tasklets.
1286 *
1287 **************************************************************************/
1288
1289/* Enable/disable/generate Falcon interrupts */
1290static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1291 int force)
1292{
1293 efx_oword_t int_en_reg_ker;
1294
1295 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1296 KER_INT_KER, force,
1297 DRV_INT_EN_KER, enabled);
1298 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1299}
1300
1301void falcon_enable_interrupts(struct efx_nic *efx)
1302{
1303 efx_oword_t int_adr_reg_ker;
1304 struct efx_channel *channel;
1305
1306 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1307 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1308
1309 /* Program address */
1310 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1311 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1312 INT_ADR_KER, efx->irq_status.dma_addr);
1313 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1314
1315 /* Enable interrupts */
1316 falcon_interrupts(efx, 1, 0);
1317
1318 /* Force processing of all the channels to get the EVQ RPTRs up to
1319 date */
1320 efx_for_each_channel_with_interrupt(channel, efx)
1321 efx_schedule_channel(channel);
1322}
1323
1324void falcon_disable_interrupts(struct efx_nic *efx)
1325{
1326 /* Disable interrupts */
1327 falcon_interrupts(efx, 0, 0);
1328}
1329
1330/* Generate a Falcon test interrupt
1331 * Interrupt must already have been enabled, otherwise nasty things
1332 * may happen.
1333 */
1334void falcon_generate_interrupt(struct efx_nic *efx)
1335{
1336 falcon_interrupts(efx, 1, 1);
1337}
1338
1339/* Acknowledge a legacy interrupt from Falcon
1340 *
1341 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1342 *
1343 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1344 * BIU. Interrupt acknowledge is read sensitive so must write instead
1345 * (then read to ensure the BIU collector is flushed)
1346 *
1347 * NB most hardware supports MSI interrupts
1348 */
1349static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1350{
1351 efx_dword_t reg;
1352
1353 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1354 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1355 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1356}
1357
1358/* Process a fatal interrupt
1359 * Disable bus mastering ASAP and schedule a reset
1360 */
1361static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1362{
1363 struct falcon_nic_data *nic_data = efx->nic_data;
d3208b5e 1364 efx_oword_t *int_ker = efx->irq_status.addr;
8ceee660
BH		 1365 efx_oword_t fatal_intr;
1366 int error, mem_perr;
1367 static int n_int_errors;
1368
1369 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1370 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1371
1372 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1373 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1374 EFX_OWORD_VAL(fatal_intr),
1375 error ? "disabling bus mastering" : "no recognised error");
1376 if (error == 0)
1377 goto out;
1378
1379 /* If this is a memory parity error dump which blocks are offending */
1380 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1381 if (mem_perr) {
1382 efx_oword_t reg;
1383 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1384 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1385 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1386 }
1387
1388 /* Disable DMA bus mastering on both devices */
1389 pci_disable_device(efx->pci_dev);
1390 if (FALCON_IS_DUAL_FUNC(efx))
1391 pci_disable_device(nic_data->pci_dev2);
1392
1393 if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1394 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1395 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1396 } else {
1397 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1398 "NIC will be disabled\n");
1399 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1400 }
1401out:
1402 return IRQ_HANDLED;
1403}
1404
1405/* Handle a legacy interrupt from Falcon
1406 * Acknowledges the interrupt and schedule event queue processing.
1407 */
1408static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1409{
d3208b5e
BH		 1410 struct efx_nic *efx = dev_id;
1411 efx_oword_t *int_ker = efx->irq_status.addr;
8ceee660
BH		 1412 struct efx_channel *channel;
1413 efx_dword_t reg;
1414 u32 queues;
1415 int syserr;
1416
1417 /* Read the ISR which also ACKs the interrupts */
1418 falcon_readl(efx, &reg, INT_ISR0_B0);
1419 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1420
1421 /* Check to see if we have a serious error condition */
1422 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1423 if (unlikely(syserr))
1424 return falcon_fatal_interrupt(efx);
1425
1426 if (queues == 0)
1427 return IRQ_NONE;
1428
1429 efx->last_irq_cpu = raw_smp_processor_id();
1430 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1431 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1432
1433 /* Schedule processing of any interrupting queues */
1434 channel = &efx->channel[0];
1435 while (queues) {
1436 if (queues & 0x01)
1437 efx_schedule_channel(channel);
1438 channel++;
1439 queues >>= 1;
1440 }
1441
1442 return IRQ_HANDLED;
1443}
1444
1445
1446static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1447{
d3208b5e
BH		 1448 struct efx_nic *efx = dev_id;
1449 efx_oword_t *int_ker = efx->irq_status.addr;
8ceee660
BH		 1450 struct efx_channel *channel;
1451 int syserr;
1452 int queues;
1453
1454 /* Check to see if this is our interrupt. If it isn't, we
1455 * exit without having touched the hardware.
1456 */
1457 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1458 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1459 raw_smp_processor_id());
1460 return IRQ_NONE;
1461 }
1462 efx->last_irq_cpu = raw_smp_processor_id();
1463 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1464 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1465
1466 /* Check to see if we have a serious error condition */
1467 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1468 if (unlikely(syserr))
1469 return falcon_fatal_interrupt(efx);
1470
1471 /* Determine interrupting queues, clear interrupt status
1472 * register and acknowledge the device interrupt.
1473 */
1474 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1475 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1476 EFX_ZERO_OWORD(*int_ker);
1477 wmb(); /* Ensure the vector is cleared before interrupt ack */
1478 falcon_irq_ack_a1(efx);
1479
1480 /* Schedule processing of any interrupting queues */
1481 channel = &efx->channel[0];
1482 while (queues) {
1483 if (queues & 0x01)
1484 efx_schedule_channel(channel);
1485 channel++;
1486 queues >>= 1;
1487 }
1488
1489 return IRQ_HANDLED;
1490}
1491
1492/* Handle an MSI interrupt from Falcon
1493 *
1494 * Handle an MSI hardware interrupt. This routine schedules event
1495 * queue processing. No interrupt acknowledgement cycle is necessary.
1496 * Also, we never need to check that the interrupt is for us, since
1497 * MSI interrupts cannot be shared.
1498 */
1499static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1500{
d3208b5e 1501 struct efx_channel *channel = dev_id;
8ceee660 1502 struct efx_nic *efx = channel->efx;
d3208b5e 1503 efx_oword_t *int_ker = efx->irq_status.addr;
8ceee660
BH		 1504 int syserr;
1505
1506 efx->last_irq_cpu = raw_smp_processor_id();
1507 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1508 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1509
1510 /* Check to see if we have a serious error condition */
1511 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1512 if (unlikely(syserr))
1513 return falcon_fatal_interrupt(efx);
1514
1515 /* Schedule processing of the channel */
1516 efx_schedule_channel(channel);
1517
1518 return IRQ_HANDLED;
1519}
1520
1521
1522/* Setup RSS indirection table.
1523 * This maps from the hash value of the packet to RXQ
1524 */
1525static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1526{
1527 int i = 0;
1528 unsigned long offset;
1529 efx_dword_t dword;
1530
55668611 1531 if (falcon_rev(efx) < FALCON_REV_B0)
8ceee660
BH		 1532 return;
1533
1534 for (offset = RX_RSS_INDIR_TBL_B0;
1535 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1536 offset += 0x10) {
1537 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1538 i % efx->rss_queues);
1539 falcon_writel(efx, &dword, offset);
1540 i++;
1541 }
1542}
1543
1544/* Hook interrupt handler(s)
1545 * Try MSI and then legacy interrupts.
1546 */
1547int falcon_init_interrupt(struct efx_nic *efx)
1548{
1549 struct efx_channel *channel;
1550 int rc;
1551
1552 if (!EFX_INT_MODE_USE_MSI(efx)) {
1553 irq_handler_t handler;
55668611 1554 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 1555 handler = falcon_legacy_interrupt_b0;
1556 else
1557 handler = falcon_legacy_interrupt_a1;
1558
1559 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1560 efx->name, efx);
1561 if (rc) {
1562 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1563 efx->pci_dev->irq);
1564 goto fail1;
1565 }
1566 return 0;
1567 }
1568
1569 /* Hook MSI or MSI-X interrupt */
1570 efx_for_each_channel_with_interrupt(channel, efx) {
1571 rc = request_irq(channel->irq, falcon_msi_interrupt,
1572 IRQF_PROBE_SHARED, /* Not shared */
1573 efx->name, channel);
1574 if (rc) {
1575 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1576 goto fail2;
1577 }
1578 }
1579
1580 return 0;
1581
1582 fail2:
1583 efx_for_each_channel_with_interrupt(channel, efx)
1584 free_irq(channel->irq, channel);
1585 fail1:
1586 return rc;
1587}
1588
1589void falcon_fini_interrupt(struct efx_nic *efx)
1590{
1591 struct efx_channel *channel;
1592 efx_oword_t reg;
1593
1594 /* Disable MSI/MSI-X interrupts */
b3475645 1595 efx_for_each_channel_with_interrupt(channel, efx) {
8ceee660
BH		 1596 if (channel->irq)
1597 free_irq(channel->irq, channel);
b3475645 1598 }
8ceee660
BH		 1599
1600 /* ACK legacy interrupt */
55668611 1601 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 1602 falcon_read(efx, &reg, INT_ISR0_B0);
1603 else
1604 falcon_irq_ack_a1(efx);
1605
1606 /* Disable legacy interrupt */
1607 if (efx->legacy_irq)
1608 free_irq(efx->legacy_irq, efx);
1609}
1610
1611/**************************************************************************
1612 *
1613 * EEPROM/flash
1614 *
1615 **************************************************************************
1616 */
1617
1618#define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1619
1620/* Wait for SPI command completion */
1621static int falcon_spi_wait(struct efx_nic *efx)
1622{
4a5b504d 1623 unsigned long timeout = jiffies + DIV_ROUND_UP(HZ, 10);
8ceee660 1624 efx_oword_t reg;
4a5b504d 1625 bool cmd_en, timer_active;
8ceee660 1626
4a5b504d 1627 for (;;) {
8ceee660
BH		 1628 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1629 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1630 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1631 if (!cmd_en && !timer_active)
1632 return 0;
4a5b504d
BH		 1633 if (time_after_eq(jiffies, timeout)) {
1634 EFX_ERR(efx, "timed out waiting for SPI\n");
1635 return -ETIMEDOUT;
1636 }
1637 cpu_relax();
1638 }
8ceee660
BH		 1639}
1640
4a5b504d
BH		 1641static int falcon_spi_cmd(const struct efx_spi_device *spi,
1642 unsigned int command, int address,
1643 const void *in, void *out, unsigned int len)
8ceee660 1644{
4a5b504d
BH		 1645 struct efx_nic *efx = spi->efx;
1646 bool addressed = (address >= 0);
1647 bool reading = (out != NULL);
8ceee660
BH		 1648 efx_oword_t reg;
1649 int rc;
1650
4a5b504d
BH		 1651 /* Input validation */
1652 if (len > FALCON_SPI_MAX_LEN)
1653 return -EINVAL;
8ceee660
BH		 1654
1655 /* Check SPI not currently being accessed */
1656 rc = falcon_spi_wait(efx);
1657 if (rc)
1658 return rc;
1659
4a5b504d
BH		 1660 /* Program address register, if we have an address */
1661 if (addressed) {
1662 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1663 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1664 }
1665
1666 /* Program data register, if we have data */
1667 if (in != NULL) {
1668 memcpy(&reg, in, len);
1669 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER);
1670 }
8ceee660 1671
4a5b504d 1672 /* Issue read/write command */
8ceee660
BH		 1673 EFX_POPULATE_OWORD_7(reg,
1674 EE_SPI_HCMD_CMD_EN, 1,
4a5b504d 1675 EE_SPI_HCMD_SF_SEL, spi->device_id,
8ceee660 1676 EE_SPI_HCMD_DABCNT, len,
4a5b504d 1677 EE_SPI_HCMD_READ, reading,
8ceee660 1678 EE_SPI_HCMD_DUBCNT, 0,
4a5b504d
BH		 1679 EE_SPI_HCMD_ADBCNT,
1680 (addressed ? spi->addr_len : 0),
8ceee660
BH		 1681 EE_SPI_HCMD_ENC, command);
1682 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1683
4a5b504d 1684 /* Wait for read/write to complete */
8ceee660
BH		 1685 rc = falcon_spi_wait(efx);
1686 if (rc)
1687 return rc;
1688
1689 /* Read data */
4a5b504d
BH		 1690 if (out != NULL) {
1691 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1692 memcpy(out, &reg, len);
1693 }
1694
8ceee660
BH		 1695 return 0;
1696}
1697
4a5b504d
BH		 1698static unsigned int
1699falcon_spi_write_limit(const struct efx_spi_device *spi, unsigned int start)
1700{
1701 return min(FALCON_SPI_MAX_LEN,
1702 (spi->block_size - (start & (spi->block_size - 1))));
1703}
1704
1705static inline u8
1706efx_spi_munge_command(const struct efx_spi_device *spi,
1707 const u8 command, const unsigned int address)
1708{
1709 return command | (((address >> 8) & spi->munge_address) << 3);
1710}
1711
1712
1713static int falcon_spi_fast_wait(const struct efx_spi_device *spi)
1714{
1715 u8 status;
1716 int i, rc;
1717
1718 /* Wait up to 1000us for flash/EEPROM to finish a fast operation. */
1719 for (i = 0; i < 50; i++) {
1720 udelay(20);
1721
1722 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1723 &status, sizeof(status));
1724 if (rc)
1725 return rc;
1726 if (!(status & SPI_STATUS_NRDY))
1727 return 0;
1728 }
1729 EFX_ERR(spi->efx,
1730 "timed out waiting for device %d last status=0x%02x\n",
1731 spi->device_id, status);
1732 return -ETIMEDOUT;
1733}
1734
1735int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1736 size_t len, size_t *retlen, u8 *buffer)
1737{
1738 unsigned int command, block_len, pos = 0;
1739 int rc = 0;
1740
1741 while (pos < len) {
1742 block_len = min((unsigned int)len - pos,
1743 FALCON_SPI_MAX_LEN);
1744
1745 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1746 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1747 buffer + pos, block_len);
1748 if (rc)
1749 break;
1750 pos += block_len;
1751
1752 /* Avoid locking up the system */
1753 cond_resched();
1754 if (signal_pending(current)) {
1755 rc = -EINTR;
1756 break;
1757 }
1758 }
1759
1760 if (retlen)
1761 *retlen = pos;
1762 return rc;
1763}
1764
1765int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1766 size_t len, size_t *retlen, const u8 *buffer)
1767{
1768 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1769 unsigned int command, block_len, pos = 0;
1770 int rc = 0;
1771
1772 while (pos < len) {
1773 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1774 if (rc)
1775 break;
1776
1777 block_len = min((unsigned int)len - pos,
1778 falcon_spi_write_limit(spi, start + pos));
1779 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1780 rc = falcon_spi_cmd(spi, command, start + pos,
1781 buffer + pos, NULL, block_len);
1782 if (rc)
1783 break;
1784
1785 rc = falcon_spi_fast_wait(spi);
1786 if (rc)
1787 break;
1788
1789 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1790 rc = falcon_spi_cmd(spi, command, start + pos,
1791 NULL, verify_buffer, block_len);
1792 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1793 rc = -EIO;
1794 break;
1795 }
1796
1797 pos += block_len;
1798
1799 /* Avoid locking up the system */
1800 cond_resched();
1801 if (signal_pending(current)) {
1802 rc = -EINTR;
1803 break;
1804 }
1805 }
1806
1807 if (retlen)
1808 *retlen = pos;
1809 return rc;
1810}
1811
8ceee660
BH		 1812/**************************************************************************
1813 *
1814 * MAC wrapper
1815 *
1816 **************************************************************************
1817 */
1818void falcon_drain_tx_fifo(struct efx_nic *efx)
1819{
1820 efx_oword_t temp;
1821 int count;
1822
55668611 1823 if ((falcon_rev(efx) < FALCON_REV_B0) ||
3273c2e8 1824 (efx->loopback_mode != LOOPBACK_NONE))
8ceee660
BH		 1825 return;
1826
1827 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1828 /* There is no point in draining more than once */
1829 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1830 return;
1831
1832 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1833 * the drain sequence with the statistics fetch */
1834 spin_lock(&efx->stats_lock);
1835
1836 EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1837 falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1838
1839 /* Reset the MAC and EM block. */
1840 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1841 EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1842 EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1843 EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1844 falcon_write(efx, &temp, GLB_CTL_REG_KER);
1845
1846 count = 0;
1847 while (1) {
1848 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1849 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1850 !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1851 !EFX_OWORD_FIELD(temp, RST_EM)) {
1852 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1853 count);
1854 break;
1855 }
1856 if (count > 20) {
1857 EFX_ERR(efx, "MAC reset failed\n");
1858 break;
1859 }
1860 count++;
1861 udelay(10);
1862 }
1863
1864 spin_unlock(&efx->stats_lock);
1865
1866 /* If we've reset the EM block and the link is up, then
1867 * we'll have to kick the XAUI link so the PHY can recover */
1868 if (efx->link_up && EFX_WORKAROUND_5147(efx))
1869 falcon_reset_xaui(efx);
1870}
1871
1872void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1873{
1874 efx_oword_t temp;
1875
55668611 1876 if (falcon_rev(efx) < FALCON_REV_B0)
8ceee660
BH		 1877 return;
1878
1879 /* Isolate the MAC -> RX */
1880 falcon_read(efx, &temp, RX_CFG_REG_KER);
1881 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1882 falcon_write(efx, &temp, RX_CFG_REG_KER);
1883
1884 if (!efx->link_up)
1885 falcon_drain_tx_fifo(efx);
1886}
1887
1888void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1889{
1890 efx_oword_t reg;
1891 int link_speed;
dc8cfa55 1892 bool tx_fc;
8ceee660
BH		 1893
1894 if (efx->link_options & GM_LPA_10000)
1895 link_speed = 0x3;
1896 else if (efx->link_options & GM_LPA_1000)
1897 link_speed = 0x2;
1898 else if (efx->link_options & GM_LPA_100)
1899 link_speed = 0x1;
1900 else
1901 link_speed = 0x0;
1902 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1903 * as advertised. Disable to ensure packets are not
1904 * indefinitely held and TX queue can be flushed at any point
1905 * while the link is down. */
1906 EFX_POPULATE_OWORD_5(reg,
1907 MAC_XOFF_VAL, 0xffff /* max pause time */,
1908 MAC_BCAD_ACPT, 1,
1909 MAC_UC_PROM, efx->promiscuous,
1910 MAC_LINK_STATUS, 1, /* always set */
1911 MAC_SPEED, link_speed);
1912 /* On B0, MAC backpressure can be disabled and packets get
1913 * discarded. */
55668611 1914 if (falcon_rev(efx) >= FALCON_REV_B0) {
8ceee660
BH		 1915 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1916 !efx->link_up);
1917 }
1918
1919 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1920
1921 /* Restore the multicast hash registers. */
1922 falcon_set_multicast_hash(efx);
1923
1924 /* Transmission of pause frames when RX crosses the threshold is
1925 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1926 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
dc8cfa55 1927 tx_fc = !!(efx->flow_control & EFX_FC_TX);
8ceee660
BH		 1928 falcon_read(efx, &reg, RX_CFG_REG_KER);
1929 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1930
1931 /* Unisolate the MAC -> RX */
55668611 1932 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 1933 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1934 falcon_write(efx, &reg, RX_CFG_REG_KER);
1935}
1936
1937int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1938{
1939 efx_oword_t reg;
1940 u32 *dma_done;
1941 int i;
1942
1943 if (disable_dma_stats)
1944 return 0;
1945
1946 /* Statistics fetch will fail if the MAC is in TX drain */
55668611 1947 if (falcon_rev(efx) >= FALCON_REV_B0) {
8ceee660
BH		 1948 efx_oword_t temp;
1949 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1950 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1951 return 0;
1952 }
1953
1954 dma_done = (efx->stats_buffer.addr + done_offset);
1955 *dma_done = FALCON_STATS_NOT_DONE;
1956 wmb(); /* ensure done flag is clear */
1957
1958 /* Initiate DMA transfer of stats */
1959 EFX_POPULATE_OWORD_2(reg,
1960 MAC_STAT_DMA_CMD, 1,
1961 MAC_STAT_DMA_ADR,
1962 efx->stats_buffer.dma_addr);
1963 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
1964
1965 /* Wait for transfer to complete */
1966 for (i = 0; i < 400; i++) {
1967 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE)
1968 return 0;
1969 udelay(10);
1970 }
1971
1972 EFX_ERR(efx, "timed out waiting for statistics\n");
1973 return -ETIMEDOUT;
1974}
1975
1976/**************************************************************************
1977 *
1978 * PHY access via GMII
1979 *
1980 **************************************************************************
1981 */
1982
1983/* Use the top bit of the MII PHY id to indicate the PHY type
1984 * (1G/10G), with the remaining bits as the actual PHY id.
1985 *
1986 * This allows us to avoid leaking information from the mii_if_info
1987 * structure into other data structures.
1988 */
1989#define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1990#define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1991#define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1992#define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1993#define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1994
1995
1996/* Packing the clause 45 port and device fields into a single value */
1997#define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1998#define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1999#define MD_DEV_ADR_COMP_LBN 0
2000#define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
2001
2002
2003/* Wait for GMII access to complete */
2004static int falcon_gmii_wait(struct efx_nic *efx)
2005{
2006 efx_dword_t md_stat;
2007 int count;
2008
2009 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
2010 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
2011 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
2012 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
2013 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
2014 EFX_ERR(efx, "error from GMII access "
2015 EFX_DWORD_FMT"\n",
2016 EFX_DWORD_VAL(md_stat));
2017 return -EIO;
2018 }
2019 return 0;
2020 }
2021 udelay(10);
2022 }
2023 EFX_ERR(efx, "timed out waiting for GMII\n");
2024 return -ETIMEDOUT;
2025}
2026
2027/* Writes a GMII register of a PHY connected to Falcon using MDIO. */
2028static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2029 int addr, int value)
2030{
767e468c 2031 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 2032 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
2033 efx_oword_t reg;
2034
2035 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
2036 * chosen so that the only current user, Falcon, can take the
2037 * packed value and use them directly.
2038 * Fail to build if this assumption is broken.
2039 */
2040 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
2041 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
2042 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
2043 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
2044
2045 if (phy_id2 == PHY_ADDR_INVALID)
2046 return;
2047
2048 /* See falcon_mdio_read for an explanation. */
2049 if (!(phy_id & FALCON_PHY_ID_10G)) {
2050 int mmd = ffs(efx->phy_op->mmds) - 1;
2051 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
2052 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
2053 & FALCON_PHY_ID_ID_MASK;
2054 }
2055
2056 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
2057 addr, value);
2058
2059 spin_lock_bh(&efx->phy_lock);
2060
2061 /* Check MII not currently being accessed */
2062 if (falcon_gmii_wait(efx) != 0)
2063 goto out;
2064
2065 /* Write the address/ID register */
2066 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2067 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2068
2069 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
2070 falcon_write(efx, &reg, MD_ID_REG_KER);
2071
2072 /* Write data */
2073 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2074 falcon_write(efx, &reg, MD_TXD_REG_KER);
2075
2076 EFX_POPULATE_OWORD_2(reg,
2077 MD_WRC, 1,
2078 MD_GC, 0);
2079 falcon_write(efx, &reg, MD_CS_REG_KER);
2080
2081 /* Wait for data to be written */
2082 if (falcon_gmii_wait(efx) != 0) {
2083 /* Abort the write operation */
2084 EFX_POPULATE_OWORD_2(reg,
2085 MD_WRC, 0,
2086 MD_GC, 1);
2087 falcon_write(efx, &reg, MD_CS_REG_KER);
2088 udelay(10);
2089 }
2090
2091 out:
2092 spin_unlock_bh(&efx->phy_lock);
2093}
2094
2095/* Reads a GMII register from a PHY connected to Falcon. If no value
2096 * could be read, -1 will be returned. */
2097static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2098{
767e468c 2099 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 2100 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2101 efx_oword_t reg;
2102 int value = -1;
2103
2104 if (phy_addr == PHY_ADDR_INVALID)
2105 return -1;
2106
2107 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2108 * but the generic Linux code does not make any distinction or have
2109 * any state for this.
2110 * We spot the case where someone tried to talk 22 to a 45 PHY and
2111 * redirect the request to the lowest numbered MMD as a clause45
2112 * request. This is enough to allow simple queries like id and link
2113 * state to succeed. TODO: We may need to do more in future.
2114 */
2115 if (!(phy_id & FALCON_PHY_ID_10G)) {
2116 int mmd = ffs(efx->phy_op->mmds) - 1;
2117 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2118 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2119 & FALCON_PHY_ID_ID_MASK;
2120 }
2121
2122 spin_lock_bh(&efx->phy_lock);
2123
2124 /* Check MII not currently being accessed */
2125 if (falcon_gmii_wait(efx) != 0)
2126 goto out;
2127
2128 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2129 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2130
2131 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2132 falcon_write(efx, &reg, MD_ID_REG_KER);
2133
2134 /* Request data to be read */
2135 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2136 falcon_write(efx, &reg, MD_CS_REG_KER);
2137
2138 /* Wait for data to become available */
2139 value = falcon_gmii_wait(efx);
2140 if (value == 0) {
2141 falcon_read(efx, &reg, MD_RXD_REG_KER);
2142 value = EFX_OWORD_FIELD(reg, MD_RXD);
2143 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2144 phy_id, addr, value);
2145 } else {
2146 /* Abort the read operation */
2147 EFX_POPULATE_OWORD_2(reg,
2148 MD_RIC, 0,
2149 MD_GC, 1);
2150 falcon_write(efx, &reg, MD_CS_REG_KER);
2151
2152 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2153 "error %d\n", phy_id, addr, value);
2154 }
2155
2156 out:
2157 spin_unlock_bh(&efx->phy_lock);
2158
2159 return value;
2160}
2161
2162static void falcon_init_mdio(struct mii_if_info *gmii)
2163{
2164 gmii->mdio_read = falcon_mdio_read;
2165 gmii->mdio_write = falcon_mdio_write;
2166 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2167 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2168}
2169
2170static int falcon_probe_phy(struct efx_nic *efx)
2171{
2172 switch (efx->phy_type) {
2173 case PHY_TYPE_10XPRESS:
2174 efx->phy_op = &falcon_tenxpress_phy_ops;
2175 break;
2176 case PHY_TYPE_XFP:
2177 efx->phy_op = &falcon_xfp_phy_ops;
2178 break;
2179 default:
2180 EFX_ERR(efx, "Unknown PHY type %d\n",
2181 efx->phy_type);
2182 return -1;
2183 }
3273c2e8
BH		 2184
2185 efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
8ceee660
BH		 2186 return 0;
2187}
2188
2189/* This call is responsible for hooking in the MAC and PHY operations */
2190int falcon_probe_port(struct efx_nic *efx)
2191{
2192 int rc;
2193
2194 /* Hook in PHY operations table */
2195 rc = falcon_probe_phy(efx);
2196 if (rc)
2197 return rc;
2198
2199 /* Set up GMII structure for PHY */
dc8cfa55 2200 efx->mii.supports_gmii = true;
8ceee660
BH		 2201 falcon_init_mdio(&efx->mii);
2202
2203 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
55668611 2204 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 2205 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2206 else
2207 efx->flow_control = EFX_FC_RX;
2208
2209 /* Allocate buffer for stats */
2210 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2211 FALCON_MAC_STATS_SIZE);
2212 if (rc)
2213 return rc;
2214 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2215 (unsigned long long)efx->stats_buffer.dma_addr,
2216 efx->stats_buffer.addr,
2217 virt_to_phys(efx->stats_buffer.addr));
2218
2219 return 0;
2220}
2221
2222void falcon_remove_port(struct efx_nic *efx)
2223{
2224 falcon_free_buffer(efx, &efx->stats_buffer);
2225}
2226
2227/**************************************************************************
2228 *
2229 * Multicast filtering
2230 *
2231 **************************************************************************
2232 */
2233
2234void falcon_set_multicast_hash(struct efx_nic *efx)
2235{
2236 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2237
2238 /* Broadcast packets go through the multicast hash filter.
2239 * ether_crc_le() of the broadcast address is 0xbe2612ff
2240 * so we always add bit 0xff to the mask.
2241 */
2242 set_bit_le(0xff, mc_hash->byte);
2243
2244 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2245 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2246}
2247
2248/**************************************************************************
2249 *
2250 * Device reset
2251 *
2252 **************************************************************************
2253 */
2254
2255/* Resets NIC to known state. This routine must be called in process
2256 * context and is allowed to sleep. */
2257int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2258{
2259 struct falcon_nic_data *nic_data = efx->nic_data;
2260 efx_oword_t glb_ctl_reg_ker;
2261 int rc;
2262
2263 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2264
2265 /* Initiate device reset */
2266 if (method == RESET_TYPE_WORLD) {
2267 rc = pci_save_state(efx->pci_dev);
2268 if (rc) {
2269 EFX_ERR(efx, "failed to backup PCI state of primary "
2270 "function prior to hardware reset\n");
2271 goto fail1;
2272 }
2273 if (FALCON_IS_DUAL_FUNC(efx)) {
2274 rc = pci_save_state(nic_data->pci_dev2);
2275 if (rc) {
2276 EFX_ERR(efx, "failed to backup PCI state of "
2277 "secondary function prior to "
2278 "hardware reset\n");
2279 goto fail2;
2280 }
2281 }
2282
2283 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2284 EXT_PHY_RST_DUR, 0x7,
2285 SWRST, 1);
2286 } else {
2287 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2288 EXCLUDE_FROM_RESET : 0);
2289
2290 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2291 EXT_PHY_RST_CTL, reset_phy,
2292 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2293 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2294 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2295 EE_RST_CTL, EXCLUDE_FROM_RESET,
2296 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2297 SWRST, 1);
2298 }
2299 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2300
2301 EFX_LOG(efx, "waiting for hardware reset\n");
2302 schedule_timeout_uninterruptible(HZ / 20);
2303
2304 /* Restore PCI configuration if needed */
2305 if (method == RESET_TYPE_WORLD) {
2306 if (FALCON_IS_DUAL_FUNC(efx)) {
2307 rc = pci_restore_state(nic_data->pci_dev2);
2308 if (rc) {
2309 EFX_ERR(efx, "failed to restore PCI config for "
2310 "the secondary function\n");
2311 goto fail3;
2312 }
2313 }
2314 rc = pci_restore_state(efx->pci_dev);
2315 if (rc) {
2316 EFX_ERR(efx, "failed to restore PCI config for the "
2317 "primary function\n");
2318 goto fail4;
2319 }
2320 EFX_LOG(efx, "successfully restored PCI config\n");
2321 }
2322
2323 /* Assert that reset complete */
2324 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2325 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2326 rc = -ETIMEDOUT;
2327 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2328 goto fail5;
2329 }
2330 EFX_LOG(efx, "hardware reset complete\n");
2331
2332 return 0;
2333
2334 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2335fail2:
2336fail3:
2337 pci_restore_state(efx->pci_dev);
2338fail1:
2339fail4:
2340fail5:
2341 return rc;
2342}
2343
2344/* Zeroes out the SRAM contents. This routine must be called in
2345 * process context and is allowed to sleep.
2346 */
2347static int falcon_reset_sram(struct efx_nic *efx)
2348{
2349 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2350 int count;
2351
2352 /* Set the SRAM wake/sleep GPIO appropriately. */
2353 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2354 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2355 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2356 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2357
2358 /* Initiate SRAM reset */
2359 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2360 SRAM_OOB_BT_INIT_EN, 1,
2361 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2362 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2363
2364 /* Wait for SRAM reset to complete */
2365 count = 0;
2366 do {
2367 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2368
2369 /* SRAM reset is slow; expect around 16ms */
2370 schedule_timeout_uninterruptible(HZ / 50);
2371
2372 /* Check for reset complete */
2373 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2374 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2375 EFX_LOG(efx, "SRAM reset complete\n");
2376
2377 return 0;
2378 }
2379 } while (++count < 20); /* wait upto 0.4 sec */
2380
2381 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2382 return -ETIMEDOUT;
2383}
2384
4a5b504d
BH		 2385static int falcon_spi_device_init(struct efx_nic *efx,
2386 struct efx_spi_device **spi_device_ret,
2387 unsigned int device_id, u32 device_type)
2388{
2389 struct efx_spi_device *spi_device;
2390
2391 if (device_type != 0) {
2392 spi_device = kmalloc(sizeof(*spi_device), GFP_KERNEL);
2393 if (!spi_device)
2394 return -ENOMEM;
2395 spi_device->device_id = device_id;
2396 spi_device->size =
2397 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2398 spi_device->addr_len =
2399 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2400 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2401 spi_device->addr_len == 1);
2402 spi_device->block_size =
2403 1 << SPI_DEV_TYPE_FIELD(device_type,
2404 SPI_DEV_TYPE_BLOCK_SIZE);
2405
2406 spi_device->efx = efx;
2407 } else {
2408 spi_device = NULL;
2409 }
2410
2411 kfree(*spi_device_ret);
2412 *spi_device_ret = spi_device;
2413 return 0;
2414}
2415
2416
2417static void falcon_remove_spi_devices(struct efx_nic *efx)
2418{
2419 kfree(efx->spi_eeprom);
2420 efx->spi_eeprom = NULL;
2421 kfree(efx->spi_flash);
2422 efx->spi_flash = NULL;
2423}
2424
8ceee660
BH		 2425/* Extract non-volatile configuration */
2426static int falcon_probe_nvconfig(struct efx_nic *efx)
2427{
2428 struct falcon_nvconfig *nvconfig;
4a5b504d 2429 struct efx_spi_device *spi;
8ceee660
BH		 2430 int magic_num, struct_ver, board_rev;
2431 int rc;
2432
8ceee660 2433 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
4a5b504d
BH		 2434 if (!nvconfig)
2435 return -ENOMEM;
8ceee660
BH		 2436
2437 /* Read the whole configuration structure into memory. */
4a5b504d
BH		 2438 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2439 rc = falcon_spi_read(spi, NVCONFIG_BASE, sizeof(*nvconfig),
2440 NULL, (char *)nvconfig);
2441 if (rc) {
2442 EFX_ERR(efx, "Failed to read %s\n", efx->spi_flash ? "flash" :
2443 "EEPROM");
2444 goto fail1;
8ceee660
BH		 2445 }
2446
2447 /* Read the MAC addresses */
2448 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2449
2450 /* Read the board configuration. */
2451 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2452 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2453
2454 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM || struct_ver < 2) {
2455 EFX_ERR(efx, "Non volatile memory bad magic=%x ver=%x "
2456 "therefore using defaults\n", magic_num, struct_ver);
2457 efx->phy_type = PHY_TYPE_NONE;
2458 efx->mii.phy_id = PHY_ADDR_INVALID;
2459 board_rev = 0;
2460 } else {
2461 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
4a5b504d 2462 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
8ceee660
BH		 2463
2464 efx->phy_type = v2->port0_phy_type;
2465 efx->mii.phy_id = v2->port0_phy_addr;
2466 board_rev = le16_to_cpu(v2->board_revision);
4a5b504d
BH		 2467
2468 if (struct_ver >= 3) {
2469 __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2470 __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2471 rc = falcon_spi_device_init(efx, &efx->spi_flash,
2472 EE_SPI_FLASH,
2473 le32_to_cpu(fl));
2474 if (rc)
2475 goto fail2;
2476 rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2477 EE_SPI_EEPROM,
2478 le32_to_cpu(ee));
2479 if (rc)
2480 goto fail2;
2481 }
8ceee660
BH		 2482 }
2483
2484 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2485
2486 efx_set_board_info(efx, board_rev);
2487
4a5b504d
BH		 2488 kfree(nvconfig);
2489 return 0;
2490
2491 fail2:
2492 falcon_remove_spi_devices(efx);
2493 fail1:
8ceee660
BH		 2494 kfree(nvconfig);
2495 return rc;
2496}
2497
2498/* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2499 * count, port speed). Set workaround and feature flags accordingly.
2500 */
2501static int falcon_probe_nic_variant(struct efx_nic *efx)
2502{
2503 efx_oword_t altera_build;
2504
2505 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2506 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2507 EFX_ERR(efx, "Falcon FPGA not supported\n");
2508 return -ENODEV;
2509 }
2510
55668611 2511 switch (falcon_rev(efx)) {
8ceee660
BH		 2512 case FALCON_REV_A0:
2513 case 0xff:
2514 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2515 return -ENODEV;
2516
2517 case FALCON_REV_A1:{
2518 efx_oword_t nic_stat;
2519
2520 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2521
2522 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2523 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2524 return -ENODEV;
2525 }
2526 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2527 EFX_ERR(efx, "1G mode not supported\n");
2528 return -ENODEV;
2529 }
2530 break;
2531 }
2532
2533 case FALCON_REV_B0:
2534 break;
2535
2536 default:
55668611 2537 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
8ceee660
BH		 2538 return -ENODEV;
2539 }
2540
2541 return 0;
2542}
2543
4a5b504d
BH		 2544/* Probe all SPI devices on the NIC */
2545static void falcon_probe_spi_devices(struct efx_nic *efx)
2546{
2547 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2548 bool has_flash, has_eeprom, boot_is_external;
2549
2550 falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2551 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2552 falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2553
2554 has_flash = EFX_OWORD_FIELD(nic_stat, SF_PRST);
2555 has_eeprom = EFX_OWORD_FIELD(nic_stat, EE_PRST);
2556 boot_is_external = EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE);
2557
2558 if (has_flash) {
2559 /* Default flash SPI device: Atmel AT25F1024
2560 * 128 KB, 24-bit address, 32 KB erase block,
2561 * 256 B write block
2562 */
2563 u32 flash_device_type =
2564 (17 << SPI_DEV_TYPE_SIZE_LBN)
2565 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2566 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
2567 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
2568 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2569
2570 falcon_spi_device_init(efx, &efx->spi_flash,
2571 EE_SPI_FLASH, flash_device_type);
2572
2573 if (!boot_is_external) {
2574 /* Disable VPD and set clock dividers to safe
2575 * values for initial programming.
2576 */
2577 EFX_LOG(efx, "Booted from internal ASIC settings;"
2578 " setting SPI config\n");
2579 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2580 /* 125 MHz / 7 ~= 20 MHz */
2581 EE_SF_CLOCK_DIV, 7,
2582 /* 125 MHz / 63 ~= 2 MHz */
2583 EE_EE_CLOCK_DIV, 63);
2584 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2585 }
2586 }
2587
2588 if (has_eeprom) {
2589 u32 eeprom_device_type;
2590
2591 /* If it has no flash, it must have a large EEPROM
2592 * for chip config; otherwise check whether 9-bit
2593 * addressing is used for VPD configuration
2594 */
2595 if (has_flash &&
2596 (!boot_is_external ||
2597 EFX_OWORD_FIELD(ee_vpd_cfg, EE_VPD_EN_AD9_MODE))) {
2598 /* Default SPI device: Atmel AT25040 or similar
2599 * 512 B, 9-bit address, 8 B write block
2600 */
2601 eeprom_device_type =
2602 (9 << SPI_DEV_TYPE_SIZE_LBN)
2603 | (1 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2604 | (3 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2605 } else {
2606 /* "Large" SPI device: Atmel AT25640 or similar
2607 * 8 KB, 16-bit address, 32 B write block
2608 */
2609 eeprom_device_type =
2610 (13 << SPI_DEV_TYPE_SIZE_LBN)
2611 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2612 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2613 }
2614
2615 falcon_spi_device_init(efx, &efx->spi_eeprom,
2616 EE_SPI_EEPROM, eeprom_device_type);
2617 }
2618
2619 EFX_LOG(efx, "flash is %s, EEPROM is %s\n",
2620 (has_flash ? "present" : "absent"),
2621 (has_eeprom ? "present" : "absent"));
2622}
2623
8ceee660
BH		 2624int falcon_probe_nic(struct efx_nic *efx)
2625{
2626 struct falcon_nic_data *nic_data;
2627 int rc;
2628
8ceee660
BH		 2629 /* Allocate storage for hardware specific data */
2630 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
5daab96d 2631 efx->nic_data = nic_data;
8ceee660
BH		 2632
2633 /* Determine number of ports etc. */
2634 rc = falcon_probe_nic_variant(efx);
2635 if (rc)
2636 goto fail1;
2637
2638 /* Probe secondary function if expected */
2639 if (FALCON_IS_DUAL_FUNC(efx)) {
2640 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2641
2642 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2643 dev))) {
2644 if (dev->bus == efx->pci_dev->bus &&
2645 dev->devfn == efx->pci_dev->devfn + 1) {
2646 nic_data->pci_dev2 = dev;
2647 break;
2648 }
2649 }
2650 if (!nic_data->pci_dev2) {
2651 EFX_ERR(efx, "failed to find secondary function\n");
2652 rc = -ENODEV;
2653 goto fail2;
2654 }
2655 }
2656
2657 /* Now we can reset the NIC */
2658 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2659 if (rc) {
2660 EFX_ERR(efx, "failed to reset NIC\n");
2661 goto fail3;
2662 }
2663
2664 /* Allocate memory for INT_KER */
2665 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2666 if (rc)
2667 goto fail4;
2668 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2669
2670 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2671 (unsigned long long)efx->irq_status.dma_addr,
2672 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2673
4a5b504d
BH		 2674 falcon_probe_spi_devices(efx);
2675
8ceee660
BH		 2676 /* Read in the non-volatile configuration */
2677 rc = falcon_probe_nvconfig(efx);
2678 if (rc)
2679 goto fail5;
2680
37b5a603
BH		 2681 /* Initialise I2C adapter */
2682 efx->i2c_adap.owner = THIS_MODULE;
37b5a603
BH		 2683 nic_data->i2c_data = falcon_i2c_bit_operations;
2684 nic_data->i2c_data.data = efx;
2685 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2686 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
9dadae68 2687 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
37b5a603
BH		 2688 rc = i2c_bit_add_bus(&efx->i2c_adap);
2689 if (rc)
2690 goto fail5;
2691
8ceee660
BH		 2692 return 0;
2693
2694 fail5:
4a5b504d 2695 falcon_remove_spi_devices(efx);
8ceee660
BH		 2696 falcon_free_buffer(efx, &efx->irq_status);
2697 fail4:
8ceee660
BH		 2698 fail3:
2699 if (nic_data->pci_dev2) {
2700 pci_dev_put(nic_data->pci_dev2);
2701 nic_data->pci_dev2 = NULL;
2702 }
2703 fail2:
8ceee660
BH		 2704 fail1:
2705 kfree(efx->nic_data);
2706 return rc;
2707}
2708
2709/* This call performs hardware-specific global initialisation, such as
2710 * defining the descriptor cache sizes and number of RSS channels.
2711 * It does not set up any buffers, descriptor rings or event queues.
2712 */
2713int falcon_init_nic(struct efx_nic *efx)
2714{
8ceee660
BH		 2715 efx_oword_t temp;
2716 unsigned thresh;
2717 int rc;
2718
8ceee660
BH		 2719 /* Set up the address region register. This is only needed
2720 * for the B0 FPGA, but since we are just pushing in the
2721 * reset defaults this may as well be unconditional. */
2722 EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2723 ADR_REGION1, (1 << 16),
2724 ADR_REGION2, (2 << 16),
2725 ADR_REGION3, (3 << 16));
2726 falcon_write(efx, &temp, ADR_REGION_REG_KER);
2727
2728 /* Use on-chip SRAM */
2729 falcon_read(efx, &temp, NIC_STAT_REG);
2730 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2731 falcon_write(efx, &temp, NIC_STAT_REG);
2732
2733 /* Set buffer table mode */
2734 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2735 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2736
2737 rc = falcon_reset_sram(efx);
2738 if (rc)
2739 return rc;
2740
2741 /* Set positions of descriptor caches in SRAM. */
2742 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2743 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2744 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2745 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2746
2747 /* Set TX descriptor cache size. */
2748 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2749 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2750 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2751
2752 /* Set RX descriptor cache size. Set low watermark to size-8, as
2753 * this allows most efficient prefetching.
2754 */
2755 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2756 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2757 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2758 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2759 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2760
2761 /* Clear the parity enables on the TX data fifos as
2762 * they produce false parity errors because of timing issues
2763 */
2764 if (EFX_WORKAROUND_5129(efx)) {
2765 falcon_read(efx, &temp, SPARE_REG_KER);
2766 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2767 falcon_write(efx, &temp, SPARE_REG_KER);
2768 }
2769
2770 /* Enable all the genuinely fatal interrupts. (They are still
2771 * masked by the overall interrupt mask, controlled by
2772 * falcon_interrupts()).
2773 *
2774 * Note: All other fatal interrupts are enabled
2775 */
2776 EFX_POPULATE_OWORD_3(temp,
2777 ILL_ADR_INT_KER_EN, 1,
2778 RBUF_OWN_INT_KER_EN, 1,
2779 TBUF_OWN_INT_KER_EN, 1);
2780 EFX_INVERT_OWORD(temp);
2781 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2782
2783 /* Set number of RSS queues for receive path. */
2784 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
55668611 2785 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 2786 EFX_SET_OWORD_FIELD(temp, NUM_KER, 0);
2787 else
2788 EFX_SET_OWORD_FIELD(temp, NUM_KER, efx->rss_queues - 1);
2789 if (EFX_WORKAROUND_7244(efx)) {
2790 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2791 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2792 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2793 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
2794 }
2795 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
2796
2797 falcon_setup_rss_indir_table(efx);
2798
2799 /* Setup RX. Wait for descriptor is broken and must
2800 * be disabled. RXDP recovery shouldn't be needed, but is.
2801 */
2802 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2803 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2804 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2805 if (EFX_WORKAROUND_5583(efx))
2806 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2807 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2808
2809 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2810 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2811 */
2812 falcon_read(efx, &temp, TX_CFG2_REG_KER);
2813 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2814 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2815 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2816 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2817 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2818 /* Enable SW_EV to inherit in char driver - assume harmless here */
2819 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2820 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2821 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2822 /* Squash TX of packets of 16 bytes or less */
55668611 2823 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
8ceee660
BH		 2824 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2825 falcon_write(efx, &temp, TX_CFG2_REG_KER);
2826
2827 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2828 * descriptors (which is bad).
2829 */
2830 falcon_read(efx, &temp, TX_CFG_REG_KER);
2831 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2832 falcon_write(efx, &temp, TX_CFG_REG_KER);
2833
2834 /* RX config */
2835 falcon_read(efx, &temp, RX_CFG_REG_KER);
2836 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2837 if (EFX_WORKAROUND_7575(efx))
2838 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2839 (3 * 4096) / 32);
55668611 2840 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 2841 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2842
2843 /* RX FIFO flow control thresholds */
2844 thresh = ((rx_xon_thresh_bytes >= 0) ?
2845 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2846 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2847 thresh = ((rx_xoff_thresh_bytes >= 0) ?
2848 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2849 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2850 /* RX control FIFO thresholds [32 entries] */
c84a6f18
BH		 2851 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
2852 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
8ceee660
BH		 2853 falcon_write(efx, &temp, RX_CFG_REG_KER);
2854
2855 /* Set destination of both TX and RX Flush events */
55668611 2856 if (falcon_rev(efx) >= FALCON_REV_B0) {
8ceee660
BH		 2857 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
2858 falcon_write(efx, &temp, DP_CTRL_REG);
2859 }
2860
2861 return 0;
2862}
2863
2864void falcon_remove_nic(struct efx_nic *efx)
2865{
2866 struct falcon_nic_data *nic_data = efx->nic_data;
37b5a603
BH		 2867 int rc;
2868
2869 rc = i2c_del_adapter(&efx->i2c_adap);
2870 BUG_ON(rc);
8ceee660 2871
4a5b504d 2872 falcon_remove_spi_devices(efx);
8ceee660
BH		 2873 falcon_free_buffer(efx, &efx->irq_status);
2874
91ad757c 2875 falcon_reset_hw(efx, RESET_TYPE_ALL);
8ceee660
BH		 2876
2877 /* Release the second function after the reset */
2878 if (nic_data->pci_dev2) {
2879 pci_dev_put(nic_data->pci_dev2);
2880 nic_data->pci_dev2 = NULL;
2881 }
2882
2883 /* Tear down the private nic state */
2884 kfree(efx->nic_data);
2885 efx->nic_data = NULL;
2886}
2887
2888void falcon_update_nic_stats(struct efx_nic *efx)
2889{
2890 efx_oword_t cnt;
2891
2892 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
2893 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
2894}
2895
2896/**************************************************************************
2897 *
2898 * Revision-dependent attributes used by efx.c
2899 *
2900 **************************************************************************
2901 */
2902
2903struct efx_nic_type falcon_a_nic_type = {
2904 .mem_bar = 2,
2905 .mem_map_size = 0x20000,
2906 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
2907 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
2908 .buf_tbl_base = BUF_TBL_KER_A1,
2909 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
2910 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
2911 .txd_ring_mask = FALCON_TXD_RING_MASK,
2912 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2913 .evq_size = FALCON_EVQ_SIZE,
2914 .max_dma_mask = FALCON_DMA_MASK,
2915 .tx_dma_mask = FALCON_TX_DMA_MASK,
2916 .bug5391_mask = 0xf,
2917 .rx_xoff_thresh = 2048,
2918 .rx_xon_thresh = 512,
2919 .rx_buffer_padding = 0x24,
2920 .max_interrupt_mode = EFX_INT_MODE_MSI,
2921 .phys_addr_channels = 4,
2922};
2923
2924struct efx_nic_type falcon_b_nic_type = {
2925 .mem_bar = 2,
2926 /* Map everything up to and including the RSS indirection
2927 * table. Don't map MSI-X table, MSI-X PBA since Linux
2928 * requires that they not be mapped. */
2929 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
2930 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
2931 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
2932 .buf_tbl_base = BUF_TBL_KER_B0,
2933 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
2934 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
2935 .txd_ring_mask = FALCON_TXD_RING_MASK,
2936 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2937 .evq_size = FALCON_EVQ_SIZE,
2938 .max_dma_mask = FALCON_DMA_MASK,
2939 .tx_dma_mask = FALCON_TX_DMA_MASK,
2940 .bug5391_mask = 0,
2941 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
2942 .rx_xon_thresh = 27648, /* ~3*max MTU */
2943 .rx_buffer_padding = 0,
2944 .max_interrupt_mode = EFX_INT_MODE_MSIX,
2945 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
2946 * interrupt handler only supports 32
2947 * channels */
2948};
2949
Linux 6.x block layer and io_uring tree(s)