projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sfc: Move struct falcon_board into struct falcon_nic_data
[linux-2.6-block.git] / drivers / net / sfc / falcon.c
CommitLineData
8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/seq_file.h>
37b5a603 16#include <linux/i2c.h>
f31a45d2 17#include <linux/mii.h>
8ceee660
BH		 18#include "net_driver.h"
19#include "bitfield.h"
20#include "efx.h"
21#include "mac.h"
8ceee660
BH		 22#include "spi.h"
23#include "falcon.h"
3e6c4538 24#include "regs.h"
12d00cad 25#include "io.h"
8ceee660
BH		 26#include "mdio_10g.h"
27#include "phy.h"
8ceee660
BH		 28#include "workarounds.h"
29
30/* Falcon hardware control.
31 * Falcon is the internal codename for the SFC4000 controller that is
32 * present in SFE400X evaluation boards
33 */
34
8ceee660
BH		 35/**************************************************************************
36 *
37 * Configurable values
38 *
39 **************************************************************************
40 */
41
42static int disable_dma_stats;
43
44/* This is set to 16 for a good reason. In summary, if larger than
45 * 16, the descriptor cache holds more than a default socket
46 * buffer's worth of packets (for UDP we can only have at most one
47 * socket buffer's worth outstanding). This combined with the fact
48 * that we only get 1 TX event per descriptor cache means the NIC
49 * goes idle.
50 */
51#define TX_DC_ENTRIES 16
52#define TX_DC_ENTRIES_ORDER 0
53#define TX_DC_BASE 0x130000
54
55#define RX_DC_ENTRIES 64
56#define RX_DC_ENTRIES_ORDER 2
57#define RX_DC_BASE 0x100000
58
2f7f5730
BH		 59static const unsigned int
60/* "Large" EEPROM device: Atmel AT25640 or similar
61 * 8 KB, 16-bit address, 32 B write block */
62large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
63 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
64 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
65/* Default flash device: Atmel AT25F1024
66 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
67default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
68 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
69 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
70 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
71 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
72
8ceee660
BH		 73/* RX FIFO XOFF watermark
74 *
75 * When the amount of the RX FIFO increases used increases past this
76 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
77 * This also has an effect on RX/TX arbitration
78 */
79static int rx_xoff_thresh_bytes = -1;
80module_param(rx_xoff_thresh_bytes, int, 0644);
81MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
82
83/* RX FIFO XON watermark
84 *
85 * When the amount of the RX FIFO used decreases below this
86 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
87 * This also has an effect on RX/TX arbitration
88 */
89static int rx_xon_thresh_bytes = -1;
90module_param(rx_xon_thresh_bytes, int, 0644);
91MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
92
2c3c3d02
BH		 93/* If FALCON_MAX_INT_ERRORS internal errors occur within
94 * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
95 * disable it.
96 */
97#define FALCON_INT_ERROR_EXPIRE 3600
98#define FALCON_MAX_INT_ERRORS 5
8ceee660 99
6bc5d3a9
BH		 100/* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
101 */
102#define FALCON_FLUSH_INTERVAL 10
103#define FALCON_FLUSH_POLL_COUNT 100
8ceee660
BH		 104
105/**************************************************************************
106 *
107 * Falcon constants
108 *
109 **************************************************************************
110 */
111
8ceee660
BH		 112/* Size and alignment of special buffers (4KB) */
113#define FALCON_BUF_SIZE 4096
114
115/* Dummy SRAM size code */
116#define SRM_NB_BSZ_ONCHIP_ONLY (-1)
117
8ceee660 118#define FALCON_IS_DUAL_FUNC(efx) \
55668611 119 (falcon_rev(efx) < FALCON_REV_B0)
8ceee660
BH		 120
121/**************************************************************************
122 *
123 * Falcon hardware access
124 *
125 **************************************************************************/
126
12d00cad
BH		 127static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
128 unsigned int index)
129{
130 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
131 value, index);
132}
133
8ceee660
BH		 134/* Read the current event from the event queue */
135static inline efx_qword_t *falcon_event(struct efx_channel *channel,
136 unsigned int index)
137{
138 return (((efx_qword_t *) (channel->eventq.addr)) + index);
139}
140
141/* See if an event is present
142 *
143 * We check both the high and low dword of the event for all ones. We
144 * wrote all ones when we cleared the event, and no valid event can
145 * have all ones in either its high or low dwords. This approach is
146 * robust against reordering.
147 *
148 * Note that using a single 64-bit comparison is incorrect; even
149 * though the CPU read will be atomic, the DMA write may not be.
150 */
151static inline int falcon_event_present(efx_qword_t *event)
152{
153 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
154 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
155}
156
157/**************************************************************************
158 *
159 * I2C bus - this is a bit-bashing interface using GPIO pins
160 * Note that it uses the output enables to tristate the outputs
161 * SDA is the data pin and SCL is the clock
162 *
163 **************************************************************************
164 */
37b5a603 165static void falcon_setsda(void *data, int state)
8ceee660 166{
37b5a603 167 struct efx_nic *efx = (struct efx_nic *)data;
8ceee660
BH		 168 efx_oword_t reg;
169
12d00cad 170 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
3e6c4538 171 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
12d00cad 172 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
8ceee660
BH		 173}
174
37b5a603 175static void falcon_setscl(void *data, int state)
8ceee660 176{
37b5a603 177 struct efx_nic *efx = (struct efx_nic *)data;
8ceee660
BH		 178 efx_oword_t reg;
179
12d00cad 180 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
3e6c4538 181 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
12d00cad 182 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
37b5a603
BH		 183}
184
185static int falcon_getsda(void *data)
186{
187 struct efx_nic *efx = (struct efx_nic *)data;
188 efx_oword_t reg;
189
12d00cad 190 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
3e6c4538 191 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
8ceee660
BH		 192}
193
37b5a603 194static int falcon_getscl(void *data)
8ceee660 195{
37b5a603 196 struct efx_nic *efx = (struct efx_nic *)data;
8ceee660
BH		 197 efx_oword_t reg;
198
12d00cad 199 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
3e6c4538 200 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
8ceee660
BH		 201}
202
37b5a603
BH		 203static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
204 .setsda = falcon_setsda,
205 .setscl = falcon_setscl,
8ceee660
BH		 206 .getsda = falcon_getsda,
207 .getscl = falcon_getscl,
62c78329 208 .udelay = 5,
9dadae68
BH		 209 /* Wait up to 50 ms for slave to let us pull SCL high */
210 .timeout = DIV_ROUND_UP(HZ, 20),
8ceee660
BH		 211};
212
213/**************************************************************************
214 *
215 * Falcon special buffer handling
216 * Special buffers are used for event queues and the TX and RX
217 * descriptor rings.
218 *
219 *************************************************************************/
220
221/*
222 * Initialise a Falcon special buffer
223 *
224 * This will define a buffer (previously allocated via
225 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
226 * it to be used for event queues, descriptor rings etc.
227 */
bc3c90a2 228static void
8ceee660
BH		 229falcon_init_special_buffer(struct efx_nic *efx,
230 struct efx_special_buffer *buffer)
231{
232 efx_qword_t buf_desc;
233 int index;
234 dma_addr_t dma_addr;
235 int i;
236
237 EFX_BUG_ON_PARANOID(!buffer->addr);
238
239 /* Write buffer descriptors to NIC */
240 for (i = 0; i < buffer->entries; i++) {
241 index = buffer->index + i;
242 dma_addr = buffer->dma_addr + (i * 4096);
243 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
244 index, (unsigned long long)dma_addr);
3e6c4538
BH		 245 EFX_POPULATE_QWORD_3(buf_desc,
246 FRF_AZ_BUF_ADR_REGION, 0,
247 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
248 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
12d00cad 249 falcon_write_buf_tbl(efx, &buf_desc, index);
8ceee660 250 }
8ceee660
BH		 251}
252
253/* Unmaps a buffer from Falcon and clears the buffer table entries */
254static void
255falcon_fini_special_buffer(struct efx_nic *efx,
256 struct efx_special_buffer *buffer)
257{
258 efx_oword_t buf_tbl_upd;
259 unsigned int start = buffer->index;
260 unsigned int end = (buffer->index + buffer->entries - 1);
261
262 if (!buffer->entries)
263 return;
264
265 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
266 buffer->index, buffer->index + buffer->entries - 1);
267
268 EFX_POPULATE_OWORD_4(buf_tbl_upd,
3e6c4538
BH		 269 FRF_AZ_BUF_UPD_CMD, 0,
270 FRF_AZ_BUF_CLR_CMD, 1,
271 FRF_AZ_BUF_CLR_END_ID, end,
272 FRF_AZ_BUF_CLR_START_ID, start);
12d00cad 273 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
8ceee660
BH		 274}
275
276/*
277 * Allocate a new Falcon special buffer
278 *
279 * This allocates memory for a new buffer, clears it and allocates a
280 * new buffer ID range. It does not write into Falcon's buffer table.
281 *
282 * This call will allocate 4KB buffers, since Falcon can't use 8KB
283 * buffers for event queues and descriptor rings.
284 */
285static int falcon_alloc_special_buffer(struct efx_nic *efx,
286 struct efx_special_buffer *buffer,
287 unsigned int len)
288{
8ceee660
BH		 289 len = ALIGN(len, FALCON_BUF_SIZE);
290
291 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
292 &buffer->dma_addr);
293 if (!buffer->addr)
294 return -ENOMEM;
295 buffer->len = len;
296 buffer->entries = len / FALCON_BUF_SIZE;
297 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
298
299 /* All zeros is a potentially valid event so memset to 0xff */
300 memset(buffer->addr, 0xff, len);
301
302 /* Select new buffer ID */
0484e0db
BH		 303 buffer->index = efx->next_buffer_table;
304 efx->next_buffer_table += buffer->entries;
8ceee660
BH		 305
306 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
9c8976a1 307 "(virt %p phys %llx)\n", buffer->index,
8ceee660 308 buffer->index + buffer->entries - 1,
9c8976a1
JSR		 309 (u64)buffer->dma_addr, len,
310 buffer->addr, (u64)virt_to_phys(buffer->addr));
8ceee660
BH		 311
312 return 0;
313}
314
315static void falcon_free_special_buffer(struct efx_nic *efx,
316 struct efx_special_buffer *buffer)
317{
318 if (!buffer->addr)
319 return;
320
321 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
9c8976a1 322 "(virt %p phys %llx)\n", buffer->index,
8ceee660 323 buffer->index + buffer->entries - 1,
9c8976a1
JSR		 324 (u64)buffer->dma_addr, buffer->len,
325 buffer->addr, (u64)virt_to_phys(buffer->addr));
8ceee660
BH		 326
327 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
328 buffer->dma_addr);
329 buffer->addr = NULL;
330 buffer->entries = 0;
331}
332
333/**************************************************************************
334 *
335 * Falcon generic buffer handling
336 * These buffers are used for interrupt status and MAC stats
337 *
338 **************************************************************************/
339
340static int falcon_alloc_buffer(struct efx_nic *efx,
341 struct efx_buffer *buffer, unsigned int len)
342{
343 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
344 &buffer->dma_addr);
345 if (!buffer->addr)
346 return -ENOMEM;
347 buffer->len = len;
348 memset(buffer->addr, 0, len);
349 return 0;
350}
351
352static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
353{
354 if (buffer->addr) {
355 pci_free_consistent(efx->pci_dev, buffer->len,
356 buffer->addr, buffer->dma_addr);
357 buffer->addr = NULL;
358 }
359}
360
361/**************************************************************************
362 *
363 * Falcon TX path
364 *
365 **************************************************************************/
366
367/* Returns a pointer to the specified transmit descriptor in the TX
368 * descriptor queue belonging to the specified channel.
369 */
370static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
371 unsigned int index)
372{
373 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
374}
375
376/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
377static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
378{
379 unsigned write_ptr;
380 efx_dword_t reg;
381
3ffeabdd 382 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
3e6c4538 383 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
12d00cad
BH		 384 efx_writed_page(tx_queue->efx, &reg,
385 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
8ceee660
BH		 386}
387
388
389/* For each entry inserted into the software descriptor ring, create a
390 * descriptor in the hardware TX descriptor ring (in host memory), and
391 * write a doorbell.
392 */
393void falcon_push_buffers(struct efx_tx_queue *tx_queue)
394{
395
396 struct efx_tx_buffer *buffer;
397 efx_qword_t *txd;
398 unsigned write_ptr;
399
400 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
401
402 do {
3ffeabdd 403 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
8ceee660
BH		 404 buffer = &tx_queue->buffer[write_ptr];
405 txd = falcon_tx_desc(tx_queue, write_ptr);
406 ++tx_queue->write_count;
407
408 /* Create TX descriptor ring entry */
3e6c4538
BH		 409 EFX_POPULATE_QWORD_4(*txd,
410 FSF_AZ_TX_KER_CONT, buffer->continuation,
411 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
412 FSF_AZ_TX_KER_BUF_REGION, 0,
413 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
8ceee660
BH		 414 } while (tx_queue->write_count != tx_queue->insert_count);
415
416 wmb(); /* Ensure descriptors are written before they are fetched */
417 falcon_notify_tx_desc(tx_queue);
418}
419
420/* Allocate hardware resources for a TX queue */
421int falcon_probe_tx(struct efx_tx_queue *tx_queue)
422{
423 struct efx_nic *efx = tx_queue->efx;
3ffeabdd
BH		 424 BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
425 EFX_TXQ_SIZE & EFX_TXQ_MASK);
8ceee660 426 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
3ffeabdd 427 EFX_TXQ_SIZE * sizeof(efx_qword_t));
8ceee660
BH		 428}
429
bc3c90a2 430void falcon_init_tx(struct efx_tx_queue *tx_queue)
8ceee660
BH		 431{
432 efx_oword_t tx_desc_ptr;
433 struct efx_nic *efx = tx_queue->efx;
8ceee660 434
6bc5d3a9
BH		 435 tx_queue->flushed = false;
436
8ceee660 437 /* Pin TX descriptor ring */
bc3c90a2 438 falcon_init_special_buffer(efx, &tx_queue->txd);
8ceee660
BH		 439
440 /* Push TX descriptor ring to card */
441 EFX_POPULATE_OWORD_10(tx_desc_ptr,
3e6c4538
BH		 442 FRF_AZ_TX_DESCQ_EN, 1,
443 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
444 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
445 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
446 FRF_AZ_TX_DESCQ_EVQ_ID,
447 tx_queue->channel->channel,
448 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
449 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
3ffeabdd
BH		 450 FRF_AZ_TX_DESCQ_SIZE,
451 __ffs(tx_queue->txd.entries),
3e6c4538
BH		 452 FRF_AZ_TX_DESCQ_TYPE, 0,
453 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
8ceee660 454
55668611 455 if (falcon_rev(efx) >= FALCON_REV_B0) {
60ac1065 456 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
3e6c4538
BH		 457 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
458 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
459 !csum);
8ceee660
BH		 460 }
461
12d00cad
BH		 462 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
463 tx_queue->queue);
8ceee660 464
55668611 465 if (falcon_rev(efx) < FALCON_REV_B0) {
8ceee660
BH		 466 efx_oword_t reg;
467
60ac1065
BH		 468 /* Only 128 bits in this register */
469 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
8ceee660 470
12d00cad 471 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
60ac1065 472 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
8ceee660
BH		 473 clear_bit_le(tx_queue->queue, (void *)&reg);
474 else
475 set_bit_le(tx_queue->queue, (void *)&reg);
12d00cad 476 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
8ceee660 477 }
8ceee660
BH		 478}
479
6bc5d3a9 480static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
8ceee660
BH		 481{
482 struct efx_nic *efx = tx_queue->efx;
8ceee660 483 efx_oword_t tx_flush_descq;
8ceee660
BH		 484
485 /* Post a flush command */
486 EFX_POPULATE_OWORD_2(tx_flush_descq,
3e6c4538
BH		 487 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
488 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
12d00cad 489 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
8ceee660
BH		 490}
491
492void falcon_fini_tx(struct efx_tx_queue *tx_queue)
493{
494 struct efx_nic *efx = tx_queue->efx;
495 efx_oword_t tx_desc_ptr;
496
6bc5d3a9
BH		 497 /* The queue should have been flushed */
498 WARN_ON(!tx_queue->flushed);
8ceee660
BH		 499
500 /* Remove TX descriptor ring from card */
501 EFX_ZERO_OWORD(tx_desc_ptr);
12d00cad
BH		 502 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
503 tx_queue->queue);
8ceee660
BH		 504
505 /* Unpin TX descriptor ring */
506 falcon_fini_special_buffer(efx, &tx_queue->txd);
507}
508
509/* Free buffers backing TX queue */
510void falcon_remove_tx(struct efx_tx_queue *tx_queue)
511{
512 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
513}
514
515/**************************************************************************
516 *
517 * Falcon RX path
518 *
519 **************************************************************************/
520
521/* Returns a pointer to the specified descriptor in the RX descriptor queue */
522static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
523 unsigned int index)
524{
525 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
526}
527
528/* This creates an entry in the RX descriptor queue */
529static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
530 unsigned index)
531{
532 struct efx_rx_buffer *rx_buf;
533 efx_qword_t *rxd;
534
535 rxd = falcon_rx_desc(rx_queue, index);
536 rx_buf = efx_rx_buffer(rx_queue, index);
537 EFX_POPULATE_QWORD_3(*rxd,
3e6c4538 538 FSF_AZ_RX_KER_BUF_SIZE,
8ceee660
BH		 539 rx_buf->len -
540 rx_queue->efx->type->rx_buffer_padding,
3e6c4538
BH		 541 FSF_AZ_RX_KER_BUF_REGION, 0,
542 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
8ceee660
BH		 543}
544
545/* This writes to the RX_DESC_WPTR register for the specified receive
546 * descriptor ring.
547 */
548void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
549{
550 efx_dword_t reg;
551 unsigned write_ptr;
552
553 while (rx_queue->notified_count != rx_queue->added_count) {
554 falcon_build_rx_desc(rx_queue,
555 rx_queue->notified_count &
3ffeabdd 556 EFX_RXQ_MASK);
8ceee660
BH		 557 ++rx_queue->notified_count;
558 }
559
560 wmb();
3ffeabdd 561 write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
3e6c4538 562 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
12d00cad
BH		 563 efx_writed_page(rx_queue->efx, &reg,
564 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
8ceee660
BH		 565}
566
567int falcon_probe_rx(struct efx_rx_queue *rx_queue)
568{
569 struct efx_nic *efx = rx_queue->efx;
3ffeabdd
BH		 570 BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
571 EFX_RXQ_SIZE & EFX_RXQ_MASK);
8ceee660 572 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
3ffeabdd 573 EFX_RXQ_SIZE * sizeof(efx_qword_t));
8ceee660
BH		 574}
575
bc3c90a2 576void falcon_init_rx(struct efx_rx_queue *rx_queue)
8ceee660
BH		 577{
578 efx_oword_t rx_desc_ptr;
579 struct efx_nic *efx = rx_queue->efx;
dc8cfa55
BH		 580 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
581 bool iscsi_digest_en = is_b0;
8ceee660
BH		 582
583 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
584 rx_queue->queue, rx_queue->rxd.index,
585 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
586
6bc5d3a9
BH		 587 rx_queue->flushed = false;
588
8ceee660 589 /* Pin RX descriptor ring */
bc3c90a2 590 falcon_init_special_buffer(efx, &rx_queue->rxd);
8ceee660
BH		 591
592 /* Push RX descriptor ring to card */
593 EFX_POPULATE_OWORD_10(rx_desc_ptr,
3e6c4538
BH		 594 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
595 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
596 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
597 FRF_AZ_RX_DESCQ_EVQ_ID,
598 rx_queue->channel->channel,
599 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
600 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
3ffeabdd
BH		 601 FRF_AZ_RX_DESCQ_SIZE,
602 __ffs(rx_queue->rxd.entries),
3e6c4538 603 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
8ceee660 604 /* For >=B0 this is scatter so disable */
3e6c4538
BH		 605 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
606 FRF_AZ_RX_DESCQ_EN, 1);
12d00cad
BH		 607 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
608 rx_queue->queue);
8ceee660
BH		 609}
610
6bc5d3a9 611static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
8ceee660
BH		 612{
613 struct efx_nic *efx = rx_queue->efx;
8ceee660
BH		 614 efx_oword_t rx_flush_descq;
615
616 /* Post a flush command */
617 EFX_POPULATE_OWORD_2(rx_flush_descq,
3e6c4538
BH		 618 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
619 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
12d00cad 620 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
8ceee660
BH		 621}
622
623void falcon_fini_rx(struct efx_rx_queue *rx_queue)
624{
625 efx_oword_t rx_desc_ptr;
626 struct efx_nic *efx = rx_queue->efx;
8ceee660 627
6bc5d3a9
BH		 628 /* The queue should already have been flushed */
629 WARN_ON(!rx_queue->flushed);
8ceee660
BH		 630
631 /* Remove RX descriptor ring from card */
632 EFX_ZERO_OWORD(rx_desc_ptr);
12d00cad
BH		 633 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
634 rx_queue->queue);
8ceee660
BH		 635
636 /* Unpin RX descriptor ring */
637 falcon_fini_special_buffer(efx, &rx_queue->rxd);
638}
639
640/* Free buffers backing RX queue */
641void falcon_remove_rx(struct efx_rx_queue *rx_queue)
642{
643 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
644}
645
646/**************************************************************************
647 *
648 * Falcon event queue processing
649 * Event queues are processed by per-channel tasklets.
650 *
651 **************************************************************************/
652
653/* Update a channel's event queue's read pointer (RPTR) register
654 *
655 * This writes the EVQ_RPTR_REG register for the specified channel's
656 * event queue.
657 *
658 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
659 * whereas channel->eventq_read_ptr contains the index of the "next to
660 * read" event.
661 */
662void falcon_eventq_read_ack(struct efx_channel *channel)
663{
664 efx_dword_t reg;
665 struct efx_nic *efx = channel->efx;
666
3e6c4538 667 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
12d00cad 668 efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
d3074025 669 channel->channel);
8ceee660
BH		 670}
671
672/* Use HW to insert a SW defined event */
673void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
674{
675 efx_oword_t drv_ev_reg;
676
3e6c4538
BH		 677 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
678 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
679 drv_ev_reg.u32[0] = event->u32[0];
680 drv_ev_reg.u32[1] = event->u32[1];
681 drv_ev_reg.u32[2] = 0;
682 drv_ev_reg.u32[3] = 0;
683 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
12d00cad 684 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
8ceee660
BH		 685}
686
687/* Handle a transmit completion event
688 *
689 * Falcon batches TX completion events; the message we receive is of
690 * the form "complete all TX events up to this index".
691 */
4d566063
BH		 692static void falcon_handle_tx_event(struct efx_channel *channel,
693 efx_qword_t *event)
8ceee660
BH		 694{
695 unsigned int tx_ev_desc_ptr;
696 unsigned int tx_ev_q_label;
697 struct efx_tx_queue *tx_queue;
698 struct efx_nic *efx = channel->efx;
699
3e6c4538 700 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
8ceee660 701 /* Transmit completion */
3e6c4538
BH		 702 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
703 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
8ceee660 704 tx_queue = &efx->tx_queue[tx_ev_q_label];
6fb70fd1
BH		 705 channel->irq_mod_score +=
706 (tx_ev_desc_ptr - tx_queue->read_count) &
3ffeabdd 707 EFX_TXQ_MASK;
8ceee660 708 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
3e6c4538 709 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
8ceee660 710 /* Rewrite the FIFO write pointer */
3e6c4538 711 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
8ceee660
BH		 712 tx_queue = &efx->tx_queue[tx_ev_q_label];
713
55668611 714 if (efx_dev_registered(efx))
8ceee660
BH		 715 netif_tx_lock(efx->net_dev);
716 falcon_notify_tx_desc(tx_queue);
55668611 717 if (efx_dev_registered(efx))
8ceee660 718 netif_tx_unlock(efx->net_dev);
3e6c4538 719 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
8ceee660
BH		 720 EFX_WORKAROUND_10727(efx)) {
721 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
722 } else {
723 EFX_ERR(efx, "channel %d unexpected TX event "
724 EFX_QWORD_FMT"\n", channel->channel,
725 EFX_QWORD_VAL(*event));
726 }
727}
728
8ceee660
BH		 729/* Detect errors included in the rx_evt_pkt_ok bit. */
730static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
731 const efx_qword_t *event,
dc8cfa55
BH		 732 bool *rx_ev_pkt_ok,
733 bool *discard)
8ceee660
BH		 734{
735 struct efx_nic *efx = rx_queue->efx;
dc8cfa55
BH		 736 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
737 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
738 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
739 bool rx_ev_other_err, rx_ev_pause_frm;
740 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
741 unsigned rx_ev_pkt_type;
8ceee660 742
3e6c4538
BH		 743 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
744 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
745 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
746 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
8ceee660 747 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
3e6c4538
BH		 748 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
749 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
8ceee660 750 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
3e6c4538 751 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
8ceee660 752 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
3e6c4538
BH		 753 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
754 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
755 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
55668611 756 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
3e6c4538
BH		 757 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
758 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
8ceee660
BH		 759
760 /* Every error apart from tobe_disc and pause_frm */
761 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
762 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
763 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
764
50050877
BH		 765 /* Count errors that are not in MAC stats. Ignore expected
766 * checksum errors during self-test. */
8ceee660
BH		 767 if (rx_ev_frm_trunc)
768 ++rx_queue->channel->n_rx_frm_trunc;
769 else if (rx_ev_tobe_disc)
770 ++rx_queue->channel->n_rx_tobe_disc;
50050877
BH		 771 else if (!efx->loopback_selftest) {
772 if (rx_ev_ip_hdr_chksum_err)
773 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
774 else if (rx_ev_tcp_udp_chksum_err)
775 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
776 }
8ceee660
BH		 777 if (rx_ev_ip_frag_err)
778 ++rx_queue->channel->n_rx_ip_frag_err;
779
780 /* The frame must be discarded if any of these are true. */
781 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
782 rx_ev_tobe_disc | rx_ev_pause_frm);
783
784 /* TOBE_DISC is expected on unicast mismatches; don't print out an
785 * error message. FRM_TRUNC indicates RXDP dropped the packet due
786 * to a FIFO overflow.
787 */
788#ifdef EFX_ENABLE_DEBUG
789 if (rx_ev_other_err) {
790 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
5b39fe30 791 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
8ceee660
BH		 792 rx_queue->queue, EFX_QWORD_VAL(*event),
793 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
794 rx_ev_ip_hdr_chksum_err ?
795 " [IP_HDR_CHKSUM_ERR]" : "",
796 rx_ev_tcp_udp_chksum_err ?
797 " [TCP_UDP_CHKSUM_ERR]" : "",
798 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
799 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
800 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
801 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
5b39fe30 802 rx_ev_pause_frm ? " [PAUSE]" : "");
8ceee660
BH		 803 }
804#endif
8ceee660
BH		 805}
806
807/* Handle receive events that are not in-order. */
808static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
809 unsigned index)
810{
811 struct efx_nic *efx = rx_queue->efx;
812 unsigned expected, dropped;
813
3ffeabdd
BH		 814 expected = rx_queue->removed_count & EFX_RXQ_MASK;
815 dropped = (index - expected) & EFX_RXQ_MASK;
8ceee660
BH		 816 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
817 dropped, index, expected);
818
819 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
820 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
821}
822
823/* Handle a packet received event
824 *
825 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
826 * wrong destination address
827 * Also "is multicast" and "matches multicast filter" flags can be used to
828 * discard non-matching multicast packets.
829 */
42cbe2d7
BH		 830static void falcon_handle_rx_event(struct efx_channel *channel,
831 const efx_qword_t *event)
8ceee660 832{
42cbe2d7 833 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
dc8cfa55 834 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
8ceee660 835 unsigned expected_ptr;
dc8cfa55 836 bool rx_ev_pkt_ok, discard = false, checksummed;
8ceee660
BH		 837 struct efx_rx_queue *rx_queue;
838 struct efx_nic *efx = channel->efx;
839
840 /* Basic packet information */
3e6c4538
BH		 841 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
842 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
843 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
844 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
845 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
846 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
847 channel->channel);
8ceee660 848
42cbe2d7 849 rx_queue = &efx->rx_queue[channel->channel];
8ceee660 850
3e6c4538 851 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
3ffeabdd 852 expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
42cbe2d7 853 if (unlikely(rx_ev_desc_ptr != expected_ptr))
8ceee660 854 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
8ceee660
BH		 855
856 if (likely(rx_ev_pkt_ok)) {
857 /* If packet is marked as OK and packet type is TCP/IPv4 or
858 * UDP/IPv4, then we can rely on the hardware checksum.
859 */
3e6c4538 860 checksummed =
9c1bbbaf
BH		 861 efx->rx_checksum_enabled &&
862 (rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
863 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP);
8ceee660
BH		 864 } else {
865 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
5b39fe30 866 &discard);
dc8cfa55 867 checksummed = false;
8ceee660
BH		 868 }
869
870 /* Detect multicast packets that didn't match the filter */
3e6c4538 871 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
8ceee660
BH		 872 if (rx_ev_mcast_pkt) {
873 unsigned int rx_ev_mcast_hash_match =
3e6c4538 874 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
8ceee660
BH		 875
876 if (unlikely(!rx_ev_mcast_hash_match))
dc8cfa55 877 discard = true;
8ceee660
BH		 878 }
879
6fb70fd1
BH		 880 channel->irq_mod_score += 2;
881
8ceee660
BH		 882 /* Handle received packet */
883 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
884 checksummed, discard);
8ceee660
BH		 885}
886
887/* Global events are basically PHY events */
888static void falcon_handle_global_event(struct efx_channel *channel,
889 efx_qword_t *event)
890{
891 struct efx_nic *efx = channel->efx;
766ca0fa 892 bool handled = false;
8ceee660 893
3e6c4538
BH		 894 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
895 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
896 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
766ca0fa
BH		 897 efx->phy_op->clear_interrupt(efx);
898 queue_work(efx->workqueue, &efx->phy_work);
899 handled = true;
900 }
8ceee660 901
55668611 902 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
3e6c4538 903 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
766ca0fa 904 queue_work(efx->workqueue, &efx->mac_work);
dc8cfa55 905 handled = true;
8ceee660
BH		 906 }
907
56241ceb 908 if (falcon_rev(efx) <= FALCON_REV_A1 ?
3e6c4538
BH		 909 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
910 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
8ceee660
BH		 911 EFX_ERR(efx, "channel %d seen global RX_RESET "
912 "event. Resetting.\n", channel->channel);
913
914 atomic_inc(&efx->rx_reset);
915 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
916 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
dc8cfa55 917 handled = true;
8ceee660
BH		 918 }
919
920 if (!handled)
921 EFX_ERR(efx, "channel %d unknown global event "
922 EFX_QWORD_FMT "\n", channel->channel,
923 EFX_QWORD_VAL(*event));
924}
925
926static void falcon_handle_driver_event(struct efx_channel *channel,
927 efx_qword_t *event)
928{
929 struct efx_nic *efx = channel->efx;
930 unsigned int ev_sub_code;
931 unsigned int ev_sub_data;
932
3e6c4538
BH		 933 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
934 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
8ceee660
BH		 935
936 switch (ev_sub_code) {
3e6c4538 937 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
8ceee660
BH		 938 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
939 channel->channel, ev_sub_data);
940 break;
3e6c4538 941 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
8ceee660
BH		 942 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
943 channel->channel, ev_sub_data);
944 break;
3e6c4538 945 case FSE_AZ_EVQ_INIT_DONE_EV:
8ceee660
BH		 946 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
947 channel->channel, ev_sub_data);
948 break;
3e6c4538 949 case FSE_AZ_SRM_UPD_DONE_EV:
8ceee660
BH		 950 EFX_TRACE(efx, "channel %d SRAM update done\n",
951 channel->channel);
952 break;
3e6c4538 953 case FSE_AZ_WAKE_UP_EV:
8ceee660
BH		 954 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
955 channel->channel, ev_sub_data);
956 break;
3e6c4538 957 case FSE_AZ_TIMER_EV:
8ceee660
BH		 958 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
959 channel->channel, ev_sub_data);
960 break;
3e6c4538 961 case FSE_AA_RX_RECOVER_EV:
8ceee660
BH		 962 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
963 "Resetting.\n", channel->channel);
05e3ec04 964 atomic_inc(&efx->rx_reset);
8ceee660
BH		 965 efx_schedule_reset(efx,
966 EFX_WORKAROUND_6555(efx) ?
967 RESET_TYPE_RX_RECOVERY :
968 RESET_TYPE_DISABLE);
969 break;
3e6c4538 970 case FSE_BZ_RX_DSC_ERROR_EV:
8ceee660
BH		 971 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
972 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
973 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
974 break;
3e6c4538 975 case FSE_BZ_TX_DSC_ERROR_EV:
8ceee660
BH		 976 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
977 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
978 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
979 break;
980 default:
981 EFX_TRACE(efx, "channel %d unknown driver event code %d "
982 "data %04x\n", channel->channel, ev_sub_code,
983 ev_sub_data);
984 break;
985 }
986}
987
42cbe2d7 988int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
8ceee660
BH		 989{
990 unsigned int read_ptr;
991 efx_qword_t event, *p_event;
992 int ev_code;
42cbe2d7 993 int rx_packets = 0;
8ceee660
BH		 994
995 read_ptr = channel->eventq_read_ptr;
996
997 do {
998 p_event = falcon_event(channel, read_ptr);
999 event = *p_event;
1000
1001 if (!falcon_event_present(&event))
1002 /* End of events */
1003 break;
1004
1005 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1006 channel->channel, EFX_QWORD_VAL(event));
1007
1008 /* Clear this event by marking it all ones */
1009 EFX_SET_QWORD(*p_event);
1010
3e6c4538 1011 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
8ceee660
BH		 1012
1013 switch (ev_code) {
3e6c4538 1014 case FSE_AZ_EV_CODE_RX_EV:
42cbe2d7
BH		 1015 falcon_handle_rx_event(channel, &event);
1016 ++rx_packets;
8ceee660 1017 break;
3e6c4538 1018 case FSE_AZ_EV_CODE_TX_EV:
8ceee660
BH		 1019 falcon_handle_tx_event(channel, &event);
1020 break;
3e6c4538
BH		 1021 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1022 channel->eventq_magic = EFX_QWORD_FIELD(
1023 event, FSF_AZ_DRV_GEN_EV_MAGIC);
8ceee660
BH		 1024 EFX_LOG(channel->efx, "channel %d received generated "
1025 "event "EFX_QWORD_FMT"\n", channel->channel,
1026 EFX_QWORD_VAL(event));
1027 break;
3e6c4538 1028 case FSE_AZ_EV_CODE_GLOBAL_EV:
8ceee660
BH		 1029 falcon_handle_global_event(channel, &event);
1030 break;
3e6c4538 1031 case FSE_AZ_EV_CODE_DRIVER_EV:
8ceee660
BH		 1032 falcon_handle_driver_event(channel, &event);
1033 break;
1034 default:
1035 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1036 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1037 ev_code, EFX_QWORD_VAL(event));
1038 }
1039
1040 /* Increment read pointer */
3ffeabdd 1041 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
8ceee660 1042
42cbe2d7 1043 } while (rx_packets < rx_quota);
8ceee660
BH		 1044
1045 channel->eventq_read_ptr = read_ptr;
42cbe2d7 1046 return rx_packets;
8ceee660
BH		 1047}
1048
1049void falcon_set_int_moderation(struct efx_channel *channel)
1050{
1051 efx_dword_t timer_cmd;
1052 struct efx_nic *efx = channel->efx;
1053
1054 /* Set timer register */
1055 if (channel->irq_moderation) {
8ceee660 1056 EFX_POPULATE_DWORD_2(timer_cmd,
3e6c4538
BH		 1057 FRF_AB_TC_TIMER_MODE,
1058 FFE_BB_TIMER_MODE_INT_HLDOFF,
1059 FRF_AB_TC_TIMER_VAL,
0d86ebd8 1060 channel->irq_moderation - 1);
8ceee660
BH		 1061 } else {
1062 EFX_POPULATE_DWORD_2(timer_cmd,
3e6c4538
BH		 1063 FRF_AB_TC_TIMER_MODE,
1064 FFE_BB_TIMER_MODE_DIS,
1065 FRF_AB_TC_TIMER_VAL, 0);
8ceee660 1066 }
3e6c4538 1067 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
12d00cad
BH		 1068 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1069 channel->channel);
8ceee660
BH		 1070
1071}
1072
1073/* Allocate buffer table entries for event queue */
1074int falcon_probe_eventq(struct efx_channel *channel)
1075{
1076 struct efx_nic *efx = channel->efx;
3ffeabdd
BH		 1077 BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1078 EFX_EVQ_SIZE & EFX_EVQ_MASK);
1079 return falcon_alloc_special_buffer(efx, &channel->eventq,
1080 EFX_EVQ_SIZE * sizeof(efx_qword_t));
8ceee660
BH		 1081}
1082
bc3c90a2 1083void falcon_init_eventq(struct efx_channel *channel)
8ceee660
BH		 1084{
1085 efx_oword_t evq_ptr;
1086 struct efx_nic *efx = channel->efx;
8ceee660
BH		 1087
1088 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1089 channel->channel, channel->eventq.index,
1090 channel->eventq.index + channel->eventq.entries - 1);
1091
1092 /* Pin event queue buffer */
bc3c90a2 1093 falcon_init_special_buffer(efx, &channel->eventq);
8ceee660
BH		 1094
1095 /* Fill event queue with all ones (i.e. empty events) */
1096 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1097
1098 /* Push event queue to card */
1099 EFX_POPULATE_OWORD_3(evq_ptr,
3e6c4538 1100 FRF_AZ_EVQ_EN, 1,
3ffeabdd 1101 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
3e6c4538 1102 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
12d00cad
BH		 1103 efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1104 channel->channel);
8ceee660
BH		 1105
1106 falcon_set_int_moderation(channel);
8ceee660
BH		 1107}
1108
1109void falcon_fini_eventq(struct efx_channel *channel)
1110{
1111 efx_oword_t eventq_ptr;
1112 struct efx_nic *efx = channel->efx;
1113
1114 /* Remove event queue from card */
1115 EFX_ZERO_OWORD(eventq_ptr);
12d00cad
BH		 1116 efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1117 channel->channel);
8ceee660
BH		 1118
1119 /* Unpin event queue */
1120 falcon_fini_special_buffer(efx, &channel->eventq);
1121}
1122
1123/* Free buffers backing event queue */
1124void falcon_remove_eventq(struct efx_channel *channel)
1125{
1126 falcon_free_special_buffer(channel->efx, &channel->eventq);
1127}
1128
1129
1130/* Generates a test event on the event queue. A subsequent call to
1131 * process_eventq() should pick up the event and place the value of
1132 * "magic" into channel->eventq_magic;
1133 */
1134void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1135{
1136 efx_qword_t test_event;
1137
3e6c4538
BH		 1138 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1139 FSE_AZ_EV_CODE_DRV_GEN_EV,
1140 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
8ceee660
BH		 1141 falcon_generate_event(channel, &test_event);
1142}
1143
177dfcd8
BH		 1144void falcon_sim_phy_event(struct efx_nic *efx)
1145{
1146 efx_qword_t phy_event;
1147
3e6c4538
BH		 1148 EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1149 FSE_AZ_EV_CODE_GLOBAL_EV);
177dfcd8 1150 if (EFX_IS10G(efx))
3e6c4538 1151 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
177dfcd8 1152 else
3e6c4538 1153 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
177dfcd8
BH		 1154
1155 falcon_generate_event(&efx->channel[0], &phy_event);
1156}
1157
6bc5d3a9
BH		 1158/**************************************************************************
1159 *
1160 * Flush handling
1161 *
1162 **************************************************************************/
1163
1164
1165static void falcon_poll_flush_events(struct efx_nic *efx)
1166{
1167 struct efx_channel *channel = &efx->channel[0];
1168 struct efx_tx_queue *tx_queue;
1169 struct efx_rx_queue *rx_queue;
4720bc6c 1170 unsigned int read_ptr = channel->eventq_read_ptr;
3ffeabdd 1171 unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
6bc5d3a9 1172
4720bc6c 1173 do {
6bc5d3a9
BH		 1174 efx_qword_t *event = falcon_event(channel, read_ptr);
1175 int ev_code, ev_sub_code, ev_queue;
1176 bool ev_failed;
4720bc6c 1177
6bc5d3a9
BH		 1178 if (!falcon_event_present(event))
1179 break;
1180
3e6c4538
BH		 1181 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1182 ev_sub_code = EFX_QWORD_FIELD(*event,
1183 FSF_AZ_DRIVER_EV_SUBCODE);
1184 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1185 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
6bc5d3a9 1186 ev_queue = EFX_QWORD_FIELD(*event,
3e6c4538 1187 FSF_AZ_DRIVER_EV_SUBDATA);
6bc5d3a9
BH		 1188 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1189 tx_queue = efx->tx_queue + ev_queue;
1190 tx_queue->flushed = true;
1191 }
3e6c4538
BH		 1192 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1193 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1194 ev_queue = EFX_QWORD_FIELD(
1195 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1196 ev_failed = EFX_QWORD_FIELD(
1197 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
6bc5d3a9
BH		 1198 if (ev_queue < efx->n_rx_queues) {
1199 rx_queue = efx->rx_queue + ev_queue;
1200
1201 /* retry the rx flush */
1202 if (ev_failed)
1203 falcon_flush_rx_queue(rx_queue);
1204 else
1205 rx_queue->flushed = true;
1206 }
6bc5d3a9
BH		 1207 }
1208
3ffeabdd 1209 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
4720bc6c 1210 } while (read_ptr != end_ptr);
6bc5d3a9
BH		 1211}
1212
1213/* Handle tx and rx flushes at the same time, since they run in
1214 * parallel in the hardware and there's no reason for us to
1215 * serialise them */
1216int falcon_flush_queues(struct efx_nic *efx)
1217{
1218 struct efx_rx_queue *rx_queue;
1219 struct efx_tx_queue *tx_queue;
1220 int i;
1221 bool outstanding;
1222
1223 /* Issue flush requests */
1224 efx_for_each_tx_queue(tx_queue, efx) {
1225 tx_queue->flushed = false;
1226 falcon_flush_tx_queue(tx_queue);
1227 }
1228 efx_for_each_rx_queue(rx_queue, efx) {
1229 rx_queue->flushed = false;
1230 falcon_flush_rx_queue(rx_queue);
1231 }
1232
1233 /* Poll the evq looking for flush completions. Since we're not pushing
1234 * any more rx or tx descriptors at this point, we're in no danger of
1235 * overflowing the evq whilst we wait */
1236 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1237 msleep(FALCON_FLUSH_INTERVAL);
1238 falcon_poll_flush_events(efx);
1239
1240 /* Check if every queue has been succesfully flushed */
1241 outstanding = false;
1242 efx_for_each_tx_queue(tx_queue, efx)
1243 outstanding |= !tx_queue->flushed;
1244 efx_for_each_rx_queue(rx_queue, efx)
1245 outstanding |= !rx_queue->flushed;
1246 if (!outstanding)
1247 return 0;
1248 }
1249
1250 /* Mark the queues as all flushed. We're going to return failure
1251 * leading to a reset, or fake up success anyway. "flushed" now
1252 * indicates that we tried to flush. */
1253 efx_for_each_tx_queue(tx_queue, efx) {
1254 if (!tx_queue->flushed)
1255 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1256 tx_queue->queue);
1257 tx_queue->flushed = true;
1258 }
1259 efx_for_each_rx_queue(rx_queue, efx) {
1260 if (!rx_queue->flushed)
1261 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1262 rx_queue->queue);
1263 rx_queue->flushed = true;
1264 }
1265
1266 if (EFX_WORKAROUND_7803(efx))
1267 return 0;
1268
1269 return -ETIMEDOUT;
1270}
8ceee660
BH		 1271
1272/**************************************************************************
1273 *
1274 * Falcon hardware interrupts
1275 * The hardware interrupt handler does very little work; all the event
1276 * queue processing is carried out by per-channel tasklets.
1277 *
1278 **************************************************************************/
1279
1280/* Enable/disable/generate Falcon interrupts */
1281static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1282 int force)
1283{
1284 efx_oword_t int_en_reg_ker;
1285
1286 EFX_POPULATE_OWORD_2(int_en_reg_ker,
3e6c4538
BH		 1287 FRF_AZ_KER_INT_KER, force,
1288 FRF_AZ_DRV_INT_EN_KER, enabled);
12d00cad 1289 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
8ceee660
BH		 1290}
1291
1292void falcon_enable_interrupts(struct efx_nic *efx)
1293{
1294 efx_oword_t int_adr_reg_ker;
1295 struct efx_channel *channel;
1296
1297 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1298 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1299
1300 /* Program address */
1301 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
3e6c4538
BH		 1302 FRF_AZ_NORM_INT_VEC_DIS_KER,
1303 EFX_INT_MODE_USE_MSI(efx),
1304 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
12d00cad 1305 efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
8ceee660
BH		 1306
1307 /* Enable interrupts */
1308 falcon_interrupts(efx, 1, 0);
1309
1310 /* Force processing of all the channels to get the EVQ RPTRs up to
1311 date */
64ee3120 1312 efx_for_each_channel(channel, efx)
8ceee660
BH		 1313 efx_schedule_channel(channel);
1314}
1315
1316void falcon_disable_interrupts(struct efx_nic *efx)
1317{
1318 /* Disable interrupts */
1319 falcon_interrupts(efx, 0, 0);
1320}
1321
1322/* Generate a Falcon test interrupt
1323 * Interrupt must already have been enabled, otherwise nasty things
1324 * may happen.
1325 */
1326void falcon_generate_interrupt(struct efx_nic *efx)
1327{
1328 falcon_interrupts(efx, 1, 1);
1329}
1330
1331/* Acknowledge a legacy interrupt from Falcon
1332 *
1333 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1334 *
1335 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1336 * BIU. Interrupt acknowledge is read sensitive so must write instead
1337 * (then read to ensure the BIU collector is flushed)
1338 *
1339 * NB most hardware supports MSI interrupts
1340 */
1341static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1342{
1343 efx_dword_t reg;
1344
3e6c4538 1345 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
12d00cad
BH		 1346 efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
1347 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
8ceee660
BH		 1348}
1349
1350/* Process a fatal interrupt
1351 * Disable bus mastering ASAP and schedule a reset
1352 */
1353static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1354{
1355 struct falcon_nic_data *nic_data = efx->nic_data;
d3208b5e 1356 efx_oword_t *int_ker = efx->irq_status.addr;
8ceee660
BH		 1357 efx_oword_t fatal_intr;
1358 int error, mem_perr;
8ceee660 1359
12d00cad 1360 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
3e6c4538 1361 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
8ceee660
BH		 1362
1363 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1364 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1365 EFX_OWORD_VAL(fatal_intr),
1366 error ? "disabling bus mastering" : "no recognised error");
1367 if (error == 0)
1368 goto out;
1369
1370 /* If this is a memory parity error dump which blocks are offending */
3e6c4538 1371 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
8ceee660
BH		 1372 if (mem_perr) {
1373 efx_oword_t reg;
12d00cad 1374 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
8ceee660
BH		 1375 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1376 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1377 }
1378
0a62f1a6 1379 /* Disable both devices */
ef1bba28 1380 pci_clear_master(efx->pci_dev);
8ceee660 1381 if (FALCON_IS_DUAL_FUNC(efx))
ef1bba28 1382 pci_clear_master(nic_data->pci_dev2);
0a62f1a6 1383 falcon_disable_interrupts(efx);
8ceee660 1384
2c3c3d02 1385 /* Count errors and reset or disable the NIC accordingly */
0484e0db
BH		 1386 if (efx->int_error_count == 0 ||
1387 time_after(jiffies, efx->int_error_expire)) {
1388 efx->int_error_count = 0;
1389 efx->int_error_expire =
2c3c3d02
BH		 1390 jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1391 }
0484e0db 1392 if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) {
8ceee660
BH		 1393 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1394 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1395 } else {
1396 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1397 "NIC will be disabled\n");
1398 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1399 }
1400out:
1401 return IRQ_HANDLED;
1402}
1403
1404/* Handle a legacy interrupt from Falcon
1405 * Acknowledges the interrupt and schedule event queue processing.
1406 */
1407static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1408{
d3208b5e
BH		 1409 struct efx_nic *efx = dev_id;
1410 efx_oword_t *int_ker = efx->irq_status.addr;
a9de9a74 1411 irqreturn_t result = IRQ_NONE;
8ceee660
BH		 1412 struct efx_channel *channel;
1413 efx_dword_t reg;
1414 u32 queues;
1415 int syserr;
1416
1417 /* Read the ISR which also ACKs the interrupts */
12d00cad 1418 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
8ceee660
BH		 1419 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1420
1421 /* Check to see if we have a serious error condition */
3e6c4538 1422 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
8ceee660
BH		 1423 if (unlikely(syserr))
1424 return falcon_fatal_interrupt(efx);
1425
8ceee660 1426 /* Schedule processing of any interrupting queues */
a9de9a74
BH		 1427 efx_for_each_channel(channel, efx) {
1428 if ((queues & 1) ||
1429 falcon_event_present(
1430 falcon_event(channel, channel->eventq_read_ptr))) {
8ceee660 1431 efx_schedule_channel(channel);
a9de9a74
BH		 1432 result = IRQ_HANDLED;
1433 }
8ceee660
BH		 1434 queues >>= 1;
1435 }
1436
a9de9a74
BH		 1437 if (result == IRQ_HANDLED) {
1438 efx->last_irq_cpu = raw_smp_processor_id();
1439 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1440 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1441 }
1442
1443 return result;
8ceee660
BH		 1444}
1445
1446
1447static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1448{
d3208b5e
BH		 1449 struct efx_nic *efx = dev_id;
1450 efx_oword_t *int_ker = efx->irq_status.addr;
8ceee660
BH		 1451 struct efx_channel *channel;
1452 int syserr;
1453 int queues;
1454
1455 /* Check to see if this is our interrupt. If it isn't, we
1456 * exit without having touched the hardware.
1457 */
1458 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1459 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1460 raw_smp_processor_id());
1461 return IRQ_NONE;
1462 }
1463 efx->last_irq_cpu = raw_smp_processor_id();
1464 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1465 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1466
1467 /* Check to see if we have a serious error condition */
3e6c4538 1468 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
8ceee660
BH		 1469 if (unlikely(syserr))
1470 return falcon_fatal_interrupt(efx);
1471
1472 /* Determine interrupting queues, clear interrupt status
1473 * register and acknowledge the device interrupt.
1474 */
1475 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1476 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1477 EFX_ZERO_OWORD(*int_ker);
1478 wmb(); /* Ensure the vector is cleared before interrupt ack */
1479 falcon_irq_ack_a1(efx);
1480
1481 /* Schedule processing of any interrupting queues */
1482 channel = &efx->channel[0];
1483 while (queues) {
1484 if (queues & 0x01)
1485 efx_schedule_channel(channel);
1486 channel++;
1487 queues >>= 1;
1488 }
1489
1490 return IRQ_HANDLED;
1491}
1492
1493/* Handle an MSI interrupt from Falcon
1494 *
1495 * Handle an MSI hardware interrupt. This routine schedules event
1496 * queue processing. No interrupt acknowledgement cycle is necessary.
1497 * Also, we never need to check that the interrupt is for us, since
1498 * MSI interrupts cannot be shared.
1499 */
1500static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1501{
d3208b5e 1502 struct efx_channel *channel = dev_id;
8ceee660 1503 struct efx_nic *efx = channel->efx;
d3208b5e 1504 efx_oword_t *int_ker = efx->irq_status.addr;
8ceee660
BH		 1505 int syserr;
1506
1507 efx->last_irq_cpu = raw_smp_processor_id();
1508 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1509 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1510
1511 /* Check to see if we have a serious error condition */
1512 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1513 if (unlikely(syserr))
1514 return falcon_fatal_interrupt(efx);
1515
1516 /* Schedule processing of the channel */
1517 efx_schedule_channel(channel);
1518
1519 return IRQ_HANDLED;
1520}
1521
1522
1523/* Setup RSS indirection table.
1524 * This maps from the hash value of the packet to RXQ
1525 */
1526static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1527{
1528 int i = 0;
1529 unsigned long offset;
1530 efx_dword_t dword;
1531
55668611 1532 if (falcon_rev(efx) < FALCON_REV_B0)
8ceee660
BH		 1533 return;
1534
3e6c4538
BH		 1535 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1536 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
8ceee660 1537 offset += 0x10) {
3e6c4538 1538 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
8831da7b 1539 i % efx->n_rx_queues);
12d00cad 1540 efx_writed(efx, &dword, offset);
8ceee660
BH		 1541 i++;
1542 }
1543}
1544
1545/* Hook interrupt handler(s)
1546 * Try MSI and then legacy interrupts.
1547 */
1548int falcon_init_interrupt(struct efx_nic *efx)
1549{
1550 struct efx_channel *channel;
1551 int rc;
1552
1553 if (!EFX_INT_MODE_USE_MSI(efx)) {
1554 irq_handler_t handler;
55668611 1555 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 1556 handler = falcon_legacy_interrupt_b0;
1557 else
1558 handler = falcon_legacy_interrupt_a1;
1559
1560 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1561 efx->name, efx);
1562 if (rc) {
1563 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1564 efx->pci_dev->irq);
1565 goto fail1;
1566 }
1567 return 0;
1568 }
1569
1570 /* Hook MSI or MSI-X interrupt */
64ee3120 1571 efx_for_each_channel(channel, efx) {
8ceee660
BH		 1572 rc = request_irq(channel->irq, falcon_msi_interrupt,
1573 IRQF_PROBE_SHARED, /* Not shared */
56536e9c 1574 channel->name, channel);
8ceee660
BH		 1575 if (rc) {
1576 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1577 goto fail2;
1578 }
1579 }
1580
1581 return 0;
1582
1583 fail2:
64ee3120 1584 efx_for_each_channel(channel, efx)
8ceee660
BH		 1585 free_irq(channel->irq, channel);
1586 fail1:
1587 return rc;
1588}
1589
1590void falcon_fini_interrupt(struct efx_nic *efx)
1591{
1592 struct efx_channel *channel;
1593 efx_oword_t reg;
1594
1595 /* Disable MSI/MSI-X interrupts */
64ee3120 1596 efx_for_each_channel(channel, efx) {
8ceee660
BH		 1597 if (channel->irq)
1598 free_irq(channel->irq, channel);
b3475645 1599 }
8ceee660
BH		 1600
1601 /* ACK legacy interrupt */
55668611 1602 if (falcon_rev(efx) >= FALCON_REV_B0)
12d00cad 1603 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
8ceee660
BH		 1604 else
1605 falcon_irq_ack_a1(efx);
1606
1607 /* Disable legacy interrupt */
1608 if (efx->legacy_irq)
1609 free_irq(efx->legacy_irq, efx);
1610}
1611
1612/**************************************************************************
1613 *
1614 * EEPROM/flash
1615 *
1616 **************************************************************************
1617 */
1618
23d30f02 1619#define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
8ceee660 1620
be4ea89c
BH		 1621static int falcon_spi_poll(struct efx_nic *efx)
1622{
1623 efx_oword_t reg;
12d00cad 1624 efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
3e6c4538 1625 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
be4ea89c
BH		 1626}
1627
8ceee660
BH		 1628/* Wait for SPI command completion */
1629static int falcon_spi_wait(struct efx_nic *efx)
1630{
be4ea89c
BH		 1631 /* Most commands will finish quickly, so we start polling at
1632 * very short intervals. Sometimes the command may have to
1633 * wait for VPD or expansion ROM access outside of our
1634 * control, so we allow up to 100 ms. */
1635 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1636 int i;
1637
1638 for (i = 0; i < 10; i++) {
1639 if (!falcon_spi_poll(efx))
1640 return 0;
1641 udelay(10);
1642 }
8ceee660 1643
4a5b504d 1644 for (;;) {
be4ea89c 1645 if (!falcon_spi_poll(efx))
8ceee660 1646 return 0;
4a5b504d
BH		 1647 if (time_after_eq(jiffies, timeout)) {
1648 EFX_ERR(efx, "timed out waiting for SPI\n");
1649 return -ETIMEDOUT;
1650 }
be4ea89c 1651 schedule_timeout_uninterruptible(1);
4a5b504d 1652 }
8ceee660
BH		 1653}
1654
f4150724
BH		 1655int falcon_spi_cmd(const struct efx_spi_device *spi,
1656 unsigned int command, int address,
23d30f02 1657 const void *in, void *out, size_t len)
8ceee660 1658{
4a5b504d
BH		 1659 struct efx_nic *efx = spi->efx;
1660 bool addressed = (address >= 0);
1661 bool reading = (out != NULL);
8ceee660
BH		 1662 efx_oword_t reg;
1663 int rc;
1664
4a5b504d
BH		 1665 /* Input validation */
1666 if (len > FALCON_SPI_MAX_LEN)
1667 return -EINVAL;
f4150724 1668 BUG_ON(!mutex_is_locked(&efx->spi_lock));
8ceee660 1669
be4ea89c
BH		 1670 /* Check that previous command is not still running */
1671 rc = falcon_spi_poll(efx);
8ceee660
BH		 1672 if (rc)
1673 return rc;
1674
4a5b504d
BH		 1675 /* Program address register, if we have an address */
1676 if (addressed) {
3e6c4538 1677 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
12d00cad 1678 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
4a5b504d
BH		 1679 }
1680
1681 /* Program data register, if we have data */
1682 if (in != NULL) {
1683 memcpy(&reg, in, len);
12d00cad 1684 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
4a5b504d 1685 }
8ceee660 1686
4a5b504d 1687 /* Issue read/write command */
8ceee660 1688 EFX_POPULATE_OWORD_7(reg,
3e6c4538
BH		 1689 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1690 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1691 FRF_AB_EE_SPI_HCMD_DABCNT, len,
1692 FRF_AB_EE_SPI_HCMD_READ, reading,
1693 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1694 FRF_AB_EE_SPI_HCMD_ADBCNT,
4a5b504d 1695 (addressed ? spi->addr_len : 0),
3e6c4538 1696 FRF_AB_EE_SPI_HCMD_ENC, command);
12d00cad 1697 efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
8ceee660 1698
4a5b504d 1699 /* Wait for read/write to complete */
8ceee660
BH		 1700 rc = falcon_spi_wait(efx);
1701 if (rc)
1702 return rc;
1703
1704 /* Read data */
4a5b504d 1705 if (out != NULL) {
12d00cad 1706 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
4a5b504d
BH		 1707 memcpy(out, &reg, len);
1708 }
1709
8ceee660
BH		 1710 return 0;
1711}
1712
23d30f02
BH		 1713static size_t
1714falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
4a5b504d
BH		 1715{
1716 return min(FALCON_SPI_MAX_LEN,
1717 (spi->block_size - (start & (spi->block_size - 1))));
1718}
1719
1720static inline u8
1721efx_spi_munge_command(const struct efx_spi_device *spi,
1722 const u8 command, const unsigned int address)
1723{
1724 return command | (((address >> 8) & spi->munge_address) << 3);
1725}
1726
be4ea89c
BH		 1727/* Wait up to 10 ms for buffered write completion */
1728int falcon_spi_wait_write(const struct efx_spi_device *spi)
4a5b504d 1729{
be4ea89c
BH		 1730 struct efx_nic *efx = spi->efx;
1731 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
4a5b504d 1732 u8 status;
be4ea89c 1733 int rc;
4a5b504d 1734
be4ea89c 1735 for (;;) {
4a5b504d
BH		 1736 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1737 &status, sizeof(status));
1738 if (rc)
1739 return rc;
1740 if (!(status & SPI_STATUS_NRDY))
1741 return 0;
be4ea89c
BH		 1742 if (time_after_eq(jiffies, timeout)) {
1743 EFX_ERR(efx, "SPI write timeout on device %d"
1744 " last status=0x%02x\n",
1745 spi->device_id, status);
1746 return -ETIMEDOUT;
1747 }
1748 schedule_timeout_uninterruptible(1);
4a5b504d 1749 }
4a5b504d
BH		 1750}
1751
1752int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1753 size_t len, size_t *retlen, u8 *buffer)
1754{
23d30f02
BH		 1755 size_t block_len, pos = 0;
1756 unsigned int command;
4a5b504d
BH		 1757 int rc = 0;
1758
1759 while (pos < len) {
23d30f02 1760 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
4a5b504d
BH		 1761
1762 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1763 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1764 buffer + pos, block_len);
1765 if (rc)
1766 break;
1767 pos += block_len;
1768
1769 /* Avoid locking up the system */
1770 cond_resched();
1771 if (signal_pending(current)) {
1772 rc = -EINTR;
1773 break;
1774 }
1775 }
1776
1777 if (retlen)
1778 *retlen = pos;
1779 return rc;
1780}
1781
1782int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1783 size_t len, size_t *retlen, const u8 *buffer)
1784{
1785 u8 verify_buffer[FALCON_SPI_MAX_LEN];
23d30f02
BH		 1786 size_t block_len, pos = 0;
1787 unsigned int command;
4a5b504d
BH		 1788 int rc = 0;
1789
1790 while (pos < len) {
1791 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1792 if (rc)
1793 break;
1794
23d30f02 1795 block_len = min(len - pos,
4a5b504d
BH		 1796 falcon_spi_write_limit(spi, start + pos));
1797 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1798 rc = falcon_spi_cmd(spi, command, start + pos,
1799 buffer + pos, NULL, block_len);
1800 if (rc)
1801 break;
1802
be4ea89c 1803 rc = falcon_spi_wait_write(spi);
4a5b504d
BH		 1804 if (rc)
1805 break;
1806
1807 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1808 rc = falcon_spi_cmd(spi, command, start + pos,
1809 NULL, verify_buffer, block_len);
1810 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1811 rc = -EIO;
1812 break;
1813 }
1814
1815 pos += block_len;
1816
1817 /* Avoid locking up the system */
1818 cond_resched();
1819 if (signal_pending(current)) {
1820 rc = -EINTR;
1821 break;
1822 }
1823 }
1824
1825 if (retlen)
1826 *retlen = pos;
1827 return rc;
1828}
1829
8ceee660
BH		 1830/**************************************************************************
1831 *
1832 * MAC wrapper
1833 *
1834 **************************************************************************
1835 */
177dfcd8
BH		 1836
1837static int falcon_reset_macs(struct efx_nic *efx)
8ceee660 1838{
177dfcd8 1839 efx_oword_t reg;
8ceee660
BH		 1840 int count;
1841
177dfcd8
BH		 1842 if (falcon_rev(efx) < FALCON_REV_B0) {
1843 /* It's not safe to use GLB_CTL_REG to reset the
1844 * macs, so instead use the internal MAC resets
1845 */
1846 if (!EFX_IS10G(efx)) {
3e6c4538 1847 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
12d00cad 1848 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
177dfcd8
BH		 1849 udelay(1000);
1850
3e6c4538 1851 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
12d00cad 1852 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
177dfcd8
BH		 1853 udelay(1000);
1854 return 0;
1855 } else {
3e6c4538 1856 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
12d00cad 1857 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
177dfcd8
BH		 1858
1859 for (count = 0; count < 10000; count++) {
12d00cad 1860 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
3e6c4538
BH		 1861 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1862 0)
177dfcd8
BH		 1863 return 0;
1864 udelay(10);
1865 }
8ceee660 1866
177dfcd8
BH		 1867 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1868 return -ETIMEDOUT;
1869 }
1870 }
8ceee660
BH		 1871
1872 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1873 * the drain sequence with the statistics fetch */
1974cc20 1874 efx_stats_disable(efx);
8ceee660 1875
12d00cad 1876 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
3e6c4538 1877 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
12d00cad 1878 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
8ceee660 1879
12d00cad 1880 efx_reado(efx, &reg, FR_AB_GLB_CTL);
3e6c4538
BH		 1881 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1882 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1883 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
12d00cad 1884 efx_writeo(efx, &reg, FR_AB_GLB_CTL);
8ceee660
BH		 1885
1886 count = 0;
1887 while (1) {
12d00cad 1888 efx_reado(efx, &reg, FR_AB_GLB_CTL);
3e6c4538
BH		 1889 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1890 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1891 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
8ceee660
BH		 1892 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1893 count);
1894 break;
1895 }
1896 if (count > 20) {
1897 EFX_ERR(efx, "MAC reset failed\n");
1898 break;
1899 }
1900 count++;
1901 udelay(10);
1902 }
1903
1974cc20 1904 efx_stats_enable(efx);
8ceee660
BH		 1905
1906 /* If we've reset the EM block and the link is up, then
1907 * we'll have to kick the XAUI link so the PHY can recover */
177dfcd8 1908 if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
8ceee660 1909 falcon_reset_xaui(efx);
177dfcd8
BH		 1910
1911 return 0;
1912}
1913
1914void falcon_drain_tx_fifo(struct efx_nic *efx)
1915{
1916 efx_oword_t reg;
1917
1918 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1919 (efx->loopback_mode != LOOPBACK_NONE))
1920 return;
1921
12d00cad 1922 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
177dfcd8 1923 /* There is no point in draining more than once */
3e6c4538 1924 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
177dfcd8
BH		 1925 return;
1926
1927 falcon_reset_macs(efx);
8ceee660
BH		 1928}
1929
1930void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1931{
177dfcd8 1932 efx_oword_t reg;
8ceee660 1933
55668611 1934 if (falcon_rev(efx) < FALCON_REV_B0)
8ceee660
BH		 1935 return;
1936
1937 /* Isolate the MAC -> RX */
12d00cad 1938 efx_reado(efx, &reg, FR_AZ_RX_CFG);
3e6c4538 1939 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
12d00cad 1940 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
8ceee660
BH		 1941
1942 if (!efx->link_up)
1943 falcon_drain_tx_fifo(efx);
1944}
1945
1946void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1947{
1948 efx_oword_t reg;
1949 int link_speed;
dc8cfa55 1950 bool tx_fc;
8ceee660 1951
f31a45d2
BH		 1952 switch (efx->link_speed) {
1953 case 10000: link_speed = 3; break;
1954 case 1000: link_speed = 2; break;
1955 case 100: link_speed = 1; break;
1956 default: link_speed = 0; break;
1957 }
8ceee660
BH		 1958 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1959 * as advertised. Disable to ensure packets are not
1960 * indefinitely held and TX queue can be flushed at any point
1961 * while the link is down. */
1962 EFX_POPULATE_OWORD_5(reg,
3e6c4538
BH		 1963 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1964 FRF_AB_MAC_BCAD_ACPT, 1,
1965 FRF_AB_MAC_UC_PROM, efx->promiscuous,
1966 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1967 FRF_AB_MAC_SPEED, link_speed);
8ceee660
BH		 1968 /* On B0, MAC backpressure can be disabled and packets get
1969 * discarded. */
55668611 1970 if (falcon_rev(efx) >= FALCON_REV_B0) {
3e6c4538 1971 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
8ceee660
BH		 1972 !efx->link_up);
1973 }
1974
12d00cad 1975 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
8ceee660
BH		 1976
1977 /* Restore the multicast hash registers. */
1978 falcon_set_multicast_hash(efx);
1979
1980 /* Transmission of pause frames when RX crosses the threshold is
1981 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1982 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
04cc8cac 1983 tx_fc = !!(efx->link_fc & EFX_FC_TX);
12d00cad 1984 efx_reado(efx, &reg, FR_AZ_RX_CFG);
3e6c4538 1985 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
8ceee660
BH		 1986
1987 /* Unisolate the MAC -> RX */
55668611 1988 if (falcon_rev(efx) >= FALCON_REV_B0)
3e6c4538 1989 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
12d00cad 1990 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
8ceee660
BH		 1991}
1992
1993int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1994{
1995 efx_oword_t reg;
1996 u32 *dma_done;
1997 int i;
1998
1999 if (disable_dma_stats)
2000 return 0;
2001
2002 /* Statistics fetch will fail if the MAC is in TX drain */
55668611 2003 if (falcon_rev(efx) >= FALCON_REV_B0) {
8ceee660 2004 efx_oword_t temp;
12d00cad 2005 efx_reado(efx, &temp, FR_AB_MAC_CTRL);
3e6c4538 2006 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
8ceee660
BH		 2007 return 0;
2008 }
2009
2010 dma_done = (efx->stats_buffer.addr + done_offset);
2011 *dma_done = FALCON_STATS_NOT_DONE;
2012 wmb(); /* ensure done flag is clear */
2013
2014 /* Initiate DMA transfer of stats */
2015 EFX_POPULATE_OWORD_2(reg,
3e6c4538
BH		 2016 FRF_AB_MAC_STAT_DMA_CMD, 1,
2017 FRF_AB_MAC_STAT_DMA_ADR,
8ceee660 2018 efx->stats_buffer.dma_addr);
12d00cad 2019 efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
8ceee660
BH		 2020
2021 /* Wait for transfer to complete */
2022 for (i = 0; i < 400; i++) {
1d0680fd
BH		 2023 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2024 rmb(); /* Ensure the stats are valid. */
8ceee660 2025 return 0;
1d0680fd 2026 }
8ceee660
BH		 2027 udelay(10);
2028 }
2029
2030 EFX_ERR(efx, "timed out waiting for statistics\n");
2031 return -ETIMEDOUT;
2032}
2033
2034/**************************************************************************
2035 *
2036 * PHY access via GMII
2037 *
2038 **************************************************************************
2039 */
2040
8ceee660
BH		 2041/* Wait for GMII access to complete */
2042static int falcon_gmii_wait(struct efx_nic *efx)
2043{
2044 efx_dword_t md_stat;
2045 int count;
2046
177dfcd8
BH		 2047 /* wait upto 50ms - taken max from datasheet */
2048 for (count = 0; count < 5000; count++) {
12d00cad 2049 efx_readd(efx, &md_stat, FR_AB_MD_STAT);
3e6c4538
BH		 2050 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2051 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2052 EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
8ceee660
BH		 2053 EFX_ERR(efx, "error from GMII access "
2054 EFX_DWORD_FMT"\n",
2055 EFX_DWORD_VAL(md_stat));
2056 return -EIO;
2057 }
2058 return 0;
2059 }
2060 udelay(10);
2061 }
2062 EFX_ERR(efx, "timed out waiting for GMII\n");
2063 return -ETIMEDOUT;
2064}
2065
68e7f45e
BH		 2066/* Write an MDIO register of a PHY connected to Falcon. */
2067static int falcon_mdio_write(struct net_device *net_dev,
2068 int prtad, int devad, u16 addr, u16 value)
8ceee660 2069{
767e468c 2070 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2071 efx_oword_t reg;
68e7f45e 2072 int rc;
8ceee660 2073
68e7f45e
BH		 2074 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2075 prtad, devad, addr, value);
8ceee660
BH		 2076
2077 spin_lock_bh(&efx->phy_lock);
2078
68e7f45e
BH		 2079 /* Check MDIO not currently being accessed */
2080 rc = falcon_gmii_wait(efx);
2081 if (rc)
8ceee660
BH		 2082 goto out;
2083
2084 /* Write the address/ID register */
3e6c4538 2085 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
12d00cad 2086 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
8ceee660 2087
3e6c4538
BH		 2088 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2089 FRF_AB_MD_DEV_ADR, devad);
12d00cad 2090 efx_writeo(efx, &reg, FR_AB_MD_ID);
8ceee660
BH		 2091
2092 /* Write data */
3e6c4538 2093 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
12d00cad 2094 efx_writeo(efx, &reg, FR_AB_MD_TXD);
8ceee660
BH		 2095
2096 EFX_POPULATE_OWORD_2(reg,
3e6c4538
BH		 2097 FRF_AB_MD_WRC, 1,
2098 FRF_AB_MD_GC, 0);
12d00cad 2099 efx_writeo(efx, &reg, FR_AB_MD_CS);
8ceee660
BH		 2100
2101 /* Wait for data to be written */
68e7f45e
BH		 2102 rc = falcon_gmii_wait(efx);
2103 if (rc) {
8ceee660
BH		 2104 /* Abort the write operation */
2105 EFX_POPULATE_OWORD_2(reg,
3e6c4538
BH		 2106 FRF_AB_MD_WRC, 0,
2107 FRF_AB_MD_GC, 1);
12d00cad 2108 efx_writeo(efx, &reg, FR_AB_MD_CS);
8ceee660
BH		 2109 udelay(10);
2110 }
2111
2112 out:
2113 spin_unlock_bh(&efx->phy_lock);
68e7f45e 2114 return rc;
8ceee660
BH		 2115}
2116
68e7f45e
BH		 2117/* Read an MDIO register of a PHY connected to Falcon. */
2118static int falcon_mdio_read(struct net_device *net_dev,
2119 int prtad, int devad, u16 addr)
8ceee660 2120{
767e468c 2121 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660 2122 efx_oword_t reg;
68e7f45e 2123 int rc;
8ceee660
BH		 2124
2125 spin_lock_bh(&efx->phy_lock);
2126
68e7f45e
BH		 2127 /* Check MDIO not currently being accessed */
2128 rc = falcon_gmii_wait(efx);
2129 if (rc)
8ceee660
BH		 2130 goto out;
2131
3e6c4538 2132 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
12d00cad 2133 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
8ceee660 2134
3e6c4538
BH		 2135 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2136 FRF_AB_MD_DEV_ADR, devad);
12d00cad 2137 efx_writeo(efx, &reg, FR_AB_MD_ID);
8ceee660
BH		 2138
2139 /* Request data to be read */
3e6c4538 2140 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
12d00cad 2141 efx_writeo(efx, &reg, FR_AB_MD_CS);
8ceee660
BH		 2142
2143 /* Wait for data to become available */
68e7f45e
BH		 2144 rc = falcon_gmii_wait(efx);
2145 if (rc == 0) {
12d00cad 2146 efx_reado(efx, &reg, FR_AB_MD_RXD);
3e6c4538 2147 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
68e7f45e
BH		 2148 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2149 prtad, devad, addr, rc);
8ceee660
BH		 2150 } else {
2151 /* Abort the read operation */
2152 EFX_POPULATE_OWORD_2(reg,
3e6c4538
BH		 2153 FRF_AB_MD_RIC, 0,
2154 FRF_AB_MD_GC, 1);
12d00cad 2155 efx_writeo(efx, &reg, FR_AB_MD_CS);
8ceee660 2156
68e7f45e
BH		 2157 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2158 prtad, devad, addr, rc);
8ceee660
BH		 2159 }
2160
2161 out:
2162 spin_unlock_bh(&efx->phy_lock);
68e7f45e 2163 return rc;
8ceee660
BH		 2164}
2165
177dfcd8
BH		 2166int falcon_switch_mac(struct efx_nic *efx)
2167{
2168 struct efx_mac_operations *old_mac_op = efx->mac_op;
2169 efx_oword_t nic_stat;
2170 unsigned strap_val;
1974cc20
BH		 2171 int rc = 0;
2172
2173 /* Don't try to fetch MAC stats while we're switching MACs */
2174 efx_stats_disable(efx);
177dfcd8
BH		 2175
2176 /* Internal loopbacks override the phy speed setting */
2177 if (efx->loopback_mode == LOOPBACK_GMAC) {
2178 efx->link_speed = 1000;
2179 efx->link_fd = true;
2180 } else if (LOOPBACK_INTERNAL(efx)) {
2181 efx->link_speed = 10000;
2182 efx->link_fd = true;
2183 }
2184
0cc12838 2185 WARN_ON(!mutex_is_locked(&efx->mac_lock));
177dfcd8
BH		 2186 efx->mac_op = (EFX_IS10G(efx) ?
2187 &falcon_xmac_operations : &falcon_gmac_operations);
177dfcd8 2188
0cc12838
SH		 2189 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2190 * changed, because this function is run post online reset */
12d00cad 2191 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
177dfcd8
BH		 2192 strap_val = EFX_IS10G(efx) ? 5 : 3;
2193 if (falcon_rev(efx) >= FALCON_REV_B0) {
3e6c4538
BH		 2194 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2195 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
12d00cad 2196 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
177dfcd8
BH		 2197 } else {
2198 /* Falcon A1 does not support 1G/10G speed switching
2199 * and must not be used with a PHY that does. */
3e6c4538
BH		 2200 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2201 strap_val);
177dfcd8
BH		 2202 }
2203
0cc12838 2204 if (old_mac_op == efx->mac_op)
1974cc20 2205 goto out;
177dfcd8
BH		 2206
2207 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
0cc12838
SH		 2208 /* Not all macs support a mac-level link state */
2209 efx->mac_up = true;
2210
1974cc20
BH		 2211 rc = falcon_reset_macs(efx);
2212out:
2213 efx_stats_enable(efx);
2214 return rc;
177dfcd8
BH		 2215}
2216
8ceee660
BH		 2217/* This call is responsible for hooking in the MAC and PHY operations */
2218int falcon_probe_port(struct efx_nic *efx)
2219{
2220 int rc;
2221
96c45726
BH		 2222 switch (efx->phy_type) {
2223 case PHY_TYPE_SFX7101:
2224 efx->phy_op = &falcon_sfx7101_phy_ops;
2225 break;
2226 case PHY_TYPE_SFT9001A:
2227 case PHY_TYPE_SFT9001B:
2228 efx->phy_op = &falcon_sft9001_phy_ops;
2229 break;
2230 case PHY_TYPE_QT2022C2:
2231 case PHY_TYPE_QT2025C:
b37b62fe 2232 efx->phy_op = &falcon_qt202x_phy_ops;
96c45726
BH		 2233 break;
2234 default:
2235 EFX_ERR(efx, "Unknown PHY type %d\n",
2236 efx->phy_type);
2237 return -ENODEV;
2238 }
2239
2240 if (efx->phy_op->macs & EFX_XMAC)
2241 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2242 (1 << LOOPBACK_XGXS) |
2243 (1 << LOOPBACK_XAUI));
2244 if (efx->phy_op->macs & EFX_GMAC)
2245 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2246 efx->loopback_modes |= efx->phy_op->loopbacks;
8ceee660 2247
68e7f45e
BH		 2248 /* Set up MDIO structure for PHY */
2249 efx->mdio.mmds = efx->phy_op->mmds;
2250 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2251 efx->mdio.mdio_read = falcon_mdio_read;
2252 efx->mdio.mdio_write = falcon_mdio_write;
8ceee660
BH		 2253
2254 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
55668611 2255 if (falcon_rev(efx) >= FALCON_REV_B0)
04cc8cac 2256 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
8ceee660 2257 else
04cc8cac 2258 efx->wanted_fc = EFX_FC_RX;
8ceee660
BH		 2259
2260 /* Allocate buffer for stats */
2261 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2262 FALCON_MAC_STATS_SIZE);
2263 if (rc)
2264 return rc;
9c8976a1
JSR		 2265 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2266 (u64)efx->stats_buffer.dma_addr,
8ceee660 2267 efx->stats_buffer.addr,
9c8976a1 2268 (u64)virt_to_phys(efx->stats_buffer.addr));
8ceee660
BH		 2269
2270 return 0;
2271}
2272
2273void falcon_remove_port(struct efx_nic *efx)
2274{
2275 falcon_free_buffer(efx, &efx->stats_buffer);
2276}
2277
2278/**************************************************************************
2279 *
2280 * Multicast filtering
2281 *
2282 **************************************************************************
2283 */
2284
2285void falcon_set_multicast_hash(struct efx_nic *efx)
2286{
2287 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2288
2289 /* Broadcast packets go through the multicast hash filter.
2290 * ether_crc_le() of the broadcast address is 0xbe2612ff
2291 * so we always add bit 0xff to the mask.
2292 */
2293 set_bit_le(0xff, mc_hash->byte);
2294
12d00cad
BH		 2295 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2296 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
8ceee660
BH		 2297}
2298
8c8661e4
BH		 2299
2300/**************************************************************************
2301 *
2302 * Falcon test code
2303 *
2304 **************************************************************************/
2305
2306int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2307{
2308 struct falcon_nvconfig *nvconfig;
2309 struct efx_spi_device *spi;
2310 void *region;
2311 int rc, magic_num, struct_ver;
2312 __le16 *word, *limit;
2313 u32 csum;
2314
2f7f5730
BH		 2315 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2316 if (!spi)
2317 return -EINVAL;
2318
0a95f563 2319 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
8c8661e4
BH		 2320 if (!region)
2321 return -ENOMEM;
3e6c4538 2322 nvconfig = region + FALCON_NVCONFIG_OFFSET;
8c8661e4 2323
f4150724 2324 mutex_lock(&efx->spi_lock);
0a95f563 2325 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
f4150724 2326 mutex_unlock(&efx->spi_lock);
8c8661e4
BH		 2327 if (rc) {
2328 EFX_ERR(efx, "Failed to read %s\n",
2329 efx->spi_flash ? "flash" : "EEPROM");
2330 rc = -EIO;
2331 goto out;
2332 }
2333
2334 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2335 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2336
2337 rc = -EINVAL;
3e6c4538 2338 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
8c8661e4
BH		 2339 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2340 goto out;
2341 }
2342 if (struct_ver < 2) {
2343 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2344 goto out;
2345 } else if (struct_ver < 4) {
2346 word = &nvconfig->board_magic_num;
2347 limit = (__le16 *) (nvconfig + 1);
2348 } else {
2349 word = region;
0a95f563 2350 limit = region + FALCON_NVCONFIG_END;
8c8661e4
BH		 2351 }
2352 for (csum = 0; word < limit; ++word)
2353 csum += le16_to_cpu(*word);
2354
2355 if (~csum & 0xffff) {
2356 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2357 goto out;
2358 }
2359
2360 rc = 0;
2361 if (nvconfig_out)
2362 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2363
2364 out:
2365 kfree(region);
2366 return rc;
2367}
2368
2369/* Registers tested in the falcon register test */
2370static struct {
2371 unsigned address;
2372 efx_oword_t mask;
2373} efx_test_registers[] = {
3e6c4538 2374 { FR_AZ_ADR_REGION,
8c8661e4 2375 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
3e6c4538 2376 { FR_AZ_RX_CFG,
8c8661e4 2377 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
3e6c4538 2378 { FR_AZ_TX_CFG,
8c8661e4 2379 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2380 { FR_AZ_TX_RESERVED,
8c8661e4 2381 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
3e6c4538 2382 { FR_AB_MAC_CTRL,
8c8661e4 2383 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2384 { FR_AZ_SRM_TX_DC_CFG,
8c8661e4 2385 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2386 { FR_AZ_RX_DC_CFG,
8c8661e4 2387 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2388 { FR_AZ_RX_DC_PF_WM,
8c8661e4 2389 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2390 { FR_BZ_DP_CTRL,
8c8661e4 2391 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2392 { FR_AB_GM_CFG2,
177dfcd8 2393 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2394 { FR_AB_GMF_CFG0,
177dfcd8 2395 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2396 { FR_AB_XM_GLB_CFG,
8c8661e4 2397 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2398 { FR_AB_XM_TX_CFG,
8c8661e4 2399 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2400 { FR_AB_XM_RX_CFG,
8c8661e4 2401 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2402 { FR_AB_XM_RX_PARAM,
8c8661e4 2403 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2404 { FR_AB_XM_FC,
8c8661e4 2405 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2406 { FR_AB_XM_ADR_LO,
8c8661e4 2407 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
3e6c4538 2408 { FR_AB_XX_SD_CTL,
8c8661e4
BH		 2409 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2410};
2411
2412static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2413 const efx_oword_t *mask)
2414{
2415 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2416 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2417}
2418
2419int falcon_test_registers(struct efx_nic *efx)
2420{
2421 unsigned address = 0, i, j;
2422 efx_oword_t mask, imask, original, reg, buf;
2423
2424 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2425 WARN_ON(!LOOPBACK_INTERNAL(efx));
2426
2427 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2428 address = efx_test_registers[i].address;
2429 mask = imask = efx_test_registers[i].mask;
2430 EFX_INVERT_OWORD(imask);
2431
12d00cad 2432 efx_reado(efx, &original, address);
8c8661e4
BH		 2433
2434 /* bit sweep on and off */
2435 for (j = 0; j < 128; j++) {
2436 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2437 continue;
2438
2439 /* Test this testable bit can be set in isolation */
2440 EFX_AND_OWORD(reg, original, mask);
2441 EFX_SET_OWORD32(reg, j, j, 1);
2442
12d00cad
BH		 2443 efx_writeo(efx, &reg, address);
2444 efx_reado(efx, &buf, address);
8c8661e4
BH		 2445
2446 if (efx_masked_compare_oword(&reg, &buf, &mask))
2447 goto fail;
2448
2449 /* Test this testable bit can be cleared in isolation */
2450 EFX_OR_OWORD(reg, original, mask);
2451 EFX_SET_OWORD32(reg, j, j, 0);
2452
12d00cad
BH		 2453 efx_writeo(efx, &reg, address);
2454 efx_reado(efx, &buf, address);
8c8661e4
BH		 2455
2456 if (efx_masked_compare_oword(&reg, &buf, &mask))
2457 goto fail;
2458 }
2459
12d00cad 2460 efx_writeo(efx, &original, address);
8c8661e4
BH		 2461 }
2462
2463 return 0;
2464
2465fail:
2466 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2467 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2468 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2469 return -EIO;
2470}
2471
8ceee660
BH		 2472/**************************************************************************
2473 *
2474 * Device reset
2475 *
2476 **************************************************************************
2477 */
2478
2479/* Resets NIC to known state. This routine must be called in process
2480 * context and is allowed to sleep. */
2481int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2482{
2483 struct falcon_nic_data *nic_data = efx->nic_data;
2484 efx_oword_t glb_ctl_reg_ker;
2485 int rc;
2486
2487 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2488
2489 /* Initiate device reset */
2490 if (method == RESET_TYPE_WORLD) {
2491 rc = pci_save_state(efx->pci_dev);
2492 if (rc) {
2493 EFX_ERR(efx, "failed to backup PCI state of primary "
2494 "function prior to hardware reset\n");
2495 goto fail1;
2496 }
2497 if (FALCON_IS_DUAL_FUNC(efx)) {
2498 rc = pci_save_state(nic_data->pci_dev2);
2499 if (rc) {
2500 EFX_ERR(efx, "failed to backup PCI state of "
2501 "secondary function prior to "
2502 "hardware reset\n");
2503 goto fail2;
2504 }
2505 }
2506
2507 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
3e6c4538
BH		 2508 FRF_AB_EXT_PHY_RST_DUR,
2509 FFE_AB_EXT_PHY_RST_DUR_10240US,
2510 FRF_AB_SWRST, 1);
8ceee660 2511 } else {
8ceee660 2512 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
3e6c4538
BH		 2513 /* exclude PHY from "invisible" reset */
2514 FRF_AB_EXT_PHY_RST_CTL,
2515 method == RESET_TYPE_INVISIBLE,
2516 /* exclude EEPROM/flash and PCIe */
2517 FRF_AB_PCIE_CORE_RST_CTL, 1,
2518 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2519 FRF_AB_PCIE_SD_RST_CTL, 1,
2520 FRF_AB_EE_RST_CTL, 1,
2521 FRF_AB_EXT_PHY_RST_DUR,
2522 FFE_AB_EXT_PHY_RST_DUR_10240US,
2523 FRF_AB_SWRST, 1);
2524 }
12d00cad 2525 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
8ceee660
BH		 2526
2527 EFX_LOG(efx, "waiting for hardware reset\n");
2528 schedule_timeout_uninterruptible(HZ / 20);
2529
2530 /* Restore PCI configuration if needed */
2531 if (method == RESET_TYPE_WORLD) {
2532 if (FALCON_IS_DUAL_FUNC(efx)) {
2533 rc = pci_restore_state(nic_data->pci_dev2);
2534 if (rc) {
2535 EFX_ERR(efx, "failed to restore PCI config for "
2536 "the secondary function\n");
2537 goto fail3;
2538 }
2539 }
2540 rc = pci_restore_state(efx->pci_dev);
2541 if (rc) {
2542 EFX_ERR(efx, "failed to restore PCI config for the "
2543 "primary function\n");
2544 goto fail4;
2545 }
2546 EFX_LOG(efx, "successfully restored PCI config\n");
2547 }
2548
2549 /* Assert that reset complete */
12d00cad 2550 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
3e6c4538 2551 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
8ceee660
BH		 2552 rc = -ETIMEDOUT;
2553 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2554 goto fail5;
2555 }
2556 EFX_LOG(efx, "hardware reset complete\n");
2557
2558 return 0;
2559
2560 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2561fail2:
2562fail3:
2563 pci_restore_state(efx->pci_dev);
2564fail1:
2565fail4:
2566fail5:
2567 return rc;
2568}
2569
2570/* Zeroes out the SRAM contents. This routine must be called in
2571 * process context and is allowed to sleep.
2572 */
2573static int falcon_reset_sram(struct efx_nic *efx)
2574{
2575 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2576 int count;
2577
2578 /* Set the SRAM wake/sleep GPIO appropriately. */
12d00cad 2579 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
3e6c4538
BH		 2580 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2581 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
12d00cad 2582 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
8ceee660
BH		 2583
2584 /* Initiate SRAM reset */
2585 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
3e6c4538
BH		 2586 FRF_AZ_SRM_INIT_EN, 1,
2587 FRF_AZ_SRM_NB_SZ, 0);
12d00cad 2588 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
8ceee660
BH		 2589
2590 /* Wait for SRAM reset to complete */
2591 count = 0;
2592 do {
2593 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2594
2595 /* SRAM reset is slow; expect around 16ms */
2596 schedule_timeout_uninterruptible(HZ / 50);
2597
2598 /* Check for reset complete */
12d00cad 2599 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
3e6c4538 2600 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
8ceee660
BH		 2601 EFX_LOG(efx, "SRAM reset complete\n");
2602
2603 return 0;
2604 }
2605 } while (++count < 20); /* wait upto 0.4 sec */
2606
2607 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2608 return -ETIMEDOUT;
2609}
2610
4a5b504d
BH		 2611static int falcon_spi_device_init(struct efx_nic *efx,
2612 struct efx_spi_device **spi_device_ret,
2613 unsigned int device_id, u32 device_type)
2614{
2615 struct efx_spi_device *spi_device;
2616
2617 if (device_type != 0) {
0c53d8c8 2618 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
4a5b504d
BH		 2619 if (!spi_device)
2620 return -ENOMEM;
2621 spi_device->device_id = device_id;
2622 spi_device->size =
2623 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2624 spi_device->addr_len =
2625 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2626 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2627 spi_device->addr_len == 1);
f4150724
BH		 2628 spi_device->erase_command =
2629 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2630 spi_device->erase_size =
2631 1 << SPI_DEV_TYPE_FIELD(device_type,
2632 SPI_DEV_TYPE_ERASE_SIZE);
4a5b504d
BH		 2633 spi_device->block_size =
2634 1 << SPI_DEV_TYPE_FIELD(device_type,
2635 SPI_DEV_TYPE_BLOCK_SIZE);
2636
2637 spi_device->efx = efx;
2638 } else {
2639 spi_device = NULL;
2640 }
2641
2642 kfree(*spi_device_ret);
2643 *spi_device_ret = spi_device;
2644 return 0;
2645}
2646
2647
2648static void falcon_remove_spi_devices(struct efx_nic *efx)
2649{
2650 kfree(efx->spi_eeprom);
2651 efx->spi_eeprom = NULL;
2652 kfree(efx->spi_flash);
2653 efx->spi_flash = NULL;
2654}
2655
8ceee660
BH		 2656/* Extract non-volatile configuration */
2657static int falcon_probe_nvconfig(struct efx_nic *efx)
2658{
2659 struct falcon_nvconfig *nvconfig;
8c8661e4 2660 int board_rev;
8ceee660
BH		 2661 int rc;
2662
8ceee660 2663 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
4a5b504d
BH		 2664 if (!nvconfig)
2665 return -ENOMEM;
8ceee660 2666
8c8661e4
BH		 2667 rc = falcon_read_nvram(efx, nvconfig);
2668 if (rc == -EINVAL) {
2669 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
8ceee660 2670 efx->phy_type = PHY_TYPE_NONE;
68e7f45e 2671 efx->mdio.prtad = MDIO_PRTAD_NONE;
8ceee660 2672 board_rev = 0;
8c8661e4
BH		 2673 rc = 0;
2674 } else if (rc) {
2675 goto fail1;
8ceee660
BH		 2676 } else {
2677 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
4a5b504d 2678 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
8ceee660
BH		 2679
2680 efx->phy_type = v2->port0_phy_type;
68e7f45e 2681 efx->mdio.prtad = v2->port0_phy_addr;
8ceee660 2682 board_rev = le16_to_cpu(v2->board_revision);
4a5b504d 2683
8c8661e4 2684 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
3e6c4538
BH		 2685 rc = falcon_spi_device_init(
2686 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2687 le32_to_cpu(v3->spi_device_type
2688 [FFE_AB_SPI_DEVICE_FLASH]));
4a5b504d
BH		 2689 if (rc)
2690 goto fail2;
3e6c4538
BH		 2691 rc = falcon_spi_device_init(
2692 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2693 le32_to_cpu(v3->spi_device_type
2694 [FFE_AB_SPI_DEVICE_EEPROM]));
4a5b504d
BH		 2695 if (rc)
2696 goto fail2;
2697 }
8ceee660
BH		 2698 }
2699
8c8661e4
BH		 2700 /* Read the MAC addresses */
2701 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2702
68e7f45e 2703 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
8ceee660 2704
3473a5b1 2705 falcon_probe_board(efx, board_rev);
8ceee660 2706
4a5b504d
BH		 2707 kfree(nvconfig);
2708 return 0;
2709
2710 fail2:
2711 falcon_remove_spi_devices(efx);
2712 fail1:
8ceee660
BH		 2713 kfree(nvconfig);
2714 return rc;
2715}
2716
2717/* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2718 * count, port speed). Set workaround and feature flags accordingly.
2719 */
2720static int falcon_probe_nic_variant(struct efx_nic *efx)
2721{
2722 efx_oword_t altera_build;
177dfcd8 2723 efx_oword_t nic_stat;
8ceee660 2724
12d00cad 2725 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
3e6c4538 2726 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
8ceee660
BH		 2727 EFX_ERR(efx, "Falcon FPGA not supported\n");
2728 return -ENODEV;
2729 }
2730
12d00cad 2731 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
177dfcd8 2732
55668611 2733 switch (falcon_rev(efx)) {
8ceee660
BH		 2734 case FALCON_REV_A0:
2735 case 0xff:
2736 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2737 return -ENODEV;
2738
177dfcd8 2739 case FALCON_REV_A1:
3e6c4538 2740 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
8ceee660
BH		 2741 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2742 return -ENODEV;
2743 }
8ceee660 2744 break;
8ceee660
BH		 2745
2746 case FALCON_REV_B0:
2747 break;
2748
2749 default:
55668611 2750 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
8ceee660
BH		 2751 return -ENODEV;
2752 }
2753
177dfcd8 2754 /* Initial assumed speed */
3e6c4538 2755 efx->link_speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
177dfcd8 2756
8ceee660
BH		 2757 return 0;
2758}
2759
4a5b504d
BH		 2760/* Probe all SPI devices on the NIC */
2761static void falcon_probe_spi_devices(struct efx_nic *efx)
2762{
2763 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2f7f5730 2764 int boot_dev;
4a5b504d 2765
12d00cad
BH		 2766 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2767 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2768 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
4a5b504d 2769
3e6c4538
BH		 2770 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2771 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2772 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2f7f5730 2773 EFX_LOG(efx, "Booted from %s\n",
3e6c4538 2774 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2f7f5730
BH		 2775 } else {
2776 /* Disable VPD and set clock dividers to safe
2777 * values for initial programming. */
2778 boot_dev = -1;
2779 EFX_LOG(efx, "Booted from internal ASIC settings;"
2780 " setting SPI config\n");
3e6c4538 2781 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2f7f5730 2782 /* 125 MHz / 7 ~= 20 MHz */
3e6c4538 2783 FRF_AB_EE_SF_CLOCK_DIV, 7,
2f7f5730 2784 /* 125 MHz / 63 ~= 2 MHz */
3e6c4538 2785 FRF_AB_EE_EE_CLOCK_DIV, 63);
12d00cad 2786 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
4a5b504d
BH		 2787 }
2788
3e6c4538
BH		 2789 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2790 falcon_spi_device_init(efx, &efx->spi_flash,
2791 FFE_AB_SPI_DEVICE_FLASH,
2f7f5730 2792 default_flash_type);
3e6c4538
BH		 2793 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2794 falcon_spi_device_init(efx, &efx->spi_eeprom,
2795 FFE_AB_SPI_DEVICE_EEPROM,
2f7f5730 2796 large_eeprom_type);
4a5b504d
BH		 2797}
2798
8ceee660
BH		 2799int falcon_probe_nic(struct efx_nic *efx)
2800{
2801 struct falcon_nic_data *nic_data;
2802 int rc;
2803
8ceee660
BH		 2804 /* Allocate storage for hardware specific data */
2805 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
88c59425
BH		 2806 if (!nic_data)
2807 return -ENOMEM;
5daab96d 2808 efx->nic_data = nic_data;
8ceee660
BH		 2809
2810 /* Determine number of ports etc. */
2811 rc = falcon_probe_nic_variant(efx);
2812 if (rc)
2813 goto fail1;
2814
2815 /* Probe secondary function if expected */
2816 if (FALCON_IS_DUAL_FUNC(efx)) {
2817 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2818
2819 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2820 dev))) {
2821 if (dev->bus == efx->pci_dev->bus &&
2822 dev->devfn == efx->pci_dev->devfn + 1) {
2823 nic_data->pci_dev2 = dev;
2824 break;
2825 }
2826 }
2827 if (!nic_data->pci_dev2) {
2828 EFX_ERR(efx, "failed to find secondary function\n");
2829 rc = -ENODEV;
2830 goto fail2;
2831 }
2832 }
2833
2834 /* Now we can reset the NIC */
2835 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2836 if (rc) {
2837 EFX_ERR(efx, "failed to reset NIC\n");
2838 goto fail3;
2839 }
2840
2841 /* Allocate memory for INT_KER */
2842 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2843 if (rc)
2844 goto fail4;
2845 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2846
9c8976a1
JSR		 2847 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2848 (u64)efx->irq_status.dma_addr,
2849 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
8ceee660 2850
4a5b504d
BH		 2851 falcon_probe_spi_devices(efx);
2852
8ceee660
BH		 2853 /* Read in the non-volatile configuration */
2854 rc = falcon_probe_nvconfig(efx);
2855 if (rc)
2856 goto fail5;
2857
37b5a603 2858 /* Initialise I2C adapter */
b4531938 2859 efx->i2c_adap.owner = THIS_MODULE;
37b5a603
BH		 2860 nic_data->i2c_data = falcon_i2c_bit_operations;
2861 nic_data->i2c_data.data = efx;
b4531938 2862 efx->i2c_adap.algo_data = &nic_data->i2c_data;
37b5a603 2863 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
9dadae68 2864 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
37b5a603
BH		 2865 rc = i2c_bit_add_bus(&efx->i2c_adap);
2866 if (rc)
2867 goto fail5;
2868
278c0621
BH		 2869 rc = falcon_board(efx)->init(efx);
2870 if (rc) {
2871 EFX_ERR(efx, "failed to initialise board\n");
2872 goto fail6;
2873 }
2874
8ceee660
BH		 2875 return 0;
2876
278c0621
BH		 2877 fail6:
2878 BUG_ON(i2c_del_adapter(&efx->i2c_adap));
2879 memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap));
8ceee660 2880 fail5:
4a5b504d 2881 falcon_remove_spi_devices(efx);
8ceee660
BH		 2882 falcon_free_buffer(efx, &efx->irq_status);
2883 fail4:
8ceee660
BH		 2884 fail3:
2885 if (nic_data->pci_dev2) {
2886 pci_dev_put(nic_data->pci_dev2);
2887 nic_data->pci_dev2 = NULL;
2888 }
2889 fail2:
8ceee660
BH		 2890 fail1:
2891 kfree(efx->nic_data);
2892 return rc;
2893}
2894
56241ceb
BH		 2895static void falcon_init_rx_cfg(struct efx_nic *efx)
2896{
2897 /* Prior to Siena the RX DMA engine will split each frame at
2898 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2899 * be so large that that never happens. */
2900 const unsigned huge_buf_size = (3 * 4096) >> 5;
2901 /* RX control FIFO thresholds (32 entries) */
2902 const unsigned ctrl_xon_thr = 20;
2903 const unsigned ctrl_xoff_thr = 25;
2904 /* RX data FIFO thresholds (256-byte units; size varies) */
625b4514
BH		 2905 int data_xon_thr = rx_xon_thresh_bytes >> 8;
2906 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
56241ceb
BH		 2907 efx_oword_t reg;
2908
12d00cad 2909 efx_reado(efx, &reg, FR_AZ_RX_CFG);
56241ceb 2910 if (falcon_rev(efx) <= FALCON_REV_A1) {
625b4514
BH		 2911 /* Data FIFO size is 5.5K */
2912 if (data_xon_thr < 0)
2913 data_xon_thr = 512 >> 8;
2914 if (data_xoff_thr < 0)
2915 data_xoff_thr = 2048 >> 8;
3e6c4538
BH		 2916 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2917 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2918 huge_buf_size);
2919 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2920 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2921 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2922 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
56241ceb 2923 } else {
625b4514
BH		 2924 /* Data FIFO size is 80K; register fields moved */
2925 if (data_xon_thr < 0)
2926 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2927 if (data_xoff_thr < 0)
2928 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
3e6c4538
BH		 2929 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2930 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2931 huge_buf_size);
2932 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2933 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2934 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2935 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2936 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
56241ceb 2937 }
12d00cad 2938 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
56241ceb
BH		 2939}
2940
8ceee660
BH		 2941/* This call performs hardware-specific global initialisation, such as
2942 * defining the descriptor cache sizes and number of RSS channels.
2943 * It does not set up any buffers, descriptor rings or event queues.
2944 */
2945int falcon_init_nic(struct efx_nic *efx)
2946{
8ceee660 2947 efx_oword_t temp;
8ceee660
BH		 2948 int rc;
2949
8ceee660 2950 /* Use on-chip SRAM */
12d00cad 2951 efx_reado(efx, &temp, FR_AB_NIC_STAT);
3e6c4538 2952 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
12d00cad 2953 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
8ceee660 2954
6f158d5f
BH		 2955 /* Set the source of the GMAC clock */
2956 if (falcon_rev(efx) == FALCON_REV_B0) {
12d00cad 2957 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
3e6c4538 2958 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
12d00cad 2959 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
6f158d5f
BH		 2960 }
2961
8ceee660
BH		 2962 rc = falcon_reset_sram(efx);
2963 if (rc)
2964 return rc;
2965
2966 /* Set positions of descriptor caches in SRAM. */
3e6c4538 2967 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
12d00cad 2968 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
3e6c4538 2969 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
12d00cad 2970 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
8ceee660
BH		 2971
2972 /* Set TX descriptor cache size. */
2973 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
3e6c4538 2974 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
12d00cad 2975 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
8ceee660
BH		 2976
2977 /* Set RX descriptor cache size. Set low watermark to size-8, as
2978 * this allows most efficient prefetching.
2979 */
2980 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
3e6c4538 2981 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
12d00cad 2982 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
3e6c4538 2983 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
12d00cad 2984 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
8ceee660
BH		 2985
2986 /* Clear the parity enables on the TX data fifos as
2987 * they produce false parity errors because of timing issues
2988 */
2989 if (EFX_WORKAROUND_5129(efx)) {
12d00cad 2990 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
3e6c4538 2991 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
12d00cad 2992 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
8ceee660
BH		 2993 }
2994
2995 /* Enable all the genuinely fatal interrupts. (They are still
2996 * masked by the overall interrupt mask, controlled by
2997 * falcon_interrupts()).
2998 *
2999 * Note: All other fatal interrupts are enabled
3000 */
3001 EFX_POPULATE_OWORD_3(temp,
3e6c4538
BH		 3002 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3003 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3004 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
8ceee660 3005 EFX_INVERT_OWORD(temp);
12d00cad 3006 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
8ceee660 3007
8ceee660 3008 if (EFX_WORKAROUND_7244(efx)) {
12d00cad 3009 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3e6c4538
BH		 3010 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3011 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3012 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3013 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
12d00cad 3014 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
8ceee660 3015 }
8ceee660
BH		 3016
3017 falcon_setup_rss_indir_table(efx);
3018
3e6c4538 3019 /* XXX This is documented only for Falcon A0/A1 */
8ceee660
BH		 3020 /* Setup RX. Wait for descriptor is broken and must
3021 * be disabled. RXDP recovery shouldn't be needed, but is.
3022 */
12d00cad 3023 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3e6c4538
BH		 3024 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3025 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
8ceee660 3026 if (EFX_WORKAROUND_5583(efx))
3e6c4538 3027 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
12d00cad 3028 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
8ceee660
BH		 3029
3030 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3031 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3032 */
12d00cad 3033 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3e6c4538
BH		 3034 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3035 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3036 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3037 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3038 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
8ceee660 3039 /* Enable SW_EV to inherit in char driver - assume harmless here */
3e6c4538 3040 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
8ceee660 3041 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3e6c4538 3042 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
8ceee660 3043 /* Squash TX of packets of 16 bytes or less */
55668611 3044 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3e6c4538 3045 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
12d00cad 3046 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
8ceee660
BH		 3047
3048 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3049 * descriptors (which is bad).
3050 */
12d00cad 3051 efx_reado(efx, &temp, FR_AZ_TX_CFG);
3e6c4538 3052 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
12d00cad 3053 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
8ceee660 3054
56241ceb 3055 falcon_init_rx_cfg(efx);
8ceee660
BH		 3056
3057 /* Set destination of both TX and RX Flush events */
55668611 3058 if (falcon_rev(efx) >= FALCON_REV_B0) {
3e6c4538 3059 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
12d00cad 3060 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
8ceee660
BH		 3061 }
3062
3063 return 0;
3064}
3065
3066void falcon_remove_nic(struct efx_nic *efx)
3067{
3068 struct falcon_nic_data *nic_data = efx->nic_data;
37b5a603
BH		 3069 int rc;
3070
278c0621
BH		 3071 falcon_board(efx)->fini(efx);
3072
8c870379 3073 /* Remove I2C adapter and clear it in preparation for a retry */
37b5a603
BH		 3074 rc = i2c_del_adapter(&efx->i2c_adap);
3075 BUG_ON(rc);
8c870379 3076 memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap));
8ceee660 3077
4a5b504d 3078 falcon_remove_spi_devices(efx);
8ceee660
BH		 3079 falcon_free_buffer(efx, &efx->irq_status);
3080
91ad757c 3081 falcon_reset_hw(efx, RESET_TYPE_ALL);
8ceee660
BH		 3082
3083 /* Release the second function after the reset */
3084 if (nic_data->pci_dev2) {
3085 pci_dev_put(nic_data->pci_dev2);
3086 nic_data->pci_dev2 = NULL;
3087 }
3088
3089 /* Tear down the private nic state */
3090 kfree(efx->nic_data);
3091 efx->nic_data = NULL;
3092}
3093
3094void falcon_update_nic_stats(struct efx_nic *efx)
3095{
3096 efx_oword_t cnt;
3097
12d00cad 3098 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3e6c4538
BH		 3099 efx->n_rx_nodesc_drop_cnt +=
3100 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
8ceee660
BH		 3101}
3102
3103/**************************************************************************
3104 *
3105 * Revision-dependent attributes used by efx.c
3106 *
3107 **************************************************************************
3108 */
3109
3110struct efx_nic_type falcon_a_nic_type = {
8ceee660 3111 .mem_map_size = 0x20000,
3e6c4538
BH		 3112 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3113 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3114 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3115 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3116 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
6d51d307 3117 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
8ceee660
BH		 3118 .rx_buffer_padding = 0x24,
3119 .max_interrupt_mode = EFX_INT_MODE_MSI,
3120 .phys_addr_channels = 4,
3121};
3122
3123struct efx_nic_type falcon_b_nic_type = {
8ceee660
BH		 3124 /* Map everything up to and including the RSS indirection
3125 * table. Don't map MSI-X table, MSI-X PBA since Linux
3126 * requires that they not be mapped. */
3e6c4538
BH		 3127 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3128 FR_BZ_RX_INDIRECTION_TBL_STEP *
3129 FR_BZ_RX_INDIRECTION_TBL_ROWS),
3130 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3131 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3132 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3133 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3134 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
6d51d307 3135 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
8ceee660
BH		 3136 .rx_buffer_padding = 0,
3137 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3138 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3139 * interrupt handler only supports 32
3140 * channels */
3141};
3142
Linux 6.x block layer and io_uring tree(s)