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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 BH |
23 | #include "net_driver.h" |
24 | #include "gmii.h" | |
25 | #include "ethtool.h" | |
26 | #include "tx.h" | |
27 | #include "rx.h" | |
28 | #include "efx.h" | |
29 | #include "mdio_10g.h" | |
30 | #include "falcon.h" | |
8ceee660 BH |
31 | #include "mac.h" |
32 | ||
33 | #define EFX_MAX_MTU (9 * 1024) | |
34 | ||
35 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
36 | * a work item is pushed onto this work queue to retry the allocation later, | |
37 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
38 | * workqueue, there is nothing to be gained in making it per NIC | |
39 | */ | |
40 | static struct workqueue_struct *refill_workqueue; | |
41 | ||
42 | /************************************************************************** | |
43 | * | |
44 | * Configurable values | |
45 | * | |
46 | *************************************************************************/ | |
47 | ||
48 | /* | |
49 | * Enable large receive offload (LRO) aka soft segment reassembly (SSR) | |
50 | * | |
51 | * This sets the default for new devices. It can be controlled later | |
52 | * using ethtool. | |
53 | */ | |
dc8cfa55 | 54 | static int lro = true; |
8ceee660 BH |
55 | module_param(lro, int, 0644); |
56 | MODULE_PARM_DESC(lro, "Large receive offload acceleration"); | |
57 | ||
58 | /* | |
59 | * Use separate channels for TX and RX events | |
60 | * | |
61 | * Set this to 1 to use separate channels for TX and RX. It allows us to | |
62 | * apply a higher level of interrupt moderation to TX events. | |
63 | * | |
64 | * This is forced to 0 for MSI interrupt mode as the interrupt vector | |
65 | * is not written | |
66 | */ | |
dc8cfa55 | 67 | static unsigned int separate_tx_and_rx_channels = true; |
8ceee660 BH |
68 | |
69 | /* This is the weight assigned to each of the (per-channel) virtual | |
70 | * NAPI devices. | |
71 | */ | |
72 | static int napi_weight = 64; | |
73 | ||
74 | /* This is the time (in jiffies) between invocations of the hardware | |
75 | * monitor, which checks for known hardware bugs and resets the | |
76 | * hardware and driver as necessary. | |
77 | */ | |
78 | unsigned int efx_monitor_interval = 1 * HZ; | |
79 | ||
80 | /* This controls whether or not the hardware monitor will trigger a | |
81 | * reset when it detects an error condition. | |
82 | */ | |
dc8cfa55 | 83 | static unsigned int monitor_reset = true; |
8ceee660 BH |
84 | |
85 | /* This controls whether or not the driver will initialise devices | |
86 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
87 | * such devices will be initialised with a random locally-generated | |
88 | * MAC address. This allows for loading the sfc_mtd driver to | |
89 | * reprogram the flash, even if the flash contents (including the MAC | |
90 | * address) have previously been erased. | |
91 | */ | |
92 | static unsigned int allow_bad_hwaddr; | |
93 | ||
94 | /* Initial interrupt moderation settings. They can be modified after | |
95 | * module load with ethtool. | |
96 | * | |
97 | * The default for RX should strike a balance between increasing the | |
98 | * round-trip latency and reducing overhead. | |
99 | */ | |
100 | static unsigned int rx_irq_mod_usec = 60; | |
101 | ||
102 | /* Initial interrupt moderation settings. They can be modified after | |
103 | * module load with ethtool. | |
104 | * | |
105 | * This default is chosen to ensure that a 10G link does not go idle | |
106 | * while a TX queue is stopped after it has become full. A queue is | |
107 | * restarted when it drops below half full. The time this takes (assuming | |
108 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
109 | * 512 / 3 * 1.2 = 205 usec. | |
110 | */ | |
111 | static unsigned int tx_irq_mod_usec = 150; | |
112 | ||
113 | /* This is the first interrupt mode to try out of: | |
114 | * 0 => MSI-X | |
115 | * 1 => MSI | |
116 | * 2 => legacy | |
117 | */ | |
118 | static unsigned int interrupt_mode; | |
119 | ||
120 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
121 | * i.e. the number of CPUs among which we may distribute simultaneous | |
122 | * interrupt handling. | |
123 | * | |
124 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
125 | * The default (0) means to assign an interrupt to each package (level II cache) | |
126 | */ | |
127 | static unsigned int rss_cpus; | |
128 | module_param(rss_cpus, uint, 0444); | |
129 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
130 | ||
131 | /************************************************************************** | |
132 | * | |
133 | * Utility functions and prototypes | |
134 | * | |
135 | *************************************************************************/ | |
136 | static void efx_remove_channel(struct efx_channel *channel); | |
137 | static void efx_remove_port(struct efx_nic *efx); | |
138 | static void efx_fini_napi(struct efx_nic *efx); | |
139 | static void efx_fini_channels(struct efx_nic *efx); | |
140 | ||
141 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
142 | do { \ | |
3c78708f | 143 | if (efx->state == STATE_RUNNING) \ |
8ceee660 BH |
144 | ASSERT_RTNL(); \ |
145 | } while (0) | |
146 | ||
147 | /************************************************************************** | |
148 | * | |
149 | * Event queue processing | |
150 | * | |
151 | *************************************************************************/ | |
152 | ||
153 | /* Process channel's event queue | |
154 | * | |
155 | * This function is responsible for processing the event queue of a | |
156 | * single channel. The caller must guarantee that this function will | |
157 | * never be concurrently called more than once on the same channel, | |
158 | * though different channels may be being processed concurrently. | |
159 | */ | |
4d566063 | 160 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 161 | { |
42cbe2d7 BH |
162 | struct efx_nic *efx = channel->efx; |
163 | int rx_packets; | |
8ceee660 | 164 | |
42cbe2d7 | 165 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 166 | !channel->enabled)) |
42cbe2d7 | 167 | return 0; |
8ceee660 | 168 | |
42cbe2d7 BH |
169 | rx_packets = falcon_process_eventq(channel, rx_quota); |
170 | if (rx_packets == 0) | |
171 | return 0; | |
8ceee660 BH |
172 | |
173 | /* Deliver last RX packet. */ | |
174 | if (channel->rx_pkt) { | |
175 | __efx_rx_packet(channel, channel->rx_pkt, | |
176 | channel->rx_pkt_csummed); | |
177 | channel->rx_pkt = NULL; | |
178 | } | |
179 | ||
180 | efx_flush_lro(channel); | |
181 | efx_rx_strategy(channel); | |
182 | ||
42cbe2d7 | 183 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 184 | |
42cbe2d7 | 185 | return rx_packets; |
8ceee660 BH |
186 | } |
187 | ||
188 | /* Mark channel as finished processing | |
189 | * | |
190 | * Note that since we will not receive further interrupts for this | |
191 | * channel before we finish processing and call the eventq_read_ack() | |
192 | * method, there is no need to use the interrupt hold-off timers. | |
193 | */ | |
194 | static inline void efx_channel_processed(struct efx_channel *channel) | |
195 | { | |
5b9e207c BH |
196 | /* The interrupt handler for this channel may set work_pending |
197 | * as soon as we acknowledge the events we've seen. Make sure | |
198 | * it's cleared before then. */ | |
dc8cfa55 | 199 | channel->work_pending = false; |
5b9e207c BH |
200 | smp_wmb(); |
201 | ||
8ceee660 BH |
202 | falcon_eventq_read_ack(channel); |
203 | } | |
204 | ||
205 | /* NAPI poll handler | |
206 | * | |
207 | * NAPI guarantees serialisation of polls of the same device, which | |
208 | * provides the guarantee required by efx_process_channel(). | |
209 | */ | |
210 | static int efx_poll(struct napi_struct *napi, int budget) | |
211 | { | |
212 | struct efx_channel *channel = | |
213 | container_of(napi, struct efx_channel, napi_str); | |
214 | struct net_device *napi_dev = channel->napi_dev; | |
8ceee660 BH |
215 | int rx_packets; |
216 | ||
217 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
218 | channel->channel, raw_smp_processor_id()); | |
219 | ||
42cbe2d7 | 220 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
221 | |
222 | if (rx_packets < budget) { | |
223 | /* There is no race here; although napi_disable() will | |
224 | * only wait for netif_rx_complete(), this isn't a problem | |
225 | * since efx_channel_processed() will have no effect if | |
226 | * interrupts have already been disabled. | |
227 | */ | |
228 | netif_rx_complete(napi_dev, napi); | |
229 | efx_channel_processed(channel); | |
230 | } | |
231 | ||
232 | return rx_packets; | |
233 | } | |
234 | ||
235 | /* Process the eventq of the specified channel immediately on this CPU | |
236 | * | |
237 | * Disable hardware generated interrupts, wait for any existing | |
238 | * processing to finish, then directly poll (and ack ) the eventq. | |
239 | * Finally reenable NAPI and interrupts. | |
240 | * | |
241 | * Since we are touching interrupts the caller should hold the suspend lock | |
242 | */ | |
243 | void efx_process_channel_now(struct efx_channel *channel) | |
244 | { | |
245 | struct efx_nic *efx = channel->efx; | |
246 | ||
247 | BUG_ON(!channel->used_flags); | |
248 | BUG_ON(!channel->enabled); | |
249 | ||
250 | /* Disable interrupts and wait for ISRs to complete */ | |
251 | falcon_disable_interrupts(efx); | |
252 | if (efx->legacy_irq) | |
253 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 254 | if (channel->irq) |
8ceee660 BH |
255 | synchronize_irq(channel->irq); |
256 | ||
257 | /* Wait for any NAPI processing to complete */ | |
258 | napi_disable(&channel->napi_str); | |
259 | ||
260 | /* Poll the channel */ | |
91ad757c | 261 | efx_process_channel(channel, efx->type->evq_size); |
8ceee660 BH |
262 | |
263 | /* Ack the eventq. This may cause an interrupt to be generated | |
264 | * when they are reenabled */ | |
265 | efx_channel_processed(channel); | |
266 | ||
267 | napi_enable(&channel->napi_str); | |
268 | falcon_enable_interrupts(efx); | |
269 | } | |
270 | ||
271 | /* Create event queue | |
272 | * Event queue memory allocations are done only once. If the channel | |
273 | * is reset, the memory buffer will be reused; this guards against | |
274 | * errors during channel reset and also simplifies interrupt handling. | |
275 | */ | |
276 | static int efx_probe_eventq(struct efx_channel *channel) | |
277 | { | |
278 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
279 | ||
280 | return falcon_probe_eventq(channel); | |
281 | } | |
282 | ||
283 | /* Prepare channel's event queue */ | |
bc3c90a2 | 284 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
285 | { |
286 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
287 | ||
288 | channel->eventq_read_ptr = 0; | |
289 | ||
bc3c90a2 | 290 | falcon_init_eventq(channel); |
8ceee660 BH |
291 | } |
292 | ||
293 | static void efx_fini_eventq(struct efx_channel *channel) | |
294 | { | |
295 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
296 | ||
297 | falcon_fini_eventq(channel); | |
298 | } | |
299 | ||
300 | static void efx_remove_eventq(struct efx_channel *channel) | |
301 | { | |
302 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
303 | ||
304 | falcon_remove_eventq(channel); | |
305 | } | |
306 | ||
307 | /************************************************************************** | |
308 | * | |
309 | * Channel handling | |
310 | * | |
311 | *************************************************************************/ | |
312 | ||
8ceee660 BH |
313 | static int efx_probe_channel(struct efx_channel *channel) |
314 | { | |
315 | struct efx_tx_queue *tx_queue; | |
316 | struct efx_rx_queue *rx_queue; | |
317 | int rc; | |
318 | ||
319 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
320 | ||
321 | rc = efx_probe_eventq(channel); | |
322 | if (rc) | |
323 | goto fail1; | |
324 | ||
325 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
326 | rc = efx_probe_tx_queue(tx_queue); | |
327 | if (rc) | |
328 | goto fail2; | |
329 | } | |
330 | ||
331 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
332 | rc = efx_probe_rx_queue(rx_queue); | |
333 | if (rc) | |
334 | goto fail3; | |
335 | } | |
336 | ||
337 | channel->n_rx_frm_trunc = 0; | |
338 | ||
339 | return 0; | |
340 | ||
341 | fail3: | |
342 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
343 | efx_remove_rx_queue(rx_queue); | |
344 | fail2: | |
345 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
346 | efx_remove_tx_queue(tx_queue); | |
347 | fail1: | |
348 | return rc; | |
349 | } | |
350 | ||
351 | ||
352 | /* Channels are shutdown and reinitialised whilst the NIC is running | |
353 | * to propagate configuration changes (mtu, checksum offload), or | |
354 | * to clear hardware error conditions | |
355 | */ | |
bc3c90a2 | 356 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
357 | { |
358 | struct efx_tx_queue *tx_queue; | |
359 | struct efx_rx_queue *rx_queue; | |
360 | struct efx_channel *channel; | |
8ceee660 | 361 | |
f7f13b0b BH |
362 | /* Calculate the rx buffer allocation parameters required to |
363 | * support the current MTU, including padding for header | |
364 | * alignment and overruns. | |
365 | */ | |
366 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
367 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
368 | efx->type->rx_buffer_padding); | |
369 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
370 | |
371 | /* Initialise the channels */ | |
372 | efx_for_each_channel(channel, efx) { | |
373 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
374 | ||
bc3c90a2 | 375 | efx_init_eventq(channel); |
8ceee660 | 376 | |
bc3c90a2 BH |
377 | efx_for_each_channel_tx_queue(tx_queue, channel) |
378 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
379 | |
380 | /* The rx buffer allocation strategy is MTU dependent */ | |
381 | efx_rx_strategy(channel); | |
382 | ||
bc3c90a2 BH |
383 | efx_for_each_channel_rx_queue(rx_queue, channel) |
384 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
385 | |
386 | WARN_ON(channel->rx_pkt != NULL); | |
387 | efx_rx_strategy(channel); | |
388 | } | |
8ceee660 BH |
389 | } |
390 | ||
391 | /* This enables event queue processing and packet transmission. | |
392 | * | |
393 | * Note that this function is not allowed to fail, since that would | |
394 | * introduce too much complexity into the suspend/resume path. | |
395 | */ | |
396 | static void efx_start_channel(struct efx_channel *channel) | |
397 | { | |
398 | struct efx_rx_queue *rx_queue; | |
399 | ||
400 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
401 | ||
402 | if (!(channel->efx->net_dev->flags & IFF_UP)) | |
403 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
404 | efx_poll, napi_weight); | |
405 | ||
5b9e207c BH |
406 | /* The interrupt handler for this channel may set work_pending |
407 | * as soon as we enable it. Make sure it's cleared before | |
408 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
409 | channel->work_pending = false; |
410 | channel->enabled = true; | |
5b9e207c | 411 | smp_wmb(); |
8ceee660 BH |
412 | |
413 | napi_enable(&channel->napi_str); | |
414 | ||
415 | /* Load up RX descriptors */ | |
416 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
417 | efx_fast_push_rx_descriptors(rx_queue); | |
418 | } | |
419 | ||
420 | /* This disables event queue processing and packet transmission. | |
421 | * This function does not guarantee that all queue processing | |
422 | * (e.g. RX refill) is complete. | |
423 | */ | |
424 | static void efx_stop_channel(struct efx_channel *channel) | |
425 | { | |
426 | struct efx_rx_queue *rx_queue; | |
427 | ||
428 | if (!channel->enabled) | |
429 | return; | |
430 | ||
431 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
432 | ||
dc8cfa55 | 433 | channel->enabled = false; |
8ceee660 BH |
434 | napi_disable(&channel->napi_str); |
435 | ||
436 | /* Ensure that any worker threads have exited or will be no-ops */ | |
437 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
438 | spin_lock_bh(&rx_queue->add_lock); | |
439 | spin_unlock_bh(&rx_queue->add_lock); | |
440 | } | |
441 | } | |
442 | ||
443 | static void efx_fini_channels(struct efx_nic *efx) | |
444 | { | |
445 | struct efx_channel *channel; | |
446 | struct efx_tx_queue *tx_queue; | |
447 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 448 | int rc; |
8ceee660 BH |
449 | |
450 | EFX_ASSERT_RESET_SERIALISED(efx); | |
451 | BUG_ON(efx->port_enabled); | |
452 | ||
6bc5d3a9 BH |
453 | rc = falcon_flush_queues(efx); |
454 | if (rc) | |
455 | EFX_ERR(efx, "failed to flush queues\n"); | |
456 | else | |
457 | EFX_LOG(efx, "successfully flushed all queues\n"); | |
458 | ||
8ceee660 BH |
459 | efx_for_each_channel(channel, efx) { |
460 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
461 | ||
462 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
463 | efx_fini_rx_queue(rx_queue); | |
464 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
465 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
466 | efx_fini_eventq(channel); |
467 | } | |
468 | } | |
469 | ||
470 | static void efx_remove_channel(struct efx_channel *channel) | |
471 | { | |
472 | struct efx_tx_queue *tx_queue; | |
473 | struct efx_rx_queue *rx_queue; | |
474 | ||
475 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
476 | ||
477 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
478 | efx_remove_rx_queue(rx_queue); | |
479 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
480 | efx_remove_tx_queue(tx_queue); | |
481 | efx_remove_eventq(channel); | |
482 | ||
483 | channel->used_flags = 0; | |
484 | } | |
485 | ||
486 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
487 | { | |
488 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
489 | } | |
490 | ||
491 | /************************************************************************** | |
492 | * | |
493 | * Port handling | |
494 | * | |
495 | **************************************************************************/ | |
496 | ||
497 | /* This ensures that the kernel is kept informed (via | |
498 | * netif_carrier_on/off) of the link status, and also maintains the | |
499 | * link status's stop on the port's TX queue. | |
500 | */ | |
501 | static void efx_link_status_changed(struct efx_nic *efx) | |
502 | { | |
8ceee660 BH |
503 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
504 | * that no events are triggered between unregister_netdev() and the | |
505 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
506 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
507 | if (!netif_running(efx->net_dev)) | |
508 | return; | |
509 | ||
8c8661e4 BH |
510 | if (efx->port_inhibited) { |
511 | netif_carrier_off(efx->net_dev); | |
512 | return; | |
513 | } | |
514 | ||
dc8cfa55 | 515 | if (efx->link_up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
516 | efx->n_link_state_changes++; |
517 | ||
518 | if (efx->link_up) | |
519 | netif_carrier_on(efx->net_dev); | |
520 | else | |
521 | netif_carrier_off(efx->net_dev); | |
522 | } | |
523 | ||
524 | /* Status message for kernel log */ | |
525 | if (efx->link_up) { | |
526 | struct mii_if_info *gmii = &efx->mii; | |
527 | unsigned adv, lpa; | |
528 | /* NONE here means direct XAUI from the controller, with no | |
529 | * MDIO-attached device we can query. */ | |
530 | if (efx->phy_type != PHY_TYPE_NONE) { | |
531 | adv = gmii_advertised(gmii); | |
532 | lpa = gmii_lpa(gmii); | |
533 | } else { | |
534 | lpa = GM_LPA_10000 | LPA_DUPLEX; | |
535 | adv = lpa; | |
536 | } | |
537 | EFX_INFO(efx, "link up at %dMbps %s-duplex " | |
538 | "(adv %04x lpa %04x) (MTU %d)%s\n", | |
539 | (efx->link_options & GM_LPA_10000 ? 10000 : | |
540 | (efx->link_options & GM_LPA_1000 ? 1000 : | |
541 | (efx->link_options & GM_LPA_100 ? 100 : | |
542 | 10))), | |
543 | (efx->link_options & GM_LPA_DUPLEX ? | |
544 | "full" : "half"), | |
545 | adv, lpa, | |
546 | efx->net_dev->mtu, | |
547 | (efx->promiscuous ? " [PROMISC]" : "")); | |
548 | } else { | |
549 | EFX_INFO(efx, "link down\n"); | |
550 | } | |
551 | ||
552 | } | |
553 | ||
554 | /* This call reinitialises the MAC to pick up new PHY settings. The | |
555 | * caller must hold the mac_lock */ | |
8c8661e4 | 556 | void __efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 BH |
557 | { |
558 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
559 | ||
560 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
561 | raw_smp_processor_id()); | |
562 | ||
a816f75a BH |
563 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
564 | if (efx_dev_registered(efx)) { | |
565 | netif_addr_lock_bh(efx->net_dev); | |
566 | netif_addr_unlock_bh(efx->net_dev); | |
567 | } | |
568 | ||
8ceee660 BH |
569 | falcon_reconfigure_xmac(efx); |
570 | ||
571 | /* Inform kernel of loss/gain of carrier */ | |
572 | efx_link_status_changed(efx); | |
573 | } | |
574 | ||
575 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
576 | * disabled. */ | |
577 | void efx_reconfigure_port(struct efx_nic *efx) | |
578 | { | |
579 | EFX_ASSERT_RESET_SERIALISED(efx); | |
580 | ||
581 | mutex_lock(&efx->mac_lock); | |
582 | __efx_reconfigure_port(efx); | |
583 | mutex_unlock(&efx->mac_lock); | |
584 | } | |
585 | ||
586 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
587 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
588 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
589 | static void efx_reconfigure_work(struct work_struct *data) | |
590 | { | |
591 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
592 | reconfigure_work); | |
593 | ||
594 | mutex_lock(&efx->mac_lock); | |
595 | if (efx->port_enabled) | |
596 | __efx_reconfigure_port(efx); | |
597 | mutex_unlock(&efx->mac_lock); | |
598 | } | |
599 | ||
600 | static int efx_probe_port(struct efx_nic *efx) | |
601 | { | |
602 | int rc; | |
603 | ||
604 | EFX_LOG(efx, "create port\n"); | |
605 | ||
606 | /* Connect up MAC/PHY operations table and read MAC address */ | |
607 | rc = falcon_probe_port(efx); | |
608 | if (rc) | |
609 | goto err; | |
610 | ||
611 | /* Sanity check MAC address */ | |
612 | if (is_valid_ether_addr(efx->mac_address)) { | |
613 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
614 | } else { | |
e174961c JB |
615 | EFX_ERR(efx, "invalid MAC address %pM\n", |
616 | efx->mac_address); | |
8ceee660 BH |
617 | if (!allow_bad_hwaddr) { |
618 | rc = -EINVAL; | |
619 | goto err; | |
620 | } | |
621 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
622 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
623 | efx->net_dev->dev_addr); | |
8ceee660 BH |
624 | } |
625 | ||
626 | return 0; | |
627 | ||
628 | err: | |
629 | efx_remove_port(efx); | |
630 | return rc; | |
631 | } | |
632 | ||
633 | static int efx_init_port(struct efx_nic *efx) | |
634 | { | |
635 | int rc; | |
636 | ||
637 | EFX_LOG(efx, "init port\n"); | |
638 | ||
639 | /* Initialise the MAC and PHY */ | |
640 | rc = falcon_init_xmac(efx); | |
641 | if (rc) | |
642 | return rc; | |
643 | ||
dc8cfa55 | 644 | efx->port_initialized = true; |
8c8661e4 | 645 | efx->stats_enabled = true; |
8ceee660 BH |
646 | |
647 | /* Reconfigure port to program MAC registers */ | |
648 | falcon_reconfigure_xmac(efx); | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
653 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
654 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
655 | * efx_reconfigure_port() may have been cancelled */ | |
656 | static void efx_start_port(struct efx_nic *efx) | |
657 | { | |
658 | EFX_LOG(efx, "start port\n"); | |
659 | BUG_ON(efx->port_enabled); | |
660 | ||
661 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 662 | efx->port_enabled = true; |
8ceee660 BH |
663 | __efx_reconfigure_port(efx); |
664 | mutex_unlock(&efx->mac_lock); | |
665 | } | |
666 | ||
667 | /* Prevent efx_reconfigure_work and efx_monitor() from executing, and | |
668 | * efx_set_multicast_list() from scheduling efx_reconfigure_work. | |
669 | * efx_reconfigure_work can still be scheduled via NAPI processing | |
670 | * until efx_flush_all() is called */ | |
671 | static void efx_stop_port(struct efx_nic *efx) | |
672 | { | |
673 | EFX_LOG(efx, "stop port\n"); | |
674 | ||
675 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 676 | efx->port_enabled = false; |
8ceee660 BH |
677 | mutex_unlock(&efx->mac_lock); |
678 | ||
679 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 680 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
681 | netif_addr_lock_bh(efx->net_dev); |
682 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
683 | } |
684 | } | |
685 | ||
686 | static void efx_fini_port(struct efx_nic *efx) | |
687 | { | |
688 | EFX_LOG(efx, "shut down port\n"); | |
689 | ||
690 | if (!efx->port_initialized) | |
691 | return; | |
692 | ||
693 | falcon_fini_xmac(efx); | |
dc8cfa55 | 694 | efx->port_initialized = false; |
8ceee660 | 695 | |
dc8cfa55 | 696 | efx->link_up = false; |
8ceee660 BH |
697 | efx_link_status_changed(efx); |
698 | } | |
699 | ||
700 | static void efx_remove_port(struct efx_nic *efx) | |
701 | { | |
702 | EFX_LOG(efx, "destroying port\n"); | |
703 | ||
704 | falcon_remove_port(efx); | |
705 | } | |
706 | ||
707 | /************************************************************************** | |
708 | * | |
709 | * NIC handling | |
710 | * | |
711 | **************************************************************************/ | |
712 | ||
713 | /* This configures the PCI device to enable I/O and DMA. */ | |
714 | static int efx_init_io(struct efx_nic *efx) | |
715 | { | |
716 | struct pci_dev *pci_dev = efx->pci_dev; | |
717 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
718 | int rc; | |
719 | ||
720 | EFX_LOG(efx, "initialising I/O\n"); | |
721 | ||
722 | rc = pci_enable_device(pci_dev); | |
723 | if (rc) { | |
724 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
725 | goto fail1; | |
726 | } | |
727 | ||
728 | pci_set_master(pci_dev); | |
729 | ||
730 | /* Set the PCI DMA mask. Try all possibilities from our | |
731 | * genuine mask down to 32 bits, because some architectures | |
732 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
733 | * masks event though they reject 46 bit masks. | |
734 | */ | |
735 | while (dma_mask > 0x7fffffffUL) { | |
736 | if (pci_dma_supported(pci_dev, dma_mask) && | |
737 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
738 | break; | |
739 | dma_mask >>= 1; | |
740 | } | |
741 | if (rc) { | |
742 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
743 | goto fail2; | |
744 | } | |
745 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
746 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
747 | if (rc) { | |
748 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
749 | * fail with a mask that pci_set_dma_mask() accepted, | |
750 | * but just in case... | |
751 | */ | |
752 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
753 | goto fail2; | |
754 | } | |
755 | ||
756 | efx->membase_phys = pci_resource_start(efx->pci_dev, | |
757 | efx->type->mem_bar); | |
758 | rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc"); | |
759 | if (rc) { | |
760 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
761 | rc = -EIO; | |
762 | goto fail3; | |
763 | } | |
764 | efx->membase = ioremap_nocache(efx->membase_phys, | |
765 | efx->type->mem_map_size); | |
766 | if (!efx->membase) { | |
086ea356 BH |
767 | EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n", |
768 | efx->type->mem_bar, | |
769 | (unsigned long long)efx->membase_phys, | |
8ceee660 BH |
770 | efx->type->mem_map_size); |
771 | rc = -ENOMEM; | |
772 | goto fail4; | |
773 | } | |
086ea356 BH |
774 | EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n", |
775 | efx->type->mem_bar, (unsigned long long)efx->membase_phys, | |
776 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
777 | |
778 | return 0; | |
779 | ||
780 | fail4: | |
e1074a0d | 781 | pci_release_region(efx->pci_dev, efx->type->mem_bar); |
8ceee660 | 782 | fail3: |
2c118e0f | 783 | efx->membase_phys = 0; |
8ceee660 BH |
784 | fail2: |
785 | pci_disable_device(efx->pci_dev); | |
786 | fail1: | |
787 | return rc; | |
788 | } | |
789 | ||
790 | static void efx_fini_io(struct efx_nic *efx) | |
791 | { | |
792 | EFX_LOG(efx, "shutting down I/O\n"); | |
793 | ||
794 | if (efx->membase) { | |
795 | iounmap(efx->membase); | |
796 | efx->membase = NULL; | |
797 | } | |
798 | ||
799 | if (efx->membase_phys) { | |
800 | pci_release_region(efx->pci_dev, efx->type->mem_bar); | |
2c118e0f | 801 | efx->membase_phys = 0; |
8ceee660 BH |
802 | } |
803 | ||
804 | pci_disable_device(efx->pci_dev); | |
805 | } | |
806 | ||
46123d04 BH |
807 | /* Get number of RX queues wanted. Return number of online CPU |
808 | * packages in the expectation that an IRQ balancer will spread | |
809 | * interrupts across them. */ | |
810 | static int efx_wanted_rx_queues(void) | |
811 | { | |
812 | cpumask_t core_mask; | |
813 | int count; | |
814 | int cpu; | |
815 | ||
816 | cpus_clear(core_mask); | |
817 | count = 0; | |
818 | for_each_online_cpu(cpu) { | |
819 | if (!cpu_isset(cpu, core_mask)) { | |
820 | ++count; | |
821 | cpus_or(core_mask, core_mask, | |
822 | topology_core_siblings(cpu)); | |
823 | } | |
824 | } | |
825 | ||
826 | return count; | |
827 | } | |
828 | ||
829 | /* Probe the number and type of interrupts we are able to obtain, and | |
830 | * the resulting numbers of channels and RX queues. | |
831 | */ | |
8ceee660 BH |
832 | static void efx_probe_interrupts(struct efx_nic *efx) |
833 | { | |
46123d04 BH |
834 | int max_channels = |
835 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
836 | int rc, i; |
837 | ||
838 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
839 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
840 | int wanted_ints; | |
aa6ef27e | 841 | |
46123d04 BH |
842 | /* We want one RX queue and interrupt per CPU package |
843 | * (or as specified by the rss_cpus module parameter). | |
844 | * We will need one channel per interrupt. | |
845 | */ | |
846 | wanted_ints = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); | |
8831da7b | 847 | efx->n_rx_queues = min(wanted_ints, max_channels); |
8ceee660 | 848 | |
8831da7b | 849 | for (i = 0; i < efx->n_rx_queues; i++) |
8ceee660 | 850 | xentries[i].entry = i; |
8831da7b | 851 | rc = pci_enable_msix(efx->pci_dev, xentries, efx->n_rx_queues); |
8ceee660 | 852 | if (rc > 0) { |
8831da7b BH |
853 | EFX_BUG_ON_PARANOID(rc >= efx->n_rx_queues); |
854 | efx->n_rx_queues = rc; | |
8ceee660 | 855 | rc = pci_enable_msix(efx->pci_dev, xentries, |
8831da7b | 856 | efx->n_rx_queues); |
8ceee660 BH |
857 | } |
858 | ||
859 | if (rc == 0) { | |
8831da7b | 860 | for (i = 0; i < efx->n_rx_queues; i++) |
8ceee660 | 861 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
862 | } else { |
863 | /* Fall back to single channel MSI */ | |
864 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
865 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
866 | } | |
867 | } | |
868 | ||
869 | /* Try single interrupt MSI */ | |
870 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 871 | efx->n_rx_queues = 1; |
8ceee660 BH |
872 | rc = pci_enable_msi(efx->pci_dev); |
873 | if (rc == 0) { | |
874 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
875 | } else { |
876 | EFX_ERR(efx, "could not enable MSI\n"); | |
877 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
878 | } | |
879 | } | |
880 | ||
881 | /* Assume legacy interrupts */ | |
882 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 883 | efx->n_rx_queues = 1; |
8ceee660 BH |
884 | efx->legacy_irq = efx->pci_dev->irq; |
885 | } | |
886 | } | |
887 | ||
888 | static void efx_remove_interrupts(struct efx_nic *efx) | |
889 | { | |
890 | struct efx_channel *channel; | |
891 | ||
892 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 893 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
894 | channel->irq = 0; |
895 | pci_disable_msi(efx->pci_dev); | |
896 | pci_disable_msix(efx->pci_dev); | |
897 | ||
898 | /* Remove legacy interrupt */ | |
899 | efx->legacy_irq = 0; | |
900 | } | |
901 | ||
8831da7b | 902 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
903 | { |
904 | struct efx_tx_queue *tx_queue; | |
905 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 906 | |
60ac1065 BH |
907 | efx_for_each_tx_queue(tx_queue, efx) { |
908 | if (!EFX_INT_MODE_USE_MSI(efx) && separate_tx_and_rx_channels) | |
909 | tx_queue->channel = &efx->channel[1]; | |
910 | else | |
911 | tx_queue->channel = &efx->channel[0]; | |
912 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
913 | } | |
8ceee660 | 914 | |
8831da7b BH |
915 | efx_for_each_rx_queue(rx_queue, efx) { |
916 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
917 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
918 | } |
919 | } | |
920 | ||
921 | static int efx_probe_nic(struct efx_nic *efx) | |
922 | { | |
923 | int rc; | |
924 | ||
925 | EFX_LOG(efx, "creating NIC\n"); | |
926 | ||
927 | /* Carry out hardware-type specific initialisation */ | |
928 | rc = falcon_probe_nic(efx); | |
929 | if (rc) | |
930 | return rc; | |
931 | ||
932 | /* Determine the number of channels and RX queues by trying to hook | |
933 | * in MSI-X interrupts. */ | |
934 | efx_probe_interrupts(efx); | |
935 | ||
8831da7b | 936 | efx_set_channels(efx); |
8ceee660 BH |
937 | |
938 | /* Initialise the interrupt moderation settings */ | |
939 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec); | |
940 | ||
941 | return 0; | |
942 | } | |
943 | ||
944 | static void efx_remove_nic(struct efx_nic *efx) | |
945 | { | |
946 | EFX_LOG(efx, "destroying NIC\n"); | |
947 | ||
948 | efx_remove_interrupts(efx); | |
949 | falcon_remove_nic(efx); | |
950 | } | |
951 | ||
952 | /************************************************************************** | |
953 | * | |
954 | * NIC startup/shutdown | |
955 | * | |
956 | *************************************************************************/ | |
957 | ||
958 | static int efx_probe_all(struct efx_nic *efx) | |
959 | { | |
960 | struct efx_channel *channel; | |
961 | int rc; | |
962 | ||
963 | /* Create NIC */ | |
964 | rc = efx_probe_nic(efx); | |
965 | if (rc) { | |
966 | EFX_ERR(efx, "failed to create NIC\n"); | |
967 | goto fail1; | |
968 | } | |
969 | ||
970 | /* Create port */ | |
971 | rc = efx_probe_port(efx); | |
972 | if (rc) { | |
973 | EFX_ERR(efx, "failed to create port\n"); | |
974 | goto fail2; | |
975 | } | |
976 | ||
977 | /* Create channels */ | |
978 | efx_for_each_channel(channel, efx) { | |
979 | rc = efx_probe_channel(channel); | |
980 | if (rc) { | |
981 | EFX_ERR(efx, "failed to create channel %d\n", | |
982 | channel->channel); | |
983 | goto fail3; | |
984 | } | |
985 | } | |
986 | ||
987 | return 0; | |
988 | ||
989 | fail3: | |
990 | efx_for_each_channel(channel, efx) | |
991 | efx_remove_channel(channel); | |
992 | efx_remove_port(efx); | |
993 | fail2: | |
994 | efx_remove_nic(efx); | |
995 | fail1: | |
996 | return rc; | |
997 | } | |
998 | ||
999 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1000 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1001 | * and ensures that the port is scheduled to be reconfigured. | |
1002 | * This function is safe to call multiple times when the NIC is in any | |
1003 | * state. */ | |
1004 | static void efx_start_all(struct efx_nic *efx) | |
1005 | { | |
1006 | struct efx_channel *channel; | |
1007 | ||
1008 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1009 | ||
1010 | /* Check that it is appropriate to restart the interface. All | |
1011 | * of these flags are safe to read under just the rtnl lock */ | |
1012 | if (efx->port_enabled) | |
1013 | return; | |
1014 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1015 | return; | |
55668611 | 1016 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1017 | return; |
1018 | ||
1019 | /* Mark the port as enabled so port reconfigurations can start, then | |
1020 | * restart the transmit interface early so the watchdog timer stops */ | |
1021 | efx_start_port(efx); | |
dacccc74 SH |
1022 | if (efx_dev_registered(efx)) |
1023 | efx_wake_queue(efx); | |
8ceee660 BH |
1024 | |
1025 | efx_for_each_channel(channel, efx) | |
1026 | efx_start_channel(channel); | |
1027 | ||
1028 | falcon_enable_interrupts(efx); | |
1029 | ||
1030 | /* Start hardware monitor if we're in RUNNING */ | |
1031 | if (efx->state == STATE_RUNNING) | |
1032 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1033 | efx_monitor_interval); | |
1034 | } | |
1035 | ||
1036 | /* Flush all delayed work. Should only be called when no more delayed work | |
1037 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1038 | * since we're holding the rtnl_lock at this point. */ | |
1039 | static void efx_flush_all(struct efx_nic *efx) | |
1040 | { | |
1041 | struct efx_rx_queue *rx_queue; | |
1042 | ||
1043 | /* Make sure the hardware monitor is stopped */ | |
1044 | cancel_delayed_work_sync(&efx->monitor_work); | |
1045 | ||
1046 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1047 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1048 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1049 | |
1050 | /* Stop scheduled port reconfigurations */ | |
1051 | cancel_work_sync(&efx->reconfigure_work); | |
1052 | ||
1053 | } | |
1054 | ||
1055 | /* Quiesce hardware and software without bringing the link down. | |
1056 | * Safe to call multiple times, when the nic and interface is in any | |
1057 | * state. The caller is guaranteed to subsequently be in a position | |
1058 | * to modify any hardware and software state they see fit without | |
1059 | * taking locks. */ | |
1060 | static void efx_stop_all(struct efx_nic *efx) | |
1061 | { | |
1062 | struct efx_channel *channel; | |
1063 | ||
1064 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1065 | ||
1066 | /* port_enabled can be read safely under the rtnl lock */ | |
1067 | if (!efx->port_enabled) | |
1068 | return; | |
1069 | ||
1070 | /* Disable interrupts and wait for ISR to complete */ | |
1071 | falcon_disable_interrupts(efx); | |
1072 | if (efx->legacy_irq) | |
1073 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1074 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1075 | if (channel->irq) |
1076 | synchronize_irq(channel->irq); | |
b3475645 | 1077 | } |
8ceee660 BH |
1078 | |
1079 | /* Stop all NAPI processing and synchronous rx refills */ | |
1080 | efx_for_each_channel(channel, efx) | |
1081 | efx_stop_channel(channel); | |
1082 | ||
1083 | /* Stop all asynchronous port reconfigurations. Since all | |
1084 | * event processing has already been stopped, there is no | |
1085 | * window to loose phy events */ | |
1086 | efx_stop_port(efx); | |
1087 | ||
1088 | /* Flush reconfigure_work, refill_workqueue, monitor_work */ | |
1089 | efx_flush_all(efx); | |
1090 | ||
1091 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1092 | * flushes will complete in a timely fashion. */ | |
8ceee660 BH |
1093 | falcon_drain_tx_fifo(efx); |
1094 | ||
1095 | /* Stop the kernel transmit interface late, so the watchdog | |
1096 | * timer isn't ticking over the flush */ | |
55668611 | 1097 | if (efx_dev_registered(efx)) { |
dacccc74 | 1098 | efx_stop_queue(efx); |
8ceee660 BH |
1099 | netif_tx_lock_bh(efx->net_dev); |
1100 | netif_tx_unlock_bh(efx->net_dev); | |
1101 | } | |
1102 | } | |
1103 | ||
1104 | static void efx_remove_all(struct efx_nic *efx) | |
1105 | { | |
1106 | struct efx_channel *channel; | |
1107 | ||
1108 | efx_for_each_channel(channel, efx) | |
1109 | efx_remove_channel(channel); | |
1110 | efx_remove_port(efx); | |
1111 | efx_remove_nic(efx); | |
1112 | } | |
1113 | ||
1114 | /* A convinience function to safely flush all the queues */ | |
bc3c90a2 | 1115 | void efx_flush_queues(struct efx_nic *efx) |
8ceee660 | 1116 | { |
8ceee660 BH |
1117 | EFX_ASSERT_RESET_SERIALISED(efx); |
1118 | ||
1119 | efx_stop_all(efx); | |
1120 | ||
1121 | efx_fini_channels(efx); | |
bc3c90a2 | 1122 | efx_init_channels(efx); |
8ceee660 BH |
1123 | |
1124 | efx_start_all(efx); | |
8ceee660 BH |
1125 | } |
1126 | ||
1127 | /************************************************************************** | |
1128 | * | |
1129 | * Interrupt moderation | |
1130 | * | |
1131 | **************************************************************************/ | |
1132 | ||
1133 | /* Set interrupt moderation parameters */ | |
1134 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs) | |
1135 | { | |
1136 | struct efx_tx_queue *tx_queue; | |
1137 | struct efx_rx_queue *rx_queue; | |
1138 | ||
1139 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1140 | ||
1141 | efx_for_each_tx_queue(tx_queue, efx) | |
1142 | tx_queue->channel->irq_moderation = tx_usecs; | |
1143 | ||
1144 | efx_for_each_rx_queue(rx_queue, efx) | |
1145 | rx_queue->channel->irq_moderation = rx_usecs; | |
1146 | } | |
1147 | ||
1148 | /************************************************************************** | |
1149 | * | |
1150 | * Hardware monitor | |
1151 | * | |
1152 | **************************************************************************/ | |
1153 | ||
1154 | /* Run periodically off the general workqueue. Serialised against | |
1155 | * efx_reconfigure_port via the mac_lock */ | |
1156 | static void efx_monitor(struct work_struct *data) | |
1157 | { | |
1158 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1159 | monitor_work.work); | |
1160 | int rc = 0; | |
1161 | ||
1162 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1163 | raw_smp_processor_id()); | |
1164 | ||
1165 | ||
1166 | /* If the mac_lock is already held then it is likely a port | |
1167 | * reconfiguration is already in place, which will likely do | |
1168 | * most of the work of check_hw() anyway. */ | |
1169 | if (!mutex_trylock(&efx->mac_lock)) { | |
1170 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1171 | efx_monitor_interval); | |
1172 | return; | |
1173 | } | |
1174 | ||
1175 | if (efx->port_enabled) | |
1176 | rc = falcon_check_xmac(efx); | |
1177 | mutex_unlock(&efx->mac_lock); | |
1178 | ||
1179 | if (rc) { | |
1180 | if (monitor_reset) { | |
1181 | EFX_ERR(efx, "hardware monitor detected a fault: " | |
1182 | "triggering reset\n"); | |
1183 | efx_schedule_reset(efx, RESET_TYPE_MONITOR); | |
1184 | } else { | |
1185 | EFX_ERR(efx, "hardware monitor detected a fault, " | |
1186 | "skipping reset\n"); | |
1187 | } | |
1188 | } | |
1189 | ||
1190 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1191 | efx_monitor_interval); | |
1192 | } | |
1193 | ||
1194 | /************************************************************************** | |
1195 | * | |
1196 | * ioctls | |
1197 | * | |
1198 | *************************************************************************/ | |
1199 | ||
1200 | /* Net device ioctl | |
1201 | * Context: process, rtnl_lock() held. | |
1202 | */ | |
1203 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1204 | { | |
767e468c | 1205 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1206 | |
1207 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1208 | ||
1209 | return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL); | |
1210 | } | |
1211 | ||
1212 | /************************************************************************** | |
1213 | * | |
1214 | * NAPI interface | |
1215 | * | |
1216 | **************************************************************************/ | |
1217 | ||
1218 | static int efx_init_napi(struct efx_nic *efx) | |
1219 | { | |
1220 | struct efx_channel *channel; | |
1221 | int rc; | |
1222 | ||
1223 | efx_for_each_channel(channel, efx) { | |
1224 | channel->napi_dev = efx->net_dev; | |
1225 | rc = efx_lro_init(&channel->lro_mgr, efx); | |
1226 | if (rc) | |
1227 | goto err; | |
1228 | } | |
1229 | return 0; | |
1230 | err: | |
1231 | efx_fini_napi(efx); | |
1232 | return rc; | |
1233 | } | |
1234 | ||
1235 | static void efx_fini_napi(struct efx_nic *efx) | |
1236 | { | |
1237 | struct efx_channel *channel; | |
1238 | ||
1239 | efx_for_each_channel(channel, efx) { | |
1240 | efx_lro_fini(&channel->lro_mgr); | |
1241 | channel->napi_dev = NULL; | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | /************************************************************************** | |
1246 | * | |
1247 | * Kernel netpoll interface | |
1248 | * | |
1249 | *************************************************************************/ | |
1250 | ||
1251 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1252 | ||
1253 | /* Although in the common case interrupts will be disabled, this is not | |
1254 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1255 | * so no locking is required. | |
1256 | */ | |
1257 | static void efx_netpoll(struct net_device *net_dev) | |
1258 | { | |
767e468c | 1259 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1260 | struct efx_channel *channel; |
1261 | ||
64ee3120 | 1262 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1263 | efx_schedule_channel(channel); |
1264 | } | |
1265 | ||
1266 | #endif | |
1267 | ||
1268 | /************************************************************************** | |
1269 | * | |
1270 | * Kernel net device interface | |
1271 | * | |
1272 | *************************************************************************/ | |
1273 | ||
1274 | /* Context: process, rtnl_lock() held. */ | |
1275 | static int efx_net_open(struct net_device *net_dev) | |
1276 | { | |
767e468c | 1277 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1278 | EFX_ASSERT_RESET_SERIALISED(efx); |
1279 | ||
1280 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1281 | raw_smp_processor_id()); | |
1282 | ||
f8b87c17 BH |
1283 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1284 | return -EBUSY; | |
1285 | ||
8ceee660 BH |
1286 | efx_start_all(efx); |
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | /* Context: process, rtnl_lock() held. | |
1291 | * Note that the kernel will ignore our return code; this method | |
1292 | * should really be a void. | |
1293 | */ | |
1294 | static int efx_net_stop(struct net_device *net_dev) | |
1295 | { | |
767e468c | 1296 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1297 | |
1298 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1299 | raw_smp_processor_id()); | |
1300 | ||
1301 | /* Stop the device and flush all the channels */ | |
1302 | efx_stop_all(efx); | |
1303 | efx_fini_channels(efx); | |
bc3c90a2 | 1304 | efx_init_channels(efx); |
8ceee660 BH |
1305 | |
1306 | return 0; | |
1307 | } | |
1308 | ||
5b9e207c | 1309 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1310 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1311 | { | |
767e468c | 1312 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1313 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1314 | struct net_device_stats *stats = &net_dev->stats; | |
1315 | ||
5b9e207c BH |
1316 | /* Update stats if possible, but do not wait if another thread |
1317 | * is updating them (or resetting the NIC); slightly stale | |
1318 | * stats are acceptable. | |
1319 | */ | |
8ceee660 BH |
1320 | if (!spin_trylock(&efx->stats_lock)) |
1321 | return stats; | |
8c8661e4 | 1322 | if (efx->stats_enabled) { |
8ceee660 BH |
1323 | falcon_update_stats_xmac(efx); |
1324 | falcon_update_nic_stats(efx); | |
1325 | } | |
1326 | spin_unlock(&efx->stats_lock); | |
1327 | ||
1328 | stats->rx_packets = mac_stats->rx_packets; | |
1329 | stats->tx_packets = mac_stats->tx_packets; | |
1330 | stats->rx_bytes = mac_stats->rx_bytes; | |
1331 | stats->tx_bytes = mac_stats->tx_bytes; | |
1332 | stats->multicast = mac_stats->rx_multicast; | |
1333 | stats->collisions = mac_stats->tx_collision; | |
1334 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1335 | mac_stats->rx_length_error); | |
1336 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1337 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1338 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1339 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1340 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1341 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1342 | ||
1343 | stats->rx_errors = (stats->rx_length_errors + | |
1344 | stats->rx_over_errors + | |
1345 | stats->rx_crc_errors + | |
1346 | stats->rx_frame_errors + | |
1347 | stats->rx_fifo_errors + | |
1348 | stats->rx_missed_errors + | |
1349 | mac_stats->rx_symbol_error); | |
1350 | stats->tx_errors = (stats->tx_window_errors + | |
1351 | mac_stats->tx_bad); | |
1352 | ||
1353 | return stats; | |
1354 | } | |
1355 | ||
1356 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1357 | static void efx_watchdog(struct net_device *net_dev) | |
1358 | { | |
767e468c | 1359 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1360 | |
1361 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d: %s\n", | |
1362 | atomic_read(&efx->netif_stop_count), efx->port_enabled, | |
1363 | monitor_reset ? "resetting channels" : "skipping reset"); | |
1364 | ||
1365 | if (monitor_reset) | |
1366 | efx_schedule_reset(efx, RESET_TYPE_MONITOR); | |
1367 | } | |
1368 | ||
1369 | ||
1370 | /* Context: process, rtnl_lock() held. */ | |
1371 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1372 | { | |
767e468c | 1373 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1374 | int rc = 0; |
1375 | ||
1376 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1377 | ||
1378 | if (new_mtu > EFX_MAX_MTU) | |
1379 | return -EINVAL; | |
1380 | ||
1381 | efx_stop_all(efx); | |
1382 | ||
1383 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1384 | ||
1385 | efx_fini_channels(efx); | |
1386 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1387 | efx_init_channels(efx); |
8ceee660 BH |
1388 | |
1389 | efx_start_all(efx); | |
1390 | return rc; | |
8ceee660 BH |
1391 | } |
1392 | ||
1393 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1394 | { | |
767e468c | 1395 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1396 | struct sockaddr *addr = data; |
1397 | char *new_addr = addr->sa_data; | |
1398 | ||
1399 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1400 | ||
1401 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1402 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1403 | new_addr); | |
8ceee660 BH |
1404 | return -EINVAL; |
1405 | } | |
1406 | ||
1407 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1408 | ||
1409 | /* Reconfigure the MAC */ | |
1410 | efx_reconfigure_port(efx); | |
1411 | ||
1412 | return 0; | |
1413 | } | |
1414 | ||
a816f75a | 1415 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1416 | static void efx_set_multicast_list(struct net_device *net_dev) |
1417 | { | |
767e468c | 1418 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1419 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1420 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
a816f75a BH |
1421 | bool promiscuous = !!(net_dev->flags & IFF_PROMISC); |
1422 | bool changed = (efx->promiscuous != promiscuous); | |
8ceee660 BH |
1423 | u32 crc; |
1424 | int bit; | |
1425 | int i; | |
1426 | ||
a816f75a | 1427 | efx->promiscuous = promiscuous; |
8ceee660 BH |
1428 | |
1429 | /* Build multicast hash table */ | |
1430 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1431 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1432 | } else { | |
1433 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1434 | for (i = 0; i < net_dev->mc_count; i++) { | |
1435 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1436 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1437 | set_bit_le(bit, mc_hash->byte); | |
1438 | mc_list = mc_list->next; | |
1439 | } | |
1440 | } | |
1441 | ||
a816f75a BH |
1442 | if (!efx->port_enabled) |
1443 | /* Delay pushing settings until efx_start_port() */ | |
1444 | return; | |
1445 | ||
1446 | if (changed) | |
1447 | queue_work(efx->workqueue, &efx->reconfigure_work); | |
1448 | ||
8ceee660 BH |
1449 | /* Create and activate new global multicast hash table */ |
1450 | falcon_set_multicast_hash(efx); | |
1451 | } | |
1452 | ||
1453 | static int efx_netdev_event(struct notifier_block *this, | |
1454 | unsigned long event, void *ptr) | |
1455 | { | |
d3208b5e | 1456 | struct net_device *net_dev = ptr; |
8ceee660 BH |
1457 | |
1458 | if (net_dev->open == efx_net_open && event == NETDEV_CHANGENAME) { | |
767e468c | 1459 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1460 | |
1461 | strcpy(efx->name, net_dev->name); | |
1462 | } | |
1463 | ||
1464 | return NOTIFY_DONE; | |
1465 | } | |
1466 | ||
1467 | static struct notifier_block efx_netdev_notifier = { | |
1468 | .notifier_call = efx_netdev_event, | |
1469 | }; | |
1470 | ||
1471 | static int efx_register_netdev(struct efx_nic *efx) | |
1472 | { | |
1473 | struct net_device *net_dev = efx->net_dev; | |
1474 | int rc; | |
1475 | ||
1476 | net_dev->watchdog_timeo = 5 * HZ; | |
1477 | net_dev->irq = efx->pci_dev->irq; | |
1478 | net_dev->open = efx_net_open; | |
1479 | net_dev->stop = efx_net_stop; | |
1480 | net_dev->get_stats = efx_net_stats; | |
1481 | net_dev->tx_timeout = &efx_watchdog; | |
1482 | net_dev->hard_start_xmit = efx_hard_start_xmit; | |
1483 | net_dev->do_ioctl = efx_ioctl; | |
1484 | net_dev->change_mtu = efx_change_mtu; | |
1485 | net_dev->set_mac_address = efx_set_mac_address; | |
1486 | net_dev->set_multicast_list = efx_set_multicast_list; | |
1487 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1488 | net_dev->poll_controller = efx_netpoll; | |
1489 | #endif | |
1490 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); | |
1491 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1492 | ||
1493 | /* Always start with carrier off; PHY events will detect the link */ | |
1494 | netif_carrier_off(efx->net_dev); | |
1495 | ||
1496 | /* Clear MAC statistics */ | |
1497 | falcon_update_stats_xmac(efx); | |
1498 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); | |
1499 | ||
1500 | rc = register_netdev(net_dev); | |
1501 | if (rc) { | |
1502 | EFX_ERR(efx, "could not register net dev\n"); | |
1503 | return rc; | |
1504 | } | |
1505 | strcpy(efx->name, net_dev->name); | |
1506 | ||
1507 | return 0; | |
1508 | } | |
1509 | ||
1510 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1511 | { | |
1512 | struct efx_tx_queue *tx_queue; | |
1513 | ||
1514 | if (!efx->net_dev) | |
1515 | return; | |
1516 | ||
767e468c | 1517 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1518 | |
1519 | /* Free up any skbs still remaining. This has to happen before | |
1520 | * we try to unregister the netdev as running their destructors | |
1521 | * may be needed to get the device ref. count to 0. */ | |
1522 | efx_for_each_tx_queue(tx_queue, efx) | |
1523 | efx_release_tx_buffers(tx_queue); | |
1524 | ||
55668611 | 1525 | if (efx_dev_registered(efx)) { |
8ceee660 BH |
1526 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
1527 | unregister_netdev(efx->net_dev); | |
1528 | } | |
1529 | } | |
1530 | ||
1531 | /************************************************************************** | |
1532 | * | |
1533 | * Device reset and suspend | |
1534 | * | |
1535 | **************************************************************************/ | |
1536 | ||
2467ca46 BH |
1537 | /* Tears down the entire software state and most of the hardware state |
1538 | * before reset. */ | |
8c8661e4 | 1539 | void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
8ceee660 BH |
1540 | { |
1541 | int rc; | |
1542 | ||
1543 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1544 | ||
2467ca46 BH |
1545 | /* The net_dev->get_stats handler is quite slow, and will fail |
1546 | * if a fetch is pending over reset. Serialise against it. */ | |
1547 | spin_lock(&efx->stats_lock); | |
8c8661e4 | 1548 | efx->stats_enabled = false; |
2467ca46 BH |
1549 | spin_unlock(&efx->stats_lock); |
1550 | ||
1551 | efx_stop_all(efx); | |
1552 | mutex_lock(&efx->mac_lock); | |
1553 | ||
8ceee660 | 1554 | rc = falcon_xmac_get_settings(efx, ecmd); |
2467ca46 | 1555 | if (rc) |
8ceee660 | 1556 | EFX_ERR(efx, "could not back up PHY settings\n"); |
8ceee660 BH |
1557 | |
1558 | efx_fini_channels(efx); | |
8ceee660 BH |
1559 | } |
1560 | ||
2467ca46 BH |
1561 | /* This function will always ensure that the locks acquired in |
1562 | * efx_reset_down() are released. A failure return code indicates | |
1563 | * that we were unable to reinitialise the hardware, and the | |
1564 | * driver should be disabled. If ok is false, then the rx and tx | |
1565 | * engines are not restarted, pending a RESET_DISABLE. */ | |
8c8661e4 | 1566 | int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd, bool ok) |
8ceee660 BH |
1567 | { |
1568 | int rc; | |
1569 | ||
2467ca46 | 1570 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1571 | |
2467ca46 | 1572 | rc = falcon_init_nic(efx); |
8ceee660 | 1573 | if (rc) { |
2467ca46 BH |
1574 | EFX_ERR(efx, "failed to initialise NIC\n"); |
1575 | ok = false; | |
8ceee660 BH |
1576 | } |
1577 | ||
2467ca46 BH |
1578 | if (ok) { |
1579 | efx_init_channels(efx); | |
8ceee660 | 1580 | |
2467ca46 BH |
1581 | if (falcon_xmac_set_settings(efx, ecmd)) |
1582 | EFX_ERR(efx, "could not restore PHY settings\n"); | |
1583 | } | |
1584 | ||
1585 | mutex_unlock(&efx->mac_lock); | |
1586 | ||
8c8661e4 | 1587 | if (ok) { |
2467ca46 | 1588 | efx_start_all(efx); |
8c8661e4 BH |
1589 | efx->stats_enabled = true; |
1590 | } | |
8ceee660 BH |
1591 | return rc; |
1592 | } | |
1593 | ||
1594 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1595 | * Note that the reset may fail, in which case the card will be left | |
1596 | * in a most-probably-unusable state. | |
1597 | * | |
1598 | * This function will sleep. You cannot reset from within an atomic | |
1599 | * state; use efx_schedule_reset() instead. | |
1600 | * | |
1601 | * Grabs the rtnl_lock. | |
1602 | */ | |
1603 | static int efx_reset(struct efx_nic *efx) | |
1604 | { | |
1605 | struct ethtool_cmd ecmd; | |
1606 | enum reset_type method = efx->reset_pending; | |
1607 | int rc; | |
1608 | ||
1609 | /* Serialise with kernel interfaces */ | |
1610 | rtnl_lock(); | |
1611 | ||
1612 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1613 | * flag set so that efx_pci_probe_main will be retried */ | |
1614 | if (efx->state != STATE_RUNNING) { | |
1615 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
1616 | goto unlock_rtnl; | |
1617 | } | |
1618 | ||
8ceee660 BH |
1619 | EFX_INFO(efx, "resetting (%d)\n", method); |
1620 | ||
2467ca46 | 1621 | efx_reset_down(efx, &ecmd); |
8ceee660 BH |
1622 | |
1623 | rc = falcon_reset_hw(efx, method); | |
1624 | if (rc) { | |
1625 | EFX_ERR(efx, "failed to reset hardware\n"); | |
2467ca46 | 1626 | goto fail; |
8ceee660 BH |
1627 | } |
1628 | ||
1629 | /* Allow resets to be rescheduled. */ | |
1630 | efx->reset_pending = RESET_TYPE_NONE; | |
1631 | ||
1632 | /* Reinitialise bus-mastering, which may have been turned off before | |
1633 | * the reset was scheduled. This is still appropriate, even in the | |
1634 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1635 | * can respond to requests. */ | |
1636 | pci_set_master(efx->pci_dev); | |
1637 | ||
8ceee660 BH |
1638 | /* Leave device stopped if necessary */ |
1639 | if (method == RESET_TYPE_DISABLE) { | |
8ceee660 | 1640 | rc = -EIO; |
2467ca46 | 1641 | goto fail; |
8ceee660 BH |
1642 | } |
1643 | ||
2467ca46 | 1644 | rc = efx_reset_up(efx, &ecmd, true); |
8ceee660 | 1645 | if (rc) |
2467ca46 | 1646 | goto disable; |
8ceee660 | 1647 | |
8ceee660 | 1648 | EFX_LOG(efx, "reset complete\n"); |
8ceee660 BH |
1649 | unlock_rtnl: |
1650 | rtnl_unlock(); | |
1651 | return 0; | |
1652 | ||
2467ca46 BH |
1653 | fail: |
1654 | efx_reset_up(efx, &ecmd, false); | |
1655 | disable: | |
8ceee660 BH |
1656 | EFX_ERR(efx, "has been disabled\n"); |
1657 | efx->state = STATE_DISABLED; | |
1658 | ||
8ceee660 BH |
1659 | rtnl_unlock(); |
1660 | efx_unregister_netdev(efx); | |
1661 | efx_fini_port(efx); | |
1662 | return rc; | |
1663 | } | |
1664 | ||
1665 | /* The worker thread exists so that code that cannot sleep can | |
1666 | * schedule a reset for later. | |
1667 | */ | |
1668 | static void efx_reset_work(struct work_struct *data) | |
1669 | { | |
1670 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1671 | ||
1672 | efx_reset(nic); | |
1673 | } | |
1674 | ||
1675 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1676 | { | |
1677 | enum reset_type method; | |
1678 | ||
1679 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1680 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1681 | return; | |
1682 | } | |
1683 | ||
1684 | switch (type) { | |
1685 | case RESET_TYPE_INVISIBLE: | |
1686 | case RESET_TYPE_ALL: | |
1687 | case RESET_TYPE_WORLD: | |
1688 | case RESET_TYPE_DISABLE: | |
1689 | method = type; | |
1690 | break; | |
1691 | case RESET_TYPE_RX_RECOVERY: | |
1692 | case RESET_TYPE_RX_DESC_FETCH: | |
1693 | case RESET_TYPE_TX_DESC_FETCH: | |
1694 | case RESET_TYPE_TX_SKIP: | |
1695 | method = RESET_TYPE_INVISIBLE; | |
1696 | break; | |
1697 | default: | |
1698 | method = RESET_TYPE_ALL; | |
1699 | break; | |
1700 | } | |
1701 | ||
1702 | if (method != type) | |
1703 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1704 | else | |
1705 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1706 | ||
1707 | efx->reset_pending = method; | |
1708 | ||
8d9853d9 | 1709 | queue_work(efx->reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1710 | } |
1711 | ||
1712 | /************************************************************************** | |
1713 | * | |
1714 | * List of NICs we support | |
1715 | * | |
1716 | **************************************************************************/ | |
1717 | ||
1718 | /* PCI device ID table */ | |
1719 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1720 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1721 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1722 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1723 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1724 | {0} /* end of list */ | |
1725 | }; | |
1726 | ||
1727 | /************************************************************************** | |
1728 | * | |
1729 | * Dummy PHY/MAC/Board operations | |
1730 | * | |
01aad7b6 | 1731 | * Can be used for some unimplemented operations |
8ceee660 BH |
1732 | * Needed so all function pointers are valid and do not have to be tested |
1733 | * before use | |
1734 | * | |
1735 | **************************************************************************/ | |
1736 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1737 | { | |
1738 | return 0; | |
1739 | } | |
1740 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
dc8cfa55 | 1741 | void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {} |
8ceee660 BH |
1742 | |
1743 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
1744 | .init = efx_port_dummy_op_int, | |
1745 | .reconfigure = efx_port_dummy_op_void, | |
1746 | .check_hw = efx_port_dummy_op_int, | |
1747 | .fini = efx_port_dummy_op_void, | |
1748 | .clear_interrupt = efx_port_dummy_op_void, | |
8ceee660 BH |
1749 | }; |
1750 | ||
8ceee660 | 1751 | static struct efx_board efx_dummy_board_info = { |
01aad7b6 BH |
1752 | .init = efx_port_dummy_op_int, |
1753 | .init_leds = efx_port_dummy_op_int, | |
1754 | .set_fault_led = efx_port_dummy_op_blink, | |
1755 | .blink = efx_port_dummy_op_blink, | |
1756 | .fini = efx_port_dummy_op_void, | |
8ceee660 BH |
1757 | }; |
1758 | ||
1759 | /************************************************************************** | |
1760 | * | |
1761 | * Data housekeeping | |
1762 | * | |
1763 | **************************************************************************/ | |
1764 | ||
1765 | /* This zeroes out and then fills in the invariants in a struct | |
1766 | * efx_nic (including all sub-structures). | |
1767 | */ | |
1768 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1769 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1770 | { | |
1771 | struct efx_channel *channel; | |
1772 | struct efx_tx_queue *tx_queue; | |
1773 | struct efx_rx_queue *rx_queue; | |
1774 | int i, rc; | |
1775 | ||
1776 | /* Initialise common structures */ | |
1777 | memset(efx, 0, sizeof(*efx)); | |
1778 | spin_lock_init(&efx->biu_lock); | |
1779 | spin_lock_init(&efx->phy_lock); | |
1780 | INIT_WORK(&efx->reset_work, efx_reset_work); | |
1781 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1782 | efx->pci_dev = pci_dev; | |
1783 | efx->state = STATE_INIT; | |
1784 | efx->reset_pending = RESET_TYPE_NONE; | |
1785 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
1786 | efx->board_info = efx_dummy_board_info; | |
1787 | ||
1788 | efx->net_dev = net_dev; | |
dc8cfa55 | 1789 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1790 | spin_lock_init(&efx->netif_stop_lock); |
1791 | spin_lock_init(&efx->stats_lock); | |
1792 | mutex_init(&efx->mac_lock); | |
1793 | efx->phy_op = &efx_dummy_phy_operations; | |
1794 | efx->mii.dev = net_dev; | |
1795 | INIT_WORK(&efx->reconfigure_work, efx_reconfigure_work); | |
1796 | atomic_set(&efx->netif_stop_count, 1); | |
1797 | ||
1798 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1799 | channel = &efx->channel[i]; | |
1800 | channel->efx = efx; | |
1801 | channel->channel = i; | |
dc8cfa55 | 1802 | channel->work_pending = false; |
8ceee660 | 1803 | } |
60ac1065 | 1804 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1805 | tx_queue = &efx->tx_queue[i]; |
1806 | tx_queue->efx = efx; | |
1807 | tx_queue->queue = i; | |
1808 | tx_queue->buffer = NULL; | |
1809 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1810 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1811 | } |
1812 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1813 | rx_queue = &efx->rx_queue[i]; | |
1814 | rx_queue->efx = efx; | |
1815 | rx_queue->queue = i; | |
1816 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1817 | rx_queue->buffer = NULL; | |
1818 | spin_lock_init(&rx_queue->add_lock); | |
1819 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1820 | } | |
1821 | ||
1822 | efx->type = type; | |
1823 | ||
1824 | /* Sanity-check NIC type */ | |
1825 | EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask & | |
1826 | (efx->type->txd_ring_mask + 1)); | |
1827 | EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask & | |
1828 | (efx->type->rxd_ring_mask + 1)); | |
1829 | EFX_BUG_ON_PARANOID(efx->type->evq_size & | |
1830 | (efx->type->evq_size - 1)); | |
1831 | /* As close as we can get to guaranteeing that we don't overflow */ | |
1832 | EFX_BUG_ON_PARANOID(efx->type->evq_size < | |
1833 | (efx->type->txd_ring_mask + 1 + | |
1834 | efx->type->rxd_ring_mask + 1)); | |
1835 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); | |
1836 | ||
1837 | /* Higher numbered interrupt modes are less capable! */ | |
1838 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1839 | interrupt_mode); | |
1840 | ||
1841 | efx->workqueue = create_singlethread_workqueue("sfc_work"); | |
1842 | if (!efx->workqueue) { | |
1843 | rc = -ENOMEM; | |
1844 | goto fail1; | |
1845 | } | |
1846 | ||
8d9853d9 BH |
1847 | efx->reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
1848 | if (!efx->reset_workqueue) { | |
1849 | rc = -ENOMEM; | |
1850 | goto fail2; | |
1851 | } | |
1852 | ||
8ceee660 BH |
1853 | return 0; |
1854 | ||
8d9853d9 BH |
1855 | fail2: |
1856 | destroy_workqueue(efx->workqueue); | |
1857 | efx->workqueue = NULL; | |
1858 | ||
8ceee660 BH |
1859 | fail1: |
1860 | return rc; | |
1861 | } | |
1862 | ||
1863 | static void efx_fini_struct(struct efx_nic *efx) | |
1864 | { | |
8d9853d9 BH |
1865 | if (efx->reset_workqueue) { |
1866 | destroy_workqueue(efx->reset_workqueue); | |
1867 | efx->reset_workqueue = NULL; | |
1868 | } | |
8ceee660 BH |
1869 | if (efx->workqueue) { |
1870 | destroy_workqueue(efx->workqueue); | |
1871 | efx->workqueue = NULL; | |
1872 | } | |
1873 | } | |
1874 | ||
1875 | /************************************************************************** | |
1876 | * | |
1877 | * PCI interface | |
1878 | * | |
1879 | **************************************************************************/ | |
1880 | ||
1881 | /* Main body of final NIC shutdown code | |
1882 | * This is called only at module unload (or hotplug removal). | |
1883 | */ | |
1884 | static void efx_pci_remove_main(struct efx_nic *efx) | |
1885 | { | |
1886 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1887 | ||
1888 | /* Skip everything if we never obtained a valid membase */ | |
1889 | if (!efx->membase) | |
1890 | return; | |
1891 | ||
1892 | efx_fini_channels(efx); | |
1893 | efx_fini_port(efx); | |
1894 | ||
1895 | /* Shutdown the board, then the NIC and board state */ | |
37b5a603 | 1896 | efx->board_info.fini(efx); |
8ceee660 BH |
1897 | falcon_fini_interrupt(efx); |
1898 | ||
1899 | efx_fini_napi(efx); | |
1900 | efx_remove_all(efx); | |
1901 | } | |
1902 | ||
1903 | /* Final NIC shutdown | |
1904 | * This is called only at module unload (or hotplug removal). | |
1905 | */ | |
1906 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
1907 | { | |
1908 | struct efx_nic *efx; | |
1909 | ||
1910 | efx = pci_get_drvdata(pci_dev); | |
1911 | if (!efx) | |
1912 | return; | |
1913 | ||
1914 | /* Mark the NIC as fini, then stop the interface */ | |
1915 | rtnl_lock(); | |
1916 | efx->state = STATE_FINI; | |
1917 | dev_close(efx->net_dev); | |
1918 | ||
1919 | /* Allow any queued efx_resets() to complete */ | |
1920 | rtnl_unlock(); | |
1921 | ||
1922 | if (efx->membase == NULL) | |
1923 | goto out; | |
1924 | ||
1925 | efx_unregister_netdev(efx); | |
1926 | ||
1927 | /* Wait for any scheduled resets to complete. No more will be | |
1928 | * scheduled from this point because efx_stop_all() has been | |
1929 | * called, we are no longer registered with driverlink, and | |
1930 | * the net_device's have been removed. */ | |
8d9853d9 | 1931 | flush_workqueue(efx->reset_workqueue); |
8ceee660 BH |
1932 | |
1933 | efx_pci_remove_main(efx); | |
1934 | ||
1935 | out: | |
1936 | efx_fini_io(efx); | |
1937 | EFX_LOG(efx, "shutdown successful\n"); | |
1938 | ||
1939 | pci_set_drvdata(pci_dev, NULL); | |
1940 | efx_fini_struct(efx); | |
1941 | free_netdev(efx->net_dev); | |
1942 | }; | |
1943 | ||
1944 | /* Main body of NIC initialisation | |
1945 | * This is called at module load (or hotplug insertion, theoretically). | |
1946 | */ | |
1947 | static int efx_pci_probe_main(struct efx_nic *efx) | |
1948 | { | |
1949 | int rc; | |
1950 | ||
1951 | /* Do start-of-day initialisation */ | |
1952 | rc = efx_probe_all(efx); | |
1953 | if (rc) | |
1954 | goto fail1; | |
1955 | ||
1956 | rc = efx_init_napi(efx); | |
1957 | if (rc) | |
1958 | goto fail2; | |
1959 | ||
1960 | /* Initialise the board */ | |
1961 | rc = efx->board_info.init(efx); | |
1962 | if (rc) { | |
1963 | EFX_ERR(efx, "failed to initialise board\n"); | |
1964 | goto fail3; | |
1965 | } | |
1966 | ||
1967 | rc = falcon_init_nic(efx); | |
1968 | if (rc) { | |
1969 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
1970 | goto fail4; | |
1971 | } | |
1972 | ||
1973 | rc = efx_init_port(efx); | |
1974 | if (rc) { | |
1975 | EFX_ERR(efx, "failed to initialise port\n"); | |
1976 | goto fail5; | |
1977 | } | |
1978 | ||
bc3c90a2 | 1979 | efx_init_channels(efx); |
8ceee660 BH |
1980 | |
1981 | rc = falcon_init_interrupt(efx); | |
1982 | if (rc) | |
bc3c90a2 | 1983 | goto fail6; |
8ceee660 BH |
1984 | |
1985 | return 0; | |
1986 | ||
8ceee660 | 1987 | fail6: |
bc3c90a2 | 1988 | efx_fini_channels(efx); |
8ceee660 BH |
1989 | efx_fini_port(efx); |
1990 | fail5: | |
1991 | fail4: | |
1992 | fail3: | |
1993 | efx_fini_napi(efx); | |
1994 | fail2: | |
1995 | efx_remove_all(efx); | |
1996 | fail1: | |
1997 | return rc; | |
1998 | } | |
1999 | ||
2000 | /* NIC initialisation | |
2001 | * | |
2002 | * This is called at module load (or hotplug insertion, | |
2003 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2004 | * sets up and registers the network devices with the kernel and hooks | |
2005 | * the interrupt service routine. It does not prepare the device for | |
2006 | * transmission; this is left to the first time one of the network | |
2007 | * interfaces is brought up (i.e. efx_net_open). | |
2008 | */ | |
2009 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2010 | const struct pci_device_id *entry) | |
2011 | { | |
2012 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2013 | struct net_device *net_dev; | |
2014 | struct efx_nic *efx; | |
2015 | int i, rc; | |
2016 | ||
2017 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2018 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2019 | if (!net_dev) | |
2020 | return -ENOMEM; | |
b9b39b62 BH |
2021 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
2022 | NETIF_F_HIGHDMA | NETIF_F_TSO); | |
8ceee660 BH |
2023 | if (lro) |
2024 | net_dev->features |= NETIF_F_LRO; | |
28506563 BH |
2025 | /* Mask for features that also apply to VLAN devices */ |
2026 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2027 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2028 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2029 | pci_set_drvdata(pci_dev, efx); |
2030 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2031 | if (rc) | |
2032 | goto fail1; | |
2033 | ||
2034 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2035 | ||
2036 | /* Set up basic I/O (BAR mappings etc) */ | |
2037 | rc = efx_init_io(efx); | |
2038 | if (rc) | |
2039 | goto fail2; | |
2040 | ||
2041 | /* No serialisation is required with the reset path because | |
2042 | * we're in STATE_INIT. */ | |
2043 | for (i = 0; i < 5; i++) { | |
2044 | rc = efx_pci_probe_main(efx); | |
2045 | if (rc == 0) | |
2046 | break; | |
2047 | ||
2048 | /* Serialise against efx_reset(). No more resets will be | |
2049 | * scheduled since efx_stop_all() has been called, and we | |
2050 | * have not and never have been registered with either | |
2051 | * the rtnetlink or driverlink layers. */ | |
8d9853d9 | 2052 | flush_workqueue(efx->reset_workqueue); |
8ceee660 BH |
2053 | |
2054 | /* Retry if a recoverably reset event has been scheduled */ | |
2055 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2056 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2057 | goto fail3; | |
2058 | ||
2059 | efx->reset_pending = RESET_TYPE_NONE; | |
2060 | } | |
2061 | ||
2062 | if (rc) { | |
2063 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2064 | goto fail4; | |
2065 | } | |
2066 | ||
2067 | /* Switch to the running state before we expose the device to | |
2068 | * the OS. This is to ensure that the initial gathering of | |
2069 | * MAC stats succeeds. */ | |
2070 | rtnl_lock(); | |
2071 | efx->state = STATE_RUNNING; | |
2072 | rtnl_unlock(); | |
2073 | ||
2074 | rc = efx_register_netdev(efx); | |
2075 | if (rc) | |
2076 | goto fail5; | |
2077 | ||
2078 | EFX_LOG(efx, "initialisation successful\n"); | |
2079 | ||
2080 | return 0; | |
2081 | ||
2082 | fail5: | |
2083 | efx_pci_remove_main(efx); | |
2084 | fail4: | |
2085 | fail3: | |
2086 | efx_fini_io(efx); | |
2087 | fail2: | |
2088 | efx_fini_struct(efx); | |
2089 | fail1: | |
2090 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2091 | free_netdev(net_dev); | |
2092 | return rc; | |
2093 | } | |
2094 | ||
2095 | static struct pci_driver efx_pci_driver = { | |
2096 | .name = EFX_DRIVER_NAME, | |
2097 | .id_table = efx_pci_table, | |
2098 | .probe = efx_pci_probe, | |
2099 | .remove = efx_pci_remove, | |
2100 | }; | |
2101 | ||
2102 | /************************************************************************** | |
2103 | * | |
2104 | * Kernel module interface | |
2105 | * | |
2106 | *************************************************************************/ | |
2107 | ||
2108 | module_param(interrupt_mode, uint, 0444); | |
2109 | MODULE_PARM_DESC(interrupt_mode, | |
2110 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2111 | ||
2112 | static int __init efx_init_module(void) | |
2113 | { | |
2114 | int rc; | |
2115 | ||
2116 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2117 | ||
2118 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2119 | if (rc) | |
2120 | goto err_notifier; | |
2121 | ||
2122 | refill_workqueue = create_workqueue("sfc_refill"); | |
2123 | if (!refill_workqueue) { | |
2124 | rc = -ENOMEM; | |
2125 | goto err_refill; | |
2126 | } | |
2127 | ||
2128 | rc = pci_register_driver(&efx_pci_driver); | |
2129 | if (rc < 0) | |
2130 | goto err_pci; | |
2131 | ||
2132 | return 0; | |
2133 | ||
2134 | err_pci: | |
2135 | destroy_workqueue(refill_workqueue); | |
2136 | err_refill: | |
2137 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2138 | err_notifier: | |
2139 | return rc; | |
2140 | } | |
2141 | ||
2142 | static void __exit efx_exit_module(void) | |
2143 | { | |
2144 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2145 | ||
2146 | pci_unregister_driver(&efx_pci_driver); | |
2147 | destroy_workqueue(refill_workqueue); | |
2148 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2149 | ||
2150 | } | |
2151 | ||
2152 | module_init(efx_init_module); | |
2153 | module_exit(efx_exit_module); | |
2154 | ||
2155 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2156 | "Solarflare Communications"); | |
2157 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2158 | MODULE_LICENSE("GPL"); | |
2159 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |