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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 | 23 | #include "net_driver.h" |
8ceee660 BH |
24 | #include "ethtool.h" |
25 | #include "tx.h" | |
26 | #include "rx.h" | |
27 | #include "efx.h" | |
28 | #include "mdio_10g.h" | |
29 | #include "falcon.h" | |
8ceee660 BH |
30 | |
31 | #define EFX_MAX_MTU (9 * 1024) | |
32 | ||
33 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
34 | * a work item is pushed onto this work queue to retry the allocation later, | |
35 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
36 | * workqueue, there is nothing to be gained in making it per NIC | |
37 | */ | |
38 | static struct workqueue_struct *refill_workqueue; | |
39 | ||
1ab00629 SH |
40 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
41 | * queued onto this work queue. This is not a per-nic work queue, because | |
42 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
43 | */ | |
44 | static struct workqueue_struct *reset_workqueue; | |
45 | ||
8ceee660 BH |
46 | /************************************************************************** |
47 | * | |
48 | * Configurable values | |
49 | * | |
50 | *************************************************************************/ | |
51 | ||
52 | /* | |
53 | * Enable large receive offload (LRO) aka soft segment reassembly (SSR) | |
54 | * | |
55 | * This sets the default for new devices. It can be controlled later | |
56 | * using ethtool. | |
57 | */ | |
dc8cfa55 | 58 | static int lro = true; |
8ceee660 BH |
59 | module_param(lro, int, 0644); |
60 | MODULE_PARM_DESC(lro, "Large receive offload acceleration"); | |
61 | ||
62 | /* | |
63 | * Use separate channels for TX and RX events | |
64 | * | |
28b581ab NT |
65 | * Set this to 1 to use separate channels for TX and RX. It allows us |
66 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 67 | * |
28b581ab | 68 | * This is only used in MSI-X interrupt mode |
8ceee660 | 69 | */ |
28b581ab NT |
70 | static unsigned int separate_tx_channels; |
71 | module_param(separate_tx_channels, uint, 0644); | |
72 | MODULE_PARM_DESC(separate_tx_channels, | |
73 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
74 | |
75 | /* This is the weight assigned to each of the (per-channel) virtual | |
76 | * NAPI devices. | |
77 | */ | |
78 | static int napi_weight = 64; | |
79 | ||
80 | /* This is the time (in jiffies) between invocations of the hardware | |
81 | * monitor, which checks for known hardware bugs and resets the | |
82 | * hardware and driver as necessary. | |
83 | */ | |
84 | unsigned int efx_monitor_interval = 1 * HZ; | |
85 | ||
8ceee660 BH |
86 | /* This controls whether or not the driver will initialise devices |
87 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
88 | * such devices will be initialised with a random locally-generated | |
89 | * MAC address. This allows for loading the sfc_mtd driver to | |
90 | * reprogram the flash, even if the flash contents (including the MAC | |
91 | * address) have previously been erased. | |
92 | */ | |
93 | static unsigned int allow_bad_hwaddr; | |
94 | ||
95 | /* Initial interrupt moderation settings. They can be modified after | |
96 | * module load with ethtool. | |
97 | * | |
98 | * The default for RX should strike a balance between increasing the | |
99 | * round-trip latency and reducing overhead. | |
100 | */ | |
101 | static unsigned int rx_irq_mod_usec = 60; | |
102 | ||
103 | /* Initial interrupt moderation settings. They can be modified after | |
104 | * module load with ethtool. | |
105 | * | |
106 | * This default is chosen to ensure that a 10G link does not go idle | |
107 | * while a TX queue is stopped after it has become full. A queue is | |
108 | * restarted when it drops below half full. The time this takes (assuming | |
109 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
110 | * 512 / 3 * 1.2 = 205 usec. | |
111 | */ | |
112 | static unsigned int tx_irq_mod_usec = 150; | |
113 | ||
114 | /* This is the first interrupt mode to try out of: | |
115 | * 0 => MSI-X | |
116 | * 1 => MSI | |
117 | * 2 => legacy | |
118 | */ | |
119 | static unsigned int interrupt_mode; | |
120 | ||
121 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
122 | * i.e. the number of CPUs among which we may distribute simultaneous | |
123 | * interrupt handling. | |
124 | * | |
125 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
126 | * The default (0) means to assign an interrupt to each package (level II cache) | |
127 | */ | |
128 | static unsigned int rss_cpus; | |
129 | module_param(rss_cpus, uint, 0444); | |
130 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
131 | ||
84ae48fe BH |
132 | static int phy_flash_cfg; |
133 | module_param(phy_flash_cfg, int, 0644); | |
134 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
135 | ||
8ceee660 BH |
136 | /************************************************************************** |
137 | * | |
138 | * Utility functions and prototypes | |
139 | * | |
140 | *************************************************************************/ | |
141 | static void efx_remove_channel(struct efx_channel *channel); | |
142 | static void efx_remove_port(struct efx_nic *efx); | |
143 | static void efx_fini_napi(struct efx_nic *efx); | |
144 | static void efx_fini_channels(struct efx_nic *efx); | |
145 | ||
146 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
147 | do { \ | |
3c78708f | 148 | if (efx->state == STATE_RUNNING) \ |
8ceee660 BH |
149 | ASSERT_RTNL(); \ |
150 | } while (0) | |
151 | ||
152 | /************************************************************************** | |
153 | * | |
154 | * Event queue processing | |
155 | * | |
156 | *************************************************************************/ | |
157 | ||
158 | /* Process channel's event queue | |
159 | * | |
160 | * This function is responsible for processing the event queue of a | |
161 | * single channel. The caller must guarantee that this function will | |
162 | * never be concurrently called more than once on the same channel, | |
163 | * though different channels may be being processed concurrently. | |
164 | */ | |
4d566063 | 165 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 166 | { |
42cbe2d7 BH |
167 | struct efx_nic *efx = channel->efx; |
168 | int rx_packets; | |
8ceee660 | 169 | |
42cbe2d7 | 170 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 171 | !channel->enabled)) |
42cbe2d7 | 172 | return 0; |
8ceee660 | 173 | |
42cbe2d7 BH |
174 | rx_packets = falcon_process_eventq(channel, rx_quota); |
175 | if (rx_packets == 0) | |
176 | return 0; | |
8ceee660 BH |
177 | |
178 | /* Deliver last RX packet. */ | |
179 | if (channel->rx_pkt) { | |
180 | __efx_rx_packet(channel, channel->rx_pkt, | |
181 | channel->rx_pkt_csummed); | |
182 | channel->rx_pkt = NULL; | |
183 | } | |
184 | ||
8ceee660 BH |
185 | efx_rx_strategy(channel); |
186 | ||
42cbe2d7 | 187 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 188 | |
42cbe2d7 | 189 | return rx_packets; |
8ceee660 BH |
190 | } |
191 | ||
192 | /* Mark channel as finished processing | |
193 | * | |
194 | * Note that since we will not receive further interrupts for this | |
195 | * channel before we finish processing and call the eventq_read_ack() | |
196 | * method, there is no need to use the interrupt hold-off timers. | |
197 | */ | |
198 | static inline void efx_channel_processed(struct efx_channel *channel) | |
199 | { | |
5b9e207c BH |
200 | /* The interrupt handler for this channel may set work_pending |
201 | * as soon as we acknowledge the events we've seen. Make sure | |
202 | * it's cleared before then. */ | |
dc8cfa55 | 203 | channel->work_pending = false; |
5b9e207c BH |
204 | smp_wmb(); |
205 | ||
8ceee660 BH |
206 | falcon_eventq_read_ack(channel); |
207 | } | |
208 | ||
209 | /* NAPI poll handler | |
210 | * | |
211 | * NAPI guarantees serialisation of polls of the same device, which | |
212 | * provides the guarantee required by efx_process_channel(). | |
213 | */ | |
214 | static int efx_poll(struct napi_struct *napi, int budget) | |
215 | { | |
216 | struct efx_channel *channel = | |
217 | container_of(napi, struct efx_channel, napi_str); | |
8ceee660 BH |
218 | int rx_packets; |
219 | ||
220 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
221 | channel->channel, raw_smp_processor_id()); | |
222 | ||
42cbe2d7 | 223 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
224 | |
225 | if (rx_packets < budget) { | |
226 | /* There is no race here; although napi_disable() will | |
288379f0 | 227 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
228 | * since efx_channel_processed() will have no effect if |
229 | * interrupts have already been disabled. | |
230 | */ | |
288379f0 | 231 | napi_complete(napi); |
8ceee660 BH |
232 | efx_channel_processed(channel); |
233 | } | |
234 | ||
235 | return rx_packets; | |
236 | } | |
237 | ||
238 | /* Process the eventq of the specified channel immediately on this CPU | |
239 | * | |
240 | * Disable hardware generated interrupts, wait for any existing | |
241 | * processing to finish, then directly poll (and ack ) the eventq. | |
242 | * Finally reenable NAPI and interrupts. | |
243 | * | |
244 | * Since we are touching interrupts the caller should hold the suspend lock | |
245 | */ | |
246 | void efx_process_channel_now(struct efx_channel *channel) | |
247 | { | |
248 | struct efx_nic *efx = channel->efx; | |
249 | ||
250 | BUG_ON(!channel->used_flags); | |
251 | BUG_ON(!channel->enabled); | |
252 | ||
253 | /* Disable interrupts and wait for ISRs to complete */ | |
254 | falcon_disable_interrupts(efx); | |
255 | if (efx->legacy_irq) | |
256 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 257 | if (channel->irq) |
8ceee660 BH |
258 | synchronize_irq(channel->irq); |
259 | ||
260 | /* Wait for any NAPI processing to complete */ | |
261 | napi_disable(&channel->napi_str); | |
262 | ||
263 | /* Poll the channel */ | |
91ad757c | 264 | efx_process_channel(channel, efx->type->evq_size); |
8ceee660 BH |
265 | |
266 | /* Ack the eventq. This may cause an interrupt to be generated | |
267 | * when they are reenabled */ | |
268 | efx_channel_processed(channel); | |
269 | ||
270 | napi_enable(&channel->napi_str); | |
271 | falcon_enable_interrupts(efx); | |
272 | } | |
273 | ||
274 | /* Create event queue | |
275 | * Event queue memory allocations are done only once. If the channel | |
276 | * is reset, the memory buffer will be reused; this guards against | |
277 | * errors during channel reset and also simplifies interrupt handling. | |
278 | */ | |
279 | static int efx_probe_eventq(struct efx_channel *channel) | |
280 | { | |
281 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
282 | ||
283 | return falcon_probe_eventq(channel); | |
284 | } | |
285 | ||
286 | /* Prepare channel's event queue */ | |
bc3c90a2 | 287 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
288 | { |
289 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
290 | ||
291 | channel->eventq_read_ptr = 0; | |
292 | ||
bc3c90a2 | 293 | falcon_init_eventq(channel); |
8ceee660 BH |
294 | } |
295 | ||
296 | static void efx_fini_eventq(struct efx_channel *channel) | |
297 | { | |
298 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
299 | ||
300 | falcon_fini_eventq(channel); | |
301 | } | |
302 | ||
303 | static void efx_remove_eventq(struct efx_channel *channel) | |
304 | { | |
305 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
306 | ||
307 | falcon_remove_eventq(channel); | |
308 | } | |
309 | ||
310 | /************************************************************************** | |
311 | * | |
312 | * Channel handling | |
313 | * | |
314 | *************************************************************************/ | |
315 | ||
8ceee660 BH |
316 | static int efx_probe_channel(struct efx_channel *channel) |
317 | { | |
318 | struct efx_tx_queue *tx_queue; | |
319 | struct efx_rx_queue *rx_queue; | |
320 | int rc; | |
321 | ||
322 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
323 | ||
324 | rc = efx_probe_eventq(channel); | |
325 | if (rc) | |
326 | goto fail1; | |
327 | ||
328 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
329 | rc = efx_probe_tx_queue(tx_queue); | |
330 | if (rc) | |
331 | goto fail2; | |
332 | } | |
333 | ||
334 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
335 | rc = efx_probe_rx_queue(rx_queue); | |
336 | if (rc) | |
337 | goto fail3; | |
338 | } | |
339 | ||
340 | channel->n_rx_frm_trunc = 0; | |
341 | ||
342 | return 0; | |
343 | ||
344 | fail3: | |
345 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
346 | efx_remove_rx_queue(rx_queue); | |
347 | fail2: | |
348 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
349 | efx_remove_tx_queue(tx_queue); | |
350 | fail1: | |
351 | return rc; | |
352 | } | |
353 | ||
354 | ||
56536e9c BH |
355 | static void efx_set_channel_names(struct efx_nic *efx) |
356 | { | |
357 | struct efx_channel *channel; | |
358 | const char *type = ""; | |
359 | int number; | |
360 | ||
361 | efx_for_each_channel(channel, efx) { | |
362 | number = channel->channel; | |
363 | if (efx->n_channels > efx->n_rx_queues) { | |
364 | if (channel->channel < efx->n_rx_queues) { | |
365 | type = "-rx"; | |
366 | } else { | |
367 | type = "-tx"; | |
368 | number -= efx->n_rx_queues; | |
369 | } | |
370 | } | |
371 | snprintf(channel->name, sizeof(channel->name), | |
372 | "%s%s-%d", efx->name, type, number); | |
373 | } | |
374 | } | |
375 | ||
8ceee660 BH |
376 | /* Channels are shutdown and reinitialised whilst the NIC is running |
377 | * to propagate configuration changes (mtu, checksum offload), or | |
378 | * to clear hardware error conditions | |
379 | */ | |
bc3c90a2 | 380 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
381 | { |
382 | struct efx_tx_queue *tx_queue; | |
383 | struct efx_rx_queue *rx_queue; | |
384 | struct efx_channel *channel; | |
8ceee660 | 385 | |
f7f13b0b BH |
386 | /* Calculate the rx buffer allocation parameters required to |
387 | * support the current MTU, including padding for header | |
388 | * alignment and overruns. | |
389 | */ | |
390 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
391 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
392 | efx->type->rx_buffer_padding); | |
393 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
394 | |
395 | /* Initialise the channels */ | |
396 | efx_for_each_channel(channel, efx) { | |
397 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
398 | ||
bc3c90a2 | 399 | efx_init_eventq(channel); |
8ceee660 | 400 | |
bc3c90a2 BH |
401 | efx_for_each_channel_tx_queue(tx_queue, channel) |
402 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
403 | |
404 | /* The rx buffer allocation strategy is MTU dependent */ | |
405 | efx_rx_strategy(channel); | |
406 | ||
bc3c90a2 BH |
407 | efx_for_each_channel_rx_queue(rx_queue, channel) |
408 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
409 | |
410 | WARN_ON(channel->rx_pkt != NULL); | |
411 | efx_rx_strategy(channel); | |
412 | } | |
8ceee660 BH |
413 | } |
414 | ||
415 | /* This enables event queue processing and packet transmission. | |
416 | * | |
417 | * Note that this function is not allowed to fail, since that would | |
418 | * introduce too much complexity into the suspend/resume path. | |
419 | */ | |
420 | static void efx_start_channel(struct efx_channel *channel) | |
421 | { | |
422 | struct efx_rx_queue *rx_queue; | |
423 | ||
424 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
425 | ||
426 | if (!(channel->efx->net_dev->flags & IFF_UP)) | |
427 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
428 | efx_poll, napi_weight); | |
429 | ||
5b9e207c BH |
430 | /* The interrupt handler for this channel may set work_pending |
431 | * as soon as we enable it. Make sure it's cleared before | |
432 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
433 | channel->work_pending = false; |
434 | channel->enabled = true; | |
5b9e207c | 435 | smp_wmb(); |
8ceee660 BH |
436 | |
437 | napi_enable(&channel->napi_str); | |
438 | ||
439 | /* Load up RX descriptors */ | |
440 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
441 | efx_fast_push_rx_descriptors(rx_queue); | |
442 | } | |
443 | ||
444 | /* This disables event queue processing and packet transmission. | |
445 | * This function does not guarantee that all queue processing | |
446 | * (e.g. RX refill) is complete. | |
447 | */ | |
448 | static void efx_stop_channel(struct efx_channel *channel) | |
449 | { | |
450 | struct efx_rx_queue *rx_queue; | |
451 | ||
452 | if (!channel->enabled) | |
453 | return; | |
454 | ||
455 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
456 | ||
dc8cfa55 | 457 | channel->enabled = false; |
8ceee660 BH |
458 | napi_disable(&channel->napi_str); |
459 | ||
460 | /* Ensure that any worker threads have exited or will be no-ops */ | |
461 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
462 | spin_lock_bh(&rx_queue->add_lock); | |
463 | spin_unlock_bh(&rx_queue->add_lock); | |
464 | } | |
465 | } | |
466 | ||
467 | static void efx_fini_channels(struct efx_nic *efx) | |
468 | { | |
469 | struct efx_channel *channel; | |
470 | struct efx_tx_queue *tx_queue; | |
471 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 472 | int rc; |
8ceee660 BH |
473 | |
474 | EFX_ASSERT_RESET_SERIALISED(efx); | |
475 | BUG_ON(efx->port_enabled); | |
476 | ||
6bc5d3a9 BH |
477 | rc = falcon_flush_queues(efx); |
478 | if (rc) | |
479 | EFX_ERR(efx, "failed to flush queues\n"); | |
480 | else | |
481 | EFX_LOG(efx, "successfully flushed all queues\n"); | |
482 | ||
8ceee660 BH |
483 | efx_for_each_channel(channel, efx) { |
484 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
485 | ||
486 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
487 | efx_fini_rx_queue(rx_queue); | |
488 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
489 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
490 | efx_fini_eventq(channel); |
491 | } | |
492 | } | |
493 | ||
494 | static void efx_remove_channel(struct efx_channel *channel) | |
495 | { | |
496 | struct efx_tx_queue *tx_queue; | |
497 | struct efx_rx_queue *rx_queue; | |
498 | ||
499 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
500 | ||
501 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
502 | efx_remove_rx_queue(rx_queue); | |
503 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
504 | efx_remove_tx_queue(tx_queue); | |
505 | efx_remove_eventq(channel); | |
506 | ||
507 | channel->used_flags = 0; | |
508 | } | |
509 | ||
510 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
511 | { | |
512 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
513 | } | |
514 | ||
515 | /************************************************************************** | |
516 | * | |
517 | * Port handling | |
518 | * | |
519 | **************************************************************************/ | |
520 | ||
521 | /* This ensures that the kernel is kept informed (via | |
522 | * netif_carrier_on/off) of the link status, and also maintains the | |
523 | * link status's stop on the port's TX queue. | |
524 | */ | |
525 | static void efx_link_status_changed(struct efx_nic *efx) | |
526 | { | |
8ceee660 BH |
527 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
528 | * that no events are triggered between unregister_netdev() and the | |
529 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
530 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
531 | if (!netif_running(efx->net_dev)) | |
532 | return; | |
533 | ||
8c8661e4 BH |
534 | if (efx->port_inhibited) { |
535 | netif_carrier_off(efx->net_dev); | |
536 | return; | |
537 | } | |
538 | ||
dc8cfa55 | 539 | if (efx->link_up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
540 | efx->n_link_state_changes++; |
541 | ||
542 | if (efx->link_up) | |
543 | netif_carrier_on(efx->net_dev); | |
544 | else | |
545 | netif_carrier_off(efx->net_dev); | |
546 | } | |
547 | ||
548 | /* Status message for kernel log */ | |
549 | if (efx->link_up) { | |
f31a45d2 BH |
550 | EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n", |
551 | efx->link_speed, efx->link_fd ? "full" : "half", | |
8ceee660 BH |
552 | efx->net_dev->mtu, |
553 | (efx->promiscuous ? " [PROMISC]" : "")); | |
554 | } else { | |
555 | EFX_INFO(efx, "link down\n"); | |
556 | } | |
557 | ||
558 | } | |
559 | ||
560 | /* This call reinitialises the MAC to pick up new PHY settings. The | |
561 | * caller must hold the mac_lock */ | |
8c8661e4 | 562 | void __efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 BH |
563 | { |
564 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
565 | ||
566 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
567 | raw_smp_processor_id()); | |
568 | ||
a816f75a BH |
569 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
570 | if (efx_dev_registered(efx)) { | |
571 | netif_addr_lock_bh(efx->net_dev); | |
572 | netif_addr_unlock_bh(efx->net_dev); | |
573 | } | |
574 | ||
177dfcd8 BH |
575 | falcon_deconfigure_mac_wrapper(efx); |
576 | ||
577 | /* Reconfigure the PHY, disabling transmit in mac level loopback. */ | |
578 | if (LOOPBACK_INTERNAL(efx)) | |
579 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
580 | else | |
581 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
582 | efx->phy_op->reconfigure(efx); | |
583 | ||
584 | if (falcon_switch_mac(efx)) | |
585 | goto fail; | |
586 | ||
587 | efx->mac_op->reconfigure(efx); | |
8ceee660 BH |
588 | |
589 | /* Inform kernel of loss/gain of carrier */ | |
590 | efx_link_status_changed(efx); | |
177dfcd8 BH |
591 | return; |
592 | ||
593 | fail: | |
594 | EFX_ERR(efx, "failed to reconfigure MAC\n"); | |
595 | efx->phy_op->fini(efx); | |
596 | efx->port_initialized = false; | |
8ceee660 BH |
597 | } |
598 | ||
599 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
600 | * disabled. */ | |
601 | void efx_reconfigure_port(struct efx_nic *efx) | |
602 | { | |
603 | EFX_ASSERT_RESET_SERIALISED(efx); | |
604 | ||
605 | mutex_lock(&efx->mac_lock); | |
606 | __efx_reconfigure_port(efx); | |
607 | mutex_unlock(&efx->mac_lock); | |
608 | } | |
609 | ||
610 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
611 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
612 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
766ca0fa | 613 | static void efx_phy_work(struct work_struct *data) |
8ceee660 | 614 | { |
766ca0fa | 615 | struct efx_nic *efx = container_of(data, struct efx_nic, phy_work); |
8ceee660 BH |
616 | |
617 | mutex_lock(&efx->mac_lock); | |
618 | if (efx->port_enabled) | |
619 | __efx_reconfigure_port(efx); | |
620 | mutex_unlock(&efx->mac_lock); | |
621 | } | |
622 | ||
766ca0fa BH |
623 | static void efx_mac_work(struct work_struct *data) |
624 | { | |
625 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
626 | ||
627 | mutex_lock(&efx->mac_lock); | |
628 | if (efx->port_enabled) | |
629 | efx->mac_op->irq(efx); | |
630 | mutex_unlock(&efx->mac_lock); | |
631 | } | |
632 | ||
8ceee660 BH |
633 | static int efx_probe_port(struct efx_nic *efx) |
634 | { | |
635 | int rc; | |
636 | ||
637 | EFX_LOG(efx, "create port\n"); | |
638 | ||
639 | /* Connect up MAC/PHY operations table and read MAC address */ | |
640 | rc = falcon_probe_port(efx); | |
641 | if (rc) | |
642 | goto err; | |
643 | ||
84ae48fe BH |
644 | if (phy_flash_cfg) |
645 | efx->phy_mode = PHY_MODE_SPECIAL; | |
646 | ||
8ceee660 BH |
647 | /* Sanity check MAC address */ |
648 | if (is_valid_ether_addr(efx->mac_address)) { | |
649 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
650 | } else { | |
e174961c JB |
651 | EFX_ERR(efx, "invalid MAC address %pM\n", |
652 | efx->mac_address); | |
8ceee660 BH |
653 | if (!allow_bad_hwaddr) { |
654 | rc = -EINVAL; | |
655 | goto err; | |
656 | } | |
657 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
658 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
659 | efx->net_dev->dev_addr); | |
8ceee660 BH |
660 | } |
661 | ||
662 | return 0; | |
663 | ||
664 | err: | |
665 | efx_remove_port(efx); | |
666 | return rc; | |
667 | } | |
668 | ||
669 | static int efx_init_port(struct efx_nic *efx) | |
670 | { | |
671 | int rc; | |
672 | ||
673 | EFX_LOG(efx, "init port\n"); | |
674 | ||
177dfcd8 | 675 | rc = efx->phy_op->init(efx); |
8ceee660 BH |
676 | if (rc) |
677 | return rc; | |
177dfcd8 | 678 | mutex_lock(&efx->mac_lock); |
4b988280 | 679 | efx->phy_op->reconfigure(efx); |
177dfcd8 BH |
680 | rc = falcon_switch_mac(efx); |
681 | mutex_unlock(&efx->mac_lock); | |
682 | if (rc) | |
683 | goto fail; | |
684 | efx->mac_op->reconfigure(efx); | |
8ceee660 | 685 | |
dc8cfa55 | 686 | efx->port_initialized = true; |
1974cc20 | 687 | efx_stats_enable(efx); |
8ceee660 | 688 | return 0; |
177dfcd8 BH |
689 | |
690 | fail: | |
691 | efx->phy_op->fini(efx); | |
692 | return rc; | |
8ceee660 BH |
693 | } |
694 | ||
695 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
696 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
766ca0fa | 697 | * efx_phy_work()/efx_mac_work() may have been cancelled */ |
8ceee660 BH |
698 | static void efx_start_port(struct efx_nic *efx) |
699 | { | |
700 | EFX_LOG(efx, "start port\n"); | |
701 | BUG_ON(efx->port_enabled); | |
702 | ||
703 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 704 | efx->port_enabled = true; |
8ceee660 | 705 | __efx_reconfigure_port(efx); |
766ca0fa | 706 | efx->mac_op->irq(efx); |
8ceee660 BH |
707 | mutex_unlock(&efx->mac_lock); |
708 | } | |
709 | ||
766ca0fa BH |
710 | /* Prevent efx_phy_work, efx_mac_work, and efx_monitor() from executing, |
711 | * and efx_set_multicast_list() from scheduling efx_phy_work. efx_phy_work | |
712 | * and efx_mac_work may still be scheduled via NAPI processing until | |
713 | * efx_flush_all() is called */ | |
8ceee660 BH |
714 | static void efx_stop_port(struct efx_nic *efx) |
715 | { | |
716 | EFX_LOG(efx, "stop port\n"); | |
717 | ||
718 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 719 | efx->port_enabled = false; |
8ceee660 BH |
720 | mutex_unlock(&efx->mac_lock); |
721 | ||
722 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 723 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
724 | netif_addr_lock_bh(efx->net_dev); |
725 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
726 | } |
727 | } | |
728 | ||
729 | static void efx_fini_port(struct efx_nic *efx) | |
730 | { | |
731 | EFX_LOG(efx, "shut down port\n"); | |
732 | ||
733 | if (!efx->port_initialized) | |
734 | return; | |
735 | ||
1974cc20 | 736 | efx_stats_disable(efx); |
177dfcd8 | 737 | efx->phy_op->fini(efx); |
dc8cfa55 | 738 | efx->port_initialized = false; |
8ceee660 | 739 | |
dc8cfa55 | 740 | efx->link_up = false; |
8ceee660 BH |
741 | efx_link_status_changed(efx); |
742 | } | |
743 | ||
744 | static void efx_remove_port(struct efx_nic *efx) | |
745 | { | |
746 | EFX_LOG(efx, "destroying port\n"); | |
747 | ||
748 | falcon_remove_port(efx); | |
749 | } | |
750 | ||
751 | /************************************************************************** | |
752 | * | |
753 | * NIC handling | |
754 | * | |
755 | **************************************************************************/ | |
756 | ||
757 | /* This configures the PCI device to enable I/O and DMA. */ | |
758 | static int efx_init_io(struct efx_nic *efx) | |
759 | { | |
760 | struct pci_dev *pci_dev = efx->pci_dev; | |
761 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
762 | int rc; | |
763 | ||
764 | EFX_LOG(efx, "initialising I/O\n"); | |
765 | ||
766 | rc = pci_enable_device(pci_dev); | |
767 | if (rc) { | |
768 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
769 | goto fail1; | |
770 | } | |
771 | ||
772 | pci_set_master(pci_dev); | |
773 | ||
774 | /* Set the PCI DMA mask. Try all possibilities from our | |
775 | * genuine mask down to 32 bits, because some architectures | |
776 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
777 | * masks event though they reject 46 bit masks. | |
778 | */ | |
779 | while (dma_mask > 0x7fffffffUL) { | |
780 | if (pci_dma_supported(pci_dev, dma_mask) && | |
781 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
782 | break; | |
783 | dma_mask >>= 1; | |
784 | } | |
785 | if (rc) { | |
786 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
787 | goto fail2; | |
788 | } | |
789 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
790 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
791 | if (rc) { | |
792 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
793 | * fail with a mask that pci_set_dma_mask() accepted, | |
794 | * but just in case... | |
795 | */ | |
796 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
797 | goto fail2; | |
798 | } | |
799 | ||
800 | efx->membase_phys = pci_resource_start(efx->pci_dev, | |
801 | efx->type->mem_bar); | |
802 | rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc"); | |
803 | if (rc) { | |
804 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
805 | rc = -EIO; | |
806 | goto fail3; | |
807 | } | |
808 | efx->membase = ioremap_nocache(efx->membase_phys, | |
809 | efx->type->mem_map_size); | |
810 | if (!efx->membase) { | |
086ea356 BH |
811 | EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n", |
812 | efx->type->mem_bar, | |
813 | (unsigned long long)efx->membase_phys, | |
8ceee660 BH |
814 | efx->type->mem_map_size); |
815 | rc = -ENOMEM; | |
816 | goto fail4; | |
817 | } | |
086ea356 BH |
818 | EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n", |
819 | efx->type->mem_bar, (unsigned long long)efx->membase_phys, | |
820 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
821 | |
822 | return 0; | |
823 | ||
824 | fail4: | |
e1074a0d | 825 | pci_release_region(efx->pci_dev, efx->type->mem_bar); |
8ceee660 | 826 | fail3: |
2c118e0f | 827 | efx->membase_phys = 0; |
8ceee660 BH |
828 | fail2: |
829 | pci_disable_device(efx->pci_dev); | |
830 | fail1: | |
831 | return rc; | |
832 | } | |
833 | ||
834 | static void efx_fini_io(struct efx_nic *efx) | |
835 | { | |
836 | EFX_LOG(efx, "shutting down I/O\n"); | |
837 | ||
838 | if (efx->membase) { | |
839 | iounmap(efx->membase); | |
840 | efx->membase = NULL; | |
841 | } | |
842 | ||
843 | if (efx->membase_phys) { | |
844 | pci_release_region(efx->pci_dev, efx->type->mem_bar); | |
2c118e0f | 845 | efx->membase_phys = 0; |
8ceee660 BH |
846 | } |
847 | ||
848 | pci_disable_device(efx->pci_dev); | |
849 | } | |
850 | ||
46123d04 BH |
851 | /* Get number of RX queues wanted. Return number of online CPU |
852 | * packages in the expectation that an IRQ balancer will spread | |
853 | * interrupts across them. */ | |
854 | static int efx_wanted_rx_queues(void) | |
855 | { | |
856 | cpumask_t core_mask; | |
857 | int count; | |
858 | int cpu; | |
859 | ||
860 | cpus_clear(core_mask); | |
861 | count = 0; | |
862 | for_each_online_cpu(cpu) { | |
863 | if (!cpu_isset(cpu, core_mask)) { | |
864 | ++count; | |
865 | cpus_or(core_mask, core_mask, | |
866 | topology_core_siblings(cpu)); | |
867 | } | |
868 | } | |
869 | ||
870 | return count; | |
871 | } | |
872 | ||
873 | /* Probe the number and type of interrupts we are able to obtain, and | |
874 | * the resulting numbers of channels and RX queues. | |
875 | */ | |
8ceee660 BH |
876 | static void efx_probe_interrupts(struct efx_nic *efx) |
877 | { | |
46123d04 BH |
878 | int max_channels = |
879 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
880 | int rc, i; |
881 | ||
882 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
883 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
884 | int wanted_ints; | |
28b581ab | 885 | int rx_queues; |
aa6ef27e | 886 | |
46123d04 BH |
887 | /* We want one RX queue and interrupt per CPU package |
888 | * (or as specified by the rss_cpus module parameter). | |
889 | * We will need one channel per interrupt. | |
890 | */ | |
28b581ab NT |
891 | rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); |
892 | wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0); | |
893 | wanted_ints = min(wanted_ints, max_channels); | |
8ceee660 | 894 | |
28b581ab | 895 | for (i = 0; i < wanted_ints; i++) |
8ceee660 | 896 | xentries[i].entry = i; |
28b581ab | 897 | rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints); |
8ceee660 | 898 | if (rc > 0) { |
28b581ab NT |
899 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
900 | " available (%d < %d).\n", rc, wanted_ints); | |
901 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); | |
902 | EFX_BUG_ON_PARANOID(rc >= wanted_ints); | |
903 | wanted_ints = rc; | |
8ceee660 | 904 | rc = pci_enable_msix(efx->pci_dev, xentries, |
28b581ab | 905 | wanted_ints); |
8ceee660 BH |
906 | } |
907 | ||
908 | if (rc == 0) { | |
28b581ab NT |
909 | efx->n_rx_queues = min(rx_queues, wanted_ints); |
910 | efx->n_channels = wanted_ints; | |
911 | for (i = 0; i < wanted_ints; i++) | |
8ceee660 | 912 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
913 | } else { |
914 | /* Fall back to single channel MSI */ | |
915 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
916 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
917 | } | |
918 | } | |
919 | ||
920 | /* Try single interrupt MSI */ | |
921 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 922 | efx->n_rx_queues = 1; |
28b581ab | 923 | efx->n_channels = 1; |
8ceee660 BH |
924 | rc = pci_enable_msi(efx->pci_dev); |
925 | if (rc == 0) { | |
926 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
927 | } else { |
928 | EFX_ERR(efx, "could not enable MSI\n"); | |
929 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
930 | } | |
931 | } | |
932 | ||
933 | /* Assume legacy interrupts */ | |
934 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 935 | efx->n_rx_queues = 1; |
28b581ab | 936 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
8ceee660 BH |
937 | efx->legacy_irq = efx->pci_dev->irq; |
938 | } | |
939 | } | |
940 | ||
941 | static void efx_remove_interrupts(struct efx_nic *efx) | |
942 | { | |
943 | struct efx_channel *channel; | |
944 | ||
945 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 946 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
947 | channel->irq = 0; |
948 | pci_disable_msi(efx->pci_dev); | |
949 | pci_disable_msix(efx->pci_dev); | |
950 | ||
951 | /* Remove legacy interrupt */ | |
952 | efx->legacy_irq = 0; | |
953 | } | |
954 | ||
8831da7b | 955 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
956 | { |
957 | struct efx_tx_queue *tx_queue; | |
958 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 959 | |
60ac1065 | 960 | efx_for_each_tx_queue(tx_queue, efx) { |
28b581ab NT |
961 | if (separate_tx_channels) |
962 | tx_queue->channel = &efx->channel[efx->n_channels-1]; | |
60ac1065 BH |
963 | else |
964 | tx_queue->channel = &efx->channel[0]; | |
965 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
966 | } | |
8ceee660 | 967 | |
8831da7b BH |
968 | efx_for_each_rx_queue(rx_queue, efx) { |
969 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
970 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
971 | } |
972 | } | |
973 | ||
974 | static int efx_probe_nic(struct efx_nic *efx) | |
975 | { | |
976 | int rc; | |
977 | ||
978 | EFX_LOG(efx, "creating NIC\n"); | |
979 | ||
980 | /* Carry out hardware-type specific initialisation */ | |
981 | rc = falcon_probe_nic(efx); | |
982 | if (rc) | |
983 | return rc; | |
984 | ||
985 | /* Determine the number of channels and RX queues by trying to hook | |
986 | * in MSI-X interrupts. */ | |
987 | efx_probe_interrupts(efx); | |
988 | ||
8831da7b | 989 | efx_set_channels(efx); |
8ceee660 BH |
990 | |
991 | /* Initialise the interrupt moderation settings */ | |
992 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec); | |
993 | ||
994 | return 0; | |
995 | } | |
996 | ||
997 | static void efx_remove_nic(struct efx_nic *efx) | |
998 | { | |
999 | EFX_LOG(efx, "destroying NIC\n"); | |
1000 | ||
1001 | efx_remove_interrupts(efx); | |
1002 | falcon_remove_nic(efx); | |
1003 | } | |
1004 | ||
1005 | /************************************************************************** | |
1006 | * | |
1007 | * NIC startup/shutdown | |
1008 | * | |
1009 | *************************************************************************/ | |
1010 | ||
1011 | static int efx_probe_all(struct efx_nic *efx) | |
1012 | { | |
1013 | struct efx_channel *channel; | |
1014 | int rc; | |
1015 | ||
1016 | /* Create NIC */ | |
1017 | rc = efx_probe_nic(efx); | |
1018 | if (rc) { | |
1019 | EFX_ERR(efx, "failed to create NIC\n"); | |
1020 | goto fail1; | |
1021 | } | |
1022 | ||
1023 | /* Create port */ | |
1024 | rc = efx_probe_port(efx); | |
1025 | if (rc) { | |
1026 | EFX_ERR(efx, "failed to create port\n"); | |
1027 | goto fail2; | |
1028 | } | |
1029 | ||
1030 | /* Create channels */ | |
1031 | efx_for_each_channel(channel, efx) { | |
1032 | rc = efx_probe_channel(channel); | |
1033 | if (rc) { | |
1034 | EFX_ERR(efx, "failed to create channel %d\n", | |
1035 | channel->channel); | |
1036 | goto fail3; | |
1037 | } | |
1038 | } | |
56536e9c | 1039 | efx_set_channel_names(efx); |
8ceee660 BH |
1040 | |
1041 | return 0; | |
1042 | ||
1043 | fail3: | |
1044 | efx_for_each_channel(channel, efx) | |
1045 | efx_remove_channel(channel); | |
1046 | efx_remove_port(efx); | |
1047 | fail2: | |
1048 | efx_remove_nic(efx); | |
1049 | fail1: | |
1050 | return rc; | |
1051 | } | |
1052 | ||
1053 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1054 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1055 | * and ensures that the port is scheduled to be reconfigured. | |
1056 | * This function is safe to call multiple times when the NIC is in any | |
1057 | * state. */ | |
1058 | static void efx_start_all(struct efx_nic *efx) | |
1059 | { | |
1060 | struct efx_channel *channel; | |
1061 | ||
1062 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1063 | ||
1064 | /* Check that it is appropriate to restart the interface. All | |
1065 | * of these flags are safe to read under just the rtnl lock */ | |
1066 | if (efx->port_enabled) | |
1067 | return; | |
1068 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1069 | return; | |
55668611 | 1070 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1071 | return; |
1072 | ||
1073 | /* Mark the port as enabled so port reconfigurations can start, then | |
1074 | * restart the transmit interface early so the watchdog timer stops */ | |
1075 | efx_start_port(efx); | |
dacccc74 SH |
1076 | if (efx_dev_registered(efx)) |
1077 | efx_wake_queue(efx); | |
8ceee660 BH |
1078 | |
1079 | efx_for_each_channel(channel, efx) | |
1080 | efx_start_channel(channel); | |
1081 | ||
1082 | falcon_enable_interrupts(efx); | |
1083 | ||
1084 | /* Start hardware monitor if we're in RUNNING */ | |
1085 | if (efx->state == STATE_RUNNING) | |
1086 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1087 | efx_monitor_interval); | |
1088 | } | |
1089 | ||
1090 | /* Flush all delayed work. Should only be called when no more delayed work | |
1091 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1092 | * since we're holding the rtnl_lock at this point. */ | |
1093 | static void efx_flush_all(struct efx_nic *efx) | |
1094 | { | |
1095 | struct efx_rx_queue *rx_queue; | |
1096 | ||
1097 | /* Make sure the hardware monitor is stopped */ | |
1098 | cancel_delayed_work_sync(&efx->monitor_work); | |
1099 | ||
1100 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1101 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1102 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1103 | |
1104 | /* Stop scheduled port reconfigurations */ | |
766ca0fa BH |
1105 | cancel_work_sync(&efx->mac_work); |
1106 | cancel_work_sync(&efx->phy_work); | |
8ceee660 BH |
1107 | |
1108 | } | |
1109 | ||
1110 | /* Quiesce hardware and software without bringing the link down. | |
1111 | * Safe to call multiple times, when the nic and interface is in any | |
1112 | * state. The caller is guaranteed to subsequently be in a position | |
1113 | * to modify any hardware and software state they see fit without | |
1114 | * taking locks. */ | |
1115 | static void efx_stop_all(struct efx_nic *efx) | |
1116 | { | |
1117 | struct efx_channel *channel; | |
1118 | ||
1119 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1120 | ||
1121 | /* port_enabled can be read safely under the rtnl lock */ | |
1122 | if (!efx->port_enabled) | |
1123 | return; | |
1124 | ||
1125 | /* Disable interrupts and wait for ISR to complete */ | |
1126 | falcon_disable_interrupts(efx); | |
1127 | if (efx->legacy_irq) | |
1128 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1129 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1130 | if (channel->irq) |
1131 | synchronize_irq(channel->irq); | |
b3475645 | 1132 | } |
8ceee660 BH |
1133 | |
1134 | /* Stop all NAPI processing and synchronous rx refills */ | |
1135 | efx_for_each_channel(channel, efx) | |
1136 | efx_stop_channel(channel); | |
1137 | ||
1138 | /* Stop all asynchronous port reconfigurations. Since all | |
1139 | * event processing has already been stopped, there is no | |
1140 | * window to loose phy events */ | |
1141 | efx_stop_port(efx); | |
1142 | ||
766ca0fa | 1143 | /* Flush efx_phy_work, efx_mac_work, refill_workqueue, monitor_work */ |
8ceee660 BH |
1144 | efx_flush_all(efx); |
1145 | ||
1146 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1147 | * flushes will complete in a timely fashion. */ | |
8ceee660 BH |
1148 | falcon_drain_tx_fifo(efx); |
1149 | ||
1150 | /* Stop the kernel transmit interface late, so the watchdog | |
1151 | * timer isn't ticking over the flush */ | |
55668611 | 1152 | if (efx_dev_registered(efx)) { |
dacccc74 | 1153 | efx_stop_queue(efx); |
8ceee660 BH |
1154 | netif_tx_lock_bh(efx->net_dev); |
1155 | netif_tx_unlock_bh(efx->net_dev); | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | static void efx_remove_all(struct efx_nic *efx) | |
1160 | { | |
1161 | struct efx_channel *channel; | |
1162 | ||
1163 | efx_for_each_channel(channel, efx) | |
1164 | efx_remove_channel(channel); | |
1165 | efx_remove_port(efx); | |
1166 | efx_remove_nic(efx); | |
1167 | } | |
1168 | ||
1169 | /* A convinience function to safely flush all the queues */ | |
bc3c90a2 | 1170 | void efx_flush_queues(struct efx_nic *efx) |
8ceee660 | 1171 | { |
8ceee660 BH |
1172 | EFX_ASSERT_RESET_SERIALISED(efx); |
1173 | ||
1174 | efx_stop_all(efx); | |
1175 | ||
1176 | efx_fini_channels(efx); | |
bc3c90a2 | 1177 | efx_init_channels(efx); |
8ceee660 BH |
1178 | |
1179 | efx_start_all(efx); | |
8ceee660 BH |
1180 | } |
1181 | ||
1182 | /************************************************************************** | |
1183 | * | |
1184 | * Interrupt moderation | |
1185 | * | |
1186 | **************************************************************************/ | |
1187 | ||
1188 | /* Set interrupt moderation parameters */ | |
1189 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs) | |
1190 | { | |
1191 | struct efx_tx_queue *tx_queue; | |
1192 | struct efx_rx_queue *rx_queue; | |
1193 | ||
1194 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1195 | ||
1196 | efx_for_each_tx_queue(tx_queue, efx) | |
1197 | tx_queue->channel->irq_moderation = tx_usecs; | |
1198 | ||
1199 | efx_for_each_rx_queue(rx_queue, efx) | |
1200 | rx_queue->channel->irq_moderation = rx_usecs; | |
1201 | } | |
1202 | ||
1203 | /************************************************************************** | |
1204 | * | |
1205 | * Hardware monitor | |
1206 | * | |
1207 | **************************************************************************/ | |
1208 | ||
1209 | /* Run periodically off the general workqueue. Serialised against | |
1210 | * efx_reconfigure_port via the mac_lock */ | |
1211 | static void efx_monitor(struct work_struct *data) | |
1212 | { | |
1213 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1214 | monitor_work.work); | |
766ca0fa | 1215 | int rc; |
8ceee660 BH |
1216 | |
1217 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1218 | raw_smp_processor_id()); | |
1219 | ||
8ceee660 BH |
1220 | /* If the mac_lock is already held then it is likely a port |
1221 | * reconfiguration is already in place, which will likely do | |
1222 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1223 | if (!mutex_trylock(&efx->mac_lock)) |
1224 | goto out_requeue; | |
1225 | if (!efx->port_enabled) | |
1226 | goto out_unlock; | |
1227 | rc = efx->board_info.monitor(efx); | |
1228 | if (rc) { | |
1229 | EFX_ERR(efx, "Board sensor %s; shutting down PHY\n", | |
1230 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
1231 | efx->phy_mode |= PHY_MODE_LOW_POWER; | |
1232 | falcon_sim_phy_event(efx); | |
8ceee660 | 1233 | } |
766ca0fa BH |
1234 | efx->phy_op->poll(efx); |
1235 | efx->mac_op->poll(efx); | |
8ceee660 | 1236 | |
766ca0fa | 1237 | out_unlock: |
8ceee660 | 1238 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1239 | out_requeue: |
8ceee660 BH |
1240 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1241 | efx_monitor_interval); | |
1242 | } | |
1243 | ||
1244 | /************************************************************************** | |
1245 | * | |
1246 | * ioctls | |
1247 | * | |
1248 | *************************************************************************/ | |
1249 | ||
1250 | /* Net device ioctl | |
1251 | * Context: process, rtnl_lock() held. | |
1252 | */ | |
1253 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1254 | { | |
767e468c | 1255 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1256 | |
1257 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1258 | ||
1259 | return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL); | |
1260 | } | |
1261 | ||
1262 | /************************************************************************** | |
1263 | * | |
1264 | * NAPI interface | |
1265 | * | |
1266 | **************************************************************************/ | |
1267 | ||
1268 | static int efx_init_napi(struct efx_nic *efx) | |
1269 | { | |
1270 | struct efx_channel *channel; | |
8ceee660 BH |
1271 | |
1272 | efx_for_each_channel(channel, efx) { | |
1273 | channel->napi_dev = efx->net_dev; | |
8ceee660 BH |
1274 | } |
1275 | return 0; | |
8ceee660 BH |
1276 | } |
1277 | ||
1278 | static void efx_fini_napi(struct efx_nic *efx) | |
1279 | { | |
1280 | struct efx_channel *channel; | |
1281 | ||
1282 | efx_for_each_channel(channel, efx) { | |
8ceee660 BH |
1283 | channel->napi_dev = NULL; |
1284 | } | |
1285 | } | |
1286 | ||
1287 | /************************************************************************** | |
1288 | * | |
1289 | * Kernel netpoll interface | |
1290 | * | |
1291 | *************************************************************************/ | |
1292 | ||
1293 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1294 | ||
1295 | /* Although in the common case interrupts will be disabled, this is not | |
1296 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1297 | * so no locking is required. | |
1298 | */ | |
1299 | static void efx_netpoll(struct net_device *net_dev) | |
1300 | { | |
767e468c | 1301 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1302 | struct efx_channel *channel; |
1303 | ||
64ee3120 | 1304 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1305 | efx_schedule_channel(channel); |
1306 | } | |
1307 | ||
1308 | #endif | |
1309 | ||
1310 | /************************************************************************** | |
1311 | * | |
1312 | * Kernel net device interface | |
1313 | * | |
1314 | *************************************************************************/ | |
1315 | ||
1316 | /* Context: process, rtnl_lock() held. */ | |
1317 | static int efx_net_open(struct net_device *net_dev) | |
1318 | { | |
767e468c | 1319 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1320 | EFX_ASSERT_RESET_SERIALISED(efx); |
1321 | ||
1322 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1323 | raw_smp_processor_id()); | |
1324 | ||
f4bd954e BH |
1325 | if (efx->state == STATE_DISABLED) |
1326 | return -EIO; | |
f8b87c17 BH |
1327 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1328 | return -EBUSY; | |
1329 | ||
8ceee660 BH |
1330 | efx_start_all(efx); |
1331 | return 0; | |
1332 | } | |
1333 | ||
1334 | /* Context: process, rtnl_lock() held. | |
1335 | * Note that the kernel will ignore our return code; this method | |
1336 | * should really be a void. | |
1337 | */ | |
1338 | static int efx_net_stop(struct net_device *net_dev) | |
1339 | { | |
767e468c | 1340 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1341 | |
1342 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1343 | raw_smp_processor_id()); | |
1344 | ||
f4bd954e BH |
1345 | if (efx->state != STATE_DISABLED) { |
1346 | /* Stop the device and flush all the channels */ | |
1347 | efx_stop_all(efx); | |
1348 | efx_fini_channels(efx); | |
1349 | efx_init_channels(efx); | |
1350 | } | |
8ceee660 BH |
1351 | |
1352 | return 0; | |
1353 | } | |
1354 | ||
1974cc20 BH |
1355 | void efx_stats_disable(struct efx_nic *efx) |
1356 | { | |
1357 | spin_lock(&efx->stats_lock); | |
1358 | ++efx->stats_disable_count; | |
1359 | spin_unlock(&efx->stats_lock); | |
1360 | } | |
1361 | ||
1362 | void efx_stats_enable(struct efx_nic *efx) | |
1363 | { | |
1364 | spin_lock(&efx->stats_lock); | |
1365 | --efx->stats_disable_count; | |
1366 | spin_unlock(&efx->stats_lock); | |
1367 | } | |
1368 | ||
5b9e207c | 1369 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1370 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1371 | { | |
767e468c | 1372 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1373 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1374 | struct net_device_stats *stats = &net_dev->stats; | |
1375 | ||
5b9e207c | 1376 | /* Update stats if possible, but do not wait if another thread |
1974cc20 BH |
1377 | * is updating them or if MAC stats fetches are temporarily |
1378 | * disabled; slightly stale stats are acceptable. | |
5b9e207c | 1379 | */ |
8ceee660 BH |
1380 | if (!spin_trylock(&efx->stats_lock)) |
1381 | return stats; | |
1974cc20 | 1382 | if (!efx->stats_disable_count) { |
177dfcd8 | 1383 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1384 | falcon_update_nic_stats(efx); |
1385 | } | |
1386 | spin_unlock(&efx->stats_lock); | |
1387 | ||
1388 | stats->rx_packets = mac_stats->rx_packets; | |
1389 | stats->tx_packets = mac_stats->tx_packets; | |
1390 | stats->rx_bytes = mac_stats->rx_bytes; | |
1391 | stats->tx_bytes = mac_stats->tx_bytes; | |
1392 | stats->multicast = mac_stats->rx_multicast; | |
1393 | stats->collisions = mac_stats->tx_collision; | |
1394 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1395 | mac_stats->rx_length_error); | |
1396 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1397 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1398 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1399 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1400 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1401 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1402 | ||
1403 | stats->rx_errors = (stats->rx_length_errors + | |
1404 | stats->rx_over_errors + | |
1405 | stats->rx_crc_errors + | |
1406 | stats->rx_frame_errors + | |
1407 | stats->rx_fifo_errors + | |
1408 | stats->rx_missed_errors + | |
1409 | mac_stats->rx_symbol_error); | |
1410 | stats->tx_errors = (stats->tx_window_errors + | |
1411 | mac_stats->tx_bad); | |
1412 | ||
1413 | return stats; | |
1414 | } | |
1415 | ||
1416 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1417 | static void efx_watchdog(struct net_device *net_dev) | |
1418 | { | |
767e468c | 1419 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1420 | |
739bb23d BH |
1421 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:" |
1422 | " resetting channels\n", | |
1423 | atomic_read(&efx->netif_stop_count), efx->port_enabled); | |
8ceee660 | 1424 | |
739bb23d | 1425 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1426 | } |
1427 | ||
1428 | ||
1429 | /* Context: process, rtnl_lock() held. */ | |
1430 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1431 | { | |
767e468c | 1432 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1433 | int rc = 0; |
1434 | ||
1435 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1436 | ||
1437 | if (new_mtu > EFX_MAX_MTU) | |
1438 | return -EINVAL; | |
1439 | ||
1440 | efx_stop_all(efx); | |
1441 | ||
1442 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1443 | ||
1444 | efx_fini_channels(efx); | |
1445 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1446 | efx_init_channels(efx); |
8ceee660 BH |
1447 | |
1448 | efx_start_all(efx); | |
1449 | return rc; | |
8ceee660 BH |
1450 | } |
1451 | ||
1452 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1453 | { | |
767e468c | 1454 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1455 | struct sockaddr *addr = data; |
1456 | char *new_addr = addr->sa_data; | |
1457 | ||
1458 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1459 | ||
1460 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1461 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1462 | new_addr); | |
8ceee660 BH |
1463 | return -EINVAL; |
1464 | } | |
1465 | ||
1466 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1467 | ||
1468 | /* Reconfigure the MAC */ | |
1469 | efx_reconfigure_port(efx); | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
a816f75a | 1474 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1475 | static void efx_set_multicast_list(struct net_device *net_dev) |
1476 | { | |
767e468c | 1477 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1478 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1479 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
a816f75a BH |
1480 | bool promiscuous = !!(net_dev->flags & IFF_PROMISC); |
1481 | bool changed = (efx->promiscuous != promiscuous); | |
8ceee660 BH |
1482 | u32 crc; |
1483 | int bit; | |
1484 | int i; | |
1485 | ||
a816f75a | 1486 | efx->promiscuous = promiscuous; |
8ceee660 BH |
1487 | |
1488 | /* Build multicast hash table */ | |
1489 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1490 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1491 | } else { | |
1492 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1493 | for (i = 0; i < net_dev->mc_count; i++) { | |
1494 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1495 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1496 | set_bit_le(bit, mc_hash->byte); | |
1497 | mc_list = mc_list->next; | |
1498 | } | |
1499 | } | |
1500 | ||
a816f75a BH |
1501 | if (!efx->port_enabled) |
1502 | /* Delay pushing settings until efx_start_port() */ | |
1503 | return; | |
1504 | ||
1505 | if (changed) | |
766ca0fa | 1506 | queue_work(efx->workqueue, &efx->phy_work); |
a816f75a | 1507 | |
8ceee660 BH |
1508 | /* Create and activate new global multicast hash table */ |
1509 | falcon_set_multicast_hash(efx); | |
1510 | } | |
1511 | ||
c3ecb9f3 SH |
1512 | static const struct net_device_ops efx_netdev_ops = { |
1513 | .ndo_open = efx_net_open, | |
1514 | .ndo_stop = efx_net_stop, | |
1515 | .ndo_get_stats = efx_net_stats, | |
1516 | .ndo_tx_timeout = efx_watchdog, | |
1517 | .ndo_start_xmit = efx_hard_start_xmit, | |
1518 | .ndo_validate_addr = eth_validate_addr, | |
1519 | .ndo_do_ioctl = efx_ioctl, | |
1520 | .ndo_change_mtu = efx_change_mtu, | |
1521 | .ndo_set_mac_address = efx_set_mac_address, | |
1522 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1523 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1524 | .ndo_poll_controller = efx_netpoll, | |
1525 | #endif | |
1526 | }; | |
1527 | ||
7dde596e BH |
1528 | static void efx_update_name(struct efx_nic *efx) |
1529 | { | |
1530 | strcpy(efx->name, efx->net_dev->name); | |
1531 | efx_mtd_rename(efx); | |
1532 | efx_set_channel_names(efx); | |
1533 | } | |
1534 | ||
8ceee660 BH |
1535 | static int efx_netdev_event(struct notifier_block *this, |
1536 | unsigned long event, void *ptr) | |
1537 | { | |
d3208b5e | 1538 | struct net_device *net_dev = ptr; |
8ceee660 | 1539 | |
7dde596e BH |
1540 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1541 | event == NETDEV_CHANGENAME) | |
1542 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1543 | |
1544 | return NOTIFY_DONE; | |
1545 | } | |
1546 | ||
1547 | static struct notifier_block efx_netdev_notifier = { | |
1548 | .notifier_call = efx_netdev_event, | |
1549 | }; | |
1550 | ||
06d5e193 BH |
1551 | static ssize_t |
1552 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1553 | { | |
1554 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1555 | return sprintf(buf, "%d\n", efx->phy_type); | |
1556 | } | |
1557 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1558 | ||
8ceee660 BH |
1559 | static int efx_register_netdev(struct efx_nic *efx) |
1560 | { | |
1561 | struct net_device *net_dev = efx->net_dev; | |
1562 | int rc; | |
1563 | ||
1564 | net_dev->watchdog_timeo = 5 * HZ; | |
1565 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1566 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1567 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1568 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1569 | ||
1570 | /* Always start with carrier off; PHY events will detect the link */ | |
1571 | netif_carrier_off(efx->net_dev); | |
1572 | ||
1573 | /* Clear MAC statistics */ | |
177dfcd8 | 1574 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1575 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1576 | ||
1577 | rc = register_netdev(net_dev); | |
1578 | if (rc) { | |
1579 | EFX_ERR(efx, "could not register net dev\n"); | |
1580 | return rc; | |
1581 | } | |
7dde596e BH |
1582 | |
1583 | rtnl_lock(); | |
1584 | efx_update_name(efx); | |
1585 | rtnl_unlock(); | |
8ceee660 | 1586 | |
06d5e193 BH |
1587 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1588 | if (rc) { | |
1589 | EFX_ERR(efx, "failed to init net dev attributes\n"); | |
1590 | goto fail_registered; | |
1591 | } | |
1592 | ||
8ceee660 | 1593 | return 0; |
06d5e193 BH |
1594 | |
1595 | fail_registered: | |
1596 | unregister_netdev(net_dev); | |
1597 | return rc; | |
8ceee660 BH |
1598 | } |
1599 | ||
1600 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1601 | { | |
1602 | struct efx_tx_queue *tx_queue; | |
1603 | ||
1604 | if (!efx->net_dev) | |
1605 | return; | |
1606 | ||
767e468c | 1607 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1608 | |
1609 | /* Free up any skbs still remaining. This has to happen before | |
1610 | * we try to unregister the netdev as running their destructors | |
1611 | * may be needed to get the device ref. count to 0. */ | |
1612 | efx_for_each_tx_queue(tx_queue, efx) | |
1613 | efx_release_tx_buffers(tx_queue); | |
1614 | ||
55668611 | 1615 | if (efx_dev_registered(efx)) { |
8ceee660 | 1616 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1617 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1618 | unregister_netdev(efx->net_dev); |
1619 | } | |
1620 | } | |
1621 | ||
1622 | /************************************************************************** | |
1623 | * | |
1624 | * Device reset and suspend | |
1625 | * | |
1626 | **************************************************************************/ | |
1627 | ||
2467ca46 BH |
1628 | /* Tears down the entire software state and most of the hardware state |
1629 | * before reset. */ | |
4b988280 SH |
1630 | void efx_reset_down(struct efx_nic *efx, enum reset_type method, |
1631 | struct ethtool_cmd *ecmd) | |
8ceee660 | 1632 | { |
8ceee660 BH |
1633 | EFX_ASSERT_RESET_SERIALISED(efx); |
1634 | ||
1974cc20 | 1635 | efx_stats_disable(efx); |
2467ca46 BH |
1636 | efx_stop_all(efx); |
1637 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1638 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1639 | |
177dfcd8 | 1640 | efx->phy_op->get_settings(efx, ecmd); |
8ceee660 BH |
1641 | |
1642 | efx_fini_channels(efx); | |
4b988280 SH |
1643 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1644 | efx->phy_op->fini(efx); | |
8ceee660 BH |
1645 | } |
1646 | ||
2467ca46 BH |
1647 | /* This function will always ensure that the locks acquired in |
1648 | * efx_reset_down() are released. A failure return code indicates | |
1649 | * that we were unable to reinitialise the hardware, and the | |
1650 | * driver should be disabled. If ok is false, then the rx and tx | |
1651 | * engines are not restarted, pending a RESET_DISABLE. */ | |
4b988280 SH |
1652 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, |
1653 | struct ethtool_cmd *ecmd, bool ok) | |
8ceee660 BH |
1654 | { |
1655 | int rc; | |
1656 | ||
2467ca46 | 1657 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1658 | |
2467ca46 | 1659 | rc = falcon_init_nic(efx); |
8ceee660 | 1660 | if (rc) { |
2467ca46 BH |
1661 | EFX_ERR(efx, "failed to initialise NIC\n"); |
1662 | ok = false; | |
8ceee660 BH |
1663 | } |
1664 | ||
4b988280 SH |
1665 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
1666 | if (ok) { | |
1667 | rc = efx->phy_op->init(efx); | |
1668 | if (rc) | |
1669 | ok = false; | |
1670 | } else | |
1671 | efx->port_initialized = false; | |
1672 | } | |
1673 | ||
2467ca46 BH |
1674 | if (ok) { |
1675 | efx_init_channels(efx); | |
8ceee660 | 1676 | |
177dfcd8 | 1677 | if (efx->phy_op->set_settings(efx, ecmd)) |
2467ca46 BH |
1678 | EFX_ERR(efx, "could not restore PHY settings\n"); |
1679 | } | |
1680 | ||
f4150724 | 1681 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1682 | mutex_unlock(&efx->mac_lock); |
1683 | ||
8c8661e4 | 1684 | if (ok) { |
2467ca46 | 1685 | efx_start_all(efx); |
1974cc20 | 1686 | efx_stats_enable(efx); |
8c8661e4 | 1687 | } |
8ceee660 BH |
1688 | return rc; |
1689 | } | |
1690 | ||
1691 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1692 | * Note that the reset may fail, in which case the card will be left | |
1693 | * in a most-probably-unusable state. | |
1694 | * | |
1695 | * This function will sleep. You cannot reset from within an atomic | |
1696 | * state; use efx_schedule_reset() instead. | |
1697 | * | |
1698 | * Grabs the rtnl_lock. | |
1699 | */ | |
1700 | static int efx_reset(struct efx_nic *efx) | |
1701 | { | |
1702 | struct ethtool_cmd ecmd; | |
1703 | enum reset_type method = efx->reset_pending; | |
f4bd954e | 1704 | int rc = 0; |
8ceee660 BH |
1705 | |
1706 | /* Serialise with kernel interfaces */ | |
1707 | rtnl_lock(); | |
1708 | ||
1709 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1710 | * flag set so that efx_pci_probe_main will be retried */ | |
1711 | if (efx->state != STATE_RUNNING) { | |
1712 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
f4bd954e | 1713 | goto out_unlock; |
8ceee660 BH |
1714 | } |
1715 | ||
8ceee660 BH |
1716 | EFX_INFO(efx, "resetting (%d)\n", method); |
1717 | ||
4b988280 | 1718 | efx_reset_down(efx, method, &ecmd); |
8ceee660 BH |
1719 | |
1720 | rc = falcon_reset_hw(efx, method); | |
1721 | if (rc) { | |
1722 | EFX_ERR(efx, "failed to reset hardware\n"); | |
f4bd954e | 1723 | goto out_disable; |
8ceee660 BH |
1724 | } |
1725 | ||
1726 | /* Allow resets to be rescheduled. */ | |
1727 | efx->reset_pending = RESET_TYPE_NONE; | |
1728 | ||
1729 | /* Reinitialise bus-mastering, which may have been turned off before | |
1730 | * the reset was scheduled. This is still appropriate, even in the | |
1731 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1732 | * can respond to requests. */ | |
1733 | pci_set_master(efx->pci_dev); | |
1734 | ||
8ceee660 BH |
1735 | /* Leave device stopped if necessary */ |
1736 | if (method == RESET_TYPE_DISABLE) { | |
4b988280 | 1737 | efx_reset_up(efx, method, &ecmd, false); |
8ceee660 | 1738 | rc = -EIO; |
f4bd954e | 1739 | } else { |
4b988280 | 1740 | rc = efx_reset_up(efx, method, &ecmd, true); |
8ceee660 BH |
1741 | } |
1742 | ||
f4bd954e BH |
1743 | out_disable: |
1744 | if (rc) { | |
1745 | EFX_ERR(efx, "has been disabled\n"); | |
1746 | efx->state = STATE_DISABLED; | |
1747 | dev_close(efx->net_dev); | |
1748 | } else { | |
1749 | EFX_LOG(efx, "reset complete\n"); | |
1750 | } | |
8ceee660 | 1751 | |
f4bd954e | 1752 | out_unlock: |
8ceee660 | 1753 | rtnl_unlock(); |
8ceee660 BH |
1754 | return rc; |
1755 | } | |
1756 | ||
1757 | /* The worker thread exists so that code that cannot sleep can | |
1758 | * schedule a reset for later. | |
1759 | */ | |
1760 | static void efx_reset_work(struct work_struct *data) | |
1761 | { | |
1762 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1763 | ||
1764 | efx_reset(nic); | |
1765 | } | |
1766 | ||
1767 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1768 | { | |
1769 | enum reset_type method; | |
1770 | ||
1771 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1772 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1773 | return; | |
1774 | } | |
1775 | ||
1776 | switch (type) { | |
1777 | case RESET_TYPE_INVISIBLE: | |
1778 | case RESET_TYPE_ALL: | |
1779 | case RESET_TYPE_WORLD: | |
1780 | case RESET_TYPE_DISABLE: | |
1781 | method = type; | |
1782 | break; | |
1783 | case RESET_TYPE_RX_RECOVERY: | |
1784 | case RESET_TYPE_RX_DESC_FETCH: | |
1785 | case RESET_TYPE_TX_DESC_FETCH: | |
1786 | case RESET_TYPE_TX_SKIP: | |
1787 | method = RESET_TYPE_INVISIBLE; | |
1788 | break; | |
1789 | default: | |
1790 | method = RESET_TYPE_ALL; | |
1791 | break; | |
1792 | } | |
1793 | ||
1794 | if (method != type) | |
1795 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1796 | else | |
1797 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1798 | ||
1799 | efx->reset_pending = method; | |
1800 | ||
1ab00629 | 1801 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1802 | } |
1803 | ||
1804 | /************************************************************************** | |
1805 | * | |
1806 | * List of NICs we support | |
1807 | * | |
1808 | **************************************************************************/ | |
1809 | ||
1810 | /* PCI device ID table */ | |
1811 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1812 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1813 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1814 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1815 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1816 | {0} /* end of list */ | |
1817 | }; | |
1818 | ||
1819 | /************************************************************************** | |
1820 | * | |
1821 | * Dummy PHY/MAC/Board operations | |
1822 | * | |
01aad7b6 | 1823 | * Can be used for some unimplemented operations |
8ceee660 BH |
1824 | * Needed so all function pointers are valid and do not have to be tested |
1825 | * before use | |
1826 | * | |
1827 | **************************************************************************/ | |
1828 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1829 | { | |
1830 | return 0; | |
1831 | } | |
1832 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
dc8cfa55 | 1833 | void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {} |
8ceee660 | 1834 | |
177dfcd8 BH |
1835 | static struct efx_mac_operations efx_dummy_mac_operations = { |
1836 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa BH |
1837 | .poll = efx_port_dummy_op_void, |
1838 | .irq = efx_port_dummy_op_void, | |
177dfcd8 BH |
1839 | }; |
1840 | ||
8ceee660 BH |
1841 | static struct efx_phy_operations efx_dummy_phy_operations = { |
1842 | .init = efx_port_dummy_op_int, | |
1843 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa | 1844 | .poll = efx_port_dummy_op_void, |
8ceee660 BH |
1845 | .fini = efx_port_dummy_op_void, |
1846 | .clear_interrupt = efx_port_dummy_op_void, | |
8ceee660 BH |
1847 | }; |
1848 | ||
8ceee660 | 1849 | static struct efx_board efx_dummy_board_info = { |
01aad7b6 | 1850 | .init = efx_port_dummy_op_int, |
8129d217 BH |
1851 | .init_leds = efx_port_dummy_op_void, |
1852 | .set_id_led = efx_port_dummy_op_blink, | |
a17102b1 | 1853 | .monitor = efx_port_dummy_op_int, |
01aad7b6 BH |
1854 | .blink = efx_port_dummy_op_blink, |
1855 | .fini = efx_port_dummy_op_void, | |
8ceee660 BH |
1856 | }; |
1857 | ||
1858 | /************************************************************************** | |
1859 | * | |
1860 | * Data housekeeping | |
1861 | * | |
1862 | **************************************************************************/ | |
1863 | ||
1864 | /* This zeroes out and then fills in the invariants in a struct | |
1865 | * efx_nic (including all sub-structures). | |
1866 | */ | |
1867 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1868 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1869 | { | |
1870 | struct efx_channel *channel; | |
1871 | struct efx_tx_queue *tx_queue; | |
1872 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1873 | int i; |
8ceee660 BH |
1874 | |
1875 | /* Initialise common structures */ | |
1876 | memset(efx, 0, sizeof(*efx)); | |
1877 | spin_lock_init(&efx->biu_lock); | |
1878 | spin_lock_init(&efx->phy_lock); | |
f4150724 | 1879 | mutex_init(&efx->spi_lock); |
8ceee660 BH |
1880 | INIT_WORK(&efx->reset_work, efx_reset_work); |
1881 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1882 | efx->pci_dev = pci_dev; | |
1883 | efx->state = STATE_INIT; | |
1884 | efx->reset_pending = RESET_TYPE_NONE; | |
1885 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
1886 | efx->board_info = efx_dummy_board_info; | |
1887 | ||
1888 | efx->net_dev = net_dev; | |
dc8cfa55 | 1889 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1890 | spin_lock_init(&efx->netif_stop_lock); |
1891 | spin_lock_init(&efx->stats_lock); | |
1974cc20 | 1892 | efx->stats_disable_count = 1; |
8ceee660 | 1893 | mutex_init(&efx->mac_lock); |
177dfcd8 | 1894 | efx->mac_op = &efx_dummy_mac_operations; |
8ceee660 BH |
1895 | efx->phy_op = &efx_dummy_phy_operations; |
1896 | efx->mii.dev = net_dev; | |
766ca0fa BH |
1897 | INIT_WORK(&efx->phy_work, efx_phy_work); |
1898 | INIT_WORK(&efx->mac_work, efx_mac_work); | |
8ceee660 BH |
1899 | atomic_set(&efx->netif_stop_count, 1); |
1900 | ||
1901 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1902 | channel = &efx->channel[i]; | |
1903 | channel->efx = efx; | |
1904 | channel->channel = i; | |
dc8cfa55 | 1905 | channel->work_pending = false; |
8ceee660 | 1906 | } |
60ac1065 | 1907 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1908 | tx_queue = &efx->tx_queue[i]; |
1909 | tx_queue->efx = efx; | |
1910 | tx_queue->queue = i; | |
1911 | tx_queue->buffer = NULL; | |
1912 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1913 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1914 | } |
1915 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1916 | rx_queue = &efx->rx_queue[i]; | |
1917 | rx_queue->efx = efx; | |
1918 | rx_queue->queue = i; | |
1919 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1920 | rx_queue->buffer = NULL; | |
1921 | spin_lock_init(&rx_queue->add_lock); | |
1922 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1923 | } | |
1924 | ||
1925 | efx->type = type; | |
1926 | ||
1927 | /* Sanity-check NIC type */ | |
1928 | EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask & | |
1929 | (efx->type->txd_ring_mask + 1)); | |
1930 | EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask & | |
1931 | (efx->type->rxd_ring_mask + 1)); | |
1932 | EFX_BUG_ON_PARANOID(efx->type->evq_size & | |
1933 | (efx->type->evq_size - 1)); | |
1934 | /* As close as we can get to guaranteeing that we don't overflow */ | |
1935 | EFX_BUG_ON_PARANOID(efx->type->evq_size < | |
1936 | (efx->type->txd_ring_mask + 1 + | |
1937 | efx->type->rxd_ring_mask + 1)); | |
1938 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); | |
1939 | ||
1940 | /* Higher numbered interrupt modes are less capable! */ | |
1941 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1942 | interrupt_mode); | |
1943 | ||
6977dc63 BH |
1944 | /* Would be good to use the net_dev name, but we're too early */ |
1945 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
1946 | pci_name(pci_dev)); | |
1947 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
1948 | if (!efx->workqueue) |
1949 | return -ENOMEM; | |
8d9853d9 | 1950 | |
8ceee660 | 1951 | return 0; |
8ceee660 BH |
1952 | } |
1953 | ||
1954 | static void efx_fini_struct(struct efx_nic *efx) | |
1955 | { | |
1956 | if (efx->workqueue) { | |
1957 | destroy_workqueue(efx->workqueue); | |
1958 | efx->workqueue = NULL; | |
1959 | } | |
1960 | } | |
1961 | ||
1962 | /************************************************************************** | |
1963 | * | |
1964 | * PCI interface | |
1965 | * | |
1966 | **************************************************************************/ | |
1967 | ||
1968 | /* Main body of final NIC shutdown code | |
1969 | * This is called only at module unload (or hotplug removal). | |
1970 | */ | |
1971 | static void efx_pci_remove_main(struct efx_nic *efx) | |
1972 | { | |
1973 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1974 | ||
1975 | /* Skip everything if we never obtained a valid membase */ | |
1976 | if (!efx->membase) | |
1977 | return; | |
1978 | ||
1979 | efx_fini_channels(efx); | |
1980 | efx_fini_port(efx); | |
1981 | ||
1982 | /* Shutdown the board, then the NIC and board state */ | |
37b5a603 | 1983 | efx->board_info.fini(efx); |
8ceee660 BH |
1984 | falcon_fini_interrupt(efx); |
1985 | ||
1986 | efx_fini_napi(efx); | |
1987 | efx_remove_all(efx); | |
1988 | } | |
1989 | ||
1990 | /* Final NIC shutdown | |
1991 | * This is called only at module unload (or hotplug removal). | |
1992 | */ | |
1993 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
1994 | { | |
1995 | struct efx_nic *efx; | |
1996 | ||
1997 | efx = pci_get_drvdata(pci_dev); | |
1998 | if (!efx) | |
1999 | return; | |
2000 | ||
2001 | /* Mark the NIC as fini, then stop the interface */ | |
2002 | rtnl_lock(); | |
2003 | efx->state = STATE_FINI; | |
2004 | dev_close(efx->net_dev); | |
2005 | ||
2006 | /* Allow any queued efx_resets() to complete */ | |
2007 | rtnl_unlock(); | |
2008 | ||
2009 | if (efx->membase == NULL) | |
2010 | goto out; | |
2011 | ||
2012 | efx_unregister_netdev(efx); | |
2013 | ||
7dde596e BH |
2014 | efx_mtd_remove(efx); |
2015 | ||
8ceee660 BH |
2016 | /* Wait for any scheduled resets to complete. No more will be |
2017 | * scheduled from this point because efx_stop_all() has been | |
2018 | * called, we are no longer registered with driverlink, and | |
2019 | * the net_device's have been removed. */ | |
1ab00629 | 2020 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2021 | |
2022 | efx_pci_remove_main(efx); | |
2023 | ||
2024 | out: | |
2025 | efx_fini_io(efx); | |
2026 | EFX_LOG(efx, "shutdown successful\n"); | |
2027 | ||
2028 | pci_set_drvdata(pci_dev, NULL); | |
2029 | efx_fini_struct(efx); | |
2030 | free_netdev(efx->net_dev); | |
2031 | }; | |
2032 | ||
2033 | /* Main body of NIC initialisation | |
2034 | * This is called at module load (or hotplug insertion, theoretically). | |
2035 | */ | |
2036 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2037 | { | |
2038 | int rc; | |
2039 | ||
2040 | /* Do start-of-day initialisation */ | |
2041 | rc = efx_probe_all(efx); | |
2042 | if (rc) | |
2043 | goto fail1; | |
2044 | ||
2045 | rc = efx_init_napi(efx); | |
2046 | if (rc) | |
2047 | goto fail2; | |
2048 | ||
2049 | /* Initialise the board */ | |
2050 | rc = efx->board_info.init(efx); | |
2051 | if (rc) { | |
2052 | EFX_ERR(efx, "failed to initialise board\n"); | |
2053 | goto fail3; | |
2054 | } | |
2055 | ||
2056 | rc = falcon_init_nic(efx); | |
2057 | if (rc) { | |
2058 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
2059 | goto fail4; | |
2060 | } | |
2061 | ||
2062 | rc = efx_init_port(efx); | |
2063 | if (rc) { | |
2064 | EFX_ERR(efx, "failed to initialise port\n"); | |
2065 | goto fail5; | |
2066 | } | |
2067 | ||
bc3c90a2 | 2068 | efx_init_channels(efx); |
8ceee660 BH |
2069 | |
2070 | rc = falcon_init_interrupt(efx); | |
2071 | if (rc) | |
bc3c90a2 | 2072 | goto fail6; |
8ceee660 BH |
2073 | |
2074 | return 0; | |
2075 | ||
8ceee660 | 2076 | fail6: |
bc3c90a2 | 2077 | efx_fini_channels(efx); |
8ceee660 BH |
2078 | efx_fini_port(efx); |
2079 | fail5: | |
2080 | fail4: | |
a17102b1 | 2081 | efx->board_info.fini(efx); |
8ceee660 BH |
2082 | fail3: |
2083 | efx_fini_napi(efx); | |
2084 | fail2: | |
2085 | efx_remove_all(efx); | |
2086 | fail1: | |
2087 | return rc; | |
2088 | } | |
2089 | ||
2090 | /* NIC initialisation | |
2091 | * | |
2092 | * This is called at module load (or hotplug insertion, | |
2093 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2094 | * sets up and registers the network devices with the kernel and hooks | |
2095 | * the interrupt service routine. It does not prepare the device for | |
2096 | * transmission; this is left to the first time one of the network | |
2097 | * interfaces is brought up (i.e. efx_net_open). | |
2098 | */ | |
2099 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2100 | const struct pci_device_id *entry) | |
2101 | { | |
2102 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2103 | struct net_device *net_dev; | |
2104 | struct efx_nic *efx; | |
2105 | int i, rc; | |
2106 | ||
2107 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2108 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2109 | if (!net_dev) | |
2110 | return -ENOMEM; | |
b9b39b62 BH |
2111 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
2112 | NETIF_F_HIGHDMA | NETIF_F_TSO); | |
8ceee660 | 2113 | if (lro) |
da3bc071 | 2114 | net_dev->features |= NETIF_F_GRO; |
28506563 BH |
2115 | /* Mask for features that also apply to VLAN devices */ |
2116 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2117 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2118 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2119 | pci_set_drvdata(pci_dev, efx); |
2120 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2121 | if (rc) | |
2122 | goto fail1; | |
2123 | ||
2124 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2125 | ||
2126 | /* Set up basic I/O (BAR mappings etc) */ | |
2127 | rc = efx_init_io(efx); | |
2128 | if (rc) | |
2129 | goto fail2; | |
2130 | ||
2131 | /* No serialisation is required with the reset path because | |
2132 | * we're in STATE_INIT. */ | |
2133 | for (i = 0; i < 5; i++) { | |
2134 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2135 | |
2136 | /* Serialise against efx_reset(). No more resets will be | |
2137 | * scheduled since efx_stop_all() has been called, and we | |
2138 | * have not and never have been registered with either | |
2139 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2140 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2141 | |
fa402b2e SH |
2142 | if (rc == 0) { |
2143 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2144 | /* If there was a scheduled reset during | |
2145 | * probe, the NIC is probably hosed anyway */ | |
2146 | efx_pci_remove_main(efx); | |
2147 | rc = -EIO; | |
2148 | } else { | |
2149 | break; | |
2150 | } | |
2151 | } | |
2152 | ||
8ceee660 BH |
2153 | /* Retry if a recoverably reset event has been scheduled */ |
2154 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2155 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2156 | goto fail3; | |
2157 | ||
2158 | efx->reset_pending = RESET_TYPE_NONE; | |
2159 | } | |
2160 | ||
2161 | if (rc) { | |
2162 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2163 | goto fail4; | |
2164 | } | |
2165 | ||
2166 | /* Switch to the running state before we expose the device to | |
2167 | * the OS. This is to ensure that the initial gathering of | |
2168 | * MAC stats succeeds. */ | |
8ceee660 | 2169 | efx->state = STATE_RUNNING; |
7dde596e BH |
2170 | |
2171 | efx_mtd_probe(efx); /* allowed to fail */ | |
8ceee660 BH |
2172 | |
2173 | rc = efx_register_netdev(efx); | |
2174 | if (rc) | |
2175 | goto fail5; | |
2176 | ||
2177 | EFX_LOG(efx, "initialisation successful\n"); | |
8ceee660 BH |
2178 | return 0; |
2179 | ||
2180 | fail5: | |
2181 | efx_pci_remove_main(efx); | |
2182 | fail4: | |
2183 | fail3: | |
2184 | efx_fini_io(efx); | |
2185 | fail2: | |
2186 | efx_fini_struct(efx); | |
2187 | fail1: | |
2188 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2189 | free_netdev(net_dev); | |
2190 | return rc; | |
2191 | } | |
2192 | ||
2193 | static struct pci_driver efx_pci_driver = { | |
2194 | .name = EFX_DRIVER_NAME, | |
2195 | .id_table = efx_pci_table, | |
2196 | .probe = efx_pci_probe, | |
2197 | .remove = efx_pci_remove, | |
2198 | }; | |
2199 | ||
2200 | /************************************************************************** | |
2201 | * | |
2202 | * Kernel module interface | |
2203 | * | |
2204 | *************************************************************************/ | |
2205 | ||
2206 | module_param(interrupt_mode, uint, 0444); | |
2207 | MODULE_PARM_DESC(interrupt_mode, | |
2208 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2209 | ||
2210 | static int __init efx_init_module(void) | |
2211 | { | |
2212 | int rc; | |
2213 | ||
2214 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2215 | ||
2216 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2217 | if (rc) | |
2218 | goto err_notifier; | |
2219 | ||
2220 | refill_workqueue = create_workqueue("sfc_refill"); | |
2221 | if (!refill_workqueue) { | |
2222 | rc = -ENOMEM; | |
2223 | goto err_refill; | |
2224 | } | |
1ab00629 SH |
2225 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2226 | if (!reset_workqueue) { | |
2227 | rc = -ENOMEM; | |
2228 | goto err_reset; | |
2229 | } | |
8ceee660 BH |
2230 | |
2231 | rc = pci_register_driver(&efx_pci_driver); | |
2232 | if (rc < 0) | |
2233 | goto err_pci; | |
2234 | ||
2235 | return 0; | |
2236 | ||
2237 | err_pci: | |
1ab00629 SH |
2238 | destroy_workqueue(reset_workqueue); |
2239 | err_reset: | |
8ceee660 BH |
2240 | destroy_workqueue(refill_workqueue); |
2241 | err_refill: | |
2242 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2243 | err_notifier: | |
2244 | return rc; | |
2245 | } | |
2246 | ||
2247 | static void __exit efx_exit_module(void) | |
2248 | { | |
2249 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2250 | ||
2251 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2252 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2253 | destroy_workqueue(refill_workqueue); |
2254 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2255 | ||
2256 | } | |
2257 | ||
2258 | module_init(efx_init_module); | |
2259 | module_exit(efx_exit_module); | |
2260 | ||
2261 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2262 | "Solarflare Communications"); | |
2263 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2264 | MODULE_LICENSE("GPL"); | |
2265 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |