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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 BH |
23 | #include "net_driver.h" |
24 | #include "gmii.h" | |
25 | #include "ethtool.h" | |
26 | #include "tx.h" | |
27 | #include "rx.h" | |
28 | #include "efx.h" | |
29 | #include "mdio_10g.h" | |
30 | #include "falcon.h" | |
31 | #include "workarounds.h" | |
32 | #include "mac.h" | |
33 | ||
34 | #define EFX_MAX_MTU (9 * 1024) | |
35 | ||
36 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
37 | * a work item is pushed onto this work queue to retry the allocation later, | |
38 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
39 | * workqueue, there is nothing to be gained in making it per NIC | |
40 | */ | |
41 | static struct workqueue_struct *refill_workqueue; | |
42 | ||
43 | /************************************************************************** | |
44 | * | |
45 | * Configurable values | |
46 | * | |
47 | *************************************************************************/ | |
48 | ||
49 | /* | |
50 | * Enable large receive offload (LRO) aka soft segment reassembly (SSR) | |
51 | * | |
52 | * This sets the default for new devices. It can be controlled later | |
53 | * using ethtool. | |
54 | */ | |
55 | static int lro = 1; | |
56 | module_param(lro, int, 0644); | |
57 | MODULE_PARM_DESC(lro, "Large receive offload acceleration"); | |
58 | ||
59 | /* | |
60 | * Use separate channels for TX and RX events | |
61 | * | |
62 | * Set this to 1 to use separate channels for TX and RX. It allows us to | |
63 | * apply a higher level of interrupt moderation to TX events. | |
64 | * | |
65 | * This is forced to 0 for MSI interrupt mode as the interrupt vector | |
66 | * is not written | |
67 | */ | |
68 | static unsigned int separate_tx_and_rx_channels = 1; | |
69 | ||
70 | /* This is the weight assigned to each of the (per-channel) virtual | |
71 | * NAPI devices. | |
72 | */ | |
73 | static int napi_weight = 64; | |
74 | ||
75 | /* This is the time (in jiffies) between invocations of the hardware | |
76 | * monitor, which checks for known hardware bugs and resets the | |
77 | * hardware and driver as necessary. | |
78 | */ | |
79 | unsigned int efx_monitor_interval = 1 * HZ; | |
80 | ||
81 | /* This controls whether or not the hardware monitor will trigger a | |
82 | * reset when it detects an error condition. | |
83 | */ | |
84 | static unsigned int monitor_reset = 1; | |
85 | ||
86 | /* This controls whether or not the driver will initialise devices | |
87 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
88 | * such devices will be initialised with a random locally-generated | |
89 | * MAC address. This allows for loading the sfc_mtd driver to | |
90 | * reprogram the flash, even if the flash contents (including the MAC | |
91 | * address) have previously been erased. | |
92 | */ | |
93 | static unsigned int allow_bad_hwaddr; | |
94 | ||
95 | /* Initial interrupt moderation settings. They can be modified after | |
96 | * module load with ethtool. | |
97 | * | |
98 | * The default for RX should strike a balance between increasing the | |
99 | * round-trip latency and reducing overhead. | |
100 | */ | |
101 | static unsigned int rx_irq_mod_usec = 60; | |
102 | ||
103 | /* Initial interrupt moderation settings. They can be modified after | |
104 | * module load with ethtool. | |
105 | * | |
106 | * This default is chosen to ensure that a 10G link does not go idle | |
107 | * while a TX queue is stopped after it has become full. A queue is | |
108 | * restarted when it drops below half full. The time this takes (assuming | |
109 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
110 | * 512 / 3 * 1.2 = 205 usec. | |
111 | */ | |
112 | static unsigned int tx_irq_mod_usec = 150; | |
113 | ||
114 | /* This is the first interrupt mode to try out of: | |
115 | * 0 => MSI-X | |
116 | * 1 => MSI | |
117 | * 2 => legacy | |
118 | */ | |
119 | static unsigned int interrupt_mode; | |
120 | ||
121 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
122 | * i.e. the number of CPUs among which we may distribute simultaneous | |
123 | * interrupt handling. | |
124 | * | |
125 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
126 | * The default (0) means to assign an interrupt to each package (level II cache) | |
127 | */ | |
128 | static unsigned int rss_cpus; | |
129 | module_param(rss_cpus, uint, 0444); | |
130 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
131 | ||
132 | /************************************************************************** | |
133 | * | |
134 | * Utility functions and prototypes | |
135 | * | |
136 | *************************************************************************/ | |
137 | static void efx_remove_channel(struct efx_channel *channel); | |
138 | static void efx_remove_port(struct efx_nic *efx); | |
139 | static void efx_fini_napi(struct efx_nic *efx); | |
140 | static void efx_fini_channels(struct efx_nic *efx); | |
141 | ||
142 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
143 | do { \ | |
144 | if ((efx->state == STATE_RUNNING) || \ | |
145 | (efx->state == STATE_RESETTING)) \ | |
146 | ASSERT_RTNL(); \ | |
147 | } while (0) | |
148 | ||
149 | /************************************************************************** | |
150 | * | |
151 | * Event queue processing | |
152 | * | |
153 | *************************************************************************/ | |
154 | ||
155 | /* Process channel's event queue | |
156 | * | |
157 | * This function is responsible for processing the event queue of a | |
158 | * single channel. The caller must guarantee that this function will | |
159 | * never be concurrently called more than once on the same channel, | |
160 | * though different channels may be being processed concurrently. | |
161 | */ | |
162 | static inline int efx_process_channel(struct efx_channel *channel, int rx_quota) | |
163 | { | |
164 | int rxdmaqs; | |
165 | struct efx_rx_queue *rx_queue; | |
166 | ||
167 | if (unlikely(channel->efx->reset_pending != RESET_TYPE_NONE || | |
168 | !channel->enabled)) | |
169 | return rx_quota; | |
170 | ||
171 | rxdmaqs = falcon_process_eventq(channel, &rx_quota); | |
172 | ||
173 | /* Deliver last RX packet. */ | |
174 | if (channel->rx_pkt) { | |
175 | __efx_rx_packet(channel, channel->rx_pkt, | |
176 | channel->rx_pkt_csummed); | |
177 | channel->rx_pkt = NULL; | |
178 | } | |
179 | ||
180 | efx_flush_lro(channel); | |
181 | efx_rx_strategy(channel); | |
182 | ||
183 | /* Refill descriptor rings as necessary */ | |
184 | rx_queue = &channel->efx->rx_queue[0]; | |
185 | while (rxdmaqs) { | |
186 | if (rxdmaqs & 0x01) | |
187 | efx_fast_push_rx_descriptors(rx_queue); | |
188 | rx_queue++; | |
189 | rxdmaqs >>= 1; | |
190 | } | |
191 | ||
192 | return rx_quota; | |
193 | } | |
194 | ||
195 | /* Mark channel as finished processing | |
196 | * | |
197 | * Note that since we will not receive further interrupts for this | |
198 | * channel before we finish processing and call the eventq_read_ack() | |
199 | * method, there is no need to use the interrupt hold-off timers. | |
200 | */ | |
201 | static inline void efx_channel_processed(struct efx_channel *channel) | |
202 | { | |
5b9e207c BH |
203 | /* The interrupt handler for this channel may set work_pending |
204 | * as soon as we acknowledge the events we've seen. Make sure | |
205 | * it's cleared before then. */ | |
8ceee660 | 206 | channel->work_pending = 0; |
5b9e207c BH |
207 | smp_wmb(); |
208 | ||
8ceee660 BH |
209 | falcon_eventq_read_ack(channel); |
210 | } | |
211 | ||
212 | /* NAPI poll handler | |
213 | * | |
214 | * NAPI guarantees serialisation of polls of the same device, which | |
215 | * provides the guarantee required by efx_process_channel(). | |
216 | */ | |
217 | static int efx_poll(struct napi_struct *napi, int budget) | |
218 | { | |
219 | struct efx_channel *channel = | |
220 | container_of(napi, struct efx_channel, napi_str); | |
221 | struct net_device *napi_dev = channel->napi_dev; | |
222 | int unused; | |
223 | int rx_packets; | |
224 | ||
225 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
226 | channel->channel, raw_smp_processor_id()); | |
227 | ||
228 | unused = efx_process_channel(channel, budget); | |
229 | rx_packets = (budget - unused); | |
230 | ||
231 | if (rx_packets < budget) { | |
232 | /* There is no race here; although napi_disable() will | |
233 | * only wait for netif_rx_complete(), this isn't a problem | |
234 | * since efx_channel_processed() will have no effect if | |
235 | * interrupts have already been disabled. | |
236 | */ | |
237 | netif_rx_complete(napi_dev, napi); | |
238 | efx_channel_processed(channel); | |
239 | } | |
240 | ||
241 | return rx_packets; | |
242 | } | |
243 | ||
244 | /* Process the eventq of the specified channel immediately on this CPU | |
245 | * | |
246 | * Disable hardware generated interrupts, wait for any existing | |
247 | * processing to finish, then directly poll (and ack ) the eventq. | |
248 | * Finally reenable NAPI and interrupts. | |
249 | * | |
250 | * Since we are touching interrupts the caller should hold the suspend lock | |
251 | */ | |
252 | void efx_process_channel_now(struct efx_channel *channel) | |
253 | { | |
254 | struct efx_nic *efx = channel->efx; | |
255 | ||
256 | BUG_ON(!channel->used_flags); | |
257 | BUG_ON(!channel->enabled); | |
258 | ||
259 | /* Disable interrupts and wait for ISRs to complete */ | |
260 | falcon_disable_interrupts(efx); | |
261 | if (efx->legacy_irq) | |
262 | synchronize_irq(efx->legacy_irq); | |
263 | if (channel->has_interrupt && channel->irq) | |
264 | synchronize_irq(channel->irq); | |
265 | ||
266 | /* Wait for any NAPI processing to complete */ | |
267 | napi_disable(&channel->napi_str); | |
268 | ||
269 | /* Poll the channel */ | |
91ad757c | 270 | efx_process_channel(channel, efx->type->evq_size); |
8ceee660 BH |
271 | |
272 | /* Ack the eventq. This may cause an interrupt to be generated | |
273 | * when they are reenabled */ | |
274 | efx_channel_processed(channel); | |
275 | ||
276 | napi_enable(&channel->napi_str); | |
277 | falcon_enable_interrupts(efx); | |
278 | } | |
279 | ||
280 | /* Create event queue | |
281 | * Event queue memory allocations are done only once. If the channel | |
282 | * is reset, the memory buffer will be reused; this guards against | |
283 | * errors during channel reset and also simplifies interrupt handling. | |
284 | */ | |
285 | static int efx_probe_eventq(struct efx_channel *channel) | |
286 | { | |
287 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
288 | ||
289 | return falcon_probe_eventq(channel); | |
290 | } | |
291 | ||
292 | /* Prepare channel's event queue */ | |
293 | static int efx_init_eventq(struct efx_channel *channel) | |
294 | { | |
295 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
296 | ||
297 | channel->eventq_read_ptr = 0; | |
298 | ||
299 | return falcon_init_eventq(channel); | |
300 | } | |
301 | ||
302 | static void efx_fini_eventq(struct efx_channel *channel) | |
303 | { | |
304 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
305 | ||
306 | falcon_fini_eventq(channel); | |
307 | } | |
308 | ||
309 | static void efx_remove_eventq(struct efx_channel *channel) | |
310 | { | |
311 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
312 | ||
313 | falcon_remove_eventq(channel); | |
314 | } | |
315 | ||
316 | /************************************************************************** | |
317 | * | |
318 | * Channel handling | |
319 | * | |
320 | *************************************************************************/ | |
321 | ||
8ceee660 BH |
322 | static int efx_probe_channel(struct efx_channel *channel) |
323 | { | |
324 | struct efx_tx_queue *tx_queue; | |
325 | struct efx_rx_queue *rx_queue; | |
326 | int rc; | |
327 | ||
328 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
329 | ||
330 | rc = efx_probe_eventq(channel); | |
331 | if (rc) | |
332 | goto fail1; | |
333 | ||
334 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
335 | rc = efx_probe_tx_queue(tx_queue); | |
336 | if (rc) | |
337 | goto fail2; | |
338 | } | |
339 | ||
340 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
341 | rc = efx_probe_rx_queue(rx_queue); | |
342 | if (rc) | |
343 | goto fail3; | |
344 | } | |
345 | ||
346 | channel->n_rx_frm_trunc = 0; | |
347 | ||
348 | return 0; | |
349 | ||
350 | fail3: | |
351 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
352 | efx_remove_rx_queue(rx_queue); | |
353 | fail2: | |
354 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
355 | efx_remove_tx_queue(tx_queue); | |
356 | fail1: | |
357 | return rc; | |
358 | } | |
359 | ||
360 | ||
361 | /* Channels are shutdown and reinitialised whilst the NIC is running | |
362 | * to propagate configuration changes (mtu, checksum offload), or | |
363 | * to clear hardware error conditions | |
364 | */ | |
365 | static int efx_init_channels(struct efx_nic *efx) | |
366 | { | |
367 | struct efx_tx_queue *tx_queue; | |
368 | struct efx_rx_queue *rx_queue; | |
369 | struct efx_channel *channel; | |
370 | int rc = 0; | |
371 | ||
f7f13b0b BH |
372 | /* Calculate the rx buffer allocation parameters required to |
373 | * support the current MTU, including padding for header | |
374 | * alignment and overruns. | |
375 | */ | |
376 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
377 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
378 | efx->type->rx_buffer_padding); | |
379 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
380 | |
381 | /* Initialise the channels */ | |
382 | efx_for_each_channel(channel, efx) { | |
383 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
384 | ||
385 | rc = efx_init_eventq(channel); | |
386 | if (rc) | |
387 | goto err; | |
388 | ||
389 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
390 | rc = efx_init_tx_queue(tx_queue); | |
391 | if (rc) | |
392 | goto err; | |
393 | } | |
394 | ||
395 | /* The rx buffer allocation strategy is MTU dependent */ | |
396 | efx_rx_strategy(channel); | |
397 | ||
398 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
399 | rc = efx_init_rx_queue(rx_queue); | |
400 | if (rc) | |
401 | goto err; | |
402 | } | |
403 | ||
404 | WARN_ON(channel->rx_pkt != NULL); | |
405 | efx_rx_strategy(channel); | |
406 | } | |
407 | ||
408 | return 0; | |
409 | ||
410 | err: | |
411 | EFX_ERR(efx, "failed to initialise channel %d\n", | |
412 | channel ? channel->channel : -1); | |
413 | efx_fini_channels(efx); | |
414 | return rc; | |
415 | } | |
416 | ||
417 | /* This enables event queue processing and packet transmission. | |
418 | * | |
419 | * Note that this function is not allowed to fail, since that would | |
420 | * introduce too much complexity into the suspend/resume path. | |
421 | */ | |
422 | static void efx_start_channel(struct efx_channel *channel) | |
423 | { | |
424 | struct efx_rx_queue *rx_queue; | |
425 | ||
426 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
427 | ||
428 | if (!(channel->efx->net_dev->flags & IFF_UP)) | |
429 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
430 | efx_poll, napi_weight); | |
431 | ||
5b9e207c BH |
432 | /* The interrupt handler for this channel may set work_pending |
433 | * as soon as we enable it. Make sure it's cleared before | |
434 | * then. Similarly, make sure it sees the enabled flag set. */ | |
8ceee660 BH |
435 | channel->work_pending = 0; |
436 | channel->enabled = 1; | |
5b9e207c | 437 | smp_wmb(); |
8ceee660 BH |
438 | |
439 | napi_enable(&channel->napi_str); | |
440 | ||
441 | /* Load up RX descriptors */ | |
442 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
443 | efx_fast_push_rx_descriptors(rx_queue); | |
444 | } | |
445 | ||
446 | /* This disables event queue processing and packet transmission. | |
447 | * This function does not guarantee that all queue processing | |
448 | * (e.g. RX refill) is complete. | |
449 | */ | |
450 | static void efx_stop_channel(struct efx_channel *channel) | |
451 | { | |
452 | struct efx_rx_queue *rx_queue; | |
453 | ||
454 | if (!channel->enabled) | |
455 | return; | |
456 | ||
457 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
458 | ||
459 | channel->enabled = 0; | |
460 | napi_disable(&channel->napi_str); | |
461 | ||
462 | /* Ensure that any worker threads have exited or will be no-ops */ | |
463 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
464 | spin_lock_bh(&rx_queue->add_lock); | |
465 | spin_unlock_bh(&rx_queue->add_lock); | |
466 | } | |
467 | } | |
468 | ||
469 | static void efx_fini_channels(struct efx_nic *efx) | |
470 | { | |
471 | struct efx_channel *channel; | |
472 | struct efx_tx_queue *tx_queue; | |
473 | struct efx_rx_queue *rx_queue; | |
474 | ||
475 | EFX_ASSERT_RESET_SERIALISED(efx); | |
476 | BUG_ON(efx->port_enabled); | |
477 | ||
478 | efx_for_each_channel(channel, efx) { | |
479 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
480 | ||
481 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
482 | efx_fini_rx_queue(rx_queue); | |
483 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
484 | efx_fini_tx_queue(tx_queue); | |
485 | } | |
486 | ||
487 | /* Do the event queues last so that we can handle flush events | |
488 | * for all DMA queues. */ | |
489 | efx_for_each_channel(channel, efx) { | |
490 | EFX_LOG(channel->efx, "shut down evq %d\n", channel->channel); | |
491 | ||
492 | efx_fini_eventq(channel); | |
493 | } | |
494 | } | |
495 | ||
496 | static void efx_remove_channel(struct efx_channel *channel) | |
497 | { | |
498 | struct efx_tx_queue *tx_queue; | |
499 | struct efx_rx_queue *rx_queue; | |
500 | ||
501 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
502 | ||
503 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
504 | efx_remove_rx_queue(rx_queue); | |
505 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
506 | efx_remove_tx_queue(tx_queue); | |
507 | efx_remove_eventq(channel); | |
508 | ||
509 | channel->used_flags = 0; | |
510 | } | |
511 | ||
512 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
513 | { | |
514 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
515 | } | |
516 | ||
517 | /************************************************************************** | |
518 | * | |
519 | * Port handling | |
520 | * | |
521 | **************************************************************************/ | |
522 | ||
523 | /* This ensures that the kernel is kept informed (via | |
524 | * netif_carrier_on/off) of the link status, and also maintains the | |
525 | * link status's stop on the port's TX queue. | |
526 | */ | |
527 | static void efx_link_status_changed(struct efx_nic *efx) | |
528 | { | |
529 | int carrier_ok; | |
530 | ||
531 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure | |
532 | * that no events are triggered between unregister_netdev() and the | |
533 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
534 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
535 | if (!netif_running(efx->net_dev)) | |
536 | return; | |
537 | ||
538 | carrier_ok = netif_carrier_ok(efx->net_dev) ? 1 : 0; | |
539 | if (efx->link_up != carrier_ok) { | |
540 | efx->n_link_state_changes++; | |
541 | ||
542 | if (efx->link_up) | |
543 | netif_carrier_on(efx->net_dev); | |
544 | else | |
545 | netif_carrier_off(efx->net_dev); | |
546 | } | |
547 | ||
548 | /* Status message for kernel log */ | |
549 | if (efx->link_up) { | |
550 | struct mii_if_info *gmii = &efx->mii; | |
551 | unsigned adv, lpa; | |
552 | /* NONE here means direct XAUI from the controller, with no | |
553 | * MDIO-attached device we can query. */ | |
554 | if (efx->phy_type != PHY_TYPE_NONE) { | |
555 | adv = gmii_advertised(gmii); | |
556 | lpa = gmii_lpa(gmii); | |
557 | } else { | |
558 | lpa = GM_LPA_10000 | LPA_DUPLEX; | |
559 | adv = lpa; | |
560 | } | |
561 | EFX_INFO(efx, "link up at %dMbps %s-duplex " | |
562 | "(adv %04x lpa %04x) (MTU %d)%s\n", | |
563 | (efx->link_options & GM_LPA_10000 ? 10000 : | |
564 | (efx->link_options & GM_LPA_1000 ? 1000 : | |
565 | (efx->link_options & GM_LPA_100 ? 100 : | |
566 | 10))), | |
567 | (efx->link_options & GM_LPA_DUPLEX ? | |
568 | "full" : "half"), | |
569 | adv, lpa, | |
570 | efx->net_dev->mtu, | |
571 | (efx->promiscuous ? " [PROMISC]" : "")); | |
572 | } else { | |
573 | EFX_INFO(efx, "link down\n"); | |
574 | } | |
575 | ||
576 | } | |
577 | ||
578 | /* This call reinitialises the MAC to pick up new PHY settings. The | |
579 | * caller must hold the mac_lock */ | |
580 | static void __efx_reconfigure_port(struct efx_nic *efx) | |
581 | { | |
582 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
583 | ||
584 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
585 | raw_smp_processor_id()); | |
586 | ||
587 | falcon_reconfigure_xmac(efx); | |
588 | ||
589 | /* Inform kernel of loss/gain of carrier */ | |
590 | efx_link_status_changed(efx); | |
591 | } | |
592 | ||
593 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
594 | * disabled. */ | |
595 | void efx_reconfigure_port(struct efx_nic *efx) | |
596 | { | |
597 | EFX_ASSERT_RESET_SERIALISED(efx); | |
598 | ||
599 | mutex_lock(&efx->mac_lock); | |
600 | __efx_reconfigure_port(efx); | |
601 | mutex_unlock(&efx->mac_lock); | |
602 | } | |
603 | ||
604 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
605 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
606 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
607 | static void efx_reconfigure_work(struct work_struct *data) | |
608 | { | |
609 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
610 | reconfigure_work); | |
611 | ||
612 | mutex_lock(&efx->mac_lock); | |
613 | if (efx->port_enabled) | |
614 | __efx_reconfigure_port(efx); | |
615 | mutex_unlock(&efx->mac_lock); | |
616 | } | |
617 | ||
618 | static int efx_probe_port(struct efx_nic *efx) | |
619 | { | |
620 | int rc; | |
621 | ||
622 | EFX_LOG(efx, "create port\n"); | |
623 | ||
624 | /* Connect up MAC/PHY operations table and read MAC address */ | |
625 | rc = falcon_probe_port(efx); | |
626 | if (rc) | |
627 | goto err; | |
628 | ||
629 | /* Sanity check MAC address */ | |
630 | if (is_valid_ether_addr(efx->mac_address)) { | |
631 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
632 | } else { | |
633 | DECLARE_MAC_BUF(mac); | |
634 | ||
635 | EFX_ERR(efx, "invalid MAC address %s\n", | |
636 | print_mac(mac, efx->mac_address)); | |
637 | if (!allow_bad_hwaddr) { | |
638 | rc = -EINVAL; | |
639 | goto err; | |
640 | } | |
641 | random_ether_addr(efx->net_dev->dev_addr); | |
642 | EFX_INFO(efx, "using locally-generated MAC %s\n", | |
643 | print_mac(mac, efx->net_dev->dev_addr)); | |
644 | } | |
645 | ||
646 | return 0; | |
647 | ||
648 | err: | |
649 | efx_remove_port(efx); | |
650 | return rc; | |
651 | } | |
652 | ||
653 | static int efx_init_port(struct efx_nic *efx) | |
654 | { | |
655 | int rc; | |
656 | ||
657 | EFX_LOG(efx, "init port\n"); | |
658 | ||
659 | /* Initialise the MAC and PHY */ | |
660 | rc = falcon_init_xmac(efx); | |
661 | if (rc) | |
662 | return rc; | |
663 | ||
664 | efx->port_initialized = 1; | |
665 | ||
666 | /* Reconfigure port to program MAC registers */ | |
667 | falcon_reconfigure_xmac(efx); | |
668 | ||
669 | return 0; | |
670 | } | |
671 | ||
672 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
673 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
674 | * efx_reconfigure_port() may have been cancelled */ | |
675 | static void efx_start_port(struct efx_nic *efx) | |
676 | { | |
677 | EFX_LOG(efx, "start port\n"); | |
678 | BUG_ON(efx->port_enabled); | |
679 | ||
680 | mutex_lock(&efx->mac_lock); | |
681 | efx->port_enabled = 1; | |
682 | __efx_reconfigure_port(efx); | |
683 | mutex_unlock(&efx->mac_lock); | |
684 | } | |
685 | ||
686 | /* Prevent efx_reconfigure_work and efx_monitor() from executing, and | |
687 | * efx_set_multicast_list() from scheduling efx_reconfigure_work. | |
688 | * efx_reconfigure_work can still be scheduled via NAPI processing | |
689 | * until efx_flush_all() is called */ | |
690 | static void efx_stop_port(struct efx_nic *efx) | |
691 | { | |
692 | EFX_LOG(efx, "stop port\n"); | |
693 | ||
694 | mutex_lock(&efx->mac_lock); | |
695 | efx->port_enabled = 0; | |
696 | mutex_unlock(&efx->mac_lock); | |
697 | ||
698 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 699 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
700 | netif_addr_lock_bh(efx->net_dev); |
701 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
702 | } |
703 | } | |
704 | ||
705 | static void efx_fini_port(struct efx_nic *efx) | |
706 | { | |
707 | EFX_LOG(efx, "shut down port\n"); | |
708 | ||
709 | if (!efx->port_initialized) | |
710 | return; | |
711 | ||
712 | falcon_fini_xmac(efx); | |
713 | efx->port_initialized = 0; | |
714 | ||
715 | efx->link_up = 0; | |
716 | efx_link_status_changed(efx); | |
717 | } | |
718 | ||
719 | static void efx_remove_port(struct efx_nic *efx) | |
720 | { | |
721 | EFX_LOG(efx, "destroying port\n"); | |
722 | ||
723 | falcon_remove_port(efx); | |
724 | } | |
725 | ||
726 | /************************************************************************** | |
727 | * | |
728 | * NIC handling | |
729 | * | |
730 | **************************************************************************/ | |
731 | ||
732 | /* This configures the PCI device to enable I/O and DMA. */ | |
733 | static int efx_init_io(struct efx_nic *efx) | |
734 | { | |
735 | struct pci_dev *pci_dev = efx->pci_dev; | |
736 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
737 | int rc; | |
738 | ||
739 | EFX_LOG(efx, "initialising I/O\n"); | |
740 | ||
741 | rc = pci_enable_device(pci_dev); | |
742 | if (rc) { | |
743 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
744 | goto fail1; | |
745 | } | |
746 | ||
747 | pci_set_master(pci_dev); | |
748 | ||
749 | /* Set the PCI DMA mask. Try all possibilities from our | |
750 | * genuine mask down to 32 bits, because some architectures | |
751 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
752 | * masks event though they reject 46 bit masks. | |
753 | */ | |
754 | while (dma_mask > 0x7fffffffUL) { | |
755 | if (pci_dma_supported(pci_dev, dma_mask) && | |
756 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
757 | break; | |
758 | dma_mask >>= 1; | |
759 | } | |
760 | if (rc) { | |
761 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
762 | goto fail2; | |
763 | } | |
764 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
765 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
766 | if (rc) { | |
767 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
768 | * fail with a mask that pci_set_dma_mask() accepted, | |
769 | * but just in case... | |
770 | */ | |
771 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
772 | goto fail2; | |
773 | } | |
774 | ||
775 | efx->membase_phys = pci_resource_start(efx->pci_dev, | |
776 | efx->type->mem_bar); | |
777 | rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc"); | |
778 | if (rc) { | |
779 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
780 | rc = -EIO; | |
781 | goto fail3; | |
782 | } | |
783 | efx->membase = ioremap_nocache(efx->membase_phys, | |
784 | efx->type->mem_map_size); | |
785 | if (!efx->membase) { | |
086ea356 BH |
786 | EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n", |
787 | efx->type->mem_bar, | |
788 | (unsigned long long)efx->membase_phys, | |
8ceee660 BH |
789 | efx->type->mem_map_size); |
790 | rc = -ENOMEM; | |
791 | goto fail4; | |
792 | } | |
086ea356 BH |
793 | EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n", |
794 | efx->type->mem_bar, (unsigned long long)efx->membase_phys, | |
795 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
796 | |
797 | return 0; | |
798 | ||
799 | fail4: | |
800 | release_mem_region(efx->membase_phys, efx->type->mem_map_size); | |
801 | fail3: | |
2c118e0f | 802 | efx->membase_phys = 0; |
8ceee660 BH |
803 | fail2: |
804 | pci_disable_device(efx->pci_dev); | |
805 | fail1: | |
806 | return rc; | |
807 | } | |
808 | ||
809 | static void efx_fini_io(struct efx_nic *efx) | |
810 | { | |
811 | EFX_LOG(efx, "shutting down I/O\n"); | |
812 | ||
813 | if (efx->membase) { | |
814 | iounmap(efx->membase); | |
815 | efx->membase = NULL; | |
816 | } | |
817 | ||
818 | if (efx->membase_phys) { | |
819 | pci_release_region(efx->pci_dev, efx->type->mem_bar); | |
2c118e0f | 820 | efx->membase_phys = 0; |
8ceee660 BH |
821 | } |
822 | ||
823 | pci_disable_device(efx->pci_dev); | |
824 | } | |
825 | ||
826 | /* Probe the number and type of interrupts we are able to obtain. */ | |
827 | static void efx_probe_interrupts(struct efx_nic *efx) | |
828 | { | |
829 | int max_channel = efx->type->phys_addr_channels - 1; | |
830 | struct msix_entry xentries[EFX_MAX_CHANNELS]; | |
831 | int rc, i; | |
832 | ||
833 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
834 | BUG_ON(!pci_find_capability(efx->pci_dev, PCI_CAP_ID_MSIX)); | |
835 | ||
aa6ef27e BH |
836 | if (rss_cpus == 0) { |
837 | cpumask_t core_mask; | |
838 | int cpu; | |
839 | ||
840 | cpus_clear(core_mask); | |
841 | efx->rss_queues = 0; | |
842 | for_each_online_cpu(cpu) { | |
843 | if (!cpu_isset(cpu, core_mask)) { | |
844 | ++efx->rss_queues; | |
845 | cpus_or(core_mask, core_mask, | |
846 | topology_core_siblings(cpu)); | |
847 | } | |
848 | } | |
849 | } else { | |
850 | efx->rss_queues = rss_cpus; | |
851 | } | |
852 | ||
8ceee660 BH |
853 | efx->rss_queues = min(efx->rss_queues, max_channel + 1); |
854 | efx->rss_queues = min(efx->rss_queues, EFX_MAX_CHANNELS); | |
855 | ||
856 | /* Request maximum number of MSI interrupts, and fill out | |
857 | * the channel interrupt information the allowed allocation */ | |
858 | for (i = 0; i < efx->rss_queues; i++) | |
859 | xentries[i].entry = i; | |
860 | rc = pci_enable_msix(efx->pci_dev, xentries, efx->rss_queues); | |
861 | if (rc > 0) { | |
862 | EFX_BUG_ON_PARANOID(rc >= efx->rss_queues); | |
863 | efx->rss_queues = rc; | |
864 | rc = pci_enable_msix(efx->pci_dev, xentries, | |
865 | efx->rss_queues); | |
866 | } | |
867 | ||
868 | if (rc == 0) { | |
869 | for (i = 0; i < efx->rss_queues; i++) { | |
870 | efx->channel[i].has_interrupt = 1; | |
871 | efx->channel[i].irq = xentries[i].vector; | |
872 | } | |
873 | } else { | |
874 | /* Fall back to single channel MSI */ | |
875 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
876 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
877 | } | |
878 | } | |
879 | ||
880 | /* Try single interrupt MSI */ | |
881 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
882 | efx->rss_queues = 1; | |
883 | rc = pci_enable_msi(efx->pci_dev); | |
884 | if (rc == 0) { | |
885 | efx->channel[0].irq = efx->pci_dev->irq; | |
886 | efx->channel[0].has_interrupt = 1; | |
887 | } else { | |
888 | EFX_ERR(efx, "could not enable MSI\n"); | |
889 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
890 | } | |
891 | } | |
892 | ||
893 | /* Assume legacy interrupts */ | |
894 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
895 | efx->rss_queues = 1; | |
896 | /* Every channel is interruptible */ | |
897 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
898 | efx->channel[i].has_interrupt = 1; | |
899 | efx->legacy_irq = efx->pci_dev->irq; | |
900 | } | |
901 | } | |
902 | ||
903 | static void efx_remove_interrupts(struct efx_nic *efx) | |
904 | { | |
905 | struct efx_channel *channel; | |
906 | ||
907 | /* Remove MSI/MSI-X interrupts */ | |
908 | efx_for_each_channel_with_interrupt(channel, efx) | |
909 | channel->irq = 0; | |
910 | pci_disable_msi(efx->pci_dev); | |
911 | pci_disable_msix(efx->pci_dev); | |
912 | ||
913 | /* Remove legacy interrupt */ | |
914 | efx->legacy_irq = 0; | |
915 | } | |
916 | ||
917 | /* Select number of used resources | |
918 | * Should be called after probe_interrupts() | |
919 | */ | |
920 | static void efx_select_used(struct efx_nic *efx) | |
921 | { | |
922 | struct efx_tx_queue *tx_queue; | |
923 | struct efx_rx_queue *rx_queue; | |
924 | int i; | |
925 | ||
926 | /* TX queues. One per port per channel with TX capability | |
927 | * (more than one per port won't work on Linux, due to out | |
928 | * of order issues... but will be fine on Solaris) | |
929 | */ | |
930 | tx_queue = &efx->tx_queue[0]; | |
931 | ||
932 | /* Perform this for each channel with TX capabilities. | |
933 | * At the moment, we only support a single TX queue | |
934 | */ | |
935 | tx_queue->used = 1; | |
936 | if ((!EFX_INT_MODE_USE_MSI(efx)) && separate_tx_and_rx_channels) | |
937 | tx_queue->channel = &efx->channel[1]; | |
938 | else | |
939 | tx_queue->channel = &efx->channel[0]; | |
940 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
941 | tx_queue++; | |
942 | ||
943 | /* RX queues. Each has a dedicated channel. */ | |
944 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
945 | rx_queue = &efx->rx_queue[i]; | |
946 | ||
947 | if (i < efx->rss_queues) { | |
948 | rx_queue->used = 1; | |
949 | /* If we allow multiple RX queues per channel | |
950 | * we need to decide that here | |
951 | */ | |
952 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
953 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
954 | rx_queue++; | |
955 | } | |
956 | } | |
957 | } | |
958 | ||
959 | static int efx_probe_nic(struct efx_nic *efx) | |
960 | { | |
961 | int rc; | |
962 | ||
963 | EFX_LOG(efx, "creating NIC\n"); | |
964 | ||
965 | /* Carry out hardware-type specific initialisation */ | |
966 | rc = falcon_probe_nic(efx); | |
967 | if (rc) | |
968 | return rc; | |
969 | ||
970 | /* Determine the number of channels and RX queues by trying to hook | |
971 | * in MSI-X interrupts. */ | |
972 | efx_probe_interrupts(efx); | |
973 | ||
974 | /* Determine number of RX queues and TX queues */ | |
975 | efx_select_used(efx); | |
976 | ||
977 | /* Initialise the interrupt moderation settings */ | |
978 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec); | |
979 | ||
980 | return 0; | |
981 | } | |
982 | ||
983 | static void efx_remove_nic(struct efx_nic *efx) | |
984 | { | |
985 | EFX_LOG(efx, "destroying NIC\n"); | |
986 | ||
987 | efx_remove_interrupts(efx); | |
988 | falcon_remove_nic(efx); | |
989 | } | |
990 | ||
991 | /************************************************************************** | |
992 | * | |
993 | * NIC startup/shutdown | |
994 | * | |
995 | *************************************************************************/ | |
996 | ||
997 | static int efx_probe_all(struct efx_nic *efx) | |
998 | { | |
999 | struct efx_channel *channel; | |
1000 | int rc; | |
1001 | ||
1002 | /* Create NIC */ | |
1003 | rc = efx_probe_nic(efx); | |
1004 | if (rc) { | |
1005 | EFX_ERR(efx, "failed to create NIC\n"); | |
1006 | goto fail1; | |
1007 | } | |
1008 | ||
1009 | /* Create port */ | |
1010 | rc = efx_probe_port(efx); | |
1011 | if (rc) { | |
1012 | EFX_ERR(efx, "failed to create port\n"); | |
1013 | goto fail2; | |
1014 | } | |
1015 | ||
1016 | /* Create channels */ | |
1017 | efx_for_each_channel(channel, efx) { | |
1018 | rc = efx_probe_channel(channel); | |
1019 | if (rc) { | |
1020 | EFX_ERR(efx, "failed to create channel %d\n", | |
1021 | channel->channel); | |
1022 | goto fail3; | |
1023 | } | |
1024 | } | |
1025 | ||
1026 | return 0; | |
1027 | ||
1028 | fail3: | |
1029 | efx_for_each_channel(channel, efx) | |
1030 | efx_remove_channel(channel); | |
1031 | efx_remove_port(efx); | |
1032 | fail2: | |
1033 | efx_remove_nic(efx); | |
1034 | fail1: | |
1035 | return rc; | |
1036 | } | |
1037 | ||
1038 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1039 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1040 | * and ensures that the port is scheduled to be reconfigured. | |
1041 | * This function is safe to call multiple times when the NIC is in any | |
1042 | * state. */ | |
1043 | static void efx_start_all(struct efx_nic *efx) | |
1044 | { | |
1045 | struct efx_channel *channel; | |
1046 | ||
1047 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1048 | ||
1049 | /* Check that it is appropriate to restart the interface. All | |
1050 | * of these flags are safe to read under just the rtnl lock */ | |
1051 | if (efx->port_enabled) | |
1052 | return; | |
1053 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1054 | return; | |
55668611 | 1055 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1056 | return; |
1057 | ||
1058 | /* Mark the port as enabled so port reconfigurations can start, then | |
1059 | * restart the transmit interface early so the watchdog timer stops */ | |
1060 | efx_start_port(efx); | |
1061 | efx_wake_queue(efx); | |
1062 | ||
1063 | efx_for_each_channel(channel, efx) | |
1064 | efx_start_channel(channel); | |
1065 | ||
1066 | falcon_enable_interrupts(efx); | |
1067 | ||
1068 | /* Start hardware monitor if we're in RUNNING */ | |
1069 | if (efx->state == STATE_RUNNING) | |
1070 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1071 | efx_monitor_interval); | |
1072 | } | |
1073 | ||
1074 | /* Flush all delayed work. Should only be called when no more delayed work | |
1075 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1076 | * since we're holding the rtnl_lock at this point. */ | |
1077 | static void efx_flush_all(struct efx_nic *efx) | |
1078 | { | |
1079 | struct efx_rx_queue *rx_queue; | |
1080 | ||
1081 | /* Make sure the hardware monitor is stopped */ | |
1082 | cancel_delayed_work_sync(&efx->monitor_work); | |
1083 | ||
1084 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1085 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1086 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1087 | |
1088 | /* Stop scheduled port reconfigurations */ | |
1089 | cancel_work_sync(&efx->reconfigure_work); | |
1090 | ||
1091 | } | |
1092 | ||
1093 | /* Quiesce hardware and software without bringing the link down. | |
1094 | * Safe to call multiple times, when the nic and interface is in any | |
1095 | * state. The caller is guaranteed to subsequently be in a position | |
1096 | * to modify any hardware and software state they see fit without | |
1097 | * taking locks. */ | |
1098 | static void efx_stop_all(struct efx_nic *efx) | |
1099 | { | |
1100 | struct efx_channel *channel; | |
1101 | ||
1102 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1103 | ||
1104 | /* port_enabled can be read safely under the rtnl lock */ | |
1105 | if (!efx->port_enabled) | |
1106 | return; | |
1107 | ||
1108 | /* Disable interrupts and wait for ISR to complete */ | |
1109 | falcon_disable_interrupts(efx); | |
1110 | if (efx->legacy_irq) | |
1111 | synchronize_irq(efx->legacy_irq); | |
b3475645 | 1112 | efx_for_each_channel_with_interrupt(channel, efx) { |
8ceee660 BH |
1113 | if (channel->irq) |
1114 | synchronize_irq(channel->irq); | |
b3475645 | 1115 | } |
8ceee660 BH |
1116 | |
1117 | /* Stop all NAPI processing and synchronous rx refills */ | |
1118 | efx_for_each_channel(channel, efx) | |
1119 | efx_stop_channel(channel); | |
1120 | ||
1121 | /* Stop all asynchronous port reconfigurations. Since all | |
1122 | * event processing has already been stopped, there is no | |
1123 | * window to loose phy events */ | |
1124 | efx_stop_port(efx); | |
1125 | ||
1126 | /* Flush reconfigure_work, refill_workqueue, monitor_work */ | |
1127 | efx_flush_all(efx); | |
1128 | ||
1129 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1130 | * flushes will complete in a timely fashion. */ | |
1131 | falcon_deconfigure_mac_wrapper(efx); | |
1132 | falcon_drain_tx_fifo(efx); | |
1133 | ||
1134 | /* Stop the kernel transmit interface late, so the watchdog | |
1135 | * timer isn't ticking over the flush */ | |
1136 | efx_stop_queue(efx); | |
55668611 | 1137 | if (efx_dev_registered(efx)) { |
8ceee660 BH |
1138 | netif_tx_lock_bh(efx->net_dev); |
1139 | netif_tx_unlock_bh(efx->net_dev); | |
1140 | } | |
1141 | } | |
1142 | ||
1143 | static void efx_remove_all(struct efx_nic *efx) | |
1144 | { | |
1145 | struct efx_channel *channel; | |
1146 | ||
1147 | efx_for_each_channel(channel, efx) | |
1148 | efx_remove_channel(channel); | |
1149 | efx_remove_port(efx); | |
1150 | efx_remove_nic(efx); | |
1151 | } | |
1152 | ||
1153 | /* A convinience function to safely flush all the queues */ | |
1154 | int efx_flush_queues(struct efx_nic *efx) | |
1155 | { | |
1156 | int rc; | |
1157 | ||
1158 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1159 | ||
1160 | efx_stop_all(efx); | |
1161 | ||
1162 | efx_fini_channels(efx); | |
1163 | rc = efx_init_channels(efx); | |
1164 | if (rc) { | |
1165 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1166 | return rc; | |
1167 | } | |
1168 | ||
1169 | efx_start_all(efx); | |
1170 | ||
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | /************************************************************************** | |
1175 | * | |
1176 | * Interrupt moderation | |
1177 | * | |
1178 | **************************************************************************/ | |
1179 | ||
1180 | /* Set interrupt moderation parameters */ | |
1181 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs) | |
1182 | { | |
1183 | struct efx_tx_queue *tx_queue; | |
1184 | struct efx_rx_queue *rx_queue; | |
1185 | ||
1186 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1187 | ||
1188 | efx_for_each_tx_queue(tx_queue, efx) | |
1189 | tx_queue->channel->irq_moderation = tx_usecs; | |
1190 | ||
1191 | efx_for_each_rx_queue(rx_queue, efx) | |
1192 | rx_queue->channel->irq_moderation = rx_usecs; | |
1193 | } | |
1194 | ||
1195 | /************************************************************************** | |
1196 | * | |
1197 | * Hardware monitor | |
1198 | * | |
1199 | **************************************************************************/ | |
1200 | ||
1201 | /* Run periodically off the general workqueue. Serialised against | |
1202 | * efx_reconfigure_port via the mac_lock */ | |
1203 | static void efx_monitor(struct work_struct *data) | |
1204 | { | |
1205 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1206 | monitor_work.work); | |
1207 | int rc = 0; | |
1208 | ||
1209 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1210 | raw_smp_processor_id()); | |
1211 | ||
1212 | ||
1213 | /* If the mac_lock is already held then it is likely a port | |
1214 | * reconfiguration is already in place, which will likely do | |
1215 | * most of the work of check_hw() anyway. */ | |
1216 | if (!mutex_trylock(&efx->mac_lock)) { | |
1217 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1218 | efx_monitor_interval); | |
1219 | return; | |
1220 | } | |
1221 | ||
1222 | if (efx->port_enabled) | |
1223 | rc = falcon_check_xmac(efx); | |
1224 | mutex_unlock(&efx->mac_lock); | |
1225 | ||
1226 | if (rc) { | |
1227 | if (monitor_reset) { | |
1228 | EFX_ERR(efx, "hardware monitor detected a fault: " | |
1229 | "triggering reset\n"); | |
1230 | efx_schedule_reset(efx, RESET_TYPE_MONITOR); | |
1231 | } else { | |
1232 | EFX_ERR(efx, "hardware monitor detected a fault, " | |
1233 | "skipping reset\n"); | |
1234 | } | |
1235 | } | |
1236 | ||
1237 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1238 | efx_monitor_interval); | |
1239 | } | |
1240 | ||
1241 | /************************************************************************** | |
1242 | * | |
1243 | * ioctls | |
1244 | * | |
1245 | *************************************************************************/ | |
1246 | ||
1247 | /* Net device ioctl | |
1248 | * Context: process, rtnl_lock() held. | |
1249 | */ | |
1250 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1251 | { | |
1252 | struct efx_nic *efx = net_dev->priv; | |
1253 | ||
1254 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1255 | ||
1256 | return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL); | |
1257 | } | |
1258 | ||
1259 | /************************************************************************** | |
1260 | * | |
1261 | * NAPI interface | |
1262 | * | |
1263 | **************************************************************************/ | |
1264 | ||
1265 | static int efx_init_napi(struct efx_nic *efx) | |
1266 | { | |
1267 | struct efx_channel *channel; | |
1268 | int rc; | |
1269 | ||
1270 | efx_for_each_channel(channel, efx) { | |
1271 | channel->napi_dev = efx->net_dev; | |
1272 | rc = efx_lro_init(&channel->lro_mgr, efx); | |
1273 | if (rc) | |
1274 | goto err; | |
1275 | } | |
1276 | return 0; | |
1277 | err: | |
1278 | efx_fini_napi(efx); | |
1279 | return rc; | |
1280 | } | |
1281 | ||
1282 | static void efx_fini_napi(struct efx_nic *efx) | |
1283 | { | |
1284 | struct efx_channel *channel; | |
1285 | ||
1286 | efx_for_each_channel(channel, efx) { | |
1287 | efx_lro_fini(&channel->lro_mgr); | |
1288 | channel->napi_dev = NULL; | |
1289 | } | |
1290 | } | |
1291 | ||
1292 | /************************************************************************** | |
1293 | * | |
1294 | * Kernel netpoll interface | |
1295 | * | |
1296 | *************************************************************************/ | |
1297 | ||
1298 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1299 | ||
1300 | /* Although in the common case interrupts will be disabled, this is not | |
1301 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1302 | * so no locking is required. | |
1303 | */ | |
1304 | static void efx_netpoll(struct net_device *net_dev) | |
1305 | { | |
1306 | struct efx_nic *efx = net_dev->priv; | |
1307 | struct efx_channel *channel; | |
1308 | ||
1309 | efx_for_each_channel_with_interrupt(channel, efx) | |
1310 | efx_schedule_channel(channel); | |
1311 | } | |
1312 | ||
1313 | #endif | |
1314 | ||
1315 | /************************************************************************** | |
1316 | * | |
1317 | * Kernel net device interface | |
1318 | * | |
1319 | *************************************************************************/ | |
1320 | ||
1321 | /* Context: process, rtnl_lock() held. */ | |
1322 | static int efx_net_open(struct net_device *net_dev) | |
1323 | { | |
1324 | struct efx_nic *efx = net_dev->priv; | |
1325 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1326 | ||
1327 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1328 | raw_smp_processor_id()); | |
1329 | ||
1330 | efx_start_all(efx); | |
1331 | return 0; | |
1332 | } | |
1333 | ||
1334 | /* Context: process, rtnl_lock() held. | |
1335 | * Note that the kernel will ignore our return code; this method | |
1336 | * should really be a void. | |
1337 | */ | |
1338 | static int efx_net_stop(struct net_device *net_dev) | |
1339 | { | |
1340 | struct efx_nic *efx = net_dev->priv; | |
1341 | int rc; | |
1342 | ||
1343 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1344 | raw_smp_processor_id()); | |
1345 | ||
1346 | /* Stop the device and flush all the channels */ | |
1347 | efx_stop_all(efx); | |
1348 | efx_fini_channels(efx); | |
1349 | rc = efx_init_channels(efx); | |
1350 | if (rc) | |
1351 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1352 | ||
1353 | return 0; | |
1354 | } | |
1355 | ||
5b9e207c | 1356 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1357 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1358 | { | |
1359 | struct efx_nic *efx = net_dev->priv; | |
1360 | struct efx_mac_stats *mac_stats = &efx->mac_stats; | |
1361 | struct net_device_stats *stats = &net_dev->stats; | |
1362 | ||
5b9e207c BH |
1363 | /* Update stats if possible, but do not wait if another thread |
1364 | * is updating them (or resetting the NIC); slightly stale | |
1365 | * stats are acceptable. | |
1366 | */ | |
8ceee660 BH |
1367 | if (!spin_trylock(&efx->stats_lock)) |
1368 | return stats; | |
1369 | if (efx->state == STATE_RUNNING) { | |
1370 | falcon_update_stats_xmac(efx); | |
1371 | falcon_update_nic_stats(efx); | |
1372 | } | |
1373 | spin_unlock(&efx->stats_lock); | |
1374 | ||
1375 | stats->rx_packets = mac_stats->rx_packets; | |
1376 | stats->tx_packets = mac_stats->tx_packets; | |
1377 | stats->rx_bytes = mac_stats->rx_bytes; | |
1378 | stats->tx_bytes = mac_stats->tx_bytes; | |
1379 | stats->multicast = mac_stats->rx_multicast; | |
1380 | stats->collisions = mac_stats->tx_collision; | |
1381 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1382 | mac_stats->rx_length_error); | |
1383 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1384 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1385 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1386 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1387 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1388 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1389 | ||
1390 | stats->rx_errors = (stats->rx_length_errors + | |
1391 | stats->rx_over_errors + | |
1392 | stats->rx_crc_errors + | |
1393 | stats->rx_frame_errors + | |
1394 | stats->rx_fifo_errors + | |
1395 | stats->rx_missed_errors + | |
1396 | mac_stats->rx_symbol_error); | |
1397 | stats->tx_errors = (stats->tx_window_errors + | |
1398 | mac_stats->tx_bad); | |
1399 | ||
1400 | return stats; | |
1401 | } | |
1402 | ||
1403 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1404 | static void efx_watchdog(struct net_device *net_dev) | |
1405 | { | |
1406 | struct efx_nic *efx = net_dev->priv; | |
1407 | ||
1408 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d: %s\n", | |
1409 | atomic_read(&efx->netif_stop_count), efx->port_enabled, | |
1410 | monitor_reset ? "resetting channels" : "skipping reset"); | |
1411 | ||
1412 | if (monitor_reset) | |
1413 | efx_schedule_reset(efx, RESET_TYPE_MONITOR); | |
1414 | } | |
1415 | ||
1416 | ||
1417 | /* Context: process, rtnl_lock() held. */ | |
1418 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1419 | { | |
1420 | struct efx_nic *efx = net_dev->priv; | |
1421 | int rc = 0; | |
1422 | ||
1423 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1424 | ||
1425 | if (new_mtu > EFX_MAX_MTU) | |
1426 | return -EINVAL; | |
1427 | ||
1428 | efx_stop_all(efx); | |
1429 | ||
1430 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1431 | ||
1432 | efx_fini_channels(efx); | |
1433 | net_dev->mtu = new_mtu; | |
1434 | rc = efx_init_channels(efx); | |
1435 | if (rc) | |
1436 | goto fail; | |
1437 | ||
1438 | efx_start_all(efx); | |
1439 | return rc; | |
1440 | ||
1441 | fail: | |
1442 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1443 | return rc; | |
1444 | } | |
1445 | ||
1446 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1447 | { | |
1448 | struct efx_nic *efx = net_dev->priv; | |
1449 | struct sockaddr *addr = data; | |
1450 | char *new_addr = addr->sa_data; | |
1451 | ||
1452 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1453 | ||
1454 | if (!is_valid_ether_addr(new_addr)) { | |
1455 | DECLARE_MAC_BUF(mac); | |
1456 | EFX_ERR(efx, "invalid ethernet MAC address requested: %s\n", | |
1457 | print_mac(mac, new_addr)); | |
1458 | return -EINVAL; | |
1459 | } | |
1460 | ||
1461 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1462 | ||
1463 | /* Reconfigure the MAC */ | |
1464 | efx_reconfigure_port(efx); | |
1465 | ||
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1470 | static void efx_set_multicast_list(struct net_device *net_dev) | |
1471 | { | |
1472 | struct efx_nic *efx = net_dev->priv; | |
1473 | struct dev_mc_list *mc_list = net_dev->mc_list; | |
1474 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
1475 | int promiscuous; | |
1476 | u32 crc; | |
1477 | int bit; | |
1478 | int i; | |
1479 | ||
1480 | /* Set per-MAC promiscuity flag and reconfigure MAC if necessary */ | |
1481 | promiscuous = (net_dev->flags & IFF_PROMISC) ? 1 : 0; | |
1482 | if (efx->promiscuous != promiscuous) { | |
1483 | efx->promiscuous = promiscuous; | |
1484 | /* Close the window between efx_stop_port() and efx_flush_all() | |
1485 | * by only queuing work when the port is enabled. */ | |
1486 | if (efx->port_enabled) | |
1487 | queue_work(efx->workqueue, &efx->reconfigure_work); | |
1488 | } | |
1489 | ||
1490 | /* Build multicast hash table */ | |
1491 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1492 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1493 | } else { | |
1494 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1495 | for (i = 0; i < net_dev->mc_count; i++) { | |
1496 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1497 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1498 | set_bit_le(bit, mc_hash->byte); | |
1499 | mc_list = mc_list->next; | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | /* Create and activate new global multicast hash table */ | |
1504 | falcon_set_multicast_hash(efx); | |
1505 | } | |
1506 | ||
1507 | static int efx_netdev_event(struct notifier_block *this, | |
1508 | unsigned long event, void *ptr) | |
1509 | { | |
d3208b5e | 1510 | struct net_device *net_dev = ptr; |
8ceee660 BH |
1511 | |
1512 | if (net_dev->open == efx_net_open && event == NETDEV_CHANGENAME) { | |
1513 | struct efx_nic *efx = net_dev->priv; | |
1514 | ||
1515 | strcpy(efx->name, net_dev->name); | |
1516 | } | |
1517 | ||
1518 | return NOTIFY_DONE; | |
1519 | } | |
1520 | ||
1521 | static struct notifier_block efx_netdev_notifier = { | |
1522 | .notifier_call = efx_netdev_event, | |
1523 | }; | |
1524 | ||
1525 | static int efx_register_netdev(struct efx_nic *efx) | |
1526 | { | |
1527 | struct net_device *net_dev = efx->net_dev; | |
1528 | int rc; | |
1529 | ||
1530 | net_dev->watchdog_timeo = 5 * HZ; | |
1531 | net_dev->irq = efx->pci_dev->irq; | |
1532 | net_dev->open = efx_net_open; | |
1533 | net_dev->stop = efx_net_stop; | |
1534 | net_dev->get_stats = efx_net_stats; | |
1535 | net_dev->tx_timeout = &efx_watchdog; | |
1536 | net_dev->hard_start_xmit = efx_hard_start_xmit; | |
1537 | net_dev->do_ioctl = efx_ioctl; | |
1538 | net_dev->change_mtu = efx_change_mtu; | |
1539 | net_dev->set_mac_address = efx_set_mac_address; | |
1540 | net_dev->set_multicast_list = efx_set_multicast_list; | |
1541 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1542 | net_dev->poll_controller = efx_netpoll; | |
1543 | #endif | |
1544 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); | |
1545 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1546 | ||
1547 | /* Always start with carrier off; PHY events will detect the link */ | |
1548 | netif_carrier_off(efx->net_dev); | |
1549 | ||
1550 | /* Clear MAC statistics */ | |
1551 | falcon_update_stats_xmac(efx); | |
1552 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); | |
1553 | ||
1554 | rc = register_netdev(net_dev); | |
1555 | if (rc) { | |
1556 | EFX_ERR(efx, "could not register net dev\n"); | |
1557 | return rc; | |
1558 | } | |
1559 | strcpy(efx->name, net_dev->name); | |
1560 | ||
1561 | return 0; | |
1562 | } | |
1563 | ||
1564 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1565 | { | |
1566 | struct efx_tx_queue *tx_queue; | |
1567 | ||
1568 | if (!efx->net_dev) | |
1569 | return; | |
1570 | ||
1571 | BUG_ON(efx->net_dev->priv != efx); | |
1572 | ||
1573 | /* Free up any skbs still remaining. This has to happen before | |
1574 | * we try to unregister the netdev as running their destructors | |
1575 | * may be needed to get the device ref. count to 0. */ | |
1576 | efx_for_each_tx_queue(tx_queue, efx) | |
1577 | efx_release_tx_buffers(tx_queue); | |
1578 | ||
55668611 | 1579 | if (efx_dev_registered(efx)) { |
8ceee660 BH |
1580 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
1581 | unregister_netdev(efx->net_dev); | |
1582 | } | |
1583 | } | |
1584 | ||
1585 | /************************************************************************** | |
1586 | * | |
1587 | * Device reset and suspend | |
1588 | * | |
1589 | **************************************************************************/ | |
1590 | ||
1591 | /* The final hardware and software finalisation before reset. */ | |
1592 | static int efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
1593 | { | |
1594 | int rc; | |
1595 | ||
1596 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1597 | ||
1598 | rc = falcon_xmac_get_settings(efx, ecmd); | |
1599 | if (rc) { | |
1600 | EFX_ERR(efx, "could not back up PHY settings\n"); | |
1601 | goto fail; | |
1602 | } | |
1603 | ||
1604 | efx_fini_channels(efx); | |
1605 | return 0; | |
1606 | ||
1607 | fail: | |
1608 | return rc; | |
1609 | } | |
1610 | ||
1611 | /* The first part of software initialisation after a hardware reset | |
1612 | * This function does not handle serialisation with the kernel, it | |
1613 | * assumes the caller has done this */ | |
1614 | static int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
1615 | { | |
1616 | int rc; | |
1617 | ||
1618 | rc = efx_init_channels(efx); | |
1619 | if (rc) | |
1620 | goto fail1; | |
1621 | ||
1622 | /* Restore MAC and PHY settings. */ | |
1623 | rc = falcon_xmac_set_settings(efx, ecmd); | |
1624 | if (rc) { | |
1625 | EFX_ERR(efx, "could not restore PHY settings\n"); | |
1626 | goto fail2; | |
1627 | } | |
1628 | ||
1629 | return 0; | |
1630 | ||
1631 | fail2: | |
1632 | efx_fini_channels(efx); | |
1633 | fail1: | |
1634 | return rc; | |
1635 | } | |
1636 | ||
1637 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1638 | * Note that the reset may fail, in which case the card will be left | |
1639 | * in a most-probably-unusable state. | |
1640 | * | |
1641 | * This function will sleep. You cannot reset from within an atomic | |
1642 | * state; use efx_schedule_reset() instead. | |
1643 | * | |
1644 | * Grabs the rtnl_lock. | |
1645 | */ | |
1646 | static int efx_reset(struct efx_nic *efx) | |
1647 | { | |
1648 | struct ethtool_cmd ecmd; | |
1649 | enum reset_type method = efx->reset_pending; | |
1650 | int rc; | |
1651 | ||
1652 | /* Serialise with kernel interfaces */ | |
1653 | rtnl_lock(); | |
1654 | ||
1655 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1656 | * flag set so that efx_pci_probe_main will be retried */ | |
1657 | if (efx->state != STATE_RUNNING) { | |
1658 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
1659 | goto unlock_rtnl; | |
1660 | } | |
1661 | ||
1662 | efx->state = STATE_RESETTING; | |
1663 | EFX_INFO(efx, "resetting (%d)\n", method); | |
1664 | ||
1665 | /* The net_dev->get_stats handler is quite slow, and will fail | |
1666 | * if a fetch is pending over reset. Serialise against it. */ | |
1667 | spin_lock(&efx->stats_lock); | |
1668 | spin_unlock(&efx->stats_lock); | |
1669 | ||
1670 | efx_stop_all(efx); | |
1671 | mutex_lock(&efx->mac_lock); | |
1672 | ||
1673 | rc = efx_reset_down(efx, &ecmd); | |
1674 | if (rc) | |
1675 | goto fail1; | |
1676 | ||
1677 | rc = falcon_reset_hw(efx, method); | |
1678 | if (rc) { | |
1679 | EFX_ERR(efx, "failed to reset hardware\n"); | |
1680 | goto fail2; | |
1681 | } | |
1682 | ||
1683 | /* Allow resets to be rescheduled. */ | |
1684 | efx->reset_pending = RESET_TYPE_NONE; | |
1685 | ||
1686 | /* Reinitialise bus-mastering, which may have been turned off before | |
1687 | * the reset was scheduled. This is still appropriate, even in the | |
1688 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1689 | * can respond to requests. */ | |
1690 | pci_set_master(efx->pci_dev); | |
1691 | ||
1692 | /* Reinitialise device. This is appropriate in the RESET_TYPE_DISABLE | |
1693 | * case so the driver can talk to external SRAM */ | |
1694 | rc = falcon_init_nic(efx); | |
1695 | if (rc) { | |
1696 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
1697 | goto fail3; | |
1698 | } | |
1699 | ||
1700 | /* Leave device stopped if necessary */ | |
1701 | if (method == RESET_TYPE_DISABLE) { | |
1702 | /* Reinitialise the device anyway so the driver unload sequence | |
1703 | * can talk to the external SRAM */ | |
91ad757c | 1704 | falcon_init_nic(efx); |
8ceee660 BH |
1705 | rc = -EIO; |
1706 | goto fail4; | |
1707 | } | |
1708 | ||
1709 | rc = efx_reset_up(efx, &ecmd); | |
1710 | if (rc) | |
1711 | goto fail5; | |
1712 | ||
1713 | mutex_unlock(&efx->mac_lock); | |
1714 | EFX_LOG(efx, "reset complete\n"); | |
1715 | ||
1716 | efx->state = STATE_RUNNING; | |
1717 | efx_start_all(efx); | |
1718 | ||
1719 | unlock_rtnl: | |
1720 | rtnl_unlock(); | |
1721 | return 0; | |
1722 | ||
1723 | fail5: | |
1724 | fail4: | |
1725 | fail3: | |
1726 | fail2: | |
1727 | fail1: | |
1728 | EFX_ERR(efx, "has been disabled\n"); | |
1729 | efx->state = STATE_DISABLED; | |
1730 | ||
1731 | mutex_unlock(&efx->mac_lock); | |
1732 | rtnl_unlock(); | |
1733 | efx_unregister_netdev(efx); | |
1734 | efx_fini_port(efx); | |
1735 | return rc; | |
1736 | } | |
1737 | ||
1738 | /* The worker thread exists so that code that cannot sleep can | |
1739 | * schedule a reset for later. | |
1740 | */ | |
1741 | static void efx_reset_work(struct work_struct *data) | |
1742 | { | |
1743 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1744 | ||
1745 | efx_reset(nic); | |
1746 | } | |
1747 | ||
1748 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1749 | { | |
1750 | enum reset_type method; | |
1751 | ||
1752 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1753 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1754 | return; | |
1755 | } | |
1756 | ||
1757 | switch (type) { | |
1758 | case RESET_TYPE_INVISIBLE: | |
1759 | case RESET_TYPE_ALL: | |
1760 | case RESET_TYPE_WORLD: | |
1761 | case RESET_TYPE_DISABLE: | |
1762 | method = type; | |
1763 | break; | |
1764 | case RESET_TYPE_RX_RECOVERY: | |
1765 | case RESET_TYPE_RX_DESC_FETCH: | |
1766 | case RESET_TYPE_TX_DESC_FETCH: | |
1767 | case RESET_TYPE_TX_SKIP: | |
1768 | method = RESET_TYPE_INVISIBLE; | |
1769 | break; | |
1770 | default: | |
1771 | method = RESET_TYPE_ALL; | |
1772 | break; | |
1773 | } | |
1774 | ||
1775 | if (method != type) | |
1776 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1777 | else | |
1778 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1779 | ||
1780 | efx->reset_pending = method; | |
1781 | ||
8d9853d9 | 1782 | queue_work(efx->reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1783 | } |
1784 | ||
1785 | /************************************************************************** | |
1786 | * | |
1787 | * List of NICs we support | |
1788 | * | |
1789 | **************************************************************************/ | |
1790 | ||
1791 | /* PCI device ID table */ | |
1792 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1793 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1794 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1795 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1796 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1797 | {0} /* end of list */ | |
1798 | }; | |
1799 | ||
1800 | /************************************************************************** | |
1801 | * | |
1802 | * Dummy PHY/MAC/Board operations | |
1803 | * | |
1804 | * Can be used where the MAC does not implement this operation | |
1805 | * Needed so all function pointers are valid and do not have to be tested | |
1806 | * before use | |
1807 | * | |
1808 | **************************************************************************/ | |
1809 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1810 | { | |
1811 | return 0; | |
1812 | } | |
1813 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
1814 | void efx_port_dummy_op_blink(struct efx_nic *efx, int blink) {} | |
1815 | ||
1816 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
1817 | .init = efx_port_dummy_op_int, | |
1818 | .reconfigure = efx_port_dummy_op_void, | |
1819 | .check_hw = efx_port_dummy_op_int, | |
1820 | .fini = efx_port_dummy_op_void, | |
1821 | .clear_interrupt = efx_port_dummy_op_void, | |
1822 | .reset_xaui = efx_port_dummy_op_void, | |
1823 | }; | |
1824 | ||
1825 | /* Dummy board operations */ | |
1826 | static int efx_nic_dummy_op_int(struct efx_nic *nic) | |
1827 | { | |
1828 | return 0; | |
1829 | } | |
1830 | ||
1831 | static struct efx_board efx_dummy_board_info = { | |
1832 | .init = efx_nic_dummy_op_int, | |
1833 | .init_leds = efx_port_dummy_op_int, | |
1834 | .set_fault_led = efx_port_dummy_op_blink, | |
37b5a603 | 1835 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
1836 | }; |
1837 | ||
1838 | /************************************************************************** | |
1839 | * | |
1840 | * Data housekeeping | |
1841 | * | |
1842 | **************************************************************************/ | |
1843 | ||
1844 | /* This zeroes out and then fills in the invariants in a struct | |
1845 | * efx_nic (including all sub-structures). | |
1846 | */ | |
1847 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1848 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1849 | { | |
1850 | struct efx_channel *channel; | |
1851 | struct efx_tx_queue *tx_queue; | |
1852 | struct efx_rx_queue *rx_queue; | |
1853 | int i, rc; | |
1854 | ||
1855 | /* Initialise common structures */ | |
1856 | memset(efx, 0, sizeof(*efx)); | |
1857 | spin_lock_init(&efx->biu_lock); | |
1858 | spin_lock_init(&efx->phy_lock); | |
1859 | INIT_WORK(&efx->reset_work, efx_reset_work); | |
1860 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1861 | efx->pci_dev = pci_dev; | |
1862 | efx->state = STATE_INIT; | |
1863 | efx->reset_pending = RESET_TYPE_NONE; | |
1864 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
1865 | efx->board_info = efx_dummy_board_info; | |
1866 | ||
1867 | efx->net_dev = net_dev; | |
1868 | efx->rx_checksum_enabled = 1; | |
1869 | spin_lock_init(&efx->netif_stop_lock); | |
1870 | spin_lock_init(&efx->stats_lock); | |
1871 | mutex_init(&efx->mac_lock); | |
1872 | efx->phy_op = &efx_dummy_phy_operations; | |
1873 | efx->mii.dev = net_dev; | |
1874 | INIT_WORK(&efx->reconfigure_work, efx_reconfigure_work); | |
1875 | atomic_set(&efx->netif_stop_count, 1); | |
1876 | ||
1877 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1878 | channel = &efx->channel[i]; | |
1879 | channel->efx = efx; | |
1880 | channel->channel = i; | |
1881 | channel->evqnum = i; | |
1882 | channel->work_pending = 0; | |
1883 | } | |
1884 | for (i = 0; i < EFX_MAX_TX_QUEUES; i++) { | |
1885 | tx_queue = &efx->tx_queue[i]; | |
1886 | tx_queue->efx = efx; | |
1887 | tx_queue->queue = i; | |
1888 | tx_queue->buffer = NULL; | |
1889 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1890 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1891 | } |
1892 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1893 | rx_queue = &efx->rx_queue[i]; | |
1894 | rx_queue->efx = efx; | |
1895 | rx_queue->queue = i; | |
1896 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1897 | rx_queue->buffer = NULL; | |
1898 | spin_lock_init(&rx_queue->add_lock); | |
1899 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1900 | } | |
1901 | ||
1902 | efx->type = type; | |
1903 | ||
1904 | /* Sanity-check NIC type */ | |
1905 | EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask & | |
1906 | (efx->type->txd_ring_mask + 1)); | |
1907 | EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask & | |
1908 | (efx->type->rxd_ring_mask + 1)); | |
1909 | EFX_BUG_ON_PARANOID(efx->type->evq_size & | |
1910 | (efx->type->evq_size - 1)); | |
1911 | /* As close as we can get to guaranteeing that we don't overflow */ | |
1912 | EFX_BUG_ON_PARANOID(efx->type->evq_size < | |
1913 | (efx->type->txd_ring_mask + 1 + | |
1914 | efx->type->rxd_ring_mask + 1)); | |
1915 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); | |
1916 | ||
1917 | /* Higher numbered interrupt modes are less capable! */ | |
1918 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1919 | interrupt_mode); | |
1920 | ||
1921 | efx->workqueue = create_singlethread_workqueue("sfc_work"); | |
1922 | if (!efx->workqueue) { | |
1923 | rc = -ENOMEM; | |
1924 | goto fail1; | |
1925 | } | |
1926 | ||
8d9853d9 BH |
1927 | efx->reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
1928 | if (!efx->reset_workqueue) { | |
1929 | rc = -ENOMEM; | |
1930 | goto fail2; | |
1931 | } | |
1932 | ||
8ceee660 BH |
1933 | return 0; |
1934 | ||
8d9853d9 BH |
1935 | fail2: |
1936 | destroy_workqueue(efx->workqueue); | |
1937 | efx->workqueue = NULL; | |
1938 | ||
8ceee660 BH |
1939 | fail1: |
1940 | return rc; | |
1941 | } | |
1942 | ||
1943 | static void efx_fini_struct(struct efx_nic *efx) | |
1944 | { | |
8d9853d9 BH |
1945 | if (efx->reset_workqueue) { |
1946 | destroy_workqueue(efx->reset_workqueue); | |
1947 | efx->reset_workqueue = NULL; | |
1948 | } | |
8ceee660 BH |
1949 | if (efx->workqueue) { |
1950 | destroy_workqueue(efx->workqueue); | |
1951 | efx->workqueue = NULL; | |
1952 | } | |
1953 | } | |
1954 | ||
1955 | /************************************************************************** | |
1956 | * | |
1957 | * PCI interface | |
1958 | * | |
1959 | **************************************************************************/ | |
1960 | ||
1961 | /* Main body of final NIC shutdown code | |
1962 | * This is called only at module unload (or hotplug removal). | |
1963 | */ | |
1964 | static void efx_pci_remove_main(struct efx_nic *efx) | |
1965 | { | |
1966 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1967 | ||
1968 | /* Skip everything if we never obtained a valid membase */ | |
1969 | if (!efx->membase) | |
1970 | return; | |
1971 | ||
1972 | efx_fini_channels(efx); | |
1973 | efx_fini_port(efx); | |
1974 | ||
1975 | /* Shutdown the board, then the NIC and board state */ | |
37b5a603 | 1976 | efx->board_info.fini(efx); |
8ceee660 BH |
1977 | falcon_fini_interrupt(efx); |
1978 | ||
1979 | efx_fini_napi(efx); | |
1980 | efx_remove_all(efx); | |
1981 | } | |
1982 | ||
1983 | /* Final NIC shutdown | |
1984 | * This is called only at module unload (or hotplug removal). | |
1985 | */ | |
1986 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
1987 | { | |
1988 | struct efx_nic *efx; | |
1989 | ||
1990 | efx = pci_get_drvdata(pci_dev); | |
1991 | if (!efx) | |
1992 | return; | |
1993 | ||
1994 | /* Mark the NIC as fini, then stop the interface */ | |
1995 | rtnl_lock(); | |
1996 | efx->state = STATE_FINI; | |
1997 | dev_close(efx->net_dev); | |
1998 | ||
1999 | /* Allow any queued efx_resets() to complete */ | |
2000 | rtnl_unlock(); | |
2001 | ||
2002 | if (efx->membase == NULL) | |
2003 | goto out; | |
2004 | ||
2005 | efx_unregister_netdev(efx); | |
2006 | ||
2007 | /* Wait for any scheduled resets to complete. No more will be | |
2008 | * scheduled from this point because efx_stop_all() has been | |
2009 | * called, we are no longer registered with driverlink, and | |
2010 | * the net_device's have been removed. */ | |
8d9853d9 | 2011 | flush_workqueue(efx->reset_workqueue); |
8ceee660 BH |
2012 | |
2013 | efx_pci_remove_main(efx); | |
2014 | ||
2015 | out: | |
2016 | efx_fini_io(efx); | |
2017 | EFX_LOG(efx, "shutdown successful\n"); | |
2018 | ||
2019 | pci_set_drvdata(pci_dev, NULL); | |
2020 | efx_fini_struct(efx); | |
2021 | free_netdev(efx->net_dev); | |
2022 | }; | |
2023 | ||
2024 | /* Main body of NIC initialisation | |
2025 | * This is called at module load (or hotplug insertion, theoretically). | |
2026 | */ | |
2027 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2028 | { | |
2029 | int rc; | |
2030 | ||
2031 | /* Do start-of-day initialisation */ | |
2032 | rc = efx_probe_all(efx); | |
2033 | if (rc) | |
2034 | goto fail1; | |
2035 | ||
2036 | rc = efx_init_napi(efx); | |
2037 | if (rc) | |
2038 | goto fail2; | |
2039 | ||
2040 | /* Initialise the board */ | |
2041 | rc = efx->board_info.init(efx); | |
2042 | if (rc) { | |
2043 | EFX_ERR(efx, "failed to initialise board\n"); | |
2044 | goto fail3; | |
2045 | } | |
2046 | ||
2047 | rc = falcon_init_nic(efx); | |
2048 | if (rc) { | |
2049 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
2050 | goto fail4; | |
2051 | } | |
2052 | ||
2053 | rc = efx_init_port(efx); | |
2054 | if (rc) { | |
2055 | EFX_ERR(efx, "failed to initialise port\n"); | |
2056 | goto fail5; | |
2057 | } | |
2058 | ||
2059 | rc = efx_init_channels(efx); | |
2060 | if (rc) | |
2061 | goto fail6; | |
2062 | ||
2063 | rc = falcon_init_interrupt(efx); | |
2064 | if (rc) | |
2065 | goto fail7; | |
2066 | ||
2067 | return 0; | |
2068 | ||
2069 | fail7: | |
2070 | efx_fini_channels(efx); | |
2071 | fail6: | |
2072 | efx_fini_port(efx); | |
2073 | fail5: | |
2074 | fail4: | |
2075 | fail3: | |
2076 | efx_fini_napi(efx); | |
2077 | fail2: | |
2078 | efx_remove_all(efx); | |
2079 | fail1: | |
2080 | return rc; | |
2081 | } | |
2082 | ||
2083 | /* NIC initialisation | |
2084 | * | |
2085 | * This is called at module load (or hotplug insertion, | |
2086 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2087 | * sets up and registers the network devices with the kernel and hooks | |
2088 | * the interrupt service routine. It does not prepare the device for | |
2089 | * transmission; this is left to the first time one of the network | |
2090 | * interfaces is brought up (i.e. efx_net_open). | |
2091 | */ | |
2092 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2093 | const struct pci_device_id *entry) | |
2094 | { | |
2095 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2096 | struct net_device *net_dev; | |
2097 | struct efx_nic *efx; | |
2098 | int i, rc; | |
2099 | ||
2100 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2101 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2102 | if (!net_dev) | |
2103 | return -ENOMEM; | |
b9b39b62 BH |
2104 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
2105 | NETIF_F_HIGHDMA | NETIF_F_TSO); | |
8ceee660 BH |
2106 | if (lro) |
2107 | net_dev->features |= NETIF_F_LRO; | |
2108 | efx = net_dev->priv; | |
2109 | pci_set_drvdata(pci_dev, efx); | |
2110 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2111 | if (rc) | |
2112 | goto fail1; | |
2113 | ||
2114 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2115 | ||
2116 | /* Set up basic I/O (BAR mappings etc) */ | |
2117 | rc = efx_init_io(efx); | |
2118 | if (rc) | |
2119 | goto fail2; | |
2120 | ||
2121 | /* No serialisation is required with the reset path because | |
2122 | * we're in STATE_INIT. */ | |
2123 | for (i = 0; i < 5; i++) { | |
2124 | rc = efx_pci_probe_main(efx); | |
2125 | if (rc == 0) | |
2126 | break; | |
2127 | ||
2128 | /* Serialise against efx_reset(). No more resets will be | |
2129 | * scheduled since efx_stop_all() has been called, and we | |
2130 | * have not and never have been registered with either | |
2131 | * the rtnetlink or driverlink layers. */ | |
8d9853d9 | 2132 | flush_workqueue(efx->reset_workqueue); |
8ceee660 BH |
2133 | |
2134 | /* Retry if a recoverably reset event has been scheduled */ | |
2135 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2136 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2137 | goto fail3; | |
2138 | ||
2139 | efx->reset_pending = RESET_TYPE_NONE; | |
2140 | } | |
2141 | ||
2142 | if (rc) { | |
2143 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2144 | goto fail4; | |
2145 | } | |
2146 | ||
2147 | /* Switch to the running state before we expose the device to | |
2148 | * the OS. This is to ensure that the initial gathering of | |
2149 | * MAC stats succeeds. */ | |
2150 | rtnl_lock(); | |
2151 | efx->state = STATE_RUNNING; | |
2152 | rtnl_unlock(); | |
2153 | ||
2154 | rc = efx_register_netdev(efx); | |
2155 | if (rc) | |
2156 | goto fail5; | |
2157 | ||
2158 | EFX_LOG(efx, "initialisation successful\n"); | |
2159 | ||
2160 | return 0; | |
2161 | ||
2162 | fail5: | |
2163 | efx_pci_remove_main(efx); | |
2164 | fail4: | |
2165 | fail3: | |
2166 | efx_fini_io(efx); | |
2167 | fail2: | |
2168 | efx_fini_struct(efx); | |
2169 | fail1: | |
2170 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2171 | free_netdev(net_dev); | |
2172 | return rc; | |
2173 | } | |
2174 | ||
2175 | static struct pci_driver efx_pci_driver = { | |
2176 | .name = EFX_DRIVER_NAME, | |
2177 | .id_table = efx_pci_table, | |
2178 | .probe = efx_pci_probe, | |
2179 | .remove = efx_pci_remove, | |
2180 | }; | |
2181 | ||
2182 | /************************************************************************** | |
2183 | * | |
2184 | * Kernel module interface | |
2185 | * | |
2186 | *************************************************************************/ | |
2187 | ||
2188 | module_param(interrupt_mode, uint, 0444); | |
2189 | MODULE_PARM_DESC(interrupt_mode, | |
2190 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2191 | ||
2192 | static int __init efx_init_module(void) | |
2193 | { | |
2194 | int rc; | |
2195 | ||
2196 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2197 | ||
2198 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2199 | if (rc) | |
2200 | goto err_notifier; | |
2201 | ||
2202 | refill_workqueue = create_workqueue("sfc_refill"); | |
2203 | if (!refill_workqueue) { | |
2204 | rc = -ENOMEM; | |
2205 | goto err_refill; | |
2206 | } | |
2207 | ||
2208 | rc = pci_register_driver(&efx_pci_driver); | |
2209 | if (rc < 0) | |
2210 | goto err_pci; | |
2211 | ||
2212 | return 0; | |
2213 | ||
2214 | err_pci: | |
2215 | destroy_workqueue(refill_workqueue); | |
2216 | err_refill: | |
2217 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2218 | err_notifier: | |
2219 | return rc; | |
2220 | } | |
2221 | ||
2222 | static void __exit efx_exit_module(void) | |
2223 | { | |
2224 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2225 | ||
2226 | pci_unregister_driver(&efx_pci_driver); | |
2227 | destroy_workqueue(refill_workqueue); | |
2228 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2229 | ||
2230 | } | |
2231 | ||
2232 | module_init(efx_init_module); | |
2233 | module_exit(efx_exit_module); | |
2234 | ||
2235 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2236 | "Solarflare Communications"); | |
2237 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2238 | MODULE_LICENSE("GPL"); | |
2239 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |