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[linux-2.6-block.git] / drivers / net / sb1250-mac.c
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LT		 1/*
2 * Copyright (C) 2001,2002,2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 *
19 * This driver is designed for the Broadcom SiByte SOC built-in
20 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
21 */
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/timer.h>
26#include <linux/errno.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/interrupt.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/init.h>
34#include <linux/config.h>
35#include <linux/bitops.h>
36#include <asm/processor.h> /* Processor type for cache alignment. */
37#include <asm/io.h>
38#include <asm/cache.h>
39
40/* This is only here until the firmware is ready. In that case,
41 the firmware leaves the ethernet address in the register for us. */
42#ifdef CONFIG_SIBYTE_STANDALONE
43#define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
44#define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
45#define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
46#endif
47
48
49/* These identify the driver base version and may not be removed. */
50#if 0
51static char version1[] __devinitdata =
52"sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
53#endif
54
55
56/* Operational parameters that usually are not changed. */
57
58#define CONFIG_SBMAC_COALESCE
59
60#define MAX_UNITS 3 /* More are supported, limit only on options */
61
62/* Time in jiffies before concluding the transmitter is hung. */
63#define TX_TIMEOUT (2*HZ)
64
65
66MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
67MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
68
69/* A few user-configurable values which may be modified when a driver
70 module is loaded. */
71
72/* 1 normal messages, 0 quiet .. 7 verbose. */
73static int debug = 1;
74module_param(debug, int, S_IRUGO);
75MODULE_PARM_DESC(debug, "Debug messages");
76
77/* mii status msgs */
78static int noisy_mii = 1;
79module_param(noisy_mii, int, S_IRUGO);
80MODULE_PARM_DESC(noisy_mii, "MII status messages");
81
82/* Used to pass the media type, etc.
83 Both 'options[]' and 'full_duplex[]' should exist for driver
84 interoperability.
85 The media type is usually passed in 'options[]'.
86*/
87#ifdef MODULE
88static int options[MAX_UNITS] = {-1, -1, -1};
89module_param_array(options, int, NULL, S_IRUGO);
90MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
91
92static int full_duplex[MAX_UNITS] = {-1, -1, -1};
93module_param_array(full_duplex, int, NULL, S_IRUGO);
94MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
95#endif
96
97#ifdef CONFIG_SBMAC_COALESCE
98static int int_pktcnt = 0;
99module_param(int_pktcnt, int, S_IRUGO);
100MODULE_PARM_DESC(int_pktcnt, "Packet count");
101
102static int int_timeout = 0;
103module_param(int_timeout, int, S_IRUGO);
104MODULE_PARM_DESC(int_timeout, "Timeout value");
105#endif
106
107#include <asm/sibyte/sb1250.h>
108#include <asm/sibyte/sb1250_defs.h>
109#include <asm/sibyte/sb1250_regs.h>
110#include <asm/sibyte/sb1250_mac.h>
111#include <asm/sibyte/sb1250_dma.h>
112#include <asm/sibyte/sb1250_int.h>
113#include <asm/sibyte/sb1250_scd.h>
114
115
116/**********************************************************************
117 * Simple types
118 ********************************************************************* */
119
120
121typedef unsigned long sbmac_port_t;
122
123typedef enum { sbmac_speed_auto, sbmac_speed_10,
124 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
125
126typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
127 sbmac_duplex_full } sbmac_duplex_t;
128
129typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
130 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
131
132typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
133 sbmac_state_broken } sbmac_state_t;
134
135
136/**********************************************************************
137 * Macros
138 ********************************************************************* */
139
140
141#define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
142 (d)->sbdma_dscrtable : (d)->f+1)
143
144
145#define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
146
147#define SBMAC_READCSR(t) __raw_readq((unsigned long)t)
148#define SBMAC_WRITECSR(t,v) __raw_writeq(v, (unsigned long)t)
149
150
151#define SBMAC_MAX_TXDESCR 32
152#define SBMAC_MAX_RXDESCR 32
153
154#define ETHER_ALIGN 2
155#define ETHER_ADDR_LEN 6
156#define ENET_PACKET_SIZE 1518
157/*#define ENET_PACKET_SIZE 9216 */
158
159/**********************************************************************
160 * DMA Descriptor structure
161 ********************************************************************* */
162
163typedef struct sbdmadscr_s {
164 uint64_t dscr_a;
165 uint64_t dscr_b;
166} sbdmadscr_t;
167
168typedef unsigned long paddr_t;
169
170/**********************************************************************
171 * DMA Controller structure
172 ********************************************************************* */
173
174typedef struct sbmacdma_s {
175
176 /*
177 * This stuff is used to identify the channel and the registers
178 * associated with it.
179 */
180
181 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */
182 int sbdma_channel; /* channel number */
183 int sbdma_txdir; /* direction (1=transmit) */
184 int sbdma_maxdescr; /* total # of descriptors in ring */
185#ifdef CONFIG_SBMAC_COALESCE
186 int sbdma_int_pktcnt; /* # descriptors rx/tx before interrupt*/
187 int sbdma_int_timeout; /* # usec rx/tx interrupt */
188#endif
189
190 sbmac_port_t sbdma_config0; /* DMA config register 0 */
191 sbmac_port_t sbdma_config1; /* DMA config register 1 */
192 sbmac_port_t sbdma_dscrbase; /* Descriptor base address */
193 sbmac_port_t sbdma_dscrcnt; /* Descriptor count register */
194 sbmac_port_t sbdma_curdscr; /* current descriptor address */
195
196 /*
197 * This stuff is for maintenance of the ring
198 */
199
200 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */
201 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */
202
203 struct sk_buff **sbdma_ctxtable; /* context table, one per descr */
204
205 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */
206 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */
207 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */
208} sbmacdma_t;
209
210
211/**********************************************************************
212 * Ethernet softc structure
213 ********************************************************************* */
214
215struct sbmac_softc {
216
217 /*
218 * Linux-specific things
219 */
220
221 struct net_device *sbm_dev; /* pointer to linux device */
222 spinlock_t sbm_lock; /* spin lock */
223 struct timer_list sbm_timer; /* for monitoring MII */
224 struct net_device_stats sbm_stats;
225 int sbm_devflags; /* current device flags */
226
227 int sbm_phy_oldbmsr;
228 int sbm_phy_oldanlpar;
229 int sbm_phy_oldk1stsr;
230 int sbm_phy_oldlinkstat;
231 int sbm_buffersize;
232
233 unsigned char sbm_phys[2];
234
235 /*
236 * Controller-specific things
237 */
238
239 unsigned long sbm_base; /* MAC's base address */
240 sbmac_state_t sbm_state; /* current state */
241
242 sbmac_port_t sbm_macenable; /* MAC Enable Register */
243 sbmac_port_t sbm_maccfg; /* MAC Configuration Register */
244 sbmac_port_t sbm_fifocfg; /* FIFO configuration register */
245 sbmac_port_t sbm_framecfg; /* Frame configuration register */
246 sbmac_port_t sbm_rxfilter; /* receive filter register */
247 sbmac_port_t sbm_isr; /* Interrupt status register */
248 sbmac_port_t sbm_imr; /* Interrupt mask register */
249 sbmac_port_t sbm_mdio; /* MDIO register */
250
251 sbmac_speed_t sbm_speed; /* current speed */
252 sbmac_duplex_t sbm_duplex; /* current duplex */
253 sbmac_fc_t sbm_fc; /* current flow control setting */
254
255 unsigned char sbm_hwaddr[ETHER_ADDR_LEN];
256
257 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */
258 sbmacdma_t sbm_rxdma;
259 int rx_hw_checksum;
260 int sbe_idx;
261};
262
263
264/**********************************************************************
265 * Externs
266 ********************************************************************* */
267
268/**********************************************************************
269 * Prototypes
270 ********************************************************************* */
271
272static void sbdma_initctx(sbmacdma_t *d,
273 struct sbmac_softc *s,
274 int chan,
275 int txrx,
276 int maxdescr);
277static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
278static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
279static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
280static void sbdma_emptyring(sbmacdma_t *d);
281static void sbdma_fillring(sbmacdma_t *d);
282static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d);
283static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d);
284static int sbmac_initctx(struct sbmac_softc *s);
285static void sbmac_channel_start(struct sbmac_softc *s);
286static void sbmac_channel_stop(struct sbmac_softc *s);
287static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
288static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
289static uint64_t sbmac_addr2reg(unsigned char *ptr);
290static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs);
291static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
292static void sbmac_setmulti(struct sbmac_softc *sc);
293static int sbmac_init(struct net_device *dev, int idx);
294static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
295static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
296
297static int sbmac_open(struct net_device *dev);
298static void sbmac_timer(unsigned long data);
299static void sbmac_tx_timeout (struct net_device *dev);
300static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
301static void sbmac_set_rx_mode(struct net_device *dev);
302static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
303static int sbmac_close(struct net_device *dev);
304static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
305
306static void sbmac_mii_sync(struct sbmac_softc *s);
307static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
308static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
309static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
310 unsigned int regval);
311
312
313/**********************************************************************
314 * Globals
315 ********************************************************************* */
316
317static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
318
319
320/**********************************************************************
321 * MDIO constants
322 ********************************************************************* */
323
324#define MII_COMMAND_START 0x01
325#define MII_COMMAND_READ 0x02
326#define MII_COMMAND_WRITE 0x01
327#define MII_COMMAND_ACK 0x02
328
329#define BMCR_RESET 0x8000
330#define BMCR_LOOPBACK 0x4000
331#define BMCR_SPEED0 0x2000
332#define BMCR_ANENABLE 0x1000
333#define BMCR_POWERDOWN 0x0800
334#define BMCR_ISOLATE 0x0400
335#define BMCR_RESTARTAN 0x0200
336#define BMCR_DUPLEX 0x0100
337#define BMCR_COLTEST 0x0080
338#define BMCR_SPEED1 0x0040
339#define BMCR_SPEED1000 BMCR_SPEED1
340#define BMCR_SPEED100 BMCR_SPEED0
341#define BMCR_SPEED10 0
342
343#define BMSR_100BT4 0x8000
344#define BMSR_100BT_FDX 0x4000
345#define BMSR_100BT_HDX 0x2000
346#define BMSR_10BT_FDX 0x1000
347#define BMSR_10BT_HDX 0x0800
348#define BMSR_100BT2_FDX 0x0400
349#define BMSR_100BT2_HDX 0x0200
350#define BMSR_1000BT_XSR 0x0100
351#define BMSR_PRESUP 0x0040
352#define BMSR_ANCOMPLT 0x0020
353#define BMSR_REMFAULT 0x0010
354#define BMSR_AUTONEG 0x0008
355#define BMSR_LINKSTAT 0x0004
356#define BMSR_JABDETECT 0x0002
357#define BMSR_EXTCAPAB 0x0001
358
359#define PHYIDR1 0x2000
360#define PHYIDR2 0x5C60
361
362#define ANAR_NP 0x8000
363#define ANAR_RF 0x2000
364#define ANAR_ASYPAUSE 0x0800
365#define ANAR_PAUSE 0x0400
366#define ANAR_T4 0x0200
367#define ANAR_TXFD 0x0100
368#define ANAR_TXHD 0x0080
369#define ANAR_10FD 0x0040
370#define ANAR_10HD 0x0020
371#define ANAR_PSB 0x0001
372
373#define ANLPAR_NP 0x8000
374#define ANLPAR_ACK 0x4000
375#define ANLPAR_RF 0x2000
376#define ANLPAR_ASYPAUSE 0x0800
377#define ANLPAR_PAUSE 0x0400
378#define ANLPAR_T4 0x0200
379#define ANLPAR_TXFD 0x0100
380#define ANLPAR_TXHD 0x0080
381#define ANLPAR_10FD 0x0040
382#define ANLPAR_10HD 0x0020
383#define ANLPAR_PSB 0x0001 /* 802.3 */
384
385#define ANER_PDF 0x0010
386#define ANER_LPNPABLE 0x0008
387#define ANER_NPABLE 0x0004
388#define ANER_PAGERX 0x0002
389#define ANER_LPANABLE 0x0001
390
391#define ANNPTR_NP 0x8000
392#define ANNPTR_MP 0x2000
393#define ANNPTR_ACK2 0x1000
394#define ANNPTR_TOGTX 0x0800
395#define ANNPTR_CODE 0x0008
396
397#define ANNPRR_NP 0x8000
398#define ANNPRR_MP 0x2000
399#define ANNPRR_ACK3 0x1000
400#define ANNPRR_TOGTX 0x0800
401#define ANNPRR_CODE 0x0008
402
403#define K1TCR_TESTMODE 0x0000
404#define K1TCR_MSMCE 0x1000
405#define K1TCR_MSCV 0x0800
406#define K1TCR_RPTR 0x0400
407#define K1TCR_1000BT_FDX 0x200
408#define K1TCR_1000BT_HDX 0x100
409
410#define K1STSR_MSMCFLT 0x8000
411#define K1STSR_MSCFGRES 0x4000
412#define K1STSR_LRSTAT 0x2000
413#define K1STSR_RRSTAT 0x1000
414#define K1STSR_LP1KFD 0x0800
415#define K1STSR_LP1KHD 0x0400
416#define K1STSR_LPASMDIR 0x0200
417
418#define K1SCR_1KX_FDX 0x8000
419#define K1SCR_1KX_HDX 0x4000
420#define K1SCR_1KT_FDX 0x2000
421#define K1SCR_1KT_HDX 0x1000
422
423#define STRAP_PHY1 0x0800
424#define STRAP_NCMODE 0x0400
425#define STRAP_MANMSCFG 0x0200
426#define STRAP_ANENABLE 0x0100
427#define STRAP_MSVAL 0x0080
428#define STRAP_1KHDXADV 0x0010
429#define STRAP_1KFDXADV 0x0008
430#define STRAP_100ADV 0x0004
431#define STRAP_SPEEDSEL 0x0000
432#define STRAP_SPEED100 0x0001
433
434#define PHYSUP_SPEED1000 0x10
435#define PHYSUP_SPEED100 0x08
436#define PHYSUP_SPEED10 0x00
437#define PHYSUP_LINKUP 0x04
438#define PHYSUP_FDX 0x02
439
440#define MII_BMCR 0x00 /* Basic mode control register (rw) */
441#define MII_BMSR 0x01 /* Basic mode status register (ro) */
442#define MII_K1STSR 0x0A /* 1K Status Register (ro) */
443#define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
444
445
446#define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
447
448#define ENABLE 1
449#define DISABLE 0
450
451/**********************************************************************
452 * SBMAC_MII_SYNC(s)
453 *
454 * Synchronize with the MII - send a pattern of bits to the MII
455 * that will guarantee that it is ready to accept a command.
456 *
457 * Input parameters:
458 * s - sbmac structure
459 *
460 * Return value:
461 * nothing
462 ********************************************************************* */
463
464static void sbmac_mii_sync(struct sbmac_softc *s)
465{
466 int cnt;
467 uint64_t bits;
468 int mac_mdio_genc;
469
470 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
471
472 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
473
474 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
475
476 for (cnt = 0; cnt < 32; cnt++) {
477 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc);
478 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
479 }
480}
481
482/**********************************************************************
483 * SBMAC_MII_SENDDATA(s,data,bitcnt)
484 *
485 * Send some bits to the MII. The bits to be sent are right-
486 * justified in the 'data' parameter.
487 *
488 * Input parameters:
489 * s - sbmac structure
490 * data - data to send
491 * bitcnt - number of bits to send
492 ********************************************************************* */
493
494static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
495{
496 int i;
497 uint64_t bits;
498 unsigned int curmask;
499 int mac_mdio_genc;
500
501 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
502
503 bits = M_MAC_MDIO_DIR_OUTPUT;
504 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
505
506 curmask = 1 << (bitcnt - 1);
507
508 for (i = 0; i < bitcnt; i++) {
509 if (data & curmask)
510 bits |= M_MAC_MDIO_OUT;
511 else bits &= ~M_MAC_MDIO_OUT;
512 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
513 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc);
514 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
515 curmask >>= 1;
516 }
517}
518
519
520
521/**********************************************************************
522 * SBMAC_MII_READ(s,phyaddr,regidx)
523 *
524 * Read a PHY register.
525 *
526 * Input parameters:
527 * s - sbmac structure
528 * phyaddr - PHY's address
529 * regidx = index of register to read
530 *
531 * Return value:
532 * value read, or 0 if an error occurred.
533 ********************************************************************* */
534
535static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
536{
537 int idx;
538 int error;
539 int regval;
540 int mac_mdio_genc;
541
542 /*
543 * Synchronize ourselves so that the PHY knows the next
544 * thing coming down is a command
545 */
546
547 sbmac_mii_sync(s);
548
549 /*
550 * Send the data to the PHY. The sequence is
551 * a "start" command (2 bits)
552 * a "read" command (2 bits)
553 * the PHY addr (5 bits)
554 * the register index (5 bits)
555 */
556
557 sbmac_mii_senddata(s,MII_COMMAND_START, 2);
558 sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
559 sbmac_mii_senddata(s,phyaddr, 5);
560 sbmac_mii_senddata(s,regidx, 5);
561
562 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
563
564 /*
565 * Switch the port around without a clock transition.
566 */
567 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
568
569 /*
570 * Send out a clock pulse to signal we want the status
571 */
572
573 SBMAC_WRITECSR(s->sbm_mdio,
574 M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc);
575 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
576
577 /*
578 * If an error occurred, the PHY will signal '1' back
579 */
580 error = SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN;
581
582 /*
583 * Issue an 'idle' clock pulse, but keep the direction
584 * the same.
585 */
586 SBMAC_WRITECSR(s->sbm_mdio,
587 M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc);
588 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
589
590 regval = 0;
591
592 for (idx = 0; idx < 16; idx++) {
593 regval <<= 1;
594
595 if (error == 0) {
596 if (SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN)
597 regval |= 1;
598 }
599
600 SBMAC_WRITECSR(s->sbm_mdio,
601 M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc);
602 SBMAC_WRITECSR(s->sbm_mdio,
603 M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
604 }
605
606 /* Switch back to output */
607 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc);
608
609 if (error == 0)
610 return regval;
611 return 0;
612}
613
614
615/**********************************************************************
616 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
617 *
618 * Write a value to a PHY register.
619 *
620 * Input parameters:
621 * s - sbmac structure
622 * phyaddr - PHY to use
623 * regidx - register within the PHY
624 * regval - data to write to register
625 *
626 * Return value:
627 * nothing
628 ********************************************************************* */
629
630static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
631 unsigned int regval)
632{
633 int mac_mdio_genc;
634
635 sbmac_mii_sync(s);
636
637 sbmac_mii_senddata(s,MII_COMMAND_START,2);
638 sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
639 sbmac_mii_senddata(s,phyaddr, 5);
640 sbmac_mii_senddata(s,regidx, 5);
641 sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
642 sbmac_mii_senddata(s,regval,16);
643
644 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
645
646 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc);
647}
648
649
650
651/**********************************************************************
652 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
653 *
654 * Initialize a DMA channel context. Since there are potentially
655 * eight DMA channels per MAC, it's nice to do this in a standard
656 * way.
657 *
658 * Input parameters:
659 * d - sbmacdma_t structure (DMA channel context)
660 * s - sbmac_softc structure (pointer to a MAC)
661 * chan - channel number (0..1 right now)
662 * txrx - Identifies DMA_TX or DMA_RX for channel direction
663 * maxdescr - number of descriptors
664 *
665 * Return value:
666 * nothing
667 ********************************************************************* */
668
669static void sbdma_initctx(sbmacdma_t *d,
670 struct sbmac_softc *s,
671 int chan,
672 int txrx,
673 int maxdescr)
674{
675 /*
676 * Save away interesting stuff in the structure
677 */
678
679 d->sbdma_eth = s;
680 d->sbdma_channel = chan;
681 d->sbdma_txdir = txrx;
682
683#if 0
684 /* RMON clearing */
685 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
686#endif
687
688 SBMAC_WRITECSR(IOADDR(
689 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)), 0);
690 SBMAC_WRITECSR(IOADDR(
691 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)), 0);
692 SBMAC_WRITECSR(IOADDR(
693 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)), 0);
694 SBMAC_WRITECSR(IOADDR(
695 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)), 0);
696 SBMAC_WRITECSR(IOADDR(
697 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)), 0);
698 SBMAC_WRITECSR(IOADDR(
699 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)), 0);
700 SBMAC_WRITECSR(IOADDR(
701 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)), 0);
702 SBMAC_WRITECSR(IOADDR(
703 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)), 0);
704 SBMAC_WRITECSR(IOADDR(
705 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)), 0);
706 SBMAC_WRITECSR(IOADDR(
707 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)), 0);
708 SBMAC_WRITECSR(IOADDR(
709 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)), 0);
710 SBMAC_WRITECSR(IOADDR(
711 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)), 0);
712 SBMAC_WRITECSR(IOADDR(
713 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)), 0);
714 SBMAC_WRITECSR(IOADDR(
715 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)), 0);
716 SBMAC_WRITECSR(IOADDR(
717 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)), 0);
718 SBMAC_WRITECSR(IOADDR(
719 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)), 0);
720 SBMAC_WRITECSR(IOADDR(
721 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)), 0);
722 SBMAC_WRITECSR(IOADDR(
723 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)), 0);
724 SBMAC_WRITECSR(IOADDR(
725 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)), 0);
726 SBMAC_WRITECSR(IOADDR(
727 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)), 0);
728 SBMAC_WRITECSR(IOADDR(
729 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)), 0);
730
731 /*
732 * initialize register pointers
733 */
734
735 d->sbdma_config0 =
736 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
737 d->sbdma_config1 =
738 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
739 d->sbdma_dscrbase =
740 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
741 d->sbdma_dscrcnt =
742 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
743 d->sbdma_curdscr =
744 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
745
746 /*
747 * Allocate memory for the ring
748 */
749
750 d->sbdma_maxdescr = maxdescr;
751
752 d->sbdma_dscrtable = (sbdmadscr_t *)
04115def
RB		 753 kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL);
754
755 /*
756 * The descriptor table must be aligned to at least 16 bytes or the
757 * MAC will corrupt it.
758 */
759 d->sbdma_dscrtable = (sbdmadscr_t *)
760 ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t));
1da177e4
LT		 761
762 memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
763
764 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
765
766 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
767
768 /*
769 * And context table
770 */
771
772 d->sbdma_ctxtable = (struct sk_buff **)
773 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
774
775 memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
776
777#ifdef CONFIG_SBMAC_COALESCE
778 /*
779 * Setup Rx/Tx DMA coalescing defaults
780 */
781
782 if ( int_pktcnt ) {
783 d->sbdma_int_pktcnt = int_pktcnt;
784 } else {
785 d->sbdma_int_pktcnt = 1;
786 }
787
788 if ( int_timeout ) {
789 d->sbdma_int_timeout = int_timeout;
790 } else {
791 d->sbdma_int_timeout = 0;
792 }
793#endif
794
795}
796
797/**********************************************************************
798 * SBDMA_CHANNEL_START(d)
799 *
800 * Initialize the hardware registers for a DMA channel.
801 *
802 * Input parameters:
803 * d - DMA channel to init (context must be previously init'd
804 * rxtx - DMA_RX or DMA_TX depending on what type of channel
805 *
806 * Return value:
807 * nothing
808 ********************************************************************* */
809
810static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
811{
812 /*
813 * Turn on the DMA channel
814 */
815
816#ifdef CONFIG_SBMAC_COALESCE
817 SBMAC_WRITECSR(d->sbdma_config1,
818 V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
819 0);
820 SBMAC_WRITECSR(d->sbdma_config0,
821 M_DMA_EOP_INT_EN |
822 V_DMA_RINGSZ(d->sbdma_maxdescr) |
823 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
824 0);
825#else
826 SBMAC_WRITECSR(d->sbdma_config1,0);
827 SBMAC_WRITECSR(d->sbdma_config0,
828 V_DMA_RINGSZ(d->sbdma_maxdescr) |
829 0);
830#endif
831
832 SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys);
833
834 /*
835 * Initialize ring pointers
836 */
837
838 d->sbdma_addptr = d->sbdma_dscrtable;
839 d->sbdma_remptr = d->sbdma_dscrtable;
840}
841
842/**********************************************************************
843 * SBDMA_CHANNEL_STOP(d)
844 *
845 * Initialize the hardware registers for a DMA channel.
846 *
847 * Input parameters:
848 * d - DMA channel to init (context must be previously init'd
849 *
850 * Return value:
851 * nothing
852 ********************************************************************* */
853
854static void sbdma_channel_stop(sbmacdma_t *d)
855{
856 /*
857 * Turn off the DMA channel
858 */
859
860 SBMAC_WRITECSR(d->sbdma_config1,0);
861
862 SBMAC_WRITECSR(d->sbdma_dscrbase,0);
863
864 SBMAC_WRITECSR(d->sbdma_config0,0);
865
866 /*
867 * Zero ring pointers
868 */
869
870 d->sbdma_addptr = 0;
871 d->sbdma_remptr = 0;
872}
873
874static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
875{
876 unsigned long addr;
877 unsigned long newaddr;
878
879 addr = (unsigned long) skb->data;
880
881 newaddr = (addr + power2 - 1) & ~(power2 - 1);
882
883 skb_reserve(skb,newaddr-addr+offset);
884}
885
886
887/**********************************************************************
888 * SBDMA_ADD_RCVBUFFER(d,sb)
889 *
890 * Add a buffer to the specified DMA channel. For receive channels,
891 * this queues a buffer for inbound packets.
892 *
893 * Input parameters:
894 * d - DMA channel descriptor
895 * sb - sk_buff to add, or NULL if we should allocate one
896 *
897 * Return value:
898 * 0 if buffer could not be added (ring is full)
899 * 1 if buffer added successfully
900 ********************************************************************* */
901
902
903static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
904{
905 sbdmadscr_t *dsc;
906 sbdmadscr_t *nextdsc;
907 struct sk_buff *sb_new = NULL;
908 int pktsize = ENET_PACKET_SIZE;
909
910 /* get pointer to our current place in the ring */
911
912 dsc = d->sbdma_addptr;
913 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
914
915 /*
916 * figure out if the ring is full - if the next descriptor
917 * is the same as the one that we're going to remove from
918 * the ring, the ring is full
919 */
920
921 if (nextdsc == d->sbdma_remptr) {
922 return -ENOSPC;
923 }
924
925 /*
926 * Allocate a sk_buff if we don't already have one.
927 * If we do have an sk_buff, reset it so that it's empty.
928 *
929 * Note: sk_buffs don't seem to be guaranteed to have any sort
930 * of alignment when they are allocated. Therefore, allocate enough
931 * extra space to make sure that:
932 *
933 * 1. the data does not start in the middle of a cache line.
934 * 2. The data does not end in the middle of a cache line
935 * 3. The buffer can be aligned such that the IP addresses are
936 * naturally aligned.
937 *
938 * Remember, the SOCs MAC writes whole cache lines at a time,
939 * without reading the old contents first. So, if the sk_buff's
940 * data portion starts in the middle of a cache line, the SOC
941 * DMA will trash the beginning (and ending) portions.
942 */
943
944 if (sb == NULL) {
945 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
946 if (sb_new == NULL) {
947 printk(KERN_INFO "%s: sk_buff allocation failed\n",
948 d->sbdma_eth->sbm_dev->name);
949 return -ENOBUFS;
950 }
951
952 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
953
954 /* mark skbuff owned by our device */
955 sb_new->dev = d->sbdma_eth->sbm_dev;
956 }
957 else {
958 sb_new = sb;
959 /*
960 * nothing special to reinit buffer, it's already aligned
961 * and sb->data already points to a good place.
962 */
963 }
964
965 /*
966 * fill in the descriptor
967 */
968
969#ifdef CONFIG_SBMAC_COALESCE
970 /*
971 * Do not interrupt per DMA transfer.
972 */
689be439 973 dsc->dscr_a = virt_to_phys(sb_new->data) |
1da177e4
LT		 974 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
975 0;
976#else
689be439 977 dsc->dscr_a = virt_to_phys(sb_new->data) |
1da177e4
LT		 978 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
979 M_DMA_DSCRA_INTERRUPT;
980#endif
981
982 /* receiving: no options */
983 dsc->dscr_b = 0;
984
985 /*
986 * fill in the context
987 */
988
989 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
990
991 /*
992 * point at next packet
993 */
994
995 d->sbdma_addptr = nextdsc;
996
997 /*
998 * Give the buffer to the DMA engine.
999 */
1000
1001 SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
1002
1003 return 0; /* we did it */
1004}
1005
1006/**********************************************************************
1007 * SBDMA_ADD_TXBUFFER(d,sb)
1008 *
1009 * Add a transmit buffer to the specified DMA channel, causing a
1010 * transmit to start.
1011 *
1012 * Input parameters:
1013 * d - DMA channel descriptor
1014 * sb - sk_buff to add
1015 *
1016 * Return value:
1017 * 0 transmit queued successfully
1018 * otherwise error code
1019 ********************************************************************* */
1020
1021
1022static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1023{
1024 sbdmadscr_t *dsc;
1025 sbdmadscr_t *nextdsc;
1026 uint64_t phys;
1027 uint64_t ncb;
1028 int length;
1029
1030 /* get pointer to our current place in the ring */
1031
1032 dsc = d->sbdma_addptr;
1033 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1034
1035 /*
1036 * figure out if the ring is full - if the next descriptor
1037 * is the same as the one that we're going to remove from
1038 * the ring, the ring is full
1039 */
1040
1041 if (nextdsc == d->sbdma_remptr) {
1042 return -ENOSPC;
1043 }
1044
1045 /*
1046 * Under Linux, it's not necessary to copy/coalesce buffers
1047 * like it is on NetBSD. We think they're all contiguous,
1048 * but that may not be true for GBE.
1049 */
1050
1051 length = sb->len;
1052
1053 /*
1054 * fill in the descriptor. Note that the number of cache
1055 * blocks in the descriptor is the number of blocks
1056 * *spanned*, so we need to add in the offset (if any)
1057 * while doing the calculation.
1058 */
1059
1060 phys = virt_to_phys(sb->data);
1061 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1062
1063 dsc->dscr_a = phys |
1064 V_DMA_DSCRA_A_SIZE(ncb) |
1065#ifndef CONFIG_SBMAC_COALESCE
1066 M_DMA_DSCRA_INTERRUPT |
1067#endif
1068 M_DMA_ETHTX_SOP;
1069
1070 /* transmitting: set outbound options and length */
1071
1072 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1073 V_DMA_DSCRB_PKT_SIZE(length);
1074
1075 /*
1076 * fill in the context
1077 */
1078
1079 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1080
1081 /*
1082 * point at next packet
1083 */
1084
1085 d->sbdma_addptr = nextdsc;
1086
1087 /*
1088 * Give the buffer to the DMA engine.
1089 */
1090
1091 SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
1092
1093 return 0; /* we did it */
1094}
1095
1096
1097
1098
1099/**********************************************************************
1100 * SBDMA_EMPTYRING(d)
1101 *
1102 * Free all allocated sk_buffs on the specified DMA channel;
1103 *
1104 * Input parameters:
1105 * d - DMA channel
1106 *
1107 * Return value:
1108 * nothing
1109 ********************************************************************* */
1110
1111static void sbdma_emptyring(sbmacdma_t *d)
1112{
1113 int idx;
1114 struct sk_buff *sb;
1115
1116 for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1117 sb = d->sbdma_ctxtable[idx];
1118 if (sb) {
1119 dev_kfree_skb(sb);
1120 d->sbdma_ctxtable[idx] = NULL;
1121 }
1122 }
1123}
1124
1125
1126/**********************************************************************
1127 * SBDMA_FILLRING(d)
1128 *
1129 * Fill the specified DMA channel (must be receive channel)
1130 * with sk_buffs
1131 *
1132 * Input parameters:
1133 * d - DMA channel
1134 *
1135 * Return value:
1136 * nothing
1137 ********************************************************************* */
1138
1139static void sbdma_fillring(sbmacdma_t *d)
1140{
1141 int idx;
1142
1143 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1144 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1145 break;
1146 }
1147}
1148
1149
1150/**********************************************************************
1151 * SBDMA_RX_PROCESS(sc,d)
1152 *
1153 * Process "completed" receive buffers on the specified DMA channel.
1154 * Note that this isn't really ideal for priority channels, since
1155 * it processes all of the packets on a given channel before
1156 * returning.
1157 *
1158 * Input parameters:
1159 * sc - softc structure
1160 * d - DMA channel context
1161 *
1162 * Return value:
1163 * nothing
1164 ********************************************************************* */
1165
1166static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1167{
1168 int curidx;
1169 int hwidx;
1170 sbdmadscr_t *dsc;
1171 struct sk_buff *sb;
1172 int len;
1173
1174 for (;;) {
1175 /*
1176 * figure out where we are (as an index) and where
1177 * the hardware is (also as an index)
1178 *
1179 * This could be done faster if (for example) the
1180 * descriptor table was page-aligned and contiguous in
1181 * both virtual and physical memory -- you could then
1182 * just compare the low-order bits of the virtual address
1183 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1184 */
1185
1186 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1187 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1188 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1189
1190 /*
1191 * If they're the same, that means we've processed all
1192 * of the descriptors up to (but not including) the one that
1193 * the hardware is working on right now.
1194 */
1195
1196 if (curidx == hwidx)
1197 break;
1198
1199 /*
1200 * Otherwise, get the packet's sk_buff ptr back
1201 */
1202
1203 dsc = &(d->sbdma_dscrtable[curidx]);
1204 sb = d->sbdma_ctxtable[curidx];
1205 d->sbdma_ctxtable[curidx] = NULL;
1206
1207 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1208
1209 /*
1210 * Check packet status. If good, process it.
1211 * If not, silently drop it and put it back on the
1212 * receive ring.
1213 */
1214
1215 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
1216
1217 /*
1218 * Add a new buffer to replace the old one. If we fail
1219 * to allocate a buffer, we're going to drop this
1220 * packet and put it right back on the receive ring.
1221 */
1222
1223 if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
1224 sc->sbm_stats.rx_dropped++;
1225 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1226 } else {
1227 /*
1228 * Set length into the packet
1229 */
1230 skb_put(sb,len);
1231
1232 /*
1233 * Buffer has been replaced on the
1234 * receive ring. Pass the buffer to
1235 * the kernel
1236 */
1237 sc->sbm_stats.rx_bytes += len;
1238 sc->sbm_stats.rx_packets++;
1239 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1240 /* Check hw IPv4/TCP checksum if supported */
1241 if (sc->rx_hw_checksum == ENABLE) {
1242 if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1243 !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1244 sb->ip_summed = CHECKSUM_UNNECESSARY;
1245 /* don't need to set sb->csum */
1246 } else {
1247 sb->ip_summed = CHECKSUM_NONE;
1248 }
1249 }
1250
1251 netif_rx(sb);
1252 }
1253 } else {
1254 /*
1255 * Packet was mangled somehow. Just drop it and
1256 * put it back on the receive ring.
1257 */
1258 sc->sbm_stats.rx_errors++;
1259 sbdma_add_rcvbuffer(d,sb);
1260 }
1261
1262
1263 /*
1264 * .. and advance to the next buffer.
1265 */
1266
1267 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1268
1269 }
1270}
1271
1272
1273
1274/**********************************************************************
1275 * SBDMA_TX_PROCESS(sc,d)
1276 *
1277 * Process "completed" transmit buffers on the specified DMA channel.
1278 * This is normally called within the interrupt service routine.
1279 * Note that this isn't really ideal for priority channels, since
1280 * it processes all of the packets on a given channel before
1281 * returning.
1282 *
1283 * Input parameters:
1284 * sc - softc structure
1285 * d - DMA channel context
1286 *
1287 * Return value:
1288 * nothing
1289 ********************************************************************* */
1290
1291static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1292{
1293 int curidx;
1294 int hwidx;
1295 sbdmadscr_t *dsc;
1296 struct sk_buff *sb;
1297 unsigned long flags;
1298
1299 spin_lock_irqsave(&(sc->sbm_lock), flags);
1300
1301 for (;;) {
1302 /*
1303 * figure out where we are (as an index) and where
1304 * the hardware is (also as an index)
1305 *
1306 * This could be done faster if (for example) the
1307 * descriptor table was page-aligned and contiguous in
1308 * both virtual and physical memory -- you could then
1309 * just compare the low-order bits of the virtual address
1310 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1311 */
1312
1313 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1314 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1315 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1316
1317 /*
1318 * If they're the same, that means we've processed all
1319 * of the descriptors up to (but not including) the one that
1320 * the hardware is working on right now.
1321 */
1322
1323 if (curidx == hwidx)
1324 break;
1325
1326 /*
1327 * Otherwise, get the packet's sk_buff ptr back
1328 */
1329
1330 dsc = &(d->sbdma_dscrtable[curidx]);
1331 sb = d->sbdma_ctxtable[curidx];
1332 d->sbdma_ctxtable[curidx] = NULL;
1333
1334 /*
1335 * Stats
1336 */
1337
1338 sc->sbm_stats.tx_bytes += sb->len;
1339 sc->sbm_stats.tx_packets++;
1340
1341 /*
1342 * for transmits, we just free buffers.
1343 */
1344
1345 dev_kfree_skb_irq(sb);
1346
1347 /*
1348 * .. and advance to the next buffer.
1349 */
1350
1351 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1352
1353 }
1354
1355 /*
1356 * Decide if we should wake up the protocol or not.
1357 * Other drivers seem to do this when we reach a low
1358 * watermark on the transmit queue.
1359 */
1360
1361 netif_wake_queue(d->sbdma_eth->sbm_dev);
1362
1363 spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1364
1365}
1366
1367
1368
1369/**********************************************************************
1370 * SBMAC_INITCTX(s)
1371 *
1372 * Initialize an Ethernet context structure - this is called
1373 * once per MAC on the 1250. Memory is allocated here, so don't
1374 * call it again from inside the ioctl routines that bring the
1375 * interface up/down
1376 *
1377 * Input parameters:
1378 * s - sbmac context structure
1379 *
1380 * Return value:
1381 * 0
1382 ********************************************************************* */
1383
1384static int sbmac_initctx(struct sbmac_softc *s)
1385{
1386
1387 /*
1388 * figure out the addresses of some ports
1389 */
1390
1391 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1392 s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1393 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
1394 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
1395 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
1396 s->sbm_isr = s->sbm_base + R_MAC_STATUS;
1397 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1398 s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1399
1400 s->sbm_phys[0] = 1;
1401 s->sbm_phys[1] = 0;
1402
1403 s->sbm_phy_oldbmsr = 0;
1404 s->sbm_phy_oldanlpar = 0;
1405 s->sbm_phy_oldk1stsr = 0;
1406 s->sbm_phy_oldlinkstat = 0;
1407
1408 /*
1409 * Initialize the DMA channels. Right now, only one per MAC is used
1410 * Note: Only do this _once_, as it allocates memory from the kernel!
1411 */
1412
1413 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1414 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1415
1416 /*
1417 * initial state is OFF
1418 */
1419
1420 s->sbm_state = sbmac_state_off;
1421
1422 /*
1423 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1424 */
1425
1426 s->sbm_speed = sbmac_speed_10;
1427 s->sbm_duplex = sbmac_duplex_half;
1428 s->sbm_fc = sbmac_fc_disabled;
1429
1430 return 0;
1431}
1432
1433
1434static void sbdma_uninitctx(struct sbmacdma_s *d)
1435{
1436 if (d->sbdma_dscrtable) {
1437 kfree(d->sbdma_dscrtable);
1438 d->sbdma_dscrtable = NULL;
1439 }
1440
1441 if (d->sbdma_ctxtable) {
1442 kfree(d->sbdma_ctxtable);
1443 d->sbdma_ctxtable = NULL;
1444 }
1445}
1446
1447
1448static void sbmac_uninitctx(struct sbmac_softc *sc)
1449{
1450 sbdma_uninitctx(&(sc->sbm_txdma));
1451 sbdma_uninitctx(&(sc->sbm_rxdma));
1452}
1453
1454
1455/**********************************************************************
1456 * SBMAC_CHANNEL_START(s)
1457 *
1458 * Start packet processing on this MAC.
1459 *
1460 * Input parameters:
1461 * s - sbmac structure
1462 *
1463 * Return value:
1464 * nothing
1465 ********************************************************************* */
1466
1467static void sbmac_channel_start(struct sbmac_softc *s)
1468{
1469 uint64_t reg;
1470 sbmac_port_t port;
1471 uint64_t cfg,fifo,framecfg;
1472 int idx, th_value;
1473
1474 /*
1475 * Don't do this if running
1476 */
1477
1478 if (s->sbm_state == sbmac_state_on)
1479 return;
1480
1481 /*
1482 * Bring the controller out of reset, but leave it off.
1483 */
1484
1485 SBMAC_WRITECSR(s->sbm_macenable,0);
1486
1487 /*
1488 * Ignore all received packets
1489 */
1490
1491 SBMAC_WRITECSR(s->sbm_rxfilter,0);
1492
1493 /*
1494 * Calculate values for various control registers.
1495 */
1496
1497 cfg = M_MAC_RETRY_EN |
1498 M_MAC_TX_HOLD_SOP_EN |
1499 V_MAC_TX_PAUSE_CNT_16K |
1500 M_MAC_AP_STAT_EN |
1501 M_MAC_FAST_SYNC |
1502 M_MAC_SS_EN |
1503 0;
1504
1505 /*
1506 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1507 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1508 * Use a larger RD_THRSH for gigabit
1509 */
1510 if (periph_rev >= 2)
1511 th_value = 64;
1512 else
1513 th_value = 28;
1514
1515 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1516 ((s->sbm_speed == sbmac_speed_1000)
1517 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1518 V_MAC_TX_RL_THRSH(4) |
1519 V_MAC_RX_PL_THRSH(4) |
1520 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1521 V_MAC_RX_PL_THRSH(4) |
1522 V_MAC_RX_RL_THRSH(8) |
1523 0;
1524
1525 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1526 V_MAC_MAX_FRAMESZ_DEFAULT |
1527 V_MAC_BACKOFF_SEL(1);
1528
1529 /*
1530 * Clear out the hash address map
1531 */
1532
1533 port = s->sbm_base + R_MAC_HASH_BASE;
1534 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1535 SBMAC_WRITECSR(port,0);
1536 port += sizeof(uint64_t);
1537 }
1538
1539 /*
1540 * Clear out the exact-match table
1541 */
1542
1543 port = s->sbm_base + R_MAC_ADDR_BASE;
1544 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1545 SBMAC_WRITECSR(port,0);
1546 port += sizeof(uint64_t);
1547 }
1548
1549 /*
1550 * Clear out the DMA Channel mapping table registers
1551 */
1552
1553 port = s->sbm_base + R_MAC_CHUP0_BASE;
1554 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1555 SBMAC_WRITECSR(port,0);
1556 port += sizeof(uint64_t);
1557 }
1558
1559
1560 port = s->sbm_base + R_MAC_CHLO0_BASE;
1561 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1562 SBMAC_WRITECSR(port,0);
1563 port += sizeof(uint64_t);
1564 }
1565
1566 /*
1567 * Program the hardware address. It goes into the hardware-address
1568 * register as well as the first filter register.
1569 */
1570
1571 reg = sbmac_addr2reg(s->sbm_hwaddr);
1572
1573 port = s->sbm_base + R_MAC_ADDR_BASE;
1574 SBMAC_WRITECSR(port,reg);
1575 port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1576
1577#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1578 /*
1579 * Pass1 SOCs do not receive packets addressed to the
1580 * destination address in the R_MAC_ETHERNET_ADDR register.
1581 * Set the value to zero.
1582 */
1583 SBMAC_WRITECSR(port,0);
1584#else
1585 SBMAC_WRITECSR(port,reg);
1586#endif
1587
1588 /*
1589 * Set the receive filter for no packets, and write values
1590 * to the various config registers
1591 */
1592
1593 SBMAC_WRITECSR(s->sbm_rxfilter,0);
1594 SBMAC_WRITECSR(s->sbm_imr,0);
1595 SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1596 SBMAC_WRITECSR(s->sbm_fifocfg,fifo);
1597 SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1598
1599 /*
1600 * Initialize DMA channels (rings should be ok now)
1601 */
1602
1603 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1604 sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1605
1606 /*
1607 * Configure the speed, duplex, and flow control
1608 */
1609
1610 sbmac_set_speed(s,s->sbm_speed);
1611 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1612
1613 /*
1614 * Fill the receive ring
1615 */
1616
1617 sbdma_fillring(&(s->sbm_rxdma));
1618
1619 /*
1620 * Turn on the rest of the bits in the enable register
1621 */
1622
1623 SBMAC_WRITECSR(s->sbm_macenable,
1624 M_MAC_RXDMA_EN0 |
1625 M_MAC_TXDMA_EN0 |
1626 M_MAC_RX_ENABLE |
1627 M_MAC_TX_ENABLE);
1628
1629
1630
1631
1632#ifdef CONFIG_SBMAC_COALESCE
1633 /*
1634 * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1635 */
1636 SBMAC_WRITECSR(s->sbm_imr,
1637 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1638 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0));
1639#else
1640 /*
1641 * Accept any kind of interrupt on TX and RX DMA channel 0
1642 */
1643 SBMAC_WRITECSR(s->sbm_imr,
1644 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1645 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0));
1646#endif
1647
1648 /*
1649 * Enable receiving unicasts and broadcasts
1650 */
1651
1652 SBMAC_WRITECSR(s->sbm_rxfilter,M_MAC_UCAST_EN | M_MAC_BCAST_EN);
1653
1654 /*
1655 * we're running now.
1656 */
1657
1658 s->sbm_state = sbmac_state_on;
1659
1660 /*
1661 * Program multicast addresses
1662 */
1663
1664 sbmac_setmulti(s);
1665
1666 /*
1667 * If channel was in promiscuous mode before, turn that on
1668 */
1669
1670 if (s->sbm_devflags & IFF_PROMISC) {
1671 sbmac_promiscuous_mode(s,1);
1672 }
1673
1674}
1675
1676
1677/**********************************************************************
1678 * SBMAC_CHANNEL_STOP(s)
1679 *
1680 * Stop packet processing on this MAC.
1681 *
1682 * Input parameters:
1683 * s - sbmac structure
1684 *
1685 * Return value:
1686 * nothing
1687 ********************************************************************* */
1688
1689static void sbmac_channel_stop(struct sbmac_softc *s)
1690{
1691 /* don't do this if already stopped */
1692
1693 if (s->sbm_state == sbmac_state_off)
1694 return;
1695
1696 /* don't accept any packets, disable all interrupts */
1697
1698 SBMAC_WRITECSR(s->sbm_rxfilter,0);
1699 SBMAC_WRITECSR(s->sbm_imr,0);
1700
1701 /* Turn off ticker */
1702
1703 /* XXX */
1704
1705 /* turn off receiver and transmitter */
1706
1707 SBMAC_WRITECSR(s->sbm_macenable,0);
1708
1709 /* We're stopped now. */
1710
1711 s->sbm_state = sbmac_state_off;
1712
1713 /*
1714 * Stop DMA channels (rings should be ok now)
1715 */
1716
1717 sbdma_channel_stop(&(s->sbm_rxdma));
1718 sbdma_channel_stop(&(s->sbm_txdma));
1719
1720 /* Empty the receive and transmit rings */
1721
1722 sbdma_emptyring(&(s->sbm_rxdma));
1723 sbdma_emptyring(&(s->sbm_txdma));
1724
1725}
1726
1727/**********************************************************************
1728 * SBMAC_SET_CHANNEL_STATE(state)
1729 *
1730 * Set the channel's state ON or OFF
1731 *
1732 * Input parameters:
1733 * state - new state
1734 *
1735 * Return value:
1736 * old state
1737 ********************************************************************* */
1738static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1739 sbmac_state_t state)
1740{
1741 sbmac_state_t oldstate = sc->sbm_state;
1742
1743 /*
1744 * If same as previous state, return
1745 */
1746
1747 if (state == oldstate) {
1748 return oldstate;
1749 }
1750
1751 /*
1752 * If new state is ON, turn channel on
1753 */
1754
1755 if (state == sbmac_state_on) {
1756 sbmac_channel_start(sc);
1757 }
1758 else {
1759 sbmac_channel_stop(sc);
1760 }
1761
1762 /*
1763 * Return previous state
1764 */
1765
1766 return oldstate;
1767}
1768
1769
1770/**********************************************************************
1771 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1772 *
1773 * Turn on or off promiscuous mode
1774 *
1775 * Input parameters:
1776 * sc - softc
1777 * onoff - 1 to turn on, 0 to turn off
1778 *
1779 * Return value:
1780 * nothing
1781 ********************************************************************* */
1782
1783static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1784{
1785 uint64_t reg;
1786
1787 if (sc->sbm_state != sbmac_state_on)
1788 return;
1789
1790 if (onoff) {
1791 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1792 reg |= M_MAC_ALLPKT_EN;
1793 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1794 }
1795 else {
1796 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1797 reg &= ~M_MAC_ALLPKT_EN;
1798 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1799 }
1800}
1801
1802/**********************************************************************
1803 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1804 *
1805 * Set the iphdr offset as 15 assuming ethernet encapsulation
1806 *
1807 * Input parameters:
1808 * sc - softc
1809 *
1810 * Return value:
1811 * nothing
1812 ********************************************************************* */
1813
1814static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1815{
1816 uint64_t reg;
1817
1818 /* Hard code the off set to 15 for now */
1819 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1820 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1821 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1822
1823 /* read system identification to determine revision */
1824 if (periph_rev >= 2) {
1825 sc->rx_hw_checksum = ENABLE;
1826 } else {
1827 sc->rx_hw_checksum = DISABLE;
1828 }
1829}
1830
1831
1832/**********************************************************************
1833 * SBMAC_ADDR2REG(ptr)
1834 *
1835 * Convert six bytes into the 64-bit register value that
1836 * we typically write into the SBMAC's address/mcast registers
1837 *
1838 * Input parameters:
1839 * ptr - pointer to 6 bytes
1840 *
1841 * Return value:
1842 * register value
1843 ********************************************************************* */
1844
1845static uint64_t sbmac_addr2reg(unsigned char *ptr)
1846{
1847 uint64_t reg = 0;
1848
1849 ptr += 6;
1850
1851 reg |= (uint64_t) *(--ptr);
1852 reg <<= 8;
1853 reg |= (uint64_t) *(--ptr);
1854 reg <<= 8;
1855 reg |= (uint64_t) *(--ptr);
1856 reg <<= 8;
1857 reg |= (uint64_t) *(--ptr);
1858 reg <<= 8;
1859 reg |= (uint64_t) *(--ptr);
1860 reg <<= 8;
1861 reg |= (uint64_t) *(--ptr);
1862
1863 return reg;
1864}
1865
1866
1867/**********************************************************************
1868 * SBMAC_SET_SPEED(s,speed)
1869 *
1870 * Configure LAN speed for the specified MAC.
1871 * Warning: must be called when MAC is off!
1872 *
1873 * Input parameters:
1874 * s - sbmac structure
1875 * speed - speed to set MAC to (see sbmac_speed_t enum)
1876 *
1877 * Return value:
1878 * 1 if successful
1879 * 0 indicates invalid parameters
1880 ********************************************************************* */
1881
1882static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1883{
1884 uint64_t cfg;
1885 uint64_t framecfg;
1886
1887 /*
1888 * Save new current values
1889 */
1890
1891 s->sbm_speed = speed;
1892
1893 if (s->sbm_state == sbmac_state_on)
1894 return 0; /* save for next restart */
1895
1896 /*
1897 * Read current register values
1898 */
1899
1900 cfg = SBMAC_READCSR(s->sbm_maccfg);
1901 framecfg = SBMAC_READCSR(s->sbm_framecfg);
1902
1903 /*
1904 * Mask out the stuff we want to change
1905 */
1906
1907 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1908 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1909 M_MAC_SLOT_SIZE);
1910
1911 /*
1912 * Now add in the new bits
1913 */
1914
1915 switch (speed) {
1916 case sbmac_speed_10:
1917 framecfg |= V_MAC_IFG_RX_10 |
1918 V_MAC_IFG_TX_10 |
1919 K_MAC_IFG_THRSH_10 |
1920 V_MAC_SLOT_SIZE_10;
1921 cfg |= V_MAC_SPEED_SEL_10MBPS;
1922 break;
1923
1924 case sbmac_speed_100:
1925 framecfg |= V_MAC_IFG_RX_100 |
1926 V_MAC_IFG_TX_100 |
1927 V_MAC_IFG_THRSH_100 |
1928 V_MAC_SLOT_SIZE_100;
1929 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1930 break;
1931
1932 case sbmac_speed_1000:
1933 framecfg |= V_MAC_IFG_RX_1000 |
1934 V_MAC_IFG_TX_1000 |
1935 V_MAC_IFG_THRSH_1000 |
1936 V_MAC_SLOT_SIZE_1000;
1937 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1938 break;
1939
1940 case sbmac_speed_auto: /* XXX not implemented */
1941 /* fall through */
1942 default:
1943 return 0;
1944 }
1945
1946 /*
1947 * Send the bits back to the hardware
1948 */
1949
1950 SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1951 SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1952
1953 return 1;
1954}
1955
1956/**********************************************************************
1957 * SBMAC_SET_DUPLEX(s,duplex,fc)
1958 *
1959 * Set Ethernet duplex and flow control options for this MAC
1960 * Warning: must be called when MAC is off!
1961 *
1962 * Input parameters:
1963 * s - sbmac structure
1964 * duplex - duplex setting (see sbmac_duplex_t)
1965 * fc - flow control setting (see sbmac_fc_t)
1966 *
1967 * Return value:
1968 * 1 if ok
1969 * 0 if an invalid parameter combination was specified
1970 ********************************************************************* */
1971
1972static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
1973{
1974 uint64_t cfg;
1975
1976 /*
1977 * Save new current values
1978 */
1979
1980 s->sbm_duplex = duplex;
1981 s->sbm_fc = fc;
1982
1983 if (s->sbm_state == sbmac_state_on)
1984 return 0; /* save for next restart */
1985
1986 /*
1987 * Read current register values
1988 */
1989
1990 cfg = SBMAC_READCSR(s->sbm_maccfg);
1991
1992 /*
1993 * Mask off the stuff we're about to change
1994 */
1995
1996 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1997
1998
1999 switch (duplex) {
2000 case sbmac_duplex_half:
2001 switch (fc) {
2002 case sbmac_fc_disabled:
2003 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
2004 break;
2005
2006 case sbmac_fc_collision:
2007 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
2008 break;
2009
2010 case sbmac_fc_carrier:
2011 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2012 break;
2013
2014 case sbmac_fc_auto: /* XXX not implemented */
2015 /* fall through */
2016 case sbmac_fc_frame: /* not valid in half duplex */
2017 default: /* invalid selection */
2018 return 0;
2019 }
2020 break;
2021
2022 case sbmac_duplex_full:
2023 switch (fc) {
2024 case sbmac_fc_disabled:
2025 cfg |= V_MAC_FC_CMD_DISABLED;
2026 break;
2027
2028 case sbmac_fc_frame:
2029 cfg |= V_MAC_FC_CMD_ENABLED;
2030 break;
2031
2032 case sbmac_fc_collision: /* not valid in full duplex */
2033 case sbmac_fc_carrier: /* not valid in full duplex */
2034 case sbmac_fc_auto: /* XXX not implemented */
2035 /* fall through */
2036 default:
2037 return 0;
2038 }
2039 break;
2040 case sbmac_duplex_auto:
2041 /* XXX not implemented */
2042 break;
2043 }
2044
2045 /*
2046 * Send the bits back to the hardware
2047 */
2048
2049 SBMAC_WRITECSR(s->sbm_maccfg,cfg);
2050
2051 return 1;
2052}
2053
2054
2055
2056
2057/**********************************************************************
2058 * SBMAC_INTR()
2059 *
2060 * Interrupt handler for MAC interrupts
2061 *
2062 * Input parameters:
2063 * MAC structure
2064 *
2065 * Return value:
2066 * nothing
2067 ********************************************************************* */
2068static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs)
2069{
2070 struct net_device *dev = (struct net_device *) dev_instance;
2071 struct sbmac_softc *sc = netdev_priv(dev);
2072 uint64_t isr;
2073 int handled = 0;
2074
2075 for (;;) {
2076
2077 /*
2078 * Read the ISR (this clears the bits in the real
2079 * register, except for counter addr)
2080 */
2081
2082 isr = SBMAC_READCSR(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2083
2084 if (isr == 0)
2085 break;
2086
2087 handled = 1;
2088
2089 /*
2090 * Transmits on channel 0
2091 */
2092
2093 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2094 sbdma_tx_process(sc,&(sc->sbm_txdma));
2095 }
2096
2097 /*
2098 * Receives on channel 0
2099 */
2100
2101 /*
2102 * It's important to test all the bits (or at least the
2103 * EOP_SEEN bit) when deciding to do the RX process
2104 * particularly when coalescing, to make sure we
2105 * take care of the following:
2106 *
2107 * If you have some packets waiting (have been received
2108 * but no interrupt) and get a TX interrupt before
2109 * the RX timer or counter expires, reading the ISR
2110 * above will clear the timer and counter, and you
2111 * won't get another interrupt until a packet shows
2112 * up to start the timer again. Testing
2113 * EOP_SEEN here takes care of this case.
2114 * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2115 */
2116
2117
2118 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2119 sbdma_rx_process(sc,&(sc->sbm_rxdma));
2120 }
2121 }
2122 return IRQ_RETVAL(handled);
2123}
2124
2125
2126/**********************************************************************
2127 * SBMAC_START_TX(skb,dev)
2128 *
2129 * Start output on the specified interface. Basically, we
2130 * queue as many buffers as we can until the ring fills up, or
2131 * we run off the end of the queue, whichever comes first.
2132 *
2133 * Input parameters:
2134 *
2135 *
2136 * Return value:
2137 * nothing
2138 ********************************************************************* */
2139static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2140{
2141 struct sbmac_softc *sc = netdev_priv(dev);
2142
2143 /* lock eth irq */
2144 spin_lock_irq (&sc->sbm_lock);
2145
2146 /*
2147 * Put the buffer on the transmit ring. If we
2148 * don't have room, stop the queue.
2149 */
2150
2151 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2152 /* XXX save skb that we could not send */
2153 netif_stop_queue(dev);
2154 spin_unlock_irq(&sc->sbm_lock);
2155
2156 return 1;
2157 }
2158
2159 dev->trans_start = jiffies;
2160
2161 spin_unlock_irq (&sc->sbm_lock);
2162
2163 return 0;
2164}
2165
2166/**********************************************************************
2167 * SBMAC_SETMULTI(sc)
2168 *
2169 * Reprogram the multicast table into the hardware, given
2170 * the list of multicasts associated with the interface
2171 * structure.
2172 *
2173 * Input parameters:
2174 * sc - softc
2175 *
2176 * Return value:
2177 * nothing
2178 ********************************************************************* */
2179
2180static void sbmac_setmulti(struct sbmac_softc *sc)
2181{
2182 uint64_t reg;
2183 sbmac_port_t port;
2184 int idx;
2185 struct dev_mc_list *mclist;
2186 struct net_device *dev = sc->sbm_dev;
2187
2188 /*
2189 * Clear out entire multicast table. We do this by nuking
2190 * the entire hash table and all the direct matches except
2191 * the first one, which is used for our station address
2192 */
2193
2194 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2195 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2196 SBMAC_WRITECSR(port,0);
2197 }
2198
2199 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2200 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2201 SBMAC_WRITECSR(port,0);
2202 }
2203
2204 /*
2205 * Clear the filter to say we don't want any multicasts.
2206 */
2207
2208 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2209 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2210 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2211
2212 if (dev->flags & IFF_ALLMULTI) {
2213 /*
2214 * Enable ALL multicasts. Do this by inverting the
2215 * multicast enable bit.
2216 */
2217 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2218 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2219 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2220 return;
2221 }
2222
2223
2224 /*
2225 * Progam new multicast entries. For now, only use the
2226 * perfect filter. In the future we'll need to use the
2227 * hash filter if the perfect filter overflows
2228 */
2229
2230 /* XXX only using perfect filter for now, need to use hash
2231 * XXX if the table overflows */
2232
2233 idx = 1; /* skip station address */
2234 mclist = dev->mc_list;
2235 while (mclist && (idx < MAC_ADDR_COUNT)) {
2236 reg = sbmac_addr2reg(mclist->dmi_addr);
2237 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2238 SBMAC_WRITECSR(port,reg);
2239 idx++;
2240 mclist = mclist->next;
2241 }
2242
2243 /*
2244 * Enable the "accept multicast bits" if we programmed at least one
2245 * multicast.
2246 */
2247
2248 if (idx > 1) {
2249 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2250 reg |= M_MAC_MCAST_EN;
2251 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2252 }
2253}
2254
2255
2256
2257#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2258/**********************************************************************
2259 * SBMAC_PARSE_XDIGIT(str)
2260 *
2261 * Parse a hex digit, returning its value
2262 *
2263 * Input parameters:
2264 * str - character
2265 *
2266 * Return value:
2267 * hex value, or -1 if invalid
2268 ********************************************************************* */
2269
2270static int sbmac_parse_xdigit(char str)
2271{
2272 int digit;
2273
2274 if ((str >= '0') && (str <= '9'))
2275 digit = str - '0';
2276 else if ((str >= 'a') && (str <= 'f'))
2277 digit = str - 'a' + 10;
2278 else if ((str >= 'A') && (str <= 'F'))
2279 digit = str - 'A' + 10;
2280 else
2281 return -1;
2282
2283 return digit;
2284}
2285
2286/**********************************************************************
2287 * SBMAC_PARSE_HWADDR(str,hwaddr)
2288 *
2289 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2290 * Ethernet address.
2291 *
2292 * Input parameters:
2293 * str - string
2294 * hwaddr - pointer to hardware address
2295 *
2296 * Return value:
2297 * 0 if ok, else -1
2298 ********************************************************************* */
2299
2300static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2301{
2302 int digit1,digit2;
2303 int idx = 6;
2304
2305 while (*str && (idx > 0)) {
2306 digit1 = sbmac_parse_xdigit(*str);
2307 if (digit1 < 0)
2308 return -1;
2309 str++;
2310 if (!*str)
2311 return -1;
2312
2313 if ((*str == ':') || (*str == '-')) {
2314 digit2 = digit1;
2315 digit1 = 0;
2316 }
2317 else {
2318 digit2 = sbmac_parse_xdigit(*str);
2319 if (digit2 < 0)
2320 return -1;
2321 str++;
2322 }
2323
2324 *hwaddr++ = (digit1 << 4) | digit2;
2325 idx--;
2326
2327 if (*str == '-')
2328 str++;
2329 if (*str == ':')
2330 str++;
2331 }
2332 return 0;
2333}
2334#endif
2335
2336static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2337{
2338 if (new_mtu > ENET_PACKET_SIZE)
2339 return -EINVAL;
2340 _dev->mtu = new_mtu;
2341 printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2342 return 0;
2343}
2344
2345/**********************************************************************
2346 * SBMAC_INIT(dev)
2347 *
2348 * Attach routine - init hardware and hook ourselves into linux
2349 *
2350 * Input parameters:
2351 * dev - net_device structure
2352 *
2353 * Return value:
2354 * status
2355 ********************************************************************* */
2356
2357static int sbmac_init(struct net_device *dev, int idx)
2358{
2359 struct sbmac_softc *sc;
2360 unsigned char *eaddr;
2361 uint64_t ea_reg;
2362 int i;
2363 int err;
2364
2365 sc = netdev_priv(dev);
2366
2367 /* Determine controller base address */
2368
2369 sc->sbm_base = IOADDR(dev->base_addr);
2370 sc->sbm_dev = dev;
2371 sc->sbe_idx = idx;
2372
2373 eaddr = sc->sbm_hwaddr;
2374
2375 /*
2376 * Read the ethernet address. The firwmare left this programmed
2377 * for us in the ethernet address register for each mac.
2378 */
2379
2380 ea_reg = SBMAC_READCSR(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2381 SBMAC_WRITECSR(sc->sbm_base + R_MAC_ETHERNET_ADDR, 0);
2382 for (i = 0; i < 6; i++) {
2383 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2384 ea_reg >>= 8;
2385 }
2386
2387 for (i = 0; i < 6; i++) {
2388 dev->dev_addr[i] = eaddr[i];
2389 }
2390
2391
2392 /*
2393 * Init packet size
2394 */
2395
2396 sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2397
2398 /*
2399 * Initialize context (get pointers to registers and stuff), then
2400 * allocate the memory for the descriptor tables.
2401 */
2402
2403 sbmac_initctx(sc);
2404
2405 /*
2406 * Set up Linux device callins
2407 */
2408
2409 spin_lock_init(&(sc->sbm_lock));
2410
2411 dev->open = sbmac_open;
2412 dev->hard_start_xmit = sbmac_start_tx;
2413 dev->stop = sbmac_close;
2414 dev->get_stats = sbmac_get_stats;
2415 dev->set_multicast_list = sbmac_set_rx_mode;
2416 dev->do_ioctl = sbmac_mii_ioctl;
2417 dev->tx_timeout = sbmac_tx_timeout;
2418 dev->watchdog_timeo = TX_TIMEOUT;
2419
2420 dev->change_mtu = sb1250_change_mtu;
2421
2422 /* This is needed for PASS2 for Rx H/W checksum feature */
2423 sbmac_set_iphdr_offset(sc);
2424
2425 err = register_netdev(dev);
2426 if (err)
2427 goto out_uninit;
2428
f567ef93 2429 if (sc->rx_hw_checksum == ENABLE) {
1da177e4
LT		 2430 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
2431 sc->sbm_dev->name);
2432 }
2433
2434 /*
2435 * Display Ethernet address (this is called during the config
2436 * process so we need to finish off the config message that
2437 * was being displayed)
2438 */
2439 printk(KERN_INFO
2440 "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
2441 dev->name, dev->base_addr,
2442 eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2443
2444
2445 return 0;
2446
2447out_uninit:
2448 sbmac_uninitctx(sc);
2449
2450 return err;
2451}
2452
2453
2454static int sbmac_open(struct net_device *dev)
2455{
2456 struct sbmac_softc *sc = netdev_priv(dev);
2457
2458 if (debug > 1) {
2459 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2460 }
2461
2462 /*
2463 * map/route interrupt (clear status first, in case something
2464 * weird is pending; we haven't initialized the mac registers
2465 * yet)
2466 */
2467
2468 SBMAC_READCSR(sc->sbm_isr);
2469 if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev))
2470 return -EBUSY;
2471
2472 /*
2473 * Configure default speed
2474 */
2475
2476 sbmac_mii_poll(sc,noisy_mii);
2477
2478 /*
2479 * Turn on the channel
2480 */
2481
2482 sbmac_set_channel_state(sc,sbmac_state_on);
2483
2484 /*
2485 * XXX Station address is in dev->dev_addr
2486 */
2487
2488 if (dev->if_port == 0)
2489 dev->if_port = 0;
2490
2491 netif_start_queue(dev);
2492
2493 sbmac_set_rx_mode(dev);
2494
2495 /* Set the timer to check for link beat. */
2496 init_timer(&sc->sbm_timer);
2497 sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2498 sc->sbm_timer.data = (unsigned long)dev;
2499 sc->sbm_timer.function = &sbmac_timer;
2500 add_timer(&sc->sbm_timer);
2501
2502 return 0;
2503}
2504
2505
2506
2507static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2508{
2509 int bmsr,bmcr,k1stsr,anlpar;
2510 int chg;
2511 char buffer[100];
2512 char *p = buffer;
2513
2514 /* Read the mode status and mode control registers. */
2515 bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2516 bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2517
2518 /* get the link partner status */
2519 anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2520
2521 /* if supported, read the 1000baseT register */
2522 if (bmsr & BMSR_1000BT_XSR) {
2523 k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2524 }
2525 else {
2526 k1stsr = 0;
2527 }
2528
2529 chg = 0;
2530
2531 if ((bmsr & BMSR_LINKSTAT) == 0) {
2532 /*
2533 * If link status is down, clear out old info so that when
2534 * it comes back up it will force us to reconfigure speed
2535 */
2536 s->sbm_phy_oldbmsr = 0;
2537 s->sbm_phy_oldanlpar = 0;
2538 s->sbm_phy_oldk1stsr = 0;
2539 return 0;
2540 }
2541
2542 if ((s->sbm_phy_oldbmsr != bmsr) ||
2543 (s->sbm_phy_oldanlpar != anlpar) ||
2544 (s->sbm_phy_oldk1stsr != k1stsr)) {
2545 if (debug > 1) {
2546 printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n",
2547 s->sbm_dev->name,
2548 s->sbm_phy_oldbmsr,bmsr,
2549 s->sbm_phy_oldanlpar,anlpar,
2550 s->sbm_phy_oldk1stsr,k1stsr);
2551 }
2552 s->sbm_phy_oldbmsr = bmsr;
2553 s->sbm_phy_oldanlpar = anlpar;
2554 s->sbm_phy_oldk1stsr = k1stsr;
2555 chg = 1;
2556 }
2557
2558 if (chg == 0)
2559 return 0;
2560
2561 p += sprintf(p,"Link speed: ");
2562
2563 if (k1stsr & K1STSR_LP1KFD) {
2564 s->sbm_speed = sbmac_speed_1000;
2565 s->sbm_duplex = sbmac_duplex_full;
2566 s->sbm_fc = sbmac_fc_frame;
2567 p += sprintf(p,"1000BaseT FDX");
2568 }
2569 else if (k1stsr & K1STSR_LP1KHD) {
2570 s->sbm_speed = sbmac_speed_1000;
2571 s->sbm_duplex = sbmac_duplex_half;
2572 s->sbm_fc = sbmac_fc_disabled;
2573 p += sprintf(p,"1000BaseT HDX");
2574 }
2575 else if (anlpar & ANLPAR_TXFD) {
2576 s->sbm_speed = sbmac_speed_100;
2577 s->sbm_duplex = sbmac_duplex_full;
2578 s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2579 p += sprintf(p,"100BaseT FDX");
2580 }
2581 else if (anlpar & ANLPAR_TXHD) {
2582 s->sbm_speed = sbmac_speed_100;
2583 s->sbm_duplex = sbmac_duplex_half;
2584 s->sbm_fc = sbmac_fc_disabled;
2585 p += sprintf(p,"100BaseT HDX");
2586 }
2587 else if (anlpar & ANLPAR_10FD) {
2588 s->sbm_speed = sbmac_speed_10;
2589 s->sbm_duplex = sbmac_duplex_full;
2590 s->sbm_fc = sbmac_fc_frame;
2591 p += sprintf(p,"10BaseT FDX");
2592 }
2593 else if (anlpar & ANLPAR_10HD) {
2594 s->sbm_speed = sbmac_speed_10;
2595 s->sbm_duplex = sbmac_duplex_half;
2596 s->sbm_fc = sbmac_fc_collision;
2597 p += sprintf(p,"10BaseT HDX");
2598 }
2599 else {
2600 p += sprintf(p,"Unknown");
2601 }
2602
2603 if (noisy) {
2604 printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2605 }
2606
2607 return 1;
2608}
2609
2610
2611static void sbmac_timer(unsigned long data)
2612{
2613 struct net_device *dev = (struct net_device *)data;
2614 struct sbmac_softc *sc = netdev_priv(dev);
2615 int next_tick = HZ;
2616 int mii_status;
2617
2618 spin_lock_irq (&sc->sbm_lock);
2619
2620 /* make IFF_RUNNING follow the MII status bit "Link established" */
2621 mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2622
2623 if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2624 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2625 if (mii_status & BMSR_LINKSTAT) {
2626 netif_carrier_on(dev);
2627 }
2628 else {
2629 netif_carrier_off(dev);
2630 }
2631 }
2632
2633 /*
2634 * Poll the PHY to see what speed we should be running at
2635 */
2636
2637 if (sbmac_mii_poll(sc,noisy_mii)) {
2638 if (sc->sbm_state != sbmac_state_off) {
2639 /*
2640 * something changed, restart the channel
2641 */
2642 if (debug > 1) {
2643 printk("%s: restarting channel because speed changed\n",
2644 sc->sbm_dev->name);
2645 }
2646 sbmac_channel_stop(sc);
2647 sbmac_channel_start(sc);
2648 }
2649 }
2650
2651 spin_unlock_irq (&sc->sbm_lock);
2652
2653 sc->sbm_timer.expires = jiffies + next_tick;
2654 add_timer(&sc->sbm_timer);
2655}
2656
2657
2658static void sbmac_tx_timeout (struct net_device *dev)
2659{
2660 struct sbmac_softc *sc = netdev_priv(dev);
2661
2662 spin_lock_irq (&sc->sbm_lock);
2663
2664
2665 dev->trans_start = jiffies;
2666 sc->sbm_stats.tx_errors++;
2667
2668 spin_unlock_irq (&sc->sbm_lock);
2669
2670 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2671}
2672
2673
2674
2675
2676static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2677{
2678 struct sbmac_softc *sc = netdev_priv(dev);
2679 unsigned long flags;
2680
2681 spin_lock_irqsave(&sc->sbm_lock, flags);
2682
2683 /* XXX update other stats here */
2684
2685 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2686
2687 return &sc->sbm_stats;
2688}
2689
2690
2691
2692static void sbmac_set_rx_mode(struct net_device *dev)
2693{
2694 unsigned long flags;
2695 int msg_flag = 0;
2696 struct sbmac_softc *sc = netdev_priv(dev);
2697
2698 spin_lock_irqsave(&sc->sbm_lock, flags);
2699 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2700 /*
2701 * Promiscuous changed.
2702 */
2703
2704 if (dev->flags & IFF_PROMISC) {
2705 /* Unconditionally log net taps. */
2706 msg_flag = 1;
2707 sbmac_promiscuous_mode(sc,1);
2708 }
2709 else {
2710 msg_flag = 2;
2711 sbmac_promiscuous_mode(sc,0);
2712 }
2713 }
2714 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2715
2716 if (msg_flag) {
2717 printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n",
2718 dev->name,(msg_flag==1)?"en":"dis");
2719 }
2720
2721 /*
2722 * Program the multicasts. Do this every time.
2723 */
2724
2725 sbmac_setmulti(sc);
2726
2727}
2728
2729static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2730{
2731 struct sbmac_softc *sc = netdev_priv(dev);
2732 u16 *data = (u16 *)&rq->ifr_ifru;
2733 unsigned long flags;
2734 int retval;
2735
2736 spin_lock_irqsave(&sc->sbm_lock, flags);
2737 retval = 0;
2738
2739 switch(cmd) {
2740 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2741 data[0] = sc->sbm_phys[0] & 0x1f;
2742 /* Fall Through */
2743 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2744 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2745 break;
2746 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2747 if (!capable(CAP_NET_ADMIN)) {
2748 retval = -EPERM;
2749 break;
2750 }
2751 if (debug > 1) {
2752 printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2753 data[0],data[1],data[2]);
2754 }
2755 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2756 break;
2757 default:
2758 retval = -EOPNOTSUPP;
2759 }
2760
2761 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2762 return retval;
2763}
2764
2765static int sbmac_close(struct net_device *dev)
2766{
2767 struct sbmac_softc *sc = netdev_priv(dev);
2768 unsigned long flags;
2769 int irq;
2770
2771 sbmac_set_channel_state(sc,sbmac_state_off);
2772
2773 del_timer_sync(&sc->sbm_timer);
2774
2775 spin_lock_irqsave(&sc->sbm_lock, flags);
2776
2777 netif_stop_queue(dev);
2778
2779 if (debug > 1) {
2780 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2781 }
2782
2783 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2784
2785 irq = dev->irq;
2786 synchronize_irq(irq);
2787 free_irq(irq, dev);
2788
2789 sbdma_emptyring(&(sc->sbm_txdma));
2790 sbdma_emptyring(&(sc->sbm_rxdma));
2791
2792 return 0;
2793}
2794
2795
2796
2797#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2798static void
2799sbmac_setup_hwaddr(int chan,char *addr)
2800{
2801 uint8_t eaddr[6];
2802 uint64_t val;
2803 sbmac_port_t port;
2804
2805 port = A_MAC_CHANNEL_BASE(chan);
2806 sbmac_parse_hwaddr(addr,eaddr);
2807 val = sbmac_addr2reg(eaddr);
2808 SBMAC_WRITECSR(IOADDR(port+R_MAC_ETHERNET_ADDR),val);
2809 val = SBMAC_READCSR(IOADDR(port+R_MAC_ETHERNET_ADDR));
2810}
2811#endif
2812
2813static struct net_device *dev_sbmac[MAX_UNITS];
2814
2815static int __init
2816sbmac_init_module(void)
2817{
2818 int idx;
2819 struct net_device *dev;
2820 sbmac_port_t port;
2821 int chip_max_units;
2822
2823 /*
2824 * For bringup when not using the firmware, we can pre-fill
2825 * the MAC addresses using the environment variables
2826 * specified in this file (or maybe from the config file?)
2827 */
2828#ifdef SBMAC_ETH0_HWADDR
2829 sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2830#endif
2831#ifdef SBMAC_ETH1_HWADDR
2832 sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2833#endif
2834#ifdef SBMAC_ETH2_HWADDR
2835 sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2836#endif
2837
2838 /*
2839 * Walk through the Ethernet controllers and find
2840 * those who have their MAC addresses set.
2841 */
2842 switch (soc_type) {
2843 case K_SYS_SOC_TYPE_BCM1250:
2844 case K_SYS_SOC_TYPE_BCM1250_ALT:
2845 chip_max_units = 3;
2846 break;
2847 case K_SYS_SOC_TYPE_BCM1120:
2848 case K_SYS_SOC_TYPE_BCM1125:
2849 case K_SYS_SOC_TYPE_BCM1125H:
2850 case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2851 chip_max_units = 2;
2852 break;
2853 default:
2854 chip_max_units = 0;
2855 break;
2856 }
2857 if (chip_max_units > MAX_UNITS)
2858 chip_max_units = MAX_UNITS;
2859
2860 for (idx = 0; idx < chip_max_units; idx++) {
2861
2862 /*
2863 * This is the base address of the MAC.
2864 */
2865
2866 port = A_MAC_CHANNEL_BASE(idx);
2867
2868 /*
2869 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2870 * value for us by the firmware if we're going to use this MAC.
2871 * If we find a zero, skip this MAC.
2872 */
2873
2874 sbmac_orig_hwaddr[idx] = SBMAC_READCSR(IOADDR(port+R_MAC_ETHERNET_ADDR));
2875 if (sbmac_orig_hwaddr[idx] == 0) {
2876 printk(KERN_DEBUG "sbmac: not configuring MAC at "
2877 "%lx\n", port);
2878 continue;
2879 }
2880
2881 /*
2882 * Okay, cool. Initialize this MAC.
2883 */
2884
2885 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2886 if (!dev)
2887 return -ENOMEM; /* return ENOMEM */
2888
2889 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
2890
2891 dev->irq = K_INT_MAC_0 + idx;
2892 dev->base_addr = port;
2893 dev->mem_end = 0;
2894 if (sbmac_init(dev, idx)) {
2895 port = A_MAC_CHANNEL_BASE(idx);
2896 SBMAC_WRITECSR(IOADDR(port+R_MAC_ETHERNET_ADDR),
2897 sbmac_orig_hwaddr[idx]);
2898 free_netdev(dev);
2899 continue;
2900 }
2901 dev_sbmac[idx] = dev;
2902 }
2903 return 0;
2904}
2905
2906
2907static void __exit
2908sbmac_cleanup_module(void)
2909{
2910 struct net_device *dev;
2911 int idx;
2912
2913 for (idx = 0; idx < MAX_UNITS; idx++) {
2914 struct sbmac_softc *sc;
2915 dev = dev_sbmac[idx];
2916 if (!dev)
2917 continue;
2918
2919 sc = netdev_priv(dev);
2920 unregister_netdev(dev);
2921 sbmac_uninitctx(sc);
2922 free_netdev(dev);
2923 }
2924}
2925
2926module_init(sbmac_init_module);
2927module_exit(sbmac_cleanup_module);
Linux 6.x block layer and io_uring tree(s)