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hamradio/scc: add missing block braces to multi-statement if
[linux-2.6-block.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/types.h>
59#include <linux/errno.h>
60#include <linux/ioport.h>
61#include <linux/pci.h>
1e7f0bd8 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/kernel.h>
64#include <linux/netdevice.h>
65#include <linux/etherdevice.h>
66#include <linux/skbuff.h>
67#include <linux/init.h>
68#include <linux/delay.h>
69#include <linux/stddef.h>
70#include <linux/ioctl.h>
71#include <linux/timex.h>
1da177e4 72#include <linux/ethtool.h>
1da177e4 73#include <linux/workqueue.h>
be3a6b02 74#include <linux/if_vlan.h>
7d3d0439
RA		 75#include <linux/ip.h>
76#include <linux/tcp.h>
77#include <net/tcp.h>
1da177e4 78
1da177e4
LT		 79#include <asm/system.h>
80#include <asm/uaccess.h>
20346722 81#include <asm/io.h>
fe931395 82#include <asm/div64.h>
330ce0de 83#include <asm/irq.h>
1da177e4
LT		 84
85/* local include */
86#include "s2io.h"
87#include "s2io-regs.h"
88
23d9b387 89#define DRV_VERSION "2.0.26.23"
6c1792f4 90
1da177e4 91/* S2io Driver name & version. */
20346722 92static char s2io_driver_name[] = "Neterion";
6c1792f4 93static char s2io_driver_version[] = DRV_VERSION;
1da177e4 94
6d517a27
VP		 95static int rxd_size[2] = {32,48};
96static int rxd_count[2] = {127,85};
da6971d8 97
1ee6dd77 98static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd 99{
100 int ret;
101
102 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
103 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
104
105 return ret;
106}
107
20346722 108/*
1da177e4
LT		 109 * Cards with following subsystem_id have a link state indication
110 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
111 * macro below identifies these cards given the subsystem_id.
112 */
541ae68f 113#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
114 (dev_type == XFRAME_I_DEVICE) ? \
115 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
116 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 117
118#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
119 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 120
92b84437
SS		 121static inline int is_s2io_card_up(const struct s2io_nic * sp)
122{
123 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
124}
125
1da177e4
LT		 126/* Ethtool related variables and Macros. */
127static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128 "Register test\t(offline)",
129 "Eeprom test\t(offline)",
130 "Link test\t(online)",
131 "RLDRAM test\t(offline)",
132 "BIST Test\t(offline)"
133};
134
fa1f0cb3 135static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 136 {"tmac_frms"},
137 {"tmac_data_octets"},
138 {"tmac_drop_frms"},
139 {"tmac_mcst_frms"},
140 {"tmac_bcst_frms"},
141 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 142 {"tmac_ttl_octets"},
143 {"tmac_ucst_frms"},
144 {"tmac_nucst_frms"},
1da177e4 145 {"tmac_any_err_frms"},
bd1034f0 146 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 147 {"tmac_vld_ip_octets"},
148 {"tmac_vld_ip"},
149 {"tmac_drop_ip"},
150 {"tmac_icmp"},
151 {"tmac_rst_tcp"},
152 {"tmac_tcp"},
153 {"tmac_udp"},
154 {"rmac_vld_frms"},
155 {"rmac_data_octets"},
156 {"rmac_fcs_err_frms"},
157 {"rmac_drop_frms"},
158 {"rmac_vld_mcst_frms"},
159 {"rmac_vld_bcst_frms"},
160 {"rmac_in_rng_len_err_frms"},
bd1034f0 161 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 162 {"rmac_long_frms"},
163 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 164 {"rmac_unsup_ctrl_frms"},
165 {"rmac_ttl_octets"},
166 {"rmac_accepted_ucst_frms"},
167 {"rmac_accepted_nucst_frms"},
1da177e4 168 {"rmac_discarded_frms"},
bd1034f0
AR		 169 {"rmac_drop_events"},
170 {"rmac_ttl_less_fb_octets"},
171 {"rmac_ttl_frms"},
1da177e4
LT		 172 {"rmac_usized_frms"},
173 {"rmac_osized_frms"},
174 {"rmac_frag_frms"},
175 {"rmac_jabber_frms"},
bd1034f0
AR		 176 {"rmac_ttl_64_frms"},
177 {"rmac_ttl_65_127_frms"},
178 {"rmac_ttl_128_255_frms"},
179 {"rmac_ttl_256_511_frms"},
180 {"rmac_ttl_512_1023_frms"},
181 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 182 {"rmac_ip"},
183 {"rmac_ip_octets"},
184 {"rmac_hdr_err_ip"},
185 {"rmac_drop_ip"},
186 {"rmac_icmp"},
187 {"rmac_tcp"},
188 {"rmac_udp"},
189 {"rmac_err_drp_udp"},
bd1034f0
AR		 190 {"rmac_xgmii_err_sym"},
191 {"rmac_frms_q0"},
192 {"rmac_frms_q1"},
193 {"rmac_frms_q2"},
194 {"rmac_frms_q3"},
195 {"rmac_frms_q4"},
196 {"rmac_frms_q5"},
197 {"rmac_frms_q6"},
198 {"rmac_frms_q7"},
199 {"rmac_full_q0"},
200 {"rmac_full_q1"},
201 {"rmac_full_q2"},
202 {"rmac_full_q3"},
203 {"rmac_full_q4"},
204 {"rmac_full_q5"},
205 {"rmac_full_q6"},
206 {"rmac_full_q7"},
1da177e4 207 {"rmac_pause_cnt"},
bd1034f0
AR		 208 {"rmac_xgmii_data_err_cnt"},
209 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 210 {"rmac_accepted_ip"},
211 {"rmac_err_tcp"},
bd1034f0
AR		 212 {"rd_req_cnt"},
213 {"new_rd_req_cnt"},
214 {"new_rd_req_rtry_cnt"},
215 {"rd_rtry_cnt"},
216 {"wr_rtry_rd_ack_cnt"},
217 {"wr_req_cnt"},
218 {"new_wr_req_cnt"},
219 {"new_wr_req_rtry_cnt"},
220 {"wr_rtry_cnt"},
221 {"wr_disc_cnt"},
222 {"rd_rtry_wr_ack_cnt"},
223 {"txp_wr_cnt"},
224 {"txd_rd_cnt"},
225 {"txd_wr_cnt"},
226 {"rxd_rd_cnt"},
227 {"rxd_wr_cnt"},
228 {"txf_rd_cnt"},
fa1f0cb3
SS		 229 {"rxf_wr_cnt"}
230};
231
232static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 233 {"rmac_ttl_1519_4095_frms"},
234 {"rmac_ttl_4096_8191_frms"},
235 {"rmac_ttl_8192_max_frms"},
236 {"rmac_ttl_gt_max_frms"},
237 {"rmac_osized_alt_frms"},
238 {"rmac_jabber_alt_frms"},
239 {"rmac_gt_max_alt_frms"},
240 {"rmac_vlan_frms"},
241 {"rmac_len_discard"},
242 {"rmac_fcs_discard"},
243 {"rmac_pf_discard"},
244 {"rmac_da_discard"},
245 {"rmac_red_discard"},
246 {"rmac_rts_discard"},
247 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 248 {"link_fault_cnt"}
249};
250
251static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac 252 {"\n DRIVER STATISTICS"},
253 {"single_bit_ecc_errs"},
254 {"double_bit_ecc_errs"},
bd1034f0
AR		 255 {"parity_err_cnt"},
256 {"serious_err_cnt"},
257 {"soft_reset_cnt"},
258 {"fifo_full_cnt"},
8116f3cf
SS		 259 {"ring_0_full_cnt"},
260 {"ring_1_full_cnt"},
261 {"ring_2_full_cnt"},
262 {"ring_3_full_cnt"},
263 {"ring_4_full_cnt"},
264 {"ring_5_full_cnt"},
265 {"ring_6_full_cnt"},
266 {"ring_7_full_cnt"},
43b7c451
SH		 267 {"alarm_transceiver_temp_high"},
268 {"alarm_transceiver_temp_low"},
269 {"alarm_laser_bias_current_high"},
270 {"alarm_laser_bias_current_low"},
271 {"alarm_laser_output_power_high"},
272 {"alarm_laser_output_power_low"},
273 {"warn_transceiver_temp_high"},
274 {"warn_transceiver_temp_low"},
275 {"warn_laser_bias_current_high"},
276 {"warn_laser_bias_current_low"},
277 {"warn_laser_output_power_high"},
278 {"warn_laser_output_power_low"},
279 {"lro_aggregated_pkts"},
280 {"lro_flush_both_count"},
281 {"lro_out_of_sequence_pkts"},
282 {"lro_flush_due_to_max_pkts"},
283 {"lro_avg_aggr_pkts"},
284 {"mem_alloc_fail_cnt"},
285 {"pci_map_fail_cnt"},
286 {"watchdog_timer_cnt"},
287 {"mem_allocated"},
288 {"mem_freed"},
289 {"link_up_cnt"},
290 {"link_down_cnt"},
291 {"link_up_time"},
292 {"link_down_time"},
293 {"tx_tcode_buf_abort_cnt"},
294 {"tx_tcode_desc_abort_cnt"},
295 {"tx_tcode_parity_err_cnt"},
296 {"tx_tcode_link_loss_cnt"},
297 {"tx_tcode_list_proc_err_cnt"},
298 {"rx_tcode_parity_err_cnt"},
299 {"rx_tcode_abort_cnt"},
300 {"rx_tcode_parity_abort_cnt"},
301 {"rx_tcode_rda_fail_cnt"},
302 {"rx_tcode_unkn_prot_cnt"},
303 {"rx_tcode_fcs_err_cnt"},
304 {"rx_tcode_buf_size_err_cnt"},
305 {"rx_tcode_rxd_corrupt_cnt"},
306 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 307 {"tda_err_cnt"},
308 {"pfc_err_cnt"},
309 {"pcc_err_cnt"},
310 {"tti_err_cnt"},
311 {"tpa_err_cnt"},
312 {"sm_err_cnt"},
313 {"lso_err_cnt"},
314 {"mac_tmac_err_cnt"},
315 {"mac_rmac_err_cnt"},
316 {"xgxs_txgxs_err_cnt"},
317 {"xgxs_rxgxs_err_cnt"},
318 {"rc_err_cnt"},
319 {"prc_pcix_err_cnt"},
320 {"rpa_err_cnt"},
321 {"rda_err_cnt"},
322 {"rti_err_cnt"},
323 {"mc_err_cnt"}
1da177e4
LT		 324};
325
4c3616cd
AMR		 326#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
327#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
328#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3
SS		 329
330#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
331#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
332
333#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
334#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4 335
4c3616cd 336#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
1da177e4
LT		 337#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
338
25fff88e 339#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
340 init_timer(&timer); \
341 timer.function = handle; \
342 timer.data = (unsigned long) arg; \
343 mod_timer(&timer, (jiffies + exp)) \
344
2fd37688
SS		 345/* copy mac addr to def_mac_addr array */
346static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
347{
348 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
349 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
350 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
351 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
352 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
353 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
354}
be3a6b02 355/* Add the vlan */
356static void s2io_vlan_rx_register(struct net_device *dev,
357 struct vlan_group *grp)
358{
2fda096d 359 int i;
1ee6dd77 360 struct s2io_nic *nic = dev->priv;
2fda096d
SR		 361 unsigned long flags[MAX_TX_FIFOS];
362 struct mac_info *mac_control = &nic->mac_control;
363 struct config_param *config = &nic->config;
364
365 for (i = 0; i < config->tx_fifo_num; i++)
366 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
be3a6b02 367
be3a6b02 368 nic->vlgrp = grp;
2fda096d
SR		 369 for (i = config->tx_fifo_num - 1; i >= 0; i--)
370 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
371 flags[i]);
be3a6b02 372}
373
926930b2 374/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
7b490343 375static int vlan_strip_flag;
926930b2 376
cdb5bf02
SH		 377/* Unregister the vlan */
378static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
379{
380 int i;
381 struct s2io_nic *nic = dev->priv;
382 unsigned long flags[MAX_TX_FIFOS];
383 struct mac_info *mac_control = &nic->mac_control;
384 struct config_param *config = &nic->config;
385
386 for (i = 0; i < config->tx_fifo_num; i++)
387 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
388
389 if (nic->vlgrp)
390 vlan_group_set_device(nic->vlgrp, vid, NULL);
391
392 for (i = config->tx_fifo_num - 1; i >= 0; i--)
393 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
394 flags[i]);
395}
396
20346722 397/*
1da177e4
LT		 398 * Constants to be programmed into the Xena's registers, to configure
399 * the XAUI.
400 */
401
1da177e4 402#define END_SIGN 0x0
f71e1309 403static const u64 herc_act_dtx_cfg[] = {
541ae68f 404 /* Set address */
e960fc5c 405 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 406 /* Write data */
e960fc5c 407 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f 408 /* Set address */
409 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
410 /* Write data */
411 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
412 /* Set address */
e960fc5c 413 0x801205150D440000ULL, 0x801205150D4400E0ULL,
414 /* Write data */
415 0x801205150D440004ULL, 0x801205150D4400E4ULL,
416 /* Set address */
541ae68f 417 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
418 /* Write data */
419 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
420 /* Done */
421 END_SIGN
422};
423
f71e1309 424static const u64 xena_dtx_cfg[] = {
c92ca04b 425 /* Set address */
1da177e4 426 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 427 /* Write data */
428 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
429 /* Set address */
430 0x8001051500000000ULL, 0x80010515000000E0ULL,
431 /* Write data */
432 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
433 /* Set address */
1da177e4 434 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 435 /* Write data */
436 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 437 END_SIGN
438};
439
20346722 440/*
1da177e4
LT		 441 * Constants for Fixing the MacAddress problem seen mostly on
442 * Alpha machines.
443 */
f71e1309 444static const u64 fix_mac[] = {
1da177e4
LT		 445 0x0060000000000000ULL, 0x0060600000000000ULL,
446 0x0040600000000000ULL, 0x0000600000000000ULL,
447 0x0020600000000000ULL, 0x0060600000000000ULL,
448 0x0020600000000000ULL, 0x0060600000000000ULL,
449 0x0020600000000000ULL, 0x0060600000000000ULL,
450 0x0020600000000000ULL, 0x0060600000000000ULL,
451 0x0020600000000000ULL, 0x0060600000000000ULL,
452 0x0020600000000000ULL, 0x0060600000000000ULL,
453 0x0020600000000000ULL, 0x0060600000000000ULL,
454 0x0020600000000000ULL, 0x0060600000000000ULL,
455 0x0020600000000000ULL, 0x0060600000000000ULL,
456 0x0020600000000000ULL, 0x0060600000000000ULL,
457 0x0020600000000000ULL, 0x0000600000000000ULL,
458 0x0040600000000000ULL, 0x0060600000000000ULL,
459 END_SIGN
460};
461
b41477f3
AR		 462MODULE_LICENSE("GPL");
463MODULE_VERSION(DRV_VERSION);
464
465
1da177e4 466/* Module Loadable parameters. */
6cfc482b 467S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 468S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 469S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 470S2IO_PARM_INT(rx_ring_mode, 1);
471S2IO_PARM_INT(use_continuous_tx_intrs, 1);
472S2IO_PARM_INT(rmac_pause_time, 0x100);
473S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
474S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
475S2IO_PARM_INT(shared_splits, 0);
476S2IO_PARM_INT(tmac_util_period, 5);
477S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 478S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 479/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
480S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 481/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 482S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 483/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 484S2IO_PARM_INT(intr_type, 2);
7d3d0439 485/* Large receive offload feature */
43b7c451
SH		 486static unsigned int lro_enable;
487module_param_named(lro, lro_enable, uint, 0);
488
7d3d0439
RA		 489/* Max pkts to be aggregated by LRO at one time. If not specified,
490 * aggregation happens until we hit max IP pkt size(64K)
491 */
b41477f3 492S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 493S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 494
495S2IO_PARM_INT(napi, 1);
496S2IO_PARM_INT(ufo, 0);
926930b2 497S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 498
499static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
500 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
501static unsigned int rx_ring_sz[MAX_RX_RINGS] =
502 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
503static unsigned int rts_frm_len[MAX_RX_RINGS] =
504 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
505
506module_param_array(tx_fifo_len, uint, NULL, 0);
507module_param_array(rx_ring_sz, uint, NULL, 0);
508module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 509
20346722 510/*
1da177e4 511 * S2IO device table.
20346722 512 * This table lists all the devices that this driver supports.
1da177e4
LT		 513 */
514static struct pci_device_id s2io_tbl[] __devinitdata = {
515 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
516 PCI_ANY_ID, PCI_ANY_ID},
517 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
518 PCI_ANY_ID, PCI_ANY_ID},
519 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722 520 PCI_ANY_ID, PCI_ANY_ID},
521 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
522 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 523 {0,}
524};
525
526MODULE_DEVICE_TABLE(pci, s2io_tbl);
527
d796fdb7
LV		 528static struct pci_error_handlers s2io_err_handler = {
529 .error_detected = s2io_io_error_detected,
530 .slot_reset = s2io_io_slot_reset,
531 .resume = s2io_io_resume,
532};
533
1da177e4
LT		 534static struct pci_driver s2io_driver = {
535 .name = "S2IO",
536 .id_table = s2io_tbl,
537 .probe = s2io_init_nic,
538 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 539 .err_handler = &s2io_err_handler,
1da177e4
LT		 540};
541
542/* A simplifier macro used both by init and free shared_mem Fns(). */
543#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
544
3a3d5756
SH		 545/* netqueue manipulation helper functions */
546static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
547{
548 int i;
549#ifdef CONFIG_NETDEVICES_MULTIQUEUE
550 if (sp->config.multiq) {
551 for (i = 0; i < sp->config.tx_fifo_num; i++)
552 netif_stop_subqueue(sp->dev, i);
553 } else
554#endif
555 {
556 for (i = 0; i < sp->config.tx_fifo_num; i++)
557 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
558 netif_stop_queue(sp->dev);
559 }
560}
561
562static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
563{
564#ifdef CONFIG_NETDEVICES_MULTIQUEUE
565 if (sp->config.multiq)
566 netif_stop_subqueue(sp->dev, fifo_no);
567 else
568#endif
569 {
570 sp->mac_control.fifos[fifo_no].queue_state =
571 FIFO_QUEUE_STOP;
572 netif_stop_queue(sp->dev);
573 }
574}
575
576static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
577{
578 int i;
579#ifdef CONFIG_NETDEVICES_MULTIQUEUE
580 if (sp->config.multiq) {
581 for (i = 0; i < sp->config.tx_fifo_num; i++)
582 netif_start_subqueue(sp->dev, i);
583 } else
584#endif
585 {
586 for (i = 0; i < sp->config.tx_fifo_num; i++)
587 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
588 netif_start_queue(sp->dev);
589 }
590}
591
592static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
593{
594#ifdef CONFIG_NETDEVICES_MULTIQUEUE
595 if (sp->config.multiq)
596 netif_start_subqueue(sp->dev, fifo_no);
597 else
598#endif
599 {
600 sp->mac_control.fifos[fifo_no].queue_state =
601 FIFO_QUEUE_START;
602 netif_start_queue(sp->dev);
603 }
604}
605
606static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
607{
608 int i;
609#ifdef CONFIG_NETDEVICES_MULTIQUEUE
610 if (sp->config.multiq) {
611 for (i = 0; i < sp->config.tx_fifo_num; i++)
612 netif_wake_subqueue(sp->dev, i);
613 } else
614#endif
615 {
616 for (i = 0; i < sp->config.tx_fifo_num; i++)
617 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
618 netif_wake_queue(sp->dev);
619 }
620}
621
622static inline void s2io_wake_tx_queue(
623 struct fifo_info *fifo, int cnt, u8 multiq)
624{
625
626#ifdef CONFIG_NETDEVICES_MULTIQUEUE
627 if (multiq) {
628 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
629 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
630 } else
631#endif
632 if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
633 if (netif_queue_stopped(fifo->dev)) {
634 fifo->queue_state = FIFO_QUEUE_START;
635 netif_wake_queue(fifo->dev);
636 }
637 }
638}
639
1da177e4
LT		 640/**
641 * init_shared_mem - Allocation and Initialization of Memory
642 * @nic: Device private variable.
20346722 643 * Description: The function allocates all the memory areas shared
644 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 645 * Rx descriptors and the statistics block.
646 */
647
648static int init_shared_mem(struct s2io_nic *nic)
649{
650 u32 size;
651 void *tmp_v_addr, *tmp_v_addr_next;
652 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 653 struct RxD_block *pre_rxd_blk = NULL;
372cc597 654 int i, j, blk_cnt;
1da177e4
LT		 655 int lst_size, lst_per_page;
656 struct net_device *dev = nic->dev;
8ae418cf 657 unsigned long tmp;
1ee6dd77 658 struct buffAdd *ba;
1da177e4 659
1ee6dd77 660 struct mac_info *mac_control;
1da177e4 661 struct config_param *config;
491976b2 662 unsigned long long mem_allocated = 0;
1da177e4
LT		 663
664 mac_control = &nic->mac_control;
665 config = &nic->config;
666
667
668 /* Allocation and initialization of TXDLs in FIOFs */
669 size = 0;
670 for (i = 0; i < config->tx_fifo_num; i++) {
671 size += config->tx_cfg[i].fifo_len;
672 }
673 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 674 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 675 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 676 return -EINVAL;
1da177e4
LT		 677 }
678
2fda096d
SR		 679 size = 0;
680 for (i = 0; i < config->tx_fifo_num; i++) {
681 size = config->tx_cfg[i].fifo_len;
682 /*
683 * Legal values are from 2 to 8192
684 */
685 if (size < 2) {
686 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
687 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
688 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
689 "are 2 to 8192\n");
690 return -EINVAL;
691 }
692 }
693
1ee6dd77 694 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 695 lst_per_page = PAGE_SIZE / lst_size;
696
697 for (i = 0; i < config->tx_fifo_num; i++) {
698 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 699 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
bd684e43 700 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
20346722 701 GFP_KERNEL);
702 if (!mac_control->fifos[i].list_info) {
0c61ed5f 703 DBG_PRINT(INFO_DBG,
1da177e4
LT		 704 "Malloc failed for list_info\n");
705 return -ENOMEM;
706 }
491976b2 707 mem_allocated += list_holder_size;
1da177e4
LT		 708 }
709 for (i = 0; i < config->tx_fifo_num; i++) {
710 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
711 lst_per_page);
20346722 712 mac_control->fifos[i].tx_curr_put_info.offset = 0;
713 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 714 config->tx_cfg[i].fifo_len - 1;
20346722 715 mac_control->fifos[i].tx_curr_get_info.offset = 0;
716 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 717 config->tx_cfg[i].fifo_len - 1;
20346722 718 mac_control->fifos[i].fifo_no = i;
719 mac_control->fifos[i].nic = nic;
fed5eccd 720 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
3a3d5756 721 mac_control->fifos[i].dev = dev;
20346722 722
1da177e4
LT		 723 for (j = 0; j < page_num; j++) {
724 int k = 0;
725 dma_addr_t tmp_p;
726 void *tmp_v;
727 tmp_v = pci_alloc_consistent(nic->pdev,
728 PAGE_SIZE, &tmp_p);
729 if (!tmp_v) {
0c61ed5f 730 DBG_PRINT(INFO_DBG,
1da177e4 731 "pci_alloc_consistent ");
0c61ed5f 732 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 733 return -ENOMEM;
734 }
776bd20f 735 /* If we got a zero DMA address(can happen on
736 * certain platforms like PPC), reallocate.
737 * Store virtual address of page we don't want,
738 * to be freed later.
739 */
740 if (!tmp_p) {
741 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 742 DBG_PRINT(INIT_DBG,
776bd20f 743 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 744 DBG_PRINT(INIT_DBG,
6b4d617d 745 "Virtual address %p\n", tmp_v);
776bd20f 746 tmp_v = pci_alloc_consistent(nic->pdev,
747 PAGE_SIZE, &tmp_p);
748 if (!tmp_v) {
0c61ed5f 749 DBG_PRINT(INFO_DBG,
776bd20f 750 "pci_alloc_consistent ");
0c61ed5f 751 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 752 return -ENOMEM;
753 }
491976b2 754 mem_allocated += PAGE_SIZE;
776bd20f 755 }
1da177e4
LT		 756 while (k < lst_per_page) {
757 int l = (j * lst_per_page) + k;
758 if (l == config->tx_cfg[i].fifo_len)
20346722 759 break;
760 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 761 tmp_v + (k * lst_size);
20346722 762 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 763 tmp_p + (k * lst_size);
764 k++;
765 }
766 }
767 }
1da177e4 768
2fda096d
SR		 769 for (i = 0; i < config->tx_fifo_num; i++) {
770 size = config->tx_cfg[i].fifo_len;
771 mac_control->fifos[i].ufo_in_band_v
772 = kcalloc(size, sizeof(u64), GFP_KERNEL);
773 if (!mac_control->fifos[i].ufo_in_band_v)
774 return -ENOMEM;
775 mem_allocated += (size * sizeof(u64));
776 }
fed5eccd 777
1da177e4
LT		 778 /* Allocation and initialization of RXDs in Rings */
779 size = 0;
780 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 781 if (config->rx_cfg[i].num_rxd %
782 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 783 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
784 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
785 i);
786 DBG_PRINT(ERR_DBG, "RxDs per Block");
787 return FAILURE;
788 }
789 size += config->rx_cfg[i].num_rxd;
20346722 790 mac_control->rings[i].block_count =
da6971d8
AR		 791 config->rx_cfg[i].num_rxd /
792 (rxd_count[nic->rxd_mode] + 1 );
793 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
794 mac_control->rings[i].block_count;
1da177e4 795 }
da6971d8 796 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 797 size = (size * (sizeof(struct RxD1)));
da6971d8 798 else
1ee6dd77 799 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 800
801 for (i = 0; i < config->rx_ring_num; i++) {
20346722 802 mac_control->rings[i].rx_curr_get_info.block_index = 0;
803 mac_control->rings[i].rx_curr_get_info.offset = 0;
804 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 805 config->rx_cfg[i].num_rxd - 1;
20346722 806 mac_control->rings[i].rx_curr_put_info.block_index = 0;
807 mac_control->rings[i].rx_curr_put_info.offset = 0;
808 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 809 config->rx_cfg[i].num_rxd - 1;
20346722 810 mac_control->rings[i].nic = nic;
811 mac_control->rings[i].ring_no = i;
0425b46a 812 mac_control->rings[i].lro = lro_enable;
20346722 813
da6971d8
AR		 814 blk_cnt = config->rx_cfg[i].num_rxd /
815 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 816 /* Allocating all the Rx blocks */
817 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 818 struct rx_block_info *rx_blocks;
da6971d8
AR		 819 int l;
820
821 rx_blocks = &mac_control->rings[i].rx_blocks[j];
822 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 823 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
824 &tmp_p_addr);
825 if (tmp_v_addr == NULL) {
826 /*
20346722 827 * In case of failure, free_shared_mem()
828 * is called, which should free any
829 * memory that was alloced till the
1da177e4
LT		 830 * failure happened.
831 */
da6971d8 832 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 833 return -ENOMEM;
834 }
491976b2 835 mem_allocated += size;
1da177e4 836 memset(tmp_v_addr, 0, size);
da6971d8
AR		 837 rx_blocks->block_virt_addr = tmp_v_addr;
838 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 839 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 840 rxd_count[nic->rxd_mode],
841 GFP_KERNEL);
372cc597
SS		 842 if (!rx_blocks->rxds)
843 return -ENOMEM;
8a4bdbaa 844 mem_allocated +=
491976b2 845 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
da6971d8
AR		 846 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
847 rx_blocks->rxds[l].virt_addr =
848 rx_blocks->block_virt_addr +
849 (rxd_size[nic->rxd_mode] * l);
850 rx_blocks->rxds[l].dma_addr =
851 rx_blocks->block_dma_addr +
852 (rxd_size[nic->rxd_mode] * l);
853 }
1da177e4
LT		 854 }
855 /* Interlinking all Rx Blocks */
856 for (j = 0; j < blk_cnt; j++) {
20346722 857 tmp_v_addr =
858 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 859 tmp_v_addr_next =
20346722 860 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 861 blk_cnt].block_virt_addr;
20346722 862 tmp_p_addr =
863 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 864 tmp_p_addr_next =
20346722 865 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 866 blk_cnt].block_dma_addr;
867
1ee6dd77 868 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 869 pre_rxd_blk->reserved_2_pNext_RxD_block =
870 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 871 pre_rxd_blk->pNext_RxD_Blk_physical =
872 (u64) tmp_p_addr_next;
873 }
874 }
6d517a27 875 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 876 /*
877 * Allocation of Storages for buffer addresses in 2BUFF mode
878 * and the buffers as well.
879 */
880 for (i = 0; i < config->rx_ring_num; i++) {
881 blk_cnt = config->rx_cfg[i].num_rxd /
882 (rxd_count[nic->rxd_mode]+ 1);
883 mac_control->rings[i].ba =
1ee6dd77 884 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 885 GFP_KERNEL);
da6971d8 886 if (!mac_control->rings[i].ba)
1da177e4 887 return -ENOMEM;
491976b2 888 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
da6971d8
AR		 889 for (j = 0; j < blk_cnt; j++) {
890 int k = 0;
891 mac_control->rings[i].ba[j] =
1ee6dd77 892 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 893 (rxd_count[nic->rxd_mode] + 1)),
894 GFP_KERNEL);
895 if (!mac_control->rings[i].ba[j])
1da177e4 896 return -ENOMEM;
491976b2
SH		 897 mem_allocated += (sizeof(struct buffAdd) * \
898 (rxd_count[nic->rxd_mode] + 1));
da6971d8
AR		 899 while (k != rxd_count[nic->rxd_mode]) {
900 ba = &mac_control->rings[i].ba[j][k];
901
902 ba->ba_0_org = (void *) kmalloc
903 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
904 if (!ba->ba_0_org)
905 return -ENOMEM;
8a4bdbaa 906 mem_allocated +=
491976b2 907 (BUF0_LEN + ALIGN_SIZE);
da6971d8
AR		 908 tmp = (unsigned long)ba->ba_0_org;
909 tmp += ALIGN_SIZE;
910 tmp &= ~((unsigned long) ALIGN_SIZE);
911 ba->ba_0 = (void *) tmp;
912
913 ba->ba_1_org = (void *) kmalloc
914 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
915 if (!ba->ba_1_org)
916 return -ENOMEM;
8a4bdbaa 917 mem_allocated
491976b2 918 += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 919 tmp = (unsigned long) ba->ba_1_org;
920 tmp += ALIGN_SIZE;
921 tmp &= ~((unsigned long) ALIGN_SIZE);
922 ba->ba_1 = (void *) tmp;
923 k++;
924 }
1da177e4
LT		 925 }
926 }
927 }
1da177e4
LT		 928
929 /* Allocation and initialization of Statistics block */
1ee6dd77 930 size = sizeof(struct stat_block);
1da177e4
LT		 931 mac_control->stats_mem = pci_alloc_consistent
932 (nic->pdev, size, &mac_control->stats_mem_phy);
933
934 if (!mac_control->stats_mem) {
20346722 935 /*
936 * In case of failure, free_shared_mem() is called, which
937 * should free any memory that was alloced till the
1da177e4
LT		 938 * failure happened.
939 */
940 return -ENOMEM;
941 }
491976b2 942 mem_allocated += size;
1da177e4
LT		 943 mac_control->stats_mem_sz = size;
944
945 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 946 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 947 memset(tmp_v_addr, 0, size);
1da177e4
LT		 948 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
949 (unsigned long long) tmp_p_addr);
491976b2 950 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 951 return SUCCESS;
952}
953
20346722 954/**
955 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 956 * @nic: Device private variable.
957 * Description: This function is to free all memory locations allocated by
958 * the init_shared_mem() function and return it to the kernel.
959 */
960
961static void free_shared_mem(struct s2io_nic *nic)
962{
963 int i, j, blk_cnt, size;
964 void *tmp_v_addr;
965 dma_addr_t tmp_p_addr;
1ee6dd77 966 struct mac_info *mac_control;
1da177e4
LT		 967 struct config_param *config;
968 int lst_size, lst_per_page;
8910b49f 969 struct net_device *dev;
491976b2 970 int page_num = 0;
1da177e4
LT		 971
972 if (!nic)
973 return;
974
8910b49f
MG		 975 dev = nic->dev;
976
1da177e4
LT		 977 mac_control = &nic->mac_control;
978 config = &nic->config;
979
1ee6dd77 980 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 981 lst_per_page = PAGE_SIZE / lst_size;
982
983 for (i = 0; i < config->tx_fifo_num; i++) {
491976b2
SH		 984 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
985 lst_per_page);
1da177e4
LT		 986 for (j = 0; j < page_num; j++) {
987 int mem_blks = (j * lst_per_page);
776bd20f 988 if (!mac_control->fifos[i].list_info)
6aa20a22 989 return;
776bd20f 990 if (!mac_control->fifos[i].list_info[mem_blks].
991 list_virt_addr)
1da177e4
LT		 992 break;
993 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722 994 mac_control->fifos[i].
995 list_info[mem_blks].
1da177e4 996 list_virt_addr,
20346722 997 mac_control->fifos[i].
998 list_info[mem_blks].
1da177e4 999 list_phy_addr);
8a4bdbaa 1000 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 1001 += PAGE_SIZE;
1da177e4 1002 }
776bd20f 1003 /* If we got a zero DMA address during allocation,
1004 * free the page now
1005 */
1006 if (mac_control->zerodma_virt_addr) {
1007 pci_free_consistent(nic->pdev, PAGE_SIZE,
1008 mac_control->zerodma_virt_addr,
1009 (dma_addr_t)0);
6aa20a22 1010 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 1011 "%s: Freeing TxDL with zero DMA addr. ",
1012 dev->name);
1013 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
1014 mac_control->zerodma_virt_addr);
8a4bdbaa 1015 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 1016 += PAGE_SIZE;
776bd20f 1017 }
20346722 1018 kfree(mac_control->fifos[i].list_info);
8a4bdbaa 1019 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1020 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 1021 }
1022
1da177e4 1023 size = SIZE_OF_BLOCK;
1da177e4 1024 for (i = 0; i < config->rx_ring_num; i++) {
20346722 1025 blk_cnt = mac_control->rings[i].block_count;
1da177e4 1026 for (j = 0; j < blk_cnt; j++) {
20346722 1027 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
1028 block_virt_addr;
1029 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
1030 block_dma_addr;
1da177e4
LT		 1031 if (tmp_v_addr == NULL)
1032 break;
1033 pci_free_consistent(nic->pdev, size,
1034 tmp_v_addr, tmp_p_addr);
491976b2 1035 nic->mac_control.stats_info->sw_stat.mem_freed += size;
da6971d8 1036 kfree(mac_control->rings[i].rx_blocks[j].rxds);
8a4bdbaa 1037 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1038 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 1039 }
1040 }
1041
6d517a27 1042 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1043 /* Freeing buffer storage addresses in 2BUFF mode. */
1044 for (i = 0; i < config->rx_ring_num; i++) {
1045 blk_cnt = config->rx_cfg[i].num_rxd /
1046 (rxd_count[nic->rxd_mode] + 1);
1047 for (j = 0; j < blk_cnt; j++) {
1048 int k = 0;
1049 if (!mac_control->rings[i].ba[j])
1050 continue;
1051 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 1052 struct buffAdd *ba =
da6971d8
AR		 1053 &mac_control->rings[i].ba[j][k];
1054 kfree(ba->ba_0_org);
491976b2
SH		 1055 nic->mac_control.stats_info->sw_stat.\
1056 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 1057 kfree(ba->ba_1_org);
491976b2
SH		 1058 nic->mac_control.stats_info->sw_stat.\
1059 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 1060 k++;
1061 }
1062 kfree(mac_control->rings[i].ba[j]);
9caab458
SS		 1063 nic->mac_control.stats_info->sw_stat.mem_freed +=
1064 (sizeof(struct buffAdd) *
1065 (rxd_count[nic->rxd_mode] + 1));
1da177e4 1066 }
da6971d8 1067 kfree(mac_control->rings[i].ba);
8a4bdbaa 1068 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1069 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 1070 }
1da177e4 1071 }
1da177e4 1072
2fda096d
SR		 1073 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1074 if (mac_control->fifos[i].ufo_in_band_v) {
1075 nic->mac_control.stats_info->sw_stat.mem_freed
1076 += (config->tx_cfg[i].fifo_len * sizeof(u64));
1077 kfree(mac_control->fifos[i].ufo_in_band_v);
1078 }
1079 }
1080
1da177e4 1081 if (mac_control->stats_mem) {
2fda096d
SR		 1082 nic->mac_control.stats_info->sw_stat.mem_freed +=
1083 mac_control->stats_mem_sz;
1da177e4
LT		 1084 pci_free_consistent(nic->pdev,
1085 mac_control->stats_mem_sz,
1086 mac_control->stats_mem,
1087 mac_control->stats_mem_phy);
491976b2 1088 }
1da177e4
LT		 1089}
1090
541ae68f 1091/**
1092 * s2io_verify_pci_mode -
1093 */
1094
1ee6dd77 1095static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1096{
1ee6dd77 1097 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1098 register u64 val64 = 0;
1099 int mode;
1100
1101 val64 = readq(&bar0->pci_mode);
1102 mode = (u8)GET_PCI_MODE(val64);
1103
1104 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1105 return -1; /* Unknown PCI mode */
1106 return mode;
1107}
1108
c92ca04b
AR		 1109#define NEC_VENID 0x1033
1110#define NEC_DEVID 0x0125
1111static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1112{
1113 struct pci_dev *tdev = NULL;
26d36b64
AC		 1114 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1115 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 1116 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 1117 pci_dev_put(tdev);
c92ca04b
AR		 1118 return 1;
1119 }
1120 }
1121 return 0;
1122}
541ae68f 1123
7b32a312 1124static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f 1125/**
1126 * s2io_print_pci_mode -
1127 */
1ee6dd77 1128static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1129{
1ee6dd77 1130 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1131 register u64 val64 = 0;
1132 int mode;
1133 struct config_param *config = &nic->config;
1134
1135 val64 = readq(&bar0->pci_mode);
1136 mode = (u8)GET_PCI_MODE(val64);
1137
1138 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1139 return -1; /* Unknown PCI mode */
1140
c92ca04b
AR		 1141 config->bus_speed = bus_speed[mode];
1142
1143 if (s2io_on_nec_bridge(nic->pdev)) {
1144 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1145 nic->dev->name);
1146 return mode;
1147 }
1148
541ae68f 1149 if (val64 & PCI_MODE_32_BITS) {
1150 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1151 } else {
1152 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1153 }
1154
1155 switch(mode) {
1156 case PCI_MODE_PCI_33:
1157 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f 1158 break;
1159 case PCI_MODE_PCI_66:
1160 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f 1161 break;
1162 case PCI_MODE_PCIX_M1_66:
1163 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f 1164 break;
1165 case PCI_MODE_PCIX_M1_100:
1166 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f 1167 break;
1168 case PCI_MODE_PCIX_M1_133:
1169 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f 1170 break;
1171 case PCI_MODE_PCIX_M2_66:
1172 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f 1173 break;
1174 case PCI_MODE_PCIX_M2_100:
1175 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f 1176 break;
1177 case PCI_MODE_PCIX_M2_133:
1178 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f 1179 break;
1180 default:
1181 return -1; /* Unsupported bus speed */
1182 }
1183
1184 return mode;
1185}
1186
b7c5678f
RV		 1187/**
1188 * init_tti - Initialization transmit traffic interrupt scheme
1189 * @nic: device private variable
1190 * @link: link status (UP/DOWN) used to enable/disable continuous
1191 * transmit interrupts
1192 * Description: The function configures transmit traffic interrupts
1193 * Return Value: SUCCESS on success and
1194 * '-1' on failure
1195 */
1196
0d66afe7 1197static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1198{
1199 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1200 register u64 val64 = 0;
1201 int i;
1202 struct config_param *config;
1203
1204 config = &nic->config;
1205
1206 for (i = 0; i < config->tx_fifo_num; i++) {
1207 /*
1208 * TTI Initialization. Default Tx timer gets us about
1209 * 250 interrupts per sec. Continuous interrupts are enabled
1210 * by default.
1211 */
1212 if (nic->device_type == XFRAME_II_DEVICE) {
1213 int count = (nic->config.bus_speed * 125)/2;
1214 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1215 } else
1216 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1217
1218 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1219 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1220 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1221 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1222
1223 if (use_continuous_tx_intrs && (link == LINK_UP))
1224 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1225 writeq(val64, &bar0->tti_data1_mem);
1226
1227 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1228 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1229 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1230 TTI_DATA2_MEM_TX_UFC_D(0x80);
1231
1232 writeq(val64, &bar0->tti_data2_mem);
1233
1234 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1235 TTI_CMD_MEM_OFFSET(i);
1236 writeq(val64, &bar0->tti_command_mem);
1237
1238 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1239 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1240 return FAILURE;
1241 }
1242
1243 return SUCCESS;
1244}
1245
20346722 1246/**
1247 * init_nic - Initialization of hardware
b7c5678f 1248 * @nic: device private variable
20346722 1249 * Description: The function sequentially configures every block
1250 * of the H/W from their reset values.
1251 * Return Value: SUCCESS on success and
1da177e4
LT		 1252 * '-1' on failure (endian settings incorrect).
1253 */
1254
1255static int init_nic(struct s2io_nic *nic)
1256{
1ee6dd77 1257 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1258 struct net_device *dev = nic->dev;
1259 register u64 val64 = 0;
1260 void __iomem *add;
1261 u32 time;
1262 int i, j;
1ee6dd77 1263 struct mac_info *mac_control;
1da177e4 1264 struct config_param *config;
c92ca04b 1265 int dtx_cnt = 0;
1da177e4 1266 unsigned long long mem_share;
20346722 1267 int mem_size;
1da177e4
LT		 1268
1269 mac_control = &nic->mac_control;
1270 config = &nic->config;
1271
5e25b9dd 1272 /* to set the swapper controle on the card */
20346722 1273 if(s2io_set_swapper(nic)) {
1da177e4 1274 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
9f74ffde 1275 return -EIO;
1da177e4
LT		 1276 }
1277
541ae68f 1278 /*
1279 * Herc requires EOI to be removed from reset before XGXS, so..
1280 */
1281 if (nic->device_type & XFRAME_II_DEVICE) {
1282 val64 = 0xA500000000ULL;
1283 writeq(val64, &bar0->sw_reset);
1284 msleep(500);
1285 val64 = readq(&bar0->sw_reset);
1286 }
1287
1da177e4
LT		 1288 /* Remove XGXS from reset state */
1289 val64 = 0;
1290 writeq(val64, &bar0->sw_reset);
1da177e4 1291 msleep(500);
20346722 1292 val64 = readq(&bar0->sw_reset);
1da177e4 1293
7962024e
SH		 1294 /* Ensure that it's safe to access registers by checking
1295 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1296 */
1297 if (nic->device_type == XFRAME_II_DEVICE) {
1298 for (i = 0; i < 50; i++) {
1299 val64 = readq(&bar0->adapter_status);
1300 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1301 break;
1302 msleep(10);
1303 }
1304 if (i == 50)
1305 return -ENODEV;
1306 }
1307
1da177e4
LT		 1308 /* Enable Receiving broadcasts */
1309 add = &bar0->mac_cfg;
1310 val64 = readq(&bar0->mac_cfg);
1311 val64 |= MAC_RMAC_BCAST_ENABLE;
1312 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1313 writel((u32) val64, add);
1314 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1315 writel((u32) (val64 >> 32), (add + 4));
1316
1317 /* Read registers in all blocks */
1318 val64 = readq(&bar0->mac_int_mask);
1319 val64 = readq(&bar0->mc_int_mask);
1320 val64 = readq(&bar0->xgxs_int_mask);
1321
1322 /* Set MTU */
1323 val64 = dev->mtu;
1324 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1325
541ae68f 1326 if (nic->device_type & XFRAME_II_DEVICE) {
1327 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1328 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1329 &bar0->dtx_control, UF);
541ae68f 1330 if (dtx_cnt & 0x1)
1331 msleep(1); /* Necessary!! */
1da177e4
LT		 1332 dtx_cnt++;
1333 }
541ae68f 1334 } else {
c92ca04b
AR		 1335 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1336 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1337 &bar0->dtx_control, UF);
1338 val64 = readq(&bar0->dtx_control);
1339 dtx_cnt++;
1da177e4
LT		 1340 }
1341 }
1342
1343 /* Tx DMA Initialization */
1344 val64 = 0;
1345 writeq(val64, &bar0->tx_fifo_partition_0);
1346 writeq(val64, &bar0->tx_fifo_partition_1);
1347 writeq(val64, &bar0->tx_fifo_partition_2);
1348 writeq(val64, &bar0->tx_fifo_partition_3);
1349
1350
1351 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1352 val64 |=
b7c5678f 1353 vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1da177e4 1354 13) | vBIT(config->tx_cfg[i].fifo_priority,
b7c5678f 1355 ((j * 32) + 5), 3);
1da177e4
LT		 1356
1357 if (i == (config->tx_fifo_num - 1)) {
1358 if (i % 2 == 0)
1359 i++;
1360 }
1361
1362 switch (i) {
1363 case 1:
1364 writeq(val64, &bar0->tx_fifo_partition_0);
1365 val64 = 0;
b7c5678f 1366 j = 0;
1da177e4
LT		 1367 break;
1368 case 3:
1369 writeq(val64, &bar0->tx_fifo_partition_1);
1370 val64 = 0;
b7c5678f 1371 j = 0;
1da177e4
LT		 1372 break;
1373 case 5:
1374 writeq(val64, &bar0->tx_fifo_partition_2);
1375 val64 = 0;
b7c5678f 1376 j = 0;
1da177e4
LT		 1377 break;
1378 case 7:
1379 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1380 val64 = 0;
1381 j = 0;
1382 break;
1383 default:
1384 j++;
1da177e4
LT		 1385 break;
1386 }
1387 }
1388
5e25b9dd 1389 /*
1390 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1391 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1392 */
541ae68f 1393 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1394 (nic->pdev->revision < 4))
5e25b9dd 1395 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1396
1da177e4
LT		 1397 val64 = readq(&bar0->tx_fifo_partition_0);
1398 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1399 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1400
20346722 1401 /*
1402 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1403 * integrity checking.
1404 */
1405 val64 = readq(&bar0->tx_pa_cfg);
1406 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1407 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1408 writeq(val64, &bar0->tx_pa_cfg);
1409
1410 /* Rx DMA intialization. */
1411 val64 = 0;
1412 for (i = 0; i < config->rx_ring_num; i++) {
1413 val64 |=
1414 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1415 3);
1416 }
1417 writeq(val64, &bar0->rx_queue_priority);
1418
20346722 1419 /*
1420 * Allocating equal share of memory to all the
1da177e4
LT		 1421 * configured Rings.
1422 */
1423 val64 = 0;
541ae68f 1424 if (nic->device_type & XFRAME_II_DEVICE)
1425 mem_size = 32;
1426 else
1427 mem_size = 64;
1428
1da177e4
LT		 1429 for (i = 0; i < config->rx_ring_num; i++) {
1430 switch (i) {
1431 case 0:
20346722 1432 mem_share = (mem_size / config->rx_ring_num +
1433 mem_size % config->rx_ring_num);
1da177e4
LT		 1434 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1435 continue;
1436 case 1:
20346722 1437 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1438 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1439 continue;
1440 case 2:
20346722 1441 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1442 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1443 continue;
1444 case 3:
20346722 1445 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1446 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1447 continue;
1448 case 4:
20346722 1449 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1450 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1451 continue;
1452 case 5:
20346722 1453 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1454 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1455 continue;
1456 case 6:
20346722 1457 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1458 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1459 continue;
1460 case 7:
20346722 1461 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1462 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1463 continue;
1464 }
1465 }
1466 writeq(val64, &bar0->rx_queue_cfg);
1467
20346722 1468 /*
5e25b9dd 1469 * Filling Tx round robin registers
b7c5678f 1470 * as per the number of FIFOs for equal scheduling priority
1da177e4 1471 */
5e25b9dd 1472 switch (config->tx_fifo_num) {
1473 case 1:
b7c5678f 1474 val64 = 0x0;
5e25b9dd 1475 writeq(val64, &bar0->tx_w_round_robin_0);
1476 writeq(val64, &bar0->tx_w_round_robin_1);
1477 writeq(val64, &bar0->tx_w_round_robin_2);
1478 writeq(val64, &bar0->tx_w_round_robin_3);
1479 writeq(val64, &bar0->tx_w_round_robin_4);
1480 break;
1481 case 2:
b7c5678f 1482 val64 = 0x0001000100010001ULL;
5e25b9dd 1483 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1484 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1485 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1486 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1487 val64 = 0x0001000100000000ULL;
5e25b9dd 1488 writeq(val64, &bar0->tx_w_round_robin_4);
1489 break;
1490 case 3:
b7c5678f 1491 val64 = 0x0001020001020001ULL;
5e25b9dd 1492 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1493 val64 = 0x0200010200010200ULL;
5e25b9dd 1494 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1495 val64 = 0x0102000102000102ULL;
5e25b9dd 1496 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1497 val64 = 0x0001020001020001ULL;
5e25b9dd 1498 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1499 val64 = 0x0200010200000000ULL;
5e25b9dd 1500 writeq(val64, &bar0->tx_w_round_robin_4);
1501 break;
1502 case 4:
b7c5678f 1503 val64 = 0x0001020300010203ULL;
5e25b9dd 1504 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1506 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1507 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1508 val64 = 0x0001020300000000ULL;
5e25b9dd 1509 writeq(val64, &bar0->tx_w_round_robin_4);
1510 break;
1511 case 5:
b7c5678f 1512 val64 = 0x0001020304000102ULL;
5e25b9dd 1513 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1514 val64 = 0x0304000102030400ULL;
5e25b9dd 1515 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1516 val64 = 0x0102030400010203ULL;
5e25b9dd 1517 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1518 val64 = 0x0400010203040001ULL;
5e25b9dd 1519 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1520 val64 = 0x0203040000000000ULL;
5e25b9dd 1521 writeq(val64, &bar0->tx_w_round_robin_4);
1522 break;
1523 case 6:
b7c5678f 1524 val64 = 0x0001020304050001ULL;
5e25b9dd 1525 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1526 val64 = 0x0203040500010203ULL;
5e25b9dd 1527 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1528 val64 = 0x0405000102030405ULL;
5e25b9dd 1529 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1530 val64 = 0x0001020304050001ULL;
5e25b9dd 1531 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1532 val64 = 0x0203040500000000ULL;
5e25b9dd 1533 writeq(val64, &bar0->tx_w_round_robin_4);
1534 break;
1535 case 7:
b7c5678f 1536 val64 = 0x0001020304050600ULL;
5e25b9dd 1537 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1538 val64 = 0x0102030405060001ULL;
5e25b9dd 1539 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1540 val64 = 0x0203040506000102ULL;
5e25b9dd 1541 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1542 val64 = 0x0304050600010203ULL;
5e25b9dd 1543 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1544 val64 = 0x0405060000000000ULL;
5e25b9dd 1545 writeq(val64, &bar0->tx_w_round_robin_4);
1546 break;
1547 case 8:
b7c5678f 1548 val64 = 0x0001020304050607ULL;
5e25b9dd 1549 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1551 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1552 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1553 val64 = 0x0001020300000000ULL;
5e25b9dd 1554 writeq(val64, &bar0->tx_w_round_robin_4);
1555 break;
1556 }
1557
b41477f3 1558 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1559 val64 = readq(&bar0->tx_fifo_partition_0);
1560 val64 |= (TX_FIFO_PARTITION_EN);
1561 writeq(val64, &bar0->tx_fifo_partition_0);
1562
5e25b9dd 1563 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1564 * number of Rings and steering based on QoS with
1565 * equal priority.
1566 */
5e25b9dd 1567 switch (config->rx_ring_num) {
1568 case 1:
0425b46a
SH		 1569 val64 = 0x0;
1570 writeq(val64, &bar0->rx_w_round_robin_0);
1571 writeq(val64, &bar0->rx_w_round_robin_1);
1572 writeq(val64, &bar0->rx_w_round_robin_2);
1573 writeq(val64, &bar0->rx_w_round_robin_3);
1574 writeq(val64, &bar0->rx_w_round_robin_4);
1575
5e25b9dd 1576 val64 = 0x8080808080808080ULL;
1577 writeq(val64, &bar0->rts_qos_steering);
1578 break;
1579 case 2:
0425b46a 1580 val64 = 0x0001000100010001ULL;
5e25b9dd 1581 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1582 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1583 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1584 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1585 val64 = 0x0001000100000000ULL;
5e25b9dd 1586 writeq(val64, &bar0->rx_w_round_robin_4);
1587
1588 val64 = 0x8080808040404040ULL;
1589 writeq(val64, &bar0->rts_qos_steering);
1590 break;
1591 case 3:
0425b46a 1592 val64 = 0x0001020001020001ULL;
5e25b9dd 1593 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1594 val64 = 0x0200010200010200ULL;
5e25b9dd 1595 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1596 val64 = 0x0102000102000102ULL;
5e25b9dd 1597 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1598 val64 = 0x0001020001020001ULL;
5e25b9dd 1599 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1600 val64 = 0x0200010200000000ULL;
5e25b9dd 1601 writeq(val64, &bar0->rx_w_round_robin_4);
1602
1603 val64 = 0x8080804040402020ULL;
1604 writeq(val64, &bar0->rts_qos_steering);
1605 break;
1606 case 4:
0425b46a 1607 val64 = 0x0001020300010203ULL;
5e25b9dd 1608 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1609 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1610 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1611 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1612 val64 = 0x0001020300000000ULL;
5e25b9dd 1613 writeq(val64, &bar0->rx_w_round_robin_4);
1614
1615 val64 = 0x8080404020201010ULL;
1616 writeq(val64, &bar0->rts_qos_steering);
1617 break;
1618 case 5:
0425b46a 1619 val64 = 0x0001020304000102ULL;
5e25b9dd 1620 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1621 val64 = 0x0304000102030400ULL;
5e25b9dd 1622 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1623 val64 = 0x0102030400010203ULL;
5e25b9dd 1624 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1625 val64 = 0x0400010203040001ULL;
5e25b9dd 1626 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1627 val64 = 0x0203040000000000ULL;
5e25b9dd 1628 writeq(val64, &bar0->rx_w_round_robin_4);
1629
1630 val64 = 0x8080404020201008ULL;
1631 writeq(val64, &bar0->rts_qos_steering);
1632 break;
1633 case 6:
0425b46a 1634 val64 = 0x0001020304050001ULL;
5e25b9dd 1635 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1636 val64 = 0x0203040500010203ULL;
5e25b9dd 1637 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1638 val64 = 0x0405000102030405ULL;
5e25b9dd 1639 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1640 val64 = 0x0001020304050001ULL;
5e25b9dd 1641 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1642 val64 = 0x0203040500000000ULL;
5e25b9dd 1643 writeq(val64, &bar0->rx_w_round_robin_4);
1644
1645 val64 = 0x8080404020100804ULL;
1646 writeq(val64, &bar0->rts_qos_steering);
1647 break;
1648 case 7:
0425b46a 1649 val64 = 0x0001020304050600ULL;
5e25b9dd 1650 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1651 val64 = 0x0102030405060001ULL;
5e25b9dd 1652 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1653 val64 = 0x0203040506000102ULL;
5e25b9dd 1654 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1655 val64 = 0x0304050600010203ULL;
5e25b9dd 1656 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1657 val64 = 0x0405060000000000ULL;
5e25b9dd 1658 writeq(val64, &bar0->rx_w_round_robin_4);
1659
1660 val64 = 0x8080402010080402ULL;
1661 writeq(val64, &bar0->rts_qos_steering);
1662 break;
1663 case 8:
0425b46a 1664 val64 = 0x0001020304050607ULL;
5e25b9dd 1665 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1666 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1667 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1668 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1669 val64 = 0x0001020300000000ULL;
5e25b9dd 1670 writeq(val64, &bar0->rx_w_round_robin_4);
1671
1672 val64 = 0x8040201008040201ULL;
1673 writeq(val64, &bar0->rts_qos_steering);
1674 break;
1675 }
1da177e4
LT		 1676
1677 /* UDP Fix */
1678 val64 = 0;
20346722 1679 for (i = 0; i < 8; i++)
1da177e4
LT		 1680 writeq(val64, &bar0->rts_frm_len_n[i]);
1681
5e25b9dd 1682 /* Set the default rts frame length for the rings configured */
1683 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1684 for (i = 0 ; i < config->rx_ring_num ; i++)
1685 writeq(val64, &bar0->rts_frm_len_n[i]);
1686
1687 /* Set the frame length for the configured rings
1688 * desired by the user
1689 */
1690 for (i = 0; i < config->rx_ring_num; i++) {
1691 /* If rts_frm_len[i] == 0 then it is assumed that user not
1692 * specified frame length steering.
1693 * If the user provides the frame length then program
1694 * the rts_frm_len register for those values or else
1695 * leave it as it is.
1696 */
1697 if (rts_frm_len[i] != 0) {
1698 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1699 &bar0->rts_frm_len_n[i]);
1700 }
1701 }
8a4bdbaa 1702
9fc93a41
SS		 1703 /* Disable differentiated services steering logic */
1704 for (i = 0; i < 64; i++) {
1705 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1706 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1707 dev->name);
1708 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
9f74ffde 1709 return -ENODEV;
9fc93a41
SS		 1710 }
1711 }
1712
20346722 1713 /* Program statistics memory */
1da177e4 1714 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1715
541ae68f 1716 if (nic->device_type == XFRAME_II_DEVICE) {
1717 val64 = STAT_BC(0x320);
1718 writeq(val64, &bar0->stat_byte_cnt);
1719 }
1720
20346722 1721 /*
1da177e4
LT		 1722 * Initializing the sampling rate for the device to calculate the
1723 * bandwidth utilization.
1724 */
1725 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1726 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1727 writeq(val64, &bar0->mac_link_util);
1728
20346722 1729 /*
1730 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1731 * Scheme.
1732 */
1da177e4 1733
b7c5678f
RV		 1734 /* Initialize TTI */
1735 if (SUCCESS != init_tti(nic, nic->last_link_state))
1736 return -ENODEV;
1da177e4 1737
8a4bdbaa
SS		 1738 /* RTI Initialization */
1739 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1740 /*
8a4bdbaa
SS		 1741 * Programmed to generate Apprx 500 Intrs per
1742 * second
1743 */
1744 int count = (nic->config.bus_speed * 125)/4;
1745 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1746 } else
1747 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1748 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1749 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1750 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1751
1752 writeq(val64, &bar0->rti_data1_mem);
1753
1754 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1755 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1756 if (nic->config.intr_type == MSI_X)
1757 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1758 RTI_DATA2_MEM_RX_UFC_D(0x40));
1759 else
1760 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1761 RTI_DATA2_MEM_RX_UFC_D(0x80));
1762 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1763
8a4bdbaa
SS		 1764 for (i = 0; i < config->rx_ring_num; i++) {
1765 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1766 | RTI_CMD_MEM_OFFSET(i);
1767 writeq(val64, &bar0->rti_command_mem);
1da177e4 1768
8a4bdbaa
SS		 1769 /*
1770 * Once the operation completes, the Strobe bit of the
1771 * command register will be reset. We poll for this
1772 * particular condition. We wait for a maximum of 500ms
1773 * for the operation to complete, if it's not complete
1774 * by then we return error.
1775 */
1776 time = 0;
1777 while (TRUE) {
1778 val64 = readq(&bar0->rti_command_mem);
1779 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1780 break;
b6e3f982 1781
8a4bdbaa
SS		 1782 if (time > 10) {
1783 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1784 dev->name);
9f74ffde 1785 return -ENODEV;
b6e3f982 1786 }
8a4bdbaa
SS		 1787 time++;
1788 msleep(50);
1da177e4 1789 }
1da177e4
LT		 1790 }
1791
20346722 1792 /*
1793 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1794 * the 8 Queues on Rx side.
1795 */
1796 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1798
1799 /* Disable RMAC PAD STRIPPING */
509a2671 1800 add = &bar0->mac_cfg;
1da177e4
LT		 1801 val64 = readq(&bar0->mac_cfg);
1802 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1803 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1804 writel((u32) (val64), add);
1805 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1806 writel((u32) (val64 >> 32), (add + 4));
1807 val64 = readq(&bar0->mac_cfg);
1808
7d3d0439
RA		 1809 /* Enable FCS stripping by adapter */
1810 add = &bar0->mac_cfg;
1811 val64 = readq(&bar0->mac_cfg);
1812 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1813 if (nic->device_type == XFRAME_II_DEVICE)
1814 writeq(val64, &bar0->mac_cfg);
1815 else {
1816 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1817 writel((u32) (val64), add);
1818 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1819 writel((u32) (val64 >> 32), (add + 4));
1820 }
1821
20346722 1822 /*
1823 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1824 * generated by xena.
1825 */
1826 val64 = readq(&bar0->rmac_pause_cfg);
1827 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1828 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1829 writeq(val64, &bar0->rmac_pause_cfg);
1830
20346722 1831 /*
1da177e4
LT		 1832 * Set the Threshold Limit for Generating the pause frame
1833 * If the amount of data in any Queue exceeds ratio of
1834 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1835 * pause frame is generated
1836 */
1837 val64 = 0;
1838 for (i = 0; i < 4; i++) {
1839 val64 |=
1840 (((u64) 0xFF00 | nic->mac_control.
1841 mc_pause_threshold_q0q3)
1842 << (i * 2 * 8));
1843 }
1844 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1845
1846 val64 = 0;
1847 for (i = 0; i < 4; i++) {
1848 val64 |=
1849 (((u64) 0xFF00 | nic->mac_control.
1850 mc_pause_threshold_q4q7)
1851 << (i * 2 * 8));
1852 }
1853 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1854
20346722 1855 /*
1856 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1857 * exceeded the limit pointed by shared_splits
1858 */
1859 val64 = readq(&bar0->pic_control);
1860 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1861 writeq(val64, &bar0->pic_control);
1862
863c11a9
AR		 1863 if (nic->config.bus_speed == 266) {
1864 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1865 writeq(0x0, &bar0->read_retry_delay);
1866 writeq(0x0, &bar0->write_retry_delay);
1867 }
1868
541ae68f 1869 /*
1870 * Programming the Herc to split every write transaction
1871 * that does not start on an ADB to reduce disconnects.
1872 */
1873 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1874 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1875 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1876 writeq(val64, &bar0->misc_control);
1877 val64 = readq(&bar0->pic_control2);
b7b5a128 1878 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1879 writeq(val64, &bar0->pic_control2);
541ae68f 1880 }
c92ca04b
AR		 1881 if (strstr(nic->product_name, "CX4")) {
1882 val64 = TMAC_AVG_IPG(0x17);
1883 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d 1884 }
1885
1da177e4
LT		 1886 return SUCCESS;
1887}
a371a07d 1888#define LINK_UP_DOWN_INTERRUPT 1
1889#define MAC_RMAC_ERR_TIMER 2
1890
1ee6dd77 1891static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1892{
eaae7f72 1893 if (nic->config.intr_type != INTA)
cc6e7c44 1894 return MAC_RMAC_ERR_TIMER;
a371a07d 1895 if (nic->device_type == XFRAME_II_DEVICE)
1896 return LINK_UP_DOWN_INTERRUPT;
1897 else
1898 return MAC_RMAC_ERR_TIMER;
1899}
8116f3cf 1900
9caab458
SS		 1901/**
1902 * do_s2io_write_bits - update alarm bits in alarm register
1903 * @value: alarm bits
1904 * @flag: interrupt status
1905 * @addr: address value
1906 * Description: update alarm bits in alarm register
1907 * Return Value:
1908 * NONE.
1909 */
1910static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1911{
1912 u64 temp64;
1913
1914 temp64 = readq(addr);
1915
1916 if(flag == ENABLE_INTRS)
1917 temp64 &= ~((u64) value);
1918 else
1919 temp64 |= ((u64) value);
1920 writeq(temp64, addr);
1921}
1da177e4 1922
43b7c451 1923static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1924{
1925 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1926 register u64 gen_int_mask = 0;
1927
1928 if (mask & TX_DMA_INTR) {
1929
1930 gen_int_mask |= TXDMA_INT_M;
1931
1932 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1933 TXDMA_PCC_INT | TXDMA_TTI_INT |
1934 TXDMA_LSO_INT | TXDMA_TPA_INT |
1935 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1936
1937 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1938 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1939 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1940 &bar0->pfc_err_mask);
1941
1942 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1943 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1944 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1945
1946 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1947 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1948 PCC_N_SERR | PCC_6_COF_OV_ERR |
1949 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1950 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1951 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1952
1953 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1954 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1955
1956 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1957 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1958 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1959 flag, &bar0->lso_err_mask);
1960
1961 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1962 flag, &bar0->tpa_err_mask);
1963
1964 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1965
1966 }
1967
1968 if (mask & TX_MAC_INTR) {
1969 gen_int_mask |= TXMAC_INT_M;
1970 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1971 &bar0->mac_int_mask);
1972 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1973 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1974 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1975 flag, &bar0->mac_tmac_err_mask);
1976 }
1977
1978 if (mask & TX_XGXS_INTR) {
1979 gen_int_mask |= TXXGXS_INT_M;
1980 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1981 &bar0->xgxs_int_mask);
1982 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1983 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1984 flag, &bar0->xgxs_txgxs_err_mask);
1985 }
1986
1987 if (mask & RX_DMA_INTR) {
1988 gen_int_mask |= RXDMA_INT_M;
1989 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1990 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1991 flag, &bar0->rxdma_int_mask);
1992 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1993 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1994 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1995 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1996 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1997 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1998 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1999 &bar0->prc_pcix_err_mask);
2000 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
2001 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2002 &bar0->rpa_err_mask);
2003 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2004 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2005 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2006 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
2007 flag, &bar0->rda_err_mask);
2008 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2009 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2010 flag, &bar0->rti_err_mask);
2011 }
2012
2013 if (mask & RX_MAC_INTR) {
2014 gen_int_mask |= RXMAC_INT_M;
2015 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2016 &bar0->mac_int_mask);
2017 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2018 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2019 RMAC_DOUBLE_ECC_ERR |
2020 RMAC_LINK_STATE_CHANGE_INT,
2021 flag, &bar0->mac_rmac_err_mask);
2022 }
2023
2024 if (mask & RX_XGXS_INTR)
2025 {
2026 gen_int_mask |= RXXGXS_INT_M;
2027 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2028 &bar0->xgxs_int_mask);
2029 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2030 &bar0->xgxs_rxgxs_err_mask);
2031 }
2032
2033 if (mask & MC_INTR) {
2034 gen_int_mask |= MC_INT_M;
2035 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2036 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2037 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2038 &bar0->mc_err_mask);
2039 }
2040 nic->general_int_mask = gen_int_mask;
2041
2042 /* Remove this line when alarm interrupts are enabled */
2043 nic->general_int_mask = 0;
2044}
20346722 2045/**
2046 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2047 * @nic: device private variable,
2048 * @mask: A mask indicating which Intr block must be modified and,
2049 * @flag: A flag indicating whether to enable or disable the Intrs.
2050 * Description: This function will either disable or enable the interrupts
20346722 2051 * depending on the flag argument. The mask argument can be used to
2052 * enable/disable any Intr block.
1da177e4
LT		 2053 * Return Value: NONE.
2054 */
2055
2056static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2057{
1ee6dd77 2058 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2059 register u64 temp64 = 0, intr_mask = 0;
2060
2061 intr_mask = nic->general_int_mask;
1da177e4
LT		 2062
2063 /* Top level interrupt classification */
2064 /* PIC Interrupts */
9caab458 2065 if (mask & TX_PIC_INTR) {
1da177e4 2066 /* Enable PIC Intrs in the general intr mask register */
9caab458 2067 intr_mask |= TXPIC_INT_M;
1da177e4 2068 if (flag == ENABLE_INTRS) {
20346722 2069 /*
a371a07d 2070 * If Hercules adapter enable GPIO otherwise
b41477f3 2071 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722 2072 * interrupts for now.
2073 * TODO
1da177e4 2074 */
a371a07d 2075 if (s2io_link_fault_indication(nic) ==
2076 LINK_UP_DOWN_INTERRUPT ) {
9caab458
SS		 2077 do_s2io_write_bits(PIC_INT_GPIO, flag,
2078 &bar0->pic_int_mask);
2079 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2080 &bar0->gpio_int_mask);
2081 } else
a371a07d 2082 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2083 } else if (flag == DISABLE_INTRS) {
20346722 2084 /*
2085 * Disable PIC Intrs in the general
2086 * intr mask register
1da177e4
LT		 2087 */
2088 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2089 }
2090 }
2091
1da177e4
LT		 2092 /* Tx traffic interrupts */
2093 if (mask & TX_TRAFFIC_INTR) {
9caab458 2094 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2095 if (flag == ENABLE_INTRS) {
20346722 2096 /*
1da177e4 2097 * Enable all the Tx side interrupts
20346722 2098 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2099 */
2100 writeq(0x0, &bar0->tx_traffic_mask);
2101 } else if (flag == DISABLE_INTRS) {
20346722 2102 /*
2103 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2104 * register.
2105 */
2106 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2107 }
2108 }
2109
2110 /* Rx traffic interrupts */
2111 if (mask & RX_TRAFFIC_INTR) {
9caab458 2112 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2113 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2114 /* writing 0 Enables all 8 RX interrupt levels */
2115 writeq(0x0, &bar0->rx_traffic_mask);
2116 } else if (flag == DISABLE_INTRS) {
20346722 2117 /*
2118 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2119 * register.
2120 */
2121 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2122 }
2123 }
9caab458
SS		 2124
2125 temp64 = readq(&bar0->general_int_mask);
2126 if (flag == ENABLE_INTRS)
2127 temp64 &= ~((u64) intr_mask);
2128 else
2129 temp64 = DISABLE_ALL_INTRS;
2130 writeq(temp64, &bar0->general_int_mask);
2131
2132 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2133}
2134
19a60522
SS		 2135/**
2136 * verify_pcc_quiescent- Checks for PCC quiescent state
2137 * Return: 1 If PCC is quiescence
2138 * 0 If PCC is not quiescence
2139 */
1ee6dd77 2140static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2141{
19a60522 2142 int ret = 0, herc;
1ee6dd77 2143 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2144 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2145
19a60522 2146 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2147
2148 if (flag == FALSE) {
44c10138 2149 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2150 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2151 ret = 1;
19a60522
SS		 2152 } else {
2153 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2154 ret = 1;
20346722 2155 }
2156 } else {
44c10138 2157 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2158 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2159 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2160 ret = 1;
5e25b9dd 2161 } else {
2162 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2163 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2164 ret = 1;
20346722 2165 }
2166 }
2167
2168 return ret;
2169}
2170/**
2171 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2172 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2173 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2174 * differs and the calling function passes the input argument flag to
2175 * indicate this.
20346722 2176 * Return: 1 If xena is quiescence
1da177e4
LT		 2177 * 0 If Xena is not quiescence
2178 */
2179
1ee6dd77 2180static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2181{
19a60522 2182 int mode;
1ee6dd77 2183 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2184 u64 val64 = readq(&bar0->adapter_status);
2185 mode = s2io_verify_pci_mode(sp);
1da177e4 2186
19a60522
SS		 2187 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2188 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2189 return 0;
2190 }
2191 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2192 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2193 return 0;
2194 }
2195 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2196 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2197 return 0;
2198 }
2199 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2200 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2201 return 0;
2202 }
2203 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2204 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2205 return 0;
2206 }
2207 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2208 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2209 return 0;
2210 }
2211 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2212 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2213 return 0;
2214 }
2215 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2216 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2217 return 0;
1da177e4
LT		 2218 }
2219
19a60522
SS		 2220 /*
2221 * In PCI 33 mode, the P_PLL is not used, and therefore,
2222 * the the P_PLL_LOCK bit in the adapter_status register will
2223 * not be asserted.
2224 */
2225 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2226 sp->device_type == XFRAME_II_DEVICE && mode !=
2227 PCI_MODE_PCI_33) {
2228 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2229 return 0;
2230 }
2231 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2232 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2233 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2234 return 0;
2235 }
2236 return 1;
1da177e4
LT		 2237}
2238
2239/**
2240 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2241 * @sp: Pointer to device specifc structure
20346722 2242 * Description :
1da177e4
LT		 2243 * New procedure to clear mac address reading problems on Alpha platforms
2244 *
2245 */
2246
1ee6dd77 2247static void fix_mac_address(struct s2io_nic * sp)
1da177e4 2248{
1ee6dd77 2249 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2250 u64 val64;
2251 int i = 0;
2252
2253 while (fix_mac[i] != END_SIGN) {
2254 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2255 udelay(10);
1da177e4
LT		 2256 val64 = readq(&bar0->gpio_control);
2257 }
2258}
2259
2260/**
20346722 2261 * start_nic - Turns the device on
1da177e4 2262 * @nic : device private variable.
20346722 2263 * Description:
2264 * This function actually turns the device on. Before this function is
2265 * called,all Registers are configured from their reset states
2266 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2267 * calling this function, the device interrupts are cleared and the NIC is
2268 * literally switched on by writing into the adapter control register.
20346722 2269 * Return Value:
1da177e4
LT		 2270 * SUCCESS on success and -1 on failure.
2271 */
2272
2273static int start_nic(struct s2io_nic *nic)
2274{
1ee6dd77 2275 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2276 struct net_device *dev = nic->dev;
2277 register u64 val64 = 0;
20346722 2278 u16 subid, i;
1ee6dd77 2279 struct mac_info *mac_control;
1da177e4
LT		 2280 struct config_param *config;
2281
2282 mac_control = &nic->mac_control;
2283 config = &nic->config;
2284
2285 /* PRC Initialization and configuration */
2286 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2287 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2288 &bar0->prc_rxd0_n[i]);
2289
2290 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2291 if (nic->rxd_mode == RXD_MODE_1)
2292 val64 |= PRC_CTRL_RC_ENABLED;
2293 else
2294 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2295 if (nic->device_type == XFRAME_II_DEVICE)
2296 val64 |= PRC_CTRL_GROUP_READS;
2297 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2298 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2299 writeq(val64, &bar0->prc_ctrl_n[i]);
2300 }
2301
da6971d8
AR		 2302 if (nic->rxd_mode == RXD_MODE_3B) {
2303 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2304 val64 = readq(&bar0->rx_pa_cfg);
2305 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2306 writeq(val64, &bar0->rx_pa_cfg);
2307 }
1da177e4 2308
926930b2
SS		 2309 if (vlan_tag_strip == 0) {
2310 val64 = readq(&bar0->rx_pa_cfg);
2311 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2312 writeq(val64, &bar0->rx_pa_cfg);
2313 vlan_strip_flag = 0;
2314 }
2315
20346722 2316 /*
1da177e4
LT		 2317 * Enabling MC-RLDRAM. After enabling the device, we timeout
2318 * for around 100ms, which is approximately the time required
2319 * for the device to be ready for operation.
2320 */
2321 val64 = readq(&bar0->mc_rldram_mrs);
2322 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2323 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2324 val64 = readq(&bar0->mc_rldram_mrs);
2325
20346722 2326 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2327
2328 /* Enabling ECC Protection. */
2329 val64 = readq(&bar0->adapter_control);
2330 val64 &= ~ADAPTER_ECC_EN;
2331 writeq(val64, &bar0->adapter_control);
2332
20346722 2333 /*
2334 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2335 * it.
2336 */
2337 val64 = readq(&bar0->adapter_status);
19a60522 2338 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2339 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2340 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2341 (unsigned long long) val64);
2342 return FAILURE;
2343 }
2344
20346722 2345 /*
1da177e4 2346 * With some switches, link might be already up at this point.
20346722 2347 * Because of this weird behavior, when we enable laser,
2348 * we may not get link. We need to handle this. We cannot
2349 * figure out which switch is misbehaving. So we are forced to
2350 * make a global change.
1da177e4
LT		 2351 */
2352
2353 /* Enabling Laser. */
2354 val64 = readq(&bar0->adapter_control);
2355 val64 |= ADAPTER_EOI_TX_ON;
2356 writeq(val64, &bar0->adapter_control);
2357
c92ca04b
AR		 2358 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2359 /*
2360 * Dont see link state interrupts initally on some switches,
2361 * so directly scheduling the link state task here.
2362 */
2363 schedule_work(&nic->set_link_task);
2364 }
1da177e4
LT		 2365 /* SXE-002: Initialize link and activity LED */
2366 subid = nic->pdev->subsystem_device;
541ae68f 2367 if (((subid & 0xFF) >= 0x07) &&
2368 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2369 val64 = readq(&bar0->gpio_control);
2370 val64 |= 0x0000800000000000ULL;
2371 writeq(val64, &bar0->gpio_control);
2372 val64 = 0x0411040400000000ULL;
509a2671 2373 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2374 }
2375
1da177e4
LT		 2376 return SUCCESS;
2377}
fed5eccd
AR		 2378/**
2379 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2380 */
1ee6dd77
RB		 2381static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2382 TxD *txdlp, int get_off)
fed5eccd 2383{
1ee6dd77 2384 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2385 struct sk_buff *skb;
1ee6dd77 2386 struct TxD *txds;
fed5eccd
AR		 2387 u16 j, frg_cnt;
2388
2389 txds = txdlp;
2fda096d 2390 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
fed5eccd
AR		 2391 pci_unmap_single(nic->pdev, (dma_addr_t)
2392 txds->Buffer_Pointer, sizeof(u64),
2393 PCI_DMA_TODEVICE);
2394 txds++;
2395 }
2396
2397 skb = (struct sk_buff *) ((unsigned long)
2398 txds->Host_Control);
2399 if (!skb) {
1ee6dd77 2400 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2401 return NULL;
2402 }
2403 pci_unmap_single(nic->pdev, (dma_addr_t)
2404 txds->Buffer_Pointer,
2405 skb->len - skb->data_len,
2406 PCI_DMA_TODEVICE);
2407 frg_cnt = skb_shinfo(skb)->nr_frags;
2408 if (frg_cnt) {
2409 txds++;
2410 for (j = 0; j < frg_cnt; j++, txds++) {
2411 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2412 if (!txds->Buffer_Pointer)
2413 break;
6aa20a22 2414 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2415 txds->Buffer_Pointer,
2416 frag->size, PCI_DMA_TODEVICE);
2417 }
2418 }
1ee6dd77 2419 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2420 return(skb);
2421}
1da177e4 2422
20346722 2423/**
2424 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2425 * @nic : device private variable.
20346722 2426 * Description:
1da177e4 2427 * Free all queued Tx buffers.
20346722 2428 * Return Value: void
1da177e4
LT		 2429*/
2430
2431static void free_tx_buffers(struct s2io_nic *nic)
2432{
2433 struct net_device *dev = nic->dev;
2434 struct sk_buff *skb;
1ee6dd77 2435 struct TxD *txdp;
1da177e4 2436 int i, j;
1ee6dd77 2437 struct mac_info *mac_control;
1da177e4 2438 struct config_param *config;
fed5eccd 2439 int cnt = 0;
1da177e4
LT		 2440
2441 mac_control = &nic->mac_control;
2442 config = &nic->config;
2443
2444 for (i = 0; i < config->tx_fifo_num; i++) {
2fda096d
SR		 2445 unsigned long flags;
2446 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
b35b3b49 2447 for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
491976b2
SH		 2448 txdp = (struct TxD *) \
2449 mac_control->fifos[i].list_info[j].list_virt_addr;
fed5eccd
AR		 2450 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2451 if (skb) {
8a4bdbaa 2452 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 2453 += skb->truesize;
fed5eccd
AR		 2454 dev_kfree_skb(skb);
2455 cnt++;
1da177e4 2456 }
1da177e4
LT		 2457 }
2458 DBG_PRINT(INTR_DBG,
2459 "%s:forcibly freeing %d skbs on FIFO%d\n",
2460 dev->name, cnt, i);
20346722 2461 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2462 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2fda096d 2463 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
1da177e4
LT		 2464 }
2465}
2466
20346722 2467/**
2468 * stop_nic - To stop the nic
1da177e4 2469 * @nic ; device private variable.
20346722 2470 * Description:
2471 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2472 * function does. This function is called to stop the device.
2473 * Return Value:
2474 * void.
2475 */
2476
2477static void stop_nic(struct s2io_nic *nic)
2478{
1ee6dd77 2479 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2480 register u64 val64 = 0;
5d3213cc 2481 u16 interruptible;
1ee6dd77 2482 struct mac_info *mac_control;
1da177e4
LT		 2483 struct config_param *config;
2484
2485 mac_control = &nic->mac_control;
2486 config = &nic->config;
2487
2488 /* Disable all interrupts */
9caab458 2489 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2490 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2491 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2492 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2493
5d3213cc
AR		 2494 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2495 val64 = readq(&bar0->adapter_control);
2496 val64 &= ~(ADAPTER_CNTL_EN);
2497 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2498}
2499
20346722 2500/**
2501 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2502 * @ring_info: per ring structure
20346722 2503 * Description:
1da177e4
LT		 2504 * The function allocates Rx side skbs and puts the physical
2505 * address of these buffers into the RxD buffer pointers, so that the NIC
2506 * can DMA the received frame into these locations.
2507 * The NIC supports 3 receive modes, viz
2508 * 1. single buffer,
2509 * 2. three buffer and
2510 * 3. Five buffer modes.
20346722 2511 * Each mode defines how many fragments the received frame will be split
2512 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2513 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2514 * is split into 3 fragments. As of now only single buffer mode is
2515 * supported.
2516 * Return Value:
2517 * SUCCESS on success or an appropriate -ve value on failure.
2518 */
2519
0425b46a 2520static int fill_rx_buffers(struct ring_info *ring)
1da177e4 2521{
1da177e4 2522 struct sk_buff *skb;
1ee6dd77 2523 struct RxD_t *rxdp;
0425b46a 2524 int off, size, block_no, block_no1;
1da177e4 2525 u32 alloc_tab = 0;
20346722 2526 u32 alloc_cnt;
20346722 2527 u64 tmp;
1ee6dd77 2528 struct buffAdd *ba;
1ee6dd77 2529 struct RxD_t *first_rxdp = NULL;
363dc367 2530 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2531 int rxd_index = 0;
6d517a27
VP		 2532 struct RxD1 *rxdp1;
2533 struct RxD3 *rxdp3;
0425b46a 2534 struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2535
0425b46a 2536 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2537
0425b46a 2538 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2539 while (alloc_tab < alloc_cnt) {
0425b46a 2540 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2541
0425b46a
SH		 2542 off = ring->rx_curr_put_info.offset;
2543
2544 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2545
2546 rxd_index = off + 1;
2547 if (block_no)
2548 rxd_index += (block_no * ring->rxd_count);
da6971d8 2549
0425b46a
SH		 2550 if ((block_no == block_no1) &&
2551 (off == ring->rx_curr_get_info.offset) &&
2552 (rxdp->Host_Control)) {
da6971d8 2553 DBG_PRINT(INTR_DBG, "%s: Get and Put",
0425b46a 2554 ring->dev->name);
1da177e4
LT		 2555 DBG_PRINT(INTR_DBG, " info equated\n");
2556 goto end;
2557 }
0425b46a
SH		 2558 if (off && (off == ring->rxd_count)) {
2559 ring->rx_curr_put_info.block_index++;
2560 if (ring->rx_curr_put_info.block_index ==
2561 ring->block_count)
2562 ring->rx_curr_put_info.block_index = 0;
2563 block_no = ring->rx_curr_put_info.block_index;
2564 off = 0;
2565 ring->rx_curr_put_info.offset = off;
2566 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2567 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2568 ring->dev->name, rxdp);
2569
1da177e4 2570 }
c9fcbf47 2571
da6971d8 2572 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
0425b46a 2573 ((ring->rxd_mode == RXD_MODE_3B) &&
b7b5a128 2574 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2575 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2576 goto end;
2577 }
da6971d8 2578 /* calculate size of skb based on ring mode */
0425b46a 2579 size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE +
da6971d8 2580 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2581 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2582 size += NET_IP_ALIGN;
da6971d8 2583 else
0425b46a 2584 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2585
da6971d8
AR		 2586 /* allocate skb */
2587 skb = dev_alloc_skb(size);
2588 if(!skb) {
0425b46a 2589 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
0c61ed5f 2590 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b 2591 if (first_rxdp) {
2592 wmb();
2593 first_rxdp->Control_1 |= RXD_OWN_XENA;
2594 }
0425b46a
SH		 2595 stats->mem_alloc_fail_cnt++;
2596
da6971d8
AR		 2597 return -ENOMEM ;
2598 }
0425b46a
SH		 2599 stats->mem_allocated += skb->truesize;
2600
2601 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2602 /* 1 buffer mode - normal operation mode */
6d517a27 2603 rxdp1 = (struct RxD1*)rxdp;
1ee6dd77 2604 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2605 skb_reserve(skb, NET_IP_ALIGN);
6d517a27 2606 rxdp1->Buffer0_ptr = pci_map_single
0425b46a 2607 (ring->pdev, skb->data, size - NET_IP_ALIGN,
863c11a9 2608 PCI_DMA_FROMDEVICE);
491abf25
VP		 2609 if( (rxdp1->Buffer0_ptr == 0) ||
2610 (rxdp1->Buffer0_ptr ==
2611 DMA_ERROR_CODE))
2612 goto pci_map_failed;
2613
8a4bdbaa 2614 rxdp->Control_2 =
491976b2 2615 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
0425b46a
SH		 2616 rxdp->Host_Control = (unsigned long) (skb);
2617 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2618 /*
6d517a27
VP		 2619 * 2 buffer mode -
2620 * 2 buffer mode provides 128
da6971d8 2621 * byte aligned receive buffers.
da6971d8
AR		 2622 */
2623
6d517a27 2624 rxdp3 = (struct RxD3*)rxdp;
491976b2 2625 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2626 Buffer0_ptr = rxdp3->Buffer0_ptr;
2627 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2628 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2629 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2630 rxdp3->Buffer0_ptr = Buffer0_ptr;
2631 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2632
0425b46a 2633 ba = &ring->ba[block_no][off];
da6971d8
AR		 2634 skb_reserve(skb, BUF0_LEN);
2635 tmp = (u64)(unsigned long) skb->data;
2636 tmp += ALIGN_SIZE;
2637 tmp &= ~ALIGN_SIZE;
2638 skb->data = (void *) (unsigned long)tmp;
27a884dc 2639 skb_reset_tail_pointer(skb);
da6971d8 2640
6d517a27
VP		 2641 if (!(rxdp3->Buffer0_ptr))
2642 rxdp3->Buffer0_ptr =
0425b46a
SH		 2643 pci_map_single(ring->pdev, ba->ba_0,
2644 BUF0_LEN, PCI_DMA_FROMDEVICE);
75c30b13 2645 else
0425b46a 2646 pci_dma_sync_single_for_device(ring->pdev,
6d517a27 2647 (dma_addr_t) rxdp3->Buffer0_ptr,
75c30b13 2648 BUF0_LEN, PCI_DMA_FROMDEVICE);
491abf25
VP		 2649 if( (rxdp3->Buffer0_ptr == 0) ||
2650 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2651 goto pci_map_failed;
2652
da6971d8 2653 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2654 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2655 /* Two buffer mode */
2656
2657 /*
6aa20a22 2658 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2659 * L4 payload
2660 */
6d517a27 2661 rxdp3->Buffer2_ptr = pci_map_single
0425b46a 2662 (ring->pdev, skb->data, ring->mtu + 4,
da6971d8
AR		 2663 PCI_DMA_FROMDEVICE);
2664
491abf25
VP		 2665 if( (rxdp3->Buffer2_ptr == 0) ||
2666 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2667 goto pci_map_failed;
2668
0425b46a
SH		 2669 if (!rxdp3->Buffer1_ptr)
2670 rxdp3->Buffer1_ptr =
2671 pci_map_single(ring->pdev,
75c30b13
AR		 2672 ba->ba_1, BUF1_LEN,
2673 PCI_DMA_FROMDEVICE);
0425b46a 2674
491abf25
VP		 2675 if( (rxdp3->Buffer1_ptr == 0) ||
2676 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2677 pci_unmap_single
0425b46a
SH		 2678 (ring->pdev,
2679 (dma_addr_t)(unsigned long)
2680 skb->data,
2681 ring->mtu + 4,
491abf25
VP		 2682 PCI_DMA_FROMDEVICE);
2683 goto pci_map_failed;
75c30b13 2684 }
da6971d8
AR		 2685 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2686 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
0425b46a 2687 (ring->mtu + 4);
da6971d8 2688 }
b7b5a128 2689 rxdp->Control_2 |= s2BIT(0);
0425b46a 2690 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2691 }
303bcb4b 2692 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2693 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2694 off++;
0425b46a 2695 if (off == (ring->rxd_count + 1))
da6971d8 2696 off = 0;
0425b46a 2697 ring->rx_curr_put_info.offset = off;
20346722 2698
da6971d8 2699 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b 2700 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2701 if (first_rxdp) {
2702 wmb();
2703 first_rxdp->Control_1 |= RXD_OWN_XENA;
2704 }
2705 first_rxdp = rxdp;
2706 }
0425b46a 2707 ring->rx_bufs_left += 1;
1da177e4
LT		 2708 alloc_tab++;
2709 }
2710
2711 end:
303bcb4b 2712 /* Transfer ownership of first descriptor to adapter just before
2713 * exiting. Before that, use memory barrier so that ownership
2714 * and other fields are seen by adapter correctly.
2715 */
2716 if (first_rxdp) {
2717 wmb();
2718 first_rxdp->Control_1 |= RXD_OWN_XENA;
2719 }
2720
1da177e4 2721 return SUCCESS;
491abf25
VP		 2722pci_map_failed:
2723 stats->pci_map_fail_cnt++;
2724 stats->mem_freed += skb->truesize;
2725 dev_kfree_skb_irq(skb);
2726 return -ENOMEM;
1da177e4
LT		 2727}
2728
da6971d8
AR		 2729static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2730{
2731 struct net_device *dev = sp->dev;
2732 int j;
2733 struct sk_buff *skb;
1ee6dd77
RB		 2734 struct RxD_t *rxdp;
2735 struct mac_info *mac_control;
2736 struct buffAdd *ba;
6d517a27
VP		 2737 struct RxD1 *rxdp1;
2738 struct RxD3 *rxdp3;
da6971d8
AR		 2739
2740 mac_control = &sp->mac_control;
2741 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2742 rxdp = mac_control->rings[ring_no].
2743 rx_blocks[blk].rxds[j].virt_addr;
2744 skb = (struct sk_buff *)
2745 ((unsigned long) rxdp->Host_Control);
2746 if (!skb) {
2747 continue;
2748 }
2749 if (sp->rxd_mode == RXD_MODE_1) {
6d517a27 2750 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2751 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2752 rxdp1->Buffer0_ptr,
2753 dev->mtu +
2754 HEADER_ETHERNET_II_802_3_SIZE
2755 + HEADER_802_2_SIZE +
2756 HEADER_SNAP_SIZE,
2757 PCI_DMA_FROMDEVICE);
1ee6dd77 2758 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2759 } else if(sp->rxd_mode == RXD_MODE_3B) {
6d517a27 2760 rxdp3 = (struct RxD3*)rxdp;
da6971d8
AR		 2761 ba = &mac_control->rings[ring_no].
2762 ba[blk][j];
2763 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2764 rxdp3->Buffer0_ptr,
2765 BUF0_LEN,
da6971d8
AR		 2766 PCI_DMA_FROMDEVICE);
2767 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2768 rxdp3->Buffer1_ptr,
2769 BUF1_LEN,
da6971d8
AR		 2770 PCI_DMA_FROMDEVICE);
2771 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2772 rxdp3->Buffer2_ptr,
2773 dev->mtu + 4,
da6971d8 2774 PCI_DMA_FROMDEVICE);
1ee6dd77 2775 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2776 }
491976b2 2777 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8 2778 dev_kfree_skb(skb);
0425b46a 2779 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2780 }
2781}
2782
1da177e4 2783/**
20346722 2784 * free_rx_buffers - Frees all Rx buffers
1da177e4 2785 * @sp: device private variable.
20346722 2786 * Description:
1da177e4
LT		 2787 * This function will free all Rx buffers allocated by host.
2788 * Return Value:
2789 * NONE.
2790 */
2791
2792static void free_rx_buffers(struct s2io_nic *sp)
2793{
2794 struct net_device *dev = sp->dev;
da6971d8 2795 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2796 struct mac_info *mac_control;
1da177e4 2797 struct config_param *config;
1da177e4
LT		 2798
2799 mac_control = &sp->mac_control;
2800 config = &sp->config;
2801
2802 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2803 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2804 free_rxd_blk(sp,i,blk);
1da177e4 2805
20346722 2806 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2807 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2808 mac_control->rings[i].rx_curr_put_info.offset = 0;
2809 mac_control->rings[i].rx_curr_get_info.offset = 0;
0425b46a 2810 mac_control->rings[i].rx_bufs_left = 0;
1da177e4
LT		 2811 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2812 dev->name, buf_cnt, i);
2813 }
2814}
2815
2816/**
2817 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2818 * @napi : pointer to the napi structure.
20346722 2819 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2820 * during one pass through the 'Poll" function.
2821 * Description:
2822 * Comes into picture only if NAPI support has been incorporated. It does
2823 * the same thing that rx_intr_handler does, but not in a interrupt context
2824 * also It will process only a given number of packets.
2825 * Return value:
2826 * 0 on success and 1 if there are No Rx packets to be processed.
2827 */
2828
bea3348e 2829static int s2io_poll(struct napi_struct *napi, int budget)
1da177e4 2830{
bea3348e
SH		 2831 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2832 struct net_device *dev = nic->dev;
20346722 2833 int pkt_cnt = 0, org_pkts_to_process;
1ee6dd77 2834 struct mac_info *mac_control;
1da177e4 2835 struct config_param *config;
1ee6dd77 2836 struct XENA_dev_config __iomem *bar0 = nic->bar0;
20346722 2837 int i;
1da177e4
LT		 2838
2839 mac_control = &nic->mac_control;
2840 config = &nic->config;
2841
bea3348e 2842 nic->pkts_to_process = budget;
20346722 2843 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2844
19a60522
SS		 2845 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2846 readl(&bar0->rx_traffic_int);
1da177e4
LT		 2847
2848 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2849 rx_intr_handler(&mac_control->rings[i]);
2850 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2851 if (!nic->pkts_to_process) {
2852 /* Quota for the current iteration has been met */
2853 goto no_rx;
1da177e4 2854 }
1da177e4 2855 }
1da177e4 2856
bea3348e 2857 netif_rx_complete(dev, napi);
1da177e4
LT		 2858
2859 for (i = 0; i < config->rx_ring_num; i++) {
0425b46a 2860 if (fill_rx_buffers(&mac_control->rings[i]) == -ENOMEM) {
0c61ed5f
RV		 2861 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2862 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2863 break;
2864 }
2865 }
2866 /* Re enable the Rx interrupts. */
c92ca04b 2867 writeq(0x0, &bar0->rx_traffic_mask);
19a60522 2868 readl(&bar0->rx_traffic_mask);
bea3348e 2869 return pkt_cnt;
1da177e4 2870
20346722 2871no_rx:
1da177e4 2872 for (i = 0; i < config->rx_ring_num; i++) {
0425b46a 2873 if (fill_rx_buffers(&mac_control->rings[i]) == -ENOMEM) {
0c61ed5f
RV		 2874 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2875 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2876 break;
2877 }
2878 }
bea3348e 2879 return pkt_cnt;
1da177e4 2880}
20346722 2881
b41477f3 2882#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2883/**
b41477f3 2884 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2885 * @dev : pointer to the device structure.
2886 * Description:
b41477f3
AR		 2887 * This function will be called by upper layer to check for events on the
2888 * interface in situations where interrupts are disabled. It is used for
2889 * specific in-kernel networking tasks, such as remote consoles and kernel
2890 * debugging over the network (example netdump in RedHat).
612eff0e 2891 */
612eff0e
BH		 2892static void s2io_netpoll(struct net_device *dev)
2893{
1ee6dd77
RB		 2894 struct s2io_nic *nic = dev->priv;
2895 struct mac_info *mac_control;
612eff0e 2896 struct config_param *config;
1ee6dd77 2897 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2898 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2899 int i;
2900
d796fdb7
LV		 2901 if (pci_channel_offline(nic->pdev))
2902 return;
2903
612eff0e
BH		 2904 disable_irq(dev->irq);
2905
612eff0e
BH		 2906 mac_control = &nic->mac_control;
2907 config = &nic->config;
2908
612eff0e 2909 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2910 writeq(val64, &bar0->tx_traffic_int);
2911
6aa20a22 2912 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2913 * run out of skbs and will fail and eventually netpoll application such
2914 * as netdump will fail.
2915 */
2916 for (i = 0; i < config->tx_fifo_num; i++)
2917 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2918
b41477f3 2919 /* check for received packet and indicate up to network */
612eff0e
BH		 2920 for (i = 0; i < config->rx_ring_num; i++)
2921 rx_intr_handler(&mac_control->rings[i]);
2922
2923 for (i = 0; i < config->rx_ring_num; i++) {
0425b46a 2924 if (fill_rx_buffers(&mac_control->rings[i]) == -ENOMEM) {
0c61ed5f
RV		 2925 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2926 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2927 break;
2928 }
2929 }
612eff0e
BH		 2930 enable_irq(dev->irq);
2931 return;
2932}
2933#endif
2934
20346722 2935/**
1da177e4
LT		 2936 * rx_intr_handler - Rx interrupt handler
2937 * @nic: device private variable.
20346722 2938 * Description:
2939 * If the interrupt is because of a received frame or if the
1da177e4 2940 * receive ring contains fresh as yet un-processed frames,this function is
20346722 2941 * called. It picks out the RxD at which place the last Rx processing had
2942 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2943 * the offset.
2944 * Return Value:
2945 * NONE.
2946 */
1ee6dd77 2947static void rx_intr_handler(struct ring_info *ring_data)
1da177e4 2948{
c9fcbf47 2949 int get_block, put_block;
1ee6dd77
RB		 2950 struct rx_curr_get_info get_info, put_info;
2951 struct RxD_t *rxdp;
1da177e4 2952 struct sk_buff *skb;
20346722 2953 int pkt_cnt = 0;
7d3d0439 2954 int i;
6d517a27
VP		 2955 struct RxD1* rxdp1;
2956 struct RxD3* rxdp3;
7d3d0439 2957
20346722 2958 get_info = ring_data->rx_curr_get_info;
2959 get_block = get_info.block_index;
1ee6dd77 2960 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2961 put_block = put_info.block_index;
da6971d8 2962 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2963
da6971d8 2964 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2965 /*
2966 * If your are next to put index then it's
2967 * FIFO full condition
2968 */
da6971d8
AR		 2969 if ((get_block == put_block) &&
2970 (get_info.offset + 1) == put_info.offset) {
0425b46a
SH		 2971 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2972 ring_data->dev->name);
da6971d8
AR		 2973 break;
2974 }
20346722 2975 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2976 if (skb == NULL) {
2977 DBG_PRINT(ERR_DBG, "%s: The skb is ",
0425b46a 2978 ring_data->dev->name);
20346722 2979 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2980 return;
1da177e4 2981 }
0425b46a 2982 if (ring_data->rxd_mode == RXD_MODE_1) {
6d517a27 2983 rxdp1 = (struct RxD1*)rxdp;
0425b46a 2984 pci_unmap_single(ring_data->pdev, (dma_addr_t)
6d517a27 2985 rxdp1->Buffer0_ptr,
0425b46a 2986 ring_data->mtu +
6d517a27
VP		 2987 HEADER_ETHERNET_II_802_3_SIZE +
2988 HEADER_802_2_SIZE +
2989 HEADER_SNAP_SIZE,
2990 PCI_DMA_FROMDEVICE);
0425b46a 2991 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
6d517a27 2992 rxdp3 = (struct RxD3*)rxdp;
0425b46a 2993 pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t)
6d517a27
VP		 2994 rxdp3->Buffer0_ptr,
2995 BUF0_LEN, PCI_DMA_FROMDEVICE);
0425b46a 2996 pci_unmap_single(ring_data->pdev, (dma_addr_t)
6d517a27 2997 rxdp3->Buffer2_ptr,
0425b46a 2998 ring_data->mtu + 4,
6d517a27 2999 PCI_DMA_FROMDEVICE);
da6971d8 3000 }
863c11a9 3001 prefetch(skb->data);
20346722 3002 rx_osm_handler(ring_data, rxdp);
3003 get_info.offset++;
da6971d8
AR		 3004 ring_data->rx_curr_get_info.offset = get_info.offset;
3005 rxdp = ring_data->rx_blocks[get_block].
3006 rxds[get_info.offset].virt_addr;
0425b46a 3007 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3008 get_info.offset = 0;
da6971d8 3009 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3010 get_block++;
da6971d8
AR		 3011 if (get_block == ring_data->block_count)
3012 get_block = 0;
3013 ring_data->rx_curr_get_info.block_index = get_block;
20346722 3014 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3015 }
1da177e4 3016
0425b46a
SH		 3017 if(ring_data->nic->config.napi){
3018 ring_data->nic->pkts_to_process -= 1;
3019 if (!ring_data->nic->pkts_to_process)
3020 break;
3021 }
20346722 3022 pkt_cnt++;
1da177e4
LT		 3023 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3024 break;
3025 }
0425b46a 3026 if (ring_data->lro) {
7d3d0439
RA		 3027 /* Clear all LRO sessions before exiting */
3028 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 3029 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3030 if (lro->in_use) {
0425b46a 3031 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3032 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3033 clear_lro_session(lro);
3034 }
3035 }
3036 }
1da177e4 3037}
20346722 3038
3039/**
1da177e4
LT		 3040 * tx_intr_handler - Transmit interrupt handler
3041 * @nic : device private variable
20346722 3042 * Description:
3043 * If an interrupt was raised to indicate DMA complete of the
3044 * Tx packet, this function is called. It identifies the last TxD
3045 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3046 * DMA'ed into the NICs internal memory.
3047 * Return Value:
3048 * NONE
3049 */
3050
1ee6dd77 3051static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3052{
1ee6dd77 3053 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3054 struct tx_curr_get_info get_info, put_info;
3a3d5756 3055 struct sk_buff *skb = NULL;
1ee6dd77 3056 struct TxD *txdlp;
3a3d5756 3057 int pkt_cnt = 0;
2fda096d 3058 unsigned long flags = 0;
f9046eb3 3059 u8 err_mask;
1da177e4 3060
2fda096d
SR		 3061 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3062 return;
3063
20346722 3064 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 3065 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3066 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722 3067 list_virt_addr;
3068 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3069 (get_info.offset != put_info.offset) &&
3070 (txdlp->Host_Control)) {
3071 /* Check for TxD errors */
3072 if (txdlp->Control_1 & TXD_T_CODE) {
3073 unsigned long long err;
3074 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 3075 if (err & 0x1) {
3076 nic->mac_control.stats_info->sw_stat.
3077 parity_err_cnt++;
3078 }
491976b2
SH		 3079
3080 /* update t_code statistics */
f9046eb3
OH		 3081 err_mask = err >> 48;
3082 switch(err_mask) {
491976b2
SH		 3083 case 2:
3084 nic->mac_control.stats_info->sw_stat.
3085 tx_buf_abort_cnt++;
3086 break;
3087
3088 case 3:
3089 nic->mac_control.stats_info->sw_stat.
3090 tx_desc_abort_cnt++;
3091 break;
3092
3093 case 7:
3094 nic->mac_control.stats_info->sw_stat.
3095 tx_parity_err_cnt++;
3096 break;
3097
3098 case 10:
3099 nic->mac_control.stats_info->sw_stat.
3100 tx_link_loss_cnt++;
3101 break;
3102
3103 case 15:
3104 nic->mac_control.stats_info->sw_stat.
3105 tx_list_proc_err_cnt++;
3106 break;
3107 }
20346722 3108 }
1da177e4 3109
fed5eccd 3110 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3111 if (skb == NULL) {
2fda096d 3112 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
20346722 3113 DBG_PRINT(ERR_DBG, "%s: Null skb ",
3114 __FUNCTION__);
3115 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3116 return;
3117 }
3a3d5756 3118 pkt_cnt++;
20346722 3119
20346722 3120 /* Updating the statistics block */
20346722 3121 nic->stats.tx_bytes += skb->len;
491976b2 3122 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722 3123 dev_kfree_skb_irq(skb);
3124
3125 get_info.offset++;
863c11a9
AR		 3126 if (get_info.offset == get_info.fifo_len + 1)
3127 get_info.offset = 0;
1ee6dd77 3128 txdlp = (struct TxD *) fifo_data->list_info
20346722 3129 [get_info.offset].list_virt_addr;
3130 fifo_data->tx_curr_get_info.offset =
3131 get_info.offset;
1da177e4
LT		 3132 }
3133
3a3d5756 3134 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3135
3136 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3137}
3138
bd1034f0
AR		 3139/**
3140 * s2io_mdio_write - Function to write in to MDIO registers
3141 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3142 * @addr : address value
3143 * @value : data value
3144 * @dev : pointer to net_device structure
3145 * Description:
3146 * This function is used to write values to the MDIO registers
3147 * NONE
3148 */
3149static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3150{
3151 u64 val64 = 0x0;
1ee6dd77
RB		 3152 struct s2io_nic *sp = dev->priv;
3153 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3154
3155 //address transaction
3156 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3157 | MDIO_MMD_DEV_ADDR(mmd_type)
3158 | MDIO_MMS_PRT_ADDR(0x0);
3159 writeq(val64, &bar0->mdio_control);
3160 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3161 writeq(val64, &bar0->mdio_control);
3162 udelay(100);
3163
3164 //Data transaction
3165 val64 = 0x0;
3166 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3167 | MDIO_MMD_DEV_ADDR(mmd_type)
3168 | MDIO_MMS_PRT_ADDR(0x0)
3169 | MDIO_MDIO_DATA(value)
3170 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3171 writeq(val64, &bar0->mdio_control);
3172 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3173 writeq(val64, &bar0->mdio_control);
3174 udelay(100);
3175
3176 val64 = 0x0;
3177 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3178 | MDIO_MMD_DEV_ADDR(mmd_type)
3179 | MDIO_MMS_PRT_ADDR(0x0)
3180 | MDIO_OP(MDIO_OP_READ_TRANS);
3181 writeq(val64, &bar0->mdio_control);
3182 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3183 writeq(val64, &bar0->mdio_control);
3184 udelay(100);
3185
3186}
3187
3188/**
3189 * s2io_mdio_read - Function to write in to MDIO registers
3190 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3191 * @addr : address value
3192 * @dev : pointer to net_device structure
3193 * Description:
3194 * This function is used to read values to the MDIO registers
3195 * NONE
3196 */
3197static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3198{
3199 u64 val64 = 0x0;
3200 u64 rval64 = 0x0;
1ee6dd77
RB		 3201 struct s2io_nic *sp = dev->priv;
3202 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3203
3204 /* address transaction */
3205 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3206 | MDIO_MMD_DEV_ADDR(mmd_type)
3207 | MDIO_MMS_PRT_ADDR(0x0);
3208 writeq(val64, &bar0->mdio_control);
3209 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3210 writeq(val64, &bar0->mdio_control);
3211 udelay(100);
3212
3213 /* Data transaction */
3214 val64 = 0x0;
3215 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3216 | MDIO_MMD_DEV_ADDR(mmd_type)
3217 | MDIO_MMS_PRT_ADDR(0x0)
3218 | MDIO_OP(MDIO_OP_READ_TRANS);
3219 writeq(val64, &bar0->mdio_control);
3220 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3221 writeq(val64, &bar0->mdio_control);
3222 udelay(100);
3223
3224 /* Read the value from regs */
3225 rval64 = readq(&bar0->mdio_control);
3226 rval64 = rval64 & 0xFFFF0000;
3227 rval64 = rval64 >> 16;
3228 return rval64;
3229}
3230/**
3231 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3232 * @counter : couter value to be updated
3233 * @flag : flag to indicate the status
3234 * @type : counter type
3235 * Description:
3236 * This function is to check the status of the xpak counters value
3237 * NONE
3238 */
3239
3240static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3241{
3242 u64 mask = 0x3;
3243 u64 val64;
3244 int i;
3245 for(i = 0; i <index; i++)
3246 mask = mask << 0x2;
3247
3248 if(flag > 0)
3249 {
3250 *counter = *counter + 1;
3251 val64 = *regs_stat & mask;
3252 val64 = val64 >> (index * 0x2);
3253 val64 = val64 + 1;
3254 if(val64 == 3)
3255 {
3256 switch(type)
3257 {
3258 case 1:
3259 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3260 "service. Excessive temperatures may "
3261 "result in premature transceiver "
3262 "failure \n");
3263 break;
3264 case 2:
3265 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3266 "service Excessive bias currents may "
3267 "indicate imminent laser diode "
3268 "failure \n");
3269 break;
3270 case 3:
3271 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3272 "service Excessive laser output "
3273 "power may saturate far-end "
3274 "receiver\n");
3275 break;
3276 default:
3277 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3278 "type \n");
3279 }
3280 val64 = 0x0;
3281 }
3282 val64 = val64 << (index * 0x2);
3283 *regs_stat = (*regs_stat & (~mask)) | (val64);
3284
3285 } else {
3286 *regs_stat = *regs_stat & (~mask);
3287 }
3288}
3289
3290/**
3291 * s2io_updt_xpak_counter - Function to update the xpak counters
3292 * @dev : pointer to net_device struct
3293 * Description:
3294 * This function is to upate the status of the xpak counters value
3295 * NONE
3296 */
3297static void s2io_updt_xpak_counter(struct net_device *dev)
3298{
3299 u16 flag = 0x0;
3300 u16 type = 0x0;
3301 u16 val16 = 0x0;
3302 u64 val64 = 0x0;
3303 u64 addr = 0x0;
3304
1ee6dd77
RB		 3305 struct s2io_nic *sp = dev->priv;
3306 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3307
3308 /* Check the communication with the MDIO slave */
3309 addr = 0x0000;
3310 val64 = 0x0;
3311 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3312 if((val64 == 0xFFFF) || (val64 == 0x0000))
3313 {
3314 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3315 "Returned %llx\n", (unsigned long long)val64);
3316 return;
3317 }
3318
3319 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3320 if(val64 != 0x2040)
3321 {
3322 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3323 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3324 (unsigned long long)val64);
3325 return;
3326 }
3327
3328 /* Loading the DOM register to MDIO register */
3329 addr = 0xA100;
3330 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3331 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3332
3333 /* Reading the Alarm flags */
3334 addr = 0xA070;
3335 val64 = 0x0;
3336 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3337
3338 flag = CHECKBIT(val64, 0x7);
3339 type = 1;
3340 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3341 &stat_info->xpak_stat.xpak_regs_stat,
3342 0x0, flag, type);
3343
3344 if(CHECKBIT(val64, 0x6))
3345 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3346
3347 flag = CHECKBIT(val64, 0x3);
3348 type = 2;
3349 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3350 &stat_info->xpak_stat.xpak_regs_stat,
3351 0x2, flag, type);
3352
3353 if(CHECKBIT(val64, 0x2))
3354 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3355
3356 flag = CHECKBIT(val64, 0x1);
3357 type = 3;
3358 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3359 &stat_info->xpak_stat.xpak_regs_stat,
3360 0x4, flag, type);
3361
3362 if(CHECKBIT(val64, 0x0))
3363 stat_info->xpak_stat.alarm_laser_output_power_low++;
3364
3365 /* Reading the Warning flags */
3366 addr = 0xA074;
3367 val64 = 0x0;
3368 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3369
3370 if(CHECKBIT(val64, 0x7))
3371 stat_info->xpak_stat.warn_transceiver_temp_high++;
3372
3373 if(CHECKBIT(val64, 0x6))
3374 stat_info->xpak_stat.warn_transceiver_temp_low++;
3375
3376 if(CHECKBIT(val64, 0x3))
3377 stat_info->xpak_stat.warn_laser_bias_current_high++;
3378
3379 if(CHECKBIT(val64, 0x2))
3380 stat_info->xpak_stat.warn_laser_bias_current_low++;
3381
3382 if(CHECKBIT(val64, 0x1))
3383 stat_info->xpak_stat.warn_laser_output_power_high++;
3384
3385 if(CHECKBIT(val64, 0x0))
3386 stat_info->xpak_stat.warn_laser_output_power_low++;
3387}
3388
20346722 3389/**
1da177e4 3390 * wait_for_cmd_complete - waits for a command to complete.
20346722 3391 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3392 * s2io_nic structure.
20346722 3393 * Description: Function that waits for a command to Write into RMAC
3394 * ADDR DATA registers to be completed and returns either success or
3395 * error depending on whether the command was complete or not.
1da177e4
LT		 3396 * Return value:
3397 * SUCCESS on success and FAILURE on failure.
3398 */
3399
9fc93a41
SS		 3400static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3401 int bit_state)
1da177e4 3402{
9fc93a41 3403 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3404 u64 val64;
3405
9fc93a41
SS		 3406 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3407 return FAILURE;
3408
3409 do {
c92ca04b 3410 val64 = readq(addr);
9fc93a41
SS		 3411 if (bit_state == S2IO_BIT_RESET) {
3412 if (!(val64 & busy_bit)) {
3413 ret = SUCCESS;
3414 break;
3415 }
3416 } else {
3417 if (!(val64 & busy_bit)) {
3418 ret = SUCCESS;
3419 break;
3420 }
1da177e4 3421 }
c92ca04b
AR		 3422
3423 if(in_interrupt())
9fc93a41 3424 mdelay(delay);
c92ca04b 3425 else
9fc93a41 3426 msleep(delay);
c92ca04b 3427
9fc93a41
SS		 3428 if (++cnt >= 10)
3429 delay = 50;
3430 } while (cnt < 20);
1da177e4
LT		 3431 return ret;
3432}
19a60522
SS		 3433/*
3434 * check_pci_device_id - Checks if the device id is supported
3435 * @id : device id
3436 * Description: Function to check if the pci device id is supported by driver.
3437 * Return value: Actual device id if supported else PCI_ANY_ID
3438 */
3439static u16 check_pci_device_id(u16 id)
3440{
3441 switch (id) {
3442 case PCI_DEVICE_ID_HERC_WIN:
3443 case PCI_DEVICE_ID_HERC_UNI:
3444 return XFRAME_II_DEVICE;
3445 case PCI_DEVICE_ID_S2IO_UNI:
3446 case PCI_DEVICE_ID_S2IO_WIN:
3447 return XFRAME_I_DEVICE;
3448 default:
3449 return PCI_ANY_ID;
3450 }
3451}
1da177e4 3452
20346722 3453/**
3454 * s2io_reset - Resets the card.
1da177e4
LT		 3455 * @sp : private member of the device structure.
3456 * Description: Function to Reset the card. This function then also
20346722 3457 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3458 * the card reset also resets the configuration space.
3459 * Return value:
3460 * void.
3461 */
3462
1ee6dd77 3463static void s2io_reset(struct s2io_nic * sp)
1da177e4 3464{
1ee6dd77 3465 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3466 u64 val64;
5e25b9dd 3467 u16 subid, pci_cmd;
19a60522
SS		 3468 int i;
3469 u16 val16;
491976b2
SH		 3470 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3471 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3472
19a60522
SS		 3473 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3474 __FUNCTION__, sp->dev->name);
1da177e4 3475
0b1f7ebe 3476 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3477 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3478
1da177e4
LT		 3479 val64 = SW_RESET_ALL;
3480 writeq(val64, &bar0->sw_reset);
c92ca04b
AR		 3481 if (strstr(sp->product_name, "CX4")) {
3482 msleep(750);
3483 }
19a60522
SS		 3484 msleep(250);
3485 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3486
19a60522
SS		 3487 /* Restore the PCI state saved during initialization. */
3488 pci_restore_state(sp->pdev);
3489 pci_read_config_word(sp->pdev, 0x2, &val16);
3490 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3491 break;
3492 msleep(200);
3493 }
1da177e4 3494
19a60522
SS		 3495 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3496 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3497 }
3498
3499 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3500
3501 s2io_init_pci(sp);
1da177e4 3502
20346722 3503 /* Set swapper to enable I/O register access */
3504 s2io_set_swapper(sp);
3505
faa4f796
SH		 3506 /* restore mac_addr entries */
3507 do_s2io_restore_unicast_mc(sp);
3508
cc6e7c44
RA		 3509 /* Restore the MSIX table entries from local variables */
3510 restore_xmsi_data(sp);
3511
5e25b9dd 3512 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3513 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3514 /* Clear "detected parity error" bit */
303bcb4b 3515 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3516
303bcb4b 3517 /* Clearing PCIX Ecc status register */
3518 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3519
303bcb4b 3520 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3521 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3522 }
5e25b9dd 3523
20346722 3524 /* Reset device statistics maintained by OS */
3525 memset(&sp->stats, 0, sizeof (struct net_device_stats));
8a4bdbaa 3526
491976b2
SH		 3527 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3528 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3529 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3530 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3531 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3532 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3533 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3534 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3535 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3536 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3537 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3538 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3539 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3540 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3541 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3542 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3543 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3544 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3545 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3546
1da177e4
LT		 3547 /* SXE-002: Configure link and activity LED to turn it off */
3548 subid = sp->pdev->subsystem_device;
541ae68f 3549 if (((subid & 0xFF) >= 0x07) &&
3550 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3551 val64 = readq(&bar0->gpio_control);
3552 val64 |= 0x0000800000000000ULL;
3553 writeq(val64, &bar0->gpio_control);
3554 val64 = 0x0411040400000000ULL;
509a2671 3555 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3556 }
3557
541ae68f 3558 /*
3559 * Clear spurious ECC interrupts that would have occured on
3560 * XFRAME II cards after reset.
3561 */
3562 if (sp->device_type == XFRAME_II_DEVICE) {
3563 val64 = readq(&bar0->pcc_err_reg);
3564 writeq(val64, &bar0->pcc_err_reg);
3565 }
3566
1da177e4
LT		 3567 sp->device_enabled_once = FALSE;
3568}
3569
3570/**
20346722 3571 * s2io_set_swapper - to set the swapper controle on the card
3572 * @sp : private member of the device structure,
1da177e4 3573 * pointer to the s2io_nic structure.
20346722 3574 * Description: Function to set the swapper control on the card
1da177e4
LT		 3575 * correctly depending on the 'endianness' of the system.
3576 * Return value:
3577 * SUCCESS on success and FAILURE on failure.
3578 */
3579
1ee6dd77 3580static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3581{
3582 struct net_device *dev = sp->dev;
1ee6dd77 3583 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3584 u64 val64, valt, valr;
3585
20346722 3586 /*
1da177e4
LT		 3587 * Set proper endian settings and verify the same by reading
3588 * the PIF Feed-back register.
3589 */
3590
3591 val64 = readq(&bar0->pif_rd_swapper_fb);
3592 if (val64 != 0x0123456789ABCDEFULL) {
3593 int i = 0;
3594 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3595 0x8100008181000081ULL, /* FE=1, SE=0 */
3596 0x4200004242000042ULL, /* FE=0, SE=1 */
3597 0}; /* FE=0, SE=0 */
3598
3599 while(i<4) {
3600 writeq(value[i], &bar0->swapper_ctrl);
3601 val64 = readq(&bar0->pif_rd_swapper_fb);
3602 if (val64 == 0x0123456789ABCDEFULL)
3603 break;
3604 i++;
3605 }
3606 if (i == 4) {
3607 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3608 dev->name);
3609 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3610 (unsigned long long) val64);
3611 return FAILURE;
3612 }
3613 valr = value[i];
3614 } else {
3615 valr = readq(&bar0->swapper_ctrl);
3616 }
3617
3618 valt = 0x0123456789ABCDEFULL;
3619 writeq(valt, &bar0->xmsi_address);
3620 val64 = readq(&bar0->xmsi_address);
3621
3622 if(val64 != valt) {
3623 int i = 0;
3624 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3625 0x0081810000818100ULL, /* FE=1, SE=0 */
3626 0x0042420000424200ULL, /* FE=0, SE=1 */
3627 0}; /* FE=0, SE=0 */
3628
3629 while(i<4) {
3630 writeq((value[i] | valr), &bar0->swapper_ctrl);
3631 writeq(valt, &bar0->xmsi_address);
3632 val64 = readq(&bar0->xmsi_address);
3633 if(val64 == valt)
3634 break;
3635 i++;
3636 }
3637 if(i == 4) {
20346722 3638 unsigned long long x = val64;
1da177e4 3639 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3640 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3641 return FAILURE;
3642 }
3643 }
3644 val64 = readq(&bar0->swapper_ctrl);
3645 val64 &= 0xFFFF000000000000ULL;
3646
3647#ifdef __BIG_ENDIAN
20346722 3648 /*
3649 * The device by default set to a big endian format, so a
1da177e4
LT		 3650 * big endian driver need not set anything.
3651 */
3652 val64 |= (SWAPPER_CTRL_TXP_FE |
3653 SWAPPER_CTRL_TXP_SE |
3654 SWAPPER_CTRL_TXD_R_FE |
3655 SWAPPER_CTRL_TXD_W_FE |
3656 SWAPPER_CTRL_TXF_R_FE |
3657 SWAPPER_CTRL_RXD_R_FE |
3658 SWAPPER_CTRL_RXD_W_FE |
3659 SWAPPER_CTRL_RXF_W_FE |
3660 SWAPPER_CTRL_XMSI_FE |
1da177e4 3661 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3662 if (sp->config.intr_type == INTA)
cc6e7c44 3663 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3664 writeq(val64, &bar0->swapper_ctrl);
3665#else
20346722 3666 /*
1da177e4 3667 * Initially we enable all bits to make it accessible by the
20346722 3668 * driver, then we selectively enable only those bits that
1da177e4
LT		 3669 * we want to set.
3670 */
3671 val64 |= (SWAPPER_CTRL_TXP_FE |
3672 SWAPPER_CTRL_TXP_SE |
3673 SWAPPER_CTRL_TXD_R_FE |
3674 SWAPPER_CTRL_TXD_R_SE |
3675 SWAPPER_CTRL_TXD_W_FE |
3676 SWAPPER_CTRL_TXD_W_SE |
3677 SWAPPER_CTRL_TXF_R_FE |
3678 SWAPPER_CTRL_RXD_R_FE |
3679 SWAPPER_CTRL_RXD_R_SE |
3680 SWAPPER_CTRL_RXD_W_FE |
3681 SWAPPER_CTRL_RXD_W_SE |
3682 SWAPPER_CTRL_RXF_W_FE |
3683 SWAPPER_CTRL_XMSI_FE |
1da177e4 3684 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3685 if (sp->config.intr_type == INTA)
cc6e7c44 3686 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3687 writeq(val64, &bar0->swapper_ctrl);
3688#endif
3689 val64 = readq(&bar0->swapper_ctrl);
3690
20346722 3691 /*
3692 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3693 * feedback register.
3694 */
3695 val64 = readq(&bar0->pif_rd_swapper_fb);
3696 if (val64 != 0x0123456789ABCDEFULL) {
3697 /* Endian settings are incorrect, calls for another dekko. */
3698 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3699 dev->name);
3700 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3701 (unsigned long long) val64);
3702 return FAILURE;
3703 }
3704
3705 return SUCCESS;
3706}
3707
1ee6dd77 3708static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3709{
1ee6dd77 3710 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3711 u64 val64;
3712 int ret = 0, cnt = 0;
3713
3714 do {
3715 val64 = readq(&bar0->xmsi_access);
b7b5a128 3716 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3717 break;
3718 mdelay(1);
3719 cnt++;
3720 } while(cnt < 5);
3721 if (cnt == 5) {
3722 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3723 ret = 1;
3724 }
3725
3726 return ret;
3727}
3728
1ee6dd77 3729static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3730{
1ee6dd77 3731 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3732 u64 val64;
3733 int i;
3734
75c30b13 3735 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3736 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3737 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
b7b5a128 3738 val64 = (s2BIT(7) | s2BIT(15) | vBIT(i, 26, 6));
cc6e7c44
RA		 3739 writeq(val64, &bar0->xmsi_access);
3740 if (wait_for_msix_trans(nic, i)) {
3741 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3742 continue;
3743 }
3744 }
3745}
3746
1ee6dd77 3747static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3748{
1ee6dd77 3749 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3750 u64 val64, addr, data;
3751 int i;
3752
3753 /* Store and display */
75c30b13 3754 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
b7b5a128 3755 val64 = (s2BIT(15) | vBIT(i, 26, 6));
cc6e7c44
RA		 3756 writeq(val64, &bar0->xmsi_access);
3757 if (wait_for_msix_trans(nic, i)) {
3758 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3759 continue;
3760 }
3761 addr = readq(&bar0->xmsi_address);
3762 data = readq(&bar0->xmsi_data);
3763 if (addr && data) {
3764 nic->msix_info[i].addr = addr;
3765 nic->msix_info[i].data = data;
3766 }
3767 }
3768}
3769
1ee6dd77 3770static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3771{
1ee6dd77 3772 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3773 u64 tx_mat, rx_mat;
3774 u16 msi_control; /* Temp variable */
3775 int ret, i, j, msix_indx = 1;
3776
bd684e43 3777 nic->entries = kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct msix_entry),
cc6e7c44 3778 GFP_KERNEL);
bd684e43 3779 if (!nic->entries) {
491976b2
SH		 3780 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3781 __FUNCTION__);
c53d4945 3782 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3783 return -ENOMEM;
3784 }
8a4bdbaa 3785 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 3786 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3787
3788 nic->s2io_entries =
bd684e43 3789 kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct s2io_msix_entry),
cc6e7c44 3790 GFP_KERNEL);
bd684e43 3791 if (!nic->s2io_entries) {
8a4bdbaa 3792 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
491976b2 3793 __FUNCTION__);
c53d4945 3794 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3795 kfree(nic->entries);
8a4bdbaa 3796 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3797 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3798 return -ENOMEM;
3799 }
8a4bdbaa 3800 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 3801 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3802
3803 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3804 nic->entries[i].entry = i;
3805 nic->s2io_entries[i].entry = i;
3806 nic->s2io_entries[i].arg = NULL;
3807 nic->s2io_entries[i].in_use = 0;
3808 }
3809
3810 tx_mat = readq(&bar0->tx_mat0_n[0]);
3811 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3812 tx_mat |= TX_MAT_SET(i, msix_indx);
3813 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3814 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3815 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3816 }
3817 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3818
8a4bdbaa
SS		 3819 rx_mat = readq(&bar0->rx_mat);
3820 for (j = 0; j < nic->config.rx_ring_num; j++, msix_indx++) {
3821 rx_mat |= RX_MAT_SET(j, msix_indx);
3822 nic->s2io_entries[msix_indx].arg
3823 = &nic->mac_control.rings[j];
3824 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3825 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
cc6e7c44 3826 }
8a4bdbaa 3827 writeq(rx_mat, &bar0->rx_mat);
cc6e7c44 3828
c92ca04b 3829 nic->avail_msix_vectors = 0;
cc6e7c44 3830 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3831 /* We fail init if error or we get less vectors than min required */
3832 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3833 nic->avail_msix_vectors = ret;
3834 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3835 }
cc6e7c44
RA		 3836 if (ret) {
3837 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3838 kfree(nic->entries);
8a4bdbaa 3839 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3840 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44 3841 kfree(nic->s2io_entries);
8a4bdbaa 3842 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3843 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3844 nic->entries = NULL;
3845 nic->s2io_entries = NULL;
c92ca04b 3846 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3847 return -ENOMEM;
3848 }
c92ca04b
AR		 3849 if (!nic->avail_msix_vectors)
3850 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3851
3852 /*
3853 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3854 * in the herc NIC. (Temp change, needs to be removed later)
3855 */
3856 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3857 msi_control |= 0x1; /* Enable MSI */
3858 pci_write_config_word(nic->pdev, 0x42, msi_control);
3859
3860 return 0;
3861}
3862
8abc4d5b 3863/* Handle software interrupt used during MSI(X) test */
33390a70 3864static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3865{
3866 struct s2io_nic *sp = dev_id;
3867
3868 sp->msi_detected = 1;
3869 wake_up(&sp->msi_wait);
3870
3871 return IRQ_HANDLED;
3872}
3873
3874/* Test interrupt path by forcing a a software IRQ */
33390a70 3875static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3876{
3877 struct pci_dev *pdev = sp->pdev;
3878 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3879 int err;
3880 u64 val64, saved64;
3881
3882 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3883 sp->name, sp);
3884 if (err) {
3885 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3886 sp->dev->name, pci_name(pdev), pdev->irq);
3887 return err;
3888 }
3889
3890 init_waitqueue_head (&sp->msi_wait);
3891 sp->msi_detected = 0;
3892
3893 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3894 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3895 val64 |= SCHED_INT_CTRL_TIMER_EN;
3896 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3897 writeq(val64, &bar0->scheduled_int_ctrl);
3898
3899 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3900
3901 if (!sp->msi_detected) {
3902 /* MSI(X) test failed, go back to INTx mode */
2450022a 3903 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
8abc4d5b
SS		 3904 "using MSI(X) during test\n", sp->dev->name,
3905 pci_name(pdev));
3906
3907 err = -EOPNOTSUPP;
3908 }
3909
3910 free_irq(sp->entries[1].vector, sp);
3911
3912 writeq(saved64, &bar0->scheduled_int_ctrl);
3913
3914 return err;
3915}
18b2b7bd
SH		 3916
3917static void remove_msix_isr(struct s2io_nic *sp)
3918{
3919 int i;
3920 u16 msi_control;
3921
3922 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3923 if (sp->s2io_entries[i].in_use ==
3924 MSIX_REGISTERED_SUCCESS) {
3925 int vector = sp->entries[i].vector;
3926 void *arg = sp->s2io_entries[i].arg;
3927 free_irq(vector, arg);
3928 }
3929 }
3930
3931 kfree(sp->entries);
3932 kfree(sp->s2io_entries);
3933 sp->entries = NULL;
3934 sp->s2io_entries = NULL;
3935
3936 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3937 msi_control &= 0xFFFE; /* Disable MSI */
3938 pci_write_config_word(sp->pdev, 0x42, msi_control);
3939
3940 pci_disable_msix(sp->pdev);
3941}
3942
3943static void remove_inta_isr(struct s2io_nic *sp)
3944{
3945 struct net_device *dev = sp->dev;
3946
3947 free_irq(sp->pdev->irq, dev);
3948}
3949
1da177e4
LT		 3950/* ********************************************************* *
3951 * Functions defined below concern the OS part of the driver *
3952 * ********************************************************* */
3953
20346722 3954/**
1da177e4
LT		 3955 * s2io_open - open entry point of the driver
3956 * @dev : pointer to the device structure.
3957 * Description:
3958 * This function is the open entry point of the driver. It mainly calls a
3959 * function to allocate Rx buffers and inserts them into the buffer
20346722 3960 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3961 * Return value:
3962 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3963 * file on failure.
3964 */
3965
ac1f60db 3966static int s2io_open(struct net_device *dev)
1da177e4 3967{
1ee6dd77 3968 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3969 int err = 0;
3970
20346722 3971 /*
3972 * Make sure you have link off by default every time
1da177e4
LT		 3973 * Nic is initialized
3974 */
3975 netif_carrier_off(dev);
0b1f7ebe 3976 sp->last_link_state = 0;
1da177e4 3977
eaae7f72 3978 if (sp->config.intr_type == MSI_X) {
8abc4d5b
SS		 3979 int ret = s2io_enable_msi_x(sp);
3980
3981 if (!ret) {
8abc4d5b 3982 ret = s2io_test_msi(sp);
8abc4d5b 3983 /* rollback MSI-X, will re-enable during add_isr() */
18b2b7bd 3984 remove_msix_isr(sp);
8abc4d5b
SS		 3985 }
3986 if (ret) {
3987
3988 DBG_PRINT(ERR_DBG,
3989 "%s: MSI-X requested but failed to enable\n",
3990 dev->name);
eaae7f72 3991 sp->config.intr_type = INTA;
8abc4d5b
SS		 3992 }
3993 }
3994
c77dd43e 3995 /* NAPI doesn't work well with MSI(X) */
eaae7f72 3996 if (sp->config.intr_type != INTA) {
c77dd43e
SS		 3997 if(sp->config.napi)
3998 sp->config.napi = 0;
3999 }
4000
1da177e4 4001 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 4002 err = s2io_card_up(sp);
4003 if (err) {
1da177e4
LT		 4004 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4005 dev->name);
e6a8fee2 4006 goto hw_init_failed;
1da177e4
LT		 4007 }
4008
2fd37688 4009 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 4010 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4011 s2io_card_down(sp);
20346722 4012 err = -ENODEV;
e6a8fee2 4013 goto hw_init_failed;
1da177e4 4014 }
3a3d5756 4015 s2io_start_all_tx_queue(sp);
1da177e4 4016 return 0;
20346722 4017
20346722 4018hw_init_failed:
eaae7f72 4019 if (sp->config.intr_type == MSI_X) {
491976b2 4020 if (sp->entries) {
cc6e7c44 4021 kfree(sp->entries);
8a4bdbaa 4022 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2
SH		 4023 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
4024 }
4025 if (sp->s2io_entries) {
cc6e7c44 4026 kfree(sp->s2io_entries);
8a4bdbaa 4027 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2
SH		 4028 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
4029 }
cc6e7c44 4030 }
20346722 4031 return err;
1da177e4
LT		 4032}
4033
4034/**
4035 * s2io_close -close entry point of the driver
4036 * @dev : device pointer.
4037 * Description:
4038 * This is the stop entry point of the driver. It needs to undo exactly
4039 * whatever was done by the open entry point,thus it's usually referred to
4040 * as the close function.Among other things this function mainly stops the
4041 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4042 * Return value:
4043 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4044 * file on failure.
4045 */
4046
ac1f60db 4047static int s2io_close(struct net_device *dev)
1da177e4 4048{
1ee6dd77 4049 struct s2io_nic *sp = dev->priv;
faa4f796
SH		 4050 struct config_param *config = &sp->config;
4051 u64 tmp64;
4052 int offset;
cc6e7c44 4053
9f74ffde
SH		 4054 /* Return if the device is already closed *
4055 * Can happen when s2io_card_up failed in change_mtu *
4056 */
4057 if (!is_s2io_card_up(sp))
4058 return 0;
4059
3a3d5756 4060 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4061 /* delete all populated mac entries */
4062 for (offset = 1; offset < config->max_mc_addr; offset++) {
4063 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4064 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4065 do_s2io_delete_unicast_mc(sp, tmp64);
4066 }
4067
e6a8fee2 4068 s2io_card_down(sp);
cc6e7c44 4069
1da177e4
LT		 4070 return 0;
4071}
4072
4073/**
4074 * s2io_xmit - Tx entry point of te driver
4075 * @skb : the socket buffer containing the Tx data.
4076 * @dev : device pointer.
4077 * Description :
4078 * This function is the Tx entry point of the driver. S2IO NIC supports
4079 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4080 * NOTE: when device cant queue the pkt,just the trans_start variable will
4081 * not be upadted.
4082 * Return value:
4083 * 0 on success & 1 on failure.
4084 */
4085
ac1f60db 4086static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4087{
1ee6dd77 4088 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4089 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4090 register u64 val64;
1ee6dd77
RB		 4091 struct TxD *txdp;
4092 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4093 unsigned long flags = 0;
be3a6b02 4094 u16 vlan_tag = 0;
2fda096d 4095 struct fifo_info *fifo = NULL;
1ee6dd77 4096 struct mac_info *mac_control;
1da177e4 4097 struct config_param *config;
6cfc482b 4098 int do_spin_lock = 1;
75c30b13 4099 int offload_type;
6cfc482b 4100 int enable_per_list_interrupt = 0;
491abf25 4101 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 4102
4103 mac_control = &sp->mac_control;
4104 config = &sp->config;
4105
20346722 4106 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4107
4108 if (unlikely(skb->len <= 0)) {
4109 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4110 dev_kfree_skb_any(skb);
4111 return 0;
2fda096d 4112 }
491976b2 4113
92b84437 4114 if (!is_s2io_card_up(sp)) {
20346722 4115 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4116 dev->name);
20346722 4117 dev_kfree_skb(skb);
4118 return 0;
1da177e4
LT		 4119 }
4120
4121 queue = 0;
3a3d5756 4122 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4123 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4124 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4125 if (skb->protocol == htons(ETH_P_IP)) {
4126 struct iphdr *ip;
4127 struct tcphdr *th;
4128 ip = ip_hdr(skb);
4129
4130 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4131 th = (struct tcphdr *)(((unsigned char *)ip) +
4132 ip->ihl*4);
4133
4134 if (ip->protocol == IPPROTO_TCP) {
4135 queue_len = sp->total_tcp_fifos;
4136 queue = (ntohs(th->source) +
4137 ntohs(th->dest)) &
4138 sp->fifo_selector[queue_len - 1];
4139 if (queue >= queue_len)
4140 queue = queue_len - 1;
4141 } else if (ip->protocol == IPPROTO_UDP) {
4142 queue_len = sp->total_udp_fifos;
4143 queue = (ntohs(th->source) +
4144 ntohs(th->dest)) &
4145 sp->fifo_selector[queue_len - 1];
4146 if (queue >= queue_len)
4147 queue = queue_len - 1;
4148 queue += sp->udp_fifo_idx;
4149 if (skb->len > 1024)
4150 enable_per_list_interrupt = 1;
4151 do_spin_lock = 0;
4152 }
4153 }
4154 }
4155 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4156 /* get fifo number based on skb->priority value */
4157 queue = config->fifo_mapping
4158 [skb->priority & (MAX_TX_FIFOS - 1)];
4159 fifo = &mac_control->fifos[queue];
3a3d5756 4160
6cfc482b
SH		 4161 if (do_spin_lock)
4162 spin_lock_irqsave(&fifo->tx_lock, flags);
4163 else {
4164 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4165 return NETDEV_TX_LOCKED;
4166 }
be3a6b02 4167
3a3d5756
SH		 4168#ifdef CONFIG_NETDEVICES_MULTIQUEUE
4169 if (sp->config.multiq) {
4170 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4171 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4172 return NETDEV_TX_BUSY;
4173 }
4174 } else
4175#endif
4176 if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4177 if (netif_queue_stopped(dev)) {
4178 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4179 return NETDEV_TX_BUSY;
4180 }
4181 }
4182
2fda096d
SR		 4183 put_off = (u16) fifo->tx_curr_put_info.offset;
4184 get_off = (u16) fifo->tx_curr_get_info.offset;
4185 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
20346722 4186
2fda096d 4187 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4188 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 4189 if (txdp->Host_Control ||
4190 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4191 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4192 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4193 dev_kfree_skb(skb);
2fda096d 4194 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 4195 return 0;
4196 }
0b1f7ebe 4197
75c30b13 4198 offload_type = s2io_offload_type(skb);
75c30b13 4199 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4200 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4201 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4202 }
84fa7933 4203 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 4204 txdp->Control_2 |=
4205 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4206 TXD_TX_CKO_UDP_EN);
4207 }
fed5eccd
AR		 4208 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4209 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4210 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4211 if (enable_per_list_interrupt)
4212 if (put_off & (queue_len >> 5))
4213 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4214 if (vlan_tag) {
be3a6b02 4215 txdp->Control_2 |= TXD_VLAN_ENABLE;
4216 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4217 }
4218
fed5eccd 4219 frg_len = skb->len - skb->data_len;
75c30b13 4220 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4221 int ufo_size;
4222
75c30b13 4223 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4224 ufo_size &= ~7;
4225 txdp->Control_1 |= TXD_UFO_EN;
4226 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4227 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4228#ifdef __BIG_ENDIAN
3459feb8 4229 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4230 fifo->ufo_in_band_v[put_off] =
3459feb8 4231 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4232#else
2fda096d 4233 fifo->ufo_in_band_v[put_off] =
3459feb8 4234 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4235#endif
2fda096d 4236 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4237 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
2fda096d 4238 fifo->ufo_in_band_v,
fed5eccd 4239 sizeof(u64), PCI_DMA_TODEVICE);
491abf25
VP		 4240 if((txdp->Buffer_Pointer == 0) ||
4241 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4242 goto pci_map_failed;
fed5eccd 4243 txdp++;
fed5eccd 4244 }
1da177e4 4245
fed5eccd
AR		 4246 txdp->Buffer_Pointer = pci_map_single
4247 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
491abf25
VP		 4248 if((txdp->Buffer_Pointer == 0) ||
4249 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4250 goto pci_map_failed;
4251
fed5eccd
AR		 4252 txdp->Host_Control = (unsigned long) skb;
4253 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4254 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4255 txdp->Control_1 |= TXD_UFO_EN;
4256
4257 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4258 /* For fragmented SKB. */
4259 for (i = 0; i < frg_cnt; i++) {
4260 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe 4261 /* A '0' length fragment will be ignored */
4262 if (!frag->size)
4263 continue;
1da177e4
LT		 4264 txdp++;
4265 txdp->Buffer_Pointer = (u64) pci_map_page
4266 (sp->pdev, frag->page, frag->page_offset,
4267 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4268 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4269 if (offload_type == SKB_GSO_UDP)
fed5eccd 4270 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4271 }
4272 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4273
75c30b13 4274 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4275 frg_cnt++; /* as Txd0 was used for inband header */
4276
1da177e4 4277 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4278 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4279 writeq(val64, &tx_fifo->TxDL_Pointer);
4280
4281 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4282 TX_FIFO_LAST_LIST);
75c30b13 4283 if (offload_type)
fed5eccd 4284 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4285
1da177e4
LT		 4286 writeq(val64, &tx_fifo->List_Control);
4287
303bcb4b 4288 mmiowb();
4289
1da177e4 4290 put_off++;
2fda096d 4291 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4292 put_off = 0;
2fda096d 4293 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4294
4295 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4296 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4297 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4298 DBG_PRINT(TX_DBG,
4299 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4300 put_off, get_off);
3a3d5756 4301 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4302 }
491976b2 4303 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
1da177e4 4304 dev->trans_start = jiffies;
2fda096d 4305 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4306
f6f4bfa3
SH		 4307 if (sp->config.intr_type == MSI_X)
4308 tx_intr_handler(fifo);
4309
491abf25
VP		 4310 return 0;
4311pci_map_failed:
4312 stats->pci_map_fail_cnt++;
3a3d5756 4313 s2io_stop_tx_queue(sp, fifo->fifo_no);
491abf25
VP		 4314 stats->mem_freed += skb->truesize;
4315 dev_kfree_skb(skb);
2fda096d 4316 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 4317 return 0;
4318}
4319
25fff88e 4320static void
4321s2io_alarm_handle(unsigned long data)
4322{
1ee6dd77 4323 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4324 struct net_device *dev = sp->dev;
25fff88e 4325
8116f3cf 4326 s2io_handle_errors(dev);
25fff88e 4327 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4328}
4329
0425b46a 4330static int s2io_chk_rx_buffers(struct ring_info *ring)
75c30b13 4331{
0425b46a
SH		 4332 if (fill_rx_buffers(ring) == -ENOMEM) {
4333 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
99993af6 4334 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
75c30b13
AR		 4335 }
4336 return 0;
4337}
4338
7d12e780 4339static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4340{
1ee6dd77
RB		 4341 struct ring_info *ring = (struct ring_info *)dev_id;
4342 struct s2io_nic *sp = ring->nic;
cc6e7c44 4343
596c5c97 4344 if (!is_s2io_card_up(sp))
92b84437 4345 return IRQ_HANDLED;
92b84437 4346
75c30b13 4347 rx_intr_handler(ring);
0425b46a 4348 s2io_chk_rx_buffers(ring);
7d3d0439 4349
cc6e7c44
RA		 4350 return IRQ_HANDLED;
4351}
4352
7d12e780 4353static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4354{
1ee6dd77
RB		 4355 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4356 struct s2io_nic *sp = fifo->nic;
cc6e7c44 4357
596c5c97 4358 if (!is_s2io_card_up(sp))
92b84437 4359 return IRQ_HANDLED;
92b84437 4360
cc6e7c44 4361 tx_intr_handler(fifo);
cc6e7c44
RA		 4362 return IRQ_HANDLED;
4363}
1ee6dd77 4364static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4365{
1ee6dd77 4366 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d 4367 u64 val64;
4368
4369 val64 = readq(&bar0->pic_int_status);
4370 if (val64 & PIC_INT_GPIO) {
4371 val64 = readq(&bar0->gpio_int_reg);
4372 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4373 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4374 /*
4375 * This is unstable state so clear both up/down
4376 * interrupt and adapter to re-evaluate the link state.
4377 */
a371a07d 4378 val64 |= GPIO_INT_REG_LINK_DOWN;
4379 val64 |= GPIO_INT_REG_LINK_UP;
4380 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4381 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4382 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4383 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4384 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4385 }
c92ca04b
AR		 4386 else if (val64 & GPIO_INT_REG_LINK_UP) {
4387 val64 = readq(&bar0->adapter_status);
c92ca04b 4388 /* Enable Adapter */
19a60522
SS		 4389 val64 = readq(&bar0->adapter_control);
4390 val64 |= ADAPTER_CNTL_EN;
4391 writeq(val64, &bar0->adapter_control);
4392 val64 |= ADAPTER_LED_ON;
4393 writeq(val64, &bar0->adapter_control);
4394 if (!sp->device_enabled_once)
4395 sp->device_enabled_once = 1;
c92ca04b 4396
19a60522
SS		 4397 s2io_link(sp, LINK_UP);
4398 /*
4399 * unmask link down interrupt and mask link-up
4400 * intr
4401 */
4402 val64 = readq(&bar0->gpio_int_mask);
4403 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4404 val64 |= GPIO_INT_MASK_LINK_UP;
4405 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4406
c92ca04b
AR		 4407 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4408 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4409 s2io_link(sp, LINK_DOWN);
4410 /* Link is down so unmaks link up interrupt */
4411 val64 = readq(&bar0->gpio_int_mask);
4412 val64 &= ~GPIO_INT_MASK_LINK_UP;
4413 val64 |= GPIO_INT_MASK_LINK_DOWN;
4414 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4415
4416 /* turn off LED */
4417 val64 = readq(&bar0->adapter_control);
4418 val64 = val64 &(~ADAPTER_LED_ON);
4419 writeq(val64, &bar0->adapter_control);
a371a07d 4420 }
4421 }
c92ca04b 4422 val64 = readq(&bar0->gpio_int_mask);
a371a07d 4423}
4424
8116f3cf
SS		 4425/**
4426 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4427 * @value: alarm bits
4428 * @addr: address value
4429 * @cnt: counter variable
4430 * Description: Check for alarm and increment the counter
4431 * Return Value:
4432 * 1 - if alarm bit set
4433 * 0 - if alarm bit is not set
4434 */
43b7c451 4435static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
8116f3cf
SS		 4436 unsigned long long *cnt)
4437{
4438 u64 val64;
4439 val64 = readq(addr);
4440 if ( val64 & value ) {
4441 writeq(val64, addr);
4442 (*cnt)++;
4443 return 1;
4444 }
4445 return 0;
4446
4447}
4448
4449/**
4450 * s2io_handle_errors - Xframe error indication handler
4451 * @nic: device private variable
4452 * Description: Handle alarms such as loss of link, single or
4453 * double ECC errors, critical and serious errors.
4454 * Return Value:
4455 * NONE
4456 */
4457static void s2io_handle_errors(void * dev_id)
4458{
4459 struct net_device *dev = (struct net_device *) dev_id;
4460 struct s2io_nic *sp = dev->priv;
4461 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4462 u64 temp64 = 0,val64=0;
4463 int i = 0;
4464
4465 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4466 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4467
92b84437 4468 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4469 return;
4470
4471 if (pci_channel_offline(sp->pdev))
4472 return;
4473
4474 memset(&sw_stat->ring_full_cnt, 0,
4475 sizeof(sw_stat->ring_full_cnt));
4476
4477 /* Handling the XPAK counters update */
4478 if(stats->xpak_timer_count < 72000) {
4479 /* waiting for an hour */
4480 stats->xpak_timer_count++;
4481 } else {
4482 s2io_updt_xpak_counter(dev);
4483 /* reset the count to zero */
4484 stats->xpak_timer_count = 0;
4485 }
4486
4487 /* Handling link status change error Intr */
4488 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4489 val64 = readq(&bar0->mac_rmac_err_reg);
4490 writeq(val64, &bar0->mac_rmac_err_reg);
4491 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4492 schedule_work(&sp->set_link_task);
4493 }
4494
4495 /* In case of a serious error, the device will be Reset. */
4496 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4497 &sw_stat->serious_err_cnt))
4498 goto reset;
4499
4500 /* Check for data parity error */
4501 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4502 &sw_stat->parity_err_cnt))
4503 goto reset;
4504
4505 /* Check for ring full counter */
4506 if (sp->device_type == XFRAME_II_DEVICE) {
4507 val64 = readq(&bar0->ring_bump_counter1);
4508 for (i=0; i<4; i++) {
4509 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4510 temp64 >>= 64 - ((i+1)*16);
4511 sw_stat->ring_full_cnt[i] += temp64;
4512 }
4513
4514 val64 = readq(&bar0->ring_bump_counter2);
4515 for (i=0; i<4; i++) {
4516 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4517 temp64 >>= 64 - ((i+1)*16);
4518 sw_stat->ring_full_cnt[i+4] += temp64;
4519 }
4520 }
4521
4522 val64 = readq(&bar0->txdma_int_status);
4523 /*check for pfc_err*/
4524 if (val64 & TXDMA_PFC_INT) {
4525 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4526 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4527 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4528 &sw_stat->pfc_err_cnt))
4529 goto reset;
4530 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4531 &sw_stat->pfc_err_cnt);
4532 }
4533
4534 /*check for tda_err*/
4535 if (val64 & TXDMA_TDA_INT) {
4536 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4537 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4538 &sw_stat->tda_err_cnt))
4539 goto reset;
4540 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4541 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4542 }
4543 /*check for pcc_err*/
4544 if (val64 & TXDMA_PCC_INT) {
4545 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4546 | PCC_N_SERR | PCC_6_COF_OV_ERR
4547 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4548 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4549 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4550 &sw_stat->pcc_err_cnt))
4551 goto reset;
4552 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4553 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4554 }
4555
4556 /*check for tti_err*/
4557 if (val64 & TXDMA_TTI_INT) {
4558 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4559 &sw_stat->tti_err_cnt))
4560 goto reset;
4561 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4562 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4563 }
4564
4565 /*check for lso_err*/
4566 if (val64 & TXDMA_LSO_INT) {
4567 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4568 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4569 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4570 goto reset;
4571 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4572 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4573 }
4574
4575 /*check for tpa_err*/
4576 if (val64 & TXDMA_TPA_INT) {
4577 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4578 &sw_stat->tpa_err_cnt))
4579 goto reset;
4580 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4581 &sw_stat->tpa_err_cnt);
4582 }
4583
4584 /*check for sm_err*/
4585 if (val64 & TXDMA_SM_INT) {
4586 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4587 &sw_stat->sm_err_cnt))
4588 goto reset;
4589 }
4590
4591 val64 = readq(&bar0->mac_int_status);
4592 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4593 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4594 &bar0->mac_tmac_err_reg,
4595 &sw_stat->mac_tmac_err_cnt))
4596 goto reset;
4597 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4598 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4599 &bar0->mac_tmac_err_reg,
4600 &sw_stat->mac_tmac_err_cnt);
4601 }
4602
4603 val64 = readq(&bar0->xgxs_int_status);
4604 if (val64 & XGXS_INT_STATUS_TXGXS) {
4605 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4606 &bar0->xgxs_txgxs_err_reg,
4607 &sw_stat->xgxs_txgxs_err_cnt))
4608 goto reset;
4609 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4610 &bar0->xgxs_txgxs_err_reg,
4611 &sw_stat->xgxs_txgxs_err_cnt);
4612 }
4613
4614 val64 = readq(&bar0->rxdma_int_status);
4615 if (val64 & RXDMA_INT_RC_INT_M) {
4616 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4617 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4618 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4619 goto reset;
4620 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4621 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4622 &sw_stat->rc_err_cnt);
4623 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4624 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4625 &sw_stat->prc_pcix_err_cnt))
4626 goto reset;
4627 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4628 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4629 &sw_stat->prc_pcix_err_cnt);
4630 }
4631
4632 if (val64 & RXDMA_INT_RPA_INT_M) {
4633 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4634 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4635 goto reset;
4636 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4637 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4638 }
4639
4640 if (val64 & RXDMA_INT_RDA_INT_M) {
4641 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4642 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4643 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4644 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4645 goto reset;
4646 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4647 | RDA_MISC_ERR | RDA_PCIX_ERR,
4648 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4649 }
4650
4651 if (val64 & RXDMA_INT_RTI_INT_M) {
4652 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4653 &sw_stat->rti_err_cnt))
4654 goto reset;
4655 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4656 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4657 }
4658
4659 val64 = readq(&bar0->mac_int_status);
4660 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4661 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4662 &bar0->mac_rmac_err_reg,
4663 &sw_stat->mac_rmac_err_cnt))
4664 goto reset;
4665 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4666 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4667 &sw_stat->mac_rmac_err_cnt);
4668 }
4669
4670 val64 = readq(&bar0->xgxs_int_status);
4671 if (val64 & XGXS_INT_STATUS_RXGXS) {
4672 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4673 &bar0->xgxs_rxgxs_err_reg,
4674 &sw_stat->xgxs_rxgxs_err_cnt))
4675 goto reset;
4676 }
4677
4678 val64 = readq(&bar0->mc_int_status);
4679 if(val64 & MC_INT_STATUS_MC_INT) {
4680 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4681 &sw_stat->mc_err_cnt))
4682 goto reset;
4683
4684 /* Handling Ecc errors */
4685 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4686 writeq(val64, &bar0->mc_err_reg);
4687 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4688 sw_stat->double_ecc_errs++;
4689 if (sp->device_type != XFRAME_II_DEVICE) {
4690 /*
4691 * Reset XframeI only if critical error
4692 */
4693 if (val64 &
4694 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4695 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4696 goto reset;
4697 }
4698 } else
4699 sw_stat->single_ecc_errs++;
4700 }
4701 }
4702 return;
4703
4704reset:
3a3d5756 4705 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4706 schedule_work(&sp->rst_timer_task);
4707 sw_stat->soft_reset_cnt++;
4708 return;
4709}
4710
1da177e4
LT		 4711/**
4712 * s2io_isr - ISR handler of the device .
4713 * @irq: the irq of the device.
4714 * @dev_id: a void pointer to the dev structure of the NIC.
20346722 4715 * Description: This function is the ISR handler of the device. It
4716 * identifies the reason for the interrupt and calls the relevant
4717 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4718 * recv buffers, if their numbers are below the panic value which is
4719 * presently set to 25% of the original number of rcv buffers allocated.
4720 * Return value:
20346722 4721 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4722 * IRQ_NONE: will be returned if interrupt is not from our device
4723 */
7d12e780 4724static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4725{
4726 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77
RB		 4727 struct s2io_nic *sp = dev->priv;
4728 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4729 int i;
19a60522 4730 u64 reason = 0;
1ee6dd77 4731 struct mac_info *mac_control;
1da177e4
LT		 4732 struct config_param *config;
4733
d796fdb7
LV		 4734 /* Pretend we handled any irq's from a disconnected card */
4735 if (pci_channel_offline(sp->pdev))
4736 return IRQ_NONE;
4737
596c5c97 4738 if (!is_s2io_card_up(sp))
92b84437 4739 return IRQ_NONE;
92b84437 4740
1da177e4
LT		 4741 mac_control = &sp->mac_control;
4742 config = &sp->config;
4743
20346722 4744 /*
1da177e4
LT		 4745 * Identify the cause for interrupt and call the appropriate
4746 * interrupt handler. Causes for the interrupt could be;
4747 * 1. Rx of packet.
4748 * 2. Tx complete.
4749 * 3. Link down.
1da177e4
LT		 4750 */
4751 reason = readq(&bar0->general_int_status);
4752
596c5c97
SS		 4753 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4754 /* Nothing much can be done. Get out */
4755 return IRQ_HANDLED;
1da177e4 4756 }
5d3213cc 4757
596c5c97
SS		 4758 if (reason & (GEN_INTR_RXTRAFFIC |
4759 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4760 {
4761 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4762
4763 if (config->napi) {
4764 if (reason & GEN_INTR_RXTRAFFIC) {
4765 if (likely(netif_rx_schedule_prep(dev,
4766 &sp->napi))) {
4767 __netif_rx_schedule(dev, &sp->napi);
4768 writeq(S2IO_MINUS_ONE,
4769 &bar0->rx_traffic_mask);
4770 } else
4771 writeq(S2IO_MINUS_ONE,
4772 &bar0->rx_traffic_int);
db874e65 4773 }
596c5c97
SS		 4774 } else {
4775 /*
4776 * rx_traffic_int reg is an R1 register, writing all 1's
4777 * will ensure that the actual interrupt causing bit
4778 * get's cleared and hence a read can be avoided.
4779 */
4780 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4781 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97
SS		 4782
4783 for (i = 0; i < config->rx_ring_num; i++)
4784 rx_intr_handler(&mac_control->rings[i]);
db874e65 4785 }
596c5c97 4786
db874e65 4787 /*
596c5c97 4788 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4789 * will ensure that the actual interrupt causing bit get's
4790 * cleared and hence a read can be avoided.
4791 */
596c5c97
SS		 4792 if (reason & GEN_INTR_TXTRAFFIC)
4793 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4794
596c5c97
SS		 4795 for (i = 0; i < config->tx_fifo_num; i++)
4796 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4797
596c5c97
SS		 4798 if (reason & GEN_INTR_TXPIC)
4799 s2io_txpic_intr_handle(sp);
fe113638 4800
596c5c97
SS		 4801 /*
4802 * Reallocate the buffers from the interrupt handler itself.
4803 */
4804 if (!config->napi) {
4805 for (i = 0; i < config->rx_ring_num; i++)
0425b46a 4806 s2io_chk_rx_buffers(&mac_control->rings[i]);
596c5c97
SS		 4807 }
4808 writeq(sp->general_int_mask, &bar0->general_int_mask);
4809 readl(&bar0->general_int_status);
20346722 4810
596c5c97 4811 return IRQ_HANDLED;
db874e65 4812
596c5c97
SS		 4813 }
4814 else if (!reason) {
4815 /* The interrupt was not raised by us */
4816 return IRQ_NONE;
4817 }
db874e65 4818
1da177e4
LT		 4819 return IRQ_HANDLED;
4820}
4821
7ba013ac 4822/**
4823 * s2io_updt_stats -
4824 */
1ee6dd77 4825static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4826{
1ee6dd77 4827 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac 4828 u64 val64;
4829 int cnt = 0;
4830
92b84437 4831 if (is_s2io_card_up(sp)) {
7ba013ac 4832 /* Apprx 30us on a 133 MHz bus */
4833 val64 = SET_UPDT_CLICKS(10) |
4834 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4835 writeq(val64, &bar0->stat_cfg);
4836 do {
4837 udelay(100);
4838 val64 = readq(&bar0->stat_cfg);
b7b5a128 4839 if (!(val64 & s2BIT(0)))
7ba013ac 4840 break;
4841 cnt++;
4842 if (cnt == 5)
4843 break; /* Updt failed */
4844 } while(1);
8a4bdbaa 4845 }
7ba013ac 4846}
4847
1da177e4 4848/**
20346722 4849 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4850 * @dev : pointer to the device structure.
4851 * Description:
20346722 4852 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4853 * structure and returns a pointer to the same.
4854 * Return value:
4855 * pointer to the updated net_device_stats structure.
4856 */
4857
ac1f60db 4858static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4859{
1ee6dd77
RB		 4860 struct s2io_nic *sp = dev->priv;
4861 struct mac_info *mac_control;
1da177e4 4862 struct config_param *config;
0425b46a 4863 int i;
1da177e4 4864
20346722 4865
1da177e4
LT		 4866 mac_control = &sp->mac_control;
4867 config = &sp->config;
4868
7ba013ac 4869 /* Configure Stats for immediate updt */
4870 s2io_updt_stats(sp);
4871
4872 sp->stats.tx_packets =
4873 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722 4874 sp->stats.tx_errors =
4875 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4876 sp->stats.rx_errors =
ee705dba 4877 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722 4878 sp->stats.multicast =
4879 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4880 sp->stats.rx_length_errors =
ee705dba 4881 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4 4882
0425b46a
SH		 4883 /* collect per-ring rx_packets and rx_bytes */
4884 sp->stats.rx_packets = sp->stats.rx_bytes = 0;
4885 for (i = 0; i < config->rx_ring_num; i++) {
4886 sp->stats.rx_packets += mac_control->rings[i].rx_packets;
4887 sp->stats.rx_bytes += mac_control->rings[i].rx_bytes;
4888 }
4889
1da177e4
LT		 4890 return (&sp->stats);
4891}
4892
4893/**
4894 * s2io_set_multicast - entry point for multicast address enable/disable.
4895 * @dev : pointer to the device structure
4896 * Description:
20346722 4897 * This function is a driver entry point which gets called by the kernel
4898 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4899 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4900 * determine, if multicast address must be enabled or if promiscuous mode
4901 * is to be disabled etc.
4902 * Return value:
4903 * void.
4904 */
4905
4906static void s2io_set_multicast(struct net_device *dev)
4907{
4908 int i, j, prev_cnt;
4909 struct dev_mc_list *mclist;
1ee6dd77
RB		 4910 struct s2io_nic *sp = dev->priv;
4911 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4912 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4913 0xfeffffffffffULL;
faa4f796 4914 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4915 void __iomem *add;
faa4f796 4916 struct config_param *config = &sp->config;
1da177e4
LT		 4917
4918 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4919 /* Enable all Multicast addresses */
4920 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4921 &bar0->rmac_addr_data0_mem);
4922 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4923 &bar0->rmac_addr_data1_mem);
4924 val64 = RMAC_ADDR_CMD_MEM_WE |
4925 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 4926 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4927 writeq(val64, &bar0->rmac_addr_cmd_mem);
4928 /* Wait till command completes */
c92ca04b 4929 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4930 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4931 S2IO_BIT_RESET);
1da177e4
LT		 4932
4933 sp->m_cast_flg = 1;
faa4f796 4934 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 4935 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4936 /* Disable all Multicast addresses */
4937 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4938 &bar0->rmac_addr_data0_mem);
5e25b9dd 4939 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4940 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4941 val64 = RMAC_ADDR_CMD_MEM_WE |
4942 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4943 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4944 writeq(val64, &bar0->rmac_addr_cmd_mem);
4945 /* Wait till command completes */
c92ca04b 4946 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4947 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4948 S2IO_BIT_RESET);
1da177e4
LT		 4949
4950 sp->m_cast_flg = 0;
4951 sp->all_multi_pos = 0;
4952 }
4953
4954 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4955 /* Put the NIC into promiscuous mode */
4956 add = &bar0->mac_cfg;
4957 val64 = readq(&bar0->mac_cfg);
4958 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4959
4960 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4961 writel((u32) val64, add);
4962 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4963 writel((u32) (val64 >> 32), (add + 4));
4964
926930b2
SS		 4965 if (vlan_tag_strip != 1) {
4966 val64 = readq(&bar0->rx_pa_cfg);
4967 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4968 writeq(val64, &bar0->rx_pa_cfg);
4969 vlan_strip_flag = 0;
4970 }
4971
1da177e4
LT		 4972 val64 = readq(&bar0->mac_cfg);
4973 sp->promisc_flg = 1;
776bd20f 4974 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 4975 dev->name);
4976 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4977 /* Remove the NIC from promiscuous mode */
4978 add = &bar0->mac_cfg;
4979 val64 = readq(&bar0->mac_cfg);
4980 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4981
4982 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4983 writel((u32) val64, add);
4984 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4985 writel((u32) (val64 >> 32), (add + 4));
4986
926930b2
SS		 4987 if (vlan_tag_strip != 0) {
4988 val64 = readq(&bar0->rx_pa_cfg);
4989 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4990 writeq(val64, &bar0->rx_pa_cfg);
4991 vlan_strip_flag = 1;
4992 }
4993
1da177e4
LT		 4994 val64 = readq(&bar0->mac_cfg);
4995 sp->promisc_flg = 0;
776bd20f 4996 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 4997 dev->name);
4998 }
4999
5000 /* Update individual M_CAST address list */
5001 if ((!sp->m_cast_flg) && dev->mc_count) {
5002 if (dev->mc_count >
faa4f796 5003 (config->max_mc_addr - config->max_mac_addr)) {
1da177e4
LT		 5004 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5005 dev->name);
5006 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5007 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5008 return;
5009 }
5010
5011 prev_cnt = sp->mc_addr_count;
5012 sp->mc_addr_count = dev->mc_count;
5013
5014 /* Clear out the previous list of Mc in the H/W. */
5015 for (i = 0; i < prev_cnt; i++) {
5016 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5017 &bar0->rmac_addr_data0_mem);
5018 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5019 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5020 val64 = RMAC_ADDR_CMD_MEM_WE |
5021 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5022 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5023 (config->mc_start_offset + i);
1da177e4
LT		 5024 writeq(val64, &bar0->rmac_addr_cmd_mem);
5025
5026 /* Wait for command completes */
c92ca04b 5027 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5028 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5029 S2IO_BIT_RESET)) {
1da177e4
LT		 5030 DBG_PRINT(ERR_DBG, "%s: Adding ",
5031 dev->name);
5032 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5033 return;
5034 }
5035 }
5036
5037 /* Create the new Rx filter list and update the same in H/W. */
5038 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5039 i++, mclist = mclist->next) {
5040 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5041 ETH_ALEN);
a7a80d5a 5042 mac_addr = 0;
1da177e4
LT		 5043 for (j = 0; j < ETH_ALEN; j++) {
5044 mac_addr |= mclist->dmi_addr[j];
5045 mac_addr <<= 8;
5046 }
5047 mac_addr >>= 8;
5048 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5049 &bar0->rmac_addr_data0_mem);
5050 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5051 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5052 val64 = RMAC_ADDR_CMD_MEM_WE |
5053 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5054 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5055 (i + config->mc_start_offset);
1da177e4
LT		 5056 writeq(val64, &bar0->rmac_addr_cmd_mem);
5057
5058 /* Wait for command completes */
c92ca04b 5059 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5060 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5061 S2IO_BIT_RESET)) {
1da177e4
LT		 5062 DBG_PRINT(ERR_DBG, "%s: Adding ",
5063 dev->name);
5064 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5065 return;
5066 }
5067 }
5068 }
5069}
5070
faa4f796
SH		 5071/* read from CAM unicast & multicast addresses and store it in
5072 * def_mac_addr structure
5073 */
5074void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5075{
5076 int offset;
5077 u64 mac_addr = 0x0;
5078 struct config_param *config = &sp->config;
5079
5080 /* store unicast & multicast mac addresses */
5081 for (offset = 0; offset < config->max_mc_addr; offset++) {
5082 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5083 /* if read fails disable the entry */
5084 if (mac_addr == FAILURE)
5085 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5086 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5087 }
5088}
5089
5090/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5091static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5092{
5093 int offset;
5094 struct config_param *config = &sp->config;
5095 /* restore unicast mac address */
5096 for (offset = 0; offset < config->max_mac_addr; offset++)
5097 do_s2io_prog_unicast(sp->dev,
5098 sp->def_mac_addr[offset].mac_addr);
5099
5100 /* restore multicast mac address */
5101 for (offset = config->mc_start_offset;
5102 offset < config->max_mc_addr; offset++)
5103 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5104}
5105
5106/* add a multicast MAC address to CAM */
5107static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5108{
5109 int i;
5110 u64 mac_addr = 0;
5111 struct config_param *config = &sp->config;
5112
5113 for (i = 0; i < ETH_ALEN; i++) {
5114 mac_addr <<= 8;
5115 mac_addr |= addr[i];
5116 }
5117 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5118 return SUCCESS;
5119
5120 /* check if the multicast mac already preset in CAM */
5121 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5122 u64 tmp64;
5123 tmp64 = do_s2io_read_unicast_mc(sp, i);
5124 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5125 break;
5126
5127 if (tmp64 == mac_addr)
5128 return SUCCESS;
5129 }
5130 if (i == config->max_mc_addr) {
5131 DBG_PRINT(ERR_DBG,
5132 "CAM full no space left for multicast MAC\n");
5133 return FAILURE;
5134 }
5135 /* Update the internal structure with this new mac address */
5136 do_s2io_copy_mac_addr(sp, i, mac_addr);
5137
5138 return (do_s2io_add_mac(sp, mac_addr, i));
5139}
5140
5141/* add MAC address to CAM */
5142static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5143{
5144 u64 val64;
5145 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5146
5147 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5148 &bar0->rmac_addr_data0_mem);
5149
5150 val64 =
5151 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5152 RMAC_ADDR_CMD_MEM_OFFSET(off);
5153 writeq(val64, &bar0->rmac_addr_cmd_mem);
5154
5155 /* Wait till command completes */
5156 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5157 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5158 S2IO_BIT_RESET)) {
faa4f796 5159 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5160 return FAILURE;
5161 }
5162 return SUCCESS;
5163}
faa4f796
SH		 5164/* deletes a specified unicast/multicast mac entry from CAM */
5165static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5166{
5167 int offset;
5168 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5169 struct config_param *config = &sp->config;
5170
5171 for (offset = 1;
5172 offset < config->max_mc_addr; offset++) {
5173 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5174 if (tmp64 == addr) {
5175 /* disable the entry by writing 0xffffffffffffULL */
5176 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5177 return FAILURE;
5178 /* store the new mac list from CAM */
5179 do_s2io_store_unicast_mc(sp);
5180 return SUCCESS;
5181 }
5182 }
5183 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5184 (unsigned long long)addr);
5185 return FAILURE;
5186}
5187
5188/* read mac entries from CAM */
5189static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5190{
5191 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5192 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5193
5194 /* read mac addr */
5195 val64 =
5196 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5197 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5198 writeq(val64, &bar0->rmac_addr_cmd_mem);
5199
5200 /* Wait till command completes */
5201 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5202 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5203 S2IO_BIT_RESET)) {
5204 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5205 return FAILURE;
5206 }
5207 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5208 return (tmp64 >> 16);
5209}
2fd37688
SS		 5210
5211/**
5212 * s2io_set_mac_addr driver entry point
5213 */
faa4f796 5214
2fd37688
SS		 5215static int s2io_set_mac_addr(struct net_device *dev, void *p)
5216{
5217 struct sockaddr *addr = p;
5218
5219 if (!is_valid_ether_addr(addr->sa_data))
5220 return -EINVAL;
5221
5222 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5223
5224 /* store the MAC address in CAM */
5225 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5226}
1da177e4 5227/**
2fd37688 5228 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5229 * @dev : pointer to the device structure.
5230 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5231 * Description : This procedure will program the Xframe to receive
1da177e4 5232 * frames with new Mac Address
20346722 5233 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5234 * as defined in errno.h file on failure.
5235 */
faa4f796 5236
2fd37688 5237static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5238{
1ee6dd77 5239 struct s2io_nic *sp = dev->priv;
2fd37688 5240 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5241 int i;
faa4f796
SH		 5242 u64 tmp64;
5243 struct config_param *config = &sp->config;
1da177e4 5244
20346722 5245 /*
2fd37688
SS		 5246 * Set the new MAC address as the new unicast filter and reflect this
5247 * change on the device address registered with the OS. It will be
5248 * at offset 0.
5249 */
1da177e4
LT		 5250 for (i = 0; i < ETH_ALEN; i++) {
5251 mac_addr <<= 8;
5252 mac_addr |= addr[i];
2fd37688
SS		 5253 perm_addr <<= 8;
5254 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5255 }
5256
2fd37688
SS		 5257 /* check if the dev_addr is different than perm_addr */
5258 if (mac_addr == perm_addr)
d8d70caf
SS		 5259 return SUCCESS;
5260
faa4f796
SH		 5261 /* check if the mac already preset in CAM */
5262 for (i = 1; i < config->max_mac_addr; i++) {
5263 tmp64 = do_s2io_read_unicast_mc(sp, i);
5264 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5265 break;
5266
5267 if (tmp64 == mac_addr) {
5268 DBG_PRINT(INFO_DBG,
5269 "MAC addr:0x%llx already present in CAM\n",
5270 (unsigned long long)mac_addr);
5271 return SUCCESS;
5272 }
5273 }
5274 if (i == config->max_mac_addr) {
5275 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5276 return FAILURE;
5277 }
d8d70caf 5278 /* Update the internal structure with this new mac address */
faa4f796
SH		 5279 do_s2io_copy_mac_addr(sp, i, mac_addr);
5280 return (do_s2io_add_mac(sp, mac_addr, i));
1da177e4
LT		 5281}
5282
5283/**
20346722 5284 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5285 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5286 * @info: pointer to the structure with parameters given by ethtool to set
5287 * link information.
5288 * Description:
20346722 5289 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5290 * the NIC.
5291 * Return value:
5292 * 0 on success.
5293*/
5294
5295static int s2io_ethtool_sset(struct net_device *dev,
5296 struct ethtool_cmd *info)
5297{
1ee6dd77 5298 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5299 if ((info->autoneg == AUTONEG_ENABLE) ||
5300 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5301 return -EINVAL;
5302 else {
5303 s2io_close(sp->dev);
5304 s2io_open(sp->dev);
5305 }
5306
5307 return 0;
5308}
5309
5310/**
20346722 5311 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5312 * @sp : private member of the device structure, pointer to the
5313 * s2io_nic structure.
5314 * @info : pointer to the structure with parameters given by ethtool
5315 * to return link information.
5316 * Description:
5317 * Returns link specific information like speed, duplex etc.. to ethtool.
5318 * Return value :
5319 * return 0 on success.
5320 */
5321
5322static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5323{
1ee6dd77 5324 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5325 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5326 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5327 info->port = PORT_FIBRE;
1a7eb72b
SS		 5328
5329 /* info->transceiver */
5330 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5331
5332 if (netif_carrier_ok(sp->dev)) {
5333 info->speed = 10000;
5334 info->duplex = DUPLEX_FULL;
5335 } else {
5336 info->speed = -1;
5337 info->duplex = -1;
5338 }
5339
5340 info->autoneg = AUTONEG_DISABLE;
5341 return 0;
5342}
5343
5344/**
20346722 5345 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5346 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5347 * s2io_nic structure.
5348 * @info : pointer to the structure with parameters given by ethtool to
5349 * return driver information.
5350 * Description:
5351 * Returns driver specefic information like name, version etc.. to ethtool.
5352 * Return value:
5353 * void
5354 */
5355
5356static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5357 struct ethtool_drvinfo *info)
5358{
1ee6dd77 5359 struct s2io_nic *sp = dev->priv;
1da177e4 5360
dbc2309d
JL		 5361 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5362 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5363 strncpy(info->fw_version, "", sizeof(info->fw_version));
5364 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5365 info->regdump_len = XENA_REG_SPACE;
5366 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5367}
5368
5369/**
5370 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5371 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5372 * s2io_nic structure.
20346722 5373 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5374 * dumping the registers.
5375 * @reg_space: The input argumnet into which all the registers are dumped.
5376 * Description:
5377 * Dumps the entire register space of xFrame NIC into the user given
5378 * buffer area.
5379 * Return value :
5380 * void .
5381*/
5382
5383static void s2io_ethtool_gregs(struct net_device *dev,
5384 struct ethtool_regs *regs, void *space)
5385{
5386 int i;
5387 u64 reg;
5388 u8 *reg_space = (u8 *) space;
1ee6dd77 5389 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5390
5391 regs->len = XENA_REG_SPACE;
5392 regs->version = sp->pdev->subsystem_device;
5393
5394 for (i = 0; i < regs->len; i += 8) {
5395 reg = readq(sp->bar0 + i);
5396 memcpy((reg_space + i), &reg, 8);
5397 }
5398}
5399
5400/**
5401 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5402 * @data : address of the private member of the device structure, which
1da177e4 5403 * is a pointer to the s2io_nic structure, provided as an u32.
20346722 5404 * Description: This is actually the timer function that alternates the
5405 * adapter LED bit of the adapter control bit to set/reset every time on
5406 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 5407 * once every second.
5408*/
5409static void s2io_phy_id(unsigned long data)
5410{
1ee6dd77
RB		 5411 struct s2io_nic *sp = (struct s2io_nic *) data;
5412 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5413 u64 val64 = 0;
5414 u16 subid;
5415
5416 subid = sp->pdev->subsystem_device;
541ae68f 5417 if ((sp->device_type == XFRAME_II_DEVICE) ||
5418 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5419 val64 = readq(&bar0->gpio_control);
5420 val64 ^= GPIO_CTRL_GPIO_0;
5421 writeq(val64, &bar0->gpio_control);
5422 } else {
5423 val64 = readq(&bar0->adapter_control);
5424 val64 ^= ADAPTER_LED_ON;
5425 writeq(val64, &bar0->adapter_control);
5426 }
5427
5428 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5429}
5430
5431/**
5432 * s2io_ethtool_idnic - To physically identify the nic on the system.
5433 * @sp : private member of the device structure, which is a pointer to the
5434 * s2io_nic structure.
20346722 5435 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5436 * ethtool.
5437 * Description: Used to physically identify the NIC on the system.
20346722 5438 * The Link LED will blink for a time specified by the user for
1da177e4 5439 * identification.
20346722 5440 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5441 * identification is possible only if it's link is up.
5442 * Return value:
5443 * int , returns 0 on success
5444 */
5445
5446static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5447{
5448 u64 val64 = 0, last_gpio_ctrl_val;
1ee6dd77
RB		 5449 struct s2io_nic *sp = dev->priv;
5450 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5451 u16 subid;
5452
5453 subid = sp->pdev->subsystem_device;
5454 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f 5455 if ((sp->device_type == XFRAME_I_DEVICE) &&
5456 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5457 val64 = readq(&bar0->adapter_control);
5458 if (!(val64 & ADAPTER_CNTL_EN)) {
5459 printk(KERN_ERR
5460 "Adapter Link down, cannot blink LED\n");
5461 return -EFAULT;
5462 }
5463 }
5464 if (sp->id_timer.function == NULL) {
5465 init_timer(&sp->id_timer);
5466 sp->id_timer.function = s2io_phy_id;
5467 sp->id_timer.data = (unsigned long) sp;
5468 }
5469 mod_timer(&sp->id_timer, jiffies);
5470 if (data)
20346722 5471 msleep_interruptible(data * HZ);
1da177e4 5472 else
20346722 5473 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5474 del_timer_sync(&sp->id_timer);
5475
541ae68f 5476 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5477 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5478 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5479 }
5480
5481 return 0;
5482}
5483
0cec35eb
SH		 5484static void s2io_ethtool_gringparam(struct net_device *dev,
5485 struct ethtool_ringparam *ering)
5486{
5487 struct s2io_nic *sp = dev->priv;
5488 int i,tx_desc_count=0,rx_desc_count=0;
5489
5490 if (sp->rxd_mode == RXD_MODE_1)
5491 ering->rx_max_pending = MAX_RX_DESC_1;
5492 else if (sp->rxd_mode == RXD_MODE_3B)
5493 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5494
5495 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5496 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5497 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5498
0cec35eb
SH		 5499 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5500 ering->tx_pending = tx_desc_count;
5501 rx_desc_count = 0;
8a4bdbaa 5502 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5503 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5504
0cec35eb
SH		 5505 ering->rx_pending = rx_desc_count;
5506
5507 ering->rx_mini_max_pending = 0;
5508 ering->rx_mini_pending = 0;
5509 if(sp->rxd_mode == RXD_MODE_1)
5510 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5511 else if (sp->rxd_mode == RXD_MODE_3B)
5512 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5513 ering->rx_jumbo_pending = rx_desc_count;
5514}
5515
1da177e4
LT		 5516/**
5517 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722 5518 * @sp : private member of the device structure, which is a pointer to the
5519 * s2io_nic structure.
1da177e4
LT		 5520 * @ep : pointer to the structure with pause parameters given by ethtool.
5521 * Description:
5522 * Returns the Pause frame generation and reception capability of the NIC.
5523 * Return value:
5524 * void
5525 */
5526static void s2io_ethtool_getpause_data(struct net_device *dev,
5527 struct ethtool_pauseparam *ep)
5528{
5529 u64 val64;
1ee6dd77
RB		 5530 struct s2io_nic *sp = dev->priv;
5531 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5532
5533 val64 = readq(&bar0->rmac_pause_cfg);
5534 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5535 ep->tx_pause = TRUE;
5536 if (val64 & RMAC_PAUSE_RX_ENABLE)
5537 ep->rx_pause = TRUE;
5538 ep->autoneg = FALSE;
5539}
5540
5541/**
5542 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5543 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5544 * s2io_nic structure.
5545 * @ep : pointer to the structure with pause parameters given by ethtool.
5546 * Description:
5547 * It can be used to set or reset Pause frame generation or reception
5548 * support of the NIC.
5549 * Return value:
5550 * int, returns 0 on Success
5551 */
5552
5553static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 5554 struct ethtool_pauseparam *ep)
1da177e4
LT		 5555{
5556 u64 val64;
1ee6dd77
RB		 5557 struct s2io_nic *sp = dev->priv;
5558 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5559
5560 val64 = readq(&bar0->rmac_pause_cfg);
5561 if (ep->tx_pause)
5562 val64 |= RMAC_PAUSE_GEN_ENABLE;
5563 else
5564 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5565 if (ep->rx_pause)
5566 val64 |= RMAC_PAUSE_RX_ENABLE;
5567 else
5568 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5569 writeq(val64, &bar0->rmac_pause_cfg);
5570 return 0;
5571}
5572
5573/**
5574 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5575 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5576 * s2io_nic structure.
5577 * @off : offset at which the data must be written
5578 * @data : Its an output parameter where the data read at the given
20346722 5579 * offset is stored.
1da177e4 5580 * Description:
20346722 5581 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5582 * read data.
5583 * NOTE: Will allow to read only part of the EEPROM visible through the
5584 * I2C bus.
5585 * Return value:
5586 * -1 on failure and 0 on success.
5587 */
5588
5589#define S2IO_DEV_ID 5
1ee6dd77 5590static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 5591{
5592 int ret = -1;
5593 u32 exit_cnt = 0;
5594 u64 val64;
1ee6dd77 5595 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5596
ad4ebed0 5597 if (sp->device_type == XFRAME_I_DEVICE) {
5598 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5599 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5600 I2C_CONTROL_CNTL_START;
5601 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5602
ad4ebed0 5603 while (exit_cnt < 5) {
5604 val64 = readq(&bar0->i2c_control);
5605 if (I2C_CONTROL_CNTL_END(val64)) {
5606 *data = I2C_CONTROL_GET_DATA(val64);
5607 ret = 0;
5608 break;
5609 }
5610 msleep(50);
5611 exit_cnt++;
1da177e4 5612 }
1da177e4
LT		 5613 }
5614
ad4ebed0 5615 if (sp->device_type == XFRAME_II_DEVICE) {
5616 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5617 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5618 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5619 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5620 val64 |= SPI_CONTROL_REQ;
5621 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5622 while (exit_cnt < 5) {
5623 val64 = readq(&bar0->spi_control);
5624 if (val64 & SPI_CONTROL_NACK) {
5625 ret = 1;
5626 break;
5627 } else if (val64 & SPI_CONTROL_DONE) {
5628 *data = readq(&bar0->spi_data);
5629 *data &= 0xffffff;
5630 ret = 0;
5631 break;
5632 }
5633 msleep(50);
5634 exit_cnt++;
5635 }
5636 }
1da177e4
LT		 5637 return ret;
5638}
5639
5640/**
5641 * write_eeprom - actually writes the relevant part of the data value.
5642 * @sp : private member of the device structure, which is a pointer to the
5643 * s2io_nic structure.
5644 * @off : offset at which the data must be written
5645 * @data : The data that is to be written
20346722 5646 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5647 * the Eeprom. (max of 3)
5648 * Description:
5649 * Actually writes the relevant part of the data value into the Eeprom
5650 * through the I2C bus.
5651 * Return value:
5652 * 0 on success, -1 on failure.
5653 */
5654
1ee6dd77 5655static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 5656{
5657 int exit_cnt = 0, ret = -1;
5658 u64 val64;
1ee6dd77 5659 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5660
ad4ebed0 5661 if (sp->device_type == XFRAME_I_DEVICE) {
5662 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5663 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5664 I2C_CONTROL_CNTL_START;
5665 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5666
5667 while (exit_cnt < 5) {
5668 val64 = readq(&bar0->i2c_control);
5669 if (I2C_CONTROL_CNTL_END(val64)) {
5670 if (!(val64 & I2C_CONTROL_NACK))
5671 ret = 0;
5672 break;
5673 }
5674 msleep(50);
5675 exit_cnt++;
5676 }
5677 }
1da177e4 5678
ad4ebed0 5679 if (sp->device_type == XFRAME_II_DEVICE) {
5680 int write_cnt = (cnt == 8) ? 0 : cnt;
5681 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5682
5683 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5684 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5685 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5686 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5687 val64 |= SPI_CONTROL_REQ;
5688 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5689 while (exit_cnt < 5) {
5690 val64 = readq(&bar0->spi_control);
5691 if (val64 & SPI_CONTROL_NACK) {
5692 ret = 1;
5693 break;
5694 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5695 ret = 0;
ad4ebed0 5696 break;
5697 }
5698 msleep(50);
5699 exit_cnt++;
1da177e4 5700 }
1da177e4 5701 }
1da177e4
LT		 5702 return ret;
5703}
1ee6dd77 5704static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5705{
b41477f3
AR		 5706 u8 *vpd_data;
5707 u8 data;
9dc737a7
AR		 5708 int i=0, cnt, fail = 0;
5709 int vpd_addr = 0x80;
5710
5711 if (nic->device_type == XFRAME_II_DEVICE) {
5712 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5713 vpd_addr = 0x80;
5714 }
5715 else {
5716 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5717 vpd_addr = 0x50;
5718 }
19a60522 5719 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5720
b41477f3 5721 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5722 if (!vpd_data) {
5723 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5724 return;
c53d4945 5725 }
491976b2 5726 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5727
9dc737a7
AR		 5728 for (i = 0; i < 256; i +=4 ) {
5729 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5730 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5731 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5732 for (cnt = 0; cnt <5; cnt++) {
5733 msleep(2);
5734 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5735 if (data == 0x80)
5736 break;
5737 }
5738 if (cnt >= 5) {
5739 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5740 fail = 1;
5741 break;
5742 }
5743 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5744 (u32 *)&vpd_data[i]);
5745 }
19a60522
SS		 5746
5747 if(!fail) {
5748 /* read serial number of adapter */
5749 for (cnt = 0; cnt < 256; cnt++) {
5750 if ((vpd_data[cnt] == 'S') &&
5751 (vpd_data[cnt+1] == 'N') &&
5752 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5753 memset(nic->serial_num, 0, VPD_STRING_LEN);
5754 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5755 vpd_data[cnt+2]);
5756 break;
5757 }
5758 }
5759 }
5760
5761 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5762 memset(nic->product_name, 0, vpd_data[1]);
5763 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5764 }
b41477f3 5765 kfree(vpd_data);
491976b2 5766 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5767}
5768
1da177e4
LT		 5769/**
5770 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5771 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5772 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5773 * containing all relevant information.
5774 * @data_buf : user defined value to be written into Eeprom.
5775 * Description: Reads the values stored in the Eeprom at given offset
5776 * for a given length. Stores these values int the input argument data
5777 * buffer 'data_buf' and returns these to the caller (ethtool.)
5778 * Return value:
5779 * int 0 on success
5780 */
5781
5782static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5783 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5784{
ad4ebed0 5785 u32 i, valid;
5786 u64 data;
1ee6dd77 5787 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5788
5789 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5790
5791 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5792 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5793
5794 for (i = 0; i < eeprom->len; i += 4) {
5795 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5796 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5797 return -EFAULT;
5798 }
5799 valid = INV(data);
5800 memcpy((data_buf + i), &valid, 4);
5801 }
5802 return 0;
5803}
5804
5805/**
5806 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5807 * @sp : private member of the device structure, which is a pointer to the
5808 * s2io_nic structure.
20346722 5809 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5810 * containing all relevant information.
5811 * @data_buf ; user defined value to be written into Eeprom.
5812 * Description:
5813 * Tries to write the user provided value in the Eeprom, at the offset
5814 * given by the user.
5815 * Return value:
5816 * 0 on success, -EFAULT on failure.
5817 */
5818
5819static int s2io_ethtool_seeprom(struct net_device *dev,
5820 struct ethtool_eeprom *eeprom,
5821 u8 * data_buf)
5822{
5823 int len = eeprom->len, cnt = 0;
ad4ebed0 5824 u64 valid = 0, data;
1ee6dd77 5825 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5826
5827 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5828 DBG_PRINT(ERR_DBG,
5829 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5830 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5831 eeprom->magic);
5832 return -EFAULT;
5833 }
5834
5835 while (len) {
5836 data = (u32) data_buf[cnt] & 0x000000FF;
5837 if (data) {
5838 valid = (u32) (data << 24);
5839 } else
5840 valid = data;
5841
5842 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5843 DBG_PRINT(ERR_DBG,
5844 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5845 DBG_PRINT(ERR_DBG,
5846 "write into the specified offset\n");
5847 return -EFAULT;
5848 }
5849 cnt++;
5850 len--;
5851 }
5852
5853 return 0;
5854}
5855
5856/**
20346722 5857 * s2io_register_test - reads and writes into all clock domains.
5858 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5859 * s2io_nic structure.
5860 * @data : variable that returns the result of each of the test conducted b
5861 * by the driver.
5862 * Description:
5863 * Read and write into all clock domains. The NIC has 3 clock domains,
5864 * see that registers in all the three regions are accessible.
5865 * Return value:
5866 * 0 on success.
5867 */
5868
1ee6dd77 5869static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5870{
1ee6dd77 5871 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5872 u64 val64 = 0, exp_val;
1da177e4
LT		 5873 int fail = 0;
5874
20346722 5875 val64 = readq(&bar0->pif_rd_swapper_fb);
5876 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5877 fail = 1;
5878 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5879 }
5880
5881 val64 = readq(&bar0->rmac_pause_cfg);
5882 if (val64 != 0xc000ffff00000000ULL) {
5883 fail = 1;
5884 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5885 }
5886
5887 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5888 if (sp->device_type == XFRAME_II_DEVICE)
5889 exp_val = 0x0404040404040404ULL;
5890 else
5891 exp_val = 0x0808080808080808ULL;
5892 if (val64 != exp_val) {
1da177e4
LT		 5893 fail = 1;
5894 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5895 }
5896
5897 val64 = readq(&bar0->xgxs_efifo_cfg);
5898 if (val64 != 0x000000001923141EULL) {
5899 fail = 1;
5900 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5901 }
5902
5903 val64 = 0x5A5A5A5A5A5A5A5AULL;
5904 writeq(val64, &bar0->xmsi_data);
5905 val64 = readq(&bar0->xmsi_data);
5906 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5907 fail = 1;
5908 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5909 }
5910
5911 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5912 writeq(val64, &bar0->xmsi_data);
5913 val64 = readq(&bar0->xmsi_data);
5914 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5915 fail = 1;
5916 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5917 }
5918
5919 *data = fail;
ad4ebed0 5920 return fail;
1da177e4
LT		 5921}
5922
5923/**
20346722 5924 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5925 * @sp : private member of the device structure, which is a pointer to the
5926 * s2io_nic structure.
5927 * @data:variable that returns the result of each of the test conducted by
5928 * the driver.
5929 * Description:
20346722 5930 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5931 * register.
5932 * Return value:
5933 * 0 on success.
5934 */
5935
1ee6dd77 5936static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5937{
5938 int fail = 0;
ad4ebed0 5939 u64 ret_data, org_4F0, org_7F0;
5940 u8 saved_4F0 = 0, saved_7F0 = 0;
5941 struct net_device *dev = sp->dev;
1da177e4
LT		 5942
5943 /* Test Write Error at offset 0 */
ad4ebed0 5944 /* Note that SPI interface allows write access to all areas
5945 * of EEPROM. Hence doing all negative testing only for Xframe I.
5946 */
5947 if (sp->device_type == XFRAME_I_DEVICE)
5948 if (!write_eeprom(sp, 0, 0, 3))
5949 fail = 1;
5950
5951 /* Save current values at offsets 0x4F0 and 0x7F0 */
5952 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5953 saved_4F0 = 1;
5954 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5955 saved_7F0 = 1;
1da177e4
LT		 5956
5957 /* Test Write at offset 4f0 */
ad4ebed0 5958 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5959 fail = 1;
5960 if (read_eeprom(sp, 0x4F0, &ret_data))
5961 fail = 1;
5962
ad4ebed0 5963 if (ret_data != 0x012345) {
26b7625c
AM		 5964 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5965 "Data written %llx Data read %llx\n",
5966 dev->name, (unsigned long long)0x12345,
5967 (unsigned long long)ret_data);
1da177e4 5968 fail = 1;
ad4ebed0 5969 }
1da177e4
LT		 5970
5971 /* Reset the EEPROM data go FFFF */
ad4ebed0 5972 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 5973
5974 /* Test Write Request Error at offset 0x7c */
ad4ebed0 5975 if (sp->device_type == XFRAME_I_DEVICE)
5976 if (!write_eeprom(sp, 0x07C, 0, 3))
5977 fail = 1;
1da177e4 5978
ad4ebed0 5979 /* Test Write Request at offset 0x7f0 */
5980 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 5981 fail = 1;
ad4ebed0 5982 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 5983 fail = 1;
5984
ad4ebed0 5985 if (ret_data != 0x012345) {
26b7625c
AM		 5986 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5987 "Data written %llx Data read %llx\n",
5988 dev->name, (unsigned long long)0x12345,
5989 (unsigned long long)ret_data);
1da177e4 5990 fail = 1;
ad4ebed0 5991 }
1da177e4
LT		 5992
5993 /* Reset the EEPROM data go FFFF */
ad4ebed0 5994 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 5995
ad4ebed0 5996 if (sp->device_type == XFRAME_I_DEVICE) {
5997 /* Test Write Error at offset 0x80 */
5998 if (!write_eeprom(sp, 0x080, 0, 3))
5999 fail = 1;
1da177e4 6000
ad4ebed0 6001 /* Test Write Error at offset 0xfc */
6002 if (!write_eeprom(sp, 0x0FC, 0, 3))
6003 fail = 1;
1da177e4 6004
ad4ebed0 6005 /* Test Write Error at offset 0x100 */
6006 if (!write_eeprom(sp, 0x100, 0, 3))
6007 fail = 1;
1da177e4 6008
ad4ebed0 6009 /* Test Write Error at offset 4ec */
6010 if (!write_eeprom(sp, 0x4EC, 0, 3))
6011 fail = 1;
6012 }
6013
6014 /* Restore values at offsets 0x4F0 and 0x7F0 */
6015 if (saved_4F0)
6016 write_eeprom(sp, 0x4F0, org_4F0, 3);
6017 if (saved_7F0)
6018 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6019
6020 *data = fail;
ad4ebed0 6021 return fail;
1da177e4
LT		 6022}
6023
6024/**
6025 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6026 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6027 * s2io_nic structure.
20346722 6028 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6029 * the driver.
6030 * Description:
6031 * This invokes the MemBist test of the card. We give around
6032 * 2 secs time for the Test to complete. If it's still not complete
20346722 6033 * within this peiod, we consider that the test failed.
1da177e4
LT		 6034 * Return value:
6035 * 0 on success and -1 on failure.
6036 */
6037
1ee6dd77 6038static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 6039{
6040 u8 bist = 0;
6041 int cnt = 0, ret = -1;
6042
6043 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6044 bist |= PCI_BIST_START;
6045 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6046
6047 while (cnt < 20) {
6048 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6049 if (!(bist & PCI_BIST_START)) {
6050 *data = (bist & PCI_BIST_CODE_MASK);
6051 ret = 0;
6052 break;
6053 }
6054 msleep(100);
6055 cnt++;
6056 }
6057
6058 return ret;
6059}
6060
6061/**
20346722 6062 * s2io-link_test - verifies the link state of the nic
6063 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6064 * s2io_nic structure.
6065 * @data: variable that returns the result of each of the test conducted by
6066 * the driver.
6067 * Description:
20346722 6068 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6069 * argument 'data' appropriately.
6070 * Return value:
6071 * 0 on success.
6072 */
6073
1ee6dd77 6074static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6075{
1ee6dd77 6076 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6077 u64 val64;
6078
6079 val64 = readq(&bar0->adapter_status);
c92ca04b 6080 if(!(LINK_IS_UP(val64)))
1da177e4 6081 *data = 1;
c92ca04b
AR		 6082 else
6083 *data = 0;
1da177e4 6084
b41477f3 6085 return *data;
1da177e4
LT		 6086}
6087
6088/**
20346722 6089 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6090 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6091 * s2io_nic structure.
20346722 6092 * @data - variable that returns the result of each of the test
1da177e4
LT		 6093 * conducted by the driver.
6094 * Description:
20346722 6095 * This is one of the offline test that tests the read and write
1da177e4
LT		 6096 * access to the RldRam chip on the NIC.
6097 * Return value:
6098 * 0 on success.
6099 */
6100
1ee6dd77 6101static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6102{
1ee6dd77 6103 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6104 u64 val64;
ad4ebed0 6105 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6106
6107 val64 = readq(&bar0->adapter_control);
6108 val64 &= ~ADAPTER_ECC_EN;
6109 writeq(val64, &bar0->adapter_control);
6110
6111 val64 = readq(&bar0->mc_rldram_test_ctrl);
6112 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6113 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6114
6115 val64 = readq(&bar0->mc_rldram_mrs);
6116 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6117 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6118
6119 val64 |= MC_RLDRAM_MRS_ENABLE;
6120 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6121
6122 while (iteration < 2) {
6123 val64 = 0x55555555aaaa0000ULL;
6124 if (iteration == 1) {
6125 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6126 }
6127 writeq(val64, &bar0->mc_rldram_test_d0);
6128
6129 val64 = 0xaaaa5a5555550000ULL;
6130 if (iteration == 1) {
6131 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6132 }
6133 writeq(val64, &bar0->mc_rldram_test_d1);
6134
6135 val64 = 0x55aaaaaaaa5a0000ULL;
6136 if (iteration == 1) {
6137 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6138 }
6139 writeq(val64, &bar0->mc_rldram_test_d2);
6140
ad4ebed0 6141 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6142 writeq(val64, &bar0->mc_rldram_test_add);
6143
ad4ebed0 6144 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6145 MC_RLDRAM_TEST_GO;
6146 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6147
6148 for (cnt = 0; cnt < 5; cnt++) {
6149 val64 = readq(&bar0->mc_rldram_test_ctrl);
6150 if (val64 & MC_RLDRAM_TEST_DONE)
6151 break;
6152 msleep(200);
6153 }
6154
6155 if (cnt == 5)
6156 break;
6157
ad4ebed0 6158 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6159 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6160
6161 for (cnt = 0; cnt < 5; cnt++) {
6162 val64 = readq(&bar0->mc_rldram_test_ctrl);
6163 if (val64 & MC_RLDRAM_TEST_DONE)
6164 break;
6165 msleep(500);
6166 }
6167
6168 if (cnt == 5)
6169 break;
6170
6171 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6172 if (!(val64 & MC_RLDRAM_TEST_PASS))
6173 test_fail = 1;
1da177e4
LT		 6174
6175 iteration++;
6176 }
6177
ad4ebed0 6178 *data = test_fail;
1da177e4 6179
ad4ebed0 6180 /* Bring the adapter out of test mode */
6181 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6182
6183 return test_fail;
1da177e4
LT		 6184}
6185
6186/**
6187 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6188 * @sp : private member of the device structure, which is a pointer to the
6189 * s2io_nic structure.
6190 * @ethtest : pointer to a ethtool command specific structure that will be
6191 * returned to the user.
20346722 6192 * @data : variable that returns the result of each of the test
1da177e4
LT		 6193 * conducted by the driver.
6194 * Description:
6195 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6196 * the health of the card.
6197 * Return value:
6198 * void
6199 */
6200
6201static void s2io_ethtool_test(struct net_device *dev,
6202 struct ethtool_test *ethtest,
6203 uint64_t * data)
6204{
1ee6dd77 6205 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6206 int orig_state = netif_running(sp->dev);
6207
6208 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6209 /* Offline Tests. */
20346722 6210 if (orig_state)
1da177e4 6211 s2io_close(sp->dev);
1da177e4
LT		 6212
6213 if (s2io_register_test(sp, &data[0]))
6214 ethtest->flags |= ETH_TEST_FL_FAILED;
6215
6216 s2io_reset(sp);
1da177e4
LT		 6217
6218 if (s2io_rldram_test(sp, &data[3]))
6219 ethtest->flags |= ETH_TEST_FL_FAILED;
6220
6221 s2io_reset(sp);
1da177e4
LT		 6222
6223 if (s2io_eeprom_test(sp, &data[1]))
6224 ethtest->flags |= ETH_TEST_FL_FAILED;
6225
6226 if (s2io_bist_test(sp, &data[4]))
6227 ethtest->flags |= ETH_TEST_FL_FAILED;
6228
6229 if (orig_state)
6230 s2io_open(sp->dev);
6231
6232 data[2] = 0;
6233 } else {
6234 /* Online Tests. */
6235 if (!orig_state) {
6236 DBG_PRINT(ERR_DBG,
6237 "%s: is not up, cannot run test\n",
6238 dev->name);
6239 data[0] = -1;
6240 data[1] = -1;
6241 data[2] = -1;
6242 data[3] = -1;
6243 data[4] = -1;
6244 }
6245
6246 if (s2io_link_test(sp, &data[2]))
6247 ethtest->flags |= ETH_TEST_FL_FAILED;
6248
6249 data[0] = 0;
6250 data[1] = 0;
6251 data[3] = 0;
6252 data[4] = 0;
6253 }
6254}
6255
6256static void s2io_get_ethtool_stats(struct net_device *dev,
6257 struct ethtool_stats *estats,
6258 u64 * tmp_stats)
6259{
8116f3cf 6260 int i = 0, k;
1ee6dd77
RB		 6261 struct s2io_nic *sp = dev->priv;
6262 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 6263
7ba013ac 6264 s2io_updt_stats(sp);
541ae68f 6265 tmp_stats[i++] =
6266 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6267 le32_to_cpu(stat_info->tmac_frms);
6268 tmp_stats[i++] =
6269 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6270 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 6271 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f 6272 tmp_stats[i++] =
6273 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6274 le32_to_cpu(stat_info->tmac_mcst_frms);
6275 tmp_stats[i++] =
6276 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6277 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 6278 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 6279 tmp_stats[i++] =
6280 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6281 le32_to_cpu(stat_info->tmac_ttl_octets);
6282 tmp_stats[i++] =
6283 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6284 le32_to_cpu(stat_info->tmac_ucst_frms);
6285 tmp_stats[i++] =
6286 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6287 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f 6288 tmp_stats[i++] =
6289 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6290 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 6291 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 6292 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f 6293 tmp_stats[i++] =
6294 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6295 le32_to_cpu(stat_info->tmac_vld_ip);
6296 tmp_stats[i++] =
6297 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6298 le32_to_cpu(stat_info->tmac_drop_ip);
6299 tmp_stats[i++] =
6300 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6301 le32_to_cpu(stat_info->tmac_icmp);
6302 tmp_stats[i++] =
6303 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6304 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 6305 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f 6306 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6307 le32_to_cpu(stat_info->tmac_udp);
6308 tmp_stats[i++] =
6309 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6310 le32_to_cpu(stat_info->rmac_vld_frms);
6311 tmp_stats[i++] =
6312 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6313 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 6314 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6315 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f 6316 tmp_stats[i++] =
6317 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6318 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6319 tmp_stats[i++] =
6320 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6321 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 6322 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 6323 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 6324 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6325 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 6326 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6327 tmp_stats[i++] =
6328 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6329 le32_to_cpu(stat_info->rmac_ttl_octets);
6330 tmp_stats[i++] =
6331 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6332 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6333 tmp_stats[i++] =
6334 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6335 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f 6336 tmp_stats[i++] =
6337 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6338 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 6339 tmp_stats[i++] =
6340 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6341 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6342 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6343 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f 6344 tmp_stats[i++] =
6345 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6346 le32_to_cpu(stat_info->rmac_usized_frms);
6347 tmp_stats[i++] =
6348 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6349 le32_to_cpu(stat_info->rmac_osized_frms);
6350 tmp_stats[i++] =
6351 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6352 le32_to_cpu(stat_info->rmac_frag_frms);
6353 tmp_stats[i++] =
6354 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6355 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 6356 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6357 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6358 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6359 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6360 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6361 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6362 tmp_stats[i++] =
6363 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 6364 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 6365 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6366 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 6367 tmp_stats[i++] =
6368 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 6369 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 6370 tmp_stats[i++] =
6371 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 6372 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 6373 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 6374 tmp_stats[i++] =
6375 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f 6376 le32_to_cpu(stat_info->rmac_udp);
6377 tmp_stats[i++] =
6378 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6379 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 6380 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6381 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6382 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6383 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6384 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6385 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6386 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6387 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6388 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6389 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6390 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6391 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6392 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6393 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6394 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6395 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6396 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f 6397 tmp_stats[i++] =
6398 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6399 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 6400 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6401 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f 6402 tmp_stats[i++] =
6403 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6404 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 6405 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 6406 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6407 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6408 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6409 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6410 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6411 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6412 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6413 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6414 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6415 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6416 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6417 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6418 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6419 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6420 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6421 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6422 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6423 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 6424
6425 /* Enhanced statistics exist only for Hercules */
6426 if(sp->device_type == XFRAME_II_DEVICE) {
6427 tmp_stats[i++] =
6428 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6429 tmp_stats[i++] =
6430 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6431 tmp_stats[i++] =
6432 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6433 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6434 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6435 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6436 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6437 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6438 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6439 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6440 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6441 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6442 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6443 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6444 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6445 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6446 }
6447
7ba013ac 6448 tmp_stats[i++] = 0;
6449 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6450 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 6451 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6452 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6453 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6454 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
8116f3cf
SS		 6455 for (k = 0; k < MAX_RX_RINGS; k++)
6456 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
bd1034f0
AR		 6457 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6458 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6459 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6460 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6461 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6462 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6463 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6464 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6465 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6466 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6467 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6468 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 6469 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6470 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6471 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6472 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 6473 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 6474 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6475 int count = 0;
6aa20a22 6476 /*
bd1034f0
AR		 6477 * Since 64-bit divide does not work on all platforms,
6478 * do repeated subtraction.
6479 */
6480 while (tmp >= stat_info->sw_stat.num_aggregations) {
6481 tmp -= stat_info->sw_stat.num_aggregations;
6482 count++;
6483 }
6484 tmp_stats[i++] = count;
fe931395 6485 }
bd1034f0
AR		 6486 else
6487 tmp_stats[i++] = 0;
c53d4945 6488 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
491abf25 6489 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
c53d4945 6490 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 6491 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6492 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6493 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6494 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6495 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6496 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6497
6498 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6499 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6500 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6501 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6502 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6503
6504 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6505 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6506 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6507 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6508 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6509 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6510 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6511 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6512 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
8116f3cf
SS		 6513 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6514 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6515 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6516 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6517 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6518 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6519 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6520 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6521 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6522 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6523 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6524 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6525 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6526 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6527 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6528 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6529 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
1da177e4
LT		 6530}
6531
ac1f60db 6532static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 6533{
6534 return (XENA_REG_SPACE);
6535}
6536
6537
ac1f60db 6538static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 6539{
1ee6dd77 6540 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6541
6542 return (sp->rx_csum);
6543}
ac1f60db
AB		 6544
6545static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6546{
1ee6dd77 6547 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6548
6549 if (data)
6550 sp->rx_csum = 1;
6551 else
6552 sp->rx_csum = 0;
6553
6554 return 0;
6555}
ac1f60db
AB		 6556
6557static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 6558{
6559 return (XENA_EEPROM_SPACE);
6560}
6561
b9f2c044 6562static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6563{
b9f2c044
JG		 6564 struct s2io_nic *sp = dev->priv;
6565
6566 switch (sset) {
6567 case ETH_SS_TEST:
6568 return S2IO_TEST_LEN;
6569 case ETH_SS_STATS:
6570 switch(sp->device_type) {
6571 case XFRAME_I_DEVICE:
6572 return XFRAME_I_STAT_LEN;
6573 case XFRAME_II_DEVICE:
6574 return XFRAME_II_STAT_LEN;
6575 default:
6576 return 0;
6577 }
6578 default:
6579 return -EOPNOTSUPP;
6580 }
1da177e4 6581}
ac1f60db
AB		 6582
6583static void s2io_ethtool_get_strings(struct net_device *dev,
6584 u32 stringset, u8 * data)
1da177e4 6585{
fa1f0cb3
SS		 6586 int stat_size = 0;
6587 struct s2io_nic *sp = dev->priv;
6588
1da177e4
LT		 6589 switch (stringset) {
6590 case ETH_SS_TEST:
6591 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6592 break;
6593 case ETH_SS_STATS:
fa1f0cb3
SS		 6594 stat_size = sizeof(ethtool_xena_stats_keys);
6595 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6596 if(sp->device_type == XFRAME_II_DEVICE) {
6597 memcpy(data + stat_size,
6598 &ethtool_enhanced_stats_keys,
6599 sizeof(ethtool_enhanced_stats_keys));
6600 stat_size += sizeof(ethtool_enhanced_stats_keys);
6601 }
6602
6603 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6604 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6605 }
6606}
1da177e4 6607
ac1f60db 6608static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6609{
6610 if (data)
6611 dev->features |= NETIF_F_IP_CSUM;
6612 else
6613 dev->features &= ~NETIF_F_IP_CSUM;
6614
6615 return 0;
6616}
6617
75c30b13
AR		 6618static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6619{
6620 return (dev->features & NETIF_F_TSO) != 0;
6621}
6622static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6623{
6624 if (data)
6625 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6626 else
6627 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6628
6629 return 0;
6630}
1da177e4 6631
7282d491 6632static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6633 .get_settings = s2io_ethtool_gset,
6634 .set_settings = s2io_ethtool_sset,
6635 .get_drvinfo = s2io_ethtool_gdrvinfo,
6636 .get_regs_len = s2io_ethtool_get_regs_len,
6637 .get_regs = s2io_ethtool_gregs,
6638 .get_link = ethtool_op_get_link,
6639 .get_eeprom_len = s2io_get_eeprom_len,
6640 .get_eeprom = s2io_ethtool_geeprom,
6641 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6642 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6643 .get_pauseparam = s2io_ethtool_getpause_data,
6644 .set_pauseparam = s2io_ethtool_setpause_data,
6645 .get_rx_csum = s2io_ethtool_get_rx_csum,
6646 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6647 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6648 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6649 .get_tso = s2io_ethtool_op_get_tso,
6650 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6651 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6652 .self_test = s2io_ethtool_test,
6653 .get_strings = s2io_ethtool_get_strings,
6654 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6655 .get_ethtool_stats = s2io_get_ethtool_stats,
6656 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6657};
6658
6659/**
20346722 6660 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6661 * @dev : Device pointer.
6662 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6663 * a proprietary structure used to pass information to the driver.
6664 * @cmd : This is used to distinguish between the different commands that
6665 * can be passed to the IOCTL functions.
6666 * Description:
20346722 6667 * Currently there are no special functionality supported in IOCTL, hence
6668 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6669 */
6670
ac1f60db 6671static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6672{
6673 return -EOPNOTSUPP;
6674}
6675
6676/**
6677 * s2io_change_mtu - entry point to change MTU size for the device.
6678 * @dev : device pointer.
6679 * @new_mtu : the new MTU size for the device.
6680 * Description: A driver entry point to change MTU size for the device.
6681 * Before changing the MTU the device must be stopped.
6682 * Return value:
6683 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6684 * file on failure.
6685 */
6686
ac1f60db 6687static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6688{
1ee6dd77 6689 struct s2io_nic *sp = dev->priv;
9f74ffde 6690 int ret = 0;
1da177e4
LT		 6691
6692 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6693 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6694 dev->name);
6695 return -EPERM;
6696 }
6697
1da177e4 6698 dev->mtu = new_mtu;
d8892c6e 6699 if (netif_running(dev)) {
3a3d5756 6700 s2io_stop_all_tx_queue(sp);
e6a8fee2 6701 s2io_card_down(sp);
9f74ffde
SH		 6702 ret = s2io_card_up(sp);
6703 if (ret) {
d8892c6e 6704 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6705 __FUNCTION__);
9f74ffde 6706 return ret;
d8892c6e 6707 }
3a3d5756 6708 s2io_wake_all_tx_queue(sp);
d8892c6e 6709 } else { /* Device is down */
1ee6dd77 6710 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e 6711 u64 val64 = new_mtu;
6712
6713 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6714 }
1da177e4 6715
9f74ffde 6716 return ret;
1da177e4
LT		 6717}
6718
1da177e4
LT		 6719/**
6720 * s2io_set_link - Set the LInk status
6721 * @data: long pointer to device private structue
6722 * Description: Sets the link status for the adapter
6723 */
6724
c4028958 6725static void s2io_set_link(struct work_struct *work)
1da177e4 6726{
1ee6dd77 6727 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6728 struct net_device *dev = nic->dev;
1ee6dd77 6729 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6730 register u64 val64;
6731 u16 subid;
6732
22747d6b
FR		 6733 rtnl_lock();
6734
6735 if (!netif_running(dev))
6736 goto out_unlock;
6737
92b84437 6738 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6739 /* The card is being reset, no point doing anything */
22747d6b 6740 goto out_unlock;
1da177e4
LT		 6741 }
6742
6743 subid = nic->pdev->subsystem_device;
a371a07d 6744 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6745 /*
6746 * Allow a small delay for the NICs self initiated
6747 * cleanup to complete.
6748 */
6749 msleep(100);
6750 }
1da177e4
LT		 6751
6752 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6753 if (LINK_IS_UP(val64)) {
6754 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6755 if (verify_xena_quiescence(nic)) {
6756 val64 = readq(&bar0->adapter_control);
6757 val64 |= ADAPTER_CNTL_EN;
1da177e4 6758 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6759 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6760 nic->device_type, subid)) {
6761 val64 = readq(&bar0->gpio_control);
6762 val64 |= GPIO_CTRL_GPIO_0;
6763 writeq(val64, &bar0->gpio_control);
6764 val64 = readq(&bar0->gpio_control);
6765 } else {
6766 val64 |= ADAPTER_LED_ON;
6767 writeq(val64, &bar0->adapter_control);
a371a07d 6768 }
1da177e4 6769 nic->device_enabled_once = TRUE;
19a60522
SS		 6770 } else {
6771 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6772 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
3a3d5756 6773 s2io_stop_all_tx_queue(nic);
1da177e4 6774 }
19a60522 6775 }
92c48799
SS		 6776 val64 = readq(&bar0->adapter_control);
6777 val64 |= ADAPTER_LED_ON;
6778 writeq(val64, &bar0->adapter_control);
6779 s2io_link(nic, LINK_UP);
19a60522
SS		 6780 } else {
6781 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6782 subid)) {
6783 val64 = readq(&bar0->gpio_control);
6784 val64 &= ~GPIO_CTRL_GPIO_0;
6785 writeq(val64, &bar0->gpio_control);
6786 val64 = readq(&bar0->gpio_control);
1da177e4 6787 }
92c48799
SS		 6788 /* turn off LED */
6789 val64 = readq(&bar0->adapter_control);
6790 val64 = val64 &(~ADAPTER_LED_ON);
6791 writeq(val64, &bar0->adapter_control);
19a60522 6792 s2io_link(nic, LINK_DOWN);
1da177e4 6793 }
92b84437 6794 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6795
6796out_unlock:
d8d70caf 6797 rtnl_unlock();
1da177e4
LT		 6798}
6799
1ee6dd77
RB		 6800static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6801 struct buffAdd *ba,
6802 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6803 u64 *temp2, int size)
5d3213cc
AR		 6804{
6805 struct net_device *dev = sp->dev;
491abf25 6806 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6807
6808 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6809 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6810 /* allocate skb */
6811 if (*skb) {
6812 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6813 /*
6814 * As Rx frame are not going to be processed,
6815 * using same mapped address for the Rxd
6816 * buffer pointer
6817 */
6d517a27 6818 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6819 } else {
6820 *skb = dev_alloc_skb(size);
6821 if (!(*skb)) {
0c61ed5f 6822 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6823 DBG_PRINT(INFO_DBG, "memory to allocate ");
6824 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6825 sp->mac_control.stats_info->sw_stat. \
6826 mem_alloc_fail_cnt++;
5d3213cc
AR		 6827 return -ENOMEM ;
6828 }
8a4bdbaa 6829 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6830 += (*skb)->truesize;
5d3213cc
AR		 6831 /* storing the mapped addr in a temp variable
6832 * such it will be used for next rxd whose
6833 * Host Control is NULL
6834 */
6d517a27 6835 rxdp1->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6836 pci_map_single( sp->pdev, (*skb)->data,
6837 size - NET_IP_ALIGN,
6838 PCI_DMA_FROMDEVICE);
491abf25
VP		 6839 if( (rxdp1->Buffer0_ptr == 0) ||
6840 (rxdp1->Buffer0_ptr == DMA_ERROR_CODE)) {
6841 goto memalloc_failed;
6842 }
5d3213cc
AR		 6843 rxdp->Host_Control = (unsigned long) (*skb);
6844 }
6845 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6846 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6847 /* Two buffer Mode */
6848 if (*skb) {
6d517a27
VP		 6849 rxdp3->Buffer2_ptr = *temp2;
6850 rxdp3->Buffer0_ptr = *temp0;
6851 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6852 } else {
6853 *skb = dev_alloc_skb(size);
2ceaac75 6854 if (!(*skb)) {
c53d4945
SH		 6855 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6856 DBG_PRINT(INFO_DBG, "memory to allocate ");
6857 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6858 sp->mac_control.stats_info->sw_stat. \
6859 mem_alloc_fail_cnt++;
2ceaac75
DR		 6860 return -ENOMEM;
6861 }
8a4bdbaa 6862 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6863 += (*skb)->truesize;
6d517a27 6864 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6865 pci_map_single(sp->pdev, (*skb)->data,
6866 dev->mtu + 4,
6867 PCI_DMA_FROMDEVICE);
491abf25
VP		 6868 if( (rxdp3->Buffer2_ptr == 0) ||
6869 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE)) {
6870 goto memalloc_failed;
6871 }
6d517a27 6872 rxdp3->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6873 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6874 PCI_DMA_FROMDEVICE);
491abf25
VP		 6875 if( (rxdp3->Buffer0_ptr == 0) ||
6876 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE)) {
6877 pci_unmap_single (sp->pdev,
3e847423 6878 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6879 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6880 goto memalloc_failed;
6881 }
5d3213cc
AR		 6882 rxdp->Host_Control = (unsigned long) (*skb);
6883
6884 /* Buffer-1 will be dummy buffer not used */
6d517a27 6885 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6886 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5d3213cc 6887 PCI_DMA_FROMDEVICE);
491abf25
VP		 6888 if( (rxdp3->Buffer1_ptr == 0) ||
6889 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
6890 pci_unmap_single (sp->pdev,
3e847423
AV		 6891 (dma_addr_t)rxdp3->Buffer0_ptr,
6892 BUF0_LEN, PCI_DMA_FROMDEVICE);
6893 pci_unmap_single (sp->pdev,
6894 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6895 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6896 goto memalloc_failed;
6897 }
5d3213cc
AR		 6898 }
6899 }
6900 return 0;
491abf25
VP		 6901 memalloc_failed:
6902 stats->pci_map_fail_cnt++;
6903 stats->mem_freed += (*skb)->truesize;
6904 dev_kfree_skb(*skb);
6905 return -ENOMEM;
5d3213cc 6906}
491abf25 6907
1ee6dd77
RB		 6908static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6909 int size)
5d3213cc
AR		 6910{
6911 struct net_device *dev = sp->dev;
6912 if (sp->rxd_mode == RXD_MODE_1) {
6913 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6914 } else if (sp->rxd_mode == RXD_MODE_3B) {
6915 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6916 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6917 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
5d3213cc
AR		 6918 }
6919}
6920
1ee6dd77 6921static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6922{
6923 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6924 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6925 struct config_param *config = &sp->config;
6926 struct net_device *dev = sp->dev;
1ee6dd77 6927 struct RxD_t *rxdp = NULL;
5d3213cc 6928 struct sk_buff *skb = NULL;
1ee6dd77 6929 struct buffAdd *ba = NULL;
5d3213cc
AR		 6930 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6931
6932 /* Calculate the size based on ring mode */
6933 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6934 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6935 if (sp->rxd_mode == RXD_MODE_1)
6936 size += NET_IP_ALIGN;
6937 else if (sp->rxd_mode == RXD_MODE_3B)
6938 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6939
6940 for (i = 0; i < config->rx_ring_num; i++) {
6941 blk_cnt = config->rx_cfg[i].num_rxd /
6942 (rxd_count[sp->rxd_mode] +1);
6943
6944 for (j = 0; j < blk_cnt; j++) {
6945 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6946 rxdp = mac_control->rings[i].
6947 rx_blocks[j].rxds[k].virt_addr;
6d517a27 6948 if(sp->rxd_mode == RXD_MODE_3B)
5d3213cc 6949 ba = &mac_control->rings[i].ba[j][k];
ac1f90d6 6950 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 6951 &skb,(u64 *)&temp0_64,
6952 (u64 *)&temp1_64,
ac1f90d6
SS		 6953 (u64 *)&temp2_64,
6954 size) == ENOMEM) {
6955 return 0;
6956 }
5d3213cc
AR		 6957
6958 set_rxd_buffer_size(sp, rxdp, size);
6959 wmb();
6960 /* flip the Ownership bit to Hardware */
6961 rxdp->Control_1 |= RXD_OWN_XENA;
6962 }
6963 }
6964 }
6965 return 0;
6966
6967}
6968
1ee6dd77 6969static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 6970{
e6a8fee2 6971 int ret = 0;
c92ca04b 6972 struct net_device *dev = sp->dev;
e6a8fee2 6973 int err = 0;
1da177e4 6974
eaae7f72 6975 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 6976 ret = s2io_enable_msi_x(sp);
6977 if (ret) {
6978 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 6979 sp->config.intr_type = INTA;
20346722 6980 }
1da177e4 6981
1ee6dd77 6982 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 6983 store_xmsi_data(sp);
c92ca04b 6984
e6a8fee2 6985 /* After proper initialization of H/W, register ISR */
eaae7f72 6986 if (sp->config.intr_type == MSI_X) {
fb6a825b 6987 int i, msix_tx_cnt=0,msix_rx_cnt=0;
c92ca04b 6988
e6a8fee2
AR		 6989 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6990 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6991 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6992 dev->name, i);
6993 err = request_irq(sp->entries[i].vector,
6994 s2io_msix_fifo_handle, 0, sp->desc[i],
6995 sp->s2io_entries[i].arg);
fb6a825b
SS		 6996 /* If either data or addr is zero print it */
6997 if(!(sp->msix_info[i].addr &&
6998 sp->msix_info[i].data)) {
2450022a 6999 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx "
3459feb8 7000 "Data:0x%llx\n",sp->desc[i],
fb6a825b
SS		 7001 (unsigned long long)
7002 sp->msix_info[i].addr,
3459feb8
AV		 7003 (unsigned long long)
7004 sp->msix_info[i].data);
fb6a825b
SS		 7005 } else {
7006 msix_tx_cnt++;
7007 }
e6a8fee2
AR		 7008 } else {
7009 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7010 dev->name, i);
7011 err = request_irq(sp->entries[i].vector,
7012 s2io_msix_ring_handle, 0, sp->desc[i],
7013 sp->s2io_entries[i].arg);
fb6a825b
SS		 7014 /* If either data or addr is zero print it */
7015 if(!(sp->msix_info[i].addr &&
7016 sp->msix_info[i].data)) {
2450022a 7017 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx "
3459feb8 7018 "Data:0x%llx\n",sp->desc[i],
fb6a825b
SS		 7019 (unsigned long long)
7020 sp->msix_info[i].addr,
3459feb8
AV		 7021 (unsigned long long)
7022 sp->msix_info[i].data);
fb6a825b
SS		 7023 } else {
7024 msix_rx_cnt++;
7025 }
c92ca04b 7026 }
e6a8fee2 7027 if (err) {
18b2b7bd 7028 remove_msix_isr(sp);
e6a8fee2
AR		 7029 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
7030 "failed\n", dev->name, i);
18b2b7bd
SH		 7031 DBG_PRINT(ERR_DBG, "%s: defaulting to INTA\n",
7032 dev->name);
7033 sp->config.intr_type = INTA;
7034 break;
e6a8fee2
AR		 7035 }
7036 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
7037 }
18b2b7bd
SH		 7038 if (!err) {
7039 printk(KERN_INFO "MSI-X-TX %d entries enabled\n",
7040 msix_tx_cnt);
7041 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
7042 msix_rx_cnt);
7043 }
e6a8fee2 7044 }
eaae7f72 7045 if (sp->config.intr_type == INTA) {
e6a8fee2
AR		 7046 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
7047 sp->name, dev);
7048 if (err) {
7049 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7050 dev->name);
7051 return -1;
7052 }
7053 }
7054 return 0;
7055}
1ee6dd77 7056static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2 7057{
18b2b7bd
SH		 7058 if (sp->config.intr_type == MSI_X)
7059 remove_msix_isr(sp);
7060 else
7061 remove_inta_isr(sp);
e6a8fee2
AR		 7062}
7063
d796fdb7 7064static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 7065{
7066 int cnt = 0;
1ee6dd77 7067 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7068 register u64 val64 = 0;
5f490c96
SH		 7069 struct config_param *config;
7070 config = &sp->config;
e6a8fee2 7071
9f74ffde
SH		 7072 if (!is_s2io_card_up(sp))
7073 return;
7074
e6a8fee2
AR		 7075 del_timer_sync(&sp->alarm_timer);
7076 /* If s2io_set_link task is executing, wait till it completes. */
92b84437 7077 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
e6a8fee2
AR		 7078 msleep(50);
7079 }
92b84437 7080 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7081
5f490c96
SH		 7082 /* Disable napi */
7083 if (config->napi)
7084 napi_disable(&sp->napi);
7085
e6a8fee2 7086 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7087 if (do_io)
7088 stop_nic(sp);
e6a8fee2
AR		 7089
7090 s2io_rem_isr(sp);
1da177e4 7091
1da177e4 7092 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 7093 while(do_io) {
5d3213cc
AR		 7094 /* As per the HW requirement we need to replenish the
7095 * receive buffer to avoid the ring bump. Since there is
7096 * no intention of processing the Rx frame at this pointwe are
7097 * just settting the ownership bit of rxd in Each Rx
7098 * ring to HW and set the appropriate buffer size
7099 * based on the ring mode
7100 */
7101 rxd_owner_bit_reset(sp);
7102
1da177e4 7103 val64 = readq(&bar0->adapter_status);
19a60522
SS		 7104 if (verify_xena_quiescence(sp)) {
7105 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 7106 break;
7107 }
7108
7109 msleep(50);
7110 cnt++;
7111 if (cnt == 10) {
7112 DBG_PRINT(ERR_DBG,
7113 "s2io_close:Device not Quiescent ");
7114 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7115 (unsigned long long) val64);
7116 break;
7117 }
d796fdb7
LV		 7118 }
7119 if (do_io)
7120 s2io_reset(sp);
1da177e4 7121
7ba013ac 7122 /* Free all Tx buffers */
1da177e4 7123 free_tx_buffers(sp);
7ba013ac 7124
7125 /* Free all Rx buffers */
1da177e4
LT		 7126 free_rx_buffers(sp);
7127
92b84437 7128 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7129}
7130
d796fdb7
LV		 7131static void s2io_card_down(struct s2io_nic * sp)
7132{
7133 do_s2io_card_down(sp, 1);
7134}
7135
1ee6dd77 7136static int s2io_card_up(struct s2io_nic * sp)
1da177e4 7137{
cc6e7c44 7138 int i, ret = 0;
1ee6dd77 7139 struct mac_info *mac_control;
1da177e4
LT		 7140 struct config_param *config;
7141 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 7142 u16 interruptible;
1da177e4
LT		 7143
7144 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7145 ret = init_nic(sp);
7146 if (ret != 0) {
1da177e4
LT		 7147 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7148 dev->name);
9f74ffde
SH		 7149 if (ret != -EIO)
7150 s2io_reset(sp);
7151 return ret;
1da177e4
LT		 7152 }
7153
20346722 7154 /*
7155 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7156 * Rx ring and initializing buffers into 30 Rx blocks
7157 */
7158 mac_control = &sp->mac_control;
7159 config = &sp->config;
7160
7161 for (i = 0; i < config->rx_ring_num; i++) {
0425b46a
SH		 7162 mac_control->rings[i].mtu = dev->mtu;
7163 ret = fill_rx_buffers(&mac_control->rings[i]);
7164 if (ret) {
1da177e4
LT		 7165 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7166 dev->name);
7167 s2io_reset(sp);
7168 free_rx_buffers(sp);
7169 return -ENOMEM;
7170 }
7171 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
0425b46a 7172 mac_control->rings[i].rx_bufs_left);
1da177e4 7173 }
5f490c96
SH		 7174
7175 /* Initialise napi */
7176 if (config->napi)
7177 napi_enable(&sp->napi);
7178
19a60522
SS		 7179 /* Maintain the state prior to the open */
7180 if (sp->promisc_flg)
7181 sp->promisc_flg = 0;
7182 if (sp->m_cast_flg) {
7183 sp->m_cast_flg = 0;
7184 sp->all_multi_pos= 0;
7185 }
1da177e4
LT		 7186
7187 /* Setting its receive mode */
7188 s2io_set_multicast(dev);
7189
7d3d0439 7190 if (sp->lro) {
b41477f3 7191 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 7192 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7193 /* Check if we can use(if specified) user provided value */
7194 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7195 sp->lro_max_aggr_per_sess = lro_max_pkts;
7196 }
7197
1da177e4
LT		 7198 /* Enable Rx Traffic and interrupts on the NIC */
7199 if (start_nic(sp)) {
7200 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7201 s2io_reset(sp);
e6a8fee2
AR		 7202 free_rx_buffers(sp);
7203 return -ENODEV;
7204 }
7205
7206 /* Add interrupt service routine */
7207 if (s2io_add_isr(sp) != 0) {
eaae7f72 7208 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7209 s2io_rem_isr(sp);
7210 s2io_reset(sp);
1da177e4
LT		 7211 free_rx_buffers(sp);
7212 return -ENODEV;
7213 }
7214
25fff88e 7215 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7216
e6a8fee2 7217 /* Enable select interrupts */
9caab458 7218 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
eaae7f72 7219 if (sp->config.intr_type != INTA)
e6a8fee2
AR		 7220 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
7221 else {
7222 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7223 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7224 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7225 }
7226
92b84437 7227 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
1da177e4
LT		 7228 return 0;
7229}
7230
20346722 7231/**
1da177e4
LT		 7232 * s2io_restart_nic - Resets the NIC.
7233 * @data : long pointer to the device private structure
7234 * Description:
7235 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7236 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7237 * the run time of the watch dog routine which is run holding a
7238 * spin lock.
7239 */
7240
c4028958 7241static void s2io_restart_nic(struct work_struct *work)
1da177e4 7242{
1ee6dd77 7243 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7244 struct net_device *dev = sp->dev;
1da177e4 7245
22747d6b
FR		 7246 rtnl_lock();
7247
7248 if (!netif_running(dev))
7249 goto out_unlock;
7250
e6a8fee2 7251 s2io_card_down(sp);
1da177e4
LT		 7252 if (s2io_card_up(sp)) {
7253 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7254 dev->name);
7255 }
3a3d5756 7256 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7257 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7258 dev->name);
22747d6b
FR		 7259out_unlock:
7260 rtnl_unlock();
1da177e4
LT		 7261}
7262
20346722 7263/**
7264 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7265 * @dev : Pointer to net device structure
7266 * Description:
7267 * This function is triggered if the Tx Queue is stopped
7268 * for a pre-defined amount of time when the Interface is still up.
7269 * If the Interface is jammed in such a situation, the hardware is
7270 * reset (by s2io_close) and restarted again (by s2io_open) to
7271 * overcome any problem that might have been caused in the hardware.
7272 * Return value:
7273 * void
7274 */
7275
7276static void s2io_tx_watchdog(struct net_device *dev)
7277{
1ee6dd77 7278 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 7279
7280 if (netif_carrier_ok(dev)) {
c53d4945 7281 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 7282 schedule_work(&sp->rst_timer_task);
bd1034f0 7283 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 7284 }
7285}
7286
7287/**
7288 * rx_osm_handler - To perform some OS related operations on SKB.
7289 * @sp: private member of the device structure,pointer to s2io_nic structure.
7290 * @skb : the socket buffer pointer.
7291 * @len : length of the packet
7292 * @cksum : FCS checksum of the frame.
7293 * @ring_no : the ring from which this RxD was extracted.
20346722 7294 * Description:
b41477f3 7295 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7296 * some OS related operations on the SKB before passing it to the upper
7297 * layers. It mainly checks if the checksum is OK, if so adds it to the
7298 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7299 * to the upper layer. If the checksum is wrong, it increments the Rx
7300 * packet error count, frees the SKB and returns error.
7301 * Return value:
7302 * SUCCESS on success and -1 on failure.
7303 */
1ee6dd77 7304static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7305{
1ee6dd77 7306 struct s2io_nic *sp = ring_data->nic;
0425b46a 7307 struct net_device *dev = (struct net_device *) ring_data->dev;
20346722 7308 struct sk_buff *skb = (struct sk_buff *)
7309 ((unsigned long) rxdp->Host_Control);
7310 int ring_no = ring_data->ring_no;
1da177e4 7311 u16 l3_csum, l4_csum;
863c11a9 7312 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
1ee6dd77 7313 struct lro *lro;
f9046eb3 7314 u8 err_mask;
da6971d8 7315
20346722 7316 skb->dev = dev;
c92ca04b 7317
863c11a9 7318 if (err) {
bd1034f0
AR		 7319 /* Check for parity error */
7320 if (err & 0x1) {
7321 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7322 }
f9046eb3
OH		 7323 err_mask = err >> 48;
7324 switch(err_mask) {
491976b2
SH		 7325 case 1:
7326 sp->mac_control.stats_info->sw_stat.
7327 rx_parity_err_cnt++;
7328 break;
7329
7330 case 2:
7331 sp->mac_control.stats_info->sw_stat.
7332 rx_abort_cnt++;
7333 break;
7334
7335 case 3:
7336 sp->mac_control.stats_info->sw_stat.
7337 rx_parity_abort_cnt++;
7338 break;
7339
7340 case 4:
7341 sp->mac_control.stats_info->sw_stat.
7342 rx_rda_fail_cnt++;
7343 break;
7344
7345 case 5:
7346 sp->mac_control.stats_info->sw_stat.
7347 rx_unkn_prot_cnt++;
7348 break;
7349
7350 case 6:
7351 sp->mac_control.stats_info->sw_stat.
7352 rx_fcs_err_cnt++;
7353 break;
bd1034f0 7354
491976b2
SH		 7355 case 7:
7356 sp->mac_control.stats_info->sw_stat.
7357 rx_buf_size_err_cnt++;
7358 break;
7359
7360 case 8:
7361 sp->mac_control.stats_info->sw_stat.
7362 rx_rxd_corrupt_cnt++;
7363 break;
7364
7365 case 15:
7366 sp->mac_control.stats_info->sw_stat.
7367 rx_unkn_err_cnt++;
7368 break;
7369 }
863c11a9
AR		 7370 /*
7371 * Drop the packet if bad transfer code. Exception being
7372 * 0x5, which could be due to unsupported IPv6 extension header.
7373 * In this case, we let stack handle the packet.
7374 * Note that in this case, since checksum will be incorrect,
7375 * stack will validate the same.
7376 */
f9046eb3
OH		 7377 if (err_mask != 0x5) {
7378 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7379 dev->name, err_mask);
863c11a9 7380 sp->stats.rx_crc_errors++;
8a4bdbaa 7381 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2 7382 += skb->truesize;
863c11a9 7383 dev_kfree_skb(skb);
0425b46a 7384 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7385 rxdp->Host_Control = 0;
7386 return 0;
7387 }
20346722 7388 }
1da177e4 7389
20346722 7390 /* Updating statistics */
0425b46a 7391 ring_data->rx_packets++;
20346722 7392 rxdp->Host_Control = 0;
da6971d8
AR		 7393 if (sp->rxd_mode == RXD_MODE_1) {
7394 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7395
0425b46a 7396 ring_data->rx_bytes += len;
da6971d8
AR		 7397 skb_put(skb, len);
7398
6d517a27 7399 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7400 int get_block = ring_data->rx_curr_get_info.block_index;
7401 int get_off = ring_data->rx_curr_get_info.offset;
7402 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7403 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7404 unsigned char *buff = skb_push(skb, buf0_len);
7405
1ee6dd77 7406 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
0425b46a 7407 ring_data->rx_bytes += buf0_len + buf2_len;
da6971d8 7408 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7409 skb_put(skb, buf2_len);
da6971d8 7410 }
20346722 7411
0425b46a
SH		 7412 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!ring_data->lro) ||
7413 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722 7414 (sp->rx_csum)) {
7415 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7416 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7417 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7418 /*
1da177e4
LT		 7419 * NIC verifies if the Checksum of the received
7420 * frame is Ok or not and accordingly returns
7421 * a flag in the RxD.
7422 */
7423 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7424 if (ring_data->lro) {
7d3d0439
RA		 7425 u32 tcp_len;
7426 u8 *tcp;
7427 int ret = 0;
7428
0425b46a
SH		 7429 ret = s2io_club_tcp_session(ring_data,
7430 skb->data, &tcp, &tcp_len, &lro,
7431 rxdp, sp);
7d3d0439
RA		 7432 switch (ret) {
7433 case 3: /* Begin anew */
7434 lro->parent = skb;
7435 goto aggregate;
7436 case 1: /* Aggregate */
7437 {
7438 lro_append_pkt(sp, lro,
7439 skb, tcp_len);
7440 goto aggregate;
7441 }
7442 case 4: /* Flush session */
7443 {
7444 lro_append_pkt(sp, lro,
7445 skb, tcp_len);
cdb5bf02
SH		 7446 queue_rx_frame(lro->parent,
7447 lro->vlan_tag);
7d3d0439
RA		 7448 clear_lro_session(lro);
7449 sp->mac_control.stats_info->
7450 sw_stat.flush_max_pkts++;
7451 goto aggregate;
7452 }
7453 case 2: /* Flush both */
7454 lro->parent->data_len =
7455 lro->frags_len;
7456 sp->mac_control.stats_info->
7457 sw_stat.sending_both++;
cdb5bf02
SH		 7458 queue_rx_frame(lro->parent,
7459 lro->vlan_tag);
7d3d0439
RA		 7460 clear_lro_session(lro);
7461 goto send_up;
7462 case 0: /* sessions exceeded */
c92ca04b
AR		 7463 case -1: /* non-TCP or not
7464 * L2 aggregatable
7465 */
7d3d0439
RA		 7466 case 5: /*
7467 * First pkt in session not
7468 * L3/L4 aggregatable
7469 */
7470 break;
7471 default:
7472 DBG_PRINT(ERR_DBG,
7473 "%s: Samadhana!!\n",
7474 __FUNCTION__);
7475 BUG();
7476 }
7477 }
1da177e4 7478 } else {
20346722 7479 /*
7480 * Packet with erroneous checksum, let the
1da177e4
LT		 7481 * upper layers deal with it.
7482 */
7483 skb->ip_summed = CHECKSUM_NONE;
7484 }
cdb5bf02 7485 } else
1da177e4 7486 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7487
491976b2 7488 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439 7489send_up:
cdb5bf02 7490 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
1da177e4 7491 dev->last_rx = jiffies;
7d3d0439 7492aggregate:
0425b46a 7493 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7494 return SUCCESS;
7495}
7496
7497/**
7498 * s2io_link - stops/starts the Tx queue.
7499 * @sp : private member of the device structure, which is a pointer to the
7500 * s2io_nic structure.
7501 * @link : inidicates whether link is UP/DOWN.
7502 * Description:
7503 * This function stops/starts the Tx queue depending on whether the link
20346722 7504 * status of the NIC is is down or up. This is called by the Alarm
7505 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7506 * Return value:
7507 * void.
7508 */
7509
1ee6dd77 7510static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 7511{
7512 struct net_device *dev = (struct net_device *) sp->dev;
7513
7514 if (link != sp->last_link_state) {
b7c5678f 7515 init_tti(sp, link);
1da177e4
LT		 7516 if (link == LINK_DOWN) {
7517 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7518 s2io_stop_all_tx_queue(sp);
1da177e4 7519 netif_carrier_off(dev);
491976b2 7520 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
8a4bdbaa 7521 sp->mac_control.stats_info->sw_stat.link_up_time =
491976b2
SH		 7522 jiffies - sp->start_time;
7523 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 7524 } else {
7525 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2 7526 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
8a4bdbaa 7527 sp->mac_control.stats_info->sw_stat.link_down_time =
491976b2
SH		 7528 jiffies - sp->start_time;
7529 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4 7530 netif_carrier_on(dev);
3a3d5756 7531 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7532 }
7533 }
7534 sp->last_link_state = link;
491976b2 7535 sp->start_time = jiffies;
1da177e4
LT		 7536}
7537
20346722 7538/**
7539 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7540 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7541 * s2io_nic structure.
7542 * Description:
7543 * This function initializes a few of the PCI and PCI-X configuration registers
7544 * with recommended values.
7545 * Return value:
7546 * void
7547 */
7548
1ee6dd77 7549static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 7550{
20346722 7551 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7552
7553 /* Enable Data Parity Error Recovery in PCI-X command register. */
7554 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7555 &(pcix_cmd));
1da177e4 7556 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7557 (pcix_cmd | 1));
1da177e4 7558 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7559 &(pcix_cmd));
1da177e4
LT		 7560
7561 /* Set the PErr Response bit in PCI command register. */
7562 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7563 pci_write_config_word(sp->pdev, PCI_COMMAND,
7564 (pci_cmd | PCI_COMMAND_PARITY));
7565 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7566}
7567
3a3d5756
SH		 7568static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7569 u8 *dev_multiq)
9dc737a7 7570{
2fda096d 7571 if ((tx_fifo_num > MAX_TX_FIFOS) ||
6cfc482b 7572 (tx_fifo_num < 1)) {
2fda096d
SR		 7573 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7574 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7575
7576 if (tx_fifo_num < 1)
7577 tx_fifo_num = 1;
7578 else
7579 tx_fifo_num = MAX_TX_FIFOS;
7580
2fda096d
SR		 7581 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7582 DBG_PRINT(ERR_DBG, "tx fifos\n");
9dc737a7 7583 }
2fda096d 7584
3a3d5756
SH		 7585#ifndef CONFIG_NETDEVICES_MULTIQUEUE
7586 if (multiq) {
7587 DBG_PRINT(ERR_DBG, "s2io: Multiqueue support not enabled\n");
7588 multiq = 0;
7589 }
7590#endif
6cfc482b 7591 if (multiq)
3a3d5756 7592 *dev_multiq = multiq;
6cfc482b
SH		 7593
7594 if (tx_steering_type && (1 == tx_fifo_num)) {
7595 if (tx_steering_type != TX_DEFAULT_STEERING)
7596 DBG_PRINT(ERR_DBG,
7597 "s2io: Tx steering is not supported with "
7598 "one fifo. Disabling Tx steering.\n");
7599 tx_steering_type = NO_STEERING;
7600 }
7601
7602 if ((tx_steering_type < NO_STEERING) ||
7603 (tx_steering_type > TX_DEFAULT_STEERING)) {
7604 DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
7605 "supported\n");
7606 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7607 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7608 }
7609
0425b46a
SH		 7610 if (rx_ring_num > MAX_RX_RINGS) {
7611 DBG_PRINT(ERR_DBG, "s2io: Requested number of rx rings not "
9dc737a7 7612 "supported\n");
0425b46a
SH		 7613 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
7614 MAX_RX_RINGS);
7615 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7616 }
0425b46a 7617
db874e65
SS		 7618 if (*dev_intr_type != INTA)
7619 napi = 0;
7620
eccb8628 7621 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 7622 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7623 "Defaulting to INTA\n");
7624 *dev_intr_type = INTA;
7625 }
596c5c97 7626
9dc737a7
AR		 7627 if ((*dev_intr_type == MSI_X) &&
7628 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7629 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7630 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 7631 "Defaulting to INTA\n");
7632 *dev_intr_type = INTA;
7633 }
fb6a825b 7634
6d517a27 7635 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7636 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7637 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7638 rx_ring_mode = 1;
9dc737a7
AR		 7639 }
7640 return SUCCESS;
7641}
7642
9fc93a41
SS		 7643/**
7644 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7645 * or Traffic class respectively.
b7c5678f 7646 * @nic: device private variable
9fc93a41
SS		 7647 * Description: The function configures the receive steering to
7648 * desired receive ring.
7649 * Return Value: SUCCESS on success and
7650 * '-1' on failure (endian settings incorrect).
7651 */
7652static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7653{
7654 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7655 register u64 val64 = 0;
7656
7657 if (ds_codepoint > 63)
7658 return FAILURE;
7659
7660 val64 = RTS_DS_MEM_DATA(ring);
7661 writeq(val64, &bar0->rts_ds_mem_data);
7662
7663 val64 = RTS_DS_MEM_CTRL_WE |
7664 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7665 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7666
7667 writeq(val64, &bar0->rts_ds_mem_ctrl);
7668
7669 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7670 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7671 S2IO_BIT_RESET);
7672}
7673
1da177e4 7674/**
20346722 7675 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7676 * @pdev : structure containing the PCI related information of the device.
7677 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7678 * Description:
7679 * The function initializes an adapter identified by the pci_dec structure.
20346722 7680 * All OS related initialization including memory and device structure and
7681 * initlaization of the device private variable is done. Also the swapper
7682 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7683 * registers of the device.
7684 * Return value:
7685 * returns 0 on success and negative on failure.
7686 */
7687
7688static int __devinit
7689s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7690{
1ee6dd77 7691 struct s2io_nic *sp;
1da177e4 7692 struct net_device *dev;
1da177e4
LT		 7693 int i, j, ret;
7694 int dma_flag = FALSE;
7695 u32 mac_up, mac_down;
7696 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7697 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7698 u16 subid;
1ee6dd77 7699 struct mac_info *mac_control;
1da177e4 7700 struct config_param *config;
541ae68f 7701 int mode;
cc6e7c44 7702 u8 dev_intr_type = intr_type;
3a3d5756 7703 u8 dev_multiq = 0;
0795af57 7704 DECLARE_MAC_BUF(mac);
1da177e4 7705
3a3d5756
SH		 7706 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7707 if (ret)
9dc737a7 7708 return ret;
1da177e4
LT		 7709
7710 if ((ret = pci_enable_device(pdev))) {
7711 DBG_PRINT(ERR_DBG,
7712 "s2io_init_nic: pci_enable_device failed\n");
7713 return ret;
7714 }
7715
1e7f0bd8 7716 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7717 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7718 dma_flag = TRUE;
1da177e4 7719 if (pci_set_consistent_dma_mask
1e7f0bd8 7720 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7721 DBG_PRINT(ERR_DBG,
7722 "Unable to obtain 64bit DMA for \
7723 consistent allocations\n");
7724 pci_disable_device(pdev);
7725 return -ENOMEM;
7726 }
1e7f0bd8 7727 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 7728 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7729 } else {
7730 pci_disable_device(pdev);
7731 return -ENOMEM;
7732 }
eccb8628
VP		 7733 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7734 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7735 pci_disable_device(pdev);
7736 return -ENODEV;
1da177e4 7737 }
3a3d5756
SH		 7738#ifdef CONFIG_NETDEVICES_MULTIQUEUE
7739 if (dev_multiq)
6cfc482b 7740 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756
SH		 7741 else
7742#endif
1ee6dd77 7743 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7744 if (dev == NULL) {
7745 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7746 pci_disable_device(pdev);
7747 pci_release_regions(pdev);
7748 return -ENODEV;
7749 }
7750
7751 pci_set_master(pdev);
7752 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7753 SET_NETDEV_DEV(dev, &pdev->dev);
7754
7755 /* Private member variable initialized to s2io NIC structure */
7756 sp = dev->priv;
1ee6dd77 7757 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7758 sp->dev = dev;
7759 sp->pdev = pdev;
1da177e4 7760 sp->high_dma_flag = dma_flag;
1da177e4 7761 sp->device_enabled_once = FALSE;
da6971d8
AR		 7762 if (rx_ring_mode == 1)
7763 sp->rxd_mode = RXD_MODE_1;
7764 if (rx_ring_mode == 2)
7765 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7766
eaae7f72 7767 sp->config.intr_type = dev_intr_type;
1da177e4 7768
541ae68f 7769 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7770 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7771 sp->device_type = XFRAME_II_DEVICE;
7772 else
7773 sp->device_type = XFRAME_I_DEVICE;
7774
43b7c451 7775 sp->lro = lro_enable;
6aa20a22 7776
1da177e4
LT		 7777 /* Initialize some PCI/PCI-X fields of the NIC. */
7778 s2io_init_pci(sp);
7779
20346722 7780 /*
1da177e4 7781 * Setting the device configuration parameters.
20346722 7782 * Most of these parameters can be specified by the user during
7783 * module insertion as they are module loadable parameters. If
7784 * these parameters are not not specified during load time, they
1da177e4
LT		 7785 * are initialized with default values.
7786 */
7787 mac_control = &sp->mac_control;
7788 config = &sp->config;
7789
596c5c97 7790 config->napi = napi;
6cfc482b 7791 config->tx_steering_type = tx_steering_type;
596c5c97 7792
1da177e4 7793 /* Tx side parameters. */
6cfc482b
SH		 7794 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7795 config->tx_fifo_num = MAX_TX_FIFOS;
7796 else
7797 config->tx_fifo_num = tx_fifo_num;
7798
7799 /* Initialize the fifos used for tx steering */
7800 if (config->tx_fifo_num < 5) {
7801 if (config->tx_fifo_num == 1)
7802 sp->total_tcp_fifos = 1;
7803 else
7804 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7805 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7806 sp->total_udp_fifos = 1;
7807 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7808 } else {
7809 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7810 FIFO_OTHER_MAX_NUM);
7811 sp->udp_fifo_idx = sp->total_tcp_fifos;
7812 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7813 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7814 }
7815
3a3d5756 7816 config->multiq = dev_multiq;
6cfc482b 7817 for (i = 0; i < config->tx_fifo_num; i++) {
1da177e4
LT		 7818 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7819 config->tx_cfg[i].fifo_priority = i;
7820 }
7821
20346722 7822 /* mapping the QoS priority to the configured fifos */
7823 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7824 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7825
6cfc482b
SH		 7826 /* map the hashing selector table to the configured fifos */
7827 for (i = 0; i < config->tx_fifo_num; i++)
7828 sp->fifo_selector[i] = fifo_selector[i];
7829
7830
1da177e4
LT		 7831 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7832 for (i = 0; i < config->tx_fifo_num; i++) {
7833 config->tx_cfg[i].f_no_snoop =
7834 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7835 if (config->tx_cfg[i].fifo_len < 65) {
7836 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7837 break;
7838 }
7839 }
fed5eccd
AR		 7840 /* + 2 because one Txd for skb->data and one Txd for UFO */
7841 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7842
7843 /* Rx side parameters. */
1da177e4 7844 config->rx_ring_num = rx_ring_num;
0425b46a 7845 for (i = 0; i < config->rx_ring_num; i++) {
1da177e4 7846 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 7847 (rxd_count[sp->rxd_mode] + 1);
1da177e4 7848 config->rx_cfg[i].ring_priority = i;
0425b46a
SH		 7849 mac_control->rings[i].rx_bufs_left = 0;
7850 mac_control->rings[i].rxd_mode = sp->rxd_mode;
7851 mac_control->rings[i].rxd_count = rxd_count[sp->rxd_mode];
7852 mac_control->rings[i].pdev = sp->pdev;
7853 mac_control->rings[i].dev = sp->dev;
1da177e4
LT		 7854 }
7855
7856 for (i = 0; i < rx_ring_num; i++) {
7857 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7858 config->rx_cfg[i].f_no_snoop =
7859 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7860 }
7861
7862 /* Setting Mac Control parameters */
7863 mac_control->rmac_pause_time = rmac_pause_time;
7864 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7865 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7866
7867
1da177e4
LT		 7868 /* initialize the shared memory used by the NIC and the host */
7869 if (init_shared_mem(sp)) {
7870 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7871 dev->name);
1da177e4
LT		 7872 ret = -ENOMEM;
7873 goto mem_alloc_failed;
7874 }
7875
7876 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7877 pci_resource_len(pdev, 0));
7878 if (!sp->bar0) {
19a60522 7879 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7880 dev->name);
7881 ret = -ENOMEM;
7882 goto bar0_remap_failed;
7883 }
7884
7885 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7886 pci_resource_len(pdev, 2));
7887 if (!sp->bar1) {
19a60522 7888 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7889 dev->name);
7890 ret = -ENOMEM;
7891 goto bar1_remap_failed;
7892 }
7893
7894 dev->irq = pdev->irq;
7895 dev->base_addr = (unsigned long) sp->bar0;
7896
7897 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7898 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7899 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7900 (sp->bar1 + (j * 0x00020000));
7901 }
7902
7903 /* Driver entry points */
7904 dev->open = &s2io_open;
7905 dev->stop = &s2io_close;
7906 dev->hard_start_xmit = &s2io_xmit;
7907 dev->get_stats = &s2io_get_stats;
7908 dev->set_multicast_list = &s2io_set_multicast;
7909 dev->do_ioctl = &s2io_ioctl;
2fd37688 7910 dev->set_mac_address = &s2io_set_mac_addr;
1da177e4
LT		 7911 dev->change_mtu = &s2io_change_mtu;
7912 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 7913 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7914 dev->vlan_rx_register = s2io_vlan_rx_register;
cdb5bf02 7915 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
20346722 7916
1da177e4
LT		 7917 /*
7918 * will use eth_mac_addr() for dev->set_mac_address
7919 * mac address will be set every time dev->open() is called
7920 */
bea3348e 7921 netif_napi_add(dev, &sp->napi, s2io_poll, 32);
1da177e4 7922
612eff0e
BH		 7923#ifdef CONFIG_NET_POLL_CONTROLLER
7924 dev->poll_controller = s2io_netpoll;
7925#endif
7926
1da177e4
LT		 7927 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7928 if (sp->high_dma_flag == TRUE)
7929 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7930 dev->features |= NETIF_F_TSO;
f83ef8c0 7931 dev->features |= NETIF_F_TSO6;
db874e65 7932 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7933 dev->features |= NETIF_F_UFO;
7934 dev->features |= NETIF_F_HW_CSUM;
7935 }
3a3d5756
SH		 7936#ifdef CONFIG_NETDEVICES_MULTIQUEUE
7937 if (config->multiq)
7938 dev->features |= NETIF_F_MULTI_QUEUE;
7939#endif
1da177e4
LT		 7940 dev->tx_timeout = &s2io_tx_watchdog;
7941 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7942 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7943 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7944
e960fc5c 7945 pci_save_state(sp->pdev);
1da177e4
LT		 7946
7947 /* Setting swapper control on the NIC, for proper reset operation */
7948 if (s2io_set_swapper(sp)) {
7949 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7950 dev->name);
7951 ret = -EAGAIN;
7952 goto set_swap_failed;
7953 }
7954
541ae68f 7955 /* Verify if the Herc works on the slot its placed into */
7956 if (sp->device_type & XFRAME_II_DEVICE) {
7957 mode = s2io_verify_pci_mode(sp);
7958 if (mode < 0) {
7959 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7960 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7961 ret = -EBADSLT;
7962 goto set_swap_failed;
7963 }
7964 }
7965
7966 /* Not needed for Herc */
7967 if (sp->device_type & XFRAME_I_DEVICE) {
7968 /*
7969 * Fix for all "FFs" MAC address problems observed on
7970 * Alpha platforms
7971 */
7972 fix_mac_address(sp);
7973 s2io_reset(sp);
7974 }
1da177e4
LT		 7975
7976 /*
1da177e4
LT		 7977 * MAC address initialization.
7978 * For now only one mac address will be read and used.
7979 */
7980 bar0 = sp->bar0;
7981 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 7982 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 7983 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 7984 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 7985 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 7986 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7987 mac_down = (u32) tmp64;
7988 mac_up = (u32) (tmp64 >> 32);
7989
1da177e4
LT		 7990 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7991 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7992 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7993 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7994 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7995 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7996
1da177e4
LT		 7997 /* Set the factory defined MAC address initially */
7998 dev->addr_len = ETH_ALEN;
7999 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8000 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8001
faa4f796
SH		 8002 /* initialize number of multicast & unicast MAC entries variables */
8003 if (sp->device_type == XFRAME_I_DEVICE) {
8004 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8005 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8006 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8007 } else if (sp->device_type == XFRAME_II_DEVICE) {
8008 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8009 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8010 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8011 }
8012
8013 /* store mac addresses from CAM to s2io_nic structure */
8014 do_s2io_store_unicast_mc(sp);
8015
c77dd43e
SS		 8016 /* Store the values of the MSIX table in the s2io_nic structure */
8017 store_xmsi_data(sp);
b41477f3
AR		 8018 /* reset Nic and bring it to known state */
8019 s2io_reset(sp);
8020
1da177e4 8021 /*
99993af6 8022 * Initialize link state flags
541ae68f 8023 * and the card state parameter
1da177e4 8024 */
92b84437 8025 sp->state = 0;
1da177e4 8026
1da177e4 8027 /* Initialize spinlocks */
2fda096d
SR		 8028 for (i = 0; i < sp->config.tx_fifo_num; i++)
8029 spin_lock_init(&mac_control->fifos[i].tx_lock);
db874e65 8030
20346722 8031 /*
8032 * SXE-002: Configure link and activity LED to init state
8033 * on driver load.
1da177e4
LT		 8034 */
8035 subid = sp->pdev->subsystem_device;
8036 if ((subid & 0xFF) >= 0x07) {
8037 val64 = readq(&bar0->gpio_control);
8038 val64 |= 0x0000800000000000ULL;
8039 writeq(val64, &bar0->gpio_control);
8040 val64 = 0x0411040400000000ULL;
8041 writeq(val64, (void __iomem *) bar0 + 0x2700);
8042 val64 = readq(&bar0->gpio_control);
8043 }
8044
8045 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8046
8047 if (register_netdev(dev)) {
8048 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8049 ret = -ENODEV;
8050 goto register_failed;
8051 }
9dc737a7 8052 s2io_vpd_read(sp);
0c61ed5f 8053 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 8054 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 8055 sp->product_name, pdev->revision);
b41477f3
AR		 8056 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8057 s2io_driver_version);
0795af57
JP		 8058 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
8059 dev->name, print_mac(mac, dev->dev_addr));
19a60522 8060 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 8061 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8062 mode = s2io_print_pci_mode(sp);
541ae68f 8063 if (mode < 0) {
9dc737a7 8064 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 8065 ret = -EBADSLT;
9dc737a7 8066 unregister_netdev(dev);
541ae68f 8067 goto set_swap_failed;
8068 }
541ae68f 8069 }
9dc737a7
AR		 8070 switch(sp->rxd_mode) {
8071 case RXD_MODE_1:
8072 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8073 dev->name);
8074 break;
8075 case RXD_MODE_3B:
8076 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8077 dev->name);
8078 break;
9dc737a7 8079 }
db874e65
SS		 8080
8081 if (napi)
8082 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
3a3d5756
SH		 8083
8084 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8085 sp->config.tx_fifo_num);
8086
0425b46a
SH		 8087 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8088 sp->config.rx_ring_num);
8089
eaae7f72 8090 switch(sp->config.intr_type) {
9dc737a7
AR		 8091 case INTA:
8092 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8093 break;
9dc737a7
AR		 8094 case MSI_X:
8095 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8096 break;
8097 }
3a3d5756
SH		 8098 if (sp->config.multiq) {
8099 for (i = 0; i < sp->config.tx_fifo_num; i++)
8100 mac_control->fifos[i].multiq = config->multiq;
8101 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8102 dev->name);
8103 } else
8104 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8105 dev->name);
8106
6cfc482b
SH		 8107 switch (sp->config.tx_steering_type) {
8108 case NO_STEERING:
8109 DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
8110 " transmit\n", dev->name);
8111 break;
8112 case TX_PRIORITY_STEERING:
8113 DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
8114 " transmit\n", dev->name);
8115 break;
8116 case TX_DEFAULT_STEERING:
8117 DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
8118 " transmit\n", dev->name);
8119 }
8120
7d3d0439
RA		 8121 if (sp->lro)
8122 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8123 dev->name);
db874e65
SS		 8124 if (ufo)
8125 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
8126 " enabled\n", dev->name);
7ba013ac 8127 /* Initialize device name */
9dc737a7 8128 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8129
20346722 8130 /*
8131 * Make Link state as off at this point, when the Link change
8132 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8133 * the right state.
8134 */
8135 netif_carrier_off(dev);
1da177e4
LT		 8136
8137 return 0;
8138
8139 register_failed:
8140 set_swap_failed:
8141 iounmap(sp->bar1);
8142 bar1_remap_failed:
8143 iounmap(sp->bar0);
8144 bar0_remap_failed:
8145 mem_alloc_failed:
8146 free_shared_mem(sp);
8147 pci_disable_device(pdev);
eccb8628 8148 pci_release_regions(pdev);
1da177e4
LT		 8149 pci_set_drvdata(pdev, NULL);
8150 free_netdev(dev);
8151
8152 return ret;
8153}
8154
8155/**
20346722 8156 * s2io_rem_nic - Free the PCI device
1da177e4 8157 * @pdev: structure containing the PCI related information of the device.
20346722 8158 * Description: This function is called by the Pci subsystem to release a
1da177e4 8159 * PCI device and free up all resource held up by the device. This could
20346722 8160 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8161 * from memory.
8162 */
8163
8164static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8165{
8166 struct net_device *dev =
8167 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 8168 struct s2io_nic *sp;
1da177e4
LT		 8169
8170 if (dev == NULL) {
8171 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8172 return;
8173 }
8174
22747d6b
FR		 8175 flush_scheduled_work();
8176
1da177e4
LT		 8177 sp = dev->priv;
8178 unregister_netdev(dev);
8179
8180 free_shared_mem(sp);
8181 iounmap(sp->bar0);
8182 iounmap(sp->bar1);
eccb8628 8183 pci_release_regions(pdev);
1da177e4 8184 pci_set_drvdata(pdev, NULL);
1da177e4 8185 free_netdev(dev);
19a60522 8186 pci_disable_device(pdev);
1da177e4
LT		 8187}
8188
8189/**
8190 * s2io_starter - Entry point for the driver
8191 * Description: This function is the entry point for the driver. It verifies
8192 * the module loadable parameters and initializes PCI configuration space.
8193 */
8194
43b7c451 8195static int __init s2io_starter(void)
1da177e4 8196{
29917620 8197 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8198}
8199
8200/**
20346722 8201 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8202 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8203 */
8204
372cc597 8205static __exit void s2io_closer(void)
1da177e4
LT		 8206{
8207 pci_unregister_driver(&s2io_driver);
8208 DBG_PRINT(INIT_DBG, "cleanup done\n");
8209}
8210
8211module_init(s2io_starter);
8212module_exit(s2io_closer);
7d3d0439 8213
6aa20a22 8214static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
cdb5bf02
SH		 8215 struct tcphdr **tcp, struct RxD_t *rxdp,
8216 struct s2io_nic *sp)
7d3d0439
RA		 8217{
8218 int ip_off;
8219 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8220
8221 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8222 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
8223 __FUNCTION__);
8224 return -1;
8225 }
8226
cdb5bf02
SH		 8227 /* Checking for DIX type or DIX type with VLAN */
8228 if ((l2_type == 0)
8229 || (l2_type == 4)) {
8230 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8231 /*
8232 * If vlan stripping is disabled and the frame is VLAN tagged,
8233 * shift the offset by the VLAN header size bytes.
8234 */
8235 if ((!vlan_strip_flag) &&
8236 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8237 ip_off += HEADER_VLAN_SIZE;
8238 } else {
7d3d0439 8239 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8240 return -1;
7d3d0439
RA		 8241 }
8242
8243 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8244 ip_len = (u8)((*ip)->ihl);
8245 ip_len <<= 2;
8246 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8247
8248 return 0;
8249}
8250
1ee6dd77 8251static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8252 struct tcphdr *tcp)
8253{
8254 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8255 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8256 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8257 return -1;
8258 return 0;
8259}
8260
8261static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8262{
8263 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8264}
8265
1ee6dd77 8266static void initiate_new_session(struct lro *lro, u8 *l2h,
cdb5bf02 8267 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439
RA		 8268{
8269 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8270 lro->l2h = l2h;
8271 lro->iph = ip;
8272 lro->tcph = tcp;
8273 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8274 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8275 lro->sg_num = 1;
8276 lro->total_len = ntohs(ip->tot_len);
8277 lro->frags_len = 0;
cdb5bf02 8278 lro->vlan_tag = vlan_tag;
6aa20a22 8279 /*
7d3d0439
RA		 8280 * check if we saw TCP timestamp. Other consistency checks have
8281 * already been done.
8282 */
8283 if (tcp->doff == 8) {
c8855953
SR		 8284 __be32 *ptr;
8285 ptr = (__be32 *)(tcp+1);
7d3d0439 8286 lro->saw_ts = 1;
c8855953 8287 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8288 lro->cur_tsecr = *(ptr+2);
8289 }
8290 lro->in_use = 1;
8291}
8292
1ee6dd77 8293static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8294{
8295 struct iphdr *ip = lro->iph;
8296 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8297 __sum16 nchk;
1ee6dd77 8298 struct stat_block *statinfo = sp->mac_control.stats_info;
7d3d0439
RA		 8299 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8300
8301 /* Update L3 header */
8302 ip->tot_len = htons(lro->total_len);
8303 ip->check = 0;
8304 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8305 ip->check = nchk;
8306
8307 /* Update L4 header */
8308 tcp->ack_seq = lro->tcp_ack;
8309 tcp->window = lro->window;
8310
8311 /* Update tsecr field if this session has timestamps enabled */
8312 if (lro->saw_ts) {
c8855953 8313 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8314 *(ptr+2) = lro->cur_tsecr;
8315 }
8316
8317 /* Update counters required for calculation of
8318 * average no. of packets aggregated.
8319 */
8320 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8321 statinfo->sw_stat.num_aggregations++;
8322}
8323
1ee6dd77 8324static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8325 struct tcphdr *tcp, u32 l4_pyld)
8326{
8327 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8328 lro->total_len += l4_pyld;
8329 lro->frags_len += l4_pyld;
8330 lro->tcp_next_seq += l4_pyld;
8331 lro->sg_num++;
8332
8333 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8334 lro->tcp_ack = tcp->ack_seq;
8335 lro->window = tcp->window;
6aa20a22 8336
7d3d0439 8337 if (lro->saw_ts) {
c8855953 8338 __be32 *ptr;
7d3d0439 8339 /* Update tsecr and tsval from this packet */
c8855953
SR		 8340 ptr = (__be32 *)(tcp+1);
8341 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8342 lro->cur_tsecr = *(ptr + 2);
8343 }
8344}
8345
1ee6dd77 8346static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8347 struct tcphdr *tcp, u32 tcp_pyld_len)
8348{
7d3d0439
RA		 8349 u8 *ptr;
8350
79dc1901
AM		 8351 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8352
7d3d0439
RA		 8353 if (!tcp_pyld_len) {
8354 /* Runt frame or a pure ack */
8355 return -1;
8356 }
8357
8358 if (ip->ihl != 5) /* IP has options */
8359 return -1;
8360
75c30b13
AR		 8361 /* If we see CE codepoint in IP header, packet is not mergeable */
8362 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8363 return -1;
8364
8365 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 8366 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 8367 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8368 /*
8369 * Currently recognize only the ack control word and
8370 * any other control field being set would result in
8371 * flushing the LRO session
8372 */
8373 return -1;
8374 }
8375
6aa20a22 8376 /*
7d3d0439
RA		 8377 * Allow only one TCP timestamp option. Don't aggregate if
8378 * any other options are detected.
8379 */
8380 if (tcp->doff != 5 && tcp->doff != 8)
8381 return -1;
8382
8383 if (tcp->doff == 8) {
6aa20a22 8384 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8385 while (*ptr == TCPOPT_NOP)
8386 ptr++;
8387 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8388 return -1;
8389
8390 /* Ensure timestamp value increases monotonically */
8391 if (l_lro)
c8855953 8392 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8393 return -1;
8394
8395 /* timestamp echo reply should be non-zero */
c8855953 8396 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8397 return -1;
8398 }
8399
8400 return 0;
8401}
8402
8403static int
0425b46a
SH		 8404s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp,
8405 u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
8406 struct s2io_nic *sp)
7d3d0439
RA		 8407{
8408 struct iphdr *ip;
8409 struct tcphdr *tcph;
8410 int ret = 0, i;
cdb5bf02 8411 u16 vlan_tag = 0;
7d3d0439
RA		 8412
8413 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
cdb5bf02 8414 rxdp, sp))) {
7d3d0439
RA		 8415 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8416 ip->saddr, ip->daddr);
cdb5bf02 8417 } else
7d3d0439 8418 return ret;
7d3d0439 8419
cdb5bf02 8420 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8421 tcph = (struct tcphdr *)*tcp;
8422 *tcp_len = get_l4_pyld_length(ip, tcph);
8423 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 8424 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8425 if (l_lro->in_use) {
8426 if (check_for_socket_match(l_lro, ip, tcph))
8427 continue;
8428 /* Sock pair matched */
8429 *lro = l_lro;
8430
8431 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8432 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8433 "0x%x, actual 0x%x\n", __FUNCTION__,
8434 (*lro)->tcp_next_seq,
8435 ntohl(tcph->seq));
8436
8437 sp->mac_control.stats_info->
8438 sw_stat.outof_sequence_pkts++;
8439 ret = 2;
8440 break;
8441 }
8442
8443 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8444 ret = 1; /* Aggregate */
8445 else
8446 ret = 2; /* Flush both */
8447 break;
8448 }
8449 }
8450
8451 if (ret == 0) {
8452 /* Before searching for available LRO objects,
8453 * check if the pkt is L3/L4 aggregatable. If not
8454 * don't create new LRO session. Just send this
8455 * packet up.
8456 */
8457 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8458 return 5;
8459 }
8460
8461 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 8462 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8463 if (!(l_lro->in_use)) {
8464 *lro = l_lro;
8465 ret = 3; /* Begin anew */
8466 break;
8467 }
8468 }
8469 }
8470
8471 if (ret == 0) { /* sessions exceeded */
8472 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8473 __FUNCTION__);
8474 *lro = NULL;
8475 return ret;
8476 }
8477
8478 switch (ret) {
8479 case 3:
cdb5bf02
SH		 8480 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8481 vlan_tag);
7d3d0439
RA		 8482 break;
8483 case 2:
8484 update_L3L4_header(sp, *lro);
8485 break;
8486 case 1:
8487 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8488 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8489 update_L3L4_header(sp, *lro);
8490 ret = 4; /* Flush the LRO */
8491 }
8492 break;
8493 default:
8494 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8495 __FUNCTION__);
8496 break;
8497 }
8498
8499 return ret;
8500}
8501
1ee6dd77 8502static void clear_lro_session(struct lro *lro)
7d3d0439 8503{
1ee6dd77 8504 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8505
8506 memset(lro, 0, lro_struct_size);
8507}
8508
cdb5bf02 8509static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8510{
8511 struct net_device *dev = skb->dev;
cdb5bf02 8512 struct s2io_nic *sp = dev->priv;
7d3d0439
RA		 8513
8514 skb->protocol = eth_type_trans(skb, dev);
cdb5bf02
SH		 8515 if (sp->vlgrp && vlan_tag
8516 && (vlan_strip_flag)) {
8517 /* Queueing the vlan frame to the upper layer */
8518 if (sp->config.napi)
8519 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8520 else
8521 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8522 } else {
8523 if (sp->config.napi)
8524 netif_receive_skb(skb);
8525 else
8526 netif_rx(skb);
8527 }
7d3d0439
RA		 8528}
8529
1ee6dd77
RB		 8530static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8531 struct sk_buff *skb,
7d3d0439
RA		 8532 u32 tcp_len)
8533{
75c30b13 8534 struct sk_buff *first = lro->parent;
7d3d0439
RA		 8535
8536 first->len += tcp_len;
8537 first->data_len = lro->frags_len;
8538 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8539 if (skb_shinfo(first)->frag_list)
8540 lro->last_frag->next = skb;
7d3d0439
RA		 8541 else
8542 skb_shinfo(first)->frag_list = skb;
372cc597 8543 first->truesize += skb->truesize;
75c30b13 8544 lro->last_frag = skb;
7d3d0439
RA		 8545 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8546 return;
8547}
d796fdb7
LV		 8548
8549/**
8550 * s2io_io_error_detected - called when PCI error is detected
8551 * @pdev: Pointer to PCI device
8453d43f 8552 * @state: The current pci connection state
d796fdb7
LV		 8553 *
8554 * This function is called after a PCI bus error affecting
8555 * this device has been detected.
8556 */
8557static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8558 pci_channel_state_t state)
8559{
8560 struct net_device *netdev = pci_get_drvdata(pdev);
8561 struct s2io_nic *sp = netdev->priv;
8562
8563 netif_device_detach(netdev);
8564
8565 if (netif_running(netdev)) {
8566 /* Bring down the card, while avoiding PCI I/O */
8567 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8568 }
8569 pci_disable_device(pdev);
8570
8571 return PCI_ERS_RESULT_NEED_RESET;
8572}
8573
8574/**
8575 * s2io_io_slot_reset - called after the pci bus has been reset.
8576 * @pdev: Pointer to PCI device
8577 *
8578 * Restart the card from scratch, as if from a cold-boot.
8579 * At this point, the card has exprienced a hard reset,
8580 * followed by fixups by BIOS, and has its config space
8581 * set up identically to what it was at cold boot.
8582 */
8583static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8584{
8585 struct net_device *netdev = pci_get_drvdata(pdev);
8586 struct s2io_nic *sp = netdev->priv;
8587
8588 if (pci_enable_device(pdev)) {
8589 printk(KERN_ERR "s2io: "
8590 "Cannot re-enable PCI device after reset.\n");
8591 return PCI_ERS_RESULT_DISCONNECT;
8592 }
8593
8594 pci_set_master(pdev);
8595 s2io_reset(sp);
8596
8597 return PCI_ERS_RESULT_RECOVERED;
8598}
8599
8600/**
8601 * s2io_io_resume - called when traffic can start flowing again.
8602 * @pdev: Pointer to PCI device
8603 *
8604 * This callback is called when the error recovery driver tells
8605 * us that its OK to resume normal operation.
8606 */
8607static void s2io_io_resume(struct pci_dev *pdev)
8608{
8609 struct net_device *netdev = pci_get_drvdata(pdev);
8610 struct s2io_nic *sp = netdev->priv;
8611
8612 if (netif_running(netdev)) {
8613 if (s2io_card_up(sp)) {
8614 printk(KERN_ERR "s2io: "
8615 "Can't bring device back up after reset.\n");
8616 return;
8617 }
8618
8619 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8620 s2io_card_down(sp);
8621 printk(KERN_ERR "s2io: "
8622 "Can't resetore mac addr after reset.\n");
8623 return;
8624 }
8625 }
8626
8627 netif_device_attach(netdev);
8628 netif_wake_queue(netdev);
8629}
Linux 6.x block layer and io_uring tree(s)