projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6-block.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
926bd900 3 * Copyright(c) 2002-2010 Exar Corp.
d44570e4 4 *
1da177e4
LT		 5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4 27 * The module loadable parameters that are supported by the driver and a brief
a2a20aef 28 * explanation of all the variables.
9dc737a7 29 *
20346722 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
9dc737a7
AR		 41 * lro_max_pkts: This parameter defines maximum number of packets can be
42 * aggregated as a single large packet
926930b2
SS		 43 * napi: This parameter used to enable/disable NAPI (polling Rx)
44 * Possible values '1' for enable and '0' for disable. Default is '1'
45 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
46 * Possible values '1' for enable and '0' for disable. Default is '0'
47 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
48 * Possible values '1' for enable , '0' for disable.
49 * Default is '2' - which means disable in promisc mode
50 * and enable in non-promiscuous mode.
3a3d5756
SH		 51 * multiq: This parameter used to enable/disable MULTIQUEUE support.
52 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 53 ************************************************************************/
54
6cef2b8e
JP		 55#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/types.h>
59#include <linux/errno.h>
60#include <linux/ioport.h>
61#include <linux/pci.h>
1e7f0bd8 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/kernel.h>
64#include <linux/netdevice.h>
65#include <linux/etherdevice.h>
40239396 66#include <linux/mdio.h>
1da177e4
LT		 67#include <linux/skbuff.h>
68#include <linux/init.h>
69#include <linux/delay.h>
70#include <linux/stddef.h>
71#include <linux/ioctl.h>
72#include <linux/timex.h>
1da177e4 73#include <linux/ethtool.h>
1da177e4 74#include <linux/workqueue.h>
be3a6b02 75#include <linux/if_vlan.h>
7d3d0439
RA		 76#include <linux/ip.h>
77#include <linux/tcp.h>
d44570e4
JP		 78#include <linux/uaccess.h>
79#include <linux/io.h>
5a0e3ad6 80#include <linux/slab.h>
70c71606 81#include <linux/prefetch.h>
7d3d0439 82#include <net/tcp.h>
1da177e4 83
1da177e4 84#include <asm/system.h>
fe931395 85#include <asm/div64.h>
330ce0de 86#include <asm/irq.h>
1da177e4
LT		 87
88/* local include */
89#include "s2io.h"
90#include "s2io-regs.h"
91
11410b62 92#define DRV_VERSION "2.0.26.28"
6c1792f4 93
1da177e4 94/* S2io Driver name & version. */
c0dbf37e
JM		 95static const char s2io_driver_name[] = "Neterion";
96static const char s2io_driver_version[] = DRV_VERSION;
1da177e4 97
c0dbf37e
JM		 98static const int rxd_size[2] = {32, 48};
99static const int rxd_count[2] = {127, 85};
da6971d8 100
1ee6dd77 101static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd 102{
103 int ret;
104
105 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
d44570e4 106 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
5e25b9dd 107
108 return ret;
109}
110
20346722 111/*
1da177e4
LT		 112 * Cards with following subsystem_id have a link state indication
113 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
114 * macro below identifies these cards given the subsystem_id.
115 */
d44570e4
JP		 116#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
117 (dev_type == XFRAME_I_DEVICE) ? \
118 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
119 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 120
121#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
122 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 123
d44570e4 124static inline int is_s2io_card_up(const struct s2io_nic *sp)
92b84437
SS		 125{
126 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
127}
128
1da177e4 129/* Ethtool related variables and Macros. */
6fce365d 130static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 131 "Register test\t(offline)",
132 "Eeprom test\t(offline)",
133 "Link test\t(online)",
134 "RLDRAM test\t(offline)",
135 "BIST Test\t(offline)"
136};
137
6fce365d 138static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 139 {"tmac_frms"},
140 {"tmac_data_octets"},
141 {"tmac_drop_frms"},
142 {"tmac_mcst_frms"},
143 {"tmac_bcst_frms"},
144 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 145 {"tmac_ttl_octets"},
146 {"tmac_ucst_frms"},
147 {"tmac_nucst_frms"},
1da177e4 148 {"tmac_any_err_frms"},
bd1034f0 149 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 150 {"tmac_vld_ip_octets"},
151 {"tmac_vld_ip"},
152 {"tmac_drop_ip"},
153 {"tmac_icmp"},
154 {"tmac_rst_tcp"},
155 {"tmac_tcp"},
156 {"tmac_udp"},
157 {"rmac_vld_frms"},
158 {"rmac_data_octets"},
159 {"rmac_fcs_err_frms"},
160 {"rmac_drop_frms"},
161 {"rmac_vld_mcst_frms"},
162 {"rmac_vld_bcst_frms"},
163 {"rmac_in_rng_len_err_frms"},
bd1034f0 164 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 165 {"rmac_long_frms"},
166 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 167 {"rmac_unsup_ctrl_frms"},
168 {"rmac_ttl_octets"},
169 {"rmac_accepted_ucst_frms"},
170 {"rmac_accepted_nucst_frms"},
1da177e4 171 {"rmac_discarded_frms"},
bd1034f0
AR		 172 {"rmac_drop_events"},
173 {"rmac_ttl_less_fb_octets"},
174 {"rmac_ttl_frms"},
1da177e4
LT		 175 {"rmac_usized_frms"},
176 {"rmac_osized_frms"},
177 {"rmac_frag_frms"},
178 {"rmac_jabber_frms"},
bd1034f0
AR		 179 {"rmac_ttl_64_frms"},
180 {"rmac_ttl_65_127_frms"},
181 {"rmac_ttl_128_255_frms"},
182 {"rmac_ttl_256_511_frms"},
183 {"rmac_ttl_512_1023_frms"},
184 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 185 {"rmac_ip"},
186 {"rmac_ip_octets"},
187 {"rmac_hdr_err_ip"},
188 {"rmac_drop_ip"},
189 {"rmac_icmp"},
190 {"rmac_tcp"},
191 {"rmac_udp"},
192 {"rmac_err_drp_udp"},
bd1034f0
AR		 193 {"rmac_xgmii_err_sym"},
194 {"rmac_frms_q0"},
195 {"rmac_frms_q1"},
196 {"rmac_frms_q2"},
197 {"rmac_frms_q3"},
198 {"rmac_frms_q4"},
199 {"rmac_frms_q5"},
200 {"rmac_frms_q6"},
201 {"rmac_frms_q7"},
202 {"rmac_full_q0"},
203 {"rmac_full_q1"},
204 {"rmac_full_q2"},
205 {"rmac_full_q3"},
206 {"rmac_full_q4"},
207 {"rmac_full_q5"},
208 {"rmac_full_q6"},
209 {"rmac_full_q7"},
1da177e4 210 {"rmac_pause_cnt"},
bd1034f0
AR		 211 {"rmac_xgmii_data_err_cnt"},
212 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 213 {"rmac_accepted_ip"},
214 {"rmac_err_tcp"},
bd1034f0
AR		 215 {"rd_req_cnt"},
216 {"new_rd_req_cnt"},
217 {"new_rd_req_rtry_cnt"},
218 {"rd_rtry_cnt"},
219 {"wr_rtry_rd_ack_cnt"},
220 {"wr_req_cnt"},
221 {"new_wr_req_cnt"},
222 {"new_wr_req_rtry_cnt"},
223 {"wr_rtry_cnt"},
224 {"wr_disc_cnt"},
225 {"rd_rtry_wr_ack_cnt"},
226 {"txp_wr_cnt"},
227 {"txd_rd_cnt"},
228 {"txd_wr_cnt"},
229 {"rxd_rd_cnt"},
230 {"rxd_wr_cnt"},
231 {"txf_rd_cnt"},
fa1f0cb3
SS		 232 {"rxf_wr_cnt"}
233};
234
6fce365d 235static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 236 {"rmac_ttl_1519_4095_frms"},
237 {"rmac_ttl_4096_8191_frms"},
238 {"rmac_ttl_8192_max_frms"},
239 {"rmac_ttl_gt_max_frms"},
240 {"rmac_osized_alt_frms"},
241 {"rmac_jabber_alt_frms"},
242 {"rmac_gt_max_alt_frms"},
243 {"rmac_vlan_frms"},
244 {"rmac_len_discard"},
245 {"rmac_fcs_discard"},
246 {"rmac_pf_discard"},
247 {"rmac_da_discard"},
248 {"rmac_red_discard"},
249 {"rmac_rts_discard"},
250 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 251 {"link_fault_cnt"}
252};
253
6fce365d 254static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac 255 {"\n DRIVER STATISTICS"},
256 {"single_bit_ecc_errs"},
257 {"double_bit_ecc_errs"},
bd1034f0
AR		 258 {"parity_err_cnt"},
259 {"serious_err_cnt"},
260 {"soft_reset_cnt"},
261 {"fifo_full_cnt"},
8116f3cf
SS		 262 {"ring_0_full_cnt"},
263 {"ring_1_full_cnt"},
264 {"ring_2_full_cnt"},
265 {"ring_3_full_cnt"},
266 {"ring_4_full_cnt"},
267 {"ring_5_full_cnt"},
268 {"ring_6_full_cnt"},
269 {"ring_7_full_cnt"},
43b7c451
SH		 270 {"alarm_transceiver_temp_high"},
271 {"alarm_transceiver_temp_low"},
272 {"alarm_laser_bias_current_high"},
273 {"alarm_laser_bias_current_low"},
274 {"alarm_laser_output_power_high"},
275 {"alarm_laser_output_power_low"},
276 {"warn_transceiver_temp_high"},
277 {"warn_transceiver_temp_low"},
278 {"warn_laser_bias_current_high"},
279 {"warn_laser_bias_current_low"},
280 {"warn_laser_output_power_high"},
281 {"warn_laser_output_power_low"},
282 {"lro_aggregated_pkts"},
283 {"lro_flush_both_count"},
284 {"lro_out_of_sequence_pkts"},
285 {"lro_flush_due_to_max_pkts"},
286 {"lro_avg_aggr_pkts"},
287 {"mem_alloc_fail_cnt"},
288 {"pci_map_fail_cnt"},
289 {"watchdog_timer_cnt"},
290 {"mem_allocated"},
291 {"mem_freed"},
292 {"link_up_cnt"},
293 {"link_down_cnt"},
294 {"link_up_time"},
295 {"link_down_time"},
296 {"tx_tcode_buf_abort_cnt"},
297 {"tx_tcode_desc_abort_cnt"},
298 {"tx_tcode_parity_err_cnt"},
299 {"tx_tcode_link_loss_cnt"},
300 {"tx_tcode_list_proc_err_cnt"},
301 {"rx_tcode_parity_err_cnt"},
302 {"rx_tcode_abort_cnt"},
303 {"rx_tcode_parity_abort_cnt"},
304 {"rx_tcode_rda_fail_cnt"},
305 {"rx_tcode_unkn_prot_cnt"},
306 {"rx_tcode_fcs_err_cnt"},
307 {"rx_tcode_buf_size_err_cnt"},
308 {"rx_tcode_rxd_corrupt_cnt"},
309 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 310 {"tda_err_cnt"},
311 {"pfc_err_cnt"},
312 {"pcc_err_cnt"},
313 {"tti_err_cnt"},
314 {"tpa_err_cnt"},
315 {"sm_err_cnt"},
316 {"lso_err_cnt"},
317 {"mac_tmac_err_cnt"},
318 {"mac_rmac_err_cnt"},
319 {"xgxs_txgxs_err_cnt"},
320 {"xgxs_rxgxs_err_cnt"},
321 {"rc_err_cnt"},
322 {"prc_pcix_err_cnt"},
323 {"rpa_err_cnt"},
324 {"rda_err_cnt"},
325 {"rti_err_cnt"},
326 {"mc_err_cnt"}
1da177e4
LT		 327};
328
4c3616cd
AMR		 329#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
330#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
331#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3 332
d44570e4
JP		 333#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
334#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
fa1f0cb3 335
d44570e4
JP		 336#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
337#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
1da177e4 338
4c3616cd 339#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
d44570e4 340#define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
1da177e4 341
d44570e4
JP		 342#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
343 init_timer(&timer); \
344 timer.function = handle; \
345 timer.data = (unsigned long)arg; \
346 mod_timer(&timer, (jiffies + exp)) \
25fff88e 347
2fd37688
SS		 348/* copy mac addr to def_mac_addr array */
349static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
350{
351 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
352 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
353 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
354 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
355 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
356 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
357}
04025095 358
be3a6b02 359/* Add the vlan */
360static void s2io_vlan_rx_register(struct net_device *dev,
04025095 361 struct vlan_group *grp)
be3a6b02 362{
2fda096d 363 int i;
4cf1653a 364 struct s2io_nic *nic = netdev_priv(dev);
2fda096d 365 unsigned long flags[MAX_TX_FIFOS];
2fda096d 366 struct config_param *config = &nic->config;
ffb5df6c 367 struct mac_info *mac_control = &nic->mac_control;
2fda096d 368
13d866a9
JP		 369 for (i = 0; i < config->tx_fifo_num; i++) {
370 struct fifo_info *fifo = &mac_control->fifos[i];
371
372 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
373 }
be3a6b02 374
be3a6b02 375 nic->vlgrp = grp;
13d866a9
JP		 376
377 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
378 struct fifo_info *fifo = &mac_control->fifos[i];
379
380 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
381 }
be3a6b02 382}
383
cdb5bf02 384/* Unregister the vlan */
04025095 385static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 386{
387 int i;
4cf1653a 388 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02 389 unsigned long flags[MAX_TX_FIFOS];
cdb5bf02 390 struct config_param *config = &nic->config;
ffb5df6c 391 struct mac_info *mac_control = &nic->mac_control;
cdb5bf02 392
13d866a9
JP		 393 for (i = 0; i < config->tx_fifo_num; i++) {
394 struct fifo_info *fifo = &mac_control->fifos[i];
395
396 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
397 }
cdb5bf02
SH		 398
399 if (nic->vlgrp)
400 vlan_group_set_device(nic->vlgrp, vid, NULL);
401
13d866a9
JP		 402 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
403 struct fifo_info *fifo = &mac_control->fifos[i];
404
405 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
406 }
cdb5bf02
SH		 407}
408
20346722 409/*
1da177e4
LT		 410 * Constants to be programmed into the Xena's registers, to configure
411 * the XAUI.
412 */
413
1da177e4 414#define END_SIGN 0x0
f71e1309 415static const u64 herc_act_dtx_cfg[] = {
541ae68f 416 /* Set address */
e960fc5c 417 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 418 /* Write data */
e960fc5c 419 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f 420 /* Set address */
421 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
422 /* Write data */
423 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
424 /* Set address */
e960fc5c 425 0x801205150D440000ULL, 0x801205150D4400E0ULL,
426 /* Write data */
427 0x801205150D440004ULL, 0x801205150D4400E4ULL,
428 /* Set address */
541ae68f 429 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
430 /* Write data */
431 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
432 /* Done */
433 END_SIGN
434};
435
f71e1309 436static const u64 xena_dtx_cfg[] = {
c92ca04b 437 /* Set address */
1da177e4 438 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 439 /* Write data */
440 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
441 /* Set address */
442 0x8001051500000000ULL, 0x80010515000000E0ULL,
443 /* Write data */
444 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
445 /* Set address */
1da177e4 446 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 447 /* Write data */
448 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 449 END_SIGN
450};
451
20346722 452/*
1da177e4
LT		 453 * Constants for Fixing the MacAddress problem seen mostly on
454 * Alpha machines.
455 */
f71e1309 456static const u64 fix_mac[] = {
1da177e4
LT		 457 0x0060000000000000ULL, 0x0060600000000000ULL,
458 0x0040600000000000ULL, 0x0000600000000000ULL,
459 0x0020600000000000ULL, 0x0060600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0000600000000000ULL,
470 0x0040600000000000ULL, 0x0060600000000000ULL,
471 END_SIGN
472};
473
b41477f3
AR		 474MODULE_LICENSE("GPL");
475MODULE_VERSION(DRV_VERSION);
476
477
1da177e4 478/* Module Loadable parameters. */
6cfc482b 479S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 480S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 481S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 482S2IO_PARM_INT(rx_ring_mode, 1);
483S2IO_PARM_INT(use_continuous_tx_intrs, 1);
484S2IO_PARM_INT(rmac_pause_time, 0x100);
485S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
486S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
487S2IO_PARM_INT(shared_splits, 0);
488S2IO_PARM_INT(tmac_util_period, 5);
489S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 490S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 491/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
492S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 493/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 494S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 495/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 496S2IO_PARM_INT(intr_type, 2);
7d3d0439 497/* Large receive offload feature */
43b7c451 498
7d3d0439
RA		 499/* Max pkts to be aggregated by LRO at one time. If not specified,
500 * aggregation happens until we hit max IP pkt size(64K)
501 */
b41477f3 502S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 503S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 504
505S2IO_PARM_INT(napi, 1);
506S2IO_PARM_INT(ufo, 0);
926930b2 507S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 508
509static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
d44570e4 510{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
b41477f3 511static unsigned int rx_ring_sz[MAX_RX_RINGS] =
d44570e4 512{[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
b41477f3 513static unsigned int rts_frm_len[MAX_RX_RINGS] =
d44570e4 514{[0 ...(MAX_RX_RINGS - 1)] = 0 };
b41477f3
AR		 515
516module_param_array(tx_fifo_len, uint, NULL, 0);
517module_param_array(rx_ring_sz, uint, NULL, 0);
518module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 519
20346722 520/*
1da177e4 521 * S2IO device table.
20346722 522 * This table lists all the devices that this driver supports.
1da177e4 523 */
a3aa1884 524static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
1da177e4
LT		 525 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
526 PCI_ANY_ID, PCI_ANY_ID},
527 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
528 PCI_ANY_ID, PCI_ANY_ID},
529 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
d44570e4
JP		 530 PCI_ANY_ID, PCI_ANY_ID},
531 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
532 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 533 {0,}
534};
535
536MODULE_DEVICE_TABLE(pci, s2io_tbl);
537
d796fdb7
LV		 538static struct pci_error_handlers s2io_err_handler = {
539 .error_detected = s2io_io_error_detected,
540 .slot_reset = s2io_io_slot_reset,
541 .resume = s2io_io_resume,
542};
543
1da177e4 544static struct pci_driver s2io_driver = {
d44570e4
JP		 545 .name = "S2IO",
546 .id_table = s2io_tbl,
547 .probe = s2io_init_nic,
548 .remove = __devexit_p(s2io_rem_nic),
549 .err_handler = &s2io_err_handler,
1da177e4
LT		 550};
551
552/* A simplifier macro used both by init and free shared_mem Fns(). */
553#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
554
3a3d5756
SH		 555/* netqueue manipulation helper functions */
556static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
557{
fd2ea0a7
DM		 558 if (!sp->config.multiq) {
559 int i;
560
3a3d5756
SH		 561 for (i = 0; i < sp->config.tx_fifo_num; i++)
562 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 563 }
fd2ea0a7 564 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 565}
566
567static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
568{
fd2ea0a7 569 if (!sp->config.multiq)
3a3d5756
SH		 570 sp->mac_control.fifos[fifo_no].queue_state =
571 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 572
573 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 574}
575
576static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
577{
fd2ea0a7
DM		 578 if (!sp->config.multiq) {
579 int i;
580
3a3d5756
SH		 581 for (i = 0; i < sp->config.tx_fifo_num; i++)
582 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 583 }
fd2ea0a7 584 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 585}
586
587static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
588{
fd2ea0a7 589 if (!sp->config.multiq)
3a3d5756
SH		 590 sp->mac_control.fifos[fifo_no].queue_state =
591 FIFO_QUEUE_START;
fd2ea0a7
DM		 592
593 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 594}
595
596static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
597{
fd2ea0a7
DM		 598 if (!sp->config.multiq) {
599 int i;
600
3a3d5756
SH		 601 for (i = 0; i < sp->config.tx_fifo_num; i++)
602 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 603 }
fd2ea0a7 604 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 605}
606
607static inline void s2io_wake_tx_queue(
608 struct fifo_info *fifo, int cnt, u8 multiq)
609{
610
3a3d5756
SH		 611 if (multiq) {
612 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
613 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 614 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 615 if (netif_queue_stopped(fifo->dev)) {
616 fifo->queue_state = FIFO_QUEUE_START;
617 netif_wake_queue(fifo->dev);
618 }
619 }
620}
621
1da177e4
LT		 622/**
623 * init_shared_mem - Allocation and Initialization of Memory
624 * @nic: Device private variable.
20346722 625 * Description: The function allocates all the memory areas shared
626 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 627 * Rx descriptors and the statistics block.
628 */
629
630static int init_shared_mem(struct s2io_nic *nic)
631{
632 u32 size;
633 void *tmp_v_addr, *tmp_v_addr_next;
634 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 635 struct RxD_block *pre_rxd_blk = NULL;
372cc597 636 int i, j, blk_cnt;
1da177e4
LT		 637 int lst_size, lst_per_page;
638 struct net_device *dev = nic->dev;
8ae418cf 639 unsigned long tmp;
1ee6dd77 640 struct buffAdd *ba;
ffb5df6c
JP		 641 struct config_param *config = &nic->config;
642 struct mac_info *mac_control = &nic->mac_control;
491976b2 643 unsigned long long mem_allocated = 0;
1da177e4 644
13d866a9 645 /* Allocation and initialization of TXDLs in FIFOs */
1da177e4
LT		 646 size = 0;
647 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 648 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
649
650 size += tx_cfg->fifo_len;
1da177e4
LT		 651 }
652 if (size > MAX_AVAILABLE_TXDS) {
9e39f7c5
JP		 653 DBG_PRINT(ERR_DBG,
654 "Too many TxDs requested: %d, max supported: %d\n",
655 size, MAX_AVAILABLE_TXDS);
b41477f3 656 return -EINVAL;
1da177e4
LT		 657 }
658
2fda096d
SR		 659 size = 0;
660 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 661 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
662
663 size = tx_cfg->fifo_len;
2fda096d
SR		 664 /*
665 * Legal values are from 2 to 8192
666 */
667 if (size < 2) {
9e39f7c5
JP		 668 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
669 "Valid lengths are 2 through 8192\n",
670 i, size);
2fda096d
SR		 671 return -EINVAL;
672 }
673 }
674
1ee6dd77 675 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 676 lst_per_page = PAGE_SIZE / lst_size;
677
678 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 679 struct fifo_info *fifo = &mac_control->fifos[i];
680 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
681 int fifo_len = tx_cfg->fifo_len;
1ee6dd77 682 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
13d866a9
JP		 683
684 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
685 if (!fifo->list_info) {
d44570e4 686 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
1da177e4
LT		 687 return -ENOMEM;
688 }
491976b2 689 mem_allocated += list_holder_size;
1da177e4
LT		 690 }
691 for (i = 0; i < config->tx_fifo_num; i++) {
692 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
693 lst_per_page);
13d866a9
JP		 694 struct fifo_info *fifo = &mac_control->fifos[i];
695 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
696
697 fifo->tx_curr_put_info.offset = 0;
698 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
699 fifo->tx_curr_get_info.offset = 0;
700 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
701 fifo->fifo_no = i;
702 fifo->nic = nic;
703 fifo->max_txds = MAX_SKB_FRAGS + 2;
704 fifo->dev = dev;
20346722 705
1da177e4
LT		 706 for (j = 0; j < page_num; j++) {
707 int k = 0;
708 dma_addr_t tmp_p;
709 void *tmp_v;
710 tmp_v = pci_alloc_consistent(nic->pdev,
711 PAGE_SIZE, &tmp_p);
712 if (!tmp_v) {
9e39f7c5
JP		 713 DBG_PRINT(INFO_DBG,
714 "pci_alloc_consistent failed for TxDL\n");
1da177e4
LT		 715 return -ENOMEM;
716 }
776bd20f 717 /* If we got a zero DMA address(can happen on
718 * certain platforms like PPC), reallocate.
719 * Store virtual address of page we don't want,
720 * to be freed later.
721 */
722 if (!tmp_p) {
723 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 724 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 725 "%s: Zero DMA address for TxDL. "
726 "Virtual address %p\n",
727 dev->name, tmp_v);
776bd20f 728 tmp_v = pci_alloc_consistent(nic->pdev,
d44570e4 729 PAGE_SIZE, &tmp_p);
776bd20f 730 if (!tmp_v) {
0c61ed5f 731 DBG_PRINT(INFO_DBG,
9e39f7c5 732 "pci_alloc_consistent failed for TxDL\n");
776bd20f 733 return -ENOMEM;
734 }
491976b2 735 mem_allocated += PAGE_SIZE;
776bd20f 736 }
1da177e4
LT		 737 while (k < lst_per_page) {
738 int l = (j * lst_per_page) + k;
13d866a9 739 if (l == tx_cfg->fifo_len)
20346722 740 break;
13d866a9 741 fifo->list_info[l].list_virt_addr =
d44570e4 742 tmp_v + (k * lst_size);
13d866a9 743 fifo->list_info[l].list_phy_addr =
d44570e4 744 tmp_p + (k * lst_size);
1da177e4
LT		 745 k++;
746 }
747 }
748 }
1da177e4 749
2fda096d 750 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 751 struct fifo_info *fifo = &mac_control->fifos[i];
752 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
753
754 size = tx_cfg->fifo_len;
755 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
756 if (!fifo->ufo_in_band_v)
2fda096d
SR		 757 return -ENOMEM;
758 mem_allocated += (size * sizeof(u64));
759 }
fed5eccd 760
1da177e4
LT		 761 /* Allocation and initialization of RXDs in Rings */
762 size = 0;
763 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 764 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
765 struct ring_info *ring = &mac_control->rings[i];
766
767 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
9e39f7c5
JP		 768 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
769 "multiple of RxDs per Block\n",
770 dev->name, i);
1da177e4
LT		 771 return FAILURE;
772 }
13d866a9
JP		 773 size += rx_cfg->num_rxd;
774 ring->block_count = rx_cfg->num_rxd /
d44570e4 775 (rxd_count[nic->rxd_mode] + 1);
13d866a9 776 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
1da177e4 777 }
da6971d8 778 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 779 size = (size * (sizeof(struct RxD1)));
da6971d8 780 else
1ee6dd77 781 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 782
783 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 784 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
785 struct ring_info *ring = &mac_control->rings[i];
786
787 ring->rx_curr_get_info.block_index = 0;
788 ring->rx_curr_get_info.offset = 0;
789 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
790 ring->rx_curr_put_info.block_index = 0;
791 ring->rx_curr_put_info.offset = 0;
792 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
793 ring->nic = nic;
794 ring->ring_no = i;
13d866a9
JP		 795
796 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 797 /* Allocating all the Rx blocks */
798 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 799 struct rx_block_info *rx_blocks;
da6971d8
AR		 800 int l;
801
13d866a9 802 rx_blocks = &ring->rx_blocks[j];
d44570e4 803 size = SIZE_OF_BLOCK; /* size is always page size */
1da177e4
LT		 804 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
805 &tmp_p_addr);
806 if (tmp_v_addr == NULL) {
807 /*
20346722 808 * In case of failure, free_shared_mem()
809 * is called, which should free any
810 * memory that was alloced till the
1da177e4
LT		 811 * failure happened.
812 */
da6971d8 813 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 814 return -ENOMEM;
815 }
491976b2 816 mem_allocated += size;
1da177e4 817 memset(tmp_v_addr, 0, size);
4f870320
JP		 818
819 size = sizeof(struct rxd_info) *
820 rxd_count[nic->rxd_mode];
da6971d8
AR		 821 rx_blocks->block_virt_addr = tmp_v_addr;
822 rx_blocks->block_dma_addr = tmp_p_addr;
4f870320 823 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
372cc597
SS		 824 if (!rx_blocks->rxds)
825 return -ENOMEM;
4f870320 826 mem_allocated += size;
d44570e4 827 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
da6971d8
AR		 828 rx_blocks->rxds[l].virt_addr =
829 rx_blocks->block_virt_addr +
830 (rxd_size[nic->rxd_mode] * l);
831 rx_blocks->rxds[l].dma_addr =
832 rx_blocks->block_dma_addr +
833 (rxd_size[nic->rxd_mode] * l);
834 }
1da177e4
LT		 835 }
836 /* Interlinking all Rx Blocks */
837 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 838 int next = (j + 1) % blk_cnt;
839 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
840 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
841 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
842 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
1da177e4 843
d44570e4 844 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
1da177e4 845 pre_rxd_blk->reserved_2_pNext_RxD_block =
d44570e4 846 (unsigned long)tmp_v_addr_next;
1da177e4 847 pre_rxd_blk->pNext_RxD_Blk_physical =
d44570e4 848 (u64)tmp_p_addr_next;
1da177e4
LT		 849 }
850 }
6d517a27 851 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 852 /*
853 * Allocation of Storages for buffer addresses in 2BUFF mode
854 * and the buffers as well.
855 */
856 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 857 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
858 struct ring_info *ring = &mac_control->rings[i];
859
860 blk_cnt = rx_cfg->num_rxd /
d44570e4 861 (rxd_count[nic->rxd_mode] + 1);
4f870320
JP		 862 size = sizeof(struct buffAdd *) * blk_cnt;
863 ring->ba = kmalloc(size, GFP_KERNEL);
13d866a9 864 if (!ring->ba)
1da177e4 865 return -ENOMEM;
4f870320 866 mem_allocated += size;
da6971d8
AR		 867 for (j = 0; j < blk_cnt; j++) {
868 int k = 0;
4f870320
JP		 869
870 size = sizeof(struct buffAdd) *
871 (rxd_count[nic->rxd_mode] + 1);
872 ring->ba[j] = kmalloc(size, GFP_KERNEL);
13d866a9 873 if (!ring->ba[j])
1da177e4 874 return -ENOMEM;
4f870320 875 mem_allocated += size;
da6971d8 876 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 877 ba = &ring->ba[j][k];
4f870320
JP		 878 size = BUF0_LEN + ALIGN_SIZE;
879 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 880 if (!ba->ba_0_org)
881 return -ENOMEM;
4f870320 882 mem_allocated += size;
da6971d8
AR		 883 tmp = (unsigned long)ba->ba_0_org;
884 tmp += ALIGN_SIZE;
d44570e4
JP		 885 tmp &= ~((unsigned long)ALIGN_SIZE);
886 ba->ba_0 = (void *)tmp;
da6971d8 887
4f870320
JP		 888 size = BUF1_LEN + ALIGN_SIZE;
889 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 890 if (!ba->ba_1_org)
891 return -ENOMEM;
4f870320 892 mem_allocated += size;
d44570e4 893 tmp = (unsigned long)ba->ba_1_org;
da6971d8 894 tmp += ALIGN_SIZE;
d44570e4
JP		 895 tmp &= ~((unsigned long)ALIGN_SIZE);
896 ba->ba_1 = (void *)tmp;
da6971d8
AR		 897 k++;
898 }
1da177e4
LT		 899 }
900 }
901 }
1da177e4
LT		 902
903 /* Allocation and initialization of Statistics block */
1ee6dd77 904 size = sizeof(struct stat_block);
d44570e4
JP		 905 mac_control->stats_mem =
906 pci_alloc_consistent(nic->pdev, size,
907 &mac_control->stats_mem_phy);
1da177e4
LT		 908
909 if (!mac_control->stats_mem) {
20346722 910 /*
911 * In case of failure, free_shared_mem() is called, which
912 * should free any memory that was alloced till the
1da177e4
LT		 913 * failure happened.
914 */
915 return -ENOMEM;
916 }
491976b2 917 mem_allocated += size;
1da177e4
LT		 918 mac_control->stats_mem_sz = size;
919
920 tmp_v_addr = mac_control->stats_mem;
d44570e4 921 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
1da177e4 922 memset(tmp_v_addr, 0, size);
3a22813a
BL		 923 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
924 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
491976b2 925 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 926 return SUCCESS;
927}
928
20346722 929/**
930 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 931 * @nic: Device private variable.
932 * Description: This function is to free all memory locations allocated by
933 * the init_shared_mem() function and return it to the kernel.
934 */
935
936static void free_shared_mem(struct s2io_nic *nic)
937{
938 int i, j, blk_cnt, size;
939 void *tmp_v_addr;
940 dma_addr_t tmp_p_addr;
1da177e4 941 int lst_size, lst_per_page;
8910b49f 942 struct net_device *dev;
491976b2 943 int page_num = 0;
ffb5df6c
JP		 944 struct config_param *config;
945 struct mac_info *mac_control;
946 struct stat_block *stats;
947 struct swStat *swstats;
1da177e4
LT		 948
949 if (!nic)
950 return;
951
8910b49f
MG		 952 dev = nic->dev;
953
1da177e4 954 config = &nic->config;
ffb5df6c
JP		 955 mac_control = &nic->mac_control;
956 stats = mac_control->stats_info;
957 swstats = &stats->sw_stat;
1da177e4 958
d44570e4 959 lst_size = sizeof(struct TxD) * config->max_txds;
1da177e4
LT		 960 lst_per_page = PAGE_SIZE / lst_size;
961
962 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 963 struct fifo_info *fifo = &mac_control->fifos[i];
964 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
965
966 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
1da177e4
LT		 967 for (j = 0; j < page_num; j++) {
968 int mem_blks = (j * lst_per_page);
13d866a9
JP		 969 struct list_info_hold *fli;
970
971 if (!fifo->list_info)
6aa20a22 972 return;
13d866a9
JP		 973
974 fli = &fifo->list_info[mem_blks];
975 if (!fli->list_virt_addr)
1da177e4
LT		 976 break;
977 pci_free_consistent(nic->pdev, PAGE_SIZE,
13d866a9
JP		 978 fli->list_virt_addr,
979 fli->list_phy_addr);
ffb5df6c 980 swstats->mem_freed += PAGE_SIZE;
1da177e4 981 }
776bd20f 982 /* If we got a zero DMA address during allocation,
983 * free the page now
984 */
985 if (mac_control->zerodma_virt_addr) {
986 pci_free_consistent(nic->pdev, PAGE_SIZE,
987 mac_control->zerodma_virt_addr,
988 (dma_addr_t)0);
6aa20a22 989 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 990 "%s: Freeing TxDL with zero DMA address. "
991 "Virtual address %p\n",
992 dev->name, mac_control->zerodma_virt_addr);
ffb5df6c 993 swstats->mem_freed += PAGE_SIZE;
776bd20f 994 }
13d866a9 995 kfree(fifo->list_info);
82c2d023 996 swstats->mem_freed += tx_cfg->fifo_len *
d44570e4 997 sizeof(struct list_info_hold);
1da177e4
LT		 998 }
999
1da177e4 1000 size = SIZE_OF_BLOCK;
1da177e4 1001 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1002 struct ring_info *ring = &mac_control->rings[i];
1003
1004 blk_cnt = ring->block_count;
1da177e4 1005 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 1006 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1007 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1da177e4
LT		 1008 if (tmp_v_addr == NULL)
1009 break;
1010 pci_free_consistent(nic->pdev, size,
1011 tmp_v_addr, tmp_p_addr);
ffb5df6c 1012 swstats->mem_freed += size;
13d866a9 1013 kfree(ring->rx_blocks[j].rxds);
ffb5df6c
JP		 1014 swstats->mem_freed += sizeof(struct rxd_info) *
1015 rxd_count[nic->rxd_mode];
1da177e4
LT		 1016 }
1017 }
1018
6d517a27 1019 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1020 /* Freeing buffer storage addresses in 2BUFF mode. */
1021 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1022 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1023 struct ring_info *ring = &mac_control->rings[i];
1024
1025 blk_cnt = rx_cfg->num_rxd /
1026 (rxd_count[nic->rxd_mode] + 1);
da6971d8
AR		 1027 for (j = 0; j < blk_cnt; j++) {
1028 int k = 0;
13d866a9 1029 if (!ring->ba[j])
da6971d8
AR		 1030 continue;
1031 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 1032 struct buffAdd *ba = &ring->ba[j][k];
da6971d8 1033 kfree(ba->ba_0_org);
ffb5df6c
JP		 1034 swstats->mem_freed +=
1035 BUF0_LEN + ALIGN_SIZE;
da6971d8 1036 kfree(ba->ba_1_org);
ffb5df6c
JP		 1037 swstats->mem_freed +=
1038 BUF1_LEN + ALIGN_SIZE;
da6971d8
AR		 1039 k++;
1040 }
13d866a9 1041 kfree(ring->ba[j]);
ffb5df6c
JP		 1042 swstats->mem_freed += sizeof(struct buffAdd) *
1043 (rxd_count[nic->rxd_mode] + 1);
1da177e4 1044 }
13d866a9 1045 kfree(ring->ba);
ffb5df6c
JP		 1046 swstats->mem_freed += sizeof(struct buffAdd *) *
1047 blk_cnt;
1da177e4 1048 }
1da177e4 1049 }
1da177e4 1050
2fda096d 1051 for (i = 0; i < nic->config.tx_fifo_num; i++) {
13d866a9
JP		 1052 struct fifo_info *fifo = &mac_control->fifos[i];
1053 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1054
1055 if (fifo->ufo_in_band_v) {
ffb5df6c
JP		 1056 swstats->mem_freed += tx_cfg->fifo_len *
1057 sizeof(u64);
13d866a9 1058 kfree(fifo->ufo_in_band_v);
2fda096d
SR		 1059 }
1060 }
1061
1da177e4 1062 if (mac_control->stats_mem) {
ffb5df6c 1063 swstats->mem_freed += mac_control->stats_mem_sz;
1da177e4
LT		 1064 pci_free_consistent(nic->pdev,
1065 mac_control->stats_mem_sz,
1066 mac_control->stats_mem,
1067 mac_control->stats_mem_phy);
491976b2 1068 }
1da177e4
LT		 1069}
1070
541ae68f 1071/**
1072 * s2io_verify_pci_mode -
1073 */
1074
1ee6dd77 1075static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1076{
1ee6dd77 1077 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1078 register u64 val64 = 0;
1079 int mode;
1080
1081 val64 = readq(&bar0->pci_mode);
1082 mode = (u8)GET_PCI_MODE(val64);
1083
d44570e4 1084 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f 1085 return -1; /* Unknown PCI mode */
1086 return mode;
1087}
1088
c92ca04b
AR		 1089#define NEC_VENID 0x1033
1090#define NEC_DEVID 0x0125
1091static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1092{
1093 struct pci_dev *tdev = NULL;
26d36b64
AC		 1094 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1095 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1096 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1097 pci_dev_put(tdev);
c92ca04b 1098 return 1;
7ad62dbc 1099 }
c92ca04b
AR		 1100 }
1101 }
1102 return 0;
1103}
541ae68f 1104
7b32a312 1105static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f 1106/**
1107 * s2io_print_pci_mode -
1108 */
1ee6dd77 1109static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1110{
1ee6dd77 1111 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1112 register u64 val64 = 0;
1113 int mode;
1114 struct config_param *config = &nic->config;
9e39f7c5 1115 const char *pcimode;
541ae68f 1116
1117 val64 = readq(&bar0->pci_mode);
1118 mode = (u8)GET_PCI_MODE(val64);
1119
d44570e4 1120 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f 1121 return -1; /* Unknown PCI mode */
1122
c92ca04b
AR		 1123 config->bus_speed = bus_speed[mode];
1124
1125 if (s2io_on_nec_bridge(nic->pdev)) {
1126 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
d44570e4 1127 nic->dev->name);
c92ca04b
AR		 1128 return mode;
1129 }
1130
d44570e4
JP		 1131 switch (mode) {
1132 case PCI_MODE_PCI_33:
9e39f7c5 1133 pcimode = "33MHz PCI bus";
d44570e4
JP		 1134 break;
1135 case PCI_MODE_PCI_66:
9e39f7c5 1136 pcimode = "66MHz PCI bus";
d44570e4
JP		 1137 break;
1138 case PCI_MODE_PCIX_M1_66:
9e39f7c5 1139 pcimode = "66MHz PCIX(M1) bus";
d44570e4
JP		 1140 break;
1141 case PCI_MODE_PCIX_M1_100:
9e39f7c5 1142 pcimode = "100MHz PCIX(M1) bus";
d44570e4
JP		 1143 break;
1144 case PCI_MODE_PCIX_M1_133:
9e39f7c5 1145 pcimode = "133MHz PCIX(M1) bus";
d44570e4
JP		 1146 break;
1147 case PCI_MODE_PCIX_M2_66:
9e39f7c5 1148 pcimode = "133MHz PCIX(M2) bus";
d44570e4
JP		 1149 break;
1150 case PCI_MODE_PCIX_M2_100:
9e39f7c5 1151 pcimode = "200MHz PCIX(M2) bus";
d44570e4
JP		 1152 break;
1153 case PCI_MODE_PCIX_M2_133:
9e39f7c5 1154 pcimode = "266MHz PCIX(M2) bus";
d44570e4
JP		 1155 break;
1156 default:
9e39f7c5
JP		 1157 pcimode = "unsupported bus!";
1158 mode = -1;
541ae68f 1159 }
1160
9e39f7c5
JP		 1161 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1162 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1163
541ae68f 1164 return mode;
1165}
1166
b7c5678f
RV		 1167/**
1168 * init_tti - Initialization transmit traffic interrupt scheme
1169 * @nic: device private variable
1170 * @link: link status (UP/DOWN) used to enable/disable continuous
1171 * transmit interrupts
1172 * Description: The function configures transmit traffic interrupts
1173 * Return Value: SUCCESS on success and
1174 * '-1' on failure
1175 */
1176
0d66afe7 1177static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1178{
1179 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1180 register u64 val64 = 0;
1181 int i;
ffb5df6c 1182 struct config_param *config = &nic->config;
b7c5678f
RV		 1183
1184 for (i = 0; i < config->tx_fifo_num; i++) {
1185 /*
1186 * TTI Initialization. Default Tx timer gets us about
1187 * 250 interrupts per sec. Continuous interrupts are enabled
1188 * by default.
1189 */
1190 if (nic->device_type == XFRAME_II_DEVICE) {
1191 int count = (nic->config.bus_speed * 125)/2;
1192 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1193 } else
1194 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1195
1196 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
d44570e4
JP		 1197 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1198 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1199 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1200 if (i == 0)
1201 if (use_continuous_tx_intrs && (link == LINK_UP))
1202 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1203 writeq(val64, &bar0->tti_data1_mem);
1204
ac731ab6
SH		 1205 if (nic->config.intr_type == MSI_X) {
1206 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1207 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1208 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1209 TTI_DATA2_MEM_TX_UFC_D(0x300);
1210 } else {
1211 if ((nic->config.tx_steering_type ==
d44570e4
JP		 1212 TX_DEFAULT_STEERING) &&
1213 (config->tx_fifo_num > 1) &&
1214 (i >= nic->udp_fifo_idx) &&
1215 (i < (nic->udp_fifo_idx +
1216 nic->total_udp_fifos)))
ac731ab6
SH		 1217 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1218 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1219 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1220 TTI_DATA2_MEM_TX_UFC_D(0x120);
1221 else
1222 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1223 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1224 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1225 TTI_DATA2_MEM_TX_UFC_D(0x80);
1226 }
b7c5678f
RV		 1227
1228 writeq(val64, &bar0->tti_data2_mem);
1229
d44570e4
JP		 1230 val64 = TTI_CMD_MEM_WE |
1231 TTI_CMD_MEM_STROBE_NEW_CMD |
1232 TTI_CMD_MEM_OFFSET(i);
b7c5678f
RV		 1233 writeq(val64, &bar0->tti_command_mem);
1234
1235 if (wait_for_cmd_complete(&bar0->tti_command_mem,
d44570e4
JP		 1236 TTI_CMD_MEM_STROBE_NEW_CMD,
1237 S2IO_BIT_RESET) != SUCCESS)
b7c5678f
RV		 1238 return FAILURE;
1239 }
1240
1241 return SUCCESS;
1242}
1243
20346722 1244/**
1245 * init_nic - Initialization of hardware
b7c5678f 1246 * @nic: device private variable
20346722 1247 * Description: The function sequentially configures every block
1248 * of the H/W from their reset values.
1249 * Return Value: SUCCESS on success and
1da177e4
LT		 1250 * '-1' on failure (endian settings incorrect).
1251 */
1252
1253static int init_nic(struct s2io_nic *nic)
1254{
1ee6dd77 1255 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1256 struct net_device *dev = nic->dev;
1257 register u64 val64 = 0;
1258 void __iomem *add;
1259 u32 time;
1260 int i, j;
c92ca04b 1261 int dtx_cnt = 0;
1da177e4 1262 unsigned long long mem_share;
20346722 1263 int mem_size;
ffb5df6c
JP		 1264 struct config_param *config = &nic->config;
1265 struct mac_info *mac_control = &nic->mac_control;
1da177e4 1266
5e25b9dd 1267 /* to set the swapper controle on the card */
d44570e4
JP		 1268 if (s2io_set_swapper(nic)) {
1269 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
9f74ffde 1270 return -EIO;
1da177e4
LT		 1271 }
1272
541ae68f 1273 /*
1274 * Herc requires EOI to be removed from reset before XGXS, so..
1275 */
1276 if (nic->device_type & XFRAME_II_DEVICE) {
1277 val64 = 0xA500000000ULL;
1278 writeq(val64, &bar0->sw_reset);
1279 msleep(500);
1280 val64 = readq(&bar0->sw_reset);
1281 }
1282
1da177e4
LT		 1283 /* Remove XGXS from reset state */
1284 val64 = 0;
1285 writeq(val64, &bar0->sw_reset);
1da177e4 1286 msleep(500);
20346722 1287 val64 = readq(&bar0->sw_reset);
1da177e4 1288
7962024e
SH		 1289 /* Ensure that it's safe to access registers by checking
1290 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1291 */
1292 if (nic->device_type == XFRAME_II_DEVICE) {
1293 for (i = 0; i < 50; i++) {
1294 val64 = readq(&bar0->adapter_status);
1295 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1296 break;
1297 msleep(10);
1298 }
1299 if (i == 50)
1300 return -ENODEV;
1301 }
1302
1da177e4
LT		 1303 /* Enable Receiving broadcasts */
1304 add = &bar0->mac_cfg;
1305 val64 = readq(&bar0->mac_cfg);
1306 val64 |= MAC_RMAC_BCAST_ENABLE;
1307 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 1308 writel((u32)val64, add);
1da177e4
LT		 1309 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1310 writel((u32) (val64 >> 32), (add + 4));
1311
1312 /* Read registers in all blocks */
1313 val64 = readq(&bar0->mac_int_mask);
1314 val64 = readq(&bar0->mc_int_mask);
1315 val64 = readq(&bar0->xgxs_int_mask);
1316
1317 /* Set MTU */
1318 val64 = dev->mtu;
1319 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1320
541ae68f 1321 if (nic->device_type & XFRAME_II_DEVICE) {
1322 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1323 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1324 &bar0->dtx_control, UF);
541ae68f 1325 if (dtx_cnt & 0x1)
1326 msleep(1); /* Necessary!! */
1da177e4
LT		 1327 dtx_cnt++;
1328 }
541ae68f 1329 } else {
c92ca04b
AR		 1330 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1331 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1332 &bar0->dtx_control, UF);
1333 val64 = readq(&bar0->dtx_control);
1334 dtx_cnt++;
1da177e4
LT		 1335 }
1336 }
1337
1338 /* Tx DMA Initialization */
1339 val64 = 0;
1340 writeq(val64, &bar0->tx_fifo_partition_0);
1341 writeq(val64, &bar0->tx_fifo_partition_1);
1342 writeq(val64, &bar0->tx_fifo_partition_2);
1343 writeq(val64, &bar0->tx_fifo_partition_3);
1344
1da177e4 1345 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 1346 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1347
1348 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1349 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1da177e4
LT		 1350
1351 if (i == (config->tx_fifo_num - 1)) {
1352 if (i % 2 == 0)
1353 i++;
1354 }
1355
1356 switch (i) {
1357 case 1:
1358 writeq(val64, &bar0->tx_fifo_partition_0);
1359 val64 = 0;
b7c5678f 1360 j = 0;
1da177e4
LT		 1361 break;
1362 case 3:
1363 writeq(val64, &bar0->tx_fifo_partition_1);
1364 val64 = 0;
b7c5678f 1365 j = 0;
1da177e4
LT		 1366 break;
1367 case 5:
1368 writeq(val64, &bar0->tx_fifo_partition_2);
1369 val64 = 0;
b7c5678f 1370 j = 0;
1da177e4
LT		 1371 break;
1372 case 7:
1373 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1374 val64 = 0;
1375 j = 0;
1376 break;
1377 default:
1378 j++;
1da177e4
LT		 1379 break;
1380 }
1381 }
1382
5e25b9dd 1383 /*
1384 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1385 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1386 */
d44570e4 1387 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
5e25b9dd 1388 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1389
1da177e4
LT		 1390 val64 = readq(&bar0->tx_fifo_partition_0);
1391 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
d44570e4 1392 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1da177e4 1393
20346722 1394 /*
1395 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1396 * integrity checking.
1397 */
1398 val64 = readq(&bar0->tx_pa_cfg);
d44570e4
JP		 1399 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1400 TX_PA_CFG_IGNORE_SNAP_OUI |
1401 TX_PA_CFG_IGNORE_LLC_CTRL |
1402 TX_PA_CFG_IGNORE_L2_ERR;
1da177e4
LT		 1403 writeq(val64, &bar0->tx_pa_cfg);
1404
1405 /* Rx DMA intialization. */
1406 val64 = 0;
1407 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1408 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1409
1410 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1da177e4
LT		 1411 }
1412 writeq(val64, &bar0->rx_queue_priority);
1413
20346722 1414 /*
1415 * Allocating equal share of memory to all the
1da177e4
LT		 1416 * configured Rings.
1417 */
1418 val64 = 0;
541ae68f 1419 if (nic->device_type & XFRAME_II_DEVICE)
1420 mem_size = 32;
1421 else
1422 mem_size = 64;
1423
1da177e4
LT		 1424 for (i = 0; i < config->rx_ring_num; i++) {
1425 switch (i) {
1426 case 0:
20346722 1427 mem_share = (mem_size / config->rx_ring_num +
1428 mem_size % config->rx_ring_num);
1da177e4
LT		 1429 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1430 continue;
1431 case 1:
20346722 1432 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1433 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1434 continue;
1435 case 2:
20346722 1436 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1437 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1438 continue;
1439 case 3:
20346722 1440 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1441 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1442 continue;
1443 case 4:
20346722 1444 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1445 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1446 continue;
1447 case 5:
20346722 1448 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1449 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1450 continue;
1451 case 6:
20346722 1452 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1453 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1454 continue;
1455 case 7:
20346722 1456 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1457 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1458 continue;
1459 }
1460 }
1461 writeq(val64, &bar0->rx_queue_cfg);
1462
20346722 1463 /*
5e25b9dd 1464 * Filling Tx round robin registers
b7c5678f 1465 * as per the number of FIFOs for equal scheduling priority
1da177e4 1466 */
5e25b9dd 1467 switch (config->tx_fifo_num) {
1468 case 1:
b7c5678f 1469 val64 = 0x0;
5e25b9dd 1470 writeq(val64, &bar0->tx_w_round_robin_0);
1471 writeq(val64, &bar0->tx_w_round_robin_1);
1472 writeq(val64, &bar0->tx_w_round_robin_2);
1473 writeq(val64, &bar0->tx_w_round_robin_3);
1474 writeq(val64, &bar0->tx_w_round_robin_4);
1475 break;
1476 case 2:
b7c5678f 1477 val64 = 0x0001000100010001ULL;
5e25b9dd 1478 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1479 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1480 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1481 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1482 val64 = 0x0001000100000000ULL;
5e25b9dd 1483 writeq(val64, &bar0->tx_w_round_robin_4);
1484 break;
1485 case 3:
b7c5678f 1486 val64 = 0x0001020001020001ULL;
5e25b9dd 1487 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1488 val64 = 0x0200010200010200ULL;
5e25b9dd 1489 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1490 val64 = 0x0102000102000102ULL;
5e25b9dd 1491 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1492 val64 = 0x0001020001020001ULL;
5e25b9dd 1493 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1494 val64 = 0x0200010200000000ULL;
5e25b9dd 1495 writeq(val64, &bar0->tx_w_round_robin_4);
1496 break;
1497 case 4:
b7c5678f 1498 val64 = 0x0001020300010203ULL;
5e25b9dd 1499 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1500 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1501 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1502 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1503 val64 = 0x0001020300000000ULL;
5e25b9dd 1504 writeq(val64, &bar0->tx_w_round_robin_4);
1505 break;
1506 case 5:
b7c5678f 1507 val64 = 0x0001020304000102ULL;
5e25b9dd 1508 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1509 val64 = 0x0304000102030400ULL;
5e25b9dd 1510 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1511 val64 = 0x0102030400010203ULL;
5e25b9dd 1512 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1513 val64 = 0x0400010203040001ULL;
5e25b9dd 1514 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1515 val64 = 0x0203040000000000ULL;
5e25b9dd 1516 writeq(val64, &bar0->tx_w_round_robin_4);
1517 break;
1518 case 6:
b7c5678f 1519 val64 = 0x0001020304050001ULL;
5e25b9dd 1520 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1521 val64 = 0x0203040500010203ULL;
5e25b9dd 1522 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1523 val64 = 0x0405000102030405ULL;
5e25b9dd 1524 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1525 val64 = 0x0001020304050001ULL;
5e25b9dd 1526 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1527 val64 = 0x0203040500000000ULL;
5e25b9dd 1528 writeq(val64, &bar0->tx_w_round_robin_4);
1529 break;
1530 case 7:
b7c5678f 1531 val64 = 0x0001020304050600ULL;
5e25b9dd 1532 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1533 val64 = 0x0102030405060001ULL;
5e25b9dd 1534 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1535 val64 = 0x0203040506000102ULL;
5e25b9dd 1536 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1537 val64 = 0x0304050600010203ULL;
5e25b9dd 1538 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1539 val64 = 0x0405060000000000ULL;
5e25b9dd 1540 writeq(val64, &bar0->tx_w_round_robin_4);
1541 break;
1542 case 8:
b7c5678f 1543 val64 = 0x0001020304050607ULL;
5e25b9dd 1544 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1545 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1546 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1547 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1548 val64 = 0x0001020300000000ULL;
5e25b9dd 1549 writeq(val64, &bar0->tx_w_round_robin_4);
1550 break;
1551 }
1552
b41477f3 1553 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1554 val64 = readq(&bar0->tx_fifo_partition_0);
1555 val64 |= (TX_FIFO_PARTITION_EN);
1556 writeq(val64, &bar0->tx_fifo_partition_0);
1557
5e25b9dd 1558 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1559 * number of Rings and steering based on QoS with
1560 * equal priority.
1561 */
5e25b9dd 1562 switch (config->rx_ring_num) {
1563 case 1:
0425b46a
SH		 1564 val64 = 0x0;
1565 writeq(val64, &bar0->rx_w_round_robin_0);
1566 writeq(val64, &bar0->rx_w_round_robin_1);
1567 writeq(val64, &bar0->rx_w_round_robin_2);
1568 writeq(val64, &bar0->rx_w_round_robin_3);
1569 writeq(val64, &bar0->rx_w_round_robin_4);
1570
5e25b9dd 1571 val64 = 0x8080808080808080ULL;
1572 writeq(val64, &bar0->rts_qos_steering);
1573 break;
1574 case 2:
0425b46a 1575 val64 = 0x0001000100010001ULL;
5e25b9dd 1576 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1577 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1578 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1579 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1580 val64 = 0x0001000100000000ULL;
5e25b9dd 1581 writeq(val64, &bar0->rx_w_round_robin_4);
1582
1583 val64 = 0x8080808040404040ULL;
1584 writeq(val64, &bar0->rts_qos_steering);
1585 break;
1586 case 3:
0425b46a 1587 val64 = 0x0001020001020001ULL;
5e25b9dd 1588 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1589 val64 = 0x0200010200010200ULL;
5e25b9dd 1590 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1591 val64 = 0x0102000102000102ULL;
5e25b9dd 1592 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1593 val64 = 0x0001020001020001ULL;
5e25b9dd 1594 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1595 val64 = 0x0200010200000000ULL;
5e25b9dd 1596 writeq(val64, &bar0->rx_w_round_robin_4);
1597
1598 val64 = 0x8080804040402020ULL;
1599 writeq(val64, &bar0->rts_qos_steering);
1600 break;
1601 case 4:
0425b46a 1602 val64 = 0x0001020300010203ULL;
5e25b9dd 1603 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1604 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1605 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1606 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1607 val64 = 0x0001020300000000ULL;
5e25b9dd 1608 writeq(val64, &bar0->rx_w_round_robin_4);
1609
1610 val64 = 0x8080404020201010ULL;
1611 writeq(val64, &bar0->rts_qos_steering);
1612 break;
1613 case 5:
0425b46a 1614 val64 = 0x0001020304000102ULL;
5e25b9dd 1615 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1616 val64 = 0x0304000102030400ULL;
5e25b9dd 1617 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1618 val64 = 0x0102030400010203ULL;
5e25b9dd 1619 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1620 val64 = 0x0400010203040001ULL;
5e25b9dd 1621 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1622 val64 = 0x0203040000000000ULL;
5e25b9dd 1623 writeq(val64, &bar0->rx_w_round_robin_4);
1624
1625 val64 = 0x8080404020201008ULL;
1626 writeq(val64, &bar0->rts_qos_steering);
1627 break;
1628 case 6:
0425b46a 1629 val64 = 0x0001020304050001ULL;
5e25b9dd 1630 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1631 val64 = 0x0203040500010203ULL;
5e25b9dd 1632 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1633 val64 = 0x0405000102030405ULL;
5e25b9dd 1634 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1635 val64 = 0x0001020304050001ULL;
5e25b9dd 1636 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1637 val64 = 0x0203040500000000ULL;
5e25b9dd 1638 writeq(val64, &bar0->rx_w_round_robin_4);
1639
1640 val64 = 0x8080404020100804ULL;
1641 writeq(val64, &bar0->rts_qos_steering);
1642 break;
1643 case 7:
0425b46a 1644 val64 = 0x0001020304050600ULL;
5e25b9dd 1645 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1646 val64 = 0x0102030405060001ULL;
5e25b9dd 1647 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1648 val64 = 0x0203040506000102ULL;
5e25b9dd 1649 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1650 val64 = 0x0304050600010203ULL;
5e25b9dd 1651 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1652 val64 = 0x0405060000000000ULL;
5e25b9dd 1653 writeq(val64, &bar0->rx_w_round_robin_4);
1654
1655 val64 = 0x8080402010080402ULL;
1656 writeq(val64, &bar0->rts_qos_steering);
1657 break;
1658 case 8:
0425b46a 1659 val64 = 0x0001020304050607ULL;
5e25b9dd 1660 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1661 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1662 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1663 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1664 val64 = 0x0001020300000000ULL;
5e25b9dd 1665 writeq(val64, &bar0->rx_w_round_robin_4);
1666
1667 val64 = 0x8040201008040201ULL;
1668 writeq(val64, &bar0->rts_qos_steering);
1669 break;
1670 }
1da177e4
LT		 1671
1672 /* UDP Fix */
1673 val64 = 0;
20346722 1674 for (i = 0; i < 8; i++)
1da177e4
LT		 1675 writeq(val64, &bar0->rts_frm_len_n[i]);
1676
5e25b9dd 1677 /* Set the default rts frame length for the rings configured */
1678 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1679 for (i = 0 ; i < config->rx_ring_num ; i++)
1680 writeq(val64, &bar0->rts_frm_len_n[i]);
1681
1682 /* Set the frame length for the configured rings
1683 * desired by the user
1684 */
1685 for (i = 0; i < config->rx_ring_num; i++) {
1686 /* If rts_frm_len[i] == 0 then it is assumed that user not
1687 * specified frame length steering.
1688 * If the user provides the frame length then program
1689 * the rts_frm_len register for those values or else
1690 * leave it as it is.
1691 */
1692 if (rts_frm_len[i] != 0) {
1693 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
d44570e4 1694 &bar0->rts_frm_len_n[i]);
5e25b9dd 1695 }
1696 }
8a4bdbaa 1697
9fc93a41
SS		 1698 /* Disable differentiated services steering logic */
1699 for (i = 0; i < 64; i++) {
1700 if (rts_ds_steer(nic, i, 0) == FAILURE) {
9e39f7c5
JP		 1701 DBG_PRINT(ERR_DBG,
1702 "%s: rts_ds_steer failed on codepoint %d\n",
1703 dev->name, i);
9f74ffde 1704 return -ENODEV;
9fc93a41
SS		 1705 }
1706 }
1707
20346722 1708 /* Program statistics memory */
1da177e4 1709 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1710
541ae68f 1711 if (nic->device_type == XFRAME_II_DEVICE) {
1712 val64 = STAT_BC(0x320);
1713 writeq(val64, &bar0->stat_byte_cnt);
1714 }
1715
20346722 1716 /*
1da177e4
LT		 1717 * Initializing the sampling rate for the device to calculate the
1718 * bandwidth utilization.
1719 */
1720 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
d44570e4 1721 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1da177e4
LT		 1722 writeq(val64, &bar0->mac_link_util);
1723
20346722 1724 /*
1725 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1726 * Scheme.
1727 */
1da177e4 1728
b7c5678f
RV		 1729 /* Initialize TTI */
1730 if (SUCCESS != init_tti(nic, nic->last_link_state))
1731 return -ENODEV;
1da177e4 1732
8a4bdbaa
SS		 1733 /* RTI Initialization */
1734 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1735 /*
8a4bdbaa
SS		 1736 * Programmed to generate Apprx 500 Intrs per
1737 * second
1738 */
1739 int count = (nic->config.bus_speed * 125)/4;
1740 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1741 } else
1742 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1743 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
d44570e4
JP		 1744 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1745 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1746 RTI_DATA1_MEM_RX_TIMER_AC_EN;
8a4bdbaa
SS		 1747
1748 writeq(val64, &bar0->rti_data1_mem);
1749
1750 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1751 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1752 if (nic->config.intr_type == MSI_X)
d44570e4
JP		 1753 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1754 RTI_DATA2_MEM_RX_UFC_D(0x40));
8a4bdbaa 1755 else
d44570e4
JP		 1756 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1757 RTI_DATA2_MEM_RX_UFC_D(0x80));
8a4bdbaa 1758 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1759
8a4bdbaa 1760 for (i = 0; i < config->rx_ring_num; i++) {
d44570e4
JP		 1761 val64 = RTI_CMD_MEM_WE |
1762 RTI_CMD_MEM_STROBE_NEW_CMD |
1763 RTI_CMD_MEM_OFFSET(i);
8a4bdbaa 1764 writeq(val64, &bar0->rti_command_mem);
1da177e4 1765
8a4bdbaa
SS		 1766 /*
1767 * Once the operation completes, the Strobe bit of the
1768 * command register will be reset. We poll for this
1769 * particular condition. We wait for a maximum of 500ms
1770 * for the operation to complete, if it's not complete
1771 * by then we return error.
1772 */
1773 time = 0;
f957bcf0 1774 while (true) {
8a4bdbaa
SS		 1775 val64 = readq(&bar0->rti_command_mem);
1776 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1777 break;
b6e3f982 1778
8a4bdbaa 1779 if (time > 10) {
9e39f7c5 1780 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
8a4bdbaa 1781 dev->name);
9f74ffde 1782 return -ENODEV;
b6e3f982 1783 }
8a4bdbaa
SS		 1784 time++;
1785 msleep(50);
1da177e4 1786 }
1da177e4
LT		 1787 }
1788
20346722 1789 /*
1790 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1791 * the 8 Queues on Rx side.
1792 */
1793 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1794 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1795
1796 /* Disable RMAC PAD STRIPPING */
509a2671 1797 add = &bar0->mac_cfg;
1da177e4
LT		 1798 val64 = readq(&bar0->mac_cfg);
1799 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1800 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1801 writel((u32) (val64), add);
1802 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1803 writel((u32) (val64 >> 32), (add + 4));
1804 val64 = readq(&bar0->mac_cfg);
1805
7d3d0439
RA		 1806 /* Enable FCS stripping by adapter */
1807 add = &bar0->mac_cfg;
1808 val64 = readq(&bar0->mac_cfg);
1809 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1810 if (nic->device_type == XFRAME_II_DEVICE)
1811 writeq(val64, &bar0->mac_cfg);
1812 else {
1813 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1814 writel((u32) (val64), add);
1815 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1816 writel((u32) (val64 >> 32), (add + 4));
1817 }
1818
20346722 1819 /*
1820 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1821 * generated by xena.
1822 */
1823 val64 = readq(&bar0->rmac_pause_cfg);
1824 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1825 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1826 writeq(val64, &bar0->rmac_pause_cfg);
1827
20346722 1828 /*
1da177e4
LT		 1829 * Set the Threshold Limit for Generating the pause frame
1830 * If the amount of data in any Queue exceeds ratio of
1831 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1832 * pause frame is generated
1833 */
1834 val64 = 0;
1835 for (i = 0; i < 4; i++) {
d44570e4
JP		 1836 val64 |= (((u64)0xFF00 |
1837 nic->mac_control.mc_pause_threshold_q0q3)
1838 << (i * 2 * 8));
1da177e4
LT		 1839 }
1840 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1841
1842 val64 = 0;
1843 for (i = 0; i < 4; i++) {
d44570e4
JP		 1844 val64 |= (((u64)0xFF00 |
1845 nic->mac_control.mc_pause_threshold_q4q7)
1846 << (i * 2 * 8));
1da177e4
LT		 1847 }
1848 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1849
20346722 1850 /*
1851 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1852 * exceeded the limit pointed by shared_splits
1853 */
1854 val64 = readq(&bar0->pic_control);
1855 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1856 writeq(val64, &bar0->pic_control);
1857
863c11a9
AR		 1858 if (nic->config.bus_speed == 266) {
1859 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1860 writeq(0x0, &bar0->read_retry_delay);
1861 writeq(0x0, &bar0->write_retry_delay);
1862 }
1863
541ae68f 1864 /*
1865 * Programming the Herc to split every write transaction
1866 * that does not start on an ADB to reduce disconnects.
1867 */
1868 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1869 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1870 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1871 writeq(val64, &bar0->misc_control);
1872 val64 = readq(&bar0->pic_control2);
b7b5a128 1873 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1874 writeq(val64, &bar0->pic_control2);
541ae68f 1875 }
c92ca04b
AR		 1876 if (strstr(nic->product_name, "CX4")) {
1877 val64 = TMAC_AVG_IPG(0x17);
1878 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d 1879 }
1880
1da177e4
LT		 1881 return SUCCESS;
1882}
a371a07d 1883#define LINK_UP_DOWN_INTERRUPT 1
1884#define MAC_RMAC_ERR_TIMER 2
1885
1ee6dd77 1886static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1887{
1888 if (nic->device_type == XFRAME_II_DEVICE)
1889 return LINK_UP_DOWN_INTERRUPT;
1890 else
1891 return MAC_RMAC_ERR_TIMER;
1892}
8116f3cf 1893
9caab458
SS		 1894/**
1895 * do_s2io_write_bits - update alarm bits in alarm register
1896 * @value: alarm bits
1897 * @flag: interrupt status
1898 * @addr: address value
1899 * Description: update alarm bits in alarm register
1900 * Return Value:
1901 * NONE.
1902 */
1903static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1904{
1905 u64 temp64;
1906
1907 temp64 = readq(addr);
1908
d44570e4
JP		 1909 if (flag == ENABLE_INTRS)
1910 temp64 &= ~((u64)value);
9caab458 1911 else
d44570e4 1912 temp64 |= ((u64)value);
9caab458
SS		 1913 writeq(temp64, addr);
1914}
1da177e4 1915
43b7c451 1916static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1917{
1918 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1919 register u64 gen_int_mask = 0;
01e16faa 1920 u64 interruptible;
9caab458 1921
01e16faa 1922 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458 1923 if (mask & TX_DMA_INTR) {
9caab458
SS		 1924 gen_int_mask |= TXDMA_INT_M;
1925
1926 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
d44570e4
JP		 1927 TXDMA_PCC_INT | TXDMA_TTI_INT |
1928 TXDMA_LSO_INT | TXDMA_TPA_INT |
1929 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
9caab458
SS		 1930
1931 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
d44570e4
JP		 1932 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1933 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1934 &bar0->pfc_err_mask);
9caab458
SS		 1935
1936 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
d44570e4
JP		 1937 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1938 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
9caab458
SS		 1939
1940 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
d44570e4
JP		 1941 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1942 PCC_N_SERR | PCC_6_COF_OV_ERR |
1943 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1944 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1945 PCC_TXB_ECC_SG_ERR,
1946 flag, &bar0->pcc_err_mask);
9caab458
SS		 1947
1948 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
d44570e4 1949 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
9caab458
SS		 1950
1951 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
d44570e4
JP		 1952 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1953 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1954 flag, &bar0->lso_err_mask);
9caab458
SS		 1955
1956 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
d44570e4 1957 flag, &bar0->tpa_err_mask);
9caab458
SS		 1958
1959 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
9caab458
SS		 1960 }
1961
1962 if (mask & TX_MAC_INTR) {
1963 gen_int_mask |= TXMAC_INT_M;
1964 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
d44570e4 1965 &bar0->mac_int_mask);
9caab458 1966 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
d44570e4
JP		 1967 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1968 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1969 flag, &bar0->mac_tmac_err_mask);
9caab458
SS		 1970 }
1971
1972 if (mask & TX_XGXS_INTR) {
1973 gen_int_mask |= TXXGXS_INT_M;
1974 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
d44570e4 1975 &bar0->xgxs_int_mask);
9caab458 1976 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
d44570e4
JP		 1977 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1978 flag, &bar0->xgxs_txgxs_err_mask);
9caab458
SS		 1979 }
1980
1981 if (mask & RX_DMA_INTR) {
1982 gen_int_mask |= RXDMA_INT_M;
1983 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
d44570e4
JP		 1984 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1985 flag, &bar0->rxdma_int_mask);
9caab458 1986 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
d44570e4
JP		 1987 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1988 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1989 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
9caab458 1990 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
d44570e4
JP		 1991 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1992 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1993 &bar0->prc_pcix_err_mask);
9caab458 1994 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
d44570e4
JP		 1995 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1996 &bar0->rpa_err_mask);
9caab458 1997 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
d44570e4
JP		 1998 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1999 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2000 RDA_FRM_ECC_SG_ERR |
2001 RDA_MISC_ERR|RDA_PCIX_ERR,
2002 flag, &bar0->rda_err_mask);
9caab458 2003 do_s2io_write_bits(RTI_SM_ERR_ALARM |
d44570e4
JP		 2004 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2005 flag, &bar0->rti_err_mask);
9caab458
SS		 2006 }
2007
2008 if (mask & RX_MAC_INTR) {
2009 gen_int_mask |= RXMAC_INT_M;
2010 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
d44570e4
JP		 2011 &bar0->mac_int_mask);
2012 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2013 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2014 RMAC_DOUBLE_ECC_ERR);
01e16faa
SH		 2015 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2016 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2017 do_s2io_write_bits(interruptible,
d44570e4 2018 flag, &bar0->mac_rmac_err_mask);
9caab458
SS		 2019 }
2020
d44570e4 2021 if (mask & RX_XGXS_INTR) {
9caab458
SS		 2022 gen_int_mask |= RXXGXS_INT_M;
2023 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
d44570e4 2024 &bar0->xgxs_int_mask);
9caab458 2025 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
d44570e4 2026 &bar0->xgxs_rxgxs_err_mask);
9caab458
SS		 2027 }
2028
2029 if (mask & MC_INTR) {
2030 gen_int_mask |= MC_INT_M;
d44570e4
JP		 2031 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2032 flag, &bar0->mc_int_mask);
9caab458 2033 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
d44570e4
JP		 2034 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2035 &bar0->mc_err_mask);
9caab458
SS		 2036 }
2037 nic->general_int_mask = gen_int_mask;
2038
2039 /* Remove this line when alarm interrupts are enabled */
2040 nic->general_int_mask = 0;
2041}
d44570e4 2042
20346722 2043/**
2044 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2045 * @nic: device private variable,
2046 * @mask: A mask indicating which Intr block must be modified and,
2047 * @flag: A flag indicating whether to enable or disable the Intrs.
2048 * Description: This function will either disable or enable the interrupts
20346722 2049 * depending on the flag argument. The mask argument can be used to
2050 * enable/disable any Intr block.
1da177e4
LT		 2051 * Return Value: NONE.
2052 */
2053
2054static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2055{
1ee6dd77 2056 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2057 register u64 temp64 = 0, intr_mask = 0;
2058
2059 intr_mask = nic->general_int_mask;
1da177e4
LT		 2060
2061 /* Top level interrupt classification */
2062 /* PIC Interrupts */
9caab458 2063 if (mask & TX_PIC_INTR) {
1da177e4 2064 /* Enable PIC Intrs in the general intr mask register */
9caab458 2065 intr_mask |= TXPIC_INT_M;
1da177e4 2066 if (flag == ENABLE_INTRS) {
20346722 2067 /*
a371a07d 2068 * If Hercules adapter enable GPIO otherwise
b41477f3 2069 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722 2070 * interrupts for now.
2071 * TODO
1da177e4 2072 */
a371a07d 2073 if (s2io_link_fault_indication(nic) ==
d44570e4 2074 LINK_UP_DOWN_INTERRUPT) {
9caab458 2075 do_s2io_write_bits(PIC_INT_GPIO, flag,
d44570e4 2076 &bar0->pic_int_mask);
9caab458 2077 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
d44570e4 2078 &bar0->gpio_int_mask);
9caab458 2079 } else
a371a07d 2080 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2081 } else if (flag == DISABLE_INTRS) {
20346722 2082 /*
2083 * Disable PIC Intrs in the general
2084 * intr mask register
1da177e4
LT		 2085 */
2086 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2087 }
2088 }
2089
1da177e4
LT		 2090 /* Tx traffic interrupts */
2091 if (mask & TX_TRAFFIC_INTR) {
9caab458 2092 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2093 if (flag == ENABLE_INTRS) {
20346722 2094 /*
1da177e4 2095 * Enable all the Tx side interrupts
20346722 2096 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2097 */
2098 writeq(0x0, &bar0->tx_traffic_mask);
2099 } else if (flag == DISABLE_INTRS) {
20346722 2100 /*
2101 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2102 * register.
2103 */
2104 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2105 }
2106 }
2107
2108 /* Rx traffic interrupts */
2109 if (mask & RX_TRAFFIC_INTR) {
9caab458 2110 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2111 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2112 /* writing 0 Enables all 8 RX interrupt levels */
2113 writeq(0x0, &bar0->rx_traffic_mask);
2114 } else if (flag == DISABLE_INTRS) {
20346722 2115 /*
2116 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2117 * register.
2118 */
2119 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2120 }
2121 }
9caab458
SS		 2122
2123 temp64 = readq(&bar0->general_int_mask);
2124 if (flag == ENABLE_INTRS)
d44570e4 2125 temp64 &= ~((u64)intr_mask);
9caab458
SS		 2126 else
2127 temp64 = DISABLE_ALL_INTRS;
2128 writeq(temp64, &bar0->general_int_mask);
2129
2130 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2131}
2132
19a60522
SS		 2133/**
2134 * verify_pcc_quiescent- Checks for PCC quiescent state
2135 * Return: 1 If PCC is quiescence
2136 * 0 If PCC is not quiescence
2137 */
1ee6dd77 2138static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2139{
19a60522 2140 int ret = 0, herc;
1ee6dd77 2141 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2142 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2143
19a60522 2144 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2145
f957bcf0 2146 if (flag == false) {
44c10138 2147 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2148 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2149 ret = 1;
19a60522
SS		 2150 } else {
2151 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2152 ret = 1;
20346722 2153 }
2154 } else {
44c10138 2155 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2156 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2157 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2158 ret = 1;
5e25b9dd 2159 } else {
2160 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2161 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2162 ret = 1;
20346722 2163 }
2164 }
2165
2166 return ret;
2167}
2168/**
2169 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2170 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2171 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2172 * differs and the calling function passes the input argument flag to
2173 * indicate this.
20346722 2174 * Return: 1 If xena is quiescence
1da177e4
LT		 2175 * 0 If Xena is not quiescence
2176 */
2177
1ee6dd77 2178static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2179{
19a60522 2180 int mode;
1ee6dd77 2181 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2182 u64 val64 = readq(&bar0->adapter_status);
2183 mode = s2io_verify_pci_mode(sp);
1da177e4 2184
19a60522 2185 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
9e39f7c5 2186 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
19a60522
SS		 2187 return 0;
2188 }
2189 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
9e39f7c5 2190 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
19a60522
SS		 2191 return 0;
2192 }
2193 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
9e39f7c5 2194 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
19a60522
SS		 2195 return 0;
2196 }
2197 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
9e39f7c5 2198 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
19a60522
SS		 2199 return 0;
2200 }
2201 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
9e39f7c5 2202 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
19a60522
SS		 2203 return 0;
2204 }
2205 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
9e39f7c5 2206 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
19a60522
SS		 2207 return 0;
2208 }
2209 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
9e39f7c5 2210 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
19a60522
SS		 2211 return 0;
2212 }
2213 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
9e39f7c5 2214 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
19a60522 2215 return 0;
1da177e4
LT		 2216 }
2217
19a60522
SS		 2218 /*
2219 * In PCI 33 mode, the P_PLL is not used, and therefore,
2220 * the the P_PLL_LOCK bit in the adapter_status register will
2221 * not be asserted.
2222 */
2223 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
d44570e4
JP		 2224 sp->device_type == XFRAME_II_DEVICE &&
2225 mode != PCI_MODE_PCI_33) {
9e39f7c5 2226 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
19a60522
SS		 2227 return 0;
2228 }
2229 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
d44570e4 2230 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
9e39f7c5 2231 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
19a60522
SS		 2232 return 0;
2233 }
2234 return 1;
1da177e4
LT		 2235}
2236
2237/**
2238 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2239 * @sp: Pointer to device specifc structure
20346722 2240 * Description :
1da177e4
LT		 2241 * New procedure to clear mac address reading problems on Alpha platforms
2242 *
2243 */
2244
d44570e4 2245static void fix_mac_address(struct s2io_nic *sp)
1da177e4 2246{
1ee6dd77 2247 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2248 int i = 0;
2249
2250 while (fix_mac[i] != END_SIGN) {
2251 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2252 udelay(10);
d83d282b 2253 (void) readq(&bar0->gpio_control);
1da177e4
LT		 2254 }
2255}
2256
2257/**
20346722 2258 * start_nic - Turns the device on
1da177e4 2259 * @nic : device private variable.
20346722 2260 * Description:
2261 * This function actually turns the device on. Before this function is
2262 * called,all Registers are configured from their reset states
2263 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2264 * calling this function, the device interrupts are cleared and the NIC is
2265 * literally switched on by writing into the adapter control register.
20346722 2266 * Return Value:
1da177e4
LT		 2267 * SUCCESS on success and -1 on failure.
2268 */
2269
2270static int start_nic(struct s2io_nic *nic)
2271{
1ee6dd77 2272 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2273 struct net_device *dev = nic->dev;
2274 register u64 val64 = 0;
20346722 2275 u16 subid, i;
ffb5df6c
JP		 2276 struct config_param *config = &nic->config;
2277 struct mac_info *mac_control = &nic->mac_control;
1da177e4
LT		 2278
2279 /* PRC Initialization and configuration */
2280 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2281 struct ring_info *ring = &mac_control->rings[i];
2282
d44570e4 2283 writeq((u64)ring->rx_blocks[0].block_dma_addr,
1da177e4
LT		 2284 &bar0->prc_rxd0_n[i]);
2285
2286 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2287 if (nic->rxd_mode == RXD_MODE_1)
2288 val64 |= PRC_CTRL_RC_ENABLED;
2289 else
2290 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2291 if (nic->device_type == XFRAME_II_DEVICE)
2292 val64 |= PRC_CTRL_GROUP_READS;
2293 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2294 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2295 writeq(val64, &bar0->prc_ctrl_n[i]);
2296 }
2297
da6971d8
AR		 2298 if (nic->rxd_mode == RXD_MODE_3B) {
2299 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2300 val64 = readq(&bar0->rx_pa_cfg);
2301 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2302 writeq(val64, &bar0->rx_pa_cfg);
2303 }
1da177e4 2304
926930b2
SS		 2305 if (vlan_tag_strip == 0) {
2306 val64 = readq(&bar0->rx_pa_cfg);
2307 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2308 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2309 nic->vlan_strip_flag = 0;
926930b2
SS		 2310 }
2311
20346722 2312 /*
1da177e4
LT		 2313 * Enabling MC-RLDRAM. After enabling the device, we timeout
2314 * for around 100ms, which is approximately the time required
2315 * for the device to be ready for operation.
2316 */
2317 val64 = readq(&bar0->mc_rldram_mrs);
2318 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2319 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2320 val64 = readq(&bar0->mc_rldram_mrs);
2321
20346722 2322 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2323
2324 /* Enabling ECC Protection. */
2325 val64 = readq(&bar0->adapter_control);
2326 val64 &= ~ADAPTER_ECC_EN;
2327 writeq(val64, &bar0->adapter_control);
2328
20346722 2329 /*
2330 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2331 * it.
2332 */
2333 val64 = readq(&bar0->adapter_status);
19a60522 2334 if (!verify_xena_quiescence(nic)) {
9e39f7c5
JP		 2335 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2336 "Adapter status reads: 0x%llx\n",
2337 dev->name, (unsigned long long)val64);
1da177e4
LT		 2338 return FAILURE;
2339 }
2340
20346722 2341 /*
1da177e4 2342 * With some switches, link might be already up at this point.
20346722 2343 * Because of this weird behavior, when we enable laser,
2344 * we may not get link. We need to handle this. We cannot
2345 * figure out which switch is misbehaving. So we are forced to
2346 * make a global change.
1da177e4
LT		 2347 */
2348
2349 /* Enabling Laser. */
2350 val64 = readq(&bar0->adapter_control);
2351 val64 |= ADAPTER_EOI_TX_ON;
2352 writeq(val64, &bar0->adapter_control);
2353
c92ca04b
AR		 2354 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2355 /*
25985edc 2356 * Dont see link state interrupts initially on some switches,
c92ca04b
AR		 2357 * so directly scheduling the link state task here.
2358 */
2359 schedule_work(&nic->set_link_task);
2360 }
1da177e4
LT		 2361 /* SXE-002: Initialize link and activity LED */
2362 subid = nic->pdev->subsystem_device;
541ae68f 2363 if (((subid & 0xFF) >= 0x07) &&
2364 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2365 val64 = readq(&bar0->gpio_control);
2366 val64 |= 0x0000800000000000ULL;
2367 writeq(val64, &bar0->gpio_control);
2368 val64 = 0x0411040400000000ULL;
509a2671 2369 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2370 }
2371
1da177e4
LT		 2372 return SUCCESS;
2373}
fed5eccd
AR		 2374/**
2375 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2376 */
d44570e4
JP		 2377static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2378 struct TxD *txdlp, int get_off)
fed5eccd 2379{
1ee6dd77 2380 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2381 struct sk_buff *skb;
1ee6dd77 2382 struct TxD *txds;
fed5eccd
AR		 2383 u16 j, frg_cnt;
2384
2385 txds = txdlp;
2fda096d 2386 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
d44570e4
JP		 2387 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2388 sizeof(u64), PCI_DMA_TODEVICE);
fed5eccd
AR		 2389 txds++;
2390 }
2391
d44570e4 2392 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
fed5eccd 2393 if (!skb) {
1ee6dd77 2394 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2395 return NULL;
2396 }
d44570e4 2397 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
e743d313 2398 skb_headlen(skb), PCI_DMA_TODEVICE);
fed5eccd
AR		 2399 frg_cnt = skb_shinfo(skb)->nr_frags;
2400 if (frg_cnt) {
2401 txds++;
2402 for (j = 0; j < frg_cnt; j++, txds++) {
2403 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2404 if (!txds->Buffer_Pointer)
2405 break;
d44570e4
JP		 2406 pci_unmap_page(nic->pdev,
2407 (dma_addr_t)txds->Buffer_Pointer,
fed5eccd
AR		 2408 frag->size, PCI_DMA_TODEVICE);
2409 }
2410 }
d44570e4
JP		 2411 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2412 return skb;
fed5eccd 2413}
1da177e4 2414
20346722 2415/**
2416 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2417 * @nic : device private variable.
20346722 2418 * Description:
1da177e4 2419 * Free all queued Tx buffers.
20346722 2420 * Return Value: void
d44570e4 2421 */
1da177e4
LT		 2422
2423static void free_tx_buffers(struct s2io_nic *nic)
2424{
2425 struct net_device *dev = nic->dev;
2426 struct sk_buff *skb;
1ee6dd77 2427 struct TxD *txdp;
1da177e4 2428 int i, j;
fed5eccd 2429 int cnt = 0;
ffb5df6c
JP		 2430 struct config_param *config = &nic->config;
2431 struct mac_info *mac_control = &nic->mac_control;
2432 struct stat_block *stats = mac_control->stats_info;
2433 struct swStat *swstats = &stats->sw_stat;
1da177e4
LT		 2434
2435 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 2436 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2437 struct fifo_info *fifo = &mac_control->fifos[i];
2fda096d 2438 unsigned long flags;
13d866a9
JP		 2439
2440 spin_lock_irqsave(&fifo->tx_lock, flags);
2441 for (j = 0; j < tx_cfg->fifo_len; j++) {
2442 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
fed5eccd
AR		 2443 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2444 if (skb) {
ffb5df6c 2445 swstats->mem_freed += skb->truesize;
fed5eccd
AR		 2446 dev_kfree_skb(skb);
2447 cnt++;
1da177e4 2448 }
1da177e4
LT		 2449 }
2450 DBG_PRINT(INTR_DBG,
9e39f7c5 2451 "%s: forcibly freeing %d skbs on FIFO%d\n",
1da177e4 2452 dev->name, cnt, i);
13d866a9
JP		 2453 fifo->tx_curr_get_info.offset = 0;
2454 fifo->tx_curr_put_info.offset = 0;
2455 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 2456 }
2457}
2458
20346722 2459/**
2460 * stop_nic - To stop the nic
1da177e4 2461 * @nic ; device private variable.
20346722 2462 * Description:
2463 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2464 * function does. This function is called to stop the device.
2465 * Return Value:
2466 * void.
2467 */
2468
2469static void stop_nic(struct s2io_nic *nic)
2470{
1ee6dd77 2471 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2472 register u64 val64 = 0;
5d3213cc 2473 u16 interruptible;
1da177e4
LT		 2474
2475 /* Disable all interrupts */
9caab458 2476 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2477 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2478 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2479 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2480
5d3213cc
AR		 2481 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2482 val64 = readq(&bar0->adapter_control);
2483 val64 &= ~(ADAPTER_CNTL_EN);
2484 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2485}
2486
20346722 2487/**
2488 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2489 * @ring_info: per ring structure
3f78d885
SH		 2490 * @from_card_up: If this is true, we will map the buffer to get
2491 * the dma address for buf0 and buf1 to give it to the card.
2492 * Else we will sync the already mapped buffer to give it to the card.
20346722 2493 * Description:
1da177e4
LT		 2494 * The function allocates Rx side skbs and puts the physical
2495 * address of these buffers into the RxD buffer pointers, so that the NIC
2496 * can DMA the received frame into these locations.
2497 * The NIC supports 3 receive modes, viz
2498 * 1. single buffer,
2499 * 2. three buffer and
2500 * 3. Five buffer modes.
20346722 2501 * Each mode defines how many fragments the received frame will be split
2502 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2503 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2504 * is split into 3 fragments. As of now only single buffer mode is
2505 * supported.
2506 * Return Value:
2507 * SUCCESS on success or an appropriate -ve value on failure.
2508 */
8d8bb39b 2509static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
d44570e4 2510 int from_card_up)
1da177e4 2511{
1da177e4 2512 struct sk_buff *skb;
1ee6dd77 2513 struct RxD_t *rxdp;
0425b46a 2514 int off, size, block_no, block_no1;
1da177e4 2515 u32 alloc_tab = 0;
20346722 2516 u32 alloc_cnt;
20346722 2517 u64 tmp;
1ee6dd77 2518 struct buffAdd *ba;
1ee6dd77 2519 struct RxD_t *first_rxdp = NULL;
363dc367 2520 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2521 int rxd_index = 0;
6d517a27
VP		 2522 struct RxD1 *rxdp1;
2523 struct RxD3 *rxdp3;
ffb5df6c 2524 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2525
0425b46a 2526 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2527
0425b46a 2528 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2529 while (alloc_tab < alloc_cnt) {
0425b46a 2530 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2531
0425b46a
SH		 2532 off = ring->rx_curr_put_info.offset;
2533
2534 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2535
2536 rxd_index = off + 1;
2537 if (block_no)
2538 rxd_index += (block_no * ring->rxd_count);
da6971d8 2539
7d2e3cb7 2540 if ((block_no == block_no1) &&
d44570e4
JP		 2541 (off == ring->rx_curr_get_info.offset) &&
2542 (rxdp->Host_Control)) {
9e39f7c5
JP		 2543 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2544 ring->dev->name);
1da177e4
LT		 2545 goto end;
2546 }
0425b46a
SH		 2547 if (off && (off == ring->rxd_count)) {
2548 ring->rx_curr_put_info.block_index++;
2549 if (ring->rx_curr_put_info.block_index ==
d44570e4 2550 ring->block_count)
0425b46a
SH		 2551 ring->rx_curr_put_info.block_index = 0;
2552 block_no = ring->rx_curr_put_info.block_index;
2553 off = 0;
2554 ring->rx_curr_put_info.offset = off;
2555 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2556 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2557 ring->dev->name, rxdp);
2558
1da177e4 2559 }
c9fcbf47 2560
da6971d8 2561 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
d44570e4
JP		 2562 ((ring->rxd_mode == RXD_MODE_3B) &&
2563 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2564 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2565 goto end;
2566 }
da6971d8 2567 /* calculate size of skb based on ring mode */
d44570e4
JP		 2568 size = ring->mtu +
2569 HEADER_ETHERNET_II_802_3_SIZE +
2570 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2571 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2572 size += NET_IP_ALIGN;
da6971d8 2573 else
0425b46a 2574 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2575
da6971d8
AR		 2576 /* allocate skb */
2577 skb = dev_alloc_skb(size);
d44570e4 2578 if (!skb) {
9e39f7c5
JP		 2579 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2580 ring->dev->name);
303bcb4b 2581 if (first_rxdp) {
2582 wmb();
2583 first_rxdp->Control_1 |= RXD_OWN_XENA;
2584 }
ffb5df6c 2585 swstats->mem_alloc_fail_cnt++;
7d2e3cb7 2586
da6971d8
AR		 2587 return -ENOMEM ;
2588 }
ffb5df6c 2589 swstats->mem_allocated += skb->truesize;
0425b46a
SH		 2590
2591 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2592 /* 1 buffer mode - normal operation mode */
d44570e4 2593 rxdp1 = (struct RxD1 *)rxdp;
1ee6dd77 2594 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2595 skb_reserve(skb, NET_IP_ALIGN);
d44570e4
JP		 2596 rxdp1->Buffer0_ptr =
2597 pci_map_single(ring->pdev, skb->data,
2598 size - NET_IP_ALIGN,
2599 PCI_DMA_FROMDEVICE);
8d8bb39b 2600 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2601 rxdp1->Buffer0_ptr))
491abf25
VP		 2602 goto pci_map_failed;
2603
8a4bdbaa 2604 rxdp->Control_2 =
491976b2 2605 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
d44570e4 2606 rxdp->Host_Control = (unsigned long)skb;
0425b46a 2607 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2608 /*
6d517a27
VP		 2609 * 2 buffer mode -
2610 * 2 buffer mode provides 128
da6971d8 2611 * byte aligned receive buffers.
da6971d8
AR		 2612 */
2613
d44570e4 2614 rxdp3 = (struct RxD3 *)rxdp;
491976b2 2615 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2616 Buffer0_ptr = rxdp3->Buffer0_ptr;
2617 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2618 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2619 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2620 rxdp3->Buffer0_ptr = Buffer0_ptr;
2621 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2622
0425b46a 2623 ba = &ring->ba[block_no][off];
da6971d8 2624 skb_reserve(skb, BUF0_LEN);
d44570e4 2625 tmp = (u64)(unsigned long)skb->data;
da6971d8
AR		 2626 tmp += ALIGN_SIZE;
2627 tmp &= ~ALIGN_SIZE;
2628 skb->data = (void *) (unsigned long)tmp;
27a884dc 2629 skb_reset_tail_pointer(skb);
da6971d8 2630
3f78d885 2631 if (from_card_up) {
6d517a27 2632 rxdp3->Buffer0_ptr =
d44570e4
JP		 2633 pci_map_single(ring->pdev, ba->ba_0,
2634 BUF0_LEN,
2635 PCI_DMA_FROMDEVICE);
2636 if (pci_dma_mapping_error(nic->pdev,
2637 rxdp3->Buffer0_ptr))
3f78d885
SH		 2638 goto pci_map_failed;
2639 } else
0425b46a 2640 pci_dma_sync_single_for_device(ring->pdev,
d44570e4
JP		 2641 (dma_addr_t)rxdp3->Buffer0_ptr,
2642 BUF0_LEN,
2643 PCI_DMA_FROMDEVICE);
491abf25 2644
da6971d8 2645 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2646 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2647 /* Two buffer mode */
2648
2649 /*
6aa20a22 2650 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2651 * L4 payload
2652 */
d44570e4
JP		 2653 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2654 skb->data,
2655 ring->mtu + 4,
2656 PCI_DMA_FROMDEVICE);
da6971d8 2657
8d8bb39b 2658 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2659 rxdp3->Buffer2_ptr))
491abf25
VP		 2660 goto pci_map_failed;
2661
3f78d885 2662 if (from_card_up) {
0425b46a
SH		 2663 rxdp3->Buffer1_ptr =
2664 pci_map_single(ring->pdev,
d44570e4
JP		 2665 ba->ba_1,
2666 BUF1_LEN,
2667 PCI_DMA_FROMDEVICE);
0425b46a 2668
8d8bb39b 2669 if (pci_dma_mapping_error(nic->pdev,
d44570e4
JP		 2670 rxdp3->Buffer1_ptr)) {
2671 pci_unmap_single(ring->pdev,
2672 (dma_addr_t)(unsigned long)
2673 skb->data,
2674 ring->mtu + 4,
2675 PCI_DMA_FROMDEVICE);
3f78d885
SH		 2676 goto pci_map_failed;
2677 }
75c30b13 2678 }
da6971d8
AR		 2679 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2680 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
d44570e4 2681 (ring->mtu + 4);
da6971d8 2682 }
b7b5a128 2683 rxdp->Control_2 |= s2BIT(0);
0425b46a 2684 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2685 }
303bcb4b 2686 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2687 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2688 off++;
0425b46a 2689 if (off == (ring->rxd_count + 1))
da6971d8 2690 off = 0;
0425b46a 2691 ring->rx_curr_put_info.offset = off;
20346722 2692
da6971d8 2693 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b 2694 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2695 if (first_rxdp) {
2696 wmb();
2697 first_rxdp->Control_1 |= RXD_OWN_XENA;
2698 }
2699 first_rxdp = rxdp;
2700 }
0425b46a 2701 ring->rx_bufs_left += 1;
1da177e4
LT		 2702 alloc_tab++;
2703 }
2704
d44570e4 2705end:
303bcb4b 2706 /* Transfer ownership of first descriptor to adapter just before
2707 * exiting. Before that, use memory barrier so that ownership
2708 * and other fields are seen by adapter correctly.
2709 */
2710 if (first_rxdp) {
2711 wmb();
2712 first_rxdp->Control_1 |= RXD_OWN_XENA;
2713 }
2714
1da177e4 2715 return SUCCESS;
d44570e4 2716
491abf25 2717pci_map_failed:
ffb5df6c
JP		 2718 swstats->pci_map_fail_cnt++;
2719 swstats->mem_freed += skb->truesize;
491abf25
VP		 2720 dev_kfree_skb_irq(skb);
2721 return -ENOMEM;
1da177e4
LT		 2722}
2723
da6971d8
AR		 2724static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2725{
2726 struct net_device *dev = sp->dev;
2727 int j;
2728 struct sk_buff *skb;
1ee6dd77 2729 struct RxD_t *rxdp;
6d517a27
VP		 2730 struct RxD1 *rxdp1;
2731 struct RxD3 *rxdp3;
ffb5df6c
JP		 2732 struct mac_info *mac_control = &sp->mac_control;
2733 struct stat_block *stats = mac_control->stats_info;
2734 struct swStat *swstats = &stats->sw_stat;
da6971d8 2735
da6971d8
AR		 2736 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2737 rxdp = mac_control->rings[ring_no].
d44570e4
JP		 2738 rx_blocks[blk].rxds[j].virt_addr;
2739 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2740 if (!skb)
da6971d8 2741 continue;
da6971d8 2742 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4
JP		 2743 rxdp1 = (struct RxD1 *)rxdp;
2744 pci_unmap_single(sp->pdev,
2745 (dma_addr_t)rxdp1->Buffer0_ptr,
2746 dev->mtu +
2747 HEADER_ETHERNET_II_802_3_SIZE +
2748 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2749 PCI_DMA_FROMDEVICE);
1ee6dd77 2750 memset(rxdp, 0, sizeof(struct RxD1));
d44570e4
JP		 2751 } else if (sp->rxd_mode == RXD_MODE_3B) {
2752 rxdp3 = (struct RxD3 *)rxdp;
d44570e4
JP		 2753 pci_unmap_single(sp->pdev,
2754 (dma_addr_t)rxdp3->Buffer0_ptr,
2755 BUF0_LEN,
2756 PCI_DMA_FROMDEVICE);
2757 pci_unmap_single(sp->pdev,
2758 (dma_addr_t)rxdp3->Buffer1_ptr,
2759 BUF1_LEN,
2760 PCI_DMA_FROMDEVICE);
2761 pci_unmap_single(sp->pdev,
2762 (dma_addr_t)rxdp3->Buffer2_ptr,
2763 dev->mtu + 4,
2764 PCI_DMA_FROMDEVICE);
1ee6dd77 2765 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2766 }
ffb5df6c 2767 swstats->mem_freed += skb->truesize;
da6971d8 2768 dev_kfree_skb(skb);
0425b46a 2769 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2770 }
2771}
2772
1da177e4 2773/**
20346722 2774 * free_rx_buffers - Frees all Rx buffers
1da177e4 2775 * @sp: device private variable.
20346722 2776 * Description:
1da177e4
LT		 2777 * This function will free all Rx buffers allocated by host.
2778 * Return Value:
2779 * NONE.
2780 */
2781
2782static void free_rx_buffers(struct s2io_nic *sp)
2783{
2784 struct net_device *dev = sp->dev;
da6971d8 2785 int i, blk = 0, buf_cnt = 0;
ffb5df6c
JP		 2786 struct config_param *config = &sp->config;
2787 struct mac_info *mac_control = &sp->mac_control;
1da177e4
LT		 2788
2789 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2790 struct ring_info *ring = &mac_control->rings[i];
2791
da6971d8 2792 for (blk = 0; blk < rx_ring_sz[i]; blk++)
d44570e4 2793 free_rxd_blk(sp, i, blk);
1da177e4 2794
13d866a9
JP		 2795 ring->rx_curr_put_info.block_index = 0;
2796 ring->rx_curr_get_info.block_index = 0;
2797 ring->rx_curr_put_info.offset = 0;
2798 ring->rx_curr_get_info.offset = 0;
2799 ring->rx_bufs_left = 0;
9e39f7c5 2800 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
1da177e4
LT		 2801 dev->name, buf_cnt, i);
2802 }
2803}
2804
8d8bb39b 2805static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2806{
8d8bb39b 2807 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2808 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2809 ring->dev->name);
f61e0a35
SH		 2810 }
2811 return 0;
2812}
2813
1da177e4
LT		 2814/**
2815 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2816 * @napi : pointer to the napi structure.
20346722 2817 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2818 * during one pass through the 'Poll" function.
2819 * Description:
2820 * Comes into picture only if NAPI support has been incorporated. It does
2821 * the same thing that rx_intr_handler does, but not in a interrupt context
2822 * also It will process only a given number of packets.
2823 * Return value:
2824 * 0 on success and 1 if there are No Rx packets to be processed.
2825 */
2826
f61e0a35 2827static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2828{
f61e0a35
SH		 2829 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2830 struct net_device *dev = ring->dev;
f61e0a35 2831 int pkts_processed = 0;
1a79d1c3
AV		 2832 u8 __iomem *addr = NULL;
2833 u8 val8 = 0;
4cf1653a 2834 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2835 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2836 int budget_org = budget;
1da177e4 2837
f61e0a35
SH		 2838 if (unlikely(!is_s2io_card_up(nic)))
2839 return 0;
1da177e4 2840
f61e0a35 2841 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2842 s2io_chk_rx_buffers(nic, ring);
1da177e4 2843
f61e0a35 2844 if (pkts_processed < budget_org) {
288379f0 2845 napi_complete(napi);
f61e0a35 2846 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2847 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2848 addr += 7 - ring->ring_no;
2849 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2850 writeb(val8, addr);
2851 val8 = readb(addr);
1da177e4 2852 }
f61e0a35
SH		 2853 return pkts_processed;
2854}
d44570e4 2855
f61e0a35
SH		 2856static int s2io_poll_inta(struct napi_struct *napi, int budget)
2857{
2858 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
f61e0a35
SH		 2859 int pkts_processed = 0;
2860 int ring_pkts_processed, i;
2861 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2862 int budget_org = budget;
ffb5df6c
JP		 2863 struct config_param *config = &nic->config;
2864 struct mac_info *mac_control = &nic->mac_control;
1da177e4 2865
f61e0a35
SH		 2866 if (unlikely(!is_s2io_card_up(nic)))
2867 return 0;
1da177e4 2868
1da177e4 2869 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9 2870 struct ring_info *ring = &mac_control->rings[i];
f61e0a35 2871 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2872 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2873 pkts_processed += ring_pkts_processed;
2874 budget -= ring_pkts_processed;
2875 if (budget <= 0)
1da177e4 2876 break;
1da177e4 2877 }
f61e0a35 2878 if (pkts_processed < budget_org) {
288379f0 2879 napi_complete(napi);
f61e0a35
SH		 2880 /* Re enable the Rx interrupts for the ring */
2881 writeq(0, &bar0->rx_traffic_mask);
2882 readl(&bar0->rx_traffic_mask);
2883 }
2884 return pkts_processed;
1da177e4 2885}
20346722 2886
b41477f3 2887#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2888/**
b41477f3 2889 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2890 * @dev : pointer to the device structure.
2891 * Description:
b41477f3
AR		 2892 * This function will be called by upper layer to check for events on the
2893 * interface in situations where interrupts are disabled. It is used for
2894 * specific in-kernel networking tasks, such as remote consoles and kernel
2895 * debugging over the network (example netdump in RedHat).
612eff0e 2896 */
612eff0e
BH		 2897static void s2io_netpoll(struct net_device *dev)
2898{
4cf1653a 2899 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2900 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2901 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e 2902 int i;
ffb5df6c
JP		 2903 struct config_param *config = &nic->config;
2904 struct mac_info *mac_control = &nic->mac_control;
612eff0e 2905
d796fdb7
LV		 2906 if (pci_channel_offline(nic->pdev))
2907 return;
2908
612eff0e
BH		 2909 disable_irq(dev->irq);
2910
612eff0e 2911 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2912 writeq(val64, &bar0->tx_traffic_int);
2913
6aa20a22 2914 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2915 * run out of skbs and will fail and eventually netpoll application such
2916 * as netdump will fail.
2917 */
2918 for (i = 0; i < config->tx_fifo_num; i++)
2919 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2920
b41477f3 2921 /* check for received packet and indicate up to network */
13d866a9
JP		 2922 for (i = 0; i < config->rx_ring_num; i++) {
2923 struct ring_info *ring = &mac_control->rings[i];
2924
2925 rx_intr_handler(ring, 0);
2926 }
612eff0e
BH		 2927
2928 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2929 struct ring_info *ring = &mac_control->rings[i];
2930
2931 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2932 DBG_PRINT(INFO_DBG,
2933 "%s: Out of memory in Rx Netpoll!!\n",
2934 dev->name);
612eff0e
BH		 2935 break;
2936 }
2937 }
612eff0e 2938 enable_irq(dev->irq);
612eff0e
BH		 2939}
2940#endif
2941
20346722 2942/**
1da177e4 2943 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2944 * @ring_info: per ring structure.
2945 * @budget: budget for napi processing.
20346722 2946 * Description:
2947 * If the interrupt is because of a received frame or if the
1da177e4 2948 * receive ring contains fresh as yet un-processed frames,this function is
20346722 2949 * called. It picks out the RxD at which place the last Rx processing had
2950 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2951 * the offset.
2952 * Return Value:
f61e0a35 2953 * No. of napi packets processed.
1da177e4 2954 */
f61e0a35 2955static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2956{
c9fcbf47 2957 int get_block, put_block;
1ee6dd77
RB		 2958 struct rx_curr_get_info get_info, put_info;
2959 struct RxD_t *rxdp;
1da177e4 2960 struct sk_buff *skb;
f61e0a35 2961 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 2962 int i;
d44570e4
JP		 2963 struct RxD1 *rxdp1;
2964 struct RxD3 *rxdp3;
7d3d0439 2965
20346722 2966 get_info = ring_data->rx_curr_get_info;
2967 get_block = get_info.block_index;
1ee6dd77 2968 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2969 put_block = put_info.block_index;
da6971d8 2970 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2971
da6971d8 2972 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2973 /*
2974 * If your are next to put index then it's
2975 * FIFO full condition
2976 */
da6971d8
AR		 2977 if ((get_block == put_block) &&
2978 (get_info.offset + 1) == put_info.offset) {
0425b46a 2979 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
d44570e4 2980 ring_data->dev->name);
da6971d8
AR		 2981 break;
2982 }
d44570e4 2983 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
20346722 2984 if (skb == NULL) {
9e39f7c5 2985 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
0425b46a 2986 ring_data->dev->name);
f61e0a35 2987 return 0;
1da177e4 2988 }
0425b46a 2989 if (ring_data->rxd_mode == RXD_MODE_1) {
d44570e4 2990 rxdp1 = (struct RxD1 *)rxdp;
0425b46a 2991 pci_unmap_single(ring_data->pdev, (dma_addr_t)
d44570e4
JP		 2992 rxdp1->Buffer0_ptr,
2993 ring_data->mtu +
2994 HEADER_ETHERNET_II_802_3_SIZE +
2995 HEADER_802_2_SIZE +
2996 HEADER_SNAP_SIZE,
2997 PCI_DMA_FROMDEVICE);
0425b46a 2998 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
d44570e4
JP		 2999 rxdp3 = (struct RxD3 *)rxdp;
3000 pci_dma_sync_single_for_cpu(ring_data->pdev,
3001 (dma_addr_t)rxdp3->Buffer0_ptr,
3002 BUF0_LEN,
3003 PCI_DMA_FROMDEVICE);
3004 pci_unmap_single(ring_data->pdev,
3005 (dma_addr_t)rxdp3->Buffer2_ptr,
3006 ring_data->mtu + 4,
3007 PCI_DMA_FROMDEVICE);
da6971d8 3008 }
863c11a9 3009 prefetch(skb->data);
20346722 3010 rx_osm_handler(ring_data, rxdp);
3011 get_info.offset++;
da6971d8
AR		 3012 ring_data->rx_curr_get_info.offset = get_info.offset;
3013 rxdp = ring_data->rx_blocks[get_block].
d44570e4 3014 rxds[get_info.offset].virt_addr;
0425b46a 3015 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3016 get_info.offset = 0;
da6971d8 3017 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3018 get_block++;
da6971d8
AR		 3019 if (get_block == ring_data->block_count)
3020 get_block = 0;
3021 ring_data->rx_curr_get_info.block_index = get_block;
20346722 3022 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3023 }
1da177e4 3024
f61e0a35
SH		 3025 if (ring_data->nic->config.napi) {
3026 budget--;
3027 napi_pkts++;
3028 if (!budget)
0425b46a
SH		 3029 break;
3030 }
20346722 3031 pkt_cnt++;
1da177e4
LT		 3032 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3033 break;
3034 }
0425b46a 3035 if (ring_data->lro) {
7d3d0439 3036 /* Clear all LRO sessions before exiting */
d44570e4 3037 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 3038 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3039 if (lro->in_use) {
0425b46a 3040 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3041 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3042 clear_lro_session(lro);
3043 }
3044 }
3045 }
d44570e4 3046 return napi_pkts;
1da177e4 3047}
20346722 3048
3049/**
1da177e4
LT		 3050 * tx_intr_handler - Transmit interrupt handler
3051 * @nic : device private variable
20346722 3052 * Description:
3053 * If an interrupt was raised to indicate DMA complete of the
3054 * Tx packet, this function is called. It identifies the last TxD
3055 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3056 * DMA'ed into the NICs internal memory.
3057 * Return Value:
3058 * NONE
3059 */
3060
1ee6dd77 3061static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3062{
1ee6dd77 3063 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3064 struct tx_curr_get_info get_info, put_info;
3a3d5756 3065 struct sk_buff *skb = NULL;
1ee6dd77 3066 struct TxD *txdlp;
3a3d5756 3067 int pkt_cnt = 0;
2fda096d 3068 unsigned long flags = 0;
f9046eb3 3069 u8 err_mask;
ffb5df6c
JP		 3070 struct stat_block *stats = nic->mac_control.stats_info;
3071 struct swStat *swstats = &stats->sw_stat;
1da177e4 3072
2fda096d 3073 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
d44570e4 3074 return;
2fda096d 3075
20346722 3076 get_info = fifo_data->tx_curr_get_info;
1ee6dd77 3077 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
d44570e4
JP		 3078 txdlp = (struct TxD *)
3079 fifo_data->list_info[get_info.offset].list_virt_addr;
20346722 3080 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3081 (get_info.offset != put_info.offset) &&
3082 (txdlp->Host_Control)) {
3083 /* Check for TxD errors */
3084 if (txdlp->Control_1 & TXD_T_CODE) {
3085 unsigned long long err;
3086 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0 3087 if (err & 0x1) {
ffb5df6c 3088 swstats->parity_err_cnt++;
bd1034f0 3089 }
491976b2
SH		 3090
3091 /* update t_code statistics */
f9046eb3 3092 err_mask = err >> 48;
d44570e4
JP		 3093 switch (err_mask) {
3094 case 2:
ffb5df6c 3095 swstats->tx_buf_abort_cnt++;
491976b2
SH		 3096 break;
3097
d44570e4 3098 case 3:
ffb5df6c 3099 swstats->tx_desc_abort_cnt++;
491976b2
SH		 3100 break;
3101
d44570e4 3102 case 7:
ffb5df6c 3103 swstats->tx_parity_err_cnt++;
491976b2
SH		 3104 break;
3105
d44570e4 3106 case 10:
ffb5df6c 3107 swstats->tx_link_loss_cnt++;
491976b2
SH		 3108 break;
3109
d44570e4 3110 case 15:
ffb5df6c 3111 swstats->tx_list_proc_err_cnt++;
491976b2 3112 break;
d44570e4 3113 }
20346722 3114 }
1da177e4 3115
fed5eccd 3116 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3117 if (skb == NULL) {
2fda096d 3118 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
9e39f7c5
JP		 3119 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3120 __func__);
20346722 3121 return;
3122 }
3a3d5756 3123 pkt_cnt++;
20346722 3124
20346722 3125 /* Updating the statistics block */
ffb5df6c 3126 swstats->mem_freed += skb->truesize;
20346722 3127 dev_kfree_skb_irq(skb);
3128
3129 get_info.offset++;
863c11a9
AR		 3130 if (get_info.offset == get_info.fifo_len + 1)
3131 get_info.offset = 0;
d44570e4
JP		 3132 txdlp = (struct TxD *)
3133 fifo_data->list_info[get_info.offset].list_virt_addr;
3134 fifo_data->tx_curr_get_info.offset = get_info.offset;
1da177e4
LT		 3135 }
3136
3a3d5756 3137 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3138
3139 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3140}
3141
bd1034f0
AR		 3142/**
3143 * s2io_mdio_write - Function to write in to MDIO registers
3144 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3145 * @addr : address value
3146 * @value : data value
3147 * @dev : pointer to net_device structure
3148 * Description:
3149 * This function is used to write values to the MDIO registers
3150 * NONE
3151 */
d44570e4
JP		 3152static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3153 struct net_device *dev)
bd1034f0 3154{
d44570e4 3155 u64 val64;
4cf1653a 3156 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3157 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0 3158
d44570e4
JP		 3159 /* address transaction */
3160 val64 = MDIO_MMD_INDX_ADDR(addr) |
3161 MDIO_MMD_DEV_ADDR(mmd_type) |
3162 MDIO_MMS_PRT_ADDR(0x0);
bd1034f0
AR		 3163 writeq(val64, &bar0->mdio_control);
3164 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3165 writeq(val64, &bar0->mdio_control);
3166 udelay(100);
3167
d44570e4
JP		 3168 /* Data transaction */
3169 val64 = MDIO_MMD_INDX_ADDR(addr) |
3170 MDIO_MMD_DEV_ADDR(mmd_type) |
3171 MDIO_MMS_PRT_ADDR(0x0) |
3172 MDIO_MDIO_DATA(value) |
3173 MDIO_OP(MDIO_OP_WRITE_TRANS);
bd1034f0
AR		 3174 writeq(val64, &bar0->mdio_control);
3175 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3176 writeq(val64, &bar0->mdio_control);
3177 udelay(100);
3178
d44570e4
JP		 3179 val64 = MDIO_MMD_INDX_ADDR(addr) |
3180 MDIO_MMD_DEV_ADDR(mmd_type) |
3181 MDIO_MMS_PRT_ADDR(0x0) |
3182 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3183 writeq(val64, &bar0->mdio_control);
3184 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3185 writeq(val64, &bar0->mdio_control);
3186 udelay(100);
bd1034f0
AR		 3187}
3188
3189/**
3190 * s2io_mdio_read - Function to write in to MDIO registers
3191 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3192 * @addr : address value
3193 * @dev : pointer to net_device structure
3194 * Description:
3195 * This function is used to read values to the MDIO registers
3196 * NONE
3197 */
3198static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3199{
3200 u64 val64 = 0x0;
3201 u64 rval64 = 0x0;
4cf1653a 3202 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3203 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3204
3205 /* address transaction */
d44570e4
JP		 3206 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3207 | MDIO_MMD_DEV_ADDR(mmd_type)
3208 | MDIO_MMS_PRT_ADDR(0x0));
bd1034f0
AR		 3209 writeq(val64, &bar0->mdio_control);
3210 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3211 writeq(val64, &bar0->mdio_control);
3212 udelay(100);
3213
3214 /* Data transaction */
d44570e4
JP		 3215 val64 = MDIO_MMD_INDX_ADDR(addr) |
3216 MDIO_MMD_DEV_ADDR(mmd_type) |
3217 MDIO_MMS_PRT_ADDR(0x0) |
3218 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3219 writeq(val64, &bar0->mdio_control);
3220 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3221 writeq(val64, &bar0->mdio_control);
3222 udelay(100);
3223
3224 /* Read the value from regs */
3225 rval64 = readq(&bar0->mdio_control);
3226 rval64 = rval64 & 0xFFFF0000;
3227 rval64 = rval64 >> 16;
3228 return rval64;
3229}
d44570e4 3230
bd1034f0
AR		 3231/**
3232 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
fbfecd37 3233 * @counter : counter value to be updated
bd1034f0
AR		 3234 * @flag : flag to indicate the status
3235 * @type : counter type
3236 * Description:
3237 * This function is to check the status of the xpak counters value
3238 * NONE
3239 */
3240
d44570e4
JP		 3241static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3242 u16 flag, u16 type)
bd1034f0
AR		 3243{
3244 u64 mask = 0x3;
3245 u64 val64;
3246 int i;
d44570e4 3247 for (i = 0; i < index; i++)
bd1034f0
AR		 3248 mask = mask << 0x2;
3249
d44570e4 3250 if (flag > 0) {
bd1034f0
AR		 3251 *counter = *counter + 1;
3252 val64 = *regs_stat & mask;
3253 val64 = val64 >> (index * 0x2);
3254 val64 = val64 + 1;
d44570e4
JP		 3255 if (val64 == 3) {
3256 switch (type) {
bd1034f0 3257 case 1:
9e39f7c5
JP		 3258 DBG_PRINT(ERR_DBG,
3259 "Take Xframe NIC out of service.\n");
3260 DBG_PRINT(ERR_DBG,
3261"Excessive temperatures may result in premature transceiver failure.\n");
d44570e4 3262 break;
bd1034f0 3263 case 2:
9e39f7c5
JP		 3264 DBG_PRINT(ERR_DBG,
3265 "Take Xframe NIC out of service.\n");
3266 DBG_PRINT(ERR_DBG,
3267"Excessive bias currents may indicate imminent laser diode failure.\n");
d44570e4 3268 break;
bd1034f0 3269 case 3:
9e39f7c5
JP		 3270 DBG_PRINT(ERR_DBG,
3271 "Take Xframe NIC out of service.\n");
3272 DBG_PRINT(ERR_DBG,
3273"Excessive laser output power may saturate far-end receiver.\n");
d44570e4 3274 break;
bd1034f0 3275 default:
d44570e4
JP		 3276 DBG_PRINT(ERR_DBG,
3277 "Incorrect XPAK Alarm type\n");
bd1034f0
AR		 3278 }
3279 val64 = 0x0;
3280 }
3281 val64 = val64 << (index * 0x2);
3282 *regs_stat = (*regs_stat & (~mask)) | (val64);
3283
3284 } else {
3285 *regs_stat = *regs_stat & (~mask);
3286 }
3287}
3288
3289/**
3290 * s2io_updt_xpak_counter - Function to update the xpak counters
3291 * @dev : pointer to net_device struct
3292 * Description:
3293 * This function is to upate the status of the xpak counters value
3294 * NONE
3295 */
3296static void s2io_updt_xpak_counter(struct net_device *dev)
3297{
3298 u16 flag = 0x0;
3299 u16 type = 0x0;
3300 u16 val16 = 0x0;
3301 u64 val64 = 0x0;
3302 u64 addr = 0x0;
3303
4cf1653a 3304 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 3305 struct stat_block *stats = sp->mac_control.stats_info;
3306 struct xpakStat *xstats = &stats->xpak_stat;
bd1034f0
AR		 3307
3308 /* Check the communication with the MDIO slave */
40239396 3309 addr = MDIO_CTRL1;
bd1034f0 3310 val64 = 0x0;
40239396 3311 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
d44570e4 3312 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
9e39f7c5
JP		 3313 DBG_PRINT(ERR_DBG,
3314 "ERR: MDIO slave access failed - Returned %llx\n",
3315 (unsigned long long)val64);
bd1034f0
AR		 3316 return;
3317 }
3318
40239396 3319 /* Check for the expected value of control reg 1 */
d44570e4 3320 if (val64 != MDIO_CTRL1_SPEED10G) {
9e39f7c5
JP		 3321 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3322 "Returned: %llx- Expected: 0x%x\n",
40239396 3323 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3324 return;
3325 }
3326
3327 /* Loading the DOM register to MDIO register */
3328 addr = 0xA100;
40239396
BH		 3329 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3330 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3331
3332 /* Reading the Alarm flags */
3333 addr = 0xA070;
3334 val64 = 0x0;
40239396 3335 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3336
3337 flag = CHECKBIT(val64, 0x7);
3338 type = 1;
ffb5df6c
JP		 3339 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3340 &xstats->xpak_regs_stat,
d44570e4 3341 0x0, flag, type);
bd1034f0 3342
d44570e4 3343 if (CHECKBIT(val64, 0x6))
ffb5df6c 3344 xstats->alarm_transceiver_temp_low++;
bd1034f0
AR		 3345
3346 flag = CHECKBIT(val64, 0x3);
3347 type = 2;
ffb5df6c
JP		 3348 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3349 &xstats->xpak_regs_stat,
d44570e4 3350 0x2, flag, type);
bd1034f0 3351
d44570e4 3352 if (CHECKBIT(val64, 0x2))
ffb5df6c 3353 xstats->alarm_laser_bias_current_low++;
bd1034f0
AR		 3354
3355 flag = CHECKBIT(val64, 0x1);
3356 type = 3;
ffb5df6c
JP		 3357 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3358 &xstats->xpak_regs_stat,
d44570e4 3359 0x4, flag, type);
bd1034f0 3360
d44570e4 3361 if (CHECKBIT(val64, 0x0))
ffb5df6c 3362 xstats->alarm_laser_output_power_low++;
bd1034f0
AR		 3363
3364 /* Reading the Warning flags */
3365 addr = 0xA074;
3366 val64 = 0x0;
40239396 3367 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0 3368
d44570e4 3369 if (CHECKBIT(val64, 0x7))
ffb5df6c 3370 xstats->warn_transceiver_temp_high++;
bd1034f0 3371
d44570e4 3372 if (CHECKBIT(val64, 0x6))
ffb5df6c 3373 xstats->warn_transceiver_temp_low++;
bd1034f0 3374
d44570e4 3375 if (CHECKBIT(val64, 0x3))
ffb5df6c 3376 xstats->warn_laser_bias_current_high++;
bd1034f0 3377
d44570e4 3378 if (CHECKBIT(val64, 0x2))
ffb5df6c 3379 xstats->warn_laser_bias_current_low++;
bd1034f0 3380
d44570e4 3381 if (CHECKBIT(val64, 0x1))
ffb5df6c 3382 xstats->warn_laser_output_power_high++;
bd1034f0 3383
d44570e4 3384 if (CHECKBIT(val64, 0x0))
ffb5df6c 3385 xstats->warn_laser_output_power_low++;
bd1034f0
AR		 3386}
3387
20346722 3388/**
1da177e4 3389 * wait_for_cmd_complete - waits for a command to complete.
20346722 3390 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3391 * s2io_nic structure.
20346722 3392 * Description: Function that waits for a command to Write into RMAC
3393 * ADDR DATA registers to be completed and returns either success or
3394 * error depending on whether the command was complete or not.
1da177e4
LT		 3395 * Return value:
3396 * SUCCESS on success and FAILURE on failure.
3397 */
3398
9fc93a41 3399static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
d44570e4 3400 int bit_state)
1da177e4 3401{
9fc93a41 3402 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3403 u64 val64;
3404
9fc93a41
SS		 3405 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3406 return FAILURE;
3407
3408 do {
c92ca04b 3409 val64 = readq(addr);
9fc93a41
SS		 3410 if (bit_state == S2IO_BIT_RESET) {
3411 if (!(val64 & busy_bit)) {
3412 ret = SUCCESS;
3413 break;
3414 }
3415 } else {
2d146eb1 3416 if (val64 & busy_bit) {
9fc93a41
SS		 3417 ret = SUCCESS;
3418 break;
3419 }
1da177e4 3420 }
c92ca04b 3421
d44570e4 3422 if (in_interrupt())
9fc93a41 3423 mdelay(delay);
c92ca04b 3424 else
9fc93a41 3425 msleep(delay);
c92ca04b 3426
9fc93a41
SS		 3427 if (++cnt >= 10)
3428 delay = 50;
3429 } while (cnt < 20);
1da177e4
LT		 3430 return ret;
3431}
19a60522
SS		 3432/*
3433 * check_pci_device_id - Checks if the device id is supported
3434 * @id : device id
3435 * Description: Function to check if the pci device id is supported by driver.
3436 * Return value: Actual device id if supported else PCI_ANY_ID
3437 */
3438static u16 check_pci_device_id(u16 id)
3439{
3440 switch (id) {
3441 case PCI_DEVICE_ID_HERC_WIN:
3442 case PCI_DEVICE_ID_HERC_UNI:
3443 return XFRAME_II_DEVICE;
3444 case PCI_DEVICE_ID_S2IO_UNI:
3445 case PCI_DEVICE_ID_S2IO_WIN:
3446 return XFRAME_I_DEVICE;
3447 default:
3448 return PCI_ANY_ID;
3449 }
3450}
1da177e4 3451
20346722 3452/**
3453 * s2io_reset - Resets the card.
1da177e4
LT		 3454 * @sp : private member of the device structure.
3455 * Description: Function to Reset the card. This function then also
20346722 3456 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3457 * the card reset also resets the configuration space.
3458 * Return value:
3459 * void.
3460 */
3461
d44570e4 3462static void s2io_reset(struct s2io_nic *sp)
1da177e4 3463{
1ee6dd77 3464 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3465 u64 val64;
5e25b9dd 3466 u16 subid, pci_cmd;
19a60522
SS		 3467 int i;
3468 u16 val16;
491976b2
SH		 3469 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3470 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
ffb5df6c
JP		 3471 struct stat_block *stats;
3472 struct swStat *swstats;
491976b2 3473
9e39f7c5 3474 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3a22813a 3475 __func__, pci_name(sp->pdev));
1da177e4 3476
0b1f7ebe 3477 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3478 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3479
1da177e4
LT		 3480 val64 = SW_RESET_ALL;
3481 writeq(val64, &bar0->sw_reset);
d44570e4 3482 if (strstr(sp->product_name, "CX4"))
c92ca04b 3483 msleep(750);
19a60522
SS		 3484 msleep(250);
3485 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3486
19a60522
SS		 3487 /* Restore the PCI state saved during initialization. */
3488 pci_restore_state(sp->pdev);
b8a623bf 3489 pci_save_state(sp->pdev);
19a60522
SS		 3490 pci_read_config_word(sp->pdev, 0x2, &val16);
3491 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3492 break;
3493 msleep(200);
3494 }
1da177e4 3495
d44570e4
JP		 3496 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3497 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
19a60522
SS		 3498
3499 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3500
3501 s2io_init_pci(sp);
1da177e4 3502
20346722 3503 /* Set swapper to enable I/O register access */
3504 s2io_set_swapper(sp);
3505
faa4f796
SH		 3506 /* restore mac_addr entries */
3507 do_s2io_restore_unicast_mc(sp);
3508
cc6e7c44
RA		 3509 /* Restore the MSIX table entries from local variables */
3510 restore_xmsi_data(sp);
3511
5e25b9dd 3512 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3513 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3514 /* Clear "detected parity error" bit */
303bcb4b 3515 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3516
303bcb4b 3517 /* Clearing PCIX Ecc status register */
3518 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3519
303bcb4b 3520 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3521 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3522 }
5e25b9dd 3523
20346722 3524 /* Reset device statistics maintained by OS */
d44570e4 3525 memset(&sp->stats, 0, sizeof(struct net_device_stats));
8a4bdbaa 3526
ffb5df6c
JP		 3527 stats = sp->mac_control.stats_info;
3528 swstats = &stats->sw_stat;
3529
491976b2 3530 /* save link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3531 up_cnt = swstats->link_up_cnt;
3532 down_cnt = swstats->link_down_cnt;
3533 up_time = swstats->link_up_time;
3534 down_time = swstats->link_down_time;
3535 reset_cnt = swstats->soft_reset_cnt;
3536 mem_alloc_cnt = swstats->mem_allocated;
3537 mem_free_cnt = swstats->mem_freed;
3538 watchdog_cnt = swstats->watchdog_timer_cnt;
3539
3540 memset(stats, 0, sizeof(struct stat_block));
3541
491976b2 3542 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3543 swstats->link_up_cnt = up_cnt;
3544 swstats->link_down_cnt = down_cnt;
3545 swstats->link_up_time = up_time;
3546 swstats->link_down_time = down_time;
3547 swstats->soft_reset_cnt = reset_cnt;
3548 swstats->mem_allocated = mem_alloc_cnt;
3549 swstats->mem_freed = mem_free_cnt;
3550 swstats->watchdog_timer_cnt = watchdog_cnt;
20346722 3551
1da177e4
LT		 3552 /* SXE-002: Configure link and activity LED to turn it off */
3553 subid = sp->pdev->subsystem_device;
541ae68f 3554 if (((subid & 0xFF) >= 0x07) &&
3555 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3556 val64 = readq(&bar0->gpio_control);
3557 val64 |= 0x0000800000000000ULL;
3558 writeq(val64, &bar0->gpio_control);
3559 val64 = 0x0411040400000000ULL;
509a2671 3560 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3561 }
3562
541ae68f 3563 /*
25985edc 3564 * Clear spurious ECC interrupts that would have occurred on
541ae68f 3565 * XFRAME II cards after reset.
3566 */
3567 if (sp->device_type == XFRAME_II_DEVICE) {
3568 val64 = readq(&bar0->pcc_err_reg);
3569 writeq(val64, &bar0->pcc_err_reg);
3570 }
3571
f957bcf0 3572 sp->device_enabled_once = false;
1da177e4
LT		 3573}
3574
3575/**
20346722 3576 * s2io_set_swapper - to set the swapper controle on the card
3577 * @sp : private member of the device structure,
1da177e4 3578 * pointer to the s2io_nic structure.
20346722 3579 * Description: Function to set the swapper control on the card
1da177e4
LT		 3580 * correctly depending on the 'endianness' of the system.
3581 * Return value:
3582 * SUCCESS on success and FAILURE on failure.
3583 */
3584
d44570e4 3585static int s2io_set_swapper(struct s2io_nic *sp)
1da177e4
LT		 3586{
3587 struct net_device *dev = sp->dev;
1ee6dd77 3588 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3589 u64 val64, valt, valr;
3590
20346722 3591 /*
1da177e4
LT		 3592 * Set proper endian settings and verify the same by reading
3593 * the PIF Feed-back register.
3594 */
3595
3596 val64 = readq(&bar0->pif_rd_swapper_fb);
3597 if (val64 != 0x0123456789ABCDEFULL) {
3598 int i = 0;
85a56498
JM		 3599 static const u64 value[] = {
3600 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3601 0x8100008181000081ULL, /* FE=1, SE=0 */
3602 0x4200004242000042ULL, /* FE=0, SE=1 */
3603 0 /* FE=0, SE=0 */
3604 };
1da177e4 3605
d44570e4 3606 while (i < 4) {
1da177e4
LT		 3607 writeq(value[i], &bar0->swapper_ctrl);
3608 val64 = readq(&bar0->pif_rd_swapper_fb);
3609 if (val64 == 0x0123456789ABCDEFULL)
3610 break;
3611 i++;
3612 }
3613 if (i == 4) {
9e39f7c5
JP		 3614 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3615 "feedback read %llx\n",
3616 dev->name, (unsigned long long)val64);
1da177e4
LT		 3617 return FAILURE;
3618 }
3619 valr = value[i];
3620 } else {
3621 valr = readq(&bar0->swapper_ctrl);
3622 }
3623
3624 valt = 0x0123456789ABCDEFULL;
3625 writeq(valt, &bar0->xmsi_address);
3626 val64 = readq(&bar0->xmsi_address);
3627
d44570e4 3628 if (val64 != valt) {
1da177e4 3629 int i = 0;
85a56498
JM		 3630 static const u64 value[] = {
3631 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3632 0x0081810000818100ULL, /* FE=1, SE=0 */
3633 0x0042420000424200ULL, /* FE=0, SE=1 */
3634 0 /* FE=0, SE=0 */
3635 };
1da177e4 3636
d44570e4 3637 while (i < 4) {
1da177e4
LT		 3638 writeq((value[i] | valr), &bar0->swapper_ctrl);
3639 writeq(valt, &bar0->xmsi_address);
3640 val64 = readq(&bar0->xmsi_address);
d44570e4 3641 if (val64 == valt)
1da177e4
LT		 3642 break;
3643 i++;
3644 }
d44570e4 3645 if (i == 4) {
20346722 3646 unsigned long long x = val64;
9e39f7c5
JP		 3647 DBG_PRINT(ERR_DBG,
3648 "Write failed, Xmsi_addr reads:0x%llx\n", x);
1da177e4
LT		 3649 return FAILURE;
3650 }
3651 }
3652 val64 = readq(&bar0->swapper_ctrl);
3653 val64 &= 0xFFFF000000000000ULL;
3654
d44570e4 3655#ifdef __BIG_ENDIAN
20346722 3656 /*
3657 * The device by default set to a big endian format, so a
1da177e4
LT		 3658 * big endian driver need not set anything.
3659 */
3660 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3661 SWAPPER_CTRL_TXP_SE |
3662 SWAPPER_CTRL_TXD_R_FE |
3663 SWAPPER_CTRL_TXD_W_FE |
3664 SWAPPER_CTRL_TXF_R_FE |
3665 SWAPPER_CTRL_RXD_R_FE |
3666 SWAPPER_CTRL_RXD_W_FE |
3667 SWAPPER_CTRL_RXF_W_FE |
3668 SWAPPER_CTRL_XMSI_FE |
3669 SWAPPER_CTRL_STATS_FE |
3670 SWAPPER_CTRL_STATS_SE);
eaae7f72 3671 if (sp->config.intr_type == INTA)
cc6e7c44 3672 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3673 writeq(val64, &bar0->swapper_ctrl);
3674#else
20346722 3675 /*
1da177e4 3676 * Initially we enable all bits to make it accessible by the
20346722 3677 * driver, then we selectively enable only those bits that
1da177e4
LT		 3678 * we want to set.
3679 */
3680 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3681 SWAPPER_CTRL_TXP_SE |
3682 SWAPPER_CTRL_TXD_R_FE |
3683 SWAPPER_CTRL_TXD_R_SE |
3684 SWAPPER_CTRL_TXD_W_FE |
3685 SWAPPER_CTRL_TXD_W_SE |
3686 SWAPPER_CTRL_TXF_R_FE |
3687 SWAPPER_CTRL_RXD_R_FE |
3688 SWAPPER_CTRL_RXD_R_SE |
3689 SWAPPER_CTRL_RXD_W_FE |
3690 SWAPPER_CTRL_RXD_W_SE |
3691 SWAPPER_CTRL_RXF_W_FE |
3692 SWAPPER_CTRL_XMSI_FE |
3693 SWAPPER_CTRL_STATS_FE |
3694 SWAPPER_CTRL_STATS_SE);
eaae7f72 3695 if (sp->config.intr_type == INTA)
cc6e7c44 3696 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3697 writeq(val64, &bar0->swapper_ctrl);
3698#endif
3699 val64 = readq(&bar0->swapper_ctrl);
3700
20346722 3701 /*
3702 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3703 * feedback register.
3704 */
3705 val64 = readq(&bar0->pif_rd_swapper_fb);
3706 if (val64 != 0x0123456789ABCDEFULL) {
3707 /* Endian settings are incorrect, calls for another dekko. */
9e39f7c5
JP		 3708 DBG_PRINT(ERR_DBG,
3709 "%s: Endian settings are wrong, feedback read %llx\n",
3710 dev->name, (unsigned long long)val64);
1da177e4
LT		 3711 return FAILURE;
3712 }
3713
3714 return SUCCESS;
3715}
3716
1ee6dd77 3717static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3718{
1ee6dd77 3719 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3720 u64 val64;
3721 int ret = 0, cnt = 0;
3722
3723 do {
3724 val64 = readq(&bar0->xmsi_access);
b7b5a128 3725 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3726 break;
3727 mdelay(1);
3728 cnt++;
d44570e4 3729 } while (cnt < 5);
cc6e7c44
RA		 3730 if (cnt == 5) {
3731 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3732 ret = 1;
3733 }
3734
3735 return ret;
3736}
3737
1ee6dd77 3738static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3739{
1ee6dd77 3740 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3741 u64 val64;
f61e0a35
SH		 3742 int i, msix_index;
3743
f61e0a35
SH		 3744 if (nic->device_type == XFRAME_I_DEVICE)
3745 return;
cc6e7c44 3746
d44570e4
JP		 3747 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3748 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
cc6e7c44
RA		 3749 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3750 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3751 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3752 writeq(val64, &bar0->xmsi_access);
f61e0a35 3753 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3754 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3755 __func__, msix_index);
cc6e7c44
RA		 3756 continue;
3757 }
3758 }
3759}
3760
1ee6dd77 3761static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3762{
1ee6dd77 3763 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3764 u64 val64, addr, data;
f61e0a35
SH		 3765 int i, msix_index;
3766
3767 if (nic->device_type == XFRAME_I_DEVICE)
3768 return;
cc6e7c44
RA		 3769
3770 /* Store and display */
d44570e4
JP		 3771 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3772 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
f61e0a35 3773 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3774 writeq(val64, &bar0->xmsi_access);
f61e0a35 3775 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3776 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3777 __func__, msix_index);
cc6e7c44
RA		 3778 continue;
3779 }
3780 addr = readq(&bar0->xmsi_address);
3781 data = readq(&bar0->xmsi_data);
3782 if (addr && data) {
3783 nic->msix_info[i].addr = addr;
3784 nic->msix_info[i].data = data;
3785 }
3786 }
3787}
3788
1ee6dd77 3789static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3790{
1ee6dd77 3791 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3792 u64 rx_mat;
cc6e7c44
RA		 3793 u16 msi_control; /* Temp variable */
3794 int ret, i, j, msix_indx = 1;
4f870320 3795 int size;
ffb5df6c
JP		 3796 struct stat_block *stats = nic->mac_control.stats_info;
3797 struct swStat *swstats = &stats->sw_stat;
cc6e7c44 3798
4f870320 3799 size = nic->num_entries * sizeof(struct msix_entry);
44364a03 3800 nic->entries = kzalloc(size, GFP_KERNEL);
bd684e43 3801 if (!nic->entries) {
d44570e4
JP		 3802 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3803 __func__);
ffb5df6c 3804 swstats->mem_alloc_fail_cnt++;
cc6e7c44
RA		 3805 return -ENOMEM;
3806 }
ffb5df6c 3807 swstats->mem_allocated += size;
f61e0a35 3808
4f870320 3809 size = nic->num_entries * sizeof(struct s2io_msix_entry);
44364a03 3810 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
bd684e43 3811 if (!nic->s2io_entries) {
8a4bdbaa 3812 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
d44570e4 3813 __func__);
ffb5df6c 3814 swstats->mem_alloc_fail_cnt++;
cc6e7c44 3815 kfree(nic->entries);
ffb5df6c 3816 swstats->mem_freed
f61e0a35 3817 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3818 return -ENOMEM;
3819 }
ffb5df6c 3820 swstats->mem_allocated += size;
cc6e7c44 3821
ac731ab6
SH		 3822 nic->entries[0].entry = 0;
3823 nic->s2io_entries[0].entry = 0;
3824 nic->s2io_entries[0].in_use = MSIX_FLG;
3825 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3826 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3827
f61e0a35
SH		 3828 for (i = 1; i < nic->num_entries; i++) {
3829 nic->entries[i].entry = ((i - 1) * 8) + 1;
3830 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3831 nic->s2io_entries[i].arg = NULL;
3832 nic->s2io_entries[i].in_use = 0;
3833 }
3834
8a4bdbaa 3835 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3836 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3837 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3838 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3839 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3840 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3841 msix_indx += 8;
cc6e7c44 3842 }
8a4bdbaa 3843 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3844 readq(&bar0->rx_mat);
cc6e7c44 3845
f61e0a35 3846 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3847 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3848 if (ret) {
9e39f7c5 3849 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
cc6e7c44 3850 kfree(nic->entries);
ffb5df6c
JP		 3851 swstats->mem_freed += nic->num_entries *
3852 sizeof(struct msix_entry);
cc6e7c44 3853 kfree(nic->s2io_entries);
ffb5df6c
JP		 3854 swstats->mem_freed += nic->num_entries *
3855 sizeof(struct s2io_msix_entry);
cc6e7c44
RA		 3856 nic->entries = NULL;
3857 nic->s2io_entries = NULL;
3858 return -ENOMEM;
3859 }
3860
3861 /*
3862 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3863 * in the herc NIC. (Temp change, needs to be removed later)
3864 */
3865 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3866 msi_control |= 0x1; /* Enable MSI */
3867 pci_write_config_word(nic->pdev, 0x42, msi_control);
3868
3869 return 0;
3870}
3871
8abc4d5b 3872/* Handle software interrupt used during MSI(X) test */
33390a70 3873static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3874{
3875 struct s2io_nic *sp = dev_id;
3876
3877 sp->msi_detected = 1;
3878 wake_up(&sp->msi_wait);
3879
3880 return IRQ_HANDLED;
3881}
3882
3883/* Test interrupt path by forcing a a software IRQ */
33390a70 3884static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3885{
3886 struct pci_dev *pdev = sp->pdev;
3887 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3888 int err;
3889 u64 val64, saved64;
3890
3891 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
d44570e4 3892 sp->name, sp);
8abc4d5b
SS		 3893 if (err) {
3894 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
d44570e4 3895 sp->dev->name, pci_name(pdev), pdev->irq);
8abc4d5b
SS		 3896 return err;
3897 }
3898
d44570e4 3899 init_waitqueue_head(&sp->msi_wait);
8abc4d5b
SS		 3900 sp->msi_detected = 0;
3901
3902 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3903 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3904 val64 |= SCHED_INT_CTRL_TIMER_EN;
3905 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3906 writeq(val64, &bar0->scheduled_int_ctrl);
3907
3908 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3909
3910 if (!sp->msi_detected) {
3911 /* MSI(X) test failed, go back to INTx mode */
2450022a 3912 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
9e39f7c5
JP		 3913 "using MSI(X) during test\n",
3914 sp->dev->name, pci_name(pdev));
8abc4d5b
SS		 3915
3916 err = -EOPNOTSUPP;
3917 }
3918
3919 free_irq(sp->entries[1].vector, sp);
3920
3921 writeq(saved64, &bar0->scheduled_int_ctrl);
3922
3923 return err;
3924}
18b2b7bd
SH		 3925
3926static void remove_msix_isr(struct s2io_nic *sp)
3927{
3928 int i;
3929 u16 msi_control;
3930
f61e0a35 3931 for (i = 0; i < sp->num_entries; i++) {
d44570e4 3932 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
18b2b7bd
SH		 3933 int vector = sp->entries[i].vector;
3934 void *arg = sp->s2io_entries[i].arg;
3935 free_irq(vector, arg);
3936 }
3937 }
3938
3939 kfree(sp->entries);
3940 kfree(sp->s2io_entries);
3941 sp->entries = NULL;
3942 sp->s2io_entries = NULL;
3943
3944 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3945 msi_control &= 0xFFFE; /* Disable MSI */
3946 pci_write_config_word(sp->pdev, 0x42, msi_control);
3947
3948 pci_disable_msix(sp->pdev);
3949}
3950
3951static void remove_inta_isr(struct s2io_nic *sp)
3952{
3953 struct net_device *dev = sp->dev;
3954
3955 free_irq(sp->pdev->irq, dev);
3956}
3957
1da177e4
LT		 3958/* ********************************************************* *
3959 * Functions defined below concern the OS part of the driver *
3960 * ********************************************************* */
3961
20346722 3962/**
1da177e4
LT		 3963 * s2io_open - open entry point of the driver
3964 * @dev : pointer to the device structure.
3965 * Description:
3966 * This function is the open entry point of the driver. It mainly calls a
3967 * function to allocate Rx buffers and inserts them into the buffer
20346722 3968 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3969 * Return value:
3970 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3971 * file on failure.
3972 */
3973
ac1f60db 3974static int s2io_open(struct net_device *dev)
1da177e4 3975{
4cf1653a 3976 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 3977 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 3978 int err = 0;
3979
20346722 3980 /*
3981 * Make sure you have link off by default every time
1da177e4
LT		 3982 * Nic is initialized
3983 */
3984 netif_carrier_off(dev);
0b1f7ebe 3985 sp->last_link_state = 0;
1da177e4
LT		 3986
3987 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3988 err = s2io_card_up(sp);
3989 if (err) {
1da177e4
LT		 3990 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3991 dev->name);
e6a8fee2 3992 goto hw_init_failed;
1da177e4
LT		 3993 }
3994
2fd37688 3995 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 3996 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3997 s2io_card_down(sp);
20346722 3998 err = -ENODEV;
e6a8fee2 3999 goto hw_init_failed;
1da177e4 4000 }
3a3d5756 4001 s2io_start_all_tx_queue(sp);
1da177e4 4002 return 0;
20346722 4003
20346722 4004hw_init_failed:
eaae7f72 4005 if (sp->config.intr_type == MSI_X) {
491976b2 4006 if (sp->entries) {
cc6e7c44 4007 kfree(sp->entries);
ffb5df6c
JP		 4008 swstats->mem_freed += sp->num_entries *
4009 sizeof(struct msix_entry);
491976b2
SH		 4010 }
4011 if (sp->s2io_entries) {
cc6e7c44 4012 kfree(sp->s2io_entries);
ffb5df6c
JP		 4013 swstats->mem_freed += sp->num_entries *
4014 sizeof(struct s2io_msix_entry);
491976b2 4015 }
cc6e7c44 4016 }
20346722 4017 return err;
1da177e4
LT		 4018}
4019
4020/**
4021 * s2io_close -close entry point of the driver
4022 * @dev : device pointer.
4023 * Description:
4024 * This is the stop entry point of the driver. It needs to undo exactly
4025 * whatever was done by the open entry point,thus it's usually referred to
4026 * as the close function.Among other things this function mainly stops the
4027 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4028 * Return value:
4029 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4030 * file on failure.
4031 */
4032
ac1f60db 4033static int s2io_close(struct net_device *dev)
1da177e4 4034{
4cf1653a 4035 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4036 struct config_param *config = &sp->config;
4037 u64 tmp64;
4038 int offset;
cc6e7c44 4039
9f74ffde 4040 /* Return if the device is already closed *
d44570e4
JP		 4041 * Can happen when s2io_card_up failed in change_mtu *
4042 */
9f74ffde
SH		 4043 if (!is_s2io_card_up(sp))
4044 return 0;
4045
3a3d5756 4046 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4047 /* delete all populated mac entries */
4048 for (offset = 1; offset < config->max_mc_addr; offset++) {
4049 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4050 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4051 do_s2io_delete_unicast_mc(sp, tmp64);
4052 }
4053
e6a8fee2 4054 s2io_card_down(sp);
cc6e7c44 4055
1da177e4
LT		 4056 return 0;
4057}
4058
4059/**
4060 * s2io_xmit - Tx entry point of te driver
4061 * @skb : the socket buffer containing the Tx data.
4062 * @dev : device pointer.
4063 * Description :
4064 * This function is the Tx entry point of the driver. S2IO NIC supports
4065 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
25985edc 4066 * NOTE: when device can't queue the pkt,just the trans_start variable will
1da177e4
LT		 4067 * not be upadted.
4068 * Return value:
4069 * 0 on success & 1 on failure.
4070 */
4071
61357325 4072static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4073{
4cf1653a 4074 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4075 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4076 register u64 val64;
1ee6dd77
RB		 4077 struct TxD *txdp;
4078 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4079 unsigned long flags = 0;
be3a6b02 4080 u16 vlan_tag = 0;
2fda096d 4081 struct fifo_info *fifo = NULL;
6cfc482b 4082 int do_spin_lock = 1;
75c30b13 4083 int offload_type;
6cfc482b 4084 int enable_per_list_interrupt = 0;
ffb5df6c
JP		 4085 struct config_param *config = &sp->config;
4086 struct mac_info *mac_control = &sp->mac_control;
4087 struct stat_block *stats = mac_control->stats_info;
4088 struct swStat *swstats = &stats->sw_stat;
1da177e4 4089
20346722 4090 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4091
4092 if (unlikely(skb->len <= 0)) {
9e39f7c5 4093 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
491976b2 4094 dev_kfree_skb_any(skb);
6ed10654 4095 return NETDEV_TX_OK;
2fda096d 4096 }
491976b2 4097
92b84437 4098 if (!is_s2io_card_up(sp)) {
20346722 4099 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4100 dev->name);
20346722 4101 dev_kfree_skb(skb);
6ed10654 4102 return NETDEV_TX_OK;
1da177e4
LT		 4103 }
4104
4105 queue = 0;
eab6d18d 4106 if (vlan_tx_tag_present(skb))
be3a6b02 4107 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4108 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4109 if (skb->protocol == htons(ETH_P_IP)) {
4110 struct iphdr *ip;
4111 struct tcphdr *th;
4112 ip = ip_hdr(skb);
4113
4114 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4115 th = (struct tcphdr *)(((unsigned char *)ip) +
d44570e4 4116 ip->ihl*4);
6cfc482b
SH		 4117
4118 if (ip->protocol == IPPROTO_TCP) {
4119 queue_len = sp->total_tcp_fifos;
4120 queue = (ntohs(th->source) +
d44570e4
JP		 4121 ntohs(th->dest)) &
4122 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4123 if (queue >= queue_len)
4124 queue = queue_len - 1;
4125 } else if (ip->protocol == IPPROTO_UDP) {
4126 queue_len = sp->total_udp_fifos;
4127 queue = (ntohs(th->source) +
d44570e4
JP		 4128 ntohs(th->dest)) &
4129 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4130 if (queue >= queue_len)
4131 queue = queue_len - 1;
4132 queue += sp->udp_fifo_idx;
4133 if (skb->len > 1024)
4134 enable_per_list_interrupt = 1;
4135 do_spin_lock = 0;
4136 }
4137 }
4138 }
4139 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4140 /* get fifo number based on skb->priority value */
4141 queue = config->fifo_mapping
d44570e4 4142 [skb->priority & (MAX_TX_FIFOS - 1)];
6cfc482b 4143 fifo = &mac_control->fifos[queue];
3a3d5756 4144
6cfc482b
SH		 4145 if (do_spin_lock)
4146 spin_lock_irqsave(&fifo->tx_lock, flags);
4147 else {
4148 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4149 return NETDEV_TX_LOCKED;
4150 }
be3a6b02 4151
3a3d5756
SH		 4152 if (sp->config.multiq) {
4153 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4154 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4155 return NETDEV_TX_BUSY;
4156 }
b19fa1fa 4157 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4158 if (netif_queue_stopped(dev)) {
4159 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4160 return NETDEV_TX_BUSY;
4161 }
4162 }
4163
d44570e4
JP		 4164 put_off = (u16)fifo->tx_curr_put_info.offset;
4165 get_off = (u16)fifo->tx_curr_get_info.offset;
4166 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
20346722 4167
2fda096d 4168 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4169 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4170 if (txdp->Host_Control ||
d44570e4 4171 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4172 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4173 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4174 dev_kfree_skb(skb);
2fda096d 4175 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4176 return NETDEV_TX_OK;
1da177e4 4177 }
0b1f7ebe 4178
75c30b13 4179 offload_type = s2io_offload_type(skb);
75c30b13 4180 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4181 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4182 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4183 }
84fa7933 4184 if (skb->ip_summed == CHECKSUM_PARTIAL) {
d44570e4
JP		 4185 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4186 TXD_TX_CKO_TCP_EN |
4187 TXD_TX_CKO_UDP_EN);
1da177e4 4188 }
fed5eccd
AR		 4189 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4190 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4191 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4192 if (enable_per_list_interrupt)
4193 if (put_off & (queue_len >> 5))
4194 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4195 if (vlan_tag) {
be3a6b02 4196 txdp->Control_2 |= TXD_VLAN_ENABLE;
4197 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4198 }
4199
e743d313 4200 frg_len = skb_headlen(skb);
75c30b13 4201 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4202 int ufo_size;
4203
75c30b13 4204 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4205 ufo_size &= ~7;
4206 txdp->Control_1 |= TXD_UFO_EN;
4207 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4208 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4209#ifdef __BIG_ENDIAN
3459feb8 4210 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4211 fifo->ufo_in_band_v[put_off] =
d44570e4 4212 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4213#else
2fda096d 4214 fifo->ufo_in_band_v[put_off] =
d44570e4 4215 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4216#endif
2fda096d 4217 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4218 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
d44570e4
JP		 4219 fifo->ufo_in_band_v,
4220 sizeof(u64),
4221 PCI_DMA_TODEVICE);
8d8bb39b 4222 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4223 goto pci_map_failed;
fed5eccd 4224 txdp++;
fed5eccd 4225 }
1da177e4 4226
d44570e4
JP		 4227 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4228 frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4229 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4230 goto pci_map_failed;
4231
d44570e4 4232 txdp->Host_Control = (unsigned long)skb;
fed5eccd 4233 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4234 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4235 txdp->Control_1 |= TXD_UFO_EN;
4236
4237 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4238 /* For fragmented SKB. */
4239 for (i = 0; i < frg_cnt; i++) {
4240 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe 4241 /* A '0' length fragment will be ignored */
4242 if (!frag->size)
4243 continue;
1da177e4 4244 txdp++;
d44570e4
JP		 4245 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4246 frag->page_offset,
4247 frag->size,
4248 PCI_DMA_TODEVICE);
efd51b5c 4249 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4250 if (offload_type == SKB_GSO_UDP)
fed5eccd 4251 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4252 }
4253 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4254
75c30b13 4255 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4256 frg_cnt++; /* as Txd0 was used for inband header */
4257
1da177e4 4258 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4259 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4260 writeq(val64, &tx_fifo->TxDL_Pointer);
4261
4262 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4263 TX_FIFO_LAST_LIST);
75c30b13 4264 if (offload_type)
fed5eccd 4265 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4266
1da177e4
LT		 4267 writeq(val64, &tx_fifo->List_Control);
4268
303bcb4b 4269 mmiowb();
4270
1da177e4 4271 put_off++;
2fda096d 4272 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4273 put_off = 0;
2fda096d 4274 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4275
4276 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4277 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
ffb5df6c 4278 swstats->fifo_full_cnt++;
1da177e4
LT		 4279 DBG_PRINT(TX_DBG,
4280 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4281 put_off, get_off);
3a3d5756 4282 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4283 }
ffb5df6c 4284 swstats->mem_allocated += skb->truesize;
2fda096d 4285 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4286
f6f4bfa3
SH		 4287 if (sp->config.intr_type == MSI_X)
4288 tx_intr_handler(fifo);
4289
6ed10654 4290 return NETDEV_TX_OK;
ffb5df6c 4291
491abf25 4292pci_map_failed:
ffb5df6c 4293 swstats->pci_map_fail_cnt++;
3a3d5756 4294 s2io_stop_tx_queue(sp, fifo->fifo_no);
ffb5df6c 4295 swstats->mem_freed += skb->truesize;
491abf25 4296 dev_kfree_skb(skb);
2fda096d 4297 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4298 return NETDEV_TX_OK;
1da177e4
LT		 4299}
4300
25fff88e 4301static void
4302s2io_alarm_handle(unsigned long data)
4303{
1ee6dd77 4304 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4305 struct net_device *dev = sp->dev;
25fff88e 4306
8116f3cf 4307 s2io_handle_errors(dev);
25fff88e 4308 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4309}
4310
7d12e780 4311static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4312{
1ee6dd77
RB		 4313 struct ring_info *ring = (struct ring_info *)dev_id;
4314 struct s2io_nic *sp = ring->nic;
f61e0a35 4315 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4316
f61e0a35 4317 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4318 return IRQ_HANDLED;
92b84437 4319
f61e0a35 4320 if (sp->config.napi) {
1a79d1c3
AV		 4321 u8 __iomem *addr = NULL;
4322 u8 val8 = 0;
f61e0a35 4323
1a79d1c3 4324 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4325 addr += (7 - ring->ring_no);
4326 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4327 writeb(val8, addr);
4328 val8 = readb(addr);
288379f0 4329 napi_schedule(&ring->napi);
f61e0a35
SH		 4330 } else {
4331 rx_intr_handler(ring, 0);
8d8bb39b 4332 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4333 }
7d3d0439 4334
cc6e7c44
RA		 4335 return IRQ_HANDLED;
4336}
4337
7d12e780 4338static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4339{
ac731ab6
SH		 4340 int i;
4341 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4342 struct s2io_nic *sp = fifos->nic;
4343 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4344 struct config_param *config = &sp->config;
4345 u64 reason;
cc6e7c44 4346
ac731ab6
SH		 4347 if (unlikely(!is_s2io_card_up(sp)))
4348 return IRQ_NONE;
4349
4350 reason = readq(&bar0->general_int_status);
4351 if (unlikely(reason == S2IO_MINUS_ONE))
4352 /* Nothing much can be done. Get out */
92b84437 4353 return IRQ_HANDLED;
92b84437 4354
01e16faa
SH		 4355 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4356 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4357
01e16faa
SH		 4358 if (reason & GEN_INTR_TXPIC)
4359 s2io_txpic_intr_handle(sp);
ac731ab6 4360
01e16faa
SH		 4361 if (reason & GEN_INTR_TXTRAFFIC)
4362 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4363
01e16faa
SH		 4364 for (i = 0; i < config->tx_fifo_num; i++)
4365 tx_intr_handler(&fifos[i]);
ac731ab6 4366
01e16faa
SH		 4367 writeq(sp->general_int_mask, &bar0->general_int_mask);
4368 readl(&bar0->general_int_status);
4369 return IRQ_HANDLED;
4370 }
4371 /* The interrupt was not raised by us */
4372 return IRQ_NONE;
cc6e7c44 4373}
ac731ab6 4374
1ee6dd77 4375static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4376{
1ee6dd77 4377 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d 4378 u64 val64;
4379
4380 val64 = readq(&bar0->pic_int_status);
4381 if (val64 & PIC_INT_GPIO) {
4382 val64 = readq(&bar0->gpio_int_reg);
4383 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4384 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4385 /*
4386 * This is unstable state so clear both up/down
4387 * interrupt and adapter to re-evaluate the link state.
4388 */
d44570e4 4389 val64 |= GPIO_INT_REG_LINK_DOWN;
a371a07d 4390 val64 |= GPIO_INT_REG_LINK_UP;
4391 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4392 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4393 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4394 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4395 writeq(val64, &bar0->gpio_int_mask);
d44570e4 4396 } else if (val64 & GPIO_INT_REG_LINK_UP) {
c92ca04b 4397 val64 = readq(&bar0->adapter_status);
d44570e4 4398 /* Enable Adapter */
19a60522
SS		 4399 val64 = readq(&bar0->adapter_control);
4400 val64 |= ADAPTER_CNTL_EN;
4401 writeq(val64, &bar0->adapter_control);
4402 val64 |= ADAPTER_LED_ON;
4403 writeq(val64, &bar0->adapter_control);
4404 if (!sp->device_enabled_once)
4405 sp->device_enabled_once = 1;
c92ca04b 4406
19a60522
SS		 4407 s2io_link(sp, LINK_UP);
4408 /*
4409 * unmask link down interrupt and mask link-up
4410 * intr
4411 */
4412 val64 = readq(&bar0->gpio_int_mask);
4413 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4414 val64 |= GPIO_INT_MASK_LINK_UP;
4415 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4416
d44570e4 4417 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
c92ca04b 4418 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4419 s2io_link(sp, LINK_DOWN);
4420 /* Link is down so unmaks link up interrupt */
4421 val64 = readq(&bar0->gpio_int_mask);
4422 val64 &= ~GPIO_INT_MASK_LINK_UP;
4423 val64 |= GPIO_INT_MASK_LINK_DOWN;
4424 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4425
4426 /* turn off LED */
4427 val64 = readq(&bar0->adapter_control);
d44570e4 4428 val64 = val64 & (~ADAPTER_LED_ON);
ac1f90d6 4429 writeq(val64, &bar0->adapter_control);
a371a07d 4430 }
4431 }
c92ca04b 4432 val64 = readq(&bar0->gpio_int_mask);
a371a07d 4433}
4434
8116f3cf
SS		 4435/**
4436 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4437 * @value: alarm bits
4438 * @addr: address value
4439 * @cnt: counter variable
4440 * Description: Check for alarm and increment the counter
4441 * Return Value:
4442 * 1 - if alarm bit set
4443 * 0 - if alarm bit is not set
4444 */
d44570e4
JP		 4445static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4446 unsigned long long *cnt)
8116f3cf
SS		 4447{
4448 u64 val64;
4449 val64 = readq(addr);
d44570e4 4450 if (val64 & value) {
8116f3cf
SS		 4451 writeq(val64, addr);
4452 (*cnt)++;
4453 return 1;
4454 }
4455 return 0;
4456
4457}
4458
4459/**
4460 * s2io_handle_errors - Xframe error indication handler
4461 * @nic: device private variable
4462 * Description: Handle alarms such as loss of link, single or
4463 * double ECC errors, critical and serious errors.
4464 * Return Value:
4465 * NONE
4466 */
d44570e4 4467static void s2io_handle_errors(void *dev_id)
8116f3cf 4468{
d44570e4 4469 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4470 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf 4471 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d44570e4 4472 u64 temp64 = 0, val64 = 0;
8116f3cf
SS		 4473 int i = 0;
4474
4475 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4476 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4477
92b84437 4478 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4479 return;
4480
4481 if (pci_channel_offline(sp->pdev))
4482 return;
4483
4484 memset(&sw_stat->ring_full_cnt, 0,
d44570e4 4485 sizeof(sw_stat->ring_full_cnt));
8116f3cf
SS		 4486
4487 /* Handling the XPAK counters update */
d44570e4 4488 if (stats->xpak_timer_count < 72000) {
8116f3cf
SS		 4489 /* waiting for an hour */
4490 stats->xpak_timer_count++;
4491 } else {
4492 s2io_updt_xpak_counter(dev);
4493 /* reset the count to zero */
4494 stats->xpak_timer_count = 0;
4495 }
4496
4497 /* Handling link status change error Intr */
4498 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4499 val64 = readq(&bar0->mac_rmac_err_reg);
4500 writeq(val64, &bar0->mac_rmac_err_reg);
4501 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4502 schedule_work(&sp->set_link_task);
4503 }
4504
4505 /* In case of a serious error, the device will be Reset. */
4506 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
d44570e4 4507 &sw_stat->serious_err_cnt))
8116f3cf
SS		 4508 goto reset;
4509
4510 /* Check for data parity error */
4511 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
d44570e4 4512 &sw_stat->parity_err_cnt))
8116f3cf
SS		 4513 goto reset;
4514
4515 /* Check for ring full counter */
4516 if (sp->device_type == XFRAME_II_DEVICE) {
4517 val64 = readq(&bar0->ring_bump_counter1);
d44570e4
JP		 4518 for (i = 0; i < 4; i++) {
4519 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf
SS		 4520 temp64 >>= 64 - ((i+1)*16);
4521 sw_stat->ring_full_cnt[i] += temp64;
4522 }
4523
4524 val64 = readq(&bar0->ring_bump_counter2);
d44570e4
JP		 4525 for (i = 0; i < 4; i++) {
4526 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf 4527 temp64 >>= 64 - ((i+1)*16);
d44570e4 4528 sw_stat->ring_full_cnt[i+4] += temp64;
8116f3cf
SS		 4529 }
4530 }
4531
4532 val64 = readq(&bar0->txdma_int_status);
4533 /*check for pfc_err*/
4534 if (val64 & TXDMA_PFC_INT) {
d44570e4
JP		 4535 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4536 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4537 PFC_PCIX_ERR,
4538 &bar0->pfc_err_reg,
4539 &sw_stat->pfc_err_cnt))
8116f3cf 4540 goto reset;
d44570e4
JP		 4541 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4542 &bar0->pfc_err_reg,
4543 &sw_stat->pfc_err_cnt);
8116f3cf
SS		 4544 }
4545
4546 /*check for tda_err*/
4547 if (val64 & TXDMA_TDA_INT) {
d44570e4
JP		 4548 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4549 TDA_SM0_ERR_ALARM |
4550 TDA_SM1_ERR_ALARM,
4551 &bar0->tda_err_reg,
4552 &sw_stat->tda_err_cnt))
8116f3cf
SS		 4553 goto reset;
4554 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
d44570e4
JP		 4555 &bar0->tda_err_reg,
4556 &sw_stat->tda_err_cnt);
8116f3cf
SS		 4557 }
4558 /*check for pcc_err*/
4559 if (val64 & TXDMA_PCC_INT) {
d44570e4
JP		 4560 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4561 PCC_N_SERR | PCC_6_COF_OV_ERR |
4562 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4563 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4564 PCC_TXB_ECC_DB_ERR,
4565 &bar0->pcc_err_reg,
4566 &sw_stat->pcc_err_cnt))
8116f3cf
SS		 4567 goto reset;
4568 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
d44570e4
JP		 4569 &bar0->pcc_err_reg,
4570 &sw_stat->pcc_err_cnt);
8116f3cf
SS		 4571 }
4572
4573 /*check for tti_err*/
4574 if (val64 & TXDMA_TTI_INT) {
d44570e4
JP		 4575 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4576 &bar0->tti_err_reg,
4577 &sw_stat->tti_err_cnt))
8116f3cf
SS		 4578 goto reset;
4579 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
d44570e4
JP		 4580 &bar0->tti_err_reg,
4581 &sw_stat->tti_err_cnt);
8116f3cf
SS		 4582 }
4583
4584 /*check for lso_err*/
4585 if (val64 & TXDMA_LSO_INT) {
d44570e4
JP		 4586 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4587 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4588 &bar0->lso_err_reg,
4589 &sw_stat->lso_err_cnt))
8116f3cf
SS		 4590 goto reset;
4591 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
d44570e4
JP		 4592 &bar0->lso_err_reg,
4593 &sw_stat->lso_err_cnt);
8116f3cf
SS		 4594 }
4595
4596 /*check for tpa_err*/
4597 if (val64 & TXDMA_TPA_INT) {
d44570e4
JP		 4598 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4599 &bar0->tpa_err_reg,
4600 &sw_stat->tpa_err_cnt))
8116f3cf 4601 goto reset;
d44570e4
JP		 4602 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4603 &bar0->tpa_err_reg,
4604 &sw_stat->tpa_err_cnt);
8116f3cf
SS		 4605 }
4606
4607 /*check for sm_err*/
4608 if (val64 & TXDMA_SM_INT) {
d44570e4
JP		 4609 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4610 &bar0->sm_err_reg,
4611 &sw_stat->sm_err_cnt))
8116f3cf
SS		 4612 goto reset;
4613 }
4614
4615 val64 = readq(&bar0->mac_int_status);
4616 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4617 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
d44570e4
JP		 4618 &bar0->mac_tmac_err_reg,
4619 &sw_stat->mac_tmac_err_cnt))
8116f3cf 4620 goto reset;
d44570e4
JP		 4621 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4622 TMAC_DESC_ECC_SG_ERR |
4623 TMAC_DESC_ECC_DB_ERR,
4624 &bar0->mac_tmac_err_reg,
4625 &sw_stat->mac_tmac_err_cnt);
8116f3cf
SS		 4626 }
4627
4628 val64 = readq(&bar0->xgxs_int_status);
4629 if (val64 & XGXS_INT_STATUS_TXGXS) {
4630 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
d44570e4
JP		 4631 &bar0->xgxs_txgxs_err_reg,
4632 &sw_stat->xgxs_txgxs_err_cnt))
8116f3cf
SS		 4633 goto reset;
4634 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
d44570e4
JP		 4635 &bar0->xgxs_txgxs_err_reg,
4636 &sw_stat->xgxs_txgxs_err_cnt);
8116f3cf
SS		 4637 }
4638
4639 val64 = readq(&bar0->rxdma_int_status);
4640 if (val64 & RXDMA_INT_RC_INT_M) {
d44570e4
JP		 4641 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4642 RC_FTC_ECC_DB_ERR |
4643 RC_PRCn_SM_ERR_ALARM |
4644 RC_FTC_SM_ERR_ALARM,
4645 &bar0->rc_err_reg,
4646 &sw_stat->rc_err_cnt))
8116f3cf 4647 goto reset;
d44570e4
JP		 4648 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4649 RC_FTC_ECC_SG_ERR |
4650 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4651 &sw_stat->rc_err_cnt);
4652 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4653 PRC_PCI_AB_WR_Rn |
4654 PRC_PCI_AB_F_WR_Rn,
4655 &bar0->prc_pcix_err_reg,
4656 &sw_stat->prc_pcix_err_cnt))
8116f3cf 4657 goto reset;
d44570e4
JP		 4658 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4659 PRC_PCI_DP_WR_Rn |
4660 PRC_PCI_DP_F_WR_Rn,
4661 &bar0->prc_pcix_err_reg,
4662 &sw_stat->prc_pcix_err_cnt);
8116f3cf
SS		 4663 }
4664
4665 if (val64 & RXDMA_INT_RPA_INT_M) {
4666 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
d44570e4
JP		 4667 &bar0->rpa_err_reg,
4668 &sw_stat->rpa_err_cnt))
8116f3cf
SS		 4669 goto reset;
4670 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
d44570e4
JP		 4671 &bar0->rpa_err_reg,
4672 &sw_stat->rpa_err_cnt);
8116f3cf
SS		 4673 }
4674
4675 if (val64 & RXDMA_INT_RDA_INT_M) {
d44570e4
JP		 4676 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4677 RDA_FRM_ECC_DB_N_AERR |
4678 RDA_SM1_ERR_ALARM |
4679 RDA_SM0_ERR_ALARM |
4680 RDA_RXD_ECC_DB_SERR,
4681 &bar0->rda_err_reg,
4682 &sw_stat->rda_err_cnt))
8116f3cf 4683 goto reset;
d44570e4
JP		 4684 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4685 RDA_FRM_ECC_SG_ERR |
4686 RDA_MISC_ERR |
4687 RDA_PCIX_ERR,
4688 &bar0->rda_err_reg,
4689 &sw_stat->rda_err_cnt);
8116f3cf
SS		 4690 }
4691
4692 if (val64 & RXDMA_INT_RTI_INT_M) {
d44570e4
JP		 4693 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4694 &bar0->rti_err_reg,
4695 &sw_stat->rti_err_cnt))
8116f3cf
SS		 4696 goto reset;
4697 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
d44570e4
JP		 4698 &bar0->rti_err_reg,
4699 &sw_stat->rti_err_cnt);
8116f3cf
SS		 4700 }
4701
4702 val64 = readq(&bar0->mac_int_status);
4703 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4704 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
d44570e4
JP		 4705 &bar0->mac_rmac_err_reg,
4706 &sw_stat->mac_rmac_err_cnt))
8116f3cf 4707 goto reset;
d44570e4
JP		 4708 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4709 RMAC_SINGLE_ECC_ERR |
4710 RMAC_DOUBLE_ECC_ERR,
4711 &bar0->mac_rmac_err_reg,
4712 &sw_stat->mac_rmac_err_cnt);
8116f3cf
SS		 4713 }
4714
4715 val64 = readq(&bar0->xgxs_int_status);
4716 if (val64 & XGXS_INT_STATUS_RXGXS) {
4717 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
d44570e4
JP		 4718 &bar0->xgxs_rxgxs_err_reg,
4719 &sw_stat->xgxs_rxgxs_err_cnt))
8116f3cf
SS		 4720 goto reset;
4721 }
4722
4723 val64 = readq(&bar0->mc_int_status);
d44570e4
JP		 4724 if (val64 & MC_INT_STATUS_MC_INT) {
4725 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4726 &bar0->mc_err_reg,
4727 &sw_stat->mc_err_cnt))
8116f3cf
SS		 4728 goto reset;
4729
4730 /* Handling Ecc errors */
4731 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4732 writeq(val64, &bar0->mc_err_reg);
4733 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4734 sw_stat->double_ecc_errs++;
4735 if (sp->device_type != XFRAME_II_DEVICE) {
4736 /*
4737 * Reset XframeI only if critical error
4738 */
4739 if (val64 &
d44570e4
JP		 4740 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4741 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4742 goto reset;
4743 }
8116f3cf
SS		 4744 } else
4745 sw_stat->single_ecc_errs++;
4746 }
4747 }
4748 return;
4749
4750reset:
3a3d5756 4751 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4752 schedule_work(&sp->rst_timer_task);
4753 sw_stat->soft_reset_cnt++;
8116f3cf
SS		 4754}
4755
1da177e4
LT		 4756/**
4757 * s2io_isr - ISR handler of the device .
4758 * @irq: the irq of the device.
4759 * @dev_id: a void pointer to the dev structure of the NIC.
20346722 4760 * Description: This function is the ISR handler of the device. It
4761 * identifies the reason for the interrupt and calls the relevant
4762 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4763 * recv buffers, if their numbers are below the panic value which is
4764 * presently set to 25% of the original number of rcv buffers allocated.
4765 * Return value:
20346722 4766 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4767 * IRQ_NONE: will be returned if interrupt is not from our device
4768 */
7d12e780 4769static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4 4770{
d44570e4 4771 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4772 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4773 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4774 int i;
19a60522 4775 u64 reason = 0;
1ee6dd77 4776 struct mac_info *mac_control;
1da177e4
LT		 4777 struct config_param *config;
4778
d796fdb7
LV		 4779 /* Pretend we handled any irq's from a disconnected card */
4780 if (pci_channel_offline(sp->pdev))
4781 return IRQ_NONE;
4782
596c5c97 4783 if (!is_s2io_card_up(sp))
92b84437 4784 return IRQ_NONE;
92b84437 4785
1da177e4 4786 config = &sp->config;
ffb5df6c 4787 mac_control = &sp->mac_control;
1da177e4 4788
20346722 4789 /*
1da177e4
LT		 4790 * Identify the cause for interrupt and call the appropriate
4791 * interrupt handler. Causes for the interrupt could be;
4792 * 1. Rx of packet.
4793 * 2. Tx complete.
4794 * 3. Link down.
1da177e4
LT		 4795 */
4796 reason = readq(&bar0->general_int_status);
4797
d44570e4
JP		 4798 if (unlikely(reason == S2IO_MINUS_ONE))
4799 return IRQ_HANDLED; /* Nothing much can be done. Get out */
5d3213cc 4800
d44570e4
JP		 4801 if (reason &
4802 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
596c5c97
SS		 4803 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4804
4805 if (config->napi) {
4806 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4807 napi_schedule(&sp->napi);
f61e0a35
SH		 4808 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4809 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4810 readl(&bar0->rx_traffic_int);
db874e65 4811 }
596c5c97
SS		 4812 } else {
4813 /*
4814 * rx_traffic_int reg is an R1 register, writing all 1's
4815 * will ensure that the actual interrupt causing bit
4816 * get's cleared and hence a read can be avoided.
4817 */
4818 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4819 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97 4820
13d866a9
JP		 4821 for (i = 0; i < config->rx_ring_num; i++) {
4822 struct ring_info *ring = &mac_control->rings[i];
4823
4824 rx_intr_handler(ring, 0);
4825 }
db874e65 4826 }
596c5c97 4827
db874e65 4828 /*
596c5c97 4829 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4830 * will ensure that the actual interrupt causing bit get's
4831 * cleared and hence a read can be avoided.
4832 */
596c5c97
SS		 4833 if (reason & GEN_INTR_TXTRAFFIC)
4834 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4835
596c5c97
SS		 4836 for (i = 0; i < config->tx_fifo_num; i++)
4837 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4838
596c5c97
SS		 4839 if (reason & GEN_INTR_TXPIC)
4840 s2io_txpic_intr_handle(sp);
fe113638 4841
596c5c97
SS		 4842 /*
4843 * Reallocate the buffers from the interrupt handler itself.
4844 */
4845 if (!config->napi) {
13d866a9
JP		 4846 for (i = 0; i < config->rx_ring_num; i++) {
4847 struct ring_info *ring = &mac_control->rings[i];
4848
4849 s2io_chk_rx_buffers(sp, ring);
4850 }
596c5c97
SS		 4851 }
4852 writeq(sp->general_int_mask, &bar0->general_int_mask);
4853 readl(&bar0->general_int_status);
20346722 4854
596c5c97 4855 return IRQ_HANDLED;
db874e65 4856
d44570e4 4857 } else if (!reason) {
596c5c97
SS		 4858 /* The interrupt was not raised by us */
4859 return IRQ_NONE;
4860 }
db874e65 4861
1da177e4
LT		 4862 return IRQ_HANDLED;
4863}
4864
7ba013ac 4865/**
4866 * s2io_updt_stats -
4867 */
1ee6dd77 4868static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4869{
1ee6dd77 4870 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac 4871 u64 val64;
4872 int cnt = 0;
4873
92b84437 4874 if (is_s2io_card_up(sp)) {
7ba013ac 4875 /* Apprx 30us on a 133 MHz bus */
4876 val64 = SET_UPDT_CLICKS(10) |
4877 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4878 writeq(val64, &bar0->stat_cfg);
4879 do {
4880 udelay(100);
4881 val64 = readq(&bar0->stat_cfg);
b7b5a128 4882 if (!(val64 & s2BIT(0)))
7ba013ac 4883 break;
4884 cnt++;
4885 if (cnt == 5)
4886 break; /* Updt failed */
d44570e4 4887 } while (1);
8a4bdbaa 4888 }
7ba013ac 4889}
4890
1da177e4 4891/**
20346722 4892 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4893 * @dev : pointer to the device structure.
4894 * Description:
20346722 4895 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4896 * structure and returns a pointer to the same.
4897 * Return value:
4898 * pointer to the updated net_device_stats structure.
4899 */
ac1f60db 4900static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4901{
4cf1653a 4902 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 4903 struct mac_info *mac_control = &sp->mac_control;
4904 struct stat_block *stats = mac_control->stats_info;
4a490432 4905 u64 delta;
1da177e4 4906
7ba013ac 4907 /* Configure Stats for immediate updt */
4908 s2io_updt_stats(sp);
4909
4a490432
JM		 4910 /* A device reset will cause the on-adapter statistics to be zero'ed.
4911 * This can be done while running by changing the MTU. To prevent the
4912 * system from having the stats zero'ed, the driver keeps a copy of the
4913 * last update to the system (which is also zero'ed on reset). This
4914 * enables the driver to accurately know the delta between the last
4915 * update and the current update.
4916 */
4917 delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4918 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4919 sp->stats.rx_packets += delta;
4920 dev->stats.rx_packets += delta;
4921
4922 delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4923 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4924 sp->stats.tx_packets += delta;
4925 dev->stats.tx_packets += delta;
4926
4927 delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4928 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4929 sp->stats.rx_bytes += delta;
4930 dev->stats.rx_bytes += delta;
4931
4932 delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4933 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4934 sp->stats.tx_bytes += delta;
4935 dev->stats.tx_bytes += delta;
4936
4937 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4938 sp->stats.rx_errors += delta;
4939 dev->stats.rx_errors += delta;
4940
4941 delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4942 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4943 sp->stats.tx_errors += delta;
4944 dev->stats.tx_errors += delta;
4945
4946 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4947 sp->stats.rx_dropped += delta;
4948 dev->stats.rx_dropped += delta;
4949
4950 delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4951 sp->stats.tx_dropped += delta;
4952 dev->stats.tx_dropped += delta;
4953
4954 /* The adapter MAC interprets pause frames as multicast packets, but
4955 * does not pass them up. This erroneously increases the multicast
4956 * packet count and needs to be deducted when the multicast frame count
4957 * is queried.
4958 */
4959 delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4960 le32_to_cpu(stats->rmac_vld_mcst_frms);
4961 delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4962 delta -= sp->stats.multicast;
4963 sp->stats.multicast += delta;
4964 dev->stats.multicast += delta;
1da177e4 4965
4a490432
JM		 4966 delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4967 le32_to_cpu(stats->rmac_usized_frms)) +
4968 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4969 sp->stats.rx_length_errors += delta;
4970 dev->stats.rx_length_errors += delta;
13d866a9 4971
4a490432
JM		 4972 delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4973 sp->stats.rx_crc_errors += delta;
4974 dev->stats.rx_crc_errors += delta;
0425b46a 4975
d44570e4 4976 return &dev->stats;
1da177e4
LT		 4977}
4978
4979/**
4980 * s2io_set_multicast - entry point for multicast address enable/disable.
4981 * @dev : pointer to the device structure
4982 * Description:
20346722 4983 * This function is a driver entry point which gets called by the kernel
4984 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4985 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4986 * determine, if multicast address must be enabled or if promiscuous mode
4987 * is to be disabled etc.
4988 * Return value:
4989 * void.
4990 */
4991
4992static void s2io_set_multicast(struct net_device *dev)
4993{
4994 int i, j, prev_cnt;
22bedad3 4995 struct netdev_hw_addr *ha;
4cf1653a 4996 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4997 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4998 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
d44570e4 4999 0xfeffffffffffULL;
faa4f796 5000 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 5001 void __iomem *add;
faa4f796 5002 struct config_param *config = &sp->config;
1da177e4
LT		 5003
5004 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
5005 /* Enable all Multicast addresses */
5006 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
5007 &bar0->rmac_addr_data0_mem);
5008 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
5009 &bar0->rmac_addr_data1_mem);
5010 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5011 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5012 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 5013 writeq(val64, &bar0->rmac_addr_cmd_mem);
5014 /* Wait till command completes */
c92ca04b 5015 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5016 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5017 S2IO_BIT_RESET);
1da177e4
LT		 5018
5019 sp->m_cast_flg = 1;
faa4f796 5020 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 5021 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5022 /* Disable all Multicast addresses */
5023 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5024 &bar0->rmac_addr_data0_mem);
5e25b9dd 5025 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5026 &bar0->rmac_addr_data1_mem);
1da177e4 5027 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5028 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5029 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
1da177e4
LT		 5030 writeq(val64, &bar0->rmac_addr_cmd_mem);
5031 /* Wait till command completes */
c92ca04b 5032 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5033 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5034 S2IO_BIT_RESET);
1da177e4
LT		 5035
5036 sp->m_cast_flg = 0;
5037 sp->all_multi_pos = 0;
5038 }
5039
5040 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5041 /* Put the NIC into promiscuous mode */
5042 add = &bar0->mac_cfg;
5043 val64 = readq(&bar0->mac_cfg);
5044 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5045
5046 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5047 writel((u32)val64, add);
1da177e4
LT		 5048 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5049 writel((u32) (val64 >> 32), (add + 4));
5050
926930b2
SS		 5051 if (vlan_tag_strip != 1) {
5052 val64 = readq(&bar0->rx_pa_cfg);
5053 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5054 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5055 sp->vlan_strip_flag = 0;
926930b2
SS		 5056 }
5057
1da177e4
LT		 5058 val64 = readq(&bar0->mac_cfg);
5059 sp->promisc_flg = 1;
776bd20f 5060 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5061 dev->name);
5062 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5063 /* Remove the NIC from promiscuous mode */
5064 add = &bar0->mac_cfg;
5065 val64 = readq(&bar0->mac_cfg);
5066 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5067
5068 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5069 writel((u32)val64, add);
1da177e4
LT		 5070 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5071 writel((u32) (val64 >> 32), (add + 4));
5072
926930b2
SS		 5073 if (vlan_tag_strip != 0) {
5074 val64 = readq(&bar0->rx_pa_cfg);
5075 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5076 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5077 sp->vlan_strip_flag = 1;
926930b2
SS		 5078 }
5079
1da177e4
LT		 5080 val64 = readq(&bar0->mac_cfg);
5081 sp->promisc_flg = 0;
9e39f7c5 5082 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
1da177e4
LT		 5083 }
5084
5085 /* Update individual M_CAST address list */
4cd24eaf
JP		 5086 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5087 if (netdev_mc_count(dev) >
faa4f796 5088 (config->max_mc_addr - config->max_mac_addr)) {
9e39f7c5
JP		 5089 DBG_PRINT(ERR_DBG,
5090 "%s: No more Rx filters can be added - "
5091 "please enable ALL_MULTI instead\n",
1da177e4 5092 dev->name);
1da177e4
LT		 5093 return;
5094 }
5095
5096 prev_cnt = sp->mc_addr_count;
4cd24eaf 5097 sp->mc_addr_count = netdev_mc_count(dev);
1da177e4
LT		 5098
5099 /* Clear out the previous list of Mc in the H/W. */
5100 for (i = 0; i < prev_cnt; i++) {
5101 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5102 &bar0->rmac_addr_data0_mem);
5103 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5104 &bar0->rmac_addr_data1_mem);
1da177e4 5105 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5106 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5107 RMAC_ADDR_CMD_MEM_OFFSET
5108 (config->mc_start_offset + i);
1da177e4
LT		 5109 writeq(val64, &bar0->rmac_addr_cmd_mem);
5110
5111 /* Wait for command completes */
c92ca04b 5112 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5113 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5114 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5115 DBG_PRINT(ERR_DBG,
5116 "%s: Adding Multicasts failed\n",
5117 dev->name);
1da177e4
LT		 5118 return;
5119 }
5120 }
5121
5122 /* Create the new Rx filter list and update the same in H/W. */
5508590c 5123 i = 0;
22bedad3 5124 netdev_for_each_mc_addr(ha, dev) {
a7a80d5a 5125 mac_addr = 0;
1da177e4 5126 for (j = 0; j < ETH_ALEN; j++) {
22bedad3 5127 mac_addr |= ha->addr[j];
1da177e4
LT		 5128 mac_addr <<= 8;
5129 }
5130 mac_addr >>= 8;
5131 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5132 &bar0->rmac_addr_data0_mem);
5133 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5134 &bar0->rmac_addr_data1_mem);
1da177e4 5135 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5136 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5137 RMAC_ADDR_CMD_MEM_OFFSET
5138 (i + config->mc_start_offset);
1da177e4
LT		 5139 writeq(val64, &bar0->rmac_addr_cmd_mem);
5140
5141 /* Wait for command completes */
c92ca04b 5142 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5143 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5144 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5145 DBG_PRINT(ERR_DBG,
5146 "%s: Adding Multicasts failed\n",
5147 dev->name);
1da177e4
LT		 5148 return;
5149 }
5508590c 5150 i++;
1da177e4
LT		 5151 }
5152 }
5153}
5154
faa4f796
SH		 5155/* read from CAM unicast & multicast addresses and store it in
5156 * def_mac_addr structure
5157 */
dac499f9 5158static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5159{
5160 int offset;
5161 u64 mac_addr = 0x0;
5162 struct config_param *config = &sp->config;
5163
5164 /* store unicast & multicast mac addresses */
5165 for (offset = 0; offset < config->max_mc_addr; offset++) {
5166 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5167 /* if read fails disable the entry */
5168 if (mac_addr == FAILURE)
5169 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5170 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5171 }
5172}
5173
5174/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5175static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5176{
5177 int offset;
5178 struct config_param *config = &sp->config;
5179 /* restore unicast mac address */
5180 for (offset = 0; offset < config->max_mac_addr; offset++)
5181 do_s2io_prog_unicast(sp->dev,
d44570e4 5182 sp->def_mac_addr[offset].mac_addr);
faa4f796
SH		 5183
5184 /* restore multicast mac address */
5185 for (offset = config->mc_start_offset;
d44570e4 5186 offset < config->max_mc_addr; offset++)
faa4f796
SH		 5187 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5188}
5189
5190/* add a multicast MAC address to CAM */
5191static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5192{
5193 int i;
5194 u64 mac_addr = 0;
5195 struct config_param *config = &sp->config;
5196
5197 for (i = 0; i < ETH_ALEN; i++) {
5198 mac_addr <<= 8;
5199 mac_addr |= addr[i];
5200 }
5201 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5202 return SUCCESS;
5203
5204 /* check if the multicast mac already preset in CAM */
5205 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5206 u64 tmp64;
5207 tmp64 = do_s2io_read_unicast_mc(sp, i);
5208 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5209 break;
5210
5211 if (tmp64 == mac_addr)
5212 return SUCCESS;
5213 }
5214 if (i == config->max_mc_addr) {
5215 DBG_PRINT(ERR_DBG,
d44570e4 5216 "CAM full no space left for multicast MAC\n");
faa4f796
SH		 5217 return FAILURE;
5218 }
5219 /* Update the internal structure with this new mac address */
5220 do_s2io_copy_mac_addr(sp, i, mac_addr);
5221
d44570e4 5222 return do_s2io_add_mac(sp, mac_addr, i);
faa4f796
SH		 5223}
5224
5225/* add MAC address to CAM */
5226static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5227{
5228 u64 val64;
5229 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5230
5231 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
d44570e4 5232 &bar0->rmac_addr_data0_mem);
2fd37688 5233
d44570e4 5234 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2fd37688
SS		 5235 RMAC_ADDR_CMD_MEM_OFFSET(off);
5236 writeq(val64, &bar0->rmac_addr_cmd_mem);
5237
5238 /* Wait till command completes */
5239 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5240 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5241 S2IO_BIT_RESET)) {
faa4f796 5242 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5243 return FAILURE;
5244 }
5245 return SUCCESS;
5246}
faa4f796
SH		 5247/* deletes a specified unicast/multicast mac entry from CAM */
5248static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5249{
5250 int offset;
5251 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5252 struct config_param *config = &sp->config;
5253
5254 for (offset = 1;
d44570e4 5255 offset < config->max_mc_addr; offset++) {
faa4f796
SH		 5256 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5257 if (tmp64 == addr) {
5258 /* disable the entry by writing 0xffffffffffffULL */
5259 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5260 return FAILURE;
5261 /* store the new mac list from CAM */
5262 do_s2io_store_unicast_mc(sp);
5263 return SUCCESS;
5264 }
5265 }
5266 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
d44570e4 5267 (unsigned long long)addr);
faa4f796
SH		 5268 return FAILURE;
5269}
5270
5271/* read mac entries from CAM */
5272static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5273{
5274 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5275 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5276
5277 /* read mac addr */
d44570e4 5278 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796
SH		 5279 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5280 writeq(val64, &bar0->rmac_addr_cmd_mem);
5281
5282 /* Wait till command completes */
5283 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5284 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5285 S2IO_BIT_RESET)) {
faa4f796
SH		 5286 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5287 return FAILURE;
5288 }
5289 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4
JP		 5290
5291 return tmp64 >> 16;
faa4f796 5292}
2fd37688
SS		 5293
5294/**
5295 * s2io_set_mac_addr driver entry point
5296 */
faa4f796 5297
2fd37688
SS		 5298static int s2io_set_mac_addr(struct net_device *dev, void *p)
5299{
5300 struct sockaddr *addr = p;
5301
5302 if (!is_valid_ether_addr(addr->sa_data))
5303 return -EINVAL;
5304
5305 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5306
5307 /* store the MAC address in CAM */
d44570e4 5308 return do_s2io_prog_unicast(dev, dev->dev_addr);
2fd37688 5309}
1da177e4 5310/**
2fd37688 5311 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5312 * @dev : pointer to the device structure.
5313 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5314 * Description : This procedure will program the Xframe to receive
1da177e4 5315 * frames with new Mac Address
20346722 5316 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5317 * as defined in errno.h file on failure.
5318 */
faa4f796 5319
2fd37688 5320static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5321{
4cf1653a 5322 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5323 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5324 int i;
faa4f796
SH		 5325 u64 tmp64;
5326 struct config_param *config = &sp->config;
1da177e4 5327
20346722 5328 /*
d44570e4
JP		 5329 * Set the new MAC address as the new unicast filter and reflect this
5330 * change on the device address registered with the OS. It will be
5331 * at offset 0.
5332 */
1da177e4
LT		 5333 for (i = 0; i < ETH_ALEN; i++) {
5334 mac_addr <<= 8;
5335 mac_addr |= addr[i];
2fd37688
SS		 5336 perm_addr <<= 8;
5337 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5338 }
5339
2fd37688
SS		 5340 /* check if the dev_addr is different than perm_addr */
5341 if (mac_addr == perm_addr)
d8d70caf
SS		 5342 return SUCCESS;
5343
faa4f796
SH		 5344 /* check if the mac already preset in CAM */
5345 for (i = 1; i < config->max_mac_addr; i++) {
5346 tmp64 = do_s2io_read_unicast_mc(sp, i);
5347 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5348 break;
5349
5350 if (tmp64 == mac_addr) {
5351 DBG_PRINT(INFO_DBG,
d44570e4
JP		 5352 "MAC addr:0x%llx already present in CAM\n",
5353 (unsigned long long)mac_addr);
faa4f796
SH		 5354 return SUCCESS;
5355 }
5356 }
5357 if (i == config->max_mac_addr) {
5358 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5359 return FAILURE;
5360 }
d8d70caf 5361 /* Update the internal structure with this new mac address */
faa4f796 5362 do_s2io_copy_mac_addr(sp, i, mac_addr);
d44570e4
JP		 5363
5364 return do_s2io_add_mac(sp, mac_addr, i);
1da177e4
LT		 5365}
5366
5367/**
20346722 5368 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5369 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5370 * @info: pointer to the structure with parameters given by ethtool to set
5371 * link information.
5372 * Description:
20346722 5373 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5374 * the NIC.
5375 * Return value:
5376 * 0 on success.
d44570e4 5377 */
1da177e4
LT		 5378
5379static int s2io_ethtool_sset(struct net_device *dev,
5380 struct ethtool_cmd *info)
5381{
4cf1653a 5382 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5383 if ((info->autoneg == AUTONEG_ENABLE) ||
25db0338 5384 (ethtool_cmd_speed(info) != SPEED_10000) ||
d44570e4 5385 (info->duplex != DUPLEX_FULL))
1da177e4
LT		 5386 return -EINVAL;
5387 else {
5388 s2io_close(sp->dev);
5389 s2io_open(sp->dev);
5390 }
5391
5392 return 0;
5393}
5394
5395/**
20346722 5396 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5397 * @sp : private member of the device structure, pointer to the
5398 * s2io_nic structure.
5399 * @info : pointer to the structure with parameters given by ethtool
5400 * to return link information.
5401 * Description:
5402 * Returns link specific information like speed, duplex etc.. to ethtool.
5403 * Return value :
5404 * return 0 on success.
5405 */
5406
5407static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5408{
4cf1653a 5409 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5410 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5411 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5412 info->port = PORT_FIBRE;
1a7eb72b
SS		 5413
5414 /* info->transceiver */
5415 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5416
5417 if (netif_carrier_ok(sp->dev)) {
70739497 5418 ethtool_cmd_speed_set(info, SPEED_10000);
1da177e4
LT		 5419 info->duplex = DUPLEX_FULL;
5420 } else {
70739497 5421 ethtool_cmd_speed_set(info, -1);
1da177e4
LT		 5422 info->duplex = -1;
5423 }
5424
5425 info->autoneg = AUTONEG_DISABLE;
5426 return 0;
5427}
5428
5429/**
20346722 5430 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5431 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5432 * s2io_nic structure.
5433 * @info : pointer to the structure with parameters given by ethtool to
5434 * return driver information.
5435 * Description:
5436 * Returns driver specefic information like name, version etc.. to ethtool.
5437 * Return value:
5438 * void
5439 */
5440
5441static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5442 struct ethtool_drvinfo *info)
5443{
4cf1653a 5444 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5445
dbc2309d
JL		 5446 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5447 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5448 strncpy(info->fw_version, "", sizeof(info->fw_version));
5449 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5450 info->regdump_len = XENA_REG_SPACE;
5451 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5452}
5453
5454/**
5455 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5456 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5457 * s2io_nic structure.
20346722 5458 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5459 * dumping the registers.
5460 * @reg_space: The input argumnet into which all the registers are dumped.
5461 * Description:
5462 * Dumps the entire register space of xFrame NIC into the user given
5463 * buffer area.
5464 * Return value :
5465 * void .
d44570e4 5466 */
1da177e4
LT		 5467
5468static void s2io_ethtool_gregs(struct net_device *dev,
5469 struct ethtool_regs *regs, void *space)
5470{
5471 int i;
5472 u64 reg;
d44570e4 5473 u8 *reg_space = (u8 *)space;
4cf1653a 5474 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5475
5476 regs->len = XENA_REG_SPACE;
5477 regs->version = sp->pdev->subsystem_device;
5478
5479 for (i = 0; i < regs->len; i += 8) {
5480 reg = readq(sp->bar0 + i);
5481 memcpy((reg_space + i), &reg, 8);
5482 }
5483}
5484
034e3450 5485/*
5486 * s2io_set_led - control NIC led
d44570e4 5487 */
034e3450 5488static void s2io_set_led(struct s2io_nic *sp, bool on)
1da177e4 5489{
1ee6dd77 5490 struct XENA_dev_config __iomem *bar0 = sp->bar0;
034e3450 5491 u16 subid = sp->pdev->subsystem_device;
5492 u64 val64;
1da177e4 5493
541ae68f 5494 if ((sp->device_type == XFRAME_II_DEVICE) ||
d44570e4 5495 ((subid & 0xFF) >= 0x07)) {
1da177e4 5496 val64 = readq(&bar0->gpio_control);
034e3450 5497 if (on)
5498 val64 |= GPIO_CTRL_GPIO_0;
5499 else
5500 val64 &= ~GPIO_CTRL_GPIO_0;
5501
1da177e4
LT		 5502 writeq(val64, &bar0->gpio_control);
5503 } else {
5504 val64 = readq(&bar0->adapter_control);
034e3450 5505 if (on)
5506 val64 |= ADAPTER_LED_ON;
5507 else
5508 val64 &= ~ADAPTER_LED_ON;
5509
1da177e4
LT		 5510 writeq(val64, &bar0->adapter_control);
5511 }
5512
1da177e4
LT		 5513}
5514
5515/**
034e3450 5516 * s2io_ethtool_set_led - To physically identify the nic on the system.
5517 * @dev : network device
5518 * @state: led setting
5519 *
1da177e4 5520 * Description: Used to physically identify the NIC on the system.
20346722 5521 * The Link LED will blink for a time specified by the user for
1da177e4 5522 * identification.
20346722 5523 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4 5524 * identification is possible only if it's link is up.
1da177e4
LT		 5525 */
5526
034e3450 5527static int s2io_ethtool_set_led(struct net_device *dev,
5528 enum ethtool_phys_id_state state)
1da177e4 5529{
4cf1653a 5530 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5531 struct XENA_dev_config __iomem *bar0 = sp->bar0;
034e3450 5532 u16 subid = sp->pdev->subsystem_device;
1da177e4 5533
d44570e4 5534 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
034e3450 5535 u64 val64 = readq(&bar0->adapter_control);
1da177e4 5536 if (!(val64 & ADAPTER_CNTL_EN)) {
6cef2b8e 5537 pr_err("Adapter Link down, cannot blink LED\n");
034e3450 5538 return -EAGAIN;
1da177e4
LT		 5539 }
5540 }
1da177e4 5541
034e3450 5542 switch (state) {
5543 case ETHTOOL_ID_ACTIVE:
5544 sp->adapt_ctrl_org = readq(&bar0->gpio_control);
fce55922 5545 return 1; /* cycle on/off once per second */
034e3450 5546
5547 case ETHTOOL_ID_ON:
5548 s2io_set_led(sp, true);
5549 break;
5550
5551 case ETHTOOL_ID_OFF:
5552 s2io_set_led(sp, false);
5553 break;
5554
5555 case ETHTOOL_ID_INACTIVE:
5556 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid))
5557 writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
1da177e4
LT		 5558 }
5559
5560 return 0;
5561}
5562
0cec35eb 5563static void s2io_ethtool_gringparam(struct net_device *dev,
d44570e4 5564 struct ethtool_ringparam *ering)
0cec35eb 5565{
4cf1653a 5566 struct s2io_nic *sp = netdev_priv(dev);
d44570e4 5567 int i, tx_desc_count = 0, rx_desc_count = 0;
0cec35eb 5568
1853e2e1 5569 if (sp->rxd_mode == RXD_MODE_1) {
0cec35eb 5570 ering->rx_max_pending = MAX_RX_DESC_1;
1853e2e1
JM		 5571 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5572 } else {
0cec35eb 5573 ering->rx_max_pending = MAX_RX_DESC_2;
1853e2e1
JM		 5574 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5575 }
0cec35eb 5576
1853e2e1 5577 ering->rx_mini_max_pending = 0;
0cec35eb 5578 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5579
1853e2e1 5580 for (i = 0; i < sp->config.rx_ring_num; i++)
0cec35eb 5581 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
0cec35eb 5582 ering->rx_pending = rx_desc_count;
0cec35eb 5583 ering->rx_jumbo_pending = rx_desc_count;
1853e2e1
JM		 5584 ering->rx_mini_pending = 0;
5585
5586 for (i = 0; i < sp->config.tx_fifo_num; i++)
5587 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5588 ering->tx_pending = tx_desc_count;
5589 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
0cec35eb
SH		 5590}
5591
1da177e4
LT		 5592/**
5593 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722 5594 * @sp : private member of the device structure, which is a pointer to the
5595 * s2io_nic structure.
1da177e4
LT		 5596 * @ep : pointer to the structure with pause parameters given by ethtool.
5597 * Description:
5598 * Returns the Pause frame generation and reception capability of the NIC.
5599 * Return value:
5600 * void
5601 */
5602static void s2io_ethtool_getpause_data(struct net_device *dev,
5603 struct ethtool_pauseparam *ep)
5604{
5605 u64 val64;
4cf1653a 5606 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5607 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5608
5609 val64 = readq(&bar0->rmac_pause_cfg);
5610 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5611 ep->tx_pause = true;
1da177e4 5612 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5613 ep->rx_pause = true;
5614 ep->autoneg = false;
1da177e4
LT		 5615}
5616
5617/**
5618 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5619 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5620 * s2io_nic structure.
5621 * @ep : pointer to the structure with pause parameters given by ethtool.
5622 * Description:
5623 * It can be used to set or reset Pause frame generation or reception
5624 * support of the NIC.
5625 * Return value:
5626 * int, returns 0 on Success
5627 */
5628
5629static int s2io_ethtool_setpause_data(struct net_device *dev,
d44570e4 5630 struct ethtool_pauseparam *ep)
1da177e4
LT		 5631{
5632 u64 val64;
4cf1653a 5633 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5634 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5635
5636 val64 = readq(&bar0->rmac_pause_cfg);
5637 if (ep->tx_pause)
5638 val64 |= RMAC_PAUSE_GEN_ENABLE;
5639 else
5640 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5641 if (ep->rx_pause)
5642 val64 |= RMAC_PAUSE_RX_ENABLE;
5643 else
5644 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5645 writeq(val64, &bar0->rmac_pause_cfg);
5646 return 0;
5647}
5648
5649/**
5650 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5651 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5652 * s2io_nic structure.
5653 * @off : offset at which the data must be written
5654 * @data : Its an output parameter where the data read at the given
20346722 5655 * offset is stored.
1da177e4 5656 * Description:
20346722 5657 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5658 * read data.
5659 * NOTE: Will allow to read only part of the EEPROM visible through the
5660 * I2C bus.
5661 * Return value:
5662 * -1 on failure and 0 on success.
5663 */
5664
5665#define S2IO_DEV_ID 5
d44570e4 5666static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
1da177e4
LT		 5667{
5668 int ret = -1;
5669 u32 exit_cnt = 0;
5670 u64 val64;
1ee6dd77 5671 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5672
ad4ebed0 5673 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5674 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5675 I2C_CONTROL_ADDR(off) |
5676 I2C_CONTROL_BYTE_CNT(0x3) |
5677 I2C_CONTROL_READ |
5678 I2C_CONTROL_CNTL_START;
ad4ebed0 5679 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5680
ad4ebed0 5681 while (exit_cnt < 5) {
5682 val64 = readq(&bar0->i2c_control);
5683 if (I2C_CONTROL_CNTL_END(val64)) {
5684 *data = I2C_CONTROL_GET_DATA(val64);
5685 ret = 0;
5686 break;
5687 }
5688 msleep(50);
5689 exit_cnt++;
1da177e4 5690 }
1da177e4
LT		 5691 }
5692
ad4ebed0 5693 if (sp->device_type == XFRAME_II_DEVICE) {
5694 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5695 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5696 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5697 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5698 val64 |= SPI_CONTROL_REQ;
5699 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5700 while (exit_cnt < 5) {
5701 val64 = readq(&bar0->spi_control);
5702 if (val64 & SPI_CONTROL_NACK) {
5703 ret = 1;
5704 break;
5705 } else if (val64 & SPI_CONTROL_DONE) {
5706 *data = readq(&bar0->spi_data);
5707 *data &= 0xffffff;
5708 ret = 0;
5709 break;
5710 }
5711 msleep(50);
5712 exit_cnt++;
5713 }
5714 }
1da177e4
LT		 5715 return ret;
5716}
5717
5718/**
5719 * write_eeprom - actually writes the relevant part of the data value.
5720 * @sp : private member of the device structure, which is a pointer to the
5721 * s2io_nic structure.
5722 * @off : offset at which the data must be written
5723 * @data : The data that is to be written
20346722 5724 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5725 * the Eeprom. (max of 3)
5726 * Description:
5727 * Actually writes the relevant part of the data value into the Eeprom
5728 * through the I2C bus.
5729 * Return value:
5730 * 0 on success, -1 on failure.
5731 */
5732
d44570e4 5733static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
1da177e4
LT		 5734{
5735 int exit_cnt = 0, ret = -1;
5736 u64 val64;
1ee6dd77 5737 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5738
ad4ebed0 5739 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5740 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5741 I2C_CONTROL_ADDR(off) |
5742 I2C_CONTROL_BYTE_CNT(cnt) |
5743 I2C_CONTROL_SET_DATA((u32)data) |
5744 I2C_CONTROL_CNTL_START;
ad4ebed0 5745 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5746
5747 while (exit_cnt < 5) {
5748 val64 = readq(&bar0->i2c_control);
5749 if (I2C_CONTROL_CNTL_END(val64)) {
5750 if (!(val64 & I2C_CONTROL_NACK))
5751 ret = 0;
5752 break;
5753 }
5754 msleep(50);
5755 exit_cnt++;
5756 }
5757 }
1da177e4 5758
ad4ebed0 5759 if (sp->device_type == XFRAME_II_DEVICE) {
5760 int write_cnt = (cnt == 8) ? 0 : cnt;
d44570e4 5761 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
ad4ebed0 5762
5763 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5764 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5765 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5766 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5767 val64 |= SPI_CONTROL_REQ;
5768 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5769 while (exit_cnt < 5) {
5770 val64 = readq(&bar0->spi_control);
5771 if (val64 & SPI_CONTROL_NACK) {
5772 ret = 1;
5773 break;
5774 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5775 ret = 0;
ad4ebed0 5776 break;
5777 }
5778 msleep(50);
5779 exit_cnt++;
1da177e4 5780 }
1da177e4 5781 }
1da177e4
LT		 5782 return ret;
5783}
1ee6dd77 5784static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5785{
b41477f3
AR		 5786 u8 *vpd_data;
5787 u8 data;
9c179780 5788 int i = 0, cnt, len, fail = 0;
9dc737a7 5789 int vpd_addr = 0x80;
ffb5df6c 5790 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
9dc737a7
AR		 5791
5792 if (nic->device_type == XFRAME_II_DEVICE) {
5793 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5794 vpd_addr = 0x80;
d44570e4 5795 } else {
9dc737a7
AR		 5796 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5797 vpd_addr = 0x50;
5798 }
19a60522 5799 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5800
b41477f3 5801 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945 5802 if (!vpd_data) {
ffb5df6c 5803 swstats->mem_alloc_fail_cnt++;
b41477f3 5804 return;
c53d4945 5805 }
ffb5df6c 5806 swstats->mem_allocated += 256;
b41477f3 5807
d44570e4 5808 for (i = 0; i < 256; i += 4) {
9dc737a7
AR		 5809 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5810 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5811 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
d44570e4 5812 for (cnt = 0; cnt < 5; cnt++) {
9dc737a7
AR		 5813 msleep(2);
5814 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5815 if (data == 0x80)
5816 break;
5817 }
5818 if (cnt >= 5) {
5819 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5820 fail = 1;
5821 break;
5822 }
5823 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5824 (u32 *)&vpd_data[i]);
5825 }
19a60522 5826
d44570e4 5827 if (!fail) {
19a60522 5828 /* read serial number of adapter */
9c179780 5829 for (cnt = 0; cnt < 252; cnt++) {
d44570e4 5830 if ((vpd_data[cnt] == 'S') &&
9c179780
KV		 5831 (vpd_data[cnt+1] == 'N')) {
5832 len = vpd_data[cnt+2];
5833 if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5834 memcpy(nic->serial_num,
5835 &vpd_data[cnt + 3],
5836 len);
5837 memset(nic->serial_num+len,
5838 0,
5839 VPD_STRING_LEN-len);
5840 break;
5841 }
19a60522
SS		 5842 }
5843 }
5844 }
5845
9c179780
KV		 5846 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5847 len = vpd_data[1];
5848 memcpy(nic->product_name, &vpd_data[3], len);
5849 nic->product_name[len] = 0;
5850 }
b41477f3 5851 kfree(vpd_data);
ffb5df6c 5852 swstats->mem_freed += 256;
9dc737a7
AR		 5853}
5854
1da177e4
LT		 5855/**
5856 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5857 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5858 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5859 * containing all relevant information.
5860 * @data_buf : user defined value to be written into Eeprom.
5861 * Description: Reads the values stored in the Eeprom at given offset
5862 * for a given length. Stores these values int the input argument data
5863 * buffer 'data_buf' and returns these to the caller (ethtool.)
5864 * Return value:
5865 * int 0 on success
5866 */
5867
5868static int s2io_ethtool_geeprom(struct net_device *dev,
d44570e4 5869 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5870{
ad4ebed0 5871 u32 i, valid;
5872 u64 data;
4cf1653a 5873 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5874
5875 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5876
5877 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5878 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5879
5880 for (i = 0; i < eeprom->len; i += 4) {
5881 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5882 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5883 return -EFAULT;
5884 }
5885 valid = INV(data);
5886 memcpy((data_buf + i), &valid, 4);
5887 }
5888 return 0;
5889}
5890
5891/**
5892 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5893 * @sp : private member of the device structure, which is a pointer to the
5894 * s2io_nic structure.
20346722 5895 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5896 * containing all relevant information.
5897 * @data_buf ; user defined value to be written into Eeprom.
5898 * Description:
5899 * Tries to write the user provided value in the Eeprom, at the offset
5900 * given by the user.
5901 * Return value:
5902 * 0 on success, -EFAULT on failure.
5903 */
5904
5905static int s2io_ethtool_seeprom(struct net_device *dev,
5906 struct ethtool_eeprom *eeprom,
d44570e4 5907 u8 *data_buf)
1da177e4
LT		 5908{
5909 int len = eeprom->len, cnt = 0;
ad4ebed0 5910 u64 valid = 0, data;
4cf1653a 5911 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5912
5913 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5914 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5915 "ETHTOOL_WRITE_EEPROM Err: "
5916 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5917 (sp->pdev->vendor | (sp->pdev->device << 16)),
5918 eeprom->magic);
1da177e4
LT		 5919 return -EFAULT;
5920 }
5921
5922 while (len) {
d44570e4
JP		 5923 data = (u32)data_buf[cnt] & 0x000000FF;
5924 if (data)
5925 valid = (u32)(data << 24);
5926 else
1da177e4
LT		 5927 valid = data;
5928
5929 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5930 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5931 "ETHTOOL_WRITE_EEPROM Err: "
5932 "Cannot write into the specified offset\n");
1da177e4
LT		 5933 return -EFAULT;
5934 }
5935 cnt++;
5936 len--;
5937 }
5938
5939 return 0;
5940}
5941
5942/**
20346722 5943 * s2io_register_test - reads and writes into all clock domains.
5944 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5945 * s2io_nic structure.
5946 * @data : variable that returns the result of each of the test conducted b
5947 * by the driver.
5948 * Description:
5949 * Read and write into all clock domains. The NIC has 3 clock domains,
5950 * see that registers in all the three regions are accessible.
5951 * Return value:
5952 * 0 on success.
5953 */
5954
d44570e4 5955static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 5956{
1ee6dd77 5957 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5958 u64 val64 = 0, exp_val;
1da177e4
LT		 5959 int fail = 0;
5960
20346722 5961 val64 = readq(&bar0->pif_rd_swapper_fb);
5962 if (val64 != 0x123456789abcdefULL) {
1da177e4 5963 fail = 1;
9e39f7c5 5964 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
1da177e4
LT		 5965 }
5966
5967 val64 = readq(&bar0->rmac_pause_cfg);
5968 if (val64 != 0xc000ffff00000000ULL) {
5969 fail = 1;
9e39f7c5 5970 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
1da177e4
LT		 5971 }
5972
5973 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5974 if (sp->device_type == XFRAME_II_DEVICE)
5975 exp_val = 0x0404040404040404ULL;
5976 else
5977 exp_val = 0x0808080808080808ULL;
5978 if (val64 != exp_val) {
1da177e4 5979 fail = 1;
9e39f7c5 5980 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
1da177e4
LT		 5981 }
5982
5983 val64 = readq(&bar0->xgxs_efifo_cfg);
5984 if (val64 != 0x000000001923141EULL) {
5985 fail = 1;
9e39f7c5 5986 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
1da177e4
LT		 5987 }
5988
5989 val64 = 0x5A5A5A5A5A5A5A5AULL;
5990 writeq(val64, &bar0->xmsi_data);
5991 val64 = readq(&bar0->xmsi_data);
5992 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5993 fail = 1;
9e39f7c5 5994 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
1da177e4
LT		 5995 }
5996
5997 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5998 writeq(val64, &bar0->xmsi_data);
5999 val64 = readq(&bar0->xmsi_data);
6000 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
6001 fail = 1;
9e39f7c5 6002 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
1da177e4
LT		 6003 }
6004
6005 *data = fail;
ad4ebed0 6006 return fail;
1da177e4
LT		 6007}
6008
6009/**
20346722 6010 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 6011 * @sp : private member of the device structure, which is a pointer to the
6012 * s2io_nic structure.
6013 * @data:variable that returns the result of each of the test conducted by
6014 * the driver.
6015 * Description:
20346722 6016 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 6017 * register.
6018 * Return value:
6019 * 0 on success.
6020 */
6021
d44570e4 6022static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6023{
6024 int fail = 0;
ad4ebed0 6025 u64 ret_data, org_4F0, org_7F0;
6026 u8 saved_4F0 = 0, saved_7F0 = 0;
6027 struct net_device *dev = sp->dev;
1da177e4
LT		 6028
6029 /* Test Write Error at offset 0 */
ad4ebed0 6030 /* Note that SPI interface allows write access to all areas
6031 * of EEPROM. Hence doing all negative testing only for Xframe I.
6032 */
6033 if (sp->device_type == XFRAME_I_DEVICE)
6034 if (!write_eeprom(sp, 0, 0, 3))
6035 fail = 1;
6036
6037 /* Save current values at offsets 0x4F0 and 0x7F0 */
6038 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6039 saved_4F0 = 1;
6040 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6041 saved_7F0 = 1;
1da177e4
LT		 6042
6043 /* Test Write at offset 4f0 */
ad4ebed0 6044 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6045 fail = 1;
6046 if (read_eeprom(sp, 0x4F0, &ret_data))
6047 fail = 1;
6048
ad4ebed0 6049 if (ret_data != 0x012345) {
26b7625c 6050 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
d44570e4
JP		 6051 "Data written %llx Data read %llx\n",
6052 dev->name, (unsigned long long)0x12345,
6053 (unsigned long long)ret_data);
1da177e4 6054 fail = 1;
ad4ebed0 6055 }
1da177e4
LT		 6056
6057 /* Reset the EEPROM data go FFFF */
ad4ebed0 6058 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6059
6060 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6061 if (sp->device_type == XFRAME_I_DEVICE)
6062 if (!write_eeprom(sp, 0x07C, 0, 3))
6063 fail = 1;
1da177e4 6064
ad4ebed0 6065 /* Test Write Request at offset 0x7f0 */
6066 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6067 fail = 1;
ad4ebed0 6068 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6069 fail = 1;
6070
ad4ebed0 6071 if (ret_data != 0x012345) {
26b7625c 6072 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
d44570e4
JP		 6073 "Data written %llx Data read %llx\n",
6074 dev->name, (unsigned long long)0x12345,
6075 (unsigned long long)ret_data);
1da177e4 6076 fail = 1;
ad4ebed0 6077 }
1da177e4
LT		 6078
6079 /* Reset the EEPROM data go FFFF */
ad4ebed0 6080 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6081
ad4ebed0 6082 if (sp->device_type == XFRAME_I_DEVICE) {
6083 /* Test Write Error at offset 0x80 */
6084 if (!write_eeprom(sp, 0x080, 0, 3))
6085 fail = 1;
1da177e4 6086
ad4ebed0 6087 /* Test Write Error at offset 0xfc */
6088 if (!write_eeprom(sp, 0x0FC, 0, 3))
6089 fail = 1;
1da177e4 6090
ad4ebed0 6091 /* Test Write Error at offset 0x100 */
6092 if (!write_eeprom(sp, 0x100, 0, 3))
6093 fail = 1;
1da177e4 6094
ad4ebed0 6095 /* Test Write Error at offset 4ec */
6096 if (!write_eeprom(sp, 0x4EC, 0, 3))
6097 fail = 1;
6098 }
6099
6100 /* Restore values at offsets 0x4F0 and 0x7F0 */
6101 if (saved_4F0)
6102 write_eeprom(sp, 0x4F0, org_4F0, 3);
6103 if (saved_7F0)
6104 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6105
6106 *data = fail;
ad4ebed0 6107 return fail;
1da177e4
LT		 6108}
6109
6110/**
6111 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6112 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6113 * s2io_nic structure.
20346722 6114 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6115 * the driver.
6116 * Description:
6117 * This invokes the MemBist test of the card. We give around
6118 * 2 secs time for the Test to complete. If it's still not complete
20346722 6119 * within this peiod, we consider that the test failed.
1da177e4
LT		 6120 * Return value:
6121 * 0 on success and -1 on failure.
6122 */
6123
d44570e4 6124static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6125{
6126 u8 bist = 0;
6127 int cnt = 0, ret = -1;
6128
6129 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6130 bist |= PCI_BIST_START;
6131 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6132
6133 while (cnt < 20) {
6134 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6135 if (!(bist & PCI_BIST_START)) {
6136 *data = (bist & PCI_BIST_CODE_MASK);
6137 ret = 0;
6138 break;
6139 }
6140 msleep(100);
6141 cnt++;
6142 }
6143
6144 return ret;
6145}
6146
6147/**
20346722 6148 * s2io-link_test - verifies the link state of the nic
6149 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6150 * s2io_nic structure.
6151 * @data: variable that returns the result of each of the test conducted by
6152 * the driver.
6153 * Description:
20346722 6154 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6155 * argument 'data' appropriately.
6156 * Return value:
6157 * 0 on success.
6158 */
6159
d44570e4 6160static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6161{
1ee6dd77 6162 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6163 u64 val64;
6164
6165 val64 = readq(&bar0->adapter_status);
d44570e4 6166 if (!(LINK_IS_UP(val64)))
1da177e4 6167 *data = 1;
c92ca04b
AR		 6168 else
6169 *data = 0;
1da177e4 6170
b41477f3 6171 return *data;
1da177e4
LT		 6172}
6173
6174/**
20346722 6175 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6176 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6177 * s2io_nic structure.
20346722 6178 * @data - variable that returns the result of each of the test
1da177e4
LT		 6179 * conducted by the driver.
6180 * Description:
20346722 6181 * This is one of the offline test that tests the read and write
1da177e4
LT		 6182 * access to the RldRam chip on the NIC.
6183 * Return value:
6184 * 0 on success.
6185 */
6186
d44570e4 6187static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6188{
1ee6dd77 6189 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6190 u64 val64;
ad4ebed0 6191 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6192
6193 val64 = readq(&bar0->adapter_control);
6194 val64 &= ~ADAPTER_ECC_EN;
6195 writeq(val64, &bar0->adapter_control);
6196
6197 val64 = readq(&bar0->mc_rldram_test_ctrl);
6198 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6199 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6200
6201 val64 = readq(&bar0->mc_rldram_mrs);
6202 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6203 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6204
6205 val64 |= MC_RLDRAM_MRS_ENABLE;
6206 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6207
6208 while (iteration < 2) {
6209 val64 = 0x55555555aaaa0000ULL;
d44570e4 6210 if (iteration == 1)
1da177e4 6211 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6212 writeq(val64, &bar0->mc_rldram_test_d0);
6213
6214 val64 = 0xaaaa5a5555550000ULL;
d44570e4 6215 if (iteration == 1)
1da177e4 6216 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6217 writeq(val64, &bar0->mc_rldram_test_d1);
6218
6219 val64 = 0x55aaaaaaaa5a0000ULL;
d44570e4 6220 if (iteration == 1)
1da177e4 6221 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6222 writeq(val64, &bar0->mc_rldram_test_d2);
6223
ad4ebed0 6224 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6225 writeq(val64, &bar0->mc_rldram_test_add);
6226
d44570e4
JP		 6227 val64 = MC_RLDRAM_TEST_MODE |
6228 MC_RLDRAM_TEST_WRITE |
6229 MC_RLDRAM_TEST_GO;
ad4ebed0 6230 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6231
6232 for (cnt = 0; cnt < 5; cnt++) {
6233 val64 = readq(&bar0->mc_rldram_test_ctrl);
6234 if (val64 & MC_RLDRAM_TEST_DONE)
6235 break;
6236 msleep(200);
6237 }
6238
6239 if (cnt == 5)
6240 break;
6241
ad4ebed0 6242 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6243 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6244
6245 for (cnt = 0; cnt < 5; cnt++) {
6246 val64 = readq(&bar0->mc_rldram_test_ctrl);
6247 if (val64 & MC_RLDRAM_TEST_DONE)
6248 break;
6249 msleep(500);
6250 }
6251
6252 if (cnt == 5)
6253 break;
6254
6255 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6256 if (!(val64 & MC_RLDRAM_TEST_PASS))
6257 test_fail = 1;
1da177e4
LT		 6258
6259 iteration++;
6260 }
6261
ad4ebed0 6262 *data = test_fail;
1da177e4 6263
ad4ebed0 6264 /* Bring the adapter out of test mode */
6265 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6266
6267 return test_fail;
1da177e4
LT		 6268}
6269
6270/**
6271 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6272 * @sp : private member of the device structure, which is a pointer to the
6273 * s2io_nic structure.
6274 * @ethtest : pointer to a ethtool command specific structure that will be
6275 * returned to the user.
20346722 6276 * @data : variable that returns the result of each of the test
1da177e4
LT		 6277 * conducted by the driver.
6278 * Description:
6279 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6280 * the health of the card.
6281 * Return value:
6282 * void
6283 */
6284
6285static void s2io_ethtool_test(struct net_device *dev,
6286 struct ethtool_test *ethtest,
d44570e4 6287 uint64_t *data)
1da177e4 6288{
4cf1653a 6289 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6290 int orig_state = netif_running(sp->dev);
6291
6292 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6293 /* Offline Tests. */
20346722 6294 if (orig_state)
1da177e4 6295 s2io_close(sp->dev);
1da177e4
LT		 6296
6297 if (s2io_register_test(sp, &data[0]))
6298 ethtest->flags |= ETH_TEST_FL_FAILED;
6299
6300 s2io_reset(sp);
1da177e4
LT		 6301
6302 if (s2io_rldram_test(sp, &data[3]))
6303 ethtest->flags |= ETH_TEST_FL_FAILED;
6304
6305 s2io_reset(sp);
1da177e4
LT		 6306
6307 if (s2io_eeprom_test(sp, &data[1]))
6308 ethtest->flags |= ETH_TEST_FL_FAILED;
6309
6310 if (s2io_bist_test(sp, &data[4]))
6311 ethtest->flags |= ETH_TEST_FL_FAILED;
6312
6313 if (orig_state)
6314 s2io_open(sp->dev);
6315
6316 data[2] = 0;
6317 } else {
6318 /* Online Tests. */
6319 if (!orig_state) {
d44570e4 6320 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
1da177e4
LT		 6321 dev->name);
6322 data[0] = -1;
6323 data[1] = -1;
6324 data[2] = -1;
6325 data[3] = -1;
6326 data[4] = -1;
6327 }
6328
6329 if (s2io_link_test(sp, &data[2]))
6330 ethtest->flags |= ETH_TEST_FL_FAILED;
6331
6332 data[0] = 0;
6333 data[1] = 0;
6334 data[3] = 0;
6335 data[4] = 0;
6336 }
6337}
6338
6339static void s2io_get_ethtool_stats(struct net_device *dev,
6340 struct ethtool_stats *estats,
d44570e4 6341 u64 *tmp_stats)
1da177e4 6342{
8116f3cf 6343 int i = 0, k;
4cf1653a 6344 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 6345 struct stat_block *stats = sp->mac_control.stats_info;
6346 struct swStat *swstats = &stats->sw_stat;
6347 struct xpakStat *xstats = &stats->xpak_stat;
1da177e4 6348
7ba013ac 6349 s2io_updt_stats(sp);
541ae68f 6350 tmp_stats[i++] =
ffb5df6c
JP		 6351 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6352 le32_to_cpu(stats->tmac_frms);
541ae68f 6353 tmp_stats[i++] =
ffb5df6c
JP		 6354 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6355 le32_to_cpu(stats->tmac_data_octets);
6356 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
541ae68f 6357 tmp_stats[i++] =
ffb5df6c
JP		 6358 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6359 le32_to_cpu(stats->tmac_mcst_frms);
541ae68f 6360 tmp_stats[i++] =
ffb5df6c
JP		 6361 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6362 le32_to_cpu(stats->tmac_bcst_frms);
6363 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
bd1034f0 6364 tmp_stats[i++] =
ffb5df6c
JP		 6365 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6366 le32_to_cpu(stats->tmac_ttl_octets);
bd1034f0 6367 tmp_stats[i++] =
ffb5df6c
JP		 6368 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6369 le32_to_cpu(stats->tmac_ucst_frms);
d44570e4 6370 tmp_stats[i++] =
ffb5df6c
JP		 6371 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6372 le32_to_cpu(stats->tmac_nucst_frms);
541ae68f 6373 tmp_stats[i++] =
ffb5df6c
JP		 6374 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6375 le32_to_cpu(stats->tmac_any_err_frms);
6376 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6377 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
541ae68f 6378 tmp_stats[i++] =
ffb5df6c
JP		 6379 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6380 le32_to_cpu(stats->tmac_vld_ip);
541ae68f 6381 tmp_stats[i++] =
ffb5df6c
JP		 6382 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6383 le32_to_cpu(stats->tmac_drop_ip);
541ae68f 6384 tmp_stats[i++] =
ffb5df6c
JP		 6385 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6386 le32_to_cpu(stats->tmac_icmp);
541ae68f 6387 tmp_stats[i++] =
ffb5df6c
JP		 6388 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6389 le32_to_cpu(stats->tmac_rst_tcp);
6390 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6391 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6392 le32_to_cpu(stats->tmac_udp);
541ae68f 6393 tmp_stats[i++] =
ffb5df6c
JP		 6394 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6395 le32_to_cpu(stats->rmac_vld_frms);
541ae68f 6396 tmp_stats[i++] =
ffb5df6c
JP		 6397 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6398 le32_to_cpu(stats->rmac_data_octets);
6399 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6400 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
541ae68f 6401 tmp_stats[i++] =
ffb5df6c
JP		 6402 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6403 le32_to_cpu(stats->rmac_vld_mcst_frms);
541ae68f 6404 tmp_stats[i++] =
ffb5df6c
JP		 6405 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6406 le32_to_cpu(stats->rmac_vld_bcst_frms);
6407 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6408 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6409 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6410 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6411 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
d44570e4 6412 tmp_stats[i++] =
ffb5df6c
JP		 6413 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6414 le32_to_cpu(stats->rmac_ttl_octets);
bd1034f0 6415 tmp_stats[i++] =
ffb5df6c
JP		 6416 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6417 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
d44570e4 6418 tmp_stats[i++] =
ffb5df6c
JP		 6419 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6420 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
541ae68f 6421 tmp_stats[i++] =
ffb5df6c
JP		 6422 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6423 le32_to_cpu(stats->rmac_discarded_frms);
d44570e4 6424 tmp_stats[i++] =
ffb5df6c
JP		 6425 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6426 << 32 | le32_to_cpu(stats->rmac_drop_events);
6427 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6428 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
541ae68f 6429 tmp_stats[i++] =
ffb5df6c
JP		 6430 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6431 le32_to_cpu(stats->rmac_usized_frms);
541ae68f 6432 tmp_stats[i++] =
ffb5df6c
JP		 6433 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6434 le32_to_cpu(stats->rmac_osized_frms);
541ae68f 6435 tmp_stats[i++] =
ffb5df6c
JP		 6436 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6437 le32_to_cpu(stats->rmac_frag_frms);
541ae68f 6438 tmp_stats[i++] =
ffb5df6c
JP		 6439 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6440 le32_to_cpu(stats->rmac_jabber_frms);
6441 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6442 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6443 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6444 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6445 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6446 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
bd1034f0 6447 tmp_stats[i++] =
ffb5df6c
JP		 6448 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6449 le32_to_cpu(stats->rmac_ip);
6450 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6451 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
bd1034f0 6452 tmp_stats[i++] =
ffb5df6c
JP		 6453 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6454 le32_to_cpu(stats->rmac_drop_ip);
bd1034f0 6455 tmp_stats[i++] =
ffb5df6c
JP		 6456 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6457 le32_to_cpu(stats->rmac_icmp);
6458 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
bd1034f0 6459 tmp_stats[i++] =
ffb5df6c
JP		 6460 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6461 le32_to_cpu(stats->rmac_udp);
541ae68f 6462 tmp_stats[i++] =
ffb5df6c
JP		 6463 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6464 le32_to_cpu(stats->rmac_err_drp_udp);
6465 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6466 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6467 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6468 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6469 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6470 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6471 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6472 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6473 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6474 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6475 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6476 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6477 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6478 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6479 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6480 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6481 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
541ae68f 6482 tmp_stats[i++] =
ffb5df6c
JP		 6483 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6484 le32_to_cpu(stats->rmac_pause_cnt);
6485 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6486 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
541ae68f 6487 tmp_stats[i++] =
ffb5df6c
JP		 6488 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6489 le32_to_cpu(stats->rmac_accepted_ip);
6490 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6491 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6492 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6493 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6494 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6495 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6496 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6497 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6498 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6499 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6500 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6501 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6502 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6503 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6504 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6505 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6506 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6507 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6508 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
fa1f0cb3
SS		 6509
6510 /* Enhanced statistics exist only for Hercules */
d44570e4 6511 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6512 tmp_stats[i++] =
ffb5df6c 6513 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
fa1f0cb3 6514 tmp_stats[i++] =
ffb5df6c 6515 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
fa1f0cb3 6516 tmp_stats[i++] =
ffb5df6c
JP		 6517 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6518 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6519 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6520 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6521 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6522 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6523 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6524 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6525 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6526 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6527 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6528 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6529 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6530 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
fa1f0cb3
SS		 6531 }
6532
7ba013ac 6533 tmp_stats[i++] = 0;
ffb5df6c
JP		 6534 tmp_stats[i++] = swstats->single_ecc_errs;
6535 tmp_stats[i++] = swstats->double_ecc_errs;
6536 tmp_stats[i++] = swstats->parity_err_cnt;
6537 tmp_stats[i++] = swstats->serious_err_cnt;
6538 tmp_stats[i++] = swstats->soft_reset_cnt;
6539 tmp_stats[i++] = swstats->fifo_full_cnt;
8116f3cf 6540 for (k = 0; k < MAX_RX_RINGS; k++)
ffb5df6c
JP		 6541 tmp_stats[i++] = swstats->ring_full_cnt[k];
6542 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6543 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6544 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6545 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6546 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6547 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6548 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6549 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6550 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6551 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6552 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6553 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6554 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6555 tmp_stats[i++] = swstats->sending_both;
6556 tmp_stats[i++] = swstats->outof_sequence_pkts;
6557 tmp_stats[i++] = swstats->flush_max_pkts;
6558 if (swstats->num_aggregations) {
6559 u64 tmp = swstats->sum_avg_pkts_aggregated;
bd1034f0 6560 int count = 0;
6aa20a22 6561 /*
bd1034f0
AR		 6562 * Since 64-bit divide does not work on all platforms,
6563 * do repeated subtraction.
6564 */
ffb5df6c
JP		 6565 while (tmp >= swstats->num_aggregations) {
6566 tmp -= swstats->num_aggregations;
bd1034f0
AR		 6567 count++;
6568 }
6569 tmp_stats[i++] = count;
d44570e4 6570 } else
bd1034f0 6571 tmp_stats[i++] = 0;
ffb5df6c
JP		 6572 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6573 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6574 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6575 tmp_stats[i++] = swstats->mem_allocated;
6576 tmp_stats[i++] = swstats->mem_freed;
6577 tmp_stats[i++] = swstats->link_up_cnt;
6578 tmp_stats[i++] = swstats->link_down_cnt;
6579 tmp_stats[i++] = swstats->link_up_time;
6580 tmp_stats[i++] = swstats->link_down_time;
6581
6582 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6583 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6584 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6585 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6586 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6587
6588 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6589 tmp_stats[i++] = swstats->rx_abort_cnt;
6590 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6591 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6592 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6593 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6594 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6595 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6596 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6597 tmp_stats[i++] = swstats->tda_err_cnt;
6598 tmp_stats[i++] = swstats->pfc_err_cnt;
6599 tmp_stats[i++] = swstats->pcc_err_cnt;
6600 tmp_stats[i++] = swstats->tti_err_cnt;
6601 tmp_stats[i++] = swstats->tpa_err_cnt;
6602 tmp_stats[i++] = swstats->sm_err_cnt;
6603 tmp_stats[i++] = swstats->lso_err_cnt;
6604 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6605 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6606 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6607 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6608 tmp_stats[i++] = swstats->rc_err_cnt;
6609 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6610 tmp_stats[i++] = swstats->rpa_err_cnt;
6611 tmp_stats[i++] = swstats->rda_err_cnt;
6612 tmp_stats[i++] = swstats->rti_err_cnt;
6613 tmp_stats[i++] = swstats->mc_err_cnt;
1da177e4
LT		 6614}
6615
ac1f60db 6616static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4 6617{
d44570e4 6618 return XENA_REG_SPACE;
1da177e4
LT		 6619}
6620
6621
ac1f60db 6622static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4 6623{
d44570e4 6624 return XENA_EEPROM_SPACE;
1da177e4
LT		 6625}
6626
b9f2c044 6627static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6628{
4cf1653a 6629 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6630
6631 switch (sset) {
6632 case ETH_SS_TEST:
6633 return S2IO_TEST_LEN;
6634 case ETH_SS_STATS:
d44570e4 6635 switch (sp->device_type) {
b9f2c044
JG		 6636 case XFRAME_I_DEVICE:
6637 return XFRAME_I_STAT_LEN;
6638 case XFRAME_II_DEVICE:
6639 return XFRAME_II_STAT_LEN;
6640 default:
6641 return 0;
6642 }
6643 default:
6644 return -EOPNOTSUPP;
6645 }
1da177e4 6646}
ac1f60db
AB		 6647
6648static void s2io_ethtool_get_strings(struct net_device *dev,
d44570e4 6649 u32 stringset, u8 *data)
1da177e4 6650{
fa1f0cb3 6651 int stat_size = 0;
4cf1653a 6652 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6653
1da177e4
LT		 6654 switch (stringset) {
6655 case ETH_SS_TEST:
6656 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6657 break;
6658 case ETH_SS_STATS:
fa1f0cb3 6659 stat_size = sizeof(ethtool_xena_stats_keys);
d44570e4
JP		 6660 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6661 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6662 memcpy(data + stat_size,
d44570e4
JP		 6663 &ethtool_enhanced_stats_keys,
6664 sizeof(ethtool_enhanced_stats_keys));
fa1f0cb3
SS		 6665 stat_size += sizeof(ethtool_enhanced_stats_keys);
6666 }
6667
6668 memcpy(data + stat_size, &ethtool_driver_stats_keys,
d44570e4 6669 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6670 }
6671}
1da177e4 6672
b437a8cc 6673static int s2io_set_features(struct net_device *dev, u32 features)
958de193
JM		 6674{
6675 struct s2io_nic *sp = netdev_priv(dev);
b437a8cc 6676 u32 changed = (features ^ dev->features) & NETIF_F_LRO;
958de193
JM		 6677
6678 if (changed && netif_running(dev)) {
b437a8cc
MM		 6679 int rc;
6680
958de193
JM		 6681 s2io_stop_all_tx_queue(sp);
6682 s2io_card_down(sp);
b437a8cc 6683 dev->features = features;
958de193
JM		 6684 rc = s2io_card_up(sp);
6685 if (rc)
6686 s2io_reset(sp);
6687 else
6688 s2io_start_all_tx_queue(sp);
b437a8cc
MM		 6689
6690 return rc ? rc : 1;
958de193
JM		 6691 }
6692
b437a8cc 6693 return 0;
958de193
JM		 6694}
6695
7282d491 6696static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6697 .get_settings = s2io_ethtool_gset,
6698 .set_settings = s2io_ethtool_sset,
6699 .get_drvinfo = s2io_ethtool_gdrvinfo,
6700 .get_regs_len = s2io_ethtool_get_regs_len,
6701 .get_regs = s2io_ethtool_gregs,
6702 .get_link = ethtool_op_get_link,
6703 .get_eeprom_len = s2io_get_eeprom_len,
6704 .get_eeprom = s2io_ethtool_geeprom,
6705 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6706 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6707 .get_pauseparam = s2io_ethtool_getpause_data,
6708 .set_pauseparam = s2io_ethtool_setpause_data,
1da177e4
LT		 6709 .self_test = s2io_ethtool_test,
6710 .get_strings = s2io_ethtool_get_strings,
034e3450 6711 .set_phys_id = s2io_ethtool_set_led,
b9f2c044
JG		 6712 .get_ethtool_stats = s2io_get_ethtool_stats,
6713 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6714};
6715
6716/**
20346722 6717 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6718 * @dev : Device pointer.
6719 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6720 * a proprietary structure used to pass information to the driver.
6721 * @cmd : This is used to distinguish between the different commands that
6722 * can be passed to the IOCTL functions.
6723 * Description:
20346722 6724 * Currently there are no special functionality supported in IOCTL, hence
6725 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6726 */
6727
ac1f60db 6728static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6729{
6730 return -EOPNOTSUPP;
6731}
6732
6733/**
6734 * s2io_change_mtu - entry point to change MTU size for the device.
6735 * @dev : device pointer.
6736 * @new_mtu : the new MTU size for the device.
6737 * Description: A driver entry point to change MTU size for the device.
6738 * Before changing the MTU the device must be stopped.
6739 * Return value:
6740 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6741 * file on failure.
6742 */
6743
ac1f60db 6744static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6745{
4cf1653a 6746 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6747 int ret = 0;
1da177e4
LT		 6748
6749 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
d44570e4 6750 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
1da177e4
LT		 6751 return -EPERM;
6752 }
6753
1da177e4 6754 dev->mtu = new_mtu;
d8892c6e 6755 if (netif_running(dev)) {
3a3d5756 6756 s2io_stop_all_tx_queue(sp);
e6a8fee2 6757 s2io_card_down(sp);
9f74ffde
SH		 6758 ret = s2io_card_up(sp);
6759 if (ret) {
d8892c6e 6760 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6761 __func__);
9f74ffde 6762 return ret;
d8892c6e 6763 }
3a3d5756 6764 s2io_wake_all_tx_queue(sp);
d8892c6e 6765 } else { /* Device is down */
1ee6dd77 6766 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e 6767 u64 val64 = new_mtu;
6768
6769 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6770 }
1da177e4 6771
9f74ffde 6772 return ret;
1da177e4
LT		 6773}
6774
1da177e4
LT		 6775/**
6776 * s2io_set_link - Set the LInk status
6777 * @data: long pointer to device private structue
6778 * Description: Sets the link status for the adapter
6779 */
6780
c4028958 6781static void s2io_set_link(struct work_struct *work)
1da177e4 6782{
d44570e4
JP		 6783 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6784 set_link_task);
1da177e4 6785 struct net_device *dev = nic->dev;
1ee6dd77 6786 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6787 register u64 val64;
6788 u16 subid;
6789
22747d6b
FR		 6790 rtnl_lock();
6791
6792 if (!netif_running(dev))
6793 goto out_unlock;
6794
92b84437 6795 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6796 /* The card is being reset, no point doing anything */
22747d6b 6797 goto out_unlock;
1da177e4
LT		 6798 }
6799
6800 subid = nic->pdev->subsystem_device;
a371a07d 6801 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6802 /*
6803 * Allow a small delay for the NICs self initiated
6804 * cleanup to complete.
6805 */
6806 msleep(100);
6807 }
1da177e4
LT		 6808
6809 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6810 if (LINK_IS_UP(val64)) {
6811 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6812 if (verify_xena_quiescence(nic)) {
6813 val64 = readq(&bar0->adapter_control);
6814 val64 |= ADAPTER_CNTL_EN;
1da177e4 6815 writeq(val64, &bar0->adapter_control);
19a60522 6816 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
d44570e4 6817 nic->device_type, subid)) {
19a60522
SS		 6818 val64 = readq(&bar0->gpio_control);
6819 val64 |= GPIO_CTRL_GPIO_0;
6820 writeq(val64, &bar0->gpio_control);
6821 val64 = readq(&bar0->gpio_control);
6822 } else {
6823 val64 |= ADAPTER_LED_ON;
6824 writeq(val64, &bar0->adapter_control);
a371a07d 6825 }
f957bcf0 6826 nic->device_enabled_once = true;
19a60522 6827 } else {
9e39f7c5
JP		 6828 DBG_PRINT(ERR_DBG,
6829 "%s: Error: device is not Quiescent\n",
6830 dev->name);
3a3d5756 6831 s2io_stop_all_tx_queue(nic);
1da177e4 6832 }
19a60522 6833 }
92c48799
SS		 6834 val64 = readq(&bar0->adapter_control);
6835 val64 |= ADAPTER_LED_ON;
6836 writeq(val64, &bar0->adapter_control);
6837 s2io_link(nic, LINK_UP);
19a60522
SS		 6838 } else {
6839 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6840 subid)) {
6841 val64 = readq(&bar0->gpio_control);
6842 val64 &= ~GPIO_CTRL_GPIO_0;
6843 writeq(val64, &bar0->gpio_control);
6844 val64 = readq(&bar0->gpio_control);
1da177e4 6845 }
92c48799
SS		 6846 /* turn off LED */
6847 val64 = readq(&bar0->adapter_control);
d44570e4 6848 val64 = val64 & (~ADAPTER_LED_ON);
92c48799 6849 writeq(val64, &bar0->adapter_control);
19a60522 6850 s2io_link(nic, LINK_DOWN);
1da177e4 6851 }
92b84437 6852 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6853
6854out_unlock:
d8d70caf 6855 rtnl_unlock();
1da177e4
LT		 6856}
6857
1ee6dd77 6858static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
d44570e4
JP		 6859 struct buffAdd *ba,
6860 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6861 u64 *temp2, int size)
5d3213cc
AR		 6862{
6863 struct net_device *dev = sp->dev;
491abf25 6864 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6865
6866 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6867 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6868 /* allocate skb */
6869 if (*skb) {
6870 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6871 /*
6872 * As Rx frame are not going to be processed,
6873 * using same mapped address for the Rxd
6874 * buffer pointer
6875 */
6d517a27 6876 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6877 } else {
6878 *skb = dev_alloc_skb(size);
6879 if (!(*skb)) {
9e39f7c5
JP		 6880 DBG_PRINT(INFO_DBG,
6881 "%s: Out of memory to allocate %s\n",
6882 dev->name, "1 buf mode SKBs");
ffb5df6c 6883 stats->mem_alloc_fail_cnt++;
5d3213cc
AR		 6884 return -ENOMEM ;
6885 }
ffb5df6c 6886 stats->mem_allocated += (*skb)->truesize;
5d3213cc
AR		 6887 /* storing the mapped addr in a temp variable
6888 * such it will be used for next rxd whose
6889 * Host Control is NULL
6890 */
6d517a27 6891 rxdp1->Buffer0_ptr = *temp0 =
d44570e4
JP		 6892 pci_map_single(sp->pdev, (*skb)->data,
6893 size - NET_IP_ALIGN,
6894 PCI_DMA_FROMDEVICE);
8d8bb39b 6895 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6896 goto memalloc_failed;
5d3213cc
AR		 6897 rxdp->Host_Control = (unsigned long) (*skb);
6898 }
6899 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6900 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6901 /* Two buffer Mode */
6902 if (*skb) {
6d517a27
VP		 6903 rxdp3->Buffer2_ptr = *temp2;
6904 rxdp3->Buffer0_ptr = *temp0;
6905 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6906 } else {
6907 *skb = dev_alloc_skb(size);
2ceaac75 6908 if (!(*skb)) {
9e39f7c5
JP		 6909 DBG_PRINT(INFO_DBG,
6910 "%s: Out of memory to allocate %s\n",
6911 dev->name,
6912 "2 buf mode SKBs");
ffb5df6c 6913 stats->mem_alloc_fail_cnt++;
2ceaac75
DR		 6914 return -ENOMEM;
6915 }
ffb5df6c 6916 stats->mem_allocated += (*skb)->truesize;
6d517a27 6917 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6918 pci_map_single(sp->pdev, (*skb)->data,
6919 dev->mtu + 4,
6920 PCI_DMA_FROMDEVICE);
8d8bb39b 6921 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6922 goto memalloc_failed;
6d517a27 6923 rxdp3->Buffer0_ptr = *temp0 =
d44570e4
JP		 6924 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6925 PCI_DMA_FROMDEVICE);
8d8bb39b 6926 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6927 rxdp3->Buffer0_ptr)) {
6928 pci_unmap_single(sp->pdev,
6929 (dma_addr_t)rxdp3->Buffer2_ptr,
6930 dev->mtu + 4,
6931 PCI_DMA_FROMDEVICE);
491abf25
VP		 6932 goto memalloc_failed;
6933 }
5d3213cc
AR		 6934 rxdp->Host_Control = (unsigned long) (*skb);
6935
6936 /* Buffer-1 will be dummy buffer not used */
6d517a27 6937 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6938 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
d44570e4 6939 PCI_DMA_FROMDEVICE);
8d8bb39b 6940 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6941 rxdp3->Buffer1_ptr)) {
6942 pci_unmap_single(sp->pdev,
6943 (dma_addr_t)rxdp3->Buffer0_ptr,
6944 BUF0_LEN, PCI_DMA_FROMDEVICE);
6945 pci_unmap_single(sp->pdev,
6946 (dma_addr_t)rxdp3->Buffer2_ptr,
6947 dev->mtu + 4,
6948 PCI_DMA_FROMDEVICE);
491abf25
VP		 6949 goto memalloc_failed;
6950 }
5d3213cc
AR		 6951 }
6952 }
6953 return 0;
d44570e4
JP		 6954
6955memalloc_failed:
6956 stats->pci_map_fail_cnt++;
6957 stats->mem_freed += (*skb)->truesize;
6958 dev_kfree_skb(*skb);
6959 return -ENOMEM;
5d3213cc 6960}
491abf25 6961
1ee6dd77
RB		 6962static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6963 int size)
5d3213cc
AR		 6964{
6965 struct net_device *dev = sp->dev;
6966 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4 6967 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
5d3213cc
AR		 6968 } else if (sp->rxd_mode == RXD_MODE_3B) {
6969 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6970 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
d44570e4 6971 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
5d3213cc
AR		 6972 }
6973}
6974
1ee6dd77 6975static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6976{
6977 int i, j, k, blk_cnt = 0, size;
5d3213cc 6978 struct config_param *config = &sp->config;
ffb5df6c 6979 struct mac_info *mac_control = &sp->mac_control;
5d3213cc 6980 struct net_device *dev = sp->dev;
1ee6dd77 6981 struct RxD_t *rxdp = NULL;
5d3213cc 6982 struct sk_buff *skb = NULL;
1ee6dd77 6983 struct buffAdd *ba = NULL;
5d3213cc
AR		 6984 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6985
6986 /* Calculate the size based on ring mode */
6987 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6988 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6989 if (sp->rxd_mode == RXD_MODE_1)
6990 size += NET_IP_ALIGN;
6991 else if (sp->rxd_mode == RXD_MODE_3B)
6992 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6993
6994 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 6995 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6996 struct ring_info *ring = &mac_control->rings[i];
6997
d44570e4 6998 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
5d3213cc
AR		 6999
7000 for (j = 0; j < blk_cnt; j++) {
7001 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
d44570e4
JP		 7002 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7003 if (sp->rxd_mode == RXD_MODE_3B)
13d866a9 7004 ba = &ring->ba[j][k];
d44570e4
JP		 7005 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7006 (u64 *)&temp0_64,
7007 (u64 *)&temp1_64,
7008 (u64 *)&temp2_64,
7009 size) == -ENOMEM) {
ac1f90d6
SS		 7010 return 0;
7011 }
5d3213cc
AR		 7012
7013 set_rxd_buffer_size(sp, rxdp, size);
7014 wmb();
7015 /* flip the Ownership bit to Hardware */
7016 rxdp->Control_1 |= RXD_OWN_XENA;
7017 }
7018 }
7019 }
7020 return 0;
7021
7022}
7023
d44570e4 7024static int s2io_add_isr(struct s2io_nic *sp)
1da177e4 7025{
e6a8fee2 7026 int ret = 0;
c92ca04b 7027 struct net_device *dev = sp->dev;
e6a8fee2 7028 int err = 0;
1da177e4 7029
eaae7f72 7030 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7031 ret = s2io_enable_msi_x(sp);
7032 if (ret) {
7033 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7034 sp->config.intr_type = INTA;
20346722 7035 }
1da177e4 7036
d44570e4
JP		 7037 /*
7038 * Store the values of the MSIX table in
7039 * the struct s2io_nic structure
7040 */
e6a8fee2 7041 store_xmsi_data(sp);
c92ca04b 7042
e6a8fee2 7043 /* After proper initialization of H/W, register ISR */
eaae7f72 7044 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7045 int i, msix_rx_cnt = 0;
7046
f61e0a35
SH		 7047 for (i = 0; i < sp->num_entries; i++) {
7048 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7049 if (sp->s2io_entries[i].type ==
d44570e4 7050 MSIX_RING_TYPE) {
ac731ab6
SH		 7051 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7052 dev->name, i);
7053 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7054 s2io_msix_ring_handle,
7055 0,
7056 sp->desc[i],
7057 sp->s2io_entries[i].arg);
ac731ab6 7058 } else if (sp->s2io_entries[i].type ==
d44570e4 7059 MSIX_ALARM_TYPE) {
ac731ab6 7060 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
d44570e4 7061 dev->name, i);
ac731ab6 7062 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7063 s2io_msix_fifo_handle,
7064 0,
7065 sp->desc[i],
7066 sp->s2io_entries[i].arg);
ac731ab6 7067
fb6a825b 7068 }
ac731ab6
SH		 7069 /* if either data or addr is zero print it. */
7070 if (!(sp->msix_info[i].addr &&
d44570e4 7071 sp->msix_info[i].data)) {
ac731ab6 7072 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7073 "%s @Addr:0x%llx Data:0x%llx\n",
7074 sp->desc[i],
7075 (unsigned long long)
7076 sp->msix_info[i].addr,
7077 (unsigned long long)
7078 ntohl(sp->msix_info[i].data));
ac731ab6 7079 } else
fb6a825b 7080 msix_rx_cnt++;
ac731ab6
SH		 7081 if (err) {
7082 remove_msix_isr(sp);
7083
7084 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7085 "%s:MSI-X-%d registration "
7086 "failed\n", dev->name, i);
ac731ab6
SH		 7087
7088 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7089 "%s: Defaulting to INTA\n",
7090 dev->name);
ac731ab6
SH		 7091 sp->config.intr_type = INTA;
7092 break;
fb6a825b 7093 }
ac731ab6
SH		 7094 sp->s2io_entries[i].in_use =
7095 MSIX_REGISTERED_SUCCESS;
c92ca04b 7096 }
e6a8fee2 7097 }
18b2b7bd 7098 if (!err) {
6cef2b8e 7099 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
9e39f7c5
JP		 7100 DBG_PRINT(INFO_DBG,
7101 "MSI-X-TX entries enabled through alarm vector\n");
18b2b7bd 7102 }
e6a8fee2 7103 }
eaae7f72 7104 if (sp->config.intr_type == INTA) {
d44570e4
JP		 7105 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7106 sp->name, dev);
e6a8fee2
AR		 7107 if (err) {
7108 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7109 dev->name);
7110 return -1;
7111 }
7112 }
7113 return 0;
7114}
d44570e4
JP		 7115
7116static void s2io_rem_isr(struct s2io_nic *sp)
e6a8fee2 7117{
18b2b7bd
SH		 7118 if (sp->config.intr_type == MSI_X)
7119 remove_msix_isr(sp);
7120 else
7121 remove_inta_isr(sp);
e6a8fee2
AR		 7122}
7123
d44570e4 7124static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
e6a8fee2
AR		 7125{
7126 int cnt = 0;
1ee6dd77 7127 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7128 register u64 val64 = 0;
5f490c96
SH		 7129 struct config_param *config;
7130 config = &sp->config;
e6a8fee2 7131
9f74ffde
SH		 7132 if (!is_s2io_card_up(sp))
7133 return;
7134
e6a8fee2
AR		 7135 del_timer_sync(&sp->alarm_timer);
7136 /* If s2io_set_link task is executing, wait till it completes. */
d44570e4 7137 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
e6a8fee2 7138 msleep(50);
92b84437 7139 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7140
5f490c96 7141 /* Disable napi */
f61e0a35
SH		 7142 if (sp->config.napi) {
7143 int off = 0;
7144 if (config->intr_type == MSI_X) {
7145 for (; off < sp->config.rx_ring_num; off++)
7146 napi_disable(&sp->mac_control.rings[off].napi);
d44570e4 7147 }
f61e0a35
SH		 7148 else
7149 napi_disable(&sp->napi);
7150 }
5f490c96 7151
e6a8fee2 7152 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7153 if (do_io)
7154 stop_nic(sp);
e6a8fee2
AR		 7155
7156 s2io_rem_isr(sp);
1da177e4 7157
01e16faa
SH		 7158 /* stop the tx queue, indicate link down */
7159 s2io_link(sp, LINK_DOWN);
7160
1da177e4 7161 /* Check if the device is Quiescent and then Reset the NIC */
d44570e4 7162 while (do_io) {
5d3213cc
AR		 7163 /* As per the HW requirement we need to replenish the
7164 * receive buffer to avoid the ring bump. Since there is
7165 * no intention of processing the Rx frame at this pointwe are
70f23fd6 7166 * just setting the ownership bit of rxd in Each Rx
5d3213cc
AR		 7167 * ring to HW and set the appropriate buffer size
7168 * based on the ring mode
7169 */
7170 rxd_owner_bit_reset(sp);
7171
1da177e4 7172 val64 = readq(&bar0->adapter_status);
19a60522 7173 if (verify_xena_quiescence(sp)) {
d44570e4
JP		 7174 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7175 break;
1da177e4
LT		 7176 }
7177
7178 msleep(50);
7179 cnt++;
7180 if (cnt == 10) {
9e39f7c5
JP		 7181 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7182 "adapter status reads 0x%llx\n",
d44570e4 7183 (unsigned long long)val64);
1da177e4
LT		 7184 break;
7185 }
d796fdb7
LV		 7186 }
7187 if (do_io)
7188 s2io_reset(sp);
1da177e4 7189
7ba013ac 7190 /* Free all Tx buffers */
1da177e4 7191 free_tx_buffers(sp);
7ba013ac 7192
7193 /* Free all Rx buffers */
1da177e4
LT		 7194 free_rx_buffers(sp);
7195
92b84437 7196 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7197}
7198
d44570e4 7199static void s2io_card_down(struct s2io_nic *sp)
d796fdb7
LV		 7200{
7201 do_s2io_card_down(sp, 1);
7202}
7203
d44570e4 7204static int s2io_card_up(struct s2io_nic *sp)
1da177e4 7205{
cc6e7c44 7206 int i, ret = 0;
1da177e4 7207 struct config_param *config;
ffb5df6c 7208 struct mac_info *mac_control;
d44570e4 7209 struct net_device *dev = (struct net_device *)sp->dev;
e6a8fee2 7210 u16 interruptible;
1da177e4
LT		 7211
7212 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7213 ret = init_nic(sp);
7214 if (ret != 0) {
1da177e4
LT		 7215 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7216 dev->name);
9f74ffde
SH		 7217 if (ret != -EIO)
7218 s2io_reset(sp);
7219 return ret;
1da177e4
LT		 7220 }
7221
20346722 7222 /*
7223 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7224 * Rx ring and initializing buffers into 30 Rx blocks
7225 */
1da177e4 7226 config = &sp->config;
ffb5df6c 7227 mac_control = &sp->mac_control;
1da177e4
LT		 7228
7229 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7230 struct ring_info *ring = &mac_control->rings[i];
7231
7232 ring->mtu = dev->mtu;
f0c54ace 7233 ring->lro = !!(dev->features & NETIF_F_LRO);
13d866a9 7234 ret = fill_rx_buffers(sp, ring, 1);
0425b46a 7235 if (ret) {
1da177e4
LT		 7236 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7237 dev->name);
7238 s2io_reset(sp);
7239 free_rx_buffers(sp);
7240 return -ENOMEM;
7241 }
7242 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
13d866a9 7243 ring->rx_bufs_left);
1da177e4 7244 }
5f490c96
SH		 7245
7246 /* Initialise napi */
f61e0a35 7247 if (config->napi) {
f61e0a35
SH		 7248 if (config->intr_type == MSI_X) {
7249 for (i = 0; i < sp->config.rx_ring_num; i++)
7250 napi_enable(&sp->mac_control.rings[i].napi);
7251 } else {
7252 napi_enable(&sp->napi);
7253 }
7254 }
5f490c96 7255
19a60522
SS		 7256 /* Maintain the state prior to the open */
7257 if (sp->promisc_flg)
7258 sp->promisc_flg = 0;
7259 if (sp->m_cast_flg) {
7260 sp->m_cast_flg = 0;
d44570e4 7261 sp->all_multi_pos = 0;
19a60522 7262 }
1da177e4
LT		 7263
7264 /* Setting its receive mode */
7265 s2io_set_multicast(dev);
7266
f0c54ace 7267 if (dev->features & NETIF_F_LRO) {
b41477f3 7268 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439 7269 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
d44570e4 7270 /* Check if we can use (if specified) user provided value */
7d3d0439
RA		 7271 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7272 sp->lro_max_aggr_per_sess = lro_max_pkts;
7273 }
7274
1da177e4
LT		 7275 /* Enable Rx Traffic and interrupts on the NIC */
7276 if (start_nic(sp)) {
7277 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7278 s2io_reset(sp);
e6a8fee2
AR		 7279 free_rx_buffers(sp);
7280 return -ENODEV;
7281 }
7282
7283 /* Add interrupt service routine */
7284 if (s2io_add_isr(sp) != 0) {
eaae7f72 7285 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7286 s2io_rem_isr(sp);
7287 s2io_reset(sp);
1da177e4
LT		 7288 free_rx_buffers(sp);
7289 return -ENODEV;
7290 }
7291
25fff88e 7292 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7293
01e16faa
SH		 7294 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7295
e6a8fee2 7296 /* Enable select interrupts */
9caab458 7297 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7298 if (sp->config.intr_type != INTA) {
7299 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7300 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7301 } else {
e6a8fee2 7302 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7303 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7304 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7305 }
7306
1da177e4
LT		 7307 return 0;
7308}
7309
20346722 7310/**
1da177e4
LT		 7311 * s2io_restart_nic - Resets the NIC.
7312 * @data : long pointer to the device private structure
7313 * Description:
7314 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7315 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7316 * the run time of the watch dog routine which is run holding a
7317 * spin lock.
7318 */
7319
c4028958 7320static void s2io_restart_nic(struct work_struct *work)
1da177e4 7321{
1ee6dd77 7322 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7323 struct net_device *dev = sp->dev;
1da177e4 7324
22747d6b
FR		 7325 rtnl_lock();
7326
7327 if (!netif_running(dev))
7328 goto out_unlock;
7329
e6a8fee2 7330 s2io_card_down(sp);
1da177e4 7331 if (s2io_card_up(sp)) {
d44570e4 7332 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
1da177e4 7333 }
3a3d5756 7334 s2io_wake_all_tx_queue(sp);
d44570e4 7335 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
22747d6b
FR		 7336out_unlock:
7337 rtnl_unlock();
1da177e4
LT		 7338}
7339
20346722 7340/**
7341 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7342 * @dev : Pointer to net device structure
7343 * Description:
7344 * This function is triggered if the Tx Queue is stopped
7345 * for a pre-defined amount of time when the Interface is still up.
7346 * If the Interface is jammed in such a situation, the hardware is
7347 * reset (by s2io_close) and restarted again (by s2io_open) to
7348 * overcome any problem that might have been caused in the hardware.
7349 * Return value:
7350 * void
7351 */
7352
7353static void s2io_tx_watchdog(struct net_device *dev)
7354{
4cf1653a 7355 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 7356 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7357
7358 if (netif_carrier_ok(dev)) {
ffb5df6c 7359 swstats->watchdog_timer_cnt++;
1da177e4 7360 schedule_work(&sp->rst_timer_task);
ffb5df6c 7361 swstats->soft_reset_cnt++;
1da177e4
LT		 7362 }
7363}
7364
7365/**
7366 * rx_osm_handler - To perform some OS related operations on SKB.
7367 * @sp: private member of the device structure,pointer to s2io_nic structure.
7368 * @skb : the socket buffer pointer.
7369 * @len : length of the packet
7370 * @cksum : FCS checksum of the frame.
7371 * @ring_no : the ring from which this RxD was extracted.
20346722 7372 * Description:
b41477f3 7373 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7374 * some OS related operations on the SKB before passing it to the upper
7375 * layers. It mainly checks if the checksum is OK, if so adds it to the
7376 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7377 * to the upper layer. If the checksum is wrong, it increments the Rx
7378 * packet error count, frees the SKB and returns error.
7379 * Return value:
7380 * SUCCESS on success and -1 on failure.
7381 */
1ee6dd77 7382static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7383{
1ee6dd77 7384 struct s2io_nic *sp = ring_data->nic;
d44570e4 7385 struct net_device *dev = (struct net_device *)ring_data->dev;
20346722 7386 struct sk_buff *skb = (struct sk_buff *)
d44570e4 7387 ((unsigned long)rxdp->Host_Control);
20346722 7388 int ring_no = ring_data->ring_no;
1da177e4 7389 u16 l3_csum, l4_csum;
863c11a9 7390 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7391 struct lro *uninitialized_var(lro);
f9046eb3 7392 u8 err_mask;
ffb5df6c 7393 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
da6971d8 7394
20346722 7395 skb->dev = dev;
c92ca04b 7396
863c11a9 7397 if (err) {
bd1034f0 7398 /* Check for parity error */
d44570e4 7399 if (err & 0x1)
ffb5df6c 7400 swstats->parity_err_cnt++;
d44570e4 7401
f9046eb3 7402 err_mask = err >> 48;
d44570e4
JP		 7403 switch (err_mask) {
7404 case 1:
ffb5df6c 7405 swstats->rx_parity_err_cnt++;
491976b2
SH		 7406 break;
7407
d44570e4 7408 case 2:
ffb5df6c 7409 swstats->rx_abort_cnt++;
491976b2
SH		 7410 break;
7411
d44570e4 7412 case 3:
ffb5df6c 7413 swstats->rx_parity_abort_cnt++;
491976b2
SH		 7414 break;
7415
d44570e4 7416 case 4:
ffb5df6c 7417 swstats->rx_rda_fail_cnt++;
491976b2
SH		 7418 break;
7419
d44570e4 7420 case 5:
ffb5df6c 7421 swstats->rx_unkn_prot_cnt++;
491976b2
SH		 7422 break;
7423
d44570e4 7424 case 6:
ffb5df6c 7425 swstats->rx_fcs_err_cnt++;
491976b2 7426 break;
bd1034f0 7427
d44570e4 7428 case 7:
ffb5df6c 7429 swstats->rx_buf_size_err_cnt++;
491976b2
SH		 7430 break;
7431
d44570e4 7432 case 8:
ffb5df6c 7433 swstats->rx_rxd_corrupt_cnt++;
491976b2
SH		 7434 break;
7435
d44570e4 7436 case 15:
ffb5df6c 7437 swstats->rx_unkn_err_cnt++;
491976b2
SH		 7438 break;
7439 }
863c11a9 7440 /*
d44570e4
JP		 7441 * Drop the packet if bad transfer code. Exception being
7442 * 0x5, which could be due to unsupported IPv6 extension header.
7443 * In this case, we let stack handle the packet.
7444 * Note that in this case, since checksum will be incorrect,
7445 * stack will validate the same.
7446 */
f9046eb3
OH		 7447 if (err_mask != 0x5) {
7448 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
d44570e4 7449 dev->name, err_mask);
dc56e634 7450 dev->stats.rx_crc_errors++;
ffb5df6c 7451 swstats->mem_freed
491976b2 7452 += skb->truesize;
863c11a9 7453 dev_kfree_skb(skb);
0425b46a 7454 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7455 rxdp->Host_Control = 0;
7456 return 0;
7457 }
20346722 7458 }
1da177e4 7459
20346722 7460 rxdp->Host_Control = 0;
da6971d8
AR		 7461 if (sp->rxd_mode == RXD_MODE_1) {
7462 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7463
da6971d8 7464 skb_put(skb, len);
6d517a27 7465 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7466 int get_block = ring_data->rx_curr_get_info.block_index;
7467 int get_off = ring_data->rx_curr_get_info.offset;
7468 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7469 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7470 unsigned char *buff = skb_push(skb, buf0_len);
7471
1ee6dd77 7472 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8 7473 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7474 skb_put(skb, buf2_len);
da6971d8 7475 }
20346722 7476
d44570e4
JP		 7477 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7478 ((!ring_data->lro) ||
7479 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
b437a8cc 7480 (dev->features & NETIF_F_RXCSUM)) {
20346722 7481 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7482 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7483 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7484 /*
1da177e4
LT		 7485 * NIC verifies if the Checksum of the received
7486 * frame is Ok or not and accordingly returns
7487 * a flag in the RxD.
7488 */
7489 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7490 if (ring_data->lro) {
06f0c139 7491 u32 tcp_len = 0;
7d3d0439
RA		 7492 u8 *tcp;
7493 int ret = 0;
7494
0425b46a 7495 ret = s2io_club_tcp_session(ring_data,
d44570e4
JP		 7496 skb->data, &tcp,
7497 &tcp_len, &lro,
7498 rxdp, sp);
7d3d0439 7499 switch (ret) {
d44570e4
JP		 7500 case 3: /* Begin anew */
7501 lro->parent = skb;
7502 goto aggregate;
7503 case 1: /* Aggregate */
7504 lro_append_pkt(sp, lro, skb, tcp_len);
7505 goto aggregate;
7506 case 4: /* Flush session */
7507 lro_append_pkt(sp, lro, skb, tcp_len);
7508 queue_rx_frame(lro->parent,
7509 lro->vlan_tag);
7510 clear_lro_session(lro);
ffb5df6c 7511 swstats->flush_max_pkts++;
d44570e4
JP		 7512 goto aggregate;
7513 case 2: /* Flush both */
7514 lro->parent->data_len = lro->frags_len;
ffb5df6c 7515 swstats->sending_both++;
d44570e4
JP		 7516 queue_rx_frame(lro->parent,
7517 lro->vlan_tag);
7518 clear_lro_session(lro);
7519 goto send_up;
7520 case 0: /* sessions exceeded */
7521 case -1: /* non-TCP or not L2 aggregatable */
7522 case 5: /*
7523 * First pkt in session not
7524 * L3/L4 aggregatable
7525 */
7526 break;
7527 default:
7528 DBG_PRINT(ERR_DBG,
7529 "%s: Samadhana!!\n",
7530 __func__);
7531 BUG();
7d3d0439
RA		 7532 }
7533 }
1da177e4 7534 } else {
20346722 7535 /*
7536 * Packet with erroneous checksum, let the
1da177e4
LT		 7537 * upper layers deal with it.
7538 */
bc8acf2c 7539 skb_checksum_none_assert(skb);
1da177e4 7540 }
cdb5bf02 7541 } else
bc8acf2c 7542 skb_checksum_none_assert(skb);
cdb5bf02 7543
ffb5df6c 7544 swstats->mem_freed += skb->truesize;
7d3d0439 7545send_up:
0c8dfc83 7546 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7547 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7548aggregate:
0425b46a 7549 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7550 return SUCCESS;
7551}
7552
7553/**
7554 * s2io_link - stops/starts the Tx queue.
7555 * @sp : private member of the device structure, which is a pointer to the
7556 * s2io_nic structure.
7557 * @link : inidicates whether link is UP/DOWN.
7558 * Description:
7559 * This function stops/starts the Tx queue depending on whether the link
20346722 7560 * status of the NIC is is down or up. This is called by the Alarm
7561 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7562 * Return value:
7563 * void.
7564 */
7565
d44570e4 7566static void s2io_link(struct s2io_nic *sp, int link)
1da177e4 7567{
d44570e4 7568 struct net_device *dev = (struct net_device *)sp->dev;
ffb5df6c 7569 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7570
7571 if (link != sp->last_link_state) {
b7c5678f 7572 init_tti(sp, link);
1da177e4
LT		 7573 if (link == LINK_DOWN) {
7574 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7575 s2io_stop_all_tx_queue(sp);
1da177e4 7576 netif_carrier_off(dev);
ffb5df6c
JP		 7577 if (swstats->link_up_cnt)
7578 swstats->link_up_time =
7579 jiffies - sp->start_time;
7580 swstats->link_down_cnt++;
1da177e4
LT		 7581 } else {
7582 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
ffb5df6c
JP		 7583 if (swstats->link_down_cnt)
7584 swstats->link_down_time =
d44570e4 7585 jiffies - sp->start_time;
ffb5df6c 7586 swstats->link_up_cnt++;
1da177e4 7587 netif_carrier_on(dev);
3a3d5756 7588 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7589 }
7590 }
7591 sp->last_link_state = link;
491976b2 7592 sp->start_time = jiffies;
1da177e4
LT		 7593}
7594
20346722 7595/**
7596 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7597 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7598 * s2io_nic structure.
7599 * Description:
7600 * This function initializes a few of the PCI and PCI-X configuration registers
7601 * with recommended values.
7602 * Return value:
7603 * void
7604 */
7605
d44570e4 7606static void s2io_init_pci(struct s2io_nic *sp)
1da177e4 7607{
20346722 7608 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7609
7610 /* Enable Data Parity Error Recovery in PCI-X command register. */
7611 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7612 &(pcix_cmd));
1da177e4 7613 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7614 (pcix_cmd | 1));
1da177e4 7615 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7616 &(pcix_cmd));
1da177e4
LT		 7617
7618 /* Set the PErr Response bit in PCI command register. */
7619 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7620 pci_write_config_word(sp->pdev, PCI_COMMAND,
7621 (pci_cmd | PCI_COMMAND_PARITY));
7622 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7623}
7624
3a3d5756 7625static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
d44570e4 7626 u8 *dev_multiq)
9dc737a7 7627{
1853e2e1
JM		 7628 int i;
7629
d44570e4 7630 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
9e39f7c5 7631 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
d44570e4 7632 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7633
7634 if (tx_fifo_num < 1)
7635 tx_fifo_num = 1;
7636 else
7637 tx_fifo_num = MAX_TX_FIFOS;
7638
9e39f7c5 7639 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
9dc737a7 7640 }
2fda096d 7641
6cfc482b 7642 if (multiq)
3a3d5756 7643 *dev_multiq = multiq;
6cfc482b
SH		 7644
7645 if (tx_steering_type && (1 == tx_fifo_num)) {
7646 if (tx_steering_type != TX_DEFAULT_STEERING)
7647 DBG_PRINT(ERR_DBG,
9e39f7c5 7648 "Tx steering is not supported with "
d44570e4 7649 "one fifo. Disabling Tx steering.\n");
6cfc482b
SH		 7650 tx_steering_type = NO_STEERING;
7651 }
7652
7653 if ((tx_steering_type < NO_STEERING) ||
d44570e4
JP		 7654 (tx_steering_type > TX_DEFAULT_STEERING)) {
7655 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7656 "Requested transmit steering not supported\n");
7657 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
6cfc482b 7658 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7659 }
7660
0425b46a 7661 if (rx_ring_num > MAX_RX_RINGS) {
d44570e4 7662 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7663 "Requested number of rx rings not supported\n");
7664 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
d44570e4 7665 MAX_RX_RINGS);
0425b46a 7666 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7667 }
0425b46a 7668
eccb8628 7669 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9e39f7c5 7670 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
9dc737a7
AR		 7671 "Defaulting to INTA\n");
7672 *dev_intr_type = INTA;
7673 }
596c5c97 7674
9dc737a7 7675 if ((*dev_intr_type == MSI_X) &&
d44570e4
JP		 7676 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7677 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
9e39f7c5 7678 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
d44570e4 7679 "Defaulting to INTA\n");
9dc737a7
AR		 7680 *dev_intr_type = INTA;
7681 }
fb6a825b 7682
6d517a27 7683 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9e39f7c5
JP		 7684 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7685 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
6d517a27 7686 rx_ring_mode = 1;
9dc737a7 7687 }
1853e2e1
JM		 7688
7689 for (i = 0; i < MAX_RX_RINGS; i++)
7690 if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
7691 DBG_PRINT(ERR_DBG, "Requested rx ring size not "
7692 "supported\nDefaulting to %d\n",
7693 MAX_RX_BLOCKS_PER_RING);
7694 rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
7695 }
7696
9dc737a7
AR		 7697 return SUCCESS;
7698}
7699
9fc93a41
SS		 7700/**
7701 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7702 * or Traffic class respectively.
b7c5678f 7703 * @nic: device private variable
9fc93a41
SS		 7704 * Description: The function configures the receive steering to
7705 * desired receive ring.
7706 * Return Value: SUCCESS on success and
7707 * '-1' on failure (endian settings incorrect).
7708 */
7709static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7710{
7711 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7712 register u64 val64 = 0;
7713
7714 if (ds_codepoint > 63)
7715 return FAILURE;
7716
7717 val64 = RTS_DS_MEM_DATA(ring);
7718 writeq(val64, &bar0->rts_ds_mem_data);
7719
7720 val64 = RTS_DS_MEM_CTRL_WE |
7721 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7722 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7723
7724 writeq(val64, &bar0->rts_ds_mem_ctrl);
7725
7726 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
d44570e4
JP		 7727 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7728 S2IO_BIT_RESET);
9fc93a41
SS		 7729}
7730
04025095
SH		 7731static const struct net_device_ops s2io_netdev_ops = {
7732 .ndo_open = s2io_open,
7733 .ndo_stop = s2io_close,
7734 .ndo_get_stats = s2io_get_stats,
7735 .ndo_start_xmit = s2io_xmit,
7736 .ndo_validate_addr = eth_validate_addr,
7737 .ndo_set_multicast_list = s2io_set_multicast,
7738 .ndo_do_ioctl = s2io_ioctl,
7739 .ndo_set_mac_address = s2io_set_mac_addr,
7740 .ndo_change_mtu = s2io_change_mtu,
b437a8cc 7741 .ndo_set_features = s2io_set_features,
04025095
SH		 7742 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7743 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7744 .ndo_tx_timeout = s2io_tx_watchdog,
7745#ifdef CONFIG_NET_POLL_CONTROLLER
7746 .ndo_poll_controller = s2io_netpoll,
7747#endif
7748};
7749
1da177e4 7750/**
20346722 7751 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7752 * @pdev : structure containing the PCI related information of the device.
7753 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7754 * Description:
7755 * The function initializes an adapter identified by the pci_dec structure.
20346722 7756 * All OS related initialization including memory and device structure and
7757 * initlaization of the device private variable is done. Also the swapper
7758 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7759 * registers of the device.
7760 * Return value:
7761 * returns 0 on success and negative on failure.
7762 */
7763
7764static int __devinit
7765s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7766{
1ee6dd77 7767 struct s2io_nic *sp;
1da177e4 7768 struct net_device *dev;
1da177e4 7769 int i, j, ret;
f957bcf0 7770 int dma_flag = false;
1da177e4
LT		 7771 u32 mac_up, mac_down;
7772 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7773 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7774 u16 subid;
1da177e4 7775 struct config_param *config;
ffb5df6c 7776 struct mac_info *mac_control;
541ae68f 7777 int mode;
cc6e7c44 7778 u8 dev_intr_type = intr_type;
3a3d5756 7779 u8 dev_multiq = 0;
1da177e4 7780
3a3d5756
SH		 7781 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7782 if (ret)
9dc737a7 7783 return ret;
1da177e4 7784
d44570e4
JP		 7785 ret = pci_enable_device(pdev);
7786 if (ret) {
1da177e4 7787 DBG_PRINT(ERR_DBG,
9e39f7c5 7788 "%s: pci_enable_device failed\n", __func__);
1da177e4
LT		 7789 return ret;
7790 }
7791
6a35528a 7792 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
9e39f7c5 7793 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
f957bcf0 7794 dma_flag = true;
d44570e4 7795 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7796 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7797 "Unable to obtain 64bit DMA "
7798 "for consistent allocations\n");
1da177e4
LT		 7799 pci_disable_device(pdev);
7800 return -ENOMEM;
7801 }
284901a9 7802 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
9e39f7c5 7803 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
1da177e4
LT		 7804 } else {
7805 pci_disable_device(pdev);
7806 return -ENOMEM;
7807 }
d44570e4
JP		 7808 ret = pci_request_regions(pdev, s2io_driver_name);
7809 if (ret) {
9e39f7c5 7810 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
d44570e4 7811 __func__, ret);
eccb8628
VP		 7812 pci_disable_device(pdev);
7813 return -ENODEV;
1da177e4 7814 }
3a3d5756 7815 if (dev_multiq)
6cfc482b 7816 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7817 else
b19fa1fa 7818 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7819 if (dev == NULL) {
7820 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7821 pci_disable_device(pdev);
7822 pci_release_regions(pdev);
7823 return -ENODEV;
7824 }
7825
7826 pci_set_master(pdev);
7827 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7828 SET_NETDEV_DEV(dev, &pdev->dev);
7829
7830 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7831 sp = netdev_priv(dev);
1da177e4
LT		 7832 sp->dev = dev;
7833 sp->pdev = pdev;
1da177e4 7834 sp->high_dma_flag = dma_flag;
f957bcf0 7835 sp->device_enabled_once = false;
da6971d8
AR		 7836 if (rx_ring_mode == 1)
7837 sp->rxd_mode = RXD_MODE_1;
7838 if (rx_ring_mode == 2)
7839 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7840
eaae7f72 7841 sp->config.intr_type = dev_intr_type;
1da177e4 7842
541ae68f 7843 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
d44570e4 7844 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
541ae68f 7845 sp->device_type = XFRAME_II_DEVICE;
7846 else
7847 sp->device_type = XFRAME_I_DEVICE;
7848
6aa20a22 7849
1da177e4
LT		 7850 /* Initialize some PCI/PCI-X fields of the NIC. */
7851 s2io_init_pci(sp);
7852
20346722 7853 /*
1da177e4 7854 * Setting the device configuration parameters.
20346722 7855 * Most of these parameters can be specified by the user during
7856 * module insertion as they are module loadable parameters. If
7857 * these parameters are not not specified during load time, they
1da177e4
LT		 7858 * are initialized with default values.
7859 */
1da177e4 7860 config = &sp->config;
ffb5df6c 7861 mac_control = &sp->mac_control;
1da177e4 7862
596c5c97 7863 config->napi = napi;
6cfc482b 7864 config->tx_steering_type = tx_steering_type;
596c5c97 7865
1da177e4 7866 /* Tx side parameters. */
6cfc482b
SH		 7867 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7868 config->tx_fifo_num = MAX_TX_FIFOS;
7869 else
7870 config->tx_fifo_num = tx_fifo_num;
7871
7872 /* Initialize the fifos used for tx steering */
7873 if (config->tx_fifo_num < 5) {
d44570e4
JP		 7874 if (config->tx_fifo_num == 1)
7875 sp->total_tcp_fifos = 1;
7876 else
7877 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7878 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7879 sp->total_udp_fifos = 1;
7880 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
6cfc482b
SH		 7881 } else {
7882 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
d44570e4 7883 FIFO_OTHER_MAX_NUM);
6cfc482b
SH		 7884 sp->udp_fifo_idx = sp->total_tcp_fifos;
7885 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7886 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7887 }
7888
3a3d5756 7889 config->multiq = dev_multiq;
6cfc482b 7890 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7891 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7892
7893 tx_cfg->fifo_len = tx_fifo_len[i];
7894 tx_cfg->fifo_priority = i;
1da177e4
LT		 7895 }
7896
20346722 7897 /* mapping the QoS priority to the configured fifos */
7898 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7899 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7900
6cfc482b
SH		 7901 /* map the hashing selector table to the configured fifos */
7902 for (i = 0; i < config->tx_fifo_num; i++)
7903 sp->fifo_selector[i] = fifo_selector[i];
7904
7905
1da177e4
LT		 7906 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7907 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7908 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7909
7910 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7911 if (tx_cfg->fifo_len < 65) {
1da177e4
LT		 7912 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7913 break;
7914 }
7915 }
fed5eccd
AR		 7916 /* + 2 because one Txd for skb->data and one Txd for UFO */
7917 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7918
7919 /* Rx side parameters. */
1da177e4 7920 config->rx_ring_num = rx_ring_num;
0425b46a 7921 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7922 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7923 struct ring_info *ring = &mac_control->rings[i];
7924
7925 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7926 rx_cfg->ring_priority = i;
7927 ring->rx_bufs_left = 0;
7928 ring->rxd_mode = sp->rxd_mode;
7929 ring->rxd_count = rxd_count[sp->rxd_mode];
7930 ring->pdev = sp->pdev;
7931 ring->dev = sp->dev;
1da177e4
LT		 7932 }
7933
7934 for (i = 0; i < rx_ring_num; i++) {
13d866a9
JP		 7935 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7936
7937 rx_cfg->ring_org = RING_ORG_BUFF1;
7938 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
1da177e4
LT		 7939 }
7940
7941 /* Setting Mac Control parameters */
7942 mac_control->rmac_pause_time = rmac_pause_time;
7943 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7944 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7945
7946
1da177e4
LT		 7947 /* initialize the shared memory used by the NIC and the host */
7948 if (init_shared_mem(sp)) {
d44570e4 7949 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
1da177e4
LT		 7950 ret = -ENOMEM;
7951 goto mem_alloc_failed;
7952 }
7953
275f165f 7954 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 7955 if (!sp->bar0) {
19a60522 7956 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7957 dev->name);
7958 ret = -ENOMEM;
7959 goto bar0_remap_failed;
7960 }
7961
275f165f 7962 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 7963 if (!sp->bar1) {
19a60522 7964 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7965 dev->name);
7966 ret = -ENOMEM;
7967 goto bar1_remap_failed;
7968 }
7969
7970 dev->irq = pdev->irq;
d44570e4 7971 dev->base_addr = (unsigned long)sp->bar0;
1da177e4
LT		 7972
7973 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7974 for (j = 0; j < MAX_TX_FIFOS; j++) {
d44570e4
JP		 7975 mac_control->tx_FIFO_start[j] =
7976 (struct TxFIFO_element __iomem *)
7977 (sp->bar1 + (j * 0x00020000));
1da177e4
LT		 7978 }
7979
7980 /* Driver entry points */
04025095 7981 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 7982 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
b437a8cc
MM		 7983 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
7984 NETIF_F_TSO | NETIF_F_TSO6 |
7985 NETIF_F_RXCSUM | NETIF_F_LRO;
7986 dev->features |= dev->hw_features |
7987 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7988 if (sp->device_type & XFRAME_II_DEVICE) {
7989 dev->hw_features |= NETIF_F_UFO;
7990 if (ufo)
7991 dev->features |= NETIF_F_UFO;
7992 }
f957bcf0 7993 if (sp->high_dma_flag == true)
1da177e4 7994 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7995 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7996 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7997 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7998
e960fc5c 7999 pci_save_state(sp->pdev);
1da177e4
LT		 8000
8001 /* Setting swapper control on the NIC, for proper reset operation */
8002 if (s2io_set_swapper(sp)) {
9e39f7c5 8003 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
1da177e4
LT		 8004 dev->name);
8005 ret = -EAGAIN;
8006 goto set_swap_failed;
8007 }
8008
541ae68f 8009 /* Verify if the Herc works on the slot its placed into */
8010 if (sp->device_type & XFRAME_II_DEVICE) {
8011 mode = s2io_verify_pci_mode(sp);
8012 if (mode < 0) {
9e39f7c5
JP		 8013 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8014 __func__);
541ae68f 8015 ret = -EBADSLT;
8016 goto set_swap_failed;
8017 }
8018 }
8019
f61e0a35
SH		 8020 if (sp->config.intr_type == MSI_X) {
8021 sp->num_entries = config->rx_ring_num + 1;
8022 ret = s2io_enable_msi_x(sp);
8023
8024 if (!ret) {
8025 ret = s2io_test_msi(sp);
8026 /* rollback MSI-X, will re-enable during add_isr() */
8027 remove_msix_isr(sp);
8028 }
8029 if (ret) {
8030
8031 DBG_PRINT(ERR_DBG,
9e39f7c5 8032 "MSI-X requested but failed to enable\n");
f61e0a35
SH		 8033 sp->config.intr_type = INTA;
8034 }
8035 }
8036
8037 if (config->intr_type == MSI_X) {
13d866a9
JP		 8038 for (i = 0; i < config->rx_ring_num ; i++) {
8039 struct ring_info *ring = &mac_control->rings[i];
8040
8041 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8042 }
f61e0a35
SH		 8043 } else {
8044 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8045 }
8046
541ae68f 8047 /* Not needed for Herc */
8048 if (sp->device_type & XFRAME_I_DEVICE) {
8049 /*
8050 * Fix for all "FFs" MAC address problems observed on
8051 * Alpha platforms
8052 */
8053 fix_mac_address(sp);
8054 s2io_reset(sp);
8055 }
1da177e4
LT		 8056
8057 /*
1da177e4
LT		 8058 * MAC address initialization.
8059 * For now only one mac address will be read and used.
8060 */
8061 bar0 = sp->bar0;
8062 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
d44570e4 8063 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8064 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8065 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 8066 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8067 S2IO_BIT_RESET);
1da177e4 8068 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4 8069 mac_down = (u32)tmp64;
1da177e4
LT		 8070 mac_up = (u32) (tmp64 >> 32);
8071
1da177e4
LT		 8072 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8073 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8074 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8075 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8076 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8077 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8078
1da177e4
LT		 8079 /* Set the factory defined MAC address initially */
8080 dev->addr_len = ETH_ALEN;
8081 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8082 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8083
faa4f796
SH		 8084 /* initialize number of multicast & unicast MAC entries variables */
8085 if (sp->device_type == XFRAME_I_DEVICE) {
8086 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8087 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8088 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8089 } else if (sp->device_type == XFRAME_II_DEVICE) {
8090 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8091 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8092 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8093 }
8094
8095 /* store mac addresses from CAM to s2io_nic structure */
8096 do_s2io_store_unicast_mc(sp);
8097
f61e0a35
SH		 8098 /* Configure MSIX vector for number of rings configured plus one */
8099 if ((sp->device_type == XFRAME_II_DEVICE) &&
d44570e4 8100 (config->intr_type == MSI_X))
f61e0a35
SH		 8101 sp->num_entries = config->rx_ring_num + 1;
8102
d44570e4 8103 /* Store the values of the MSIX table in the s2io_nic structure */
c77dd43e 8104 store_xmsi_data(sp);
b41477f3
AR		 8105 /* reset Nic and bring it to known state */
8106 s2io_reset(sp);
8107
1da177e4 8108 /*
99993af6 8109 * Initialize link state flags
541ae68f 8110 * and the card state parameter
1da177e4 8111 */
92b84437 8112 sp->state = 0;
1da177e4 8113
1da177e4 8114 /* Initialize spinlocks */
13d866a9
JP		 8115 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8116 struct fifo_info *fifo = &mac_control->fifos[i];
8117
8118 spin_lock_init(&fifo->tx_lock);
8119 }
db874e65 8120
20346722 8121 /*
8122 * SXE-002: Configure link and activity LED to init state
8123 * on driver load.
1da177e4
LT		 8124 */
8125 subid = sp->pdev->subsystem_device;
8126 if ((subid & 0xFF) >= 0x07) {
8127 val64 = readq(&bar0->gpio_control);
8128 val64 |= 0x0000800000000000ULL;
8129 writeq(val64, &bar0->gpio_control);
8130 val64 = 0x0411040400000000ULL;
d44570e4 8131 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 8132 val64 = readq(&bar0->gpio_control);
8133 }
8134
8135 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8136
8137 if (register_netdev(dev)) {
8138 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8139 ret = -ENODEV;
8140 goto register_failed;
8141 }
9dc737a7 8142 s2io_vpd_read(sp);
926bd900 8143 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
d44570e4 8144 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
44c10138 8145 sp->product_name, pdev->revision);
b41477f3
AR		 8146 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8147 s2io_driver_version);
9e39f7c5
JP		 8148 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8149 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
9dc737a7 8150 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8151 mode = s2io_print_pci_mode(sp);
541ae68f 8152 if (mode < 0) {
541ae68f 8153 ret = -EBADSLT;
9dc737a7 8154 unregister_netdev(dev);
541ae68f 8155 goto set_swap_failed;
8156 }
541ae68f 8157 }
d44570e4
JP		 8158 switch (sp->rxd_mode) {
8159 case RXD_MODE_1:
8160 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8161 dev->name);
8162 break;
8163 case RXD_MODE_3B:
8164 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8165 dev->name);
8166 break;
9dc737a7 8167 }
db874e65 8168
f61e0a35
SH		 8169 switch (sp->config.napi) {
8170 case 0:
8171 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8172 break;
8173 case 1:
db874e65 8174 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8175 break;
8176 }
3a3d5756
SH		 8177
8178 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
d44570e4 8179 sp->config.tx_fifo_num);
3a3d5756 8180
0425b46a
SH		 8181 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8182 sp->config.rx_ring_num);
8183
d44570e4
JP		 8184 switch (sp->config.intr_type) {
8185 case INTA:
8186 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8187 break;
8188 case MSI_X:
8189 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8190 break;
9dc737a7 8191 }
3a3d5756 8192 if (sp->config.multiq) {
13d866a9
JP		 8193 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8194 struct fifo_info *fifo = &mac_control->fifos[i];
8195
8196 fifo->multiq = config->multiq;
8197 }
3a3d5756 8198 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
d44570e4 8199 dev->name);
3a3d5756
SH		 8200 } else
8201 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
d44570e4 8202 dev->name);
3a3d5756 8203
6cfc482b
SH		 8204 switch (sp->config.tx_steering_type) {
8205 case NO_STEERING:
d44570e4
JP		 8206 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8207 dev->name);
8208 break;
6cfc482b 8209 case TX_PRIORITY_STEERING:
d44570e4
JP		 8210 DBG_PRINT(ERR_DBG,
8211 "%s: Priority steering enabled for transmit\n",
8212 dev->name);
6cfc482b
SH		 8213 break;
8214 case TX_DEFAULT_STEERING:
d44570e4
JP		 8215 DBG_PRINT(ERR_DBG,
8216 "%s: Default steering enabled for transmit\n",
8217 dev->name);
6cfc482b
SH		 8218 }
8219
f0c54ace
AW		 8220 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8221 dev->name);
db874e65 8222 if (ufo)
d44570e4
JP		 8223 DBG_PRINT(ERR_DBG,
8224 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8225 dev->name);
7ba013ac 8226 /* Initialize device name */
9dc737a7 8227 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8228
cd0fce03
BL		 8229 if (vlan_tag_strip)
8230 sp->vlan_strip_flag = 1;
8231 else
8232 sp->vlan_strip_flag = 0;
8233
20346722 8234 /*
8235 * Make Link state as off at this point, when the Link change
8236 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8237 * the right state.
8238 */
8239 netif_carrier_off(dev);
1da177e4
LT		 8240
8241 return 0;
8242
d44570e4
JP		 8243register_failed:
8244set_swap_failed:
1da177e4 8245 iounmap(sp->bar1);
d44570e4 8246bar1_remap_failed:
1da177e4 8247 iounmap(sp->bar0);
d44570e4
JP		 8248bar0_remap_failed:
8249mem_alloc_failed:
1da177e4
LT		 8250 free_shared_mem(sp);
8251 pci_disable_device(pdev);
eccb8628 8252 pci_release_regions(pdev);
1da177e4
LT		 8253 pci_set_drvdata(pdev, NULL);
8254 free_netdev(dev);
8255
8256 return ret;
8257}
8258
8259/**
20346722 8260 * s2io_rem_nic - Free the PCI device
1da177e4 8261 * @pdev: structure containing the PCI related information of the device.
20346722 8262 * Description: This function is called by the Pci subsystem to release a
1da177e4 8263 * PCI device and free up all resource held up by the device. This could
20346722 8264 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8265 * from memory.
8266 */
8267
8268static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8269{
a31ff388 8270 struct net_device *dev = pci_get_drvdata(pdev);
1ee6dd77 8271 struct s2io_nic *sp;
1da177e4
LT		 8272
8273 if (dev == NULL) {
8274 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8275 return;
8276 }
8277
4cf1653a 8278 sp = netdev_priv(dev);
23f333a2
TH		 8279
8280 cancel_work_sync(&sp->rst_timer_task);
8281 cancel_work_sync(&sp->set_link_task);
8282
1da177e4
LT		 8283 unregister_netdev(dev);
8284
8285 free_shared_mem(sp);
8286 iounmap(sp->bar0);
8287 iounmap(sp->bar1);
eccb8628 8288 pci_release_regions(pdev);
1da177e4 8289 pci_set_drvdata(pdev, NULL);
1da177e4 8290 free_netdev(dev);
19a60522 8291 pci_disable_device(pdev);
1da177e4
LT		 8292}
8293
8294/**
8295 * s2io_starter - Entry point for the driver
8296 * Description: This function is the entry point for the driver. It verifies
8297 * the module loadable parameters and initializes PCI configuration space.
8298 */
8299
43b7c451 8300static int __init s2io_starter(void)
1da177e4 8301{
29917620 8302 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8303}
8304
8305/**
20346722 8306 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8307 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8308 */
8309
372cc597 8310static __exit void s2io_closer(void)
1da177e4
LT		 8311{
8312 pci_unregister_driver(&s2io_driver);
8313 DBG_PRINT(INIT_DBG, "cleanup done\n");
8314}
8315
8316module_init(s2io_starter);
8317module_exit(s2io_closer);
7d3d0439 8318
6aa20a22 8319static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
d44570e4
JP		 8320 struct tcphdr **tcp, struct RxD_t *rxdp,
8321 struct s2io_nic *sp)
7d3d0439
RA		 8322{
8323 int ip_off;
8324 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8325
8326 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
d44570e4
JP		 8327 DBG_PRINT(INIT_DBG,
8328 "%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8329 __func__);
7d3d0439
RA		 8330 return -1;
8331 }
8332
cdb5bf02 8333 /* Checking for DIX type or DIX type with VLAN */
d44570e4 8334 if ((l2_type == 0) || (l2_type == 4)) {
cdb5bf02
SH		 8335 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8336 /*
8337 * If vlan stripping is disabled and the frame is VLAN tagged,
8338 * shift the offset by the VLAN header size bytes.
8339 */
cd0fce03 8340 if ((!sp->vlan_strip_flag) &&
d44570e4 8341 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
cdb5bf02
SH		 8342 ip_off += HEADER_VLAN_SIZE;
8343 } else {
7d3d0439 8344 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8345 return -1;
7d3d0439
RA		 8346 }
8347
8348 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8349 ip_len = (u8)((*ip)->ihl);
8350 ip_len <<= 2;
8351 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8352
8353 return 0;
8354}
8355
1ee6dd77 8356static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8357 struct tcphdr *tcp)
8358{
d44570e4
JP		 8359 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8360 if ((lro->iph->saddr != ip->saddr) ||
8361 (lro->iph->daddr != ip->daddr) ||
8362 (lro->tcph->source != tcp->source) ||
8363 (lro->tcph->dest != tcp->dest))
7d3d0439
RA		 8364 return -1;
8365 return 0;
8366}
8367
8368static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8369{
d44570e4 8370 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
7d3d0439
RA		 8371}
8372
1ee6dd77 8373static void initiate_new_session(struct lro *lro, u8 *l2h,
d44570e4
JP		 8374 struct iphdr *ip, struct tcphdr *tcp,
8375 u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8376{
d44570e4 8377 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8378 lro->l2h = l2h;
8379 lro->iph = ip;
8380 lro->tcph = tcp;
8381 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8382 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8383 lro->sg_num = 1;
8384 lro->total_len = ntohs(ip->tot_len);
8385 lro->frags_len = 0;
cdb5bf02 8386 lro->vlan_tag = vlan_tag;
6aa20a22 8387 /*
d44570e4
JP		 8388 * Check if we saw TCP timestamp.
8389 * Other consistency checks have already been done.
8390 */
7d3d0439 8391 if (tcp->doff == 8) {
c8855953
SR		 8392 __be32 *ptr;
8393 ptr = (__be32 *)(tcp+1);
7d3d0439 8394 lro->saw_ts = 1;
c8855953 8395 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8396 lro->cur_tsecr = *(ptr+2);
8397 }
8398 lro->in_use = 1;
8399}
8400
1ee6dd77 8401static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8402{
8403 struct iphdr *ip = lro->iph;
8404 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8405 __sum16 nchk;
ffb5df6c
JP		 8406 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8407
d44570e4 8408 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8409
8410 /* Update L3 header */
8411 ip->tot_len = htons(lro->total_len);
8412 ip->check = 0;
8413 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8414 ip->check = nchk;
8415
8416 /* Update L4 header */
8417 tcp->ack_seq = lro->tcp_ack;
8418 tcp->window = lro->window;
8419
8420 /* Update tsecr field if this session has timestamps enabled */
8421 if (lro->saw_ts) {
c8855953 8422 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8423 *(ptr+2) = lro->cur_tsecr;
8424 }
8425
8426 /* Update counters required for calculation of
8427 * average no. of packets aggregated.
8428 */
ffb5df6c
JP		 8429 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8430 swstats->num_aggregations++;
7d3d0439
RA		 8431}
8432
1ee6dd77 8433static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
d44570e4 8434 struct tcphdr *tcp, u32 l4_pyld)
7d3d0439 8435{
d44570e4 8436 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8437 lro->total_len += l4_pyld;
8438 lro->frags_len += l4_pyld;
8439 lro->tcp_next_seq += l4_pyld;
8440 lro->sg_num++;
8441
8442 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8443 lro->tcp_ack = tcp->ack_seq;
8444 lro->window = tcp->window;
6aa20a22 8445
7d3d0439 8446 if (lro->saw_ts) {
c8855953 8447 __be32 *ptr;
7d3d0439 8448 /* Update tsecr and tsval from this packet */
c8855953
SR		 8449 ptr = (__be32 *)(tcp+1);
8450 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8451 lro->cur_tsecr = *(ptr + 2);
8452 }
8453}
8454
1ee6dd77 8455static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8456 struct tcphdr *tcp, u32 tcp_pyld_len)
8457{
7d3d0439
RA		 8458 u8 *ptr;
8459
d44570e4 8460 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
79dc1901 8461
7d3d0439
RA		 8462 if (!tcp_pyld_len) {
8463 /* Runt frame or a pure ack */
8464 return -1;
8465 }
8466
8467 if (ip->ihl != 5) /* IP has options */
8468 return -1;
8469
75c30b13
AR		 8470 /* If we see CE codepoint in IP header, packet is not mergeable */
8471 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8472 return -1;
8473
8474 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
d44570e4
JP		 8475 if (tcp->urg || tcp->psh || tcp->rst ||
8476 tcp->syn || tcp->fin ||
8477 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8478 /*
8479 * Currently recognize only the ack control word and
8480 * any other control field being set would result in
8481 * flushing the LRO session
8482 */
8483 return -1;
8484 }
8485
6aa20a22 8486 /*
7d3d0439
RA		 8487 * Allow only one TCP timestamp option. Don't aggregate if
8488 * any other options are detected.
8489 */
8490 if (tcp->doff != 5 && tcp->doff != 8)
8491 return -1;
8492
8493 if (tcp->doff == 8) {
6aa20a22 8494 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8495 while (*ptr == TCPOPT_NOP)
8496 ptr++;
8497 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8498 return -1;
8499
8500 /* Ensure timestamp value increases monotonically */
8501 if (l_lro)
c8855953 8502 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8503 return -1;
8504
8505 /* timestamp echo reply should be non-zero */
c8855953 8506 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8507 return -1;
8508 }
8509
8510 return 0;
8511}
8512
d44570e4
JP		 8513static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8514 u8 **tcp, u32 *tcp_len, struct lro **lro,
8515 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8516{
8517 struct iphdr *ip;
8518 struct tcphdr *tcph;
8519 int ret = 0, i;
cdb5bf02 8520 u16 vlan_tag = 0;
ffb5df6c 8521 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439 8522
d44570e4
JP		 8523 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8524 rxdp, sp);
8525 if (ret)
7d3d0439 8526 return ret;
7d3d0439 8527
d44570e4
JP		 8528 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8529
cdb5bf02 8530 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8531 tcph = (struct tcphdr *)*tcp;
8532 *tcp_len = get_l4_pyld_length(ip, tcph);
d44570e4 8533 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8534 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8535 if (l_lro->in_use) {
8536 if (check_for_socket_match(l_lro, ip, tcph))
8537 continue;
8538 /* Sock pair matched */
8539 *lro = l_lro;
8540
8541 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
9e39f7c5
JP		 8542 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8543 "expected 0x%x, actual 0x%x\n",
8544 __func__,
7d3d0439
RA		 8545 (*lro)->tcp_next_seq,
8546 ntohl(tcph->seq));
8547
ffb5df6c 8548 swstats->outof_sequence_pkts++;
7d3d0439
RA		 8549 ret = 2;
8550 break;
8551 }
8552
d44570e4
JP		 8553 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8554 *tcp_len))
7d3d0439
RA		 8555 ret = 1; /* Aggregate */
8556 else
8557 ret = 2; /* Flush both */
8558 break;
8559 }
8560 }
8561
8562 if (ret == 0) {
8563 /* Before searching for available LRO objects,
8564 * check if the pkt is L3/L4 aggregatable. If not
8565 * don't create new LRO session. Just send this
8566 * packet up.
8567 */
d44570e4 8568 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
7d3d0439 8569 return 5;
7d3d0439 8570
d44570e4 8571 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8572 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8573 if (!(l_lro->in_use)) {
8574 *lro = l_lro;
8575 ret = 3; /* Begin anew */
8576 break;
8577 }
8578 }
8579 }
8580
8581 if (ret == 0) { /* sessions exceeded */
9e39f7c5 8582 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
b39d66a8 8583 __func__);
7d3d0439
RA		 8584 *lro = NULL;
8585 return ret;
8586 }
8587
8588 switch (ret) {
d44570e4
JP		 8589 case 3:
8590 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8591 vlan_tag);
8592 break;
8593 case 2:
8594 update_L3L4_header(sp, *lro);
8595 break;
8596 case 1:
8597 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8598 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7d3d0439 8599 update_L3L4_header(sp, *lro);
d44570e4
JP		 8600 ret = 4; /* Flush the LRO */
8601 }
8602 break;
8603 default:
9e39f7c5 8604 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
d44570e4 8605 break;
7d3d0439
RA		 8606 }
8607
8608 return ret;
8609}
8610
1ee6dd77 8611static void clear_lro_session(struct lro *lro)
7d3d0439 8612{
1ee6dd77 8613 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8614
8615 memset(lro, 0, lro_struct_size);
8616}
8617
cdb5bf02 8618static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8619{
8620 struct net_device *dev = skb->dev;
4cf1653a 8621 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8622
8623 skb->protocol = eth_type_trans(skb, dev);
d44570e4 8624 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8625 /* Queueing the vlan frame to the upper layer */
8626 if (sp->config.napi)
8627 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8628 else
8629 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8630 } else {
8631 if (sp->config.napi)
8632 netif_receive_skb(skb);
8633 else
8634 netif_rx(skb);
8635 }
7d3d0439
RA		 8636}
8637
1ee6dd77 8638static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
d44570e4 8639 struct sk_buff *skb, u32 tcp_len)
7d3d0439 8640{
75c30b13 8641 struct sk_buff *first = lro->parent;
ffb5df6c 8642 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439
RA		 8643
8644 first->len += tcp_len;
8645 first->data_len = lro->frags_len;
8646 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8647 if (skb_shinfo(first)->frag_list)
8648 lro->last_frag->next = skb;
7d3d0439
RA		 8649 else
8650 skb_shinfo(first)->frag_list = skb;
372cc597 8651 first->truesize += skb->truesize;
75c30b13 8652 lro->last_frag = skb;
ffb5df6c 8653 swstats->clubbed_frms_cnt++;
7d3d0439 8654}
d796fdb7
LV		 8655
8656/**
8657 * s2io_io_error_detected - called when PCI error is detected
8658 * @pdev: Pointer to PCI device
8453d43f 8659 * @state: The current pci connection state
d796fdb7
LV		 8660 *
8661 * This function is called after a PCI bus error affecting
8662 * this device has been detected.
8663 */
8664static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
d44570e4 8665 pci_channel_state_t state)
d796fdb7
LV		 8666{
8667 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8668 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8669
8670 netif_device_detach(netdev);
8671
1e3c8bd6
DN		 8672 if (state == pci_channel_io_perm_failure)
8673 return PCI_ERS_RESULT_DISCONNECT;
8674
d796fdb7
LV		 8675 if (netif_running(netdev)) {
8676 /* Bring down the card, while avoiding PCI I/O */
8677 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8678 }
8679 pci_disable_device(pdev);
8680
8681 return PCI_ERS_RESULT_NEED_RESET;
8682}
8683
8684/**
8685 * s2io_io_slot_reset - called after the pci bus has been reset.
8686 * @pdev: Pointer to PCI device
8687 *
8688 * Restart the card from scratch, as if from a cold-boot.
8689 * At this point, the card has exprienced a hard reset,
8690 * followed by fixups by BIOS, and has its config space
8691 * set up identically to what it was at cold boot.
8692 */
8693static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8694{
8695 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8696 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8697
8698 if (pci_enable_device(pdev)) {
6cef2b8e 8699 pr_err("Cannot re-enable PCI device after reset.\n");
d796fdb7
LV		 8700 return PCI_ERS_RESULT_DISCONNECT;
8701 }
8702
8703 pci_set_master(pdev);
8704 s2io_reset(sp);
8705
8706 return PCI_ERS_RESULT_RECOVERED;
8707}
8708
8709/**
8710 * s2io_io_resume - called when traffic can start flowing again.
8711 * @pdev: Pointer to PCI device
8712 *
8713 * This callback is called when the error recovery driver tells
8714 * us that its OK to resume normal operation.
8715 */
8716static void s2io_io_resume(struct pci_dev *pdev)
8717{
8718 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8719 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8720
8721 if (netif_running(netdev)) {
8722 if (s2io_card_up(sp)) {
6cef2b8e 8723 pr_err("Can't bring device back up after reset.\n");
d796fdb7
LV		 8724 return;
8725 }
8726
8727 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8728 s2io_card_down(sp);
6cef2b8e 8729 pr_err("Can't restore mac addr after reset.\n");
d796fdb7
LV		 8730 return;
8731 }
8732 }
8733
8734 netif_device_attach(netdev);
fd2ea0a7 8735 netif_tx_wake_all_queues(netdev);
d796fdb7 8736}
Linux 6.x block layer and io_uring tree(s)