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[netdrvr] Stop using legacy hooks ->self_test_count, ->get_stats_count
[linux-2.6-block.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
f7ccf420
SH		 31#ifdef CONFIG_R8169_NAPI
32#define NAPI_SUFFIX "-NAPI"
33#else
34#define NAPI_SUFFIX ""
35#endif
36
37#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 38#define MODULENAME "r8169"
39#define PFX MODULENAME ": "
40
41#ifdef RTL8169_DEBUG
42#define assert(expr) \
5b0384f4
FR		 43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
1da177e4
LT		 47#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
48#else
49#define assert(expr) do {} while (0)
50#define dprintk(fmt, args...) do {} while (0)
51#endif /* RTL8169_DEBUG */
52
b57b7e5a 53#define R8169_MSG_DEFAULT \
f0e837d9 54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 55
1da177e4
LT		 56#define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
59#ifdef CONFIG_R8169_NAPI
60#define rtl8169_rx_skb netif_receive_skb
0b50f81d 61#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 62#define rtl8169_rx_quota(count, quota) min(count, quota)
63#else
64#define rtl8169_rx_skb netif_rx
0b50f81d 65#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 66#define rtl8169_rx_quota(count, quota) count
67#endif
68
1da177e4 69/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 70static const int max_interrupt_work = 20;
1da177e4
LT		 71
72/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
73 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 74static const int multicast_filter_limit = 32;
1da177e4
LT		 75
76/* MAC address length */
77#define MAC_ADDR_LEN 6
78
79#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 82#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 83#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
84#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
85#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
86
87#define R8169_REGS_SIZE 256
88#define R8169_NAPI_WEIGHT 64
89#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
90#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
91#define RX_BUF_SIZE 1536 /* Rx Buffer size */
92#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
93#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
94
95#define RTL8169_TX_TIMEOUT (6*HZ)
96#define RTL8169_PHY_TIMEOUT (10*HZ)
97
98/* write/read MMIO register */
99#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
100#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
101#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
102#define RTL_R8(reg) readb (ioaddr + (reg))
103#define RTL_R16(reg) readw (ioaddr + (reg))
104#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
105
106enum mac_version {
ba6eb6ee
FR		 107 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
108 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
109 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
110 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
111 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 112 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530
FR		 113 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
114 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
cdf1a608
FR		 115 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
116 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
117 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
1da177e4
LT		 118};
119
120enum phy_version {
121 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
122 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
123 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
124 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
125 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
126 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
127};
128
1da177e4
LT		 129#define _R(NAME,MAC,MASK) \
130 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
131
3c6bee1d 132static const struct {
1da177e4
LT		 133 const char *name;
134 u8 mac_version;
135 u32 RxConfigMask; /* Clears the bits supported by this chip */
136} rtl_chip_info[] = {
ba6eb6ee
FR		 137 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
138 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
139 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
140 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 148};
149#undef _R
150
bcf0bf90
FR		 151enum cfg_version {
152 RTL_CFG_0 = 0x00,
153 RTL_CFG_1,
154 RTL_CFG_2
155};
156
07ce4064
FR		 157static void rtl_hw_start_8169(struct net_device *);
158static void rtl_hw_start_8168(struct net_device *);
159static void rtl_hw_start_8101(struct net_device *);
160
1da177e4 161static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
167 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
73f5e28b 168 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 169 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032,
171 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 172 {0,},
173};
174
175MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
176
177static int rx_copybreak = 200;
178static int use_dac;
b57b7e5a
SH		 179static struct {
180 u32 msg_enable;
181} debug = { -1 };
1da177e4 182
07d3f51f
FR		 183enum rtl_registers {
184 MAC0 = 0, /* Ethernet hardware address. */
773d2021 185 MAC4 = 4,
07d3f51f
FR		 186 MAR0 = 8, /* Multicast filter. */
187 CounterAddrLow = 0x10,
188 CounterAddrHigh = 0x14,
189 TxDescStartAddrLow = 0x20,
190 TxDescStartAddrHigh = 0x24,
191 TxHDescStartAddrLow = 0x28,
192 TxHDescStartAddrHigh = 0x2c,
193 FLASH = 0x30,
194 ERSR = 0x36,
195 ChipCmd = 0x37,
196 TxPoll = 0x38,
197 IntrMask = 0x3c,
198 IntrStatus = 0x3e,
199 TxConfig = 0x40,
200 RxConfig = 0x44,
201 RxMissed = 0x4c,
202 Cfg9346 = 0x50,
203 Config0 = 0x51,
204 Config1 = 0x52,
205 Config2 = 0x53,
206 Config3 = 0x54,
207 Config4 = 0x55,
208 Config5 = 0x56,
209 MultiIntr = 0x5c,
210 PHYAR = 0x60,
211 TBICSR = 0x64,
212 TBI_ANAR = 0x68,
213 TBI_LPAR = 0x6a,
214 PHYstatus = 0x6c,
215 RxMaxSize = 0xda,
216 CPlusCmd = 0xe0,
217 IntrMitigate = 0xe2,
218 RxDescAddrLow = 0xe4,
219 RxDescAddrHigh = 0xe8,
220 EarlyTxThres = 0xec,
221 FuncEvent = 0xf0,
222 FuncEventMask = 0xf4,
223 FuncPresetState = 0xf8,
224 FuncForceEvent = 0xfc,
1da177e4
LT		 225};
226
07d3f51f 227enum rtl_register_content {
1da177e4 228 /* InterruptStatusBits */
07d3f51f
FR		 229 SYSErr = 0x8000,
230 PCSTimeout = 0x4000,
231 SWInt = 0x0100,
232 TxDescUnavail = 0x0080,
233 RxFIFOOver = 0x0040,
234 LinkChg = 0x0020,
235 RxOverflow = 0x0010,
236 TxErr = 0x0008,
237 TxOK = 0x0004,
238 RxErr = 0x0002,
239 RxOK = 0x0001,
1da177e4
LT		 240
241 /* RxStatusDesc */
9dccf611
FR		 242 RxFOVF = (1 << 23),
243 RxRWT = (1 << 22),
244 RxRES = (1 << 21),
245 RxRUNT = (1 << 20),
246 RxCRC = (1 << 19),
1da177e4
LT		 247
248 /* ChipCmdBits */
07d3f51f
FR		 249 CmdReset = 0x10,
250 CmdRxEnb = 0x08,
251 CmdTxEnb = 0x04,
252 RxBufEmpty = 0x01,
1da177e4 253
275391a4
FR		 254 /* TXPoll register p.5 */
255 HPQ = 0x80, /* Poll cmd on the high prio queue */
256 NPQ = 0x40, /* Poll cmd on the low prio queue */
257 FSWInt = 0x01, /* Forced software interrupt */
258
1da177e4 259 /* Cfg9346Bits */
07d3f51f
FR		 260 Cfg9346_Lock = 0x00,
261 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 262
263 /* rx_mode_bits */
07d3f51f
FR		 264 AcceptErr = 0x20,
265 AcceptRunt = 0x10,
266 AcceptBroadcast = 0x08,
267 AcceptMulticast = 0x04,
268 AcceptMyPhys = 0x02,
269 AcceptAllPhys = 0x01,
1da177e4
LT		 270
271 /* RxConfigBits */
07d3f51f
FR		 272 RxCfgFIFOShift = 13,
273 RxCfgDMAShift = 8,
1da177e4
LT		 274
275 /* TxConfigBits */
276 TxInterFrameGapShift = 24,
277 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
278
5d06a99f
FR		 279 /* Config1 register p.24 */
280 PMEnable = (1 << 0), /* Power Management Enable */
281
6dccd16b
FR		 282 /* Config2 register p. 25 */
283 PCI_Clock_66MHz = 0x01,
284 PCI_Clock_33MHz = 0x00,
285
61a4dcc2
FR		 286 /* Config3 register p.25 */
287 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
288 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
289
5d06a99f 290 /* Config5 register p.27 */
61a4dcc2
FR		 291 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
292 MWF = (1 << 5), /* Accept Multicast wakeup frame */
293 UWF = (1 << 4), /* Accept Unicast wakeup frame */
294 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 295 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
296
1da177e4
LT		 297 /* TBICSR p.28 */
298 TBIReset = 0x80000000,
299 TBILoopback = 0x40000000,
300 TBINwEnable = 0x20000000,
301 TBINwRestart = 0x10000000,
302 TBILinkOk = 0x02000000,
303 TBINwComplete = 0x01000000,
304
305 /* CPlusCmd p.31 */
0e485150 306 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 307 RxVlan = (1 << 6),
308 RxChkSum = (1 << 5),
309 PCIDAC = (1 << 4),
310 PCIMulRW = (1 << 3),
0e485150
FR		 311 INTT_0 = 0x0000, // 8168
312 INTT_1 = 0x0001, // 8168
313 INTT_2 = 0x0002, // 8168
314 INTT_3 = 0x0003, // 8168
1da177e4
LT		 315
316 /* rtl8169_PHYstatus */
07d3f51f
FR		 317 TBI_Enable = 0x80,
318 TxFlowCtrl = 0x40,
319 RxFlowCtrl = 0x20,
320 _1000bpsF = 0x10,
321 _100bps = 0x08,
322 _10bps = 0x04,
323 LinkStatus = 0x02,
324 FullDup = 0x01,
1da177e4 325
1da177e4 326 /* _TBICSRBit */
07d3f51f 327 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 328
329 /* DumpCounterCommand */
07d3f51f 330 CounterDump = 0x8,
1da177e4
LT		 331};
332
07d3f51f 333enum desc_status_bit {
1da177e4
LT		 334 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
335 RingEnd = (1 << 30), /* End of descriptor ring */
336 FirstFrag = (1 << 29), /* First segment of a packet */
337 LastFrag = (1 << 28), /* Final segment of a packet */
338
339 /* Tx private */
340 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
341 MSSShift = 16, /* MSS value position */
342 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
343 IPCS = (1 << 18), /* Calculate IP checksum */
344 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
345 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
346 TxVlanTag = (1 << 17), /* Add VLAN tag */
347
348 /* Rx private */
349 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
350 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
351
352#define RxProtoUDP (PID1)
353#define RxProtoTCP (PID0)
354#define RxProtoIP (PID1 | PID0)
355#define RxProtoMask RxProtoIP
356
357 IPFail = (1 << 16), /* IP checksum failed */
358 UDPFail = (1 << 15), /* UDP/IP checksum failed */
359 TCPFail = (1 << 14), /* TCP/IP checksum failed */
360 RxVlanTag = (1 << 16), /* VLAN tag available */
361};
362
363#define RsvdMask 0x3fffc000
364
365struct TxDesc {
6cccd6e7
REB		 366 __le32 opts1;
367 __le32 opts2;
368 __le64 addr;
1da177e4
LT		 369};
370
371struct RxDesc {
6cccd6e7
REB		 372 __le32 opts1;
373 __le32 opts2;
374 __le64 addr;
1da177e4
LT		 375};
376
377struct ring_info {
378 struct sk_buff *skb;
379 u32 len;
380 u8 __pad[sizeof(void *) - sizeof(u32)];
381};
382
383struct rtl8169_private {
384 void __iomem *mmio_addr; /* memory map physical address */
385 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 386 struct net_device *dev;
bea3348e 387 struct napi_struct napi;
1da177e4
LT		 388 struct net_device_stats stats; /* statistics of net device */
389 spinlock_t lock; /* spin lock flag */
b57b7e5a 390 u32 msg_enable;
1da177e4
LT		 391 int chipset;
392 int mac_version;
393 int phy_version;
394 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
395 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
396 u32 dirty_rx;
397 u32 dirty_tx;
398 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
399 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
400 dma_addr_t TxPhyAddr;
401 dma_addr_t RxPhyAddr;
402 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
403 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 404 unsigned align;
1da177e4
LT		 405 unsigned rx_buf_sz;
406 struct timer_list timer;
407 u16 cp_cmd;
0e485150
FR		 408 u16 intr_event;
409 u16 napi_event;
1da177e4
LT		 410 u16 intr_mask;
411 int phy_auto_nego_reg;
412 int phy_1000_ctrl_reg;
413#ifdef CONFIG_R8169_VLAN
414 struct vlan_group *vlgrp;
415#endif
416 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
417 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
418 void (*phy_reset_enable)(void __iomem *);
07ce4064 419 void (*hw_start)(struct net_device *);
1da177e4
LT		 420 unsigned int (*phy_reset_pending)(void __iomem *);
421 unsigned int (*link_ok)(void __iomem *);
c4028958 422 struct delayed_work task;
61a4dcc2 423 unsigned wol_enabled : 1;
1da177e4
LT		 424};
425
979b6c13 426MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 427MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 428module_param(rx_copybreak, int, 0);
1b7efd58 429MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 430module_param(use_dac, int, 0);
431MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 432module_param_named(debug, debug.msg_enable, int, 0);
433MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 434MODULE_LICENSE("GPL");
435MODULE_VERSION(RTL8169_VERSION);
436
437static int rtl8169_open(struct net_device *dev);
438static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 439static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 440static int rtl8169_init_ring(struct net_device *dev);
07ce4064 441static void rtl_hw_start(struct net_device *dev);
1da177e4 442static int rtl8169_close(struct net_device *dev);
07ce4064 443static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 444static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 445static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 446static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 447 void __iomem *, u32 budget);
4dcb7d33 448static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 449static void rtl8169_down(struct net_device *dev);
99f252b0 450static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 451
452#ifdef CONFIG_R8169_NAPI
bea3348e 453static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4
LT		 454#endif
455
1da177e4 456static const unsigned int rtl8169_rx_config =
5b0384f4 457 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 458
07d3f51f 459static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 460{
461 int i;
462
07d3f51f 463 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
1da177e4 464
2371408c 465 for (i = 20; i > 0; i--) {
07d3f51f
FR		 466 /*
467 * Check if the RTL8169 has completed writing to the specified
468 * MII register.
469 */
5b0384f4 470 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 471 break;
2371408c 472 udelay(25);
1da177e4
LT		 473 }
474}
475
07d3f51f 476static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 477{
478 int i, value = -1;
479
07d3f51f 480 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
1da177e4 481
2371408c 482 for (i = 20; i > 0; i--) {
07d3f51f
FR		 483 /*
484 * Check if the RTL8169 has completed retrieving data from
485 * the specified MII register.
486 */
1da177e4
LT		 487 if (RTL_R32(PHYAR) & 0x80000000) {
488 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
489 break;
490 }
2371408c 491 udelay(25);
1da177e4
LT		 492 }
493 return value;
494}
495
496static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
497{
498 RTL_W16(IntrMask, 0x0000);
499
500 RTL_W16(IntrStatus, 0xffff);
501}
502
503static void rtl8169_asic_down(void __iomem *ioaddr)
504{
505 RTL_W8(ChipCmd, 0x00);
506 rtl8169_irq_mask_and_ack(ioaddr);
507 RTL_R16(CPlusCmd);
508}
509
510static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
511{
512 return RTL_R32(TBICSR) & TBIReset;
513}
514
515static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
516{
64e4bfb4 517 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 518}
519
520static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
521{
522 return RTL_R32(TBICSR) & TBILinkOk;
523}
524
525static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
526{
527 return RTL_R8(PHYstatus) & LinkStatus;
528}
529
530static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
531{
532 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
533}
534
535static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
536{
537 unsigned int val;
538
9e0db8ef
FR		 539 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
540 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 541}
542
543static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 544 struct rtl8169_private *tp,
545 void __iomem *ioaddr)
1da177e4
LT		 546{
547 unsigned long flags;
548
549 spin_lock_irqsave(&tp->lock, flags);
550 if (tp->link_ok(ioaddr)) {
551 netif_carrier_on(dev);
b57b7e5a
SH		 552 if (netif_msg_ifup(tp))
553 printk(KERN_INFO PFX "%s: link up\n", dev->name);
554 } else {
555 if (netif_msg_ifdown(tp))
556 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 557 netif_carrier_off(dev);
b57b7e5a 558 }
1da177e4
LT		 559 spin_unlock_irqrestore(&tp->lock, flags);
560}
561
61a4dcc2
FR		 562static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
563{
564 struct rtl8169_private *tp = netdev_priv(dev);
565 void __iomem *ioaddr = tp->mmio_addr;
566 u8 options;
567
568 wol->wolopts = 0;
569
570#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
571 wol->supported = WAKE_ANY;
572
573 spin_lock_irq(&tp->lock);
574
575 options = RTL_R8(Config1);
576 if (!(options & PMEnable))
577 goto out_unlock;
578
579 options = RTL_R8(Config3);
580 if (options & LinkUp)
581 wol->wolopts |= WAKE_PHY;
582 if (options & MagicPacket)
583 wol->wolopts |= WAKE_MAGIC;
584
585 options = RTL_R8(Config5);
586 if (options & UWF)
587 wol->wolopts |= WAKE_UCAST;
588 if (options & BWF)
5b0384f4 589 wol->wolopts |= WAKE_BCAST;
61a4dcc2 590 if (options & MWF)
5b0384f4 591 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 592
593out_unlock:
594 spin_unlock_irq(&tp->lock);
595}
596
597static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
598{
599 struct rtl8169_private *tp = netdev_priv(dev);
600 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 601 unsigned int i;
61a4dcc2
FR		 602 static struct {
603 u32 opt;
604 u16 reg;
605 u8 mask;
606 } cfg[] = {
607 { WAKE_ANY, Config1, PMEnable },
608 { WAKE_PHY, Config3, LinkUp },
609 { WAKE_MAGIC, Config3, MagicPacket },
610 { WAKE_UCAST, Config5, UWF },
611 { WAKE_BCAST, Config5, BWF },
612 { WAKE_MCAST, Config5, MWF },
613 { WAKE_ANY, Config5, LanWake }
614 };
615
616 spin_lock_irq(&tp->lock);
617
618 RTL_W8(Cfg9346, Cfg9346_Unlock);
619
620 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
621 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
622 if (wol->wolopts & cfg[i].opt)
623 options |= cfg[i].mask;
624 RTL_W8(cfg[i].reg, options);
625 }
626
627 RTL_W8(Cfg9346, Cfg9346_Lock);
628
629 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
630
631 spin_unlock_irq(&tp->lock);
632
633 return 0;
634}
635
1da177e4
LT		 636static void rtl8169_get_drvinfo(struct net_device *dev,
637 struct ethtool_drvinfo *info)
638{
639 struct rtl8169_private *tp = netdev_priv(dev);
640
641 strcpy(info->driver, MODULENAME);
642 strcpy(info->version, RTL8169_VERSION);
643 strcpy(info->bus_info, pci_name(tp->pci_dev));
644}
645
646static int rtl8169_get_regs_len(struct net_device *dev)
647{
648 return R8169_REGS_SIZE;
649}
650
651static int rtl8169_set_speed_tbi(struct net_device *dev,
652 u8 autoneg, u16 speed, u8 duplex)
653{
654 struct rtl8169_private *tp = netdev_priv(dev);
655 void __iomem *ioaddr = tp->mmio_addr;
656 int ret = 0;
657 u32 reg;
658
659 reg = RTL_R32(TBICSR);
660 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
661 (duplex == DUPLEX_FULL)) {
662 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
663 } else if (autoneg == AUTONEG_ENABLE)
664 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
665 else {
b57b7e5a
SH		 666 if (netif_msg_link(tp)) {
667 printk(KERN_WARNING "%s: "
668 "incorrect speed setting refused in TBI mode\n",
669 dev->name);
670 }
1da177e4
LT		 671 ret = -EOPNOTSUPP;
672 }
673
674 return ret;
675}
676
677static int rtl8169_set_speed_xmii(struct net_device *dev,
678 u8 autoneg, u16 speed, u8 duplex)
679{
680 struct rtl8169_private *tp = netdev_priv(dev);
681 void __iomem *ioaddr = tp->mmio_addr;
682 int auto_nego, giga_ctrl;
683
64e4bfb4
FR		 684 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
685 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
686 ADVERTISE_100HALF | ADVERTISE_100FULL);
687 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
688 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 689
690 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 691 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
692 ADVERTISE_100HALF | ADVERTISE_100FULL);
693 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 694 } else {
695 if (speed == SPEED_10)
64e4bfb4 696 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 697 else if (speed == SPEED_100)
64e4bfb4 698 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 699 else if (speed == SPEED_1000)
64e4bfb4 700 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 701
702 if (duplex == DUPLEX_HALF)
64e4bfb4 703 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 704
705 if (duplex == DUPLEX_FULL)
64e4bfb4 706 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 707
708 /* This tweak comes straight from Realtek's driver. */
709 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
710 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
64e4bfb4 711 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 712 }
713 }
714
715 /* The 8100e/8101e do Fast Ethernet only. */
716 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
717 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
718 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
64e4bfb4 719 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 720 netif_msg_link(tp)) {
721 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
722 dev->name);
723 }
64e4bfb4 724 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 725 }
726
623a1593
FR		 727 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
728
2584fbc3
RS		 729 if (tp->mac_version == RTL_GIGA_MAC_VER_12) {
730 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
731 mdio_write(ioaddr, 0x1f, 0x0000);
732 mdio_write(ioaddr, 0x0e, 0x0000);
733 }
734
1da177e4
LT		 735 tp->phy_auto_nego_reg = auto_nego;
736 tp->phy_1000_ctrl_reg = giga_ctrl;
737
64e4bfb4
FR		 738 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
739 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
740 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 741 return 0;
742}
743
744static int rtl8169_set_speed(struct net_device *dev,
745 u8 autoneg, u16 speed, u8 duplex)
746{
747 struct rtl8169_private *tp = netdev_priv(dev);
748 int ret;
749
750 ret = tp->set_speed(dev, autoneg, speed, duplex);
751
64e4bfb4 752 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 753 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
754
755 return ret;
756}
757
758static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
759{
760 struct rtl8169_private *tp = netdev_priv(dev);
761 unsigned long flags;
762 int ret;
763
764 spin_lock_irqsave(&tp->lock, flags);
765 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
766 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 767
1da177e4
LT		 768 return ret;
769}
770
771static u32 rtl8169_get_rx_csum(struct net_device *dev)
772{
773 struct rtl8169_private *tp = netdev_priv(dev);
774
775 return tp->cp_cmd & RxChkSum;
776}
777
778static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
779{
780 struct rtl8169_private *tp = netdev_priv(dev);
781 void __iomem *ioaddr = tp->mmio_addr;
782 unsigned long flags;
783
784 spin_lock_irqsave(&tp->lock, flags);
785
786 if (data)
787 tp->cp_cmd |= RxChkSum;
788 else
789 tp->cp_cmd &= ~RxChkSum;
790
791 RTL_W16(CPlusCmd, tp->cp_cmd);
792 RTL_R16(CPlusCmd);
793
794 spin_unlock_irqrestore(&tp->lock, flags);
795
796 return 0;
797}
798
799#ifdef CONFIG_R8169_VLAN
800
801static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
802 struct sk_buff *skb)
803{
804 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
805 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
806}
807
808static void rtl8169_vlan_rx_register(struct net_device *dev,
809 struct vlan_group *grp)
810{
811 struct rtl8169_private *tp = netdev_priv(dev);
812 void __iomem *ioaddr = tp->mmio_addr;
813 unsigned long flags;
814
815 spin_lock_irqsave(&tp->lock, flags);
816 tp->vlgrp = grp;
817 if (tp->vlgrp)
818 tp->cp_cmd |= RxVlan;
819 else
820 tp->cp_cmd &= ~RxVlan;
821 RTL_W16(CPlusCmd, tp->cp_cmd);
822 RTL_R16(CPlusCmd);
823 spin_unlock_irqrestore(&tp->lock, flags);
824}
825
1da177e4
LT		 826static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
827 struct sk_buff *skb)
828{
829 u32 opts2 = le32_to_cpu(desc->opts2);
830 int ret;
831
832 if (tp->vlgrp && (opts2 & RxVlanTag)) {
07d3f51f 833 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 834 ret = 0;
835 } else
836 ret = -1;
837 desc->opts2 = 0;
838 return ret;
839}
840
841#else /* !CONFIG_R8169_VLAN */
842
843static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
844 struct sk_buff *skb)
845{
846 return 0;
847}
848
849static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
850 struct sk_buff *skb)
851{
852 return -1;
853}
854
855#endif
856
857static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
858{
859 struct rtl8169_private *tp = netdev_priv(dev);
860 void __iomem *ioaddr = tp->mmio_addr;
861 u32 status;
862
863 cmd->supported =
864 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
865 cmd->port = PORT_FIBRE;
866 cmd->transceiver = XCVR_INTERNAL;
867
868 status = RTL_R32(TBICSR);
869 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
870 cmd->autoneg = !!(status & TBINwEnable);
871
872 cmd->speed = SPEED_1000;
873 cmd->duplex = DUPLEX_FULL; /* Always set */
874}
875
876static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
877{
878 struct rtl8169_private *tp = netdev_priv(dev);
879 void __iomem *ioaddr = tp->mmio_addr;
880 u8 status;
881
882 cmd->supported = SUPPORTED_10baseT_Half |
883 SUPPORTED_10baseT_Full |
884 SUPPORTED_100baseT_Half |
885 SUPPORTED_100baseT_Full |
886 SUPPORTED_1000baseT_Full |
887 SUPPORTED_Autoneg |
5b0384f4 888 SUPPORTED_TP;
1da177e4
LT		 889
890 cmd->autoneg = 1;
891 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
892
64e4bfb4 893 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 894 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 895 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 896 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 897 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 898 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 899 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 900 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 901 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 902 cmd->advertising |= ADVERTISED_1000baseT_Full;
903
904 status = RTL_R8(PHYstatus);
905
906 if (status & _1000bpsF)
907 cmd->speed = SPEED_1000;
908 else if (status & _100bps)
909 cmd->speed = SPEED_100;
910 else if (status & _10bps)
911 cmd->speed = SPEED_10;
912
623a1593
FR		 913 if (status & TxFlowCtrl)
914 cmd->advertising |= ADVERTISED_Asym_Pause;
915 if (status & RxFlowCtrl)
916 cmd->advertising |= ADVERTISED_Pause;
917
1da177e4
LT		 918 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
919 DUPLEX_FULL : DUPLEX_HALF;
920}
921
922static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
923{
924 struct rtl8169_private *tp = netdev_priv(dev);
925 unsigned long flags;
926
927 spin_lock_irqsave(&tp->lock, flags);
928
929 tp->get_settings(dev, cmd);
930
931 spin_unlock_irqrestore(&tp->lock, flags);
932 return 0;
933}
934
935static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
936 void *p)
937{
5b0384f4
FR		 938 struct rtl8169_private *tp = netdev_priv(dev);
939 unsigned long flags;
1da177e4 940
5b0384f4
FR		 941 if (regs->len > R8169_REGS_SIZE)
942 regs->len = R8169_REGS_SIZE;
1da177e4 943
5b0384f4
FR		 944 spin_lock_irqsave(&tp->lock, flags);
945 memcpy_fromio(p, tp->mmio_addr, regs->len);
946 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 947}
948
b57b7e5a
SH		 949static u32 rtl8169_get_msglevel(struct net_device *dev)
950{
951 struct rtl8169_private *tp = netdev_priv(dev);
952
953 return tp->msg_enable;
954}
955
956static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
957{
958 struct rtl8169_private *tp = netdev_priv(dev);
959
960 tp->msg_enable = value;
961}
962
d4a3a0fc
SH		 963static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
964 "tx_packets",
965 "rx_packets",
966 "tx_errors",
967 "rx_errors",
968 "rx_missed",
969 "align_errors",
970 "tx_single_collisions",
971 "tx_multi_collisions",
972 "unicast",
973 "broadcast",
974 "multicast",
975 "tx_aborted",
976 "tx_underrun",
977};
978
979struct rtl8169_counters {
980 u64 tx_packets;
981 u64 rx_packets;
982 u64 tx_errors;
983 u32 rx_errors;
984 u16 rx_missed;
985 u16 align_errors;
986 u32 tx_one_collision;
987 u32 tx_multi_collision;
988 u64 rx_unicast;
989 u64 rx_broadcast;
990 u32 rx_multicast;
991 u16 tx_aborted;
992 u16 tx_underun;
993};
994
b9f2c044 995static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 996{
b9f2c044
JG		 997 switch (sset) {
998 case ETH_SS_STATS:
999 return ARRAY_SIZE(rtl8169_gstrings);
1000 default:
1001 return -EOPNOTSUPP;
1002 }
d4a3a0fc
SH		 1003}
1004
1005static void rtl8169_get_ethtool_stats(struct net_device *dev,
1006 struct ethtool_stats *stats, u64 *data)
1007{
1008 struct rtl8169_private *tp = netdev_priv(dev);
1009 void __iomem *ioaddr = tp->mmio_addr;
1010 struct rtl8169_counters *counters;
1011 dma_addr_t paddr;
1012 u32 cmd;
1013
1014 ASSERT_RTNL();
1015
1016 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1017 if (!counters)
1018 return;
1019
1020 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1021 cmd = (u64)paddr & DMA_32BIT_MASK;
1022 RTL_W32(CounterAddrLow, cmd);
1023 RTL_W32(CounterAddrLow, cmd | CounterDump);
1024
1025 while (RTL_R32(CounterAddrLow) & CounterDump) {
1026 if (msleep_interruptible(1))
1027 break;
1028 }
1029
1030 RTL_W32(CounterAddrLow, 0);
1031 RTL_W32(CounterAddrHigh, 0);
1032
5b0384f4 1033 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1034 data[1] = le64_to_cpu(counters->rx_packets);
1035 data[2] = le64_to_cpu(counters->tx_errors);
1036 data[3] = le32_to_cpu(counters->rx_errors);
1037 data[4] = le16_to_cpu(counters->rx_missed);
1038 data[5] = le16_to_cpu(counters->align_errors);
1039 data[6] = le32_to_cpu(counters->tx_one_collision);
1040 data[7] = le32_to_cpu(counters->tx_multi_collision);
1041 data[8] = le64_to_cpu(counters->rx_unicast);
1042 data[9] = le64_to_cpu(counters->rx_broadcast);
1043 data[10] = le32_to_cpu(counters->rx_multicast);
1044 data[11] = le16_to_cpu(counters->tx_aborted);
1045 data[12] = le16_to_cpu(counters->tx_underun);
1046
1047 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1048}
1049
1050static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1051{
1052 switch(stringset) {
1053 case ETH_SS_STATS:
1054 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1055 break;
1056 }
1057}
1058
7282d491 1059static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1060 .get_drvinfo = rtl8169_get_drvinfo,
1061 .get_regs_len = rtl8169_get_regs_len,
1062 .get_link = ethtool_op_get_link,
1063 .get_settings = rtl8169_get_settings,
1064 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1065 .get_msglevel = rtl8169_get_msglevel,
1066 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1067 .get_rx_csum = rtl8169_get_rx_csum,
1068 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1069 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1070 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1071 .set_tso = ethtool_op_set_tso,
1072 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1073 .get_wol = rtl8169_get_wol,
1074 .set_wol = rtl8169_set_wol,
d4a3a0fc 1075 .get_strings = rtl8169_get_strings,
b9f2c044 1076 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1077 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1078};
1079
07d3f51f
FR		 1080static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1081 int bitnum, int bitval)
1da177e4
LT		 1082{
1083 int val;
1084
1085 val = mdio_read(ioaddr, reg);
1086 val = (bitval == 1) ?
1087 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1088 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1089}
1090
07d3f51f
FR		 1091static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1092 void __iomem *ioaddr)
1da177e4 1093{
0e485150
FR		 1094 /*
1095 * The driver currently handles the 8168Bf and the 8168Be identically
1096 * but they can be identified more specifically through the test below
1097 * if needed:
1098 *
1099 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1100 *
1101 * Same thing for the 8101Eb and the 8101Ec:
1102 *
1103 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1104 */
1da177e4
LT		 1105 const struct {
1106 u32 mask;
1107 int mac_version;
1108 } mac_info[] = {
bcf0bf90
FR		 1109 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1110 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1111 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1112 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1113 { 0x30000000, RTL_GIGA_MAC_VER_11 },
6dccd16b 1114 { 0x98000000, RTL_GIGA_MAC_VER_06 },
bcf0bf90
FR		 1115 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1116 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1117 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1118 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1119 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1120 }, *p = mac_info;
1121 u32 reg;
1122
6dccd16b 1123 reg = RTL_R32(TxConfig) & 0xfc800000;
1da177e4
LT		 1124 while ((reg & p->mask) != p->mask)
1125 p++;
1126 tp->mac_version = p->mac_version;
1127}
1128
1129static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1130{
bcf0bf90 1131 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1132}
1133
07d3f51f
FR		 1134static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1135 void __iomem *ioaddr)
1da177e4
LT		 1136{
1137 const struct {
1138 u16 mask;
1139 u16 set;
1140 int phy_version;
1141 } phy_info[] = {
1142 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1143 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1144 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1145 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1146 }, *p = phy_info;
1147 u16 reg;
1148
64e4bfb4 1149 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1da177e4
LT		 1150 while ((reg & p->mask) != p->set)
1151 p++;
1152 tp->phy_version = p->phy_version;
1153}
1154
1155static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1156{
1157 struct {
1158 int version;
1159 char *msg;
1160 u32 reg;
1161 } phy_print[] = {
1162 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1163 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1164 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1165 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1166 { 0, NULL, 0x0000 }
1167 }, *p;
1168
1169 for (p = phy_print; p->msg; p++) {
1170 if (tp->phy_version == p->version) {
1171 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1172 return;
1173 }
1174 }
1175 dprintk("phy_version == Unknown\n");
1176}
1177
1178static void rtl8169_hw_phy_config(struct net_device *dev)
1179{
1180 struct rtl8169_private *tp = netdev_priv(dev);
1181 void __iomem *ioaddr = tp->mmio_addr;
1182 struct {
1183 u16 regs[5]; /* Beware of bit-sign propagation */
1184 } phy_magic[5] = { {
1185 { 0x0000, //w 4 15 12 0
1186 0x00a1, //w 3 15 0 00a1
1187 0x0008, //w 2 15 0 0008
1188 0x1020, //w 1 15 0 1020
1189 0x1000 } },{ //w 0 15 0 1000
1190 { 0x7000, //w 4 15 12 7
1191 0xff41, //w 3 15 0 ff41
1192 0xde60, //w 2 15 0 de60
1193 0x0140, //w 1 15 0 0140
1194 0x0077 } },{ //w 0 15 0 0077
1195 { 0xa000, //w 4 15 12 a
1196 0xdf01, //w 3 15 0 df01
1197 0xdf20, //w 2 15 0 df20
1198 0xff95, //w 1 15 0 ff95
1199 0xfa00 } },{ //w 0 15 0 fa00
1200 { 0xb000, //w 4 15 12 b
1201 0xff41, //w 3 15 0 ff41
1202 0xde20, //w 2 15 0 de20
1203 0x0140, //w 1 15 0 0140
1204 0x00bb } },{ //w 0 15 0 00bb
1205 { 0xf000, //w 4 15 12 f
1206 0xdf01, //w 3 15 0 df01
1207 0xdf20, //w 2 15 0 df20
1208 0xff95, //w 1 15 0 ff95
1209 0xbf00 } //w 0 15 0 bf00
1210 }
1211 }, *p = phy_magic;
07d3f51f 1212 unsigned int i;
1da177e4
LT		 1213
1214 rtl8169_print_mac_version(tp);
1215 rtl8169_print_phy_version(tp);
1216
bcf0bf90 1217 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1218 return;
1219 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1220 return;
1221
1222 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1223 dprintk("Do final_reg2.cfg\n");
1224
1225 /* Shazam ! */
1226
bcf0bf90 1227 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1228 mdio_write(ioaddr, 31, 0x0002);
1229 mdio_write(ioaddr, 1, 0x90d0);
1230 mdio_write(ioaddr, 31, 0x0000);
1231 return;
1232 }
1233
65d916d9
EH		 1234 if ((tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1235 (tp->mac_version != RTL_GIGA_MAC_VER_03))
1236 return;
1237
1da177e4
LT		 1238 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1239 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1240 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1241 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1242
1243 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1244 int val, pos = 4;
1245
1246 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1247 mdio_write(ioaddr, pos, val);
1248 while (--pos >= 0)
1249 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1250 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1251 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1252 }
1253 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1254}
1255
1256static void rtl8169_phy_timer(unsigned long __opaque)
1257{
1258 struct net_device *dev = (struct net_device *)__opaque;
1259 struct rtl8169_private *tp = netdev_priv(dev);
1260 struct timer_list *timer = &tp->timer;
1261 void __iomem *ioaddr = tp->mmio_addr;
1262 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1263
bcf0bf90 1264 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1265 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1266
64e4bfb4 1267 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1268 return;
1269
1270 spin_lock_irq(&tp->lock);
1271
1272 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1273 /*
1da177e4
LT		 1274 * A busy loop could burn quite a few cycles on nowadays CPU.
1275 * Let's delay the execution of the timer for a few ticks.
1276 */
1277 timeout = HZ/10;
1278 goto out_mod_timer;
1279 }
1280
1281 if (tp->link_ok(ioaddr))
1282 goto out_unlock;
1283
b57b7e5a
SH		 1284 if (netif_msg_link(tp))
1285 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1286
1287 tp->phy_reset_enable(ioaddr);
1288
1289out_mod_timer:
1290 mod_timer(timer, jiffies + timeout);
1291out_unlock:
1292 spin_unlock_irq(&tp->lock);
1293}
1294
1295static inline void rtl8169_delete_timer(struct net_device *dev)
1296{
1297 struct rtl8169_private *tp = netdev_priv(dev);
1298 struct timer_list *timer = &tp->timer;
1299
bcf0bf90 1300 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1301 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1302 return;
1303
1304 del_timer_sync(timer);
1305}
1306
1307static inline void rtl8169_request_timer(struct net_device *dev)
1308{
1309 struct rtl8169_private *tp = netdev_priv(dev);
1310 struct timer_list *timer = &tp->timer;
1311
bcf0bf90 1312 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1313 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1314 return;
1315
2efa53f3 1316 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1317}
1318
1319#ifdef CONFIG_NET_POLL_CONTROLLER
1320/*
1321 * Polling 'interrupt' - used by things like netconsole to send skbs
1322 * without having to re-enable interrupts. It's not called while
1323 * the interrupt routine is executing.
1324 */
1325static void rtl8169_netpoll(struct net_device *dev)
1326{
1327 struct rtl8169_private *tp = netdev_priv(dev);
1328 struct pci_dev *pdev = tp->pci_dev;
1329
1330 disable_irq(pdev->irq);
7d12e780 1331 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1332 enable_irq(pdev->irq);
1333}
1334#endif
1335
1336static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1337 void __iomem *ioaddr)
1338{
1339 iounmap(ioaddr);
1340 pci_release_regions(pdev);
1341 pci_disable_device(pdev);
1342 free_netdev(dev);
1343}
1344
bf793295
FR		 1345static void rtl8169_phy_reset(struct net_device *dev,
1346 struct rtl8169_private *tp)
1347{
1348 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1349 unsigned int i;
bf793295
FR		 1350
1351 tp->phy_reset_enable(ioaddr);
1352 for (i = 0; i < 100; i++) {
1353 if (!tp->phy_reset_pending(ioaddr))
1354 return;
1355 msleep(1);
1356 }
1357 if (netif_msg_link(tp))
1358 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1359}
1360
4ff96fa6
FR		 1361static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1362{
1363 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6
FR		 1364
1365 rtl8169_hw_phy_config(dev);
1366
1367 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1368 RTL_W8(0x82, 0x01);
1369
6dccd16b
FR		 1370 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1371
1372 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1373 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1374
bcf0bf90 1375 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1376 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1377 RTL_W8(0x82, 0x01);
1378 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1379 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1380 }
1381
bf793295
FR		 1382 rtl8169_phy_reset(dev, tp);
1383
901dda2b
FR		 1384 /*
1385 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1386 * only 8101. Don't panic.
1387 */
1388 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1389
1390 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1391 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1392}
1393
773d2021
FR		 1394static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1395{
1396 void __iomem *ioaddr = tp->mmio_addr;
1397 u32 high;
1398 u32 low;
1399
1400 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1401 high = addr[4] | (addr[5] << 8);
1402
1403 spin_lock_irq(&tp->lock);
1404
1405 RTL_W8(Cfg9346, Cfg9346_Unlock);
1406 RTL_W32(MAC0, low);
1407 RTL_W32(MAC4, high);
1408 RTL_W8(Cfg9346, Cfg9346_Lock);
1409
1410 spin_unlock_irq(&tp->lock);
1411}
1412
1413static int rtl_set_mac_address(struct net_device *dev, void *p)
1414{
1415 struct rtl8169_private *tp = netdev_priv(dev);
1416 struct sockaddr *addr = p;
1417
1418 if (!is_valid_ether_addr(addr->sa_data))
1419 return -EADDRNOTAVAIL;
1420
1421 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1422
1423 rtl_rar_set(tp, dev->dev_addr);
1424
1425 return 0;
1426}
1427
5f787a1a
FR		 1428static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1429{
1430 struct rtl8169_private *tp = netdev_priv(dev);
1431 struct mii_ioctl_data *data = if_mii(ifr);
1432
1433 if (!netif_running(dev))
1434 return -ENODEV;
1435
1436 switch (cmd) {
1437 case SIOCGMIIPHY:
1438 data->phy_id = 32; /* Internal PHY */
1439 return 0;
1440
1441 case SIOCGMIIREG:
1442 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1443 return 0;
1444
1445 case SIOCSMIIREG:
1446 if (!capable(CAP_NET_ADMIN))
1447 return -EPERM;
1448 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1449 return 0;
1450 }
1451 return -EOPNOTSUPP;
1452}
1453
0e485150
FR		 1454static const struct rtl_cfg_info {
1455 void (*hw_start)(struct net_device *);
1456 unsigned int region;
1457 unsigned int align;
1458 u16 intr_event;
1459 u16 napi_event;
1460} rtl_cfg_infos [] = {
1461 [RTL_CFG_0] = {
1462 .hw_start = rtl_hw_start_8169,
1463 .region = 1,
e9f63f30 1464 .align = 0,
0e485150
FR		 1465 .intr_event = SYSErr | LinkChg | RxOverflow |
1466 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1467 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1468 },
1469 [RTL_CFG_1] = {
1470 .hw_start = rtl_hw_start_8168,
1471 .region = 2,
1472 .align = 8,
1473 .intr_event = SYSErr | LinkChg | RxOverflow |
1474 TxErr | TxOK | RxOK | RxErr,
1475 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1476 },
1477 [RTL_CFG_2] = {
1478 .hw_start = rtl_hw_start_8101,
1479 .region = 2,
1480 .align = 8,
1481 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1482 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1483 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1484 }
1485};
1486
1da177e4 1487static int __devinit
4ff96fa6 1488rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1489{
0e485150
FR		 1490 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1491 const unsigned int region = cfg->region;
1da177e4 1492 struct rtl8169_private *tp;
4ff96fa6
FR		 1493 struct net_device *dev;
1494 void __iomem *ioaddr;
07d3f51f
FR		 1495 unsigned int i;
1496 int rc;
1da177e4 1497
4ff96fa6
FR		 1498 if (netif_msg_drv(&debug)) {
1499 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1500 MODULENAME, RTL8169_VERSION);
1501 }
1da177e4 1502
1da177e4 1503 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1504 if (!dev) {
b57b7e5a 1505 if (netif_msg_drv(&debug))
9b91cf9d 1506 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1507 rc = -ENOMEM;
1508 goto out;
1da177e4
LT		 1509 }
1510
1da177e4
LT		 1511 SET_NETDEV_DEV(dev, &pdev->dev);
1512 tp = netdev_priv(dev);
c4028958 1513 tp->dev = dev;
b57b7e5a 1514 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1515
1516 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1517 rc = pci_enable_device(pdev);
b57b7e5a 1518 if (rc < 0) {
2e8a538d 1519 if (netif_msg_probe(tp))
9b91cf9d 1520 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1521 goto err_out_free_dev_1;
1da177e4
LT		 1522 }
1523
1524 rc = pci_set_mwi(pdev);
1525 if (rc < 0)
4ff96fa6 1526 goto err_out_disable_2;
1da177e4 1527
1da177e4 1528 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1529 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1530 if (netif_msg_probe(tp)) {
9b91cf9d 1531 dev_err(&pdev->dev,
bcf0bf90
FR		 1532 "region #%d not an MMIO resource, aborting\n",
1533 region);
4ff96fa6 1534 }
1da177e4 1535 rc = -ENODEV;
4ff96fa6 1536 goto err_out_mwi_3;
1da177e4 1537 }
4ff96fa6 1538
1da177e4 1539 /* check for weird/broken PCI region reporting */
bcf0bf90 1540 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1541 if (netif_msg_probe(tp)) {
9b91cf9d 1542 dev_err(&pdev->dev,
4ff96fa6
FR		 1543 "Invalid PCI region size(s), aborting\n");
1544 }
1da177e4 1545 rc = -ENODEV;
4ff96fa6 1546 goto err_out_mwi_3;
1da177e4
LT		 1547 }
1548
1549 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1550 if (rc < 0) {
2e8a538d 1551 if (netif_msg_probe(tp))
9b91cf9d 1552 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1553 goto err_out_mwi_3;
1da177e4
LT		 1554 }
1555
1556 tp->cp_cmd = PCIMulRW | RxChkSum;
1557
1558 if ((sizeof(dma_addr_t) > 4) &&
1559 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1560 tp->cp_cmd |= PCIDAC;
1561 dev->features |= NETIF_F_HIGHDMA;
1562 } else {
1563 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1564 if (rc < 0) {
4ff96fa6 1565 if (netif_msg_probe(tp)) {
9b91cf9d 1566 dev_err(&pdev->dev,
4ff96fa6
FR		 1567 "DMA configuration failed.\n");
1568 }
1569 goto err_out_free_res_4;
1da177e4
LT		 1570 }
1571 }
1572
1573 pci_set_master(pdev);
1574
1575 /* ioremap MMIO region */
bcf0bf90 1576 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1577 if (!ioaddr) {
b57b7e5a 1578 if (netif_msg_probe(tp))
9b91cf9d 1579 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1580 rc = -EIO;
4ff96fa6 1581 goto err_out_free_res_4;
1da177e4
LT		 1582 }
1583
1584 /* Unneeded ? Don't mess with Mrs. Murphy. */
1585 rtl8169_irq_mask_and_ack(ioaddr);
1586
1587 /* Soft reset the chip. */
1588 RTL_W8(ChipCmd, CmdReset);
1589
1590 /* Check that the chip has finished the reset. */
07d3f51f 1591 for (i = 0; i < 100; i++) {
1da177e4
LT		 1592 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1593 break;
b518fa8e 1594 msleep_interruptible(1);
1da177e4
LT		 1595 }
1596
1597 /* Identify chip attached to board */
1598 rtl8169_get_mac_version(tp, ioaddr);
1599 rtl8169_get_phy_version(tp, ioaddr);
1600
1601 rtl8169_print_mac_version(tp);
1602 rtl8169_print_phy_version(tp);
1603
1604 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1605 if (tp->mac_version == rtl_chip_info[i].mac_version)
1606 break;
1607 }
1608 if (i < 0) {
1609 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1610 if (netif_msg_probe(tp)) {
2e8a538d 1611 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1612 "unknown chip version, assuming %s\n",
1613 rtl_chip_info[0].name);
b57b7e5a 1614 }
1da177e4
LT		 1615 i++;
1616 }
1617 tp->chipset = i;
1618
5d06a99f
FR		 1619 RTL_W8(Cfg9346, Cfg9346_Unlock);
1620 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1621 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1622 RTL_W8(Cfg9346, Cfg9346_Lock);
1623
1da177e4
LT		 1624 if (RTL_R8(PHYstatus) & TBI_Enable) {
1625 tp->set_speed = rtl8169_set_speed_tbi;
1626 tp->get_settings = rtl8169_gset_tbi;
1627 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1628 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1629 tp->link_ok = rtl8169_tbi_link_ok;
1630
64e4bfb4 1631 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1632 } else {
1633 tp->set_speed = rtl8169_set_speed_xmii;
1634 tp->get_settings = rtl8169_gset_xmii;
1635 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1636 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1637 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1638
1639 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1640 }
1641
1642 /* Get MAC address. FIXME: read EEPROM */
1643 for (i = 0; i < MAC_ADDR_LEN; i++)
1644 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1645 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1646
1647 dev->open = rtl8169_open;
1648 dev->hard_start_xmit = rtl8169_start_xmit;
1649 dev->get_stats = rtl8169_get_stats;
1650 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1651 dev->stop = rtl8169_close;
1652 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1653 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1654 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1655 dev->irq = pdev->irq;
1656 dev->base_addr = (unsigned long) ioaddr;
1657 dev->change_mtu = rtl8169_change_mtu;
773d2021 1658 dev->set_mac_address = rtl_set_mac_address;
1da177e4
LT		 1659
1660#ifdef CONFIG_R8169_NAPI
bea3348e 1661 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 1662#endif
1663
1664#ifdef CONFIG_R8169_VLAN
1665 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1666 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1667#endif
1668
1669#ifdef CONFIG_NET_POLL_CONTROLLER
1670 dev->poll_controller = rtl8169_netpoll;
1671#endif
1672
1673 tp->intr_mask = 0xffff;
1674 tp->pci_dev = pdev;
1675 tp->mmio_addr = ioaddr;
0e485150
FR		 1676 tp->align = cfg->align;
1677 tp->hw_start = cfg->hw_start;
1678 tp->intr_event = cfg->intr_event;
1679 tp->napi_event = cfg->napi_event;
1da177e4 1680
2efa53f3
FR		 1681 init_timer(&tp->timer);
1682 tp->timer.data = (unsigned long) dev;
1683 tp->timer.function = rtl8169_phy_timer;
1684
1da177e4
LT		 1685 spin_lock_init(&tp->lock);
1686
1687 rc = register_netdev(dev);
4ff96fa6
FR		 1688 if (rc < 0)
1689 goto err_out_unmap_5;
1da177e4
LT		 1690
1691 pci_set_drvdata(pdev, dev);
1692
b57b7e5a 1693 if (netif_msg_probe(tp)) {
96b9709c
FR		 1694 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1695
b57b7e5a
SH		 1696 printk(KERN_INFO "%s: %s at 0x%lx, "
1697 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1698 "XID %08x IRQ %d\n",
b57b7e5a 1699 dev->name,
bcf0bf90 1700 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1701 dev->base_addr,
1702 dev->dev_addr[0], dev->dev_addr[1],
1703 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1704 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1705 }
1da177e4 1706
4ff96fa6 1707 rtl8169_init_phy(dev, tp);
1da177e4 1708
4ff96fa6
FR		 1709out:
1710 return rc;
1da177e4 1711
4ff96fa6
FR		 1712err_out_unmap_5:
1713 iounmap(ioaddr);
1714err_out_free_res_4:
1715 pci_release_regions(pdev);
1716err_out_mwi_3:
1717 pci_clear_mwi(pdev);
1718err_out_disable_2:
1719 pci_disable_device(pdev);
1720err_out_free_dev_1:
1721 free_netdev(dev);
1722 goto out;
1da177e4
LT		 1723}
1724
07d3f51f 1725static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1726{
1727 struct net_device *dev = pci_get_drvdata(pdev);
1728 struct rtl8169_private *tp = netdev_priv(dev);
1729
eb2a021c
FR		 1730 flush_scheduled_work();
1731
1da177e4
LT		 1732 unregister_netdev(dev);
1733 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1734 pci_set_drvdata(pdev, NULL);
1735}
1736
1da177e4
LT		 1737static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1738 struct net_device *dev)
1739{
1740 unsigned int mtu = dev->mtu;
1741
1742 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1743}
1744
1745static int rtl8169_open(struct net_device *dev)
1746{
1747 struct rtl8169_private *tp = netdev_priv(dev);
1748 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1749 int retval = -ENOMEM;
1da177e4 1750
1da177e4 1751
99f252b0 1752 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1753
1754 /*
1755 * Rx and Tx desscriptors needs 256 bytes alignment.
1756 * pci_alloc_consistent provides more.
1757 */
1758 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1759 &tp->TxPhyAddr);
1760 if (!tp->TxDescArray)
99f252b0 1761 goto out;
1da177e4
LT		 1762
1763 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1764 &tp->RxPhyAddr);
1765 if (!tp->RxDescArray)
99f252b0 1766 goto err_free_tx_0;
1da177e4
LT		 1767
1768 retval = rtl8169_init_ring(dev);
1769 if (retval < 0)
99f252b0 1770 goto err_free_rx_1;
1da177e4 1771
c4028958 1772 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1773
99f252b0
FR		 1774 smp_mb();
1775
1776 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1777 dev->name, dev);
1778 if (retval < 0)
1779 goto err_release_ring_2;
1780
bea3348e
SH		 1781#ifdef CONFIG_R8169_NAPI
1782 napi_enable(&tp->napi);
1783#endif
1784
07ce4064 1785 rtl_hw_start(dev);
1da177e4
LT		 1786
1787 rtl8169_request_timer(dev);
1788
1789 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1790out:
1791 return retval;
1792
99f252b0
FR		 1793err_release_ring_2:
1794 rtl8169_rx_clear(tp);
1795err_free_rx_1:
1da177e4
LT		 1796 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1797 tp->RxPhyAddr);
99f252b0 1798err_free_tx_0:
1da177e4
LT		 1799 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1800 tp->TxPhyAddr);
1da177e4
LT		 1801 goto out;
1802}
1803
1804static void rtl8169_hw_reset(void __iomem *ioaddr)
1805{
1806 /* Disable interrupts */
1807 rtl8169_irq_mask_and_ack(ioaddr);
1808
1809 /* Reset the chipset */
1810 RTL_W8(ChipCmd, CmdReset);
1811
1812 /* PCI commit */
1813 RTL_R8(ChipCmd);
1814}
1815
7f796d83 1816static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1817{
1818 void __iomem *ioaddr = tp->mmio_addr;
1819 u32 cfg = rtl8169_rx_config;
1820
1821 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1822 RTL_W32(RxConfig, cfg);
1823
1824 /* Set DMA burst size and Interframe Gap Time */
1825 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1826 (InterFrameGap << TxInterFrameGapShift));
1827}
1828
07ce4064 1829static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1830{
1831 struct rtl8169_private *tp = netdev_priv(dev);
1832 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1833 unsigned int i;
1da177e4
LT		 1834
1835 /* Soft reset the chip. */
1836 RTL_W8(ChipCmd, CmdReset);
1837
1838 /* Check that the chip has finished the reset. */
07d3f51f 1839 for (i = 0; i < 100; i++) {
1da177e4
LT		 1840 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1841 break;
b518fa8e 1842 msleep_interruptible(1);
1da177e4
LT		 1843 }
1844
07ce4064
FR		 1845 tp->hw_start(dev);
1846
07ce4064
FR		 1847 netif_start_queue(dev);
1848}
1849
1850
7f796d83
FR		 1851static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1852 void __iomem *ioaddr)
1853{
1854 /*
1855 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1856 * register to be written before TxDescAddrLow to work.
1857 * Switching from MMIO to I/O access fixes the issue as well.
1858 */
1859 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1860 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1861 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1862 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1863}
1864
1865static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1866{
1867 u16 cmd;
1868
1869 cmd = RTL_R16(CPlusCmd);
1870 RTL_W16(CPlusCmd, cmd);
1871 return cmd;
1872}
1873
1874static void rtl_set_rx_max_size(void __iomem *ioaddr)
1875{
1876 /* Low hurts. Let's disable the filtering. */
1877 RTL_W16(RxMaxSize, 16383);
1878}
1879
6dccd16b
FR		 1880static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1881{
1882 struct {
1883 u32 mac_version;
1884 u32 clk;
1885 u32 val;
1886 } cfg2_info [] = {
1887 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1888 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1889 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1890 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1891 }, *p = cfg2_info;
1892 unsigned int i;
1893 u32 clk;
1894
1895 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1896 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1897 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1898 RTL_W32(0x7c, p->val);
1899 break;
1900 }
1901 }
1902}
1903
07ce4064
FR		 1904static void rtl_hw_start_8169(struct net_device *dev)
1905{
1906 struct rtl8169_private *tp = netdev_priv(dev);
1907 void __iomem *ioaddr = tp->mmio_addr;
1908 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1909
9cb427b6
FR		 1910 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1911 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1912 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1913 }
1914
1da177e4 1915 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1916 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1917 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1918 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1919 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1920 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1921
1da177e4
LT		 1922 RTL_W8(EarlyTxThres, EarlyTxThld);
1923
7f796d83 1924 rtl_set_rx_max_size(ioaddr);
1da177e4 1925
c946b304
FR		 1926 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1927 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1928 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1929 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1930 rtl_set_rx_tx_config_registers(tp);
1da177e4 1931
7f796d83 1932 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 1933
bcf0bf90
FR		 1934 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1935 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1da177e4
LT		 1936 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1937 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1938 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1939 }
1940
bcf0bf90
FR		 1941 RTL_W16(CPlusCmd, tp->cp_cmd);
1942
6dccd16b
FR		 1943 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1944
1da177e4
LT		 1945 /*
1946 * Undocumented corner. Supposedly:
1947 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1948 */
1949 RTL_W16(IntrMitigate, 0x0000);
1950
7f796d83 1951 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 1952
c946b304
FR		 1953 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1954 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1955 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1956 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1957 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1958 rtl_set_rx_tx_config_registers(tp);
1959 }
1960
1da177e4 1961 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 1962
1963 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1964 RTL_R8(IntrMask);
1da177e4
LT		 1965
1966 RTL_W32(RxMissed, 0);
1967
07ce4064 1968 rtl_set_rx_mode(dev);
1da177e4
LT		 1969
1970 /* no early-rx interrupts */
1971 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 1972
1973 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 1974 RTL_W16(IntrMask, tp->intr_event);
07ce4064 1975}
1da177e4 1976
07ce4064
FR		 1977static void rtl_hw_start_8168(struct net_device *dev)
1978{
2dd99530
FR		 1979 struct rtl8169_private *tp = netdev_priv(dev);
1980 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1981 struct pci_dev *pdev = tp->pci_dev;
1982 u8 ctl;
2dd99530
FR		 1983
1984 RTL_W8(Cfg9346, Cfg9346_Unlock);
1985
1986 RTL_W8(EarlyTxThres, EarlyTxThld);
1987
1988 rtl_set_rx_max_size(ioaddr);
1989
0e485150
FR		 1990 rtl_set_rx_tx_config_registers(tp);
1991
1992 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 1993
1994 RTL_W16(CPlusCmd, tp->cp_cmd);
1995
0e485150
FR		 1996 /* Tx performance tweak. */
1997 pci_read_config_byte(pdev, 0x69, &ctl);
1998 ctl = (ctl & ~0x70) | 0x50;
1999 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 2000
0e485150 2001 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2002
0e485150
FR		 2003 /* Work around for RxFIFO overflow. */
2004 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2005 tp->intr_event |= RxFIFOOver | PCSTimeout;
2006 tp->intr_event &= ~RxOverflow;
2007 }
2008
2009 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2010
2011 RTL_W8(Cfg9346, Cfg9346_Lock);
2012
2013 RTL_R8(IntrMask);
2014
2015 RTL_W32(RxMissed, 0);
2016
2017 rtl_set_rx_mode(dev);
2018
0e485150
FR		 2019 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2020
2dd99530 2021 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2022
0e485150 2023 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2024}
1da177e4 2025
07ce4064
FR		 2026static void rtl_hw_start_8101(struct net_device *dev)
2027{
cdf1a608
FR		 2028 struct rtl8169_private *tp = netdev_priv(dev);
2029 void __iomem *ioaddr = tp->mmio_addr;
2030 struct pci_dev *pdev = tp->pci_dev;
2031
2032 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2033 pci_write_config_word(pdev, 0x68, 0x00);
2034 pci_write_config_word(pdev, 0x69, 0x08);
2035 }
2036
2037 RTL_W8(Cfg9346, Cfg9346_Unlock);
2038
2039 RTL_W8(EarlyTxThres, EarlyTxThld);
2040
2041 rtl_set_rx_max_size(ioaddr);
2042
2043 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2044
2045 RTL_W16(CPlusCmd, tp->cp_cmd);
2046
2047 RTL_W16(IntrMitigate, 0x0000);
2048
2049 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2050
2051 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2052 rtl_set_rx_tx_config_registers(tp);
2053
2054 RTL_W8(Cfg9346, Cfg9346_Lock);
2055
2056 RTL_R8(IntrMask);
2057
2058 RTL_W32(RxMissed, 0);
2059
2060 rtl_set_rx_mode(dev);
2061
0e485150
FR		 2062 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2063
cdf1a608 2064 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2065
0e485150 2066 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2067}
2068
2069static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2070{
2071 struct rtl8169_private *tp = netdev_priv(dev);
2072 int ret = 0;
2073
2074 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2075 return -EINVAL;
2076
2077 dev->mtu = new_mtu;
2078
2079 if (!netif_running(dev))
2080 goto out;
2081
2082 rtl8169_down(dev);
2083
2084 rtl8169_set_rxbufsize(tp, dev);
2085
2086 ret = rtl8169_init_ring(dev);
2087 if (ret < 0)
2088 goto out;
2089
bea3348e
SH		 2090#ifdef CONFIG_R8169_NAPI
2091 napi_enable(&tp->napi);
2092#endif
1da177e4 2093
07ce4064 2094 rtl_hw_start(dev);
1da177e4
LT		 2095
2096 rtl8169_request_timer(dev);
2097
2098out:
2099 return ret;
2100}
2101
2102static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2103{
2104 desc->addr = 0x0badbadbadbadbadull;
2105 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2106}
2107
2108static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2109 struct sk_buff **sk_buff, struct RxDesc *desc)
2110{
2111 struct pci_dev *pdev = tp->pci_dev;
2112
2113 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2114 PCI_DMA_FROMDEVICE);
2115 dev_kfree_skb(*sk_buff);
2116 *sk_buff = NULL;
2117 rtl8169_make_unusable_by_asic(desc);
2118}
2119
2120static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2121{
2122 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2123
2124 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2125}
2126
2127static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2128 u32 rx_buf_sz)
2129{
2130 desc->addr = cpu_to_le64(mapping);
2131 wmb();
2132 rtl8169_mark_to_asic(desc, rx_buf_sz);
2133}
2134
15d31758
SH		 2135static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2136 struct net_device *dev,
2137 struct RxDesc *desc, int rx_buf_sz,
2138 unsigned int align)
1da177e4
LT		 2139{
2140 struct sk_buff *skb;
2141 dma_addr_t mapping;
e9f63f30 2142 unsigned int pad;
1da177e4 2143
e9f63f30
FR		 2144 pad = align ? align : NET_IP_ALIGN;
2145
2146 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2147 if (!skb)
2148 goto err_out;
2149
e9f63f30 2150 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2151
689be439 2152 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2153 PCI_DMA_FROMDEVICE);
2154
2155 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2156out:
15d31758 2157 return skb;
1da177e4
LT		 2158
2159err_out:
1da177e4
LT		 2160 rtl8169_make_unusable_by_asic(desc);
2161 goto out;
2162}
2163
2164static void rtl8169_rx_clear(struct rtl8169_private *tp)
2165{
07d3f51f 2166 unsigned int i;
1da177e4
LT		 2167
2168 for (i = 0; i < NUM_RX_DESC; i++) {
2169 if (tp->Rx_skbuff[i]) {
2170 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2171 tp->RxDescArray + i);
2172 }
2173 }
2174}
2175
2176static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2177 u32 start, u32 end)
2178{
2179 u32 cur;
5b0384f4 2180
4ae47c2d 2181 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2182 struct sk_buff *skb;
2183 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2184
4ae47c2d
FR		 2185 WARN_ON((s32)(end - cur) < 0);
2186
1da177e4
LT		 2187 if (tp->Rx_skbuff[i])
2188 continue;
bcf0bf90 2189
15d31758
SH		 2190 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2191 tp->RxDescArray + i,
2192 tp->rx_buf_sz, tp->align);
2193 if (!skb)
1da177e4 2194 break;
15d31758
SH		 2195
2196 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2197 }
2198 return cur - start;
2199}
2200
2201static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2202{
2203 desc->opts1 |= cpu_to_le32(RingEnd);
2204}
2205
2206static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2207{
2208 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2209}
2210
2211static int rtl8169_init_ring(struct net_device *dev)
2212{
2213 struct rtl8169_private *tp = netdev_priv(dev);
2214
2215 rtl8169_init_ring_indexes(tp);
2216
2217 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2218 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2219
2220 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2221 goto err_out;
2222
2223 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2224
2225 return 0;
2226
2227err_out:
2228 rtl8169_rx_clear(tp);
2229 return -ENOMEM;
2230}
2231
2232static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2233 struct TxDesc *desc)
2234{
2235 unsigned int len = tx_skb->len;
2236
2237 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2238 desc->opts1 = 0x00;
2239 desc->opts2 = 0x00;
2240 desc->addr = 0x00;
2241 tx_skb->len = 0;
2242}
2243
2244static void rtl8169_tx_clear(struct rtl8169_private *tp)
2245{
2246 unsigned int i;
2247
2248 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2249 unsigned int entry = i % NUM_TX_DESC;
2250 struct ring_info *tx_skb = tp->tx_skb + entry;
2251 unsigned int len = tx_skb->len;
2252
2253 if (len) {
2254 struct sk_buff *skb = tx_skb->skb;
2255
2256 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2257 tp->TxDescArray + entry);
2258 if (skb) {
2259 dev_kfree_skb(skb);
2260 tx_skb->skb = NULL;
2261 }
2262 tp->stats.tx_dropped++;
2263 }
2264 }
2265 tp->cur_tx = tp->dirty_tx = 0;
2266}
2267
c4028958 2268static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2269{
2270 struct rtl8169_private *tp = netdev_priv(dev);
2271
c4028958 2272 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2273 schedule_delayed_work(&tp->task, 4);
2274}
2275
2276static void rtl8169_wait_for_quiescence(struct net_device *dev)
2277{
2278 struct rtl8169_private *tp = netdev_priv(dev);
2279 void __iomem *ioaddr = tp->mmio_addr;
2280
2281 synchronize_irq(dev->irq);
2282
2283 /* Wait for any pending NAPI task to complete */
bea3348e
SH		 2284#ifdef CONFIG_R8169_NAPI
2285 napi_disable(&tp->napi);
2286#endif
1da177e4
LT		 2287
2288 rtl8169_irq_mask_and_ack(ioaddr);
2289
bea3348e
SH		 2290#ifdef CONFIG_R8169_NAPI
2291 napi_enable(&tp->napi);
2292#endif
1da177e4
LT		 2293}
2294
c4028958 2295static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2296{
c4028958
DH		 2297 struct rtl8169_private *tp =
2298 container_of(work, struct rtl8169_private, task.work);
2299 struct net_device *dev = tp->dev;
1da177e4
LT		 2300 int ret;
2301
eb2a021c
FR		 2302 rtnl_lock();
2303
2304 if (!netif_running(dev))
2305 goto out_unlock;
2306
2307 rtl8169_wait_for_quiescence(dev);
2308 rtl8169_close(dev);
1da177e4
LT		 2309
2310 ret = rtl8169_open(dev);
2311 if (unlikely(ret < 0)) {
07d3f51f
FR		 2312 if (net_ratelimit() && netif_msg_drv(tp)) {
2313 printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2314 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2315 }
2316 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2317 }
eb2a021c
FR		 2318
2319out_unlock:
2320 rtnl_unlock();
1da177e4
LT		 2321}
2322
c4028958 2323static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2324{
c4028958
DH		 2325 struct rtl8169_private *tp =
2326 container_of(work, struct rtl8169_private, task.work);
2327 struct net_device *dev = tp->dev;
1da177e4 2328
eb2a021c
FR		 2329 rtnl_lock();
2330
1da177e4 2331 if (!netif_running(dev))
eb2a021c 2332 goto out_unlock;
1da177e4
LT		 2333
2334 rtl8169_wait_for_quiescence(dev);
2335
bea3348e 2336 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2337 rtl8169_tx_clear(tp);
2338
2339 if (tp->dirty_rx == tp->cur_rx) {
2340 rtl8169_init_ring_indexes(tp);
07ce4064 2341 rtl_hw_start(dev);
1da177e4
LT		 2342 netif_wake_queue(dev);
2343 } else {
07d3f51f
FR		 2344 if (net_ratelimit() && netif_msg_intr(tp)) {
2345 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2346 dev->name);
1da177e4
LT		 2347 }
2348 rtl8169_schedule_work(dev, rtl8169_reset_task);
2349 }
eb2a021c
FR		 2350
2351out_unlock:
2352 rtnl_unlock();
1da177e4
LT		 2353}
2354
2355static void rtl8169_tx_timeout(struct net_device *dev)
2356{
2357 struct rtl8169_private *tp = netdev_priv(dev);
2358
2359 rtl8169_hw_reset(tp->mmio_addr);
2360
2361 /* Let's wait a bit while any (async) irq lands on */
2362 rtl8169_schedule_work(dev, rtl8169_reset_task);
2363}
2364
2365static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2366 u32 opts1)
2367{
2368 struct skb_shared_info *info = skb_shinfo(skb);
2369 unsigned int cur_frag, entry;
a6343afb 2370 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2371
2372 entry = tp->cur_tx;
2373 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2374 skb_frag_t *frag = info->frags + cur_frag;
2375 dma_addr_t mapping;
2376 u32 status, len;
2377 void *addr;
2378
2379 entry = (entry + 1) % NUM_TX_DESC;
2380
2381 txd = tp->TxDescArray + entry;
2382 len = frag->size;
2383 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2384 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2385
2386 /* anti gcc 2.95.3 bugware (sic) */
2387 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2388
2389 txd->opts1 = cpu_to_le32(status);
2390 txd->addr = cpu_to_le64(mapping);
2391
2392 tp->tx_skb[entry].len = len;
2393 }
2394
2395 if (cur_frag) {
2396 tp->tx_skb[entry].skb = skb;
2397 txd->opts1 |= cpu_to_le32(LastFrag);
2398 }
2399
2400 return cur_frag;
2401}
2402
2403static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2404{
2405 if (dev->features & NETIF_F_TSO) {
7967168c 2406 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2407
2408 if (mss)
2409 return LargeSend | ((mss & MSSMask) << MSSShift);
2410 }
84fa7933 2411 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2412 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2413
2414 if (ip->protocol == IPPROTO_TCP)
2415 return IPCS | TCPCS;
2416 else if (ip->protocol == IPPROTO_UDP)
2417 return IPCS | UDPCS;
2418 WARN_ON(1); /* we need a WARN() */
2419 }
2420 return 0;
2421}
2422
2423static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2424{
2425 struct rtl8169_private *tp = netdev_priv(dev);
2426 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2427 struct TxDesc *txd = tp->TxDescArray + entry;
2428 void __iomem *ioaddr = tp->mmio_addr;
2429 dma_addr_t mapping;
2430 u32 status, len;
2431 u32 opts1;
188f4af0 2432 int ret = NETDEV_TX_OK;
5b0384f4 2433
1da177e4 2434 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2435 if (netif_msg_drv(tp)) {
2436 printk(KERN_ERR
2437 "%s: BUG! Tx Ring full when queue awake!\n",
2438 dev->name);
2439 }
1da177e4
LT		 2440 goto err_stop;
2441 }
2442
2443 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2444 goto err_stop;
2445
2446 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2447
2448 frags = rtl8169_xmit_frags(tp, skb, opts1);
2449 if (frags) {
2450 len = skb_headlen(skb);
2451 opts1 |= FirstFrag;
2452 } else {
2453 len = skb->len;
2454
2455 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2456 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2457 goto err_update_stats;
2458 len = ETH_ZLEN;
2459 }
2460
2461 opts1 |= FirstFrag | LastFrag;
2462 tp->tx_skb[entry].skb = skb;
2463 }
2464
2465 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2466
2467 tp->tx_skb[entry].len = len;
2468 txd->addr = cpu_to_le64(mapping);
2469 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2470
2471 wmb();
2472
2473 /* anti gcc 2.95.3 bugware (sic) */
2474 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2475 txd->opts1 = cpu_to_le32(status);
2476
2477 dev->trans_start = jiffies;
2478
2479 tp->cur_tx += frags + 1;
2480
2481 smp_wmb();
2482
275391a4 2483 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2484
2485 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2486 netif_stop_queue(dev);
2487 smp_rmb();
2488 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2489 netif_wake_queue(dev);
2490 }
2491
2492out:
2493 return ret;
2494
2495err_stop:
2496 netif_stop_queue(dev);
188f4af0 2497 ret = NETDEV_TX_BUSY;
1da177e4
LT		 2498err_update_stats:
2499 tp->stats.tx_dropped++;
2500 goto out;
2501}
2502
2503static void rtl8169_pcierr_interrupt(struct net_device *dev)
2504{
2505 struct rtl8169_private *tp = netdev_priv(dev);
2506 struct pci_dev *pdev = tp->pci_dev;
2507 void __iomem *ioaddr = tp->mmio_addr;
2508 u16 pci_status, pci_cmd;
2509
2510 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2511 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2512
b57b7e5a
SH		 2513 if (netif_msg_intr(tp)) {
2514 printk(KERN_ERR
2515 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2516 dev->name, pci_cmd, pci_status);
2517 }
1da177e4
LT		 2518
2519 /*
2520 * The recovery sequence below admits a very elaborated explanation:
2521 * - it seems to work;
d03902b8
FR		 2522 * - I did not see what else could be done;
2523 * - it makes iop3xx happy.
1da177e4
LT		 2524 *
2525 * Feel free to adjust to your needs.
2526 */
a27993f3 2527 if (pdev->broken_parity_status)
d03902b8
FR		 2528 pci_cmd &= ~PCI_COMMAND_PARITY;
2529 else
2530 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2531
2532 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2533
2534 pci_write_config_word(pdev, PCI_STATUS,
2535 pci_status & (PCI_STATUS_DETECTED_PARITY |
2536 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2537 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2538
2539 /* The infamous DAC f*ckup only happens at boot time */
2540 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2541 if (netif_msg_intr(tp))
2542 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2543 tp->cp_cmd &= ~PCIDAC;
2544 RTL_W16(CPlusCmd, tp->cp_cmd);
2545 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2546 }
2547
2548 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2549
2550 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2551}
2552
07d3f51f
FR		 2553static void rtl8169_tx_interrupt(struct net_device *dev,
2554 struct rtl8169_private *tp,
2555 void __iomem *ioaddr)
1da177e4
LT		 2556{
2557 unsigned int dirty_tx, tx_left;
2558
1da177e4
LT		 2559 dirty_tx = tp->dirty_tx;
2560 smp_rmb();
2561 tx_left = tp->cur_tx - dirty_tx;
2562
2563 while (tx_left > 0) {
2564 unsigned int entry = dirty_tx % NUM_TX_DESC;
2565 struct ring_info *tx_skb = tp->tx_skb + entry;
2566 u32 len = tx_skb->len;
2567 u32 status;
2568
2569 rmb();
2570 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2571 if (status & DescOwn)
2572 break;
2573
2574 tp->stats.tx_bytes += len;
2575 tp->stats.tx_packets++;
2576
2577 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2578
2579 if (status & LastFrag) {
2580 dev_kfree_skb_irq(tx_skb->skb);
2581 tx_skb->skb = NULL;
2582 }
2583 dirty_tx++;
2584 tx_left--;
2585 }
2586
2587 if (tp->dirty_tx != dirty_tx) {
2588 tp->dirty_tx = dirty_tx;
2589 smp_wmb();
2590 if (netif_queue_stopped(dev) &&
2591 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2592 netif_wake_queue(dev);
2593 }
d78ae2dc
FR		 2594 /*
2595 * 8168 hack: TxPoll requests are lost when the Tx packets are
2596 * too close. Let's kick an extra TxPoll request when a burst
2597 * of start_xmit activity is detected (if it is not detected,
2598 * it is slow enough). -- FR
2599 */
2600 smp_rmb();
2601 if (tp->cur_tx != dirty_tx)
2602 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 2603 }
2604}
2605
126fa4b9
FR		 2606static inline int rtl8169_fragmented_frame(u32 status)
2607{
2608 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2609}
2610
1da177e4
LT		 2611static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2612{
2613 u32 opts1 = le32_to_cpu(desc->opts1);
2614 u32 status = opts1 & RxProtoMask;
2615
2616 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2617 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2618 ((status == RxProtoIP) && !(opts1 & IPFail)))
2619 skb->ip_summed = CHECKSUM_UNNECESSARY;
2620 else
2621 skb->ip_summed = CHECKSUM_NONE;
2622}
2623
07d3f51f
FR		 2624static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2625 struct rtl8169_private *tp, int pkt_size,
2626 dma_addr_t addr)
1da177e4 2627{
b449655f
SH		 2628 struct sk_buff *skb;
2629 bool done = false;
1da177e4 2630
b449655f
SH		 2631 if (pkt_size >= rx_copybreak)
2632 goto out;
1da177e4 2633
07d3f51f 2634 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2635 if (!skb)
2636 goto out;
2637
07d3f51f
FR		 2638 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2639 PCI_DMA_FROMDEVICE);
86402234 2640 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2641 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2642 *sk_buff = skb;
2643 done = true;
2644out:
2645 return done;
1da177e4
LT		 2646}
2647
07d3f51f
FR		 2648static int rtl8169_rx_interrupt(struct net_device *dev,
2649 struct rtl8169_private *tp,
bea3348e 2650 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 2651{
2652 unsigned int cur_rx, rx_left;
2653 unsigned int delta, count;
2654
1da177e4
LT		 2655 cur_rx = tp->cur_rx;
2656 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
bea3348e 2657 rx_left = rtl8169_rx_quota(rx_left, budget);
1da177e4 2658
4dcb7d33 2659 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2660 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2661 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2662 u32 status;
2663
2664 rmb();
126fa4b9 2665 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2666
2667 if (status & DescOwn)
2668 break;
4dcb7d33 2669 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2670 if (netif_msg_rx_err(tp)) {
2671 printk(KERN_INFO
2672 "%s: Rx ERROR. status = %08x\n",
2673 dev->name, status);
2674 }
1da177e4
LT		 2675 tp->stats.rx_errors++;
2676 if (status & (RxRWT | RxRUNT))
2677 tp->stats.rx_length_errors++;
2678 if (status & RxCRC)
2679 tp->stats.rx_crc_errors++;
9dccf611
FR		 2680 if (status & RxFOVF) {
2681 rtl8169_schedule_work(dev, rtl8169_reset_task);
2682 tp->stats.rx_fifo_errors++;
2683 }
126fa4b9 2684 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2685 } else {
1da177e4 2686 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2687 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2688 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2689 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2690
126fa4b9
FR		 2691 /*
2692 * The driver does not support incoming fragmented
2693 * frames. They are seen as a symptom of over-mtu
2694 * sized frames.
2695 */
2696 if (unlikely(rtl8169_fragmented_frame(status))) {
2697 tp->stats.rx_dropped++;
2698 tp->stats.rx_length_errors++;
2699 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2700 continue;
126fa4b9
FR		 2701 }
2702
1da177e4 2703 rtl8169_rx_csum(skb, desc);
bcf0bf90 2704
07d3f51f 2705 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2706 pci_dma_sync_single_for_device(pdev, addr,
2707 pkt_size, PCI_DMA_FROMDEVICE);
2708 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2709 } else {
2710 pci_unmap_single(pdev, addr, pkt_size,
2711 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2712 tp->Rx_skbuff[entry] = NULL;
2713 }
2714
1da177e4
LT		 2715 skb_put(skb, pkt_size);
2716 skb->protocol = eth_type_trans(skb, dev);
2717
2718 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2719 rtl8169_rx_skb(skb);
2720
2721 dev->last_rx = jiffies;
2722 tp->stats.rx_bytes += pkt_size;
2723 tp->stats.rx_packets++;
2724 }
6dccd16b
FR		 2725
2726 /* Work around for AMD plateform. */
2727 if ((desc->opts2 & 0xfffe000) &&
2728 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2729 desc->opts2 = 0;
2730 cur_rx++;
2731 }
1da177e4
LT		 2732 }
2733
2734 count = cur_rx - tp->cur_rx;
2735 tp->cur_rx = cur_rx;
2736
2737 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2738 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2739 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2740 tp->dirty_rx += delta;
2741
2742 /*
2743 * FIXME: until there is periodic timer to try and refill the ring,
2744 * a temporary shortage may definitely kill the Rx process.
2745 * - disable the asic to try and avoid an overflow and kick it again
2746 * after refill ?
2747 * - how do others driver handle this condition (Uh oh...).
2748 */
b57b7e5a 2749 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2750 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2751
2752 return count;
2753}
2754
07d3f51f 2755static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2756{
07d3f51f 2757 struct net_device *dev = dev_instance;
1da177e4
LT		 2758 struct rtl8169_private *tp = netdev_priv(dev);
2759 int boguscnt = max_interrupt_work;
2760 void __iomem *ioaddr = tp->mmio_addr;
2761 int status;
2762 int handled = 0;
2763
2764 do {
2765 status = RTL_R16(IntrStatus);
2766
2767 /* hotplug/major error/no more work/shared irq */
2768 if ((status == 0xFFFF) || !status)
2769 break;
2770
2771 handled = 1;
2772
2773 if (unlikely(!netif_running(dev))) {
2774 rtl8169_asic_down(ioaddr);
2775 goto out;
2776 }
2777
2778 status &= tp->intr_mask;
2779 RTL_W16(IntrStatus,
2780 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2781
0e485150
FR		 2782 if (!(status & tp->intr_event))
2783 break;
2784
2785 /* Work around for rx fifo overflow */
2786 if (unlikely(status & RxFIFOOver) &&
2787 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2788 netif_stop_queue(dev);
2789 rtl8169_tx_timeout(dev);
1da177e4 2790 break;
0e485150 2791 }
1da177e4
LT		 2792
2793 if (unlikely(status & SYSErr)) {
2794 rtl8169_pcierr_interrupt(dev);
2795 break;
2796 }
2797
2798 if (status & LinkChg)
2799 rtl8169_check_link_status(dev, tp, ioaddr);
2800
2801#ifdef CONFIG_R8169_NAPI
313b0305
FR		 2802 if (status & tp->napi_event) {
2803 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2804 tp->intr_mask = ~tp->napi_event;
2805
bea3348e
SH		 2806 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2807 __netif_rx_schedule(dev, &tp->napi);
313b0305
FR		 2808 else if (netif_msg_intr(tp)) {
2809 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2810 dev->name, status);
2811 }
1da177e4
LT		 2812 }
2813 break;
2814#else
2815 /* Rx interrupt */
07d3f51f 2816 if (status & (RxOK | RxOverflow | RxFIFOOver))
bea3348e 2817 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
07d3f51f 2818
1da177e4
LT		 2819 /* Tx interrupt */
2820 if (status & (TxOK | TxErr))
2821 rtl8169_tx_interrupt(dev, tp, ioaddr);
2822#endif
2823
2824 boguscnt--;
2825 } while (boguscnt > 0);
2826
2827 if (boguscnt <= 0) {
7c8b2eb4 2828 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2829 printk(KERN_WARNING
2830 "%s: Too much work at interrupt!\n", dev->name);
2831 }
1da177e4
LT		 2832 /* Clear all interrupt sources. */
2833 RTL_W16(IntrStatus, 0xffff);
2834 }
2835out:
2836 return IRQ_RETVAL(handled);
2837}
2838
2839#ifdef CONFIG_R8169_NAPI
bea3348e 2840static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 2841{
bea3348e
SH		 2842 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2843 struct net_device *dev = tp->dev;
1da177e4 2844 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 2845 int work_done;
1da177e4 2846
bea3348e 2847 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 2848 rtl8169_tx_interrupt(dev, tp, ioaddr);
2849
bea3348e
SH		 2850 if (work_done < budget) {
2851 netif_rx_complete(dev, napi);
1da177e4
LT		 2852 tp->intr_mask = 0xffff;
2853 /*
2854 * 20040426: the barrier is not strictly required but the
2855 * behavior of the irq handler could be less predictable
2856 * without it. Btw, the lack of flush for the posted pci
2857 * write is safe - FR
2858 */
2859 smp_wmb();
0e485150 2860 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2861 }
2862
bea3348e 2863 return work_done;
1da177e4
LT		 2864}
2865#endif
2866
2867static void rtl8169_down(struct net_device *dev)
2868{
2869 struct rtl8169_private *tp = netdev_priv(dev);
2870 void __iomem *ioaddr = tp->mmio_addr;
2871 unsigned int poll_locked = 0;
733b736c 2872 unsigned int intrmask;
1da177e4
LT		 2873
2874 rtl8169_delete_timer(dev);
2875
2876 netif_stop_queue(dev);
2877
1da177e4
LT		 2878core_down:
2879 spin_lock_irq(&tp->lock);
2880
2881 rtl8169_asic_down(ioaddr);
2882
2883 /* Update the error counts. */
2884 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2885 RTL_W32(RxMissed, 0);
2886
2887 spin_unlock_irq(&tp->lock);
2888
2889 synchronize_irq(dev->irq);
2890
2891 if (!poll_locked) {
bea3348e 2892 napi_disable(&tp->napi);
1da177e4
LT		 2893 poll_locked++;
2894 }
2895
2896 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2897 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2898
2899 /*
2900 * And now for the 50k$ question: are IRQ disabled or not ?
2901 *
2902 * Two paths lead here:
2903 * 1) dev->close
2904 * -> netif_running() is available to sync the current code and the
2905 * IRQ handler. See rtl8169_interrupt for details.
2906 * 2) dev->change_mtu
2907 * -> rtl8169_poll can not be issued again and re-enable the
2908 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2909 *
2910 * No loop if hotpluged or major error (0xffff).
1da177e4 2911 */
733b736c
AP		 2912 intrmask = RTL_R16(IntrMask);
2913 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2914 goto core_down;
2915
2916 rtl8169_tx_clear(tp);
2917
2918 rtl8169_rx_clear(tp);
2919}
2920
2921static int rtl8169_close(struct net_device *dev)
2922{
2923 struct rtl8169_private *tp = netdev_priv(dev);
2924 struct pci_dev *pdev = tp->pci_dev;
2925
2926 rtl8169_down(dev);
2927
2928 free_irq(dev->irq, dev);
2929
1da177e4
LT		 2930 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2931 tp->RxPhyAddr);
2932 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2933 tp->TxPhyAddr);
2934 tp->TxDescArray = NULL;
2935 tp->RxDescArray = NULL;
2936
2937 return 0;
2938}
2939
07ce4064 2940static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 2941{
2942 struct rtl8169_private *tp = netdev_priv(dev);
2943 void __iomem *ioaddr = tp->mmio_addr;
2944 unsigned long flags;
2945 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 2946 int rx_mode;
1da177e4
LT		 2947 u32 tmp = 0;
2948
2949 if (dev->flags & IFF_PROMISC) {
2950 /* Unconditionally log net taps. */
b57b7e5a
SH		 2951 if (netif_msg_link(tp)) {
2952 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2953 dev->name);
2954 }
1da177e4
LT		 2955 rx_mode =
2956 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2957 AcceptAllPhys;
2958 mc_filter[1] = mc_filter[0] = 0xffffffff;
2959 } else if ((dev->mc_count > multicast_filter_limit)
2960 || (dev->flags & IFF_ALLMULTI)) {
2961 /* Too many to filter perfectly -- accept all multicasts. */
2962 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2963 mc_filter[1] = mc_filter[0] = 0xffffffff;
2964 } else {
2965 struct dev_mc_list *mclist;
07d3f51f
FR		 2966 unsigned int i;
2967
1da177e4
LT		 2968 rx_mode = AcceptBroadcast | AcceptMyPhys;
2969 mc_filter[1] = mc_filter[0] = 0;
2970 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2971 i++, mclist = mclist->next) {
2972 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2973 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2974 rx_mode |= AcceptMulticast;
2975 }
2976 }
2977
2978 spin_lock_irqsave(&tp->lock, flags);
2979
2980 tmp = rtl8169_rx_config | rx_mode |
2981 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2982
bcf0bf90
FR		 2983 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2984 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2985 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2986 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2987 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2988 mc_filter[0] = 0xffffffff;
2989 mc_filter[1] = 0xffffffff;
2990 }
2991
1da177e4
LT		 2992 RTL_W32(MAR0 + 0, mc_filter[0]);
2993 RTL_W32(MAR0 + 4, mc_filter[1]);
2994
57a9f236
FR		 2995 RTL_W32(RxConfig, tmp);
2996
1da177e4
LT		 2997 spin_unlock_irqrestore(&tp->lock, flags);
2998}
2999
3000/**
3001 * rtl8169_get_stats - Get rtl8169 read/write statistics
3002 * @dev: The Ethernet Device to get statistics for
3003 *
3004 * Get TX/RX statistics for rtl8169
3005 */
3006static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3007{
3008 struct rtl8169_private *tp = netdev_priv(dev);
3009 void __iomem *ioaddr = tp->mmio_addr;
3010 unsigned long flags;
3011
3012 if (netif_running(dev)) {
3013 spin_lock_irqsave(&tp->lock, flags);
3014 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3015 RTL_W32(RxMissed, 0);
3016 spin_unlock_irqrestore(&tp->lock, flags);
3017 }
5b0384f4 3018
1da177e4
LT		 3019 return &tp->stats;
3020}
3021
5d06a99f
FR		 3022#ifdef CONFIG_PM
3023
3024static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3025{
3026 struct net_device *dev = pci_get_drvdata(pdev);
3027 struct rtl8169_private *tp = netdev_priv(dev);
3028 void __iomem *ioaddr = tp->mmio_addr;
3029
3030 if (!netif_running(dev))
1371fa6d 3031 goto out_pci_suspend;
5d06a99f
FR		 3032
3033 netif_device_detach(dev);
3034 netif_stop_queue(dev);
3035
3036 spin_lock_irq(&tp->lock);
3037
3038 rtl8169_asic_down(ioaddr);
3039
3040 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3041 RTL_W32(RxMissed, 0);
3042
3043 spin_unlock_irq(&tp->lock);
3044
1371fa6d 3045out_pci_suspend:
5d06a99f 3046 pci_save_state(pdev);
61a4dcc2 3047 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f 3048 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3049
5d06a99f
FR		 3050 return 0;
3051}
3052
3053static int rtl8169_resume(struct pci_dev *pdev)
3054{
3055 struct net_device *dev = pci_get_drvdata(pdev);
3056
1371fa6d
FR		 3057 pci_set_power_state(pdev, PCI_D0);
3058 pci_restore_state(pdev);
3059 pci_enable_wake(pdev, PCI_D0, 0);
3060
5d06a99f
FR		 3061 if (!netif_running(dev))
3062 goto out;
3063
3064 netif_device_attach(dev);
3065
5d06a99f
FR		 3066 rtl8169_schedule_work(dev, rtl8169_reset_task);
3067out:
3068 return 0;
3069}
3070
3071#endif /* CONFIG_PM */
3072
1da177e4
LT		 3073static struct pci_driver rtl8169_pci_driver = {
3074 .name = MODULENAME,
3075 .id_table = rtl8169_pci_tbl,
3076 .probe = rtl8169_init_one,
3077 .remove = __devexit_p(rtl8169_remove_one),
3078#ifdef CONFIG_PM
3079 .suspend = rtl8169_suspend,
3080 .resume = rtl8169_resume,
3081#endif
3082};
3083
07d3f51f 3084static int __init rtl8169_init_module(void)
1da177e4 3085{
29917620 3086 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3087}
3088
07d3f51f 3089static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3090{
3091 pci_unregister_driver(&rtl8169_pci_driver);
3092}
3093
3094module_init(rtl8169_init_module);
3095module_exit(rtl8169_cleanup_module);
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