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r6040: fix scheduling while atomic in r6040_tx_timeout
[linux-2.6-block.git] / drivers / net / r6040.c
CommitLineData
7a47dd7a
SW		 1/*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
5ac5d616 6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7a47dd7a
SW		 7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23*/
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/version.h>
28#include <linux/moduleparam.h>
29#include <linux/string.h>
30#include <linux/timer.h>
31#include <linux/errno.h>
32#include <linux/ioport.h>
33#include <linux/slab.h>
34#include <linux/interrupt.h>
35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/skbuff.h>
39#include <linux/init.h>
40#include <linux/delay.h>
41#include <linux/mii.h>
42#include <linux/ethtool.h>
43#include <linux/crc32.h>
44#include <linux/spinlock.h>
092427be
JG		 45#include <linux/bitops.h>
46#include <linux/io.h>
47#include <linux/irq.h>
48#include <linux/uaccess.h>
7a47dd7a
SW		 49
50#include <asm/processor.h>
7a47dd7a
SW		 51
52#define DRV_NAME "r6040"
53#define DRV_VERSION "0.16"
54#define DRV_RELDATE "10Nov2007"
55
56/* PHY CHIP Address */
57#define PHY1_ADDR 1 /* For MAC1 */
58#define PHY2_ADDR 2 /* For MAC2 */
59#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
61
62/* Time in jiffies before concluding the transmitter is hung. */
5ac5d616 63#define TX_TIMEOUT (6000 * HZ / 1000)
7a47dd7a
SW		 64
65/* RDC MAC I/O Size */
66#define R6040_IO_SIZE 256
67
68/* MAX RDC MAC */
69#define MAX_MAC 2
70
71/* MAC registers */
72#define MCR0 0x00 /* Control register 0 */
73#define MCR1 0x04 /* Control register 1 */
74#define MAC_RST 0x0001 /* Reset the MAC */
75#define MBCR 0x08 /* Bus control */
76#define MT_ICR 0x0C /* TX interrupt control */
77#define MR_ICR 0x10 /* RX interrupt control */
78#define MTPR 0x14 /* TX poll command register */
79#define MR_BSR 0x18 /* RX buffer size */
80#define MR_DCR 0x1A /* RX descriptor control */
81#define MLSR 0x1C /* Last status */
82#define MMDIO 0x20 /* MDIO control register */
83#define MDIO_WRITE 0x4000 /* MDIO write */
84#define MDIO_READ 0x2000 /* MDIO read */
85#define MMRD 0x24 /* MDIO read data register */
86#define MMWD 0x28 /* MDIO write data register */
87#define MTD_SA0 0x2C /* TX descriptor start address 0 */
88#define MTD_SA1 0x30 /* TX descriptor start address 1 */
89#define MRD_SA0 0x34 /* RX descriptor start address 0 */
90#define MRD_SA1 0x38 /* RX descriptor start address 1 */
91#define MISR 0x3C /* Status register */
92#define MIER 0x40 /* INT enable register */
93#define MSK_INT 0x0000 /* Mask off interrupts */
3d254348
FF		 94#define RX_FINISH 0x0001 /* RX finished */
95#define RX_NO_DESC 0x0002 /* No RX descriptor available */
96#define RX_FIFO_FULL 0x0004 /* RX FIFO full */
97#define RX_EARLY 0x0008 /* RX early */
98#define TX_FINISH 0x0010 /* TX finished */
99#define TX_EARLY 0x0080 /* TX early */
100#define EVENT_OVRFL 0x0100 /* Event counter overflow */
101#define LINK_CHANGED 0x0200 /* PHY link changed */
7a47dd7a
SW		 102#define ME_CISR 0x44 /* Event counter INT status */
103#define ME_CIER 0x48 /* Event counter INT enable */
104#define MR_CNT 0x50 /* Successfully received packet counter */
105#define ME_CNT0 0x52 /* Event counter 0 */
106#define ME_CNT1 0x54 /* Event counter 1 */
107#define ME_CNT2 0x56 /* Event counter 2 */
108#define ME_CNT3 0x58 /* Event counter 3 */
109#define MT_CNT 0x5A /* Successfully transmit packet counter */
110#define ME_CNT4 0x5C /* Event counter 4 */
111#define MP_CNT 0x5E /* Pause frame counter register */
112#define MAR0 0x60 /* Hash table 0 */
113#define MAR1 0x62 /* Hash table 1 */
114#define MAR2 0x64 /* Hash table 2 */
115#define MAR3 0x66 /* Hash table 3 */
116#define MID_0L 0x68 /* Multicast address MID0 Low */
117#define MID_0M 0x6A /* Multicast address MID0 Medium */
118#define MID_0H 0x6C /* Multicast address MID0 High */
119#define MID_1L 0x70 /* MID1 Low */
120#define MID_1M 0x72 /* MID1 Medium */
121#define MID_1H 0x74 /* MID1 High */
122#define MID_2L 0x78 /* MID2 Low */
123#define MID_2M 0x7A /* MID2 Medium */
124#define MID_2H 0x7C /* MID2 High */
125#define MID_3L 0x80 /* MID3 Low */
126#define MID_3M 0x82 /* MID3 Medium */
127#define MID_3H 0x84 /* MID3 High */
128#define PHY_CC 0x88 /* PHY status change configuration register */
129#define PHY_ST 0x8A /* PHY status register */
130#define MAC_SM 0xAC /* MAC status machine */
131#define MAC_ID 0xBE /* Identifier register */
132
133#define TX_DCNT 0x80 /* TX descriptor count */
134#define RX_DCNT 0x80 /* RX descriptor count */
135#define MAX_BUF_SIZE 0x600
6c323103
FR		 136#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
137#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
7a47dd7a
SW		 138#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
139#define MCAST_MAX 4 /* Max number multicast addresses to filter */
140
141/* PHY settings */
142#define ICPLUS_PHY_ID 0x0243
143
144MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
145 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
146 "Florian Fainelli <florian@openwrt.org>");
147MODULE_LICENSE("GPL");
148MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
149
3d254348
FF		 150/* RX and TX interrupts that we handle */
151#define RX_INT (RX_FINISH)
152#define TX_INT (TX_FINISH)
153#define INT_MASK (RX_INT | TX_INT)
7a47dd7a
SW		 154
155struct r6040_descriptor {
156 u16 status, len; /* 0-3 */
157 __le32 buf; /* 4-7 */
158 __le32 ndesc; /* 8-B */
159 u32 rev1; /* C-F */
160 char *vbufp; /* 10-13 */
161 struct r6040_descriptor *vndescp; /* 14-17 */
162 struct sk_buff *skb_ptr; /* 18-1B */
163 u32 rev2; /* 1C-1F */
164} __attribute__((aligned(32)));
165
166struct r6040_private {
167 spinlock_t lock; /* driver lock */
168 struct timer_list timer;
169 struct pci_dev *pdev;
170 struct r6040_descriptor *rx_insert_ptr;
171 struct r6040_descriptor *rx_remove_ptr;
172 struct r6040_descriptor *tx_insert_ptr;
173 struct r6040_descriptor *tx_remove_ptr;
6c323103
FR		 174 struct r6040_descriptor *rx_ring;
175 struct r6040_descriptor *tx_ring;
176 dma_addr_t rx_ring_dma;
177 dma_addr_t tx_ring_dma;
7a47dd7a
SW		 178 u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
179 u16 mcr0, mcr1;
7a47dd7a
SW		 180 u16 switch_sig;
181 struct net_device *dev;
182 struct mii_if_info mii_if;
183 struct napi_struct napi;
7a47dd7a
SW		 184 void __iomem *base;
185};
186
187static char version[] __devinitdata = KERN_INFO DRV_NAME
188 ": RDC R6040 NAPI net driver,"
189 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
190
092427be 191static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
7a47dd7a
SW		 192
193/* Read a word data from PHY Chip */
c6e69bb9 194static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
7a47dd7a
SW		 195{
196 int limit = 2048;
197 u16 cmd;
198
199 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
200 /* Wait for the read bit to be cleared */
201 while (limit--) {
202 cmd = ioread16(ioaddr + MMDIO);
203 if (cmd & MDIO_READ)
204 break;
205 }
206
207 return ioread16(ioaddr + MMRD);
208}
209
210/* Write a word data from PHY Chip */
c6e69bb9 211static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
7a47dd7a
SW		 212{
213 int limit = 2048;
214 u16 cmd;
215
216 iowrite16(val, ioaddr + MMWD);
217 /* Write the command to the MDIO bus */
218 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
219 /* Wait for the write bit to be cleared */
220 while (limit--) {
221 cmd = ioread16(ioaddr + MMDIO);
222 if (cmd & MDIO_WRITE)
223 break;
224 }
225}
226
c6e69bb9 227static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg)
7a47dd7a
SW		 228{
229 struct r6040_private *lp = netdev_priv(dev);
230 void __iomem *ioaddr = lp->base;
231
c6e69bb9 232 return (r6040_phy_read(ioaddr, lp->phy_addr, reg));
7a47dd7a
SW		 233}
234
c6e69bb9 235static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val)
7a47dd7a
SW		 236{
237 struct r6040_private *lp = netdev_priv(dev);
238 void __iomem *ioaddr = lp->base;
239
c6e69bb9 240 r6040_phy_write(ioaddr, lp->phy_addr, reg, val);
7a47dd7a
SW		 241}
242
b4f1255d
FF		 243static void r6040_free_txbufs(struct net_device *dev)
244{
245 struct r6040_private *lp = netdev_priv(dev);
246 int i;
247
248 for (i = 0; i < TX_DCNT; i++) {
249 if (lp->tx_insert_ptr->skb_ptr) {
ed773b4a
AV		 250 pci_unmap_single(lp->pdev,
251 le32_to_cpu(lp->tx_insert_ptr->buf),
b4f1255d
FF		 252 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
253 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
254 lp->rx_insert_ptr->skb_ptr = NULL;
255 }
256 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
257 }
258}
259
260static void r6040_free_rxbufs(struct net_device *dev)
261{
262 struct r6040_private *lp = netdev_priv(dev);
263 int i;
264
265 for (i = 0; i < RX_DCNT; i++) {
266 if (lp->rx_insert_ptr->skb_ptr) {
ed773b4a
AV		 267 pci_unmap_single(lp->pdev,
268 le32_to_cpu(lp->rx_insert_ptr->buf),
b4f1255d
FF		 269 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
270 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
271 lp->rx_insert_ptr->skb_ptr = NULL;
272 }
273 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
274 }
275}
276
b4f1255d
FF		 277static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
278 dma_addr_t desc_dma, int size)
279{
280 struct r6040_descriptor *desc = desc_ring;
281 dma_addr_t mapping = desc_dma;
282
283 while (size-- > 0) {
3f6602ad 284 mapping += sizeof(*desc);
b4f1255d
FF		 285 desc->ndesc = cpu_to_le32(mapping);
286 desc->vndescp = desc + 1;
287 desc++;
288 }
289 desc--;
290 desc->ndesc = cpu_to_le32(desc_dma);
291 desc->vndescp = desc_ring;
292}
293
7a47dd7a 294/* Allocate skb buffer for rx descriptor */
c6e69bb9 295static void r6040_rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
7a47dd7a
SW		 296{
297 struct r6040_descriptor *descptr;
7a47dd7a
SW		 298
299 descptr = lp->rx_insert_ptr;
300 while (lp->rx_free_desc < RX_DCNT) {
ec6d2d45 301 descptr->skb_ptr = netdev_alloc_skb(dev, MAX_BUF_SIZE);
7a47dd7a
SW		 302
303 if (!descptr->skb_ptr)
304 break;
305 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
5125a786 306 descptr->skb_ptr->data,
7a47dd7a
SW		 307 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
308 descptr->status = 0x8000;
309 descptr = descptr->vndescp;
310 lp->rx_free_desc++;
7a47dd7a
SW		 311 }
312 lp->rx_insert_ptr = descptr;
313}
314
b4f1255d
FF		 315static void r6040_alloc_txbufs(struct net_device *dev)
316{
317 struct r6040_private *lp = netdev_priv(dev);
b4f1255d
FF		 318
319 lp->tx_free_desc = TX_DCNT;
320
321 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
322 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
b4f1255d
FF		 323}
324
325static void r6040_alloc_rxbufs(struct net_device *dev)
326{
327 struct r6040_private *lp = netdev_priv(dev);
b4f1255d
FF		 328
329 lp->rx_free_desc = 0;
330
331 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
332 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
333
c6e69bb9 334 r6040_rx_buf_alloc(lp, dev);
fec3a23b
FF		 335}
336
337static void r6040_init_mac_regs(struct net_device *dev)
338{
339 struct r6040_private *lp = netdev_priv(dev);
340 void __iomem *ioaddr = lp->base;
341 int limit = 2048;
342 u16 cmd;
343
344 /* Mask Off Interrupt */
345 iowrite16(MSK_INT, ioaddr + MIER);
346
347 /* Reset RDC MAC */
348 iowrite16(MAC_RST, ioaddr + MCR1);
349 while (limit--) {
350 cmd = ioread16(ioaddr + MCR1);
351 if (cmd & 0x1)
352 break;
353 }
354 /* Reset internal state machine */
355 iowrite16(2, ioaddr + MAC_SM);
356 iowrite16(0, ioaddr + MAC_SM);
357 udelay(5000);
358
359 /* MAC Bus Control Register */
360 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
361
362 /* Buffer Size Register */
363 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
364
365 /* Write TX ring start address */
366 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
367 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
b4f1255d 368
fec3a23b 369 /* Write RX ring start address */
b4f1255d
FF		 370 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
371 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
fec3a23b
FF		 372
373 /* Set interrupt waiting time and packet numbers */
374 iowrite16(0x0F06, ioaddr + MT_ICR);
375 iowrite16(0x0F06, ioaddr + MR_ICR);
376
377 /* Enable interrupts */
378 iowrite16(INT_MASK, ioaddr + MIER);
379
380 /* Enable TX and RX */
381 iowrite16(lp->mcr0 | 0x0002, ioaddr);
382
383 /* Let TX poll the descriptors
384 * we may got called by r6040_tx_timeout which has left
385 * some unsent tx buffers */
386 iowrite16(0x01, ioaddr + MTPR);
b4f1255d 387}
7a47dd7a 388
106adf3c
FF		 389static void r6040_tx_timeout(struct net_device *dev)
390{
391 struct r6040_private *priv = netdev_priv(dev);
392 void __iomem *ioaddr = priv->base;
393
fec3a23b
FF		 394 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
395 "status %4.4x, PHY status %4.4x\n",
106adf3c 396 dev->name, ioread16(ioaddr + MIER),
fec3a23b 397 ioread16(ioaddr + MISR),
c6e69bb9 398 r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
106adf3c 399
106adf3c 400 dev->stats.tx_errors++;
fec3a23b
FF		 401
402 /* Reset MAC and re-init all registers */
403 r6040_init_mac_regs(dev);
106adf3c
FF		 404}
405
7a47dd7a
SW		 406static struct net_device_stats *r6040_get_stats(struct net_device *dev)
407{
408 struct r6040_private *priv = netdev_priv(dev);
409 void __iomem *ioaddr = priv->base;
410 unsigned long flags;
411
412 spin_lock_irqsave(&priv->lock, flags);
d248fd77
FF		 413 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
414 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
7a47dd7a
SW		 415 spin_unlock_irqrestore(&priv->lock, flags);
416
d248fd77 417 return &dev->stats;
7a47dd7a
SW		 418}
419
420/* Stop RDC MAC and Free the allocated resource */
421static void r6040_down(struct net_device *dev)
422{
423 struct r6040_private *lp = netdev_priv(dev);
424 void __iomem *ioaddr = lp->base;
6c323103 425 struct pci_dev *pdev = lp->pdev;
7a47dd7a
SW		 426 int limit = 2048;
427 u16 *adrp;
428 u16 cmd;
429
430 /* Stop MAC */
431 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
432 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
433 while (limit--) {
434 cmd = ioread16(ioaddr + MCR1);
435 if (cmd & 0x1)
436 break;
437 }
438
439 /* Restore MAC Address to MIDx */
440 adrp = (u16 *) dev->dev_addr;
441 iowrite16(adrp[0], ioaddr + MID_0L);
442 iowrite16(adrp[1], ioaddr + MID_0M);
443 iowrite16(adrp[2], ioaddr + MID_0H);
444 free_irq(dev->irq, dev);
b4f1255d 445
7a47dd7a 446 /* Free RX buffer */
b4f1255d 447 r6040_free_rxbufs(dev);
7a47dd7a
SW		 448
449 /* Free TX buffer */
b4f1255d 450 r6040_free_txbufs(dev);
7a47dd7a
SW		 451
452 /* Free Descriptor memory */
6c323103
FR		 453 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
454 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
7a47dd7a
SW		 455}
456
5ac5d616 457static int r6040_close(struct net_device *dev)
7a47dd7a
SW		 458{
459 struct r6040_private *lp = netdev_priv(dev);
460
461 /* deleted timer */
462 del_timer_sync(&lp->timer);
463
464 spin_lock_irq(&lp->lock);
465 netif_stop_queue(dev);
466 r6040_down(dev);
467 spin_unlock_irq(&lp->lock);
468
469 return 0;
470}
471
472/* Status of PHY CHIP */
c6e69bb9 473static int r6040_phy_mode_chk(struct net_device *dev)
7a47dd7a
SW		 474{
475 struct r6040_private *lp = netdev_priv(dev);
476 void __iomem *ioaddr = lp->base;
477 int phy_dat;
478
479 /* PHY Link Status Check */
c6e69bb9 480 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
7a47dd7a
SW		 481 if (!(phy_dat & 0x4))
482 phy_dat = 0x8000; /* Link Failed, full duplex */
483
484 /* PHY Chip Auto-Negotiation Status */
c6e69bb9 485 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
7a47dd7a
SW		 486 if (phy_dat & 0x0020) {
487 /* Auto Negotiation Mode */
c6e69bb9
FF		 488 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5);
489 phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4);
7a47dd7a
SW		 490 if (phy_dat & 0x140)
491 /* Force full duplex */
492 phy_dat = 0x8000;
493 else
494 phy_dat = 0;
495 } else {
496 /* Force Mode */
c6e69bb9 497 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0);
7a47dd7a
SW		 498 if (phy_dat & 0x100)
499 phy_dat = 0x8000;
500 else
501 phy_dat = 0x0000;
502 }
503
504 return phy_dat;
505};
506
507static void r6040_set_carrier(struct mii_if_info *mii)
508{
c6e69bb9 509 if (r6040_phy_mode_chk(mii->dev)) {
7a47dd7a
SW		 510 /* autoneg is off: Link is always assumed to be up */
511 if (!netif_carrier_ok(mii->dev))
512 netif_carrier_on(mii->dev);
513 } else
c6e69bb9 514 r6040_phy_mode_chk(mii->dev);
7a47dd7a
SW		 515}
516
517static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
518{
519 struct r6040_private *lp = netdev_priv(dev);
5ac5d616 520 struct mii_ioctl_data *data = if_mii(rq);
7a47dd7a
SW		 521 int rc;
522
523 if (!netif_running(dev))
524 return -EINVAL;
525 spin_lock_irq(&lp->lock);
526 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
527 spin_unlock_irq(&lp->lock);
528 r6040_set_carrier(&lp->mii_if);
529 return rc;
530}
531
532static int r6040_rx(struct net_device *dev, int limit)
533{
534 struct r6040_private *priv = netdev_priv(dev);
535 int count;
536 void __iomem *ioaddr = priv->base;
537 u16 err;
538
539 for (count = 0; count < limit; ++count) {
540 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
541 struct sk_buff *skb_ptr;
542
7a47dd7a
SW		 543 descptr = priv->rx_remove_ptr;
544
545 /* Check for errors */
546 err = ioread16(ioaddr + MLSR);
d248fd77
FF		 547 if (err & 0x0400)
548 dev->stats.rx_errors++;
7a47dd7a 549 /* RX FIFO over-run */
d248fd77
FF		 550 if (err & 0x8000)
551 dev->stats.rx_fifo_errors++;
7a47dd7a 552 /* RX descriptor unavailable */
d248fd77
FF		 553 if (err & 0x0080)
554 dev->stats.rx_frame_errors++;
7a47dd7a 555 /* Received packet with length over buffer lenght */
d248fd77
FF		 556 if (err & 0x0020)
557 dev->stats.rx_over_errors++;
7a47dd7a 558 /* Received packet with too long or short */
d248fd77
FF		 559 if (err & (0x0010 | 0x0008))
560 dev->stats.rx_length_errors++;
7a47dd7a
SW		 561 /* Received packet with CRC errors */
562 if (err & 0x0004) {
563 spin_lock(&priv->lock);
d248fd77 564 dev->stats.rx_crc_errors++;
7a47dd7a
SW		 565 spin_unlock(&priv->lock);
566 }
567
568 while (priv->rx_free_desc) {
569 /* No RX packet */
570 if (descptr->status & 0x8000)
571 break;
572 skb_ptr = descptr->skb_ptr;
573 if (!skb_ptr) {
574 printk(KERN_ERR "%s: Inconsistent RX"
575 "descriptor chain\n",
576 dev->name);
577 break;
578 }
579 descptr->skb_ptr = NULL;
580 skb_ptr->dev = priv->dev;
581 /* Do not count the CRC */
582 skb_put(skb_ptr, descptr->len - 4);
ed773b4a 583 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
7a47dd7a
SW		 584 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
585 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
586 /* Send to upper layer */
587 netif_receive_skb(skb_ptr);
588 dev->last_rx = jiffies;
d248fd77
FF		 589 dev->stats.rx_packets++;
590 dev->stats.rx_bytes += descptr->len;
7a47dd7a
SW		 591 /* To next descriptor */
592 descptr = descptr->vndescp;
593 priv->rx_free_desc--;
594 }
595 priv->rx_remove_ptr = descptr;
596 }
597 /* Allocate new RX buffer */
598 if (priv->rx_free_desc < RX_DCNT)
c6e69bb9 599 r6040_rx_buf_alloc(priv, priv->dev);
7a47dd7a
SW		 600
601 return count;
602}
603
604static void r6040_tx(struct net_device *dev)
605{
606 struct r6040_private *priv = netdev_priv(dev);
607 struct r6040_descriptor *descptr;
608 void __iomem *ioaddr = priv->base;
609 struct sk_buff *skb_ptr;
610 u16 err;
611
612 spin_lock(&priv->lock);
613 descptr = priv->tx_remove_ptr;
614 while (priv->tx_free_desc < TX_DCNT) {
615 /* Check for errors */
616 err = ioread16(ioaddr + MLSR);
617
d248fd77
FF		 618 if (err & 0x0200)
619 dev->stats.rx_fifo_errors++;
620 if (err & (0x2000 | 0x4000))
621 dev->stats.tx_carrier_errors++;
7a47dd7a
SW		 622
623 if (descptr->status & 0x8000)
ec6d2d45 624 break; /* Not complete */
7a47dd7a 625 skb_ptr = descptr->skb_ptr;
ed773b4a 626 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
7a47dd7a
SW		 627 skb_ptr->len, PCI_DMA_TODEVICE);
628 /* Free buffer */
629 dev_kfree_skb_irq(skb_ptr);
630 descptr->skb_ptr = NULL;
631 /* To next descriptor */
632 descptr = descptr->vndescp;
633 priv->tx_free_desc++;
634 }
635 priv->tx_remove_ptr = descptr;
636
637 if (priv->tx_free_desc)
638 netif_wake_queue(dev);
639 spin_unlock(&priv->lock);
640}
641
642static int r6040_poll(struct napi_struct *napi, int budget)
643{
644 struct r6040_private *priv =
645 container_of(napi, struct r6040_private, napi);
646 struct net_device *dev = priv->dev;
647 void __iomem *ioaddr = priv->base;
648 int work_done;
649
650 work_done = r6040_rx(dev, budget);
651
652 if (work_done < budget) {
653 netif_rx_complete(dev, napi);
654 /* Enable RX interrupt */
655 iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
656 }
657 return work_done;
658}
659
660/* The RDC interrupt handler. */
661static irqreturn_t r6040_interrupt(int irq, void *dev_id)
662{
663 struct net_device *dev = dev_id;
664 struct r6040_private *lp = netdev_priv(dev);
665 void __iomem *ioaddr = lp->base;
666 u16 status;
7a47dd7a
SW		 667
668 /* Mask off RDC MAC interrupt */
669 iowrite16(MSK_INT, ioaddr + MIER);
670 /* Read MISR status and clear */
671 status = ioread16(ioaddr + MISR);
672
673 if (status == 0x0000 || status == 0xffff)
674 return IRQ_NONE;
675
676 /* RX interrupt request */
677 if (status & 0x01) {
3d254348
FF		 678 /* Mask off RX interrupt */
679 iowrite16(ioread16(ioaddr + MIER) & ~RX_INT, ioaddr + MIER);
7a47dd7a 680 netif_rx_schedule(dev, &lp->napi);
7a47dd7a
SW		 681 }
682
683 /* TX interrupt request */
684 if (status & 0x10)
685 r6040_tx(dev);
686
ec6d2d45 687 return IRQ_HANDLED;
7a47dd7a
SW		 688}
689
690#ifdef CONFIG_NET_POLL_CONTROLLER
691static void r6040_poll_controller(struct net_device *dev)
692{
693 disable_irq(dev->irq);
5ac5d616 694 r6040_interrupt(dev->irq, dev);
7a47dd7a
SW		 695 enable_irq(dev->irq);
696}
697#endif
698
7a47dd7a
SW		 699/* Init RDC MAC */
700static void r6040_up(struct net_device *dev)
701{
702 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a 703 void __iomem *ioaddr = lp->base;
7a47dd7a 704
b4f1255d
FF		 705 /* Initialise and alloc RX/TX buffers */
706 r6040_alloc_txbufs(dev);
707 r6040_alloc_rxbufs(dev);
7a47dd7a 708
7a47dd7a 709 /* Read the PHY ID */
c6e69bb9 710 lp->switch_sig = r6040_phy_read(ioaddr, 0, 2);
7a47dd7a
SW		 711
712 if (lp->switch_sig == ICPLUS_PHY_ID) {
c6e69bb9 713 r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
7a47dd7a
SW		 714 lp->phy_mode = 0x8000;
715 } else {
716 /* PHY Mode Check */
c6e69bb9
FF		 717 r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
718 r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
7a47dd7a
SW		 719
720 if (PHY_MODE == 0x3100)
c6e69bb9 721 lp->phy_mode = r6040_phy_mode_chk(dev);
7a47dd7a
SW		 722 else
723 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
724 }
7a47dd7a 725
fec3a23b 726 /* Set duplex mode */
7a47dd7a 727 lp->mcr0 |= lp->phy_mode;
7a47dd7a
SW		 728
729 /* improve performance (by RDC guys) */
c6e69bb9
FF		 730 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
731 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
732 r6040_phy_write(ioaddr, 0, 19, 0x0000);
733 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
7a47dd7a 734
fec3a23b
FF		 735 /* Initialize all MAC registers */
736 r6040_init_mac_regs(dev);
7a47dd7a
SW		 737}
738
739/*
740 A periodic timer routine
741 Polling PHY Chip Link Status
742*/
743static void r6040_timer(unsigned long data)
744{
745 struct net_device *dev = (struct net_device *)data;
e6a9ea10 746 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 747 void __iomem *ioaddr = lp->base;
748 u16 phy_mode;
749
750 /* Polling PHY Chip Status */
751 if (PHY_MODE == 0x3100)
c6e69bb9 752 phy_mode = r6040_phy_mode_chk(dev);
7a47dd7a
SW		 753 else
754 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
755
756 if (phy_mode != lp->phy_mode) {
757 lp->phy_mode = phy_mode;
758 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
759 iowrite16(lp->mcr0, ioaddr);
760 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
761 }
762
763 /* Timer active again */
208aefa2 764 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
7a47dd7a
SW		 765}
766
767/* Read/set MAC address routines */
768static void r6040_mac_address(struct net_device *dev)
769{
770 struct r6040_private *lp = netdev_priv(dev);
771 void __iomem *ioaddr = lp->base;
772 u16 *adrp;
773
774 /* MAC operation register */
775 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
776 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
777 iowrite16(0, ioaddr + MAC_SM);
778 udelay(5000);
779
780 /* Restore MAC Address */
781 adrp = (u16 *) dev->dev_addr;
782 iowrite16(adrp[0], ioaddr + MID_0L);
783 iowrite16(adrp[1], ioaddr + MID_0M);
784 iowrite16(adrp[2], ioaddr + MID_0H);
785}
786
5ac5d616 787static int r6040_open(struct net_device *dev)
7a47dd7a 788{
5ac5d616 789 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 790 int ret;
791
792 /* Request IRQ and Register interrupt handler */
793 ret = request_irq(dev->irq, &r6040_interrupt,
794 IRQF_SHARED, dev->name, dev);
795 if (ret)
796 return ret;
797
798 /* Set MAC address */
799 r6040_mac_address(dev);
800
801 /* Allocate Descriptor memory */
6c323103
FR		 802 lp->rx_ring =
803 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
804 if (!lp->rx_ring)
7a47dd7a
SW		 805 return -ENOMEM;
806
6c323103
FR		 807 lp->tx_ring =
808 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
809 if (!lp->tx_ring) {
810 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
811 lp->rx_ring_dma);
812 return -ENOMEM;
813 }
814
7a47dd7a
SW		 815 r6040_up(dev);
816
817 napi_enable(&lp->napi);
818 netif_start_queue(dev);
819
106adf3c
FF		 820 /* set and active a timer process */
821 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
822 if (lp->switch_sig != ICPLUS_PHY_ID)
823 mod_timer(&lp->timer, jiffies + HZ);
7a47dd7a
SW		 824 return 0;
825}
826
5ac5d616 827static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
7a47dd7a
SW		 828{
829 struct r6040_private *lp = netdev_priv(dev);
830 struct r6040_descriptor *descptr;
831 void __iomem *ioaddr = lp->base;
832 unsigned long flags;
092427be 833 int ret = NETDEV_TX_OK;
7a47dd7a
SW		 834
835 /* Critical Section */
836 spin_lock_irqsave(&lp->lock, flags);
837
838 /* TX resource check */
839 if (!lp->tx_free_desc) {
840 spin_unlock_irqrestore(&lp->lock, flags);
092427be 841 netif_stop_queue(dev);
7a47dd7a 842 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
092427be 843 ret = NETDEV_TX_BUSY;
7a47dd7a
SW		 844 return ret;
845 }
846
847 /* Statistic Counter */
848 dev->stats.tx_packets++;
849 dev->stats.tx_bytes += skb->len;
850 /* Set TX descriptor & Transmit it */
851 lp->tx_free_desc--;
852 descptr = lp->tx_insert_ptr;
853 if (skb->len < MISR)
854 descptr->len = MISR;
855 else
856 descptr->len = skb->len;
857
858 descptr->skb_ptr = skb;
859 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
860 skb->data, skb->len, PCI_DMA_TODEVICE));
861 descptr->status = 0x8000;
862 /* Trigger the MAC to check the TX descriptor */
863 iowrite16(0x01, ioaddr + MTPR);
864 lp->tx_insert_ptr = descptr->vndescp;
865
866 /* If no tx resource, stop */
867 if (!lp->tx_free_desc)
868 netif_stop_queue(dev);
869
870 dev->trans_start = jiffies;
871 spin_unlock_irqrestore(&lp->lock, flags);
872 return ret;
873}
874
5ac5d616 875static void r6040_multicast_list(struct net_device *dev)
7a47dd7a
SW		 876{
877 struct r6040_private *lp = netdev_priv(dev);
878 void __iomem *ioaddr = lp->base;
879 u16 *adrp;
880 u16 reg;
881 unsigned long flags;
882 struct dev_mc_list *dmi = dev->mc_list;
883 int i;
884
885 /* MAC Address */
886 adrp = (u16 *)dev->dev_addr;
887 iowrite16(adrp[0], ioaddr + MID_0L);
888 iowrite16(adrp[1], ioaddr + MID_0M);
889 iowrite16(adrp[2], ioaddr + MID_0H);
890
891 /* Promiscous Mode */
892 spin_lock_irqsave(&lp->lock, flags);
893
894 /* Clear AMCP & PROM bits */
895 reg = ioread16(ioaddr) & ~0x0120;
896 if (dev->flags & IFF_PROMISC) {
897 reg |= 0x0020;
898 lp->mcr0 |= 0x0020;
899 }
900 /* Too many multicast addresses
901 * accept all traffic */
902 else if ((dev->mc_count > MCAST_MAX)
903 || (dev->flags & IFF_ALLMULTI))
904 reg |= 0x0020;
905
906 iowrite16(reg, ioaddr);
907 spin_unlock_irqrestore(&lp->lock, flags);
908
909 /* Build the hash table */
910 if (dev->mc_count > MCAST_MAX) {
911 u16 hash_table[4];
912 u32 crc;
913
914 for (i = 0; i < 4; i++)
915 hash_table[i] = 0;
916
917 for (i = 0; i < dev->mc_count; i++) {
918 char *addrs = dmi->dmi_addr;
919
920 dmi = dmi->next;
921
922 if (!(*addrs & 1))
923 continue;
924
925 crc = ether_crc_le(6, addrs);
926 crc >>= 26;
927 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
928 }
929 /* Write the index of the hash table */
930 for (i = 0; i < 4; i++)
931 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
932 /* Fill the MAC hash tables with their values */
933 iowrite16(hash_table[0], ioaddr + MAR0);
934 iowrite16(hash_table[1], ioaddr + MAR1);
935 iowrite16(hash_table[2], ioaddr + MAR2);
936 iowrite16(hash_table[3], ioaddr + MAR3);
937 }
938 /* Multicast Address 1~4 case */
939 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
940 adrp = (u16 *)dmi->dmi_addr;
941 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
942 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
943 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
944 dmi = dmi->next;
945 }
946 for (i = dev->mc_count; i < MCAST_MAX; i++) {
947 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
948 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
949 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
950 }
951}
952
953static void netdev_get_drvinfo(struct net_device *dev,
954 struct ethtool_drvinfo *info)
955{
956 struct r6040_private *rp = netdev_priv(dev);
957
958 strcpy(info->driver, DRV_NAME);
959 strcpy(info->version, DRV_VERSION);
960 strcpy(info->bus_info, pci_name(rp->pdev));
961}
962
963static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
964{
965 struct r6040_private *rp = netdev_priv(dev);
966 int rc;
967
968 spin_lock_irq(&rp->lock);
969 rc = mii_ethtool_gset(&rp->mii_if, cmd);
092427be 970 spin_unlock_irq(&rp->lock);
7a47dd7a
SW		 971
972 return rc;
973}
974
975static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
976{
977 struct r6040_private *rp = netdev_priv(dev);
978 int rc;
979
980 spin_lock_irq(&rp->lock);
981 rc = mii_ethtool_sset(&rp->mii_if, cmd);
982 spin_unlock_irq(&rp->lock);
983 r6040_set_carrier(&rp->mii_if);
984
985 return rc;
986}
987
988static u32 netdev_get_link(struct net_device *dev)
989{
990 struct r6040_private *rp = netdev_priv(dev);
991
992 return mii_link_ok(&rp->mii_if);
993}
994
995static struct ethtool_ops netdev_ethtool_ops = {
996 .get_drvinfo = netdev_get_drvinfo,
997 .get_settings = netdev_get_settings,
998 .set_settings = netdev_set_settings,
999 .get_link = netdev_get_link,
1000};
1001
7a47dd7a
SW		 1002static int __devinit r6040_init_one(struct pci_dev *pdev,
1003 const struct pci_device_id *ent)
1004{
1005 struct net_device *dev;
1006 struct r6040_private *lp;
1007 void __iomem *ioaddr;
1008 int err, io_size = R6040_IO_SIZE;
1009 static int card_idx = -1;
1010 int bar = 0;
1011 long pioaddr;
1012 u16 *adrp;
1013
1014 printk(KERN_INFO "%s\n", version);
1015
1016 err = pci_enable_device(pdev);
1017 if (err)
1018 return err;
1019
1020 /* this should always be supported */
1021 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1022 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1023 "not supported by the card\n");
1024 return -ENODEV;
1025 }
092427be
JG		 1026 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1027 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1028 "not supported by the card\n");
1029 return -ENODEV;
1030 }
7a47dd7a
SW		 1031
1032 /* IO Size check */
1033 if (pci_resource_len(pdev, 0) < io_size) {
1034 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
1035 return -EIO;
1036 }
1037
1038 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1039 pci_set_master(pdev);
1040
1041 dev = alloc_etherdev(sizeof(struct r6040_private));
1042 if (!dev) {
1043 printk(KERN_ERR "Failed to allocate etherdev\n");
1044 return -ENOMEM;
1045 }
1046 SET_NETDEV_DEV(dev, &pdev->dev);
1047 lp = netdev_priv(dev);
1048 lp->pdev = pdev;
3d254348 1049 lp->dev = dev;
7a47dd7a
SW		 1050
1051 if (pci_request_regions(pdev, DRV_NAME)) {
1052 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1053 err = -ENODEV;
1054 goto err_out_disable;
1055 }
1056
1057 ioaddr = pci_iomap(pdev, bar, io_size);
1058 if (!ioaddr) {
1059 printk(KERN_ERR "ioremap failed for device %s\n",
1060 pci_name(pdev));
1061 return -EIO;
1062 }
1063
1064 /* Init system & device */
7a47dd7a
SW		 1065 lp->base = ioaddr;
1066 dev->irq = pdev->irq;
1067
1068 spin_lock_init(&lp->lock);
1069 pci_set_drvdata(pdev, dev);
1070
1071 /* Set MAC address */
1072 card_idx++;
1073
1074 adrp = (u16 *)dev->dev_addr;
1075 adrp[0] = ioread16(ioaddr + MID_0L);
1076 adrp[1] = ioread16(ioaddr + MID_0M);
1077 adrp[2] = ioread16(ioaddr + MID_0H);
1078
1079 /* Link new device into r6040_root_dev */
1080 lp->pdev = pdev;
1081
1082 /* Init RDC private data */
1083 lp->mcr0 = 0x1002;
1084 lp->phy_addr = phy_table[card_idx];
1085 lp->switch_sig = 0;
1086
1087 /* The RDC-specific entries in the device structure. */
1088 dev->open = &r6040_open;
1089 dev->hard_start_xmit = &r6040_start_xmit;
1090 dev->stop = &r6040_close;
1091 dev->get_stats = r6040_get_stats;
1092 dev->set_multicast_list = &r6040_multicast_list;
1093 dev->do_ioctl = &r6040_ioctl;
1094 dev->ethtool_ops = &netdev_ethtool_ops;
1095 dev->tx_timeout = &r6040_tx_timeout;
1096 dev->watchdog_timeo = TX_TIMEOUT;
1097#ifdef CONFIG_NET_POLL_CONTROLLER
1098 dev->poll_controller = r6040_poll_controller;
1099#endif
1100 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1101 lp->mii_if.dev = dev;
c6e69bb9
FF		 1102 lp->mii_if.mdio_read = r6040_mdio_read;
1103 lp->mii_if.mdio_write = r6040_mdio_write;
7a47dd7a
SW		 1104 lp->mii_if.phy_id = lp->phy_addr;
1105 lp->mii_if.phy_id_mask = 0x1f;
1106 lp->mii_if.reg_num_mask = 0x1f;
1107
1108 /* Register net device. After this dev->name assign */
1109 err = register_netdev(dev);
1110 if (err) {
1111 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1112 goto err_out_res;
1113 }
1114 return 0;
1115
1116err_out_res:
1117 pci_release_regions(pdev);
1118err_out_disable:
1119 pci_disable_device(pdev);
1120 pci_set_drvdata(pdev, NULL);
1121 free_netdev(dev);
1122
1123 return err;
1124}
1125
1126static void __devexit r6040_remove_one(struct pci_dev *pdev)
1127{
1128 struct net_device *dev = pci_get_drvdata(pdev);
1129
1130 unregister_netdev(dev);
1131 pci_release_regions(pdev);
1132 free_netdev(dev);
1133 pci_disable_device(pdev);
1134 pci_set_drvdata(pdev, NULL);
1135}
1136
1137
1138static struct pci_device_id r6040_pci_tbl[] = {
5ac5d616
FR		 1139 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1140 { 0 }
7a47dd7a
SW		 1141};
1142MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1143
1144static struct pci_driver r6040_driver = {
5ac5d616 1145 .name = DRV_NAME,
7a47dd7a
SW		 1146 .id_table = r6040_pci_tbl,
1147 .probe = r6040_init_one,
1148 .remove = __devexit_p(r6040_remove_one),
1149};
1150
1151
1152static int __init r6040_init(void)
1153{
1154 return pci_register_driver(&r6040_driver);
1155}
1156
1157
1158static void __exit r6040_cleanup(void)
1159{
1160 pci_unregister_driver(&r6040_driver);
1161}
1162
1163module_init(r6040_init);
1164module_exit(r6040_cleanup);
Linux 6.x block layer and io_uring tree(s)