projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
qla3xxx: bugfix: Add tx control block memset.
[linux-2.6-block.git] / drivers / net / qla3xxx.c
CommitLineData
5a4faa87
RM		 1/*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <linux/dmapool.h>
18#include <linux/mempool.h>
19#include <linux/spinlock.h>
20#include <linux/kthread.h>
21#include <linux/interrupt.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/ip.h>
bd36b0ac 25#include <linux/in.h>
5a4faa87
RM		 26#include <linux/if_arp.h>
27#include <linux/if_ether.h>
28#include <linux/netdevice.h>
29#include <linux/etherdevice.h>
30#include <linux/ethtool.h>
31#include <linux/skbuff.h>
32#include <linux/rtnetlink.h>
33#include <linux/if_vlan.h>
34#include <linux/init.h>
35#include <linux/delay.h>
36#include <linux/mm.h>
37
38#include "qla3xxx.h"
39
40#define DRV_NAME "qla3xxx"
41#define DRV_STRING "QLogic ISP3XXX Network Driver"
ed227dcc 42#define DRV_VERSION "v2.03.00-k3"
5a4faa87
RM		 43#define PFX DRV_NAME " "
44
45static const char ql3xxx_driver_name[] = DRV_NAME;
46static const char ql3xxx_driver_version[] = DRV_VERSION;
47
48MODULE_AUTHOR("QLogic Corporation");
49MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
50MODULE_LICENSE("GPL");
51MODULE_VERSION(DRV_VERSION);
52
53static const u32 default_msg
54 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
55 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
56
57static int debug = -1; /* defaults above */
58module_param(debug, int, 0);
59MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
60
61static int msi;
62module_param(msi, int, 0);
63MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
64
65static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
66 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
bd36b0ac 67 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
5a4faa87
RM		 68 /* required last entry */
69 {0,}
70};
71
72MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
73
74/*
75 * Caller must take hw_lock.
76 */
77static int ql_sem_spinlock(struct ql3_adapter *qdev,
78 u32 sem_mask, u32 sem_bits)
79{
80 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
81 u32 value;
82 unsigned int seconds = 3;
83
84 do {
85 writel((sem_mask | sem_bits),
86 &port_regs->CommonRegs.semaphoreReg);
87 value = readl(&port_regs->CommonRegs.semaphoreReg);
88 if ((value & (sem_mask >> 16)) == sem_bits)
89 return 0;
90 ssleep(1);
91 } while(--seconds);
92 return -1;
93}
94
95static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
96{
97 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
98 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
99 readl(&port_regs->CommonRegs.semaphoreReg);
100}
101
102static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
103{
104 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
105 u32 value;
106
107 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
108 value = readl(&port_regs->CommonRegs.semaphoreReg);
109 return ((value & (sem_mask >> 16)) == sem_bits);
110}
111
112/*
113 * Caller holds hw_lock.
114 */
115static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
116{
117 int i = 0;
118
119 while (1) {
120 if (!ql_sem_lock(qdev,
121 QL_DRVR_SEM_MASK,
122 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
123 * 2) << 1)) {
124 if (i < 10) {
125 ssleep(1);
126 i++;
127 } else {
128 printk(KERN_ERR PFX "%s: Timed out waiting for "
129 "driver lock...\n",
130 qdev->ndev->name);
131 return 0;
132 }
133 } else {
134 printk(KERN_DEBUG PFX
135 "%s: driver lock acquired.\n",
136 qdev->ndev->name);
137 return 1;
138 }
139 }
140}
141
142static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
143{
144 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
145
146 writel(((ISP_CONTROL_NP_MASK << 16) | page),
147 &port_regs->CommonRegs.ispControlStatus);
148 readl(&port_regs->CommonRegs.ispControlStatus);
149 qdev->current_page = page;
150}
151
152static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
153 u32 __iomem * reg)
154{
155 u32 value;
156 unsigned long hw_flags;
157
158 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
159 value = readl(reg);
160 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
161
162 return value;
163}
164
165static u32 ql_read_common_reg(struct ql3_adapter *qdev,
166 u32 __iomem * reg)
167{
168 return readl(reg);
169}
170
171static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
172{
173 u32 value;
174 unsigned long hw_flags;
175
176 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
177
178 if (qdev->current_page != 0)
179 ql_set_register_page(qdev,0);
180 value = readl(reg);
181
182 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
183 return value;
184}
185
186static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
187{
188 if (qdev->current_page != 0)
189 ql_set_register_page(qdev,0);
190 return readl(reg);
191}
192
193static void ql_write_common_reg_l(struct ql3_adapter *qdev,
ee111d11 194 u32 __iomem *reg, u32 value)
5a4faa87
RM		 195{
196 unsigned long hw_flags;
197
198 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
ee111d11 199 writel(value, reg);
5a4faa87
RM		 200 readl(reg);
201 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
202 return;
203}
204
205static void ql_write_common_reg(struct ql3_adapter *qdev,
ee111d11 206 u32 __iomem *reg, u32 value)
5a4faa87 207{
ee111d11 208 writel(value, reg);
5a4faa87
RM		 209 readl(reg);
210 return;
211}
212
80b02e59
RM		 213static void ql_write_nvram_reg(struct ql3_adapter *qdev,
214 u32 __iomem *reg, u32 value)
215{
216 writel(value, reg);
217 readl(reg);
218 udelay(1);
219 return;
220}
221
5a4faa87 222static void ql_write_page0_reg(struct ql3_adapter *qdev,
ee111d11 223 u32 __iomem *reg, u32 value)
5a4faa87
RM		 224{
225 if (qdev->current_page != 0)
226 ql_set_register_page(qdev,0);
ee111d11 227 writel(value, reg);
5a4faa87
RM		 228 readl(reg);
229 return;
230}
231
232/*
233 * Caller holds hw_lock. Only called during init.
234 */
235static void ql_write_page1_reg(struct ql3_adapter *qdev,
ee111d11 236 u32 __iomem *reg, u32 value)
5a4faa87
RM		 237{
238 if (qdev->current_page != 1)
239 ql_set_register_page(qdev,1);
ee111d11 240 writel(value, reg);
5a4faa87
RM		 241 readl(reg);
242 return;
243}
244
245/*
246 * Caller holds hw_lock. Only called during init.
247 */
248static void ql_write_page2_reg(struct ql3_adapter *qdev,
ee111d11 249 u32 __iomem *reg, u32 value)
5a4faa87
RM		 250{
251 if (qdev->current_page != 2)
252 ql_set_register_page(qdev,2);
ee111d11 253 writel(value, reg);
5a4faa87
RM		 254 readl(reg);
255 return;
256}
257
258static void ql_disable_interrupts(struct ql3_adapter *qdev)
259{
260 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
261
262 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
263 (ISP_IMR_ENABLE_INT << 16));
264
265}
266
267static void ql_enable_interrupts(struct ql3_adapter *qdev)
268{
269 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
270
271 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
272 ((0xff << 16) | ISP_IMR_ENABLE_INT));
273
274}
275
276static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
277 struct ql_rcv_buf_cb *lrg_buf_cb)
278{
0f8ab89e
BL		 279 dma_addr_t map;
280 int err;
5a4faa87
RM		 281 lrg_buf_cb->next = NULL;
282
283 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
284 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
285 } else {
286 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
287 qdev->lrg_buf_free_tail = lrg_buf_cb;
288 }
289
290 if (!lrg_buf_cb->skb) {
cd238faa
BL		 291 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
292 qdev->lrg_buffer_len);
5a4faa87 293 if (unlikely(!lrg_buf_cb->skb)) {
cd238faa 294 printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
5a4faa87
RM		 295 qdev->ndev->name);
296 qdev->lrg_buf_skb_check++;
297 } else {
298 /*
299 * We save some space to copy the ethhdr from first
300 * buffer
301 */
302 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
303 map = pci_map_single(qdev->pdev,
304 lrg_buf_cb->skb->data,
305 qdev->lrg_buffer_len -
306 QL_HEADER_SPACE,
307 PCI_DMA_FROMDEVICE);
0f8ab89e
BL		 308 err = pci_dma_mapping_error(map);
309 if(err) {
310 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
311 qdev->ndev->name, err);
312 dev_kfree_skb(lrg_buf_cb->skb);
313 lrg_buf_cb->skb = NULL;
314
315 qdev->lrg_buf_skb_check++;
316 return;
317 }
318
5a4faa87
RM		 319 lrg_buf_cb->buf_phy_addr_low =
320 cpu_to_le32(LS_64BITS(map));
321 lrg_buf_cb->buf_phy_addr_high =
322 cpu_to_le32(MS_64BITS(map));
323 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
324 pci_unmap_len_set(lrg_buf_cb, maplen,
325 qdev->lrg_buffer_len -
326 QL_HEADER_SPACE);
327 }
328 }
329
330 qdev->lrg_buf_free_count++;
331}
332
333static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
334 *qdev)
335{
336 struct ql_rcv_buf_cb *lrg_buf_cb;
337
338 if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
339 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
340 qdev->lrg_buf_free_tail = NULL;
341 qdev->lrg_buf_free_count--;
342 }
343
344 return lrg_buf_cb;
345}
346
347static u32 addrBits = EEPROM_NO_ADDR_BITS;
348static u32 dataBits = EEPROM_NO_DATA_BITS;
349
350static void fm93c56a_deselect(struct ql3_adapter *qdev);
351static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
352 unsigned short *value);
353
354/*
355 * Caller holds hw_lock.
356 */
357static void fm93c56a_select(struct ql3_adapter *qdev)
358{
359 struct ql3xxx_port_registers __iomem *port_regs =
360 qdev->mem_map_registers;
361
362 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
80b02e59 363 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87 364 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
80b02e59 365 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 366 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
367}
368
369/*
370 * Caller holds hw_lock.
371 */
372static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
373{
374 int i;
375 u32 mask;
376 u32 dataBit;
377 u32 previousBit;
378 struct ql3xxx_port_registers __iomem *port_regs =
379 qdev->mem_map_registers;
380
381 /* Clock in a zero, then do the start bit */
80b02e59 382 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 383 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
384 AUBURN_EEPROM_DO_1);
80b02e59 385 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 386 ISP_NVRAM_MASK | qdev->
387 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
388 AUBURN_EEPROM_CLK_RISE);
80b02e59 389 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 390 ISP_NVRAM_MASK | qdev->
391 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
392 AUBURN_EEPROM_CLK_FALL);
393
394 mask = 1 << (FM93C56A_CMD_BITS - 1);
395 /* Force the previous data bit to be different */
396 previousBit = 0xffff;
397 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
398 dataBit =
399 (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
400 if (previousBit != dataBit) {
401 /*
402 * If the bit changed, then change the DO state to
403 * match
404 */
80b02e59 405 ql_write_nvram_reg(qdev,
5a4faa87
RM		 406 &port_regs->CommonRegs.
407 serialPortInterfaceReg,
408 ISP_NVRAM_MASK | qdev->
409 eeprom_cmd_data | dataBit);
410 previousBit = dataBit;
411 }
80b02e59 412 ql_write_nvram_reg(qdev,
5a4faa87
RM		 413 &port_regs->CommonRegs.
414 serialPortInterfaceReg,
415 ISP_NVRAM_MASK | qdev->
416 eeprom_cmd_data | dataBit |
417 AUBURN_EEPROM_CLK_RISE);
80b02e59 418 ql_write_nvram_reg(qdev,
5a4faa87
RM		 419 &port_regs->CommonRegs.
420 serialPortInterfaceReg,
421 ISP_NVRAM_MASK | qdev->
422 eeprom_cmd_data | dataBit |
423 AUBURN_EEPROM_CLK_FALL);
424 cmd = cmd << 1;
425 }
426
427 mask = 1 << (addrBits - 1);
428 /* Force the previous data bit to be different */
429 previousBit = 0xffff;
430 for (i = 0; i < addrBits; i++) {
431 dataBit =
432 (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
433 AUBURN_EEPROM_DO_0;
434 if (previousBit != dataBit) {
435 /*
436 * If the bit changed, then change the DO state to
437 * match
438 */
80b02e59 439 ql_write_nvram_reg(qdev,
5a4faa87
RM		 440 &port_regs->CommonRegs.
441 serialPortInterfaceReg,
442 ISP_NVRAM_MASK | qdev->
443 eeprom_cmd_data | dataBit);
444 previousBit = dataBit;
445 }
80b02e59 446 ql_write_nvram_reg(qdev,
5a4faa87
RM		 447 &port_regs->CommonRegs.
448 serialPortInterfaceReg,
449 ISP_NVRAM_MASK | qdev->
450 eeprom_cmd_data | dataBit |
451 AUBURN_EEPROM_CLK_RISE);
80b02e59 452 ql_write_nvram_reg(qdev,
5a4faa87
RM		 453 &port_regs->CommonRegs.
454 serialPortInterfaceReg,
455 ISP_NVRAM_MASK | qdev->
456 eeprom_cmd_data | dataBit |
457 AUBURN_EEPROM_CLK_FALL);
458 eepromAddr = eepromAddr << 1;
459 }
460}
461
462/*
463 * Caller holds hw_lock.
464 */
465static void fm93c56a_deselect(struct ql3_adapter *qdev)
466{
467 struct ql3xxx_port_registers __iomem *port_regs =
468 qdev->mem_map_registers;
469 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
80b02e59 470 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 471 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
472}
473
474/*
475 * Caller holds hw_lock.
476 */
477static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
478{
479 int i;
480 u32 data = 0;
481 u32 dataBit;
482 struct ql3xxx_port_registers __iomem *port_regs =
483 qdev->mem_map_registers;
484
485 /* Read the data bits */
486 /* The first bit is a dummy. Clock right over it. */
487 for (i = 0; i < dataBits; i++) {
80b02e59 488 ql_write_nvram_reg(qdev,
5a4faa87
RM		 489 &port_regs->CommonRegs.
490 serialPortInterfaceReg,
491 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
492 AUBURN_EEPROM_CLK_RISE);
80b02e59 493 ql_write_nvram_reg(qdev,
5a4faa87
RM		 494 &port_regs->CommonRegs.
495 serialPortInterfaceReg,
496 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
497 AUBURN_EEPROM_CLK_FALL);
498 dataBit =
499 (ql_read_common_reg
500 (qdev,
501 &port_regs->CommonRegs.
502 serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
503 data = (data << 1) | dataBit;
504 }
505 *value = (u16) data;
506}
507
508/*
509 * Caller holds hw_lock.
510 */
511static void eeprom_readword(struct ql3_adapter *qdev,
512 u32 eepromAddr, unsigned short *value)
513{
514 fm93c56a_select(qdev);
515 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
516 fm93c56a_datain(qdev, value);
517 fm93c56a_deselect(qdev);
518}
519
520static void ql_swap_mac_addr(u8 * macAddress)
521{
522#ifdef __BIG_ENDIAN
523 u8 temp;
524 temp = macAddress[0];
525 macAddress[0] = macAddress[1];
526 macAddress[1] = temp;
527 temp = macAddress[2];
528 macAddress[2] = macAddress[3];
529 macAddress[3] = temp;
530 temp = macAddress[4];
531 macAddress[4] = macAddress[5];
532 macAddress[5] = temp;
533#endif
534}
535
536static int ql_get_nvram_params(struct ql3_adapter *qdev)
537{
538 u16 *pEEPROMData;
539 u16 checksum = 0;
540 u32 index;
541 unsigned long hw_flags;
542
543 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
544
545 pEEPROMData = (u16 *) & qdev->nvram_data;
546 qdev->eeprom_cmd_data = 0;
547 if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
548 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
549 2) << 10)) {
550 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
551 __func__);
552 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
553 return -1;
554 }
555
556 for (index = 0; index < EEPROM_SIZE; index++) {
557 eeprom_readword(qdev, index, pEEPROMData);
558 checksum += *pEEPROMData;
559 pEEPROMData++;
560 }
561 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
562
563 if (checksum != 0) {
564 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
565 qdev->ndev->name, checksum);
566 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
567 return -1;
568 }
569
570 /*
571 * We have a problem with endianness for the MAC addresses
572 * and the two 8-bit values version, and numPorts. We
573 * have to swap them on big endian systems.
574 */
575 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
576 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
577 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
578 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
579 pEEPROMData = (u16 *) & qdev->nvram_data.version;
580 *pEEPROMData = le16_to_cpu(*pEEPROMData);
581
582 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
583 return checksum;
584}
585
586static const u32 PHYAddr[2] = {
587 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
588};
589
590static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
591{
592 struct ql3xxx_port_registers __iomem *port_regs =
593 qdev->mem_map_registers;
594 u32 temp;
595 int count = 1000;
596
597 while (count) {
598 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
599 if (!(temp & MAC_MII_STATUS_BSY))
600 return 0;
601 udelay(10);
602 count--;
603 }
604 return -1;
605}
606
607static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
608{
609 struct ql3xxx_port_registers __iomem *port_regs =
610 qdev->mem_map_registers;
611 u32 scanControl;
612
613 if (qdev->numPorts > 1) {
614 /* Auto scan will cycle through multiple ports */
615 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
616 } else {
617 scanControl = MAC_MII_CONTROL_SC;
618 }
619
620 /*
621 * Scan register 1 of PHY/PETBI,
622 * Set up to scan both devices
623 * The autoscan starts from the first register, completes
624 * the last one before rolling over to the first
625 */
626 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
627 PHYAddr[0] | MII_SCAN_REGISTER);
628
629 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
630 (scanControl) |
631 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
632}
633
634static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
635{
636 u8 ret;
637 struct ql3xxx_port_registers __iomem *port_regs =
638 qdev->mem_map_registers;
639
640 /* See if scan mode is enabled before we turn it off */
641 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
642 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
643 /* Scan is enabled */
644 ret = 1;
645 } else {
646 /* Scan is disabled */
647 ret = 0;
648 }
649
650 /*
651 * When disabling scan mode you must first change the MII register
652 * address
653 */
654 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
655 PHYAddr[0] | MII_SCAN_REGISTER);
656
657 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
658 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
659 MAC_MII_CONTROL_RC) << 16));
660
661 return ret;
662}
663
664static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
665 u16 regAddr, u16 value, u32 mac_index)
666{
667 struct ql3xxx_port_registers __iomem *port_regs =
668 qdev->mem_map_registers;
669 u8 scanWasEnabled;
670
671 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
672
673 if (ql_wait_for_mii_ready(qdev)) {
674 if (netif_msg_link(qdev))
675 printk(KERN_WARNING PFX
676 "%s Timed out waiting for management port to "
677 "get free before issuing command.\n",
678 qdev->ndev->name);
679 return -1;
680 }
681
682 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
683 PHYAddr[mac_index] | regAddr);
684
685 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
686
687 /* Wait for write to complete 9/10/04 SJP */
688 if (ql_wait_for_mii_ready(qdev)) {
689 if (netif_msg_link(qdev))
690 printk(KERN_WARNING PFX
691 "%s: Timed out waiting for management port to"
692 "get free before issuing command.\n",
693 qdev->ndev->name);
694 return -1;
695 }
696
697 if (scanWasEnabled)
698 ql_mii_enable_scan_mode(qdev);
699
700 return 0;
701}
702
703static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
704 u16 * value, u32 mac_index)
705{
706 struct ql3xxx_port_registers __iomem *port_regs =
707 qdev->mem_map_registers;
708 u8 scanWasEnabled;
709 u32 temp;
710
711 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
712
713 if (ql_wait_for_mii_ready(qdev)) {
714 if (netif_msg_link(qdev))
715 printk(KERN_WARNING PFX
716 "%s: Timed out waiting for management port to "
717 "get free before issuing command.\n",
718 qdev->ndev->name);
719 return -1;
720 }
721
722 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
723 PHYAddr[mac_index] | regAddr);
724
725 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
726 (MAC_MII_CONTROL_RC << 16));
727
728 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
729 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
730
731 /* Wait for the read to complete */
732 if (ql_wait_for_mii_ready(qdev)) {
733 if (netif_msg_link(qdev))
734 printk(KERN_WARNING PFX
735 "%s: Timed out waiting for management port to "
736 "get free after issuing command.\n",
737 qdev->ndev->name);
738 return -1;
739 }
740
741 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
742 *value = (u16) temp;
743
744 if (scanWasEnabled)
745 ql_mii_enable_scan_mode(qdev);
746
747 return 0;
748}
749
750static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
751{
752 struct ql3xxx_port_registers __iomem *port_regs =
753 qdev->mem_map_registers;
754
755 ql_mii_disable_scan_mode(qdev);
756
757 if (ql_wait_for_mii_ready(qdev)) {
758 if (netif_msg_link(qdev))
759 printk(KERN_WARNING PFX
760 "%s: Timed out waiting for management port to "
761 "get free before issuing command.\n",
762 qdev->ndev->name);
763 return -1;
764 }
765
766 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
767 qdev->PHYAddr | regAddr);
768
769 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
770
771 /* Wait for write to complete. */
772 if (ql_wait_for_mii_ready(qdev)) {
773 if (netif_msg_link(qdev))
774 printk(KERN_WARNING PFX
775 "%s: Timed out waiting for management port to "
776 "get free before issuing command.\n",
777 qdev->ndev->name);
778 return -1;
779 }
780
781 ql_mii_enable_scan_mode(qdev);
782
783 return 0;
784}
785
786static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
787{
788 u32 temp;
789 struct ql3xxx_port_registers __iomem *port_regs =
790 qdev->mem_map_registers;
791
792 ql_mii_disable_scan_mode(qdev);
793
794 if (ql_wait_for_mii_ready(qdev)) {
795 if (netif_msg_link(qdev))
796 printk(KERN_WARNING PFX
797 "%s: Timed out waiting for management port to "
798 "get free before issuing command.\n",
799 qdev->ndev->name);
800 return -1;
801 }
802
803 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
804 qdev->PHYAddr | regAddr);
805
806 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
807 (MAC_MII_CONTROL_RC << 16));
808
809 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
810 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
811
812 /* Wait for the read to complete */
813 if (ql_wait_for_mii_ready(qdev)) {
814 if (netif_msg_link(qdev))
815 printk(KERN_WARNING PFX
816 "%s: Timed out waiting for management port to "
817 "get free before issuing command.\n",
818 qdev->ndev->name);
819 return -1;
820 }
821
822 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
823 *value = (u16) temp;
824
825 ql_mii_enable_scan_mode(qdev);
826
827 return 0;
828}
829
830static void ql_petbi_reset(struct ql3_adapter *qdev)
831{
832 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
833}
834
835static void ql_petbi_start_neg(struct ql3_adapter *qdev)
836{
837 u16 reg;
838
839 /* Enable Auto-negotiation sense */
840 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
841 reg |= PETBI_TBI_AUTO_SENSE;
842 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
843
844 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
845 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
846
847 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
848 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
849 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
850
851}
852
853static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
854{
855 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
856 mac_index);
857}
858
859static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
860{
861 u16 reg;
862
863 /* Enable Auto-negotiation sense */
864 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, mac_index);
865 reg |= PETBI_TBI_AUTO_SENSE;
866 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
867
868 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
869 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
870
871 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
872 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
873 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
874 mac_index);
875}
876
877static void ql_petbi_init(struct ql3_adapter *qdev)
878{
879 ql_petbi_reset(qdev);
880 ql_petbi_start_neg(qdev);
881}
882
883static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
884{
885 ql_petbi_reset_ex(qdev, mac_index);
886 ql_petbi_start_neg_ex(qdev, mac_index);
887}
888
889static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
890{
891 u16 reg;
892
893 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
894 return 0;
895
896 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
897}
898
899static int ql_phy_get_speed(struct ql3_adapter *qdev)
900{
901 u16 reg;
902
903 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
904 return 0;
905
906 reg = (((reg & 0x18) >> 3) & 3);
907
908 if (reg == 2)
909 return SPEED_1000;
910 else if (reg == 1)
911 return SPEED_100;
912 else if (reg == 0)
913 return SPEED_10;
914 else
915 return -1;
916}
917
918static int ql_is_full_dup(struct ql3_adapter *qdev)
919{
920 u16 reg;
921
922 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
923 return 0;
924
925 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
926}
927
928static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
929{
930 u16 reg;
931
932 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
933 return 0;
934
935 return (reg & PHY_NEG_PAUSE) != 0;
936}
937
938/*
939 * Caller holds hw_lock.
940 */
941static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
942{
943 struct ql3xxx_port_registers __iomem *port_regs =
944 qdev->mem_map_registers;
945 u32 value;
946
947 if (enable)
948 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
949 else
950 value = (MAC_CONFIG_REG_PE << 16);
951
952 if (qdev->mac_index)
953 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
954 else
955 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
956}
957
958/*
959 * Caller holds hw_lock.
960 */
961static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
962{
963 struct ql3xxx_port_registers __iomem *port_regs =
964 qdev->mem_map_registers;
965 u32 value;
966
967 if (enable)
968 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
969 else
970 value = (MAC_CONFIG_REG_SR << 16);
971
972 if (qdev->mac_index)
973 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
974 else
975 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
976}
977
978/*
979 * Caller holds hw_lock.
980 */
981static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
982{
983 struct ql3xxx_port_registers __iomem *port_regs =
984 qdev->mem_map_registers;
985 u32 value;
986
987 if (enable)
988 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
989 else
990 value = (MAC_CONFIG_REG_GM << 16);
991
992 if (qdev->mac_index)
993 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
994 else
995 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
996}
997
998/*
999 * Caller holds hw_lock.
1000 */
1001static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1002{
1003 struct ql3xxx_port_registers __iomem *port_regs =
1004 qdev->mem_map_registers;
1005 u32 value;
1006
1007 if (enable)
1008 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1009 else
1010 value = (MAC_CONFIG_REG_FD << 16);
1011
1012 if (qdev->mac_index)
1013 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1014 else
1015 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1016}
1017
1018/*
1019 * Caller holds hw_lock.
1020 */
1021static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1022{
1023 struct ql3xxx_port_registers __iomem *port_regs =
1024 qdev->mem_map_registers;
1025 u32 value;
1026
1027 if (enable)
1028 value =
1029 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1030 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1031 else
1032 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1033
1034 if (qdev->mac_index)
1035 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1036 else
1037 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1038}
1039
1040/*
1041 * Caller holds hw_lock.
1042 */
1043static int ql_is_fiber(struct ql3_adapter *qdev)
1044{
1045 struct ql3xxx_port_registers __iomem *port_regs =
1046 qdev->mem_map_registers;
1047 u32 bitToCheck = 0;
1048 u32 temp;
1049
1050 switch (qdev->mac_index) {
1051 case 0:
1052 bitToCheck = PORT_STATUS_SM0;
1053 break;
1054 case 1:
1055 bitToCheck = PORT_STATUS_SM1;
1056 break;
1057 }
1058
1059 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1060 return (temp & bitToCheck) != 0;
1061}
1062
1063static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1064{
1065 u16 reg;
1066 ql_mii_read_reg(qdev, 0x00, &reg);
1067 return (reg & 0x1000) != 0;
1068}
1069
1070/*
1071 * Caller holds hw_lock.
1072 */
1073static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1074{
1075 struct ql3xxx_port_registers __iomem *port_regs =
1076 qdev->mem_map_registers;
1077 u32 bitToCheck = 0;
1078 u32 temp;
1079
1080 switch (qdev->mac_index) {
1081 case 0:
1082 bitToCheck = PORT_STATUS_AC0;
1083 break;
1084 case 1:
1085 bitToCheck = PORT_STATUS_AC1;
1086 break;
1087 }
1088
1089 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1090 if (temp & bitToCheck) {
1091 if (netif_msg_link(qdev))
1092 printk(KERN_INFO PFX
1093 "%s: Auto-Negotiate complete.\n",
1094 qdev->ndev->name);
1095 return 1;
1096 } else {
1097 if (netif_msg_link(qdev))
1098 printk(KERN_WARNING PFX
1099 "%s: Auto-Negotiate incomplete.\n",
1100 qdev->ndev->name);
1101 return 0;
1102 }
1103}
1104
1105/*
1106 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1107 */
1108static int ql_is_neg_pause(struct ql3_adapter *qdev)
1109{
1110 if (ql_is_fiber(qdev))
1111 return ql_is_petbi_neg_pause(qdev);
1112 else
1113 return ql_is_phy_neg_pause(qdev);
1114}
1115
1116static int ql_auto_neg_error(struct ql3_adapter *qdev)
1117{
1118 struct ql3xxx_port_registers __iomem *port_regs =
1119 qdev->mem_map_registers;
1120 u32 bitToCheck = 0;
1121 u32 temp;
1122
1123 switch (qdev->mac_index) {
1124 case 0:
1125 bitToCheck = PORT_STATUS_AE0;
1126 break;
1127 case 1:
1128 bitToCheck = PORT_STATUS_AE1;
1129 break;
1130 }
1131 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1132 return (temp & bitToCheck) != 0;
1133}
1134
1135static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1136{
1137 if (ql_is_fiber(qdev))
1138 return SPEED_1000;
1139 else
1140 return ql_phy_get_speed(qdev);
1141}
1142
1143static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1144{
1145 if (ql_is_fiber(qdev))
1146 return 1;
1147 else
1148 return ql_is_full_dup(qdev);
1149}
1150
1151/*
1152 * Caller holds hw_lock.
1153 */
1154static int ql_link_down_detect(struct ql3_adapter *qdev)
1155{
1156 struct ql3xxx_port_registers __iomem *port_regs =
1157 qdev->mem_map_registers;
1158 u32 bitToCheck = 0;
1159 u32 temp;
1160
1161 switch (qdev->mac_index) {
1162 case 0:
1163 bitToCheck = ISP_CONTROL_LINK_DN_0;
1164 break;
1165 case 1:
1166 bitToCheck = ISP_CONTROL_LINK_DN_1;
1167 break;
1168 }
1169
1170 temp =
1171 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1172 return (temp & bitToCheck) != 0;
1173}
1174
1175/*
1176 * Caller holds hw_lock.
1177 */
1178static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1179{
1180 struct ql3xxx_port_registers __iomem *port_regs =
1181 qdev->mem_map_registers;
1182
1183 switch (qdev->mac_index) {
1184 case 0:
1185 ql_write_common_reg(qdev,
1186 &port_regs->CommonRegs.ispControlStatus,
1187 (ISP_CONTROL_LINK_DN_0) |
1188 (ISP_CONTROL_LINK_DN_0 << 16));
1189 break;
1190
1191 case 1:
1192 ql_write_common_reg(qdev,
1193 &port_regs->CommonRegs.ispControlStatus,
1194 (ISP_CONTROL_LINK_DN_1) |
1195 (ISP_CONTROL_LINK_DN_1 << 16));
1196 break;
1197
1198 default:
1199 return 1;
1200 }
1201
1202 return 0;
1203}
1204
1205/*
1206 * Caller holds hw_lock.
1207 */
1208static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
1209 u32 mac_index)
1210{
1211 struct ql3xxx_port_registers __iomem *port_regs =
1212 qdev->mem_map_registers;
1213 u32 bitToCheck = 0;
1214 u32 temp;
1215
1216 switch (mac_index) {
1217 case 0:
1218 bitToCheck = PORT_STATUS_F1_ENABLED;
1219 break;
1220 case 1:
1221 bitToCheck = PORT_STATUS_F3_ENABLED;
1222 break;
1223 default:
1224 break;
1225 }
1226
1227 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1228 if (temp & bitToCheck) {
1229 if (netif_msg_link(qdev))
1230 printk(KERN_DEBUG PFX
1231 "%s: is not link master.\n", qdev->ndev->name);
1232 return 0;
1233 } else {
1234 if (netif_msg_link(qdev))
1235 printk(KERN_DEBUG PFX
1236 "%s: is link master.\n", qdev->ndev->name);
1237 return 1;
1238 }
1239}
1240
1241static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
1242{
1243 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
1244}
1245
1246static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
1247{
1248 u16 reg;
1249
1250 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
1251 PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
1252
1253 ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, mac_index);
1254 ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
1255 mac_index);
1256}
1257
1258static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
1259{
1260 ql_phy_reset_ex(qdev, mac_index);
1261 ql_phy_start_neg_ex(qdev, mac_index);
1262}
1263
1264/*
1265 * Caller holds hw_lock.
1266 */
1267static u32 ql_get_link_state(struct ql3_adapter *qdev)
1268{
1269 struct ql3xxx_port_registers __iomem *port_regs =
1270 qdev->mem_map_registers;
1271 u32 bitToCheck = 0;
1272 u32 temp, linkState;
1273
1274 switch (qdev->mac_index) {
1275 case 0:
1276 bitToCheck = PORT_STATUS_UP0;
1277 break;
1278 case 1:
1279 bitToCheck = PORT_STATUS_UP1;
1280 break;
1281 }
1282 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1283 if (temp & bitToCheck) {
1284 linkState = LS_UP;
1285 } else {
1286 linkState = LS_DOWN;
1287 if (netif_msg_link(qdev))
1288 printk(KERN_WARNING PFX
1289 "%s: Link is down.\n", qdev->ndev->name);
1290 }
1291 return linkState;
1292}
1293
1294static int ql_port_start(struct ql3_adapter *qdev)
1295{
1296 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1297 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1298 2) << 7))
1299 return -1;
1300
1301 if (ql_is_fiber(qdev)) {
1302 ql_petbi_init(qdev);
1303 } else {
1304 /* Copper port */
1305 ql_phy_init_ex(qdev, qdev->mac_index);
1306 }
1307
1308 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1309 return 0;
1310}
1311
1312static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1313{
1314
1315 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1316 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1317 2) << 7))
1318 return -1;
1319
1320 if (!ql_auto_neg_error(qdev)) {
1321 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1322 /* configure the MAC */
1323 if (netif_msg_link(qdev))
1324 printk(KERN_DEBUG PFX
1325 "%s: Configuring link.\n",
1326 qdev->ndev->
1327 name);
1328 ql_mac_cfg_soft_reset(qdev, 1);
1329 ql_mac_cfg_gig(qdev,
1330 (ql_get_link_speed
1331 (qdev) ==
1332 SPEED_1000));
1333 ql_mac_cfg_full_dup(qdev,
1334 ql_is_link_full_dup
1335 (qdev));
1336 ql_mac_cfg_pause(qdev,
1337 ql_is_neg_pause
1338 (qdev));
1339 ql_mac_cfg_soft_reset(qdev, 0);
1340
1341 /* enable the MAC */
1342 if (netif_msg_link(qdev))
1343 printk(KERN_DEBUG PFX
1344 "%s: Enabling mac.\n",
1345 qdev->ndev->
1346 name);
1347 ql_mac_enable(qdev, 1);
1348 }
1349
1350 if (netif_msg_link(qdev))
1351 printk(KERN_DEBUG PFX
1352 "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1353 qdev->ndev->name);
1354 qdev->port_link_state = LS_UP;
1355 netif_start_queue(qdev->ndev);
1356 netif_carrier_on(qdev->ndev);
1357 if (netif_msg_link(qdev))
1358 printk(KERN_INFO PFX
1359 "%s: Link is up at %d Mbps, %s duplex.\n",
1360 qdev->ndev->name,
1361 ql_get_link_speed(qdev),
1362 ql_is_link_full_dup(qdev)
1363 ? "full" : "half");
1364
1365 } else { /* Remote error detected */
1366
1367 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1368 if (netif_msg_link(qdev))
1369 printk(KERN_DEBUG PFX
1370 "%s: Remote error detected. "
1371 "Calling ql_port_start().\n",
1372 qdev->ndev->
1373 name);
1374 /*
1375 * ql_port_start() is shared code and needs
1376 * to lock the PHY on it's own.
1377 */
1378 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1379 if(ql_port_start(qdev)) {/* Restart port */
1380 return -1;
1381 } else
1382 return 0;
1383 }
1384 }
1385 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1386 return 0;
1387}
1388
1389static void ql_link_state_machine(struct ql3_adapter *qdev)
1390{
1391 u32 curr_link_state;
1392 unsigned long hw_flags;
1393
1394 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1395
1396 curr_link_state = ql_get_link_state(qdev);
1397
1398 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1399 if (netif_msg_link(qdev))
1400 printk(KERN_INFO PFX
1401 "%s: Reset in progress, skip processing link "
1402 "state.\n", qdev->ndev->name);
04f10773
BL		 1403
1404 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 1405 return;
1406 }
1407
1408 switch (qdev->port_link_state) {
1409 default:
1410 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1411 ql_port_start(qdev);
1412 }
1413 qdev->port_link_state = LS_DOWN;
1414 /* Fall Through */
1415
1416 case LS_DOWN:
1417 if (netif_msg_link(qdev))
1418 printk(KERN_DEBUG PFX
1419 "%s: port_link_state = LS_DOWN.\n",
1420 qdev->ndev->name);
1421 if (curr_link_state == LS_UP) {
1422 if (netif_msg_link(qdev))
1423 printk(KERN_DEBUG PFX
1424 "%s: curr_link_state = LS_UP.\n",
1425 qdev->ndev->name);
1426 if (ql_is_auto_neg_complete(qdev))
1427 ql_finish_auto_neg(qdev);
1428
1429 if (qdev->port_link_state == LS_UP)
1430 ql_link_down_detect_clear(qdev);
1431
1432 }
1433 break;
1434
1435 case LS_UP:
1436 /*
1437 * See if the link is currently down or went down and came
1438 * back up
1439 */
1440 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1441 if (netif_msg_link(qdev))
1442 printk(KERN_INFO PFX "%s: Link is down.\n",
1443 qdev->ndev->name);
1444 qdev->port_link_state = LS_DOWN;
1445 }
1446 break;
1447 }
1448 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1449}
1450
1451/*
1452 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1453 */
1454static void ql_get_phy_owner(struct ql3_adapter *qdev)
1455{
1456 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1457 set_bit(QL_LINK_MASTER,&qdev->flags);
1458 else
1459 clear_bit(QL_LINK_MASTER,&qdev->flags);
1460}
1461
1462/*
1463 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1464 */
1465static void ql_init_scan_mode(struct ql3_adapter *qdev)
1466{
1467 ql_mii_enable_scan_mode(qdev);
1468
1469 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1470 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1471 ql_petbi_init_ex(qdev, qdev->mac_index);
1472 } else {
1473 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1474 ql_phy_init_ex(qdev, qdev->mac_index);
1475 }
1476}
1477
1478/*
1479 * MII_Setup needs to be called before taking the PHY out of reset so that the
1480 * management interface clock speed can be set properly. It would be better if
1481 * we had a way to disable MDC until after the PHY is out of reset, but we
1482 * don't have that capability.
1483 */
1484static int ql_mii_setup(struct ql3_adapter *qdev)
1485{
1486 u32 reg;
1487 struct ql3xxx_port_registers __iomem *port_regs =
1488 qdev->mem_map_registers;
1489
1490 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1491 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1492 2) << 7))
1493 return -1;
1494
bd36b0ac
RM		 1495 if (qdev->device_id == QL3032_DEVICE_ID)
1496 ql_write_page0_reg(qdev,
1497 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1498
5a4faa87
RM		 1499 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1500 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1501
1502 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1503 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1504
1505 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1506 return 0;
1507}
1508
1509static u32 ql_supported_modes(struct ql3_adapter *qdev)
1510{
1511 u32 supported;
1512
1513 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1514 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1515 | SUPPORTED_Autoneg;
1516 } else {
1517 supported = SUPPORTED_10baseT_Half
1518 | SUPPORTED_10baseT_Full
1519 | SUPPORTED_100baseT_Half
1520 | SUPPORTED_100baseT_Full
1521 | SUPPORTED_1000baseT_Half
1522 | SUPPORTED_1000baseT_Full
1523 | SUPPORTED_Autoneg | SUPPORTED_TP;
1524 }
1525
1526 return supported;
1527}
1528
1529static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1530{
1531 int status;
1532 unsigned long hw_flags;
1533 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1534 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1535 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1536 2) << 7)) {
1537 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1538 return 0;
04f10773 1539 }
5a4faa87
RM		 1540 status = ql_is_auto_cfg(qdev);
1541 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1542 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1543 return status;
1544}
1545
1546static u32 ql_get_speed(struct ql3_adapter *qdev)
1547{
1548 u32 status;
1549 unsigned long hw_flags;
1550 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1551 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1552 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1553 2) << 7)) {
1554 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1555 return 0;
04f10773 1556 }
5a4faa87
RM		 1557 status = ql_get_link_speed(qdev);
1558 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1559 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1560 return status;
1561}
1562
1563static int ql_get_full_dup(struct ql3_adapter *qdev)
1564{
1565 int status;
1566 unsigned long hw_flags;
1567 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1568 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1569 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1570 2) << 7)) {
1571 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1572 return 0;
04f10773 1573 }
5a4faa87
RM		 1574 status = ql_is_link_full_dup(qdev);
1575 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1576 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1577 return status;
1578}
1579
1580
1581static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1582{
1583 struct ql3_adapter *qdev = netdev_priv(ndev);
1584
1585 ecmd->transceiver = XCVR_INTERNAL;
1586 ecmd->supported = ql_supported_modes(qdev);
1587
1588 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1589 ecmd->port = PORT_FIBRE;
1590 } else {
1591 ecmd->port = PORT_TP;
1592 ecmd->phy_address = qdev->PHYAddr;
1593 }
1594 ecmd->advertising = ql_supported_modes(qdev);
1595 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1596 ecmd->speed = ql_get_speed(qdev);
1597 ecmd->duplex = ql_get_full_dup(qdev);
1598 return 0;
1599}
1600
1601static void ql_get_drvinfo(struct net_device *ndev,
1602 struct ethtool_drvinfo *drvinfo)
1603{
1604 struct ql3_adapter *qdev = netdev_priv(ndev);
1605 strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1606 strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1607 strncpy(drvinfo->fw_version, "N/A", 32);
1608 strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1609 drvinfo->n_stats = 0;
1610 drvinfo->testinfo_len = 0;
1611 drvinfo->regdump_len = 0;
1612 drvinfo->eedump_len = 0;
1613}
1614
1615static u32 ql_get_msglevel(struct net_device *ndev)
1616{
1617 struct ql3_adapter *qdev = netdev_priv(ndev);
1618 return qdev->msg_enable;
1619}
1620
1621static void ql_set_msglevel(struct net_device *ndev, u32 value)
1622{
1623 struct ql3_adapter *qdev = netdev_priv(ndev);
1624 qdev->msg_enable = value;
1625}
1626
7282d491 1627static const struct ethtool_ops ql3xxx_ethtool_ops = {
5a4faa87
RM		 1628 .get_settings = ql_get_settings,
1629 .get_drvinfo = ql_get_drvinfo,
1630 .get_perm_addr = ethtool_op_get_perm_addr,
1631 .get_link = ethtool_op_get_link,
1632 .get_msglevel = ql_get_msglevel,
1633 .set_msglevel = ql_set_msglevel,
1634};
1635
1636static int ql_populate_free_queue(struct ql3_adapter *qdev)
1637{
1638 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
0f8ab89e
BL		 1639 dma_addr_t map;
1640 int err;
5a4faa87
RM		 1641
1642 while (lrg_buf_cb) {
1643 if (!lrg_buf_cb->skb) {
cd238faa
BL		 1644 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1645 qdev->lrg_buffer_len);
5a4faa87
RM		 1646 if (unlikely(!lrg_buf_cb->skb)) {
1647 printk(KERN_DEBUG PFX
cd238faa 1648 "%s: Failed netdev_alloc_skb().\n",
5a4faa87
RM		 1649 qdev->ndev->name);
1650 break;
1651 } else {
1652 /*
1653 * We save some space to copy the ethhdr from
1654 * first buffer
1655 */
1656 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1657 map = pci_map_single(qdev->pdev,
1658 lrg_buf_cb->skb->data,
1659 qdev->lrg_buffer_len -
1660 QL_HEADER_SPACE,
1661 PCI_DMA_FROMDEVICE);
0f8ab89e
BL		 1662
1663 err = pci_dma_mapping_error(map);
1664 if(err) {
1665 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
1666 qdev->ndev->name, err);
1667 dev_kfree_skb(lrg_buf_cb->skb);
1668 lrg_buf_cb->skb = NULL;
1669 break;
1670 }
1671
1672
5a4faa87
RM		 1673 lrg_buf_cb->buf_phy_addr_low =
1674 cpu_to_le32(LS_64BITS(map));
1675 lrg_buf_cb->buf_phy_addr_high =
1676 cpu_to_le32(MS_64BITS(map));
1677 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1678 pci_unmap_len_set(lrg_buf_cb, maplen,
1679 qdev->lrg_buffer_len -
1680 QL_HEADER_SPACE);
1681 --qdev->lrg_buf_skb_check;
1682 if (!qdev->lrg_buf_skb_check)
1683 return 1;
1684 }
1685 }
1686 lrg_buf_cb = lrg_buf_cb->next;
1687 }
1688 return 0;
1689}
1690
1691/*
1692 * Caller holds hw_lock.
1693 */
1694static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1695{
1696 struct bufq_addr_element *lrg_buf_q_ele;
1697 int i;
1698 struct ql_rcv_buf_cb *lrg_buf_cb;
1699 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1700
1701 if ((qdev->lrg_buf_free_count >= 8)
1702 && (qdev->lrg_buf_release_cnt >= 16)) {
1703
1704 if (qdev->lrg_buf_skb_check)
1705 if (!ql_populate_free_queue(qdev))
1706 return;
1707
1708 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1709
1710 while ((qdev->lrg_buf_release_cnt >= 16)
1711 && (qdev->lrg_buf_free_count >= 8)) {
1712
1713 for (i = 0; i < 8; i++) {
1714 lrg_buf_cb =
1715 ql_get_from_lrg_buf_free_list(qdev);
1716 lrg_buf_q_ele->addr_high =
1717 lrg_buf_cb->buf_phy_addr_high;
1718 lrg_buf_q_ele->addr_low =
1719 lrg_buf_cb->buf_phy_addr_low;
1720 lrg_buf_q_ele++;
1721
1722 qdev->lrg_buf_release_cnt--;
1723 }
1724
1725 qdev->lrg_buf_q_producer_index++;
1726
1357bfcf 1727 if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
5a4faa87
RM		 1728 qdev->lrg_buf_q_producer_index = 0;
1729
1730 if (qdev->lrg_buf_q_producer_index ==
1357bfcf 1731 (qdev->num_lbufq_entries - 1)) {
5a4faa87
RM		 1732 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1733 }
1734 }
1735
1736 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1737
1738 ql_write_common_reg(qdev,
ee111d11 1739 &port_regs->CommonRegs.
5a4faa87
RM		 1740 rxLargeQProducerIndex,
1741 qdev->lrg_buf_q_producer_index);
1742 }
1743}
1744
1745static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1746 struct ob_mac_iocb_rsp *mac_rsp)
1747{
1748 struct ql_tx_buf_cb *tx_cb;
bd36b0ac 1749 int i;
e8f4df24 1750 int retval = 0;
5a4faa87 1751
e8f4df24
BL		 1752 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1753 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
1754 }
1755
5a4faa87 1756 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
e8f4df24
BL		 1757
1758 /* Check the transmit response flags for any errors */
1759 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1760 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
1761
1762 qdev->stats.tx_errors++;
1763 retval = -EIO;
1764 goto frame_not_sent;
1765 }
1766
1767 if(tx_cb->seg_count == 0) {
1768 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
1769
1770 qdev->stats.tx_errors++;
1771 retval = -EIO;
1772 goto invalid_seg_count;
1773 }
1774
5a4faa87 1775 pci_unmap_single(qdev->pdev,
bd36b0ac
RM		 1776 pci_unmap_addr(&tx_cb->map[0], mapaddr),
1777 pci_unmap_len(&tx_cb->map[0], maplen),
1778 PCI_DMA_TODEVICE);
1779 tx_cb->seg_count--;
1780 if (tx_cb->seg_count) {
1781 for (i = 1; i < tx_cb->seg_count; i++) {
1782 pci_unmap_page(qdev->pdev,
1783 pci_unmap_addr(&tx_cb->map[i],
1784 mapaddr),
1785 pci_unmap_len(&tx_cb->map[i], maplen),
1786 PCI_DMA_TODEVICE);
1787 }
1788 }
5a4faa87
RM		 1789 qdev->stats.tx_packets++;
1790 qdev->stats.tx_bytes += tx_cb->skb->len;
e8f4df24
BL		 1791
1792frame_not_sent:
bd36b0ac 1793 dev_kfree_skb_irq(tx_cb->skb);
5a4faa87 1794 tx_cb->skb = NULL;
e8f4df24
BL		 1795
1796invalid_seg_count:
5a4faa87
RM		 1797 atomic_inc(&qdev->tx_count);
1798}
1799
97916330
RM		 1800void ql_get_sbuf(struct ql3_adapter *qdev)
1801{
1802 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1803 qdev->small_buf_index = 0;
1804 qdev->small_buf_release_cnt++;
1805}
1806
1807struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1808{
1809 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1810 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1811 qdev->lrg_buf_release_cnt++;
1812 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1813 qdev->lrg_buf_index = 0;
1814 return(lrg_buf_cb);
1815}
1816
bd36b0ac
RM		 1817/*
1818 * The difference between 3022 and 3032 for inbound completions:
1819 * 3022 uses two buffers per completion. The first buffer contains
1820 * (some) header info, the second the remainder of the headers plus
1821 * the data. For this chip we reserve some space at the top of the
1822 * receive buffer so that the header info in buffer one can be
1823 * prepended to the buffer two. Buffer two is the sent up while
1824 * buffer one is returned to the hardware to be reused.
1825 * 3032 receives all of it's data and headers in one buffer for a
1826 * simpler process. 3032 also supports checksum verification as
1827 * can be seen in ql_process_macip_rx_intr().
1828 */
5a4faa87
RM		 1829static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1830 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
1831{
5a4faa87
RM		 1832 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1833 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
5a4faa87
RM		 1834 struct sk_buff *skb;
1835 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
1836
1837 /*
1838 * Get the inbound address list (small buffer).
1839 */
97916330 1840 ql_get_sbuf(qdev);
5a4faa87 1841
97916330
RM		 1842 if (qdev->device_id == QL3022_DEVICE_ID)
1843 lrg_buf_cb1 = ql_get_lbuf(qdev);
5a4faa87
RM		 1844
1845 /* start of second buffer */
97916330 1846 lrg_buf_cb2 = ql_get_lbuf(qdev);
5a4faa87
RM		 1847 skb = lrg_buf_cb2->skb;
1848
1849 qdev->stats.rx_packets++;
1850 qdev->stats.rx_bytes += length;
1851
1852 skb_put(skb, length);
1853 pci_unmap_single(qdev->pdev,
1854 pci_unmap_addr(lrg_buf_cb2, mapaddr),
1855 pci_unmap_len(lrg_buf_cb2, maplen),
1856 PCI_DMA_FROMDEVICE);
1857 prefetch(skb->data);
1858 skb->dev = qdev->ndev;
1859 skb->ip_summed = CHECKSUM_NONE;
1860 skb->protocol = eth_type_trans(skb, qdev->ndev);
1861
1862 netif_receive_skb(skb);
1863 qdev->ndev->last_rx = jiffies;
1864 lrg_buf_cb2->skb = NULL;
1865
bd36b0ac
RM		 1866 if (qdev->device_id == QL3022_DEVICE_ID)
1867 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
5a4faa87
RM		 1868 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1869}
1870
1871static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
1872 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
1873{
5a4faa87
RM		 1874 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1875 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
bd36b0ac 1876 struct sk_buff *skb1 = NULL, *skb2;
5a4faa87
RM		 1877 struct net_device *ndev = qdev->ndev;
1878 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
1879 u16 size = 0;
1880
1881 /*
1882 * Get the inbound address list (small buffer).
1883 */
1884
97916330 1885 ql_get_sbuf(qdev);
5a4faa87 1886
bd36b0ac
RM		 1887 if (qdev->device_id == QL3022_DEVICE_ID) {
1888 /* start of first buffer on 3022 */
97916330 1889 lrg_buf_cb1 = ql_get_lbuf(qdev);
bd36b0ac 1890 skb1 = lrg_buf_cb1->skb;
bd36b0ac
RM		 1891 size = ETH_HLEN;
1892 if (*((u16 *) skb1->data) != 0xFFFF)
1893 size += VLAN_ETH_HLEN - ETH_HLEN;
1894 }
5a4faa87
RM		 1895
1896 /* start of second buffer */
97916330 1897 lrg_buf_cb2 = ql_get_lbuf(qdev);
5a4faa87 1898 skb2 = lrg_buf_cb2->skb;
5a4faa87 1899
5a4faa87
RM		 1900 skb_put(skb2, length); /* Just the second buffer length here. */
1901 pci_unmap_single(qdev->pdev,
1902 pci_unmap_addr(lrg_buf_cb2, mapaddr),
1903 pci_unmap_len(lrg_buf_cb2, maplen),
1904 PCI_DMA_FROMDEVICE);
1905 prefetch(skb2->data);
1906
5a4faa87 1907 skb2->ip_summed = CHECKSUM_NONE;
bd36b0ac
RM		 1908 if (qdev->device_id == QL3022_DEVICE_ID) {
1909 /*
1910 * Copy the ethhdr from first buffer to second. This
1911 * is necessary for 3022 IP completions.
1912 */
1913 memcpy(skb_push(skb2, size), skb1->data + VLAN_ID_LEN, size);
1914 } else {
1915 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
1916 if (checksum &
1917 (IB_IP_IOCB_RSP_3032_ICE |
1918 IB_IP_IOCB_RSP_3032_CE |
1919 IB_IP_IOCB_RSP_3032_NUC)) {
1920 printk(KERN_ERR
1921 "%s: Bad checksum for this %s packet, checksum = %x.\n",
1922 __func__,
1923 ((checksum &
1924 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
1925 "UDP"),checksum);
1926 } else if (checksum & IB_IP_IOCB_RSP_3032_TCP) {
1927 skb2->ip_summed = CHECKSUM_UNNECESSARY;
1928 }
1929 }
1930 skb2->dev = qdev->ndev;
5a4faa87
RM		 1931 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
1932
1933 netif_receive_skb(skb2);
bd36b0ac
RM		 1934 qdev->stats.rx_packets++;
1935 qdev->stats.rx_bytes += length;
5a4faa87
RM		 1936 ndev->last_rx = jiffies;
1937 lrg_buf_cb2->skb = NULL;
1938
bd36b0ac
RM		 1939 if (qdev->device_id == QL3022_DEVICE_ID)
1940 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
5a4faa87
RM		 1941 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1942}
1943
1944static int ql_tx_rx_clean(struct ql3_adapter *qdev,
1945 int *tx_cleaned, int *rx_cleaned, int work_to_do)
1946{
1947 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1948 struct net_rsp_iocb *net_rsp;
1949 struct net_device *ndev = qdev->ndev;
1950 unsigned long hw_flags;
63b66d12 1951 int work_done = 0;
5a4faa87 1952
e8f4df24
BL		 1953 u32 rsp_producer_index = le32_to_cpu(*(qdev->prsp_producer_index));
1954
5a4faa87 1955 /* While there are entries in the completion queue. */
e8f4df24 1956 while ((rsp_producer_index !=
63b66d12 1957 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
5a4faa87
RM		 1958
1959 net_rsp = qdev->rsp_current;
1960 switch (net_rsp->opcode) {
1961
1962 case OPCODE_OB_MAC_IOCB_FN0:
1963 case OPCODE_OB_MAC_IOCB_FN2:
1964 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
1965 net_rsp);
1966 (*tx_cleaned)++;
1967 break;
1968
1969 case OPCODE_IB_MAC_IOCB:
bd36b0ac 1970 case OPCODE_IB_3032_MAC_IOCB:
5a4faa87
RM		 1971 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
1972 net_rsp);
1973 (*rx_cleaned)++;
1974 break;
1975
1976 case OPCODE_IB_IP_IOCB:
bd36b0ac 1977 case OPCODE_IB_3032_IP_IOCB:
5a4faa87
RM		 1978 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
1979 net_rsp);
1980 (*rx_cleaned)++;
1981 break;
1982 default:
1983 {
1984 u32 *tmp = (u32 *) net_rsp;
1985 printk(KERN_ERR PFX
1986 "%s: Hit default case, not "
1987 "handled!\n"
1988 " dropping the packet, opcode = "
1989 "%x.\n",
1990 ndev->name, net_rsp->opcode);
1991 printk(KERN_ERR PFX
1992 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
1993 (unsigned long int)tmp[0],
1994 (unsigned long int)tmp[1],
1995 (unsigned long int)tmp[2],
1996 (unsigned long int)tmp[3]);
1997 }
1998 }
1999
2000 qdev->rsp_consumer_index++;
2001
2002 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2003 qdev->rsp_consumer_index = 0;
2004 qdev->rsp_current = qdev->rsp_q_virt_addr;
2005 } else {
2006 qdev->rsp_current++;
2007 }
63b66d12
RM		 2008
2009 work_done = *tx_cleaned + *rx_cleaned;
5a4faa87
RM		 2010 }
2011
63b66d12
RM		 2012 if(work_done) {
2013 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
5a4faa87 2014
63b66d12 2015 ql_update_lrg_bufq_prod_index(qdev);
5a4faa87 2016
63b66d12
RM		 2017 if (qdev->small_buf_release_cnt >= 16) {
2018 while (qdev->small_buf_release_cnt >= 16) {
2019 qdev->small_buf_q_producer_index++;
5a4faa87 2020
63b66d12
RM		 2021 if (qdev->small_buf_q_producer_index ==
2022 NUM_SBUFQ_ENTRIES)
2023 qdev->small_buf_q_producer_index = 0;
2024 qdev->small_buf_release_cnt -= 8;
2025 }
5a4faa87 2026
63b66d12
RM		 2027 wmb();
2028 ql_write_common_reg(qdev,
2029 &port_regs->CommonRegs.
2030 rxSmallQProducerIndex,
2031 qdev->small_buf_q_producer_index);
5a4faa87 2032
63b66d12 2033 }
5a4faa87 2034
63b66d12 2035 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 2036 }
2037
2038 return *tx_cleaned + *rx_cleaned;
2039}
2040
2041static int ql_poll(struct net_device *ndev, int *budget)
2042{
2043 struct ql3_adapter *qdev = netdev_priv(ndev);
2044 int work_to_do = min(*budget, ndev->quota);
2045 int rx_cleaned = 0, tx_cleaned = 0;
63b66d12
RM		 2046 unsigned long hw_flags;
2047 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
5a4faa87
RM		 2048
2049 if (!netif_carrier_ok(ndev))
2050 goto quit_polling;
2051
2052 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2053 *budget -= rx_cleaned;
2054 ndev->quota -= rx_cleaned;
2055
e8f4df24
BL		 2056 if( tx_cleaned + rx_cleaned != work_to_do ||
2057 !netif_running(ndev)) {
5a4faa87
RM		 2058quit_polling:
2059 netif_rx_complete(ndev);
63b66d12
RM		 2060
2061 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2062 ql_write_common_reg(qdev,
2063 &port_regs->CommonRegs.rspQConsumerIndex,
2064 qdev->rsp_consumer_index);
2065 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2066
5a4faa87
RM		 2067 ql_enable_interrupts(qdev);
2068 return 0;
2069 }
2070 return 1;
2071}
2072
7d12e780 2073static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
5a4faa87
RM		 2074{
2075
2076 struct net_device *ndev = dev_id;
2077 struct ql3_adapter *qdev = netdev_priv(ndev);
2078 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2079 u32 value;
2080 int handled = 1;
2081 u32 var;
2082
2083 port_regs = qdev->mem_map_registers;
2084
2085 value =
2086 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2087
2088 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2089 spin_lock(&qdev->adapter_lock);
2090 netif_stop_queue(qdev->ndev);
2091 netif_carrier_off(qdev->ndev);
2092 ql_disable_interrupts(qdev);
2093 qdev->port_link_state = LS_DOWN;
2094 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2095
2096 if (value & ISP_CONTROL_FE) {
2097 /*
2098 * Chip Fatal Error.
2099 */
2100 var =
2101 ql_read_page0_reg_l(qdev,
2102 &port_regs->PortFatalErrStatus);
2103 printk(KERN_WARNING PFX
2104 "%s: Resetting chip. PortFatalErrStatus "
2105 "register = 0x%x\n", ndev->name, var);
2106 set_bit(QL_RESET_START,&qdev->flags) ;
2107 } else {
2108 /*
2109 * Soft Reset Requested.
2110 */
2111 set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2112 printk(KERN_ERR PFX
2113 "%s: Another function issued a reset to the "
2114 "chip. ISR value = %x.\n", ndev->name, value);
2115 }
c4028958 2116 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
5a4faa87
RM		 2117 spin_unlock(&qdev->adapter_lock);
2118 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
e8f4df24 2119 ql_disable_interrupts(qdev);
63b66d12 2120 if (likely(netif_rx_schedule_prep(ndev))) {
5a4faa87 2121 __netif_rx_schedule(ndev);
63b66d12 2122 }
5a4faa87
RM		 2123 } else {
2124 return IRQ_NONE;
2125 }
2126
2127 return IRQ_RETVAL(handled);
2128}
2129
bd36b0ac
RM		 2130/*
2131 * Get the total number of segments needed for the
2132 * given number of fragments. This is necessary because
2133 * outbound address lists (OAL) will be used when more than
2134 * two frags are given. Each address list has 5 addr/len
2135 * pairs. The 5th pair in each AOL is used to point to
2136 * the next AOL if more frags are coming.
2137 * That is why the frags:segment count ratio is not linear.
2138 */
e8f4df24
BL		 2139static int ql_get_seg_count(struct ql3_adapter *qdev,
2140 unsigned short frags)
bd36b0ac 2141{
e8f4df24
BL		 2142 if (qdev->device_id == QL3022_DEVICE_ID)
2143 return 1;
2144
bd36b0ac
RM		 2145 switch(frags) {
2146 case 0: return 1; /* just the skb->data seg */
2147 case 1: return 2; /* skb->data + 1 frag */
2148 case 2: return 3; /* skb->data + 2 frags */
2149 case 3: return 5; /* skb->data + 1 frag + 1 AOL containting 2 frags */
2150 case 4: return 6;
2151 case 5: return 7;
2152 case 6: return 8;
2153 case 7: return 10;
2154 case 8: return 11;
2155 case 9: return 12;
2156 case 10: return 13;
2157 case 11: return 15;
2158 case 12: return 16;
2159 case 13: return 17;
2160 case 14: return 18;
2161 case 15: return 20;
2162 case 16: return 21;
2163 case 17: return 22;
2164 case 18: return 23;
2165 }
2166 return -1;
2167}
2168
2169static void ql_hw_csum_setup(struct sk_buff *skb,
2170 struct ob_mac_iocb_req *mac_iocb_ptr)
2171{
2172 struct ethhdr *eth;
2173 struct iphdr *ip = NULL;
2174 u8 offset = ETH_HLEN;
2175
2176 eth = (struct ethhdr *)(skb->data);
2177
2178 if (eth->h_proto == __constant_htons(ETH_P_IP)) {
2179 ip = (struct iphdr *)&skb->data[ETH_HLEN];
2180 } else if (eth->h_proto == htons(ETH_P_8021Q) &&
2181 ((struct vlan_ethhdr *)skb->data)->
2182 h_vlan_encapsulated_proto == __constant_htons(ETH_P_IP)) {
2183 ip = (struct iphdr *)&skb->data[VLAN_ETH_HLEN];
2184 offset = VLAN_ETH_HLEN;
2185 }
2186
2187 if (ip) {
2188 if (ip->protocol == IPPROTO_TCP) {
3e71f6dd
RM		 2189 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2190 OB_3032MAC_IOCB_REQ_IC;
bd36b0ac
RM		 2191 mac_iocb_ptr->ip_hdr_off = offset;
2192 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2193 } else if (ip->protocol == IPPROTO_UDP) {
3e71f6dd
RM		 2194 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2195 OB_3032MAC_IOCB_REQ_IC;
bd36b0ac
RM		 2196 mac_iocb_ptr->ip_hdr_off = offset;
2197 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2198 }
2199 }
2200}
2201
2202/*
3e71f6dd
RM		 2203 * Map the buffers for this transmit. This will return
2204 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
bd36b0ac 2205 */
3e71f6dd
RM		 2206static int ql_send_map(struct ql3_adapter *qdev,
2207 struct ob_mac_iocb_req *mac_iocb_ptr,
2208 struct ql_tx_buf_cb *tx_cb,
2209 struct sk_buff *skb)
5a4faa87 2210{
bd36b0ac
RM		 2211 struct oal *oal;
2212 struct oal_entry *oal_entry;
63f77926 2213 int len = skb_headlen(skb);
0f8ab89e
BL		 2214 dma_addr_t map;
2215 int err;
2216 int completed_segs, i;
bd36b0ac
RM		 2217 int seg_cnt, seg = 0;
2218 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
5a4faa87 2219
e8f4df24
BL		 2220 seg_cnt = tx_cb->seg_count = ql_get_seg_count(qdev,
2221 (skb_shinfo(skb)->nr_frags));
bd36b0ac
RM		 2222 if(seg_cnt == -1) {
2223 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
3e71f6dd 2224 return NETDEV_TX_BUSY;
bd36b0ac 2225 }
3e71f6dd
RM		 2226 /*
2227 * Map the skb buffer first.
2228 */
bd36b0ac 2229 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
0f8ab89e
BL		 2230
2231 err = pci_dma_mapping_error(map);
2232 if(err) {
2233 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2234 qdev->ndev->name, err);
2235
2236 return NETDEV_TX_BUSY;
2237 }
2238
bd36b0ac
RM		 2239 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2240 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2241 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2242 oal_entry->len = cpu_to_le32(len);
2243 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2244 pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2245 seg++;
2246
e8f4df24 2247 if (seg_cnt == 1) {
bd36b0ac
RM		 2248 /* Terminate the last segment. */
2249 oal_entry->len =
2250 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2251 } else {
bd36b0ac 2252 oal = tx_cb->oal;
0f8ab89e
BL		 2253 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2254 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
bd36b0ac
RM		 2255 oal_entry++;
2256 if ((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2257 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2258 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2259 (seg == 17 && seg_cnt > 18)) {
2260 /* Continuation entry points to outbound address list. */
2261 map = pci_map_single(qdev->pdev, oal,
2262 sizeof(struct oal),
2263 PCI_DMA_TODEVICE);
0f8ab89e
BL		 2264
2265 err = pci_dma_mapping_error(map);
2266 if(err) {
2267
2268 printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
2269 qdev->ndev->name, err);
2270 goto map_error;
2271 }
2272
bd36b0ac
RM		 2273 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2274 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2275 oal_entry->len =
2276 cpu_to_le32(sizeof(struct oal) |
2277 OAL_CONT_ENTRY);
2278 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2279 map);
2280 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2281 len);
2282 oal_entry = (struct oal_entry *)oal;
2283 oal++;
2284 seg++;
2285 }
5a4faa87 2286
bd36b0ac
RM		 2287 map =
2288 pci_map_page(qdev->pdev, frag->page,
2289 frag->page_offset, frag->size,
2290 PCI_DMA_TODEVICE);
0f8ab89e
BL		 2291
2292 err = pci_dma_mapping_error(map);
2293 if(err) {
2294 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
2295 qdev->ndev->name, err);
2296 goto map_error;
2297 }
2298
bd36b0ac
RM		 2299 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2300 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2301 oal_entry->len = cpu_to_le32(frag->size);
2302 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2303 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2304 frag->size);
2305 }
2306 /* Terminate the last segment. */
2307 oal_entry->len =
2308 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2309 }
0f8ab89e 2310
3e71f6dd 2311 return NETDEV_TX_OK;
0f8ab89e
BL		 2312
2313map_error:
2314 /* A PCI mapping failed and now we will need to back out
2315 * We need to traverse through the oal's and associated pages which
2316 * have been mapped and now we must unmap them to clean up properly
2317 */
2318
2319 seg = 1;
2320 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2321 oal = tx_cb->oal;
2322 for (i=0; i<completed_segs; i++,seg++) {
2323 oal_entry++;
2324
2325 if((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2326 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2327 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2328 (seg == 17 && seg_cnt > 18)) {
2329 pci_unmap_single(qdev->pdev,
2330 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2331 pci_unmap_len(&tx_cb->map[seg], maplen),
2332 PCI_DMA_TODEVICE);
2333 oal++;
2334 seg++;
2335 }
2336
2337 pci_unmap_page(qdev->pdev,
2338 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2339 pci_unmap_len(&tx_cb->map[seg], maplen),
2340 PCI_DMA_TODEVICE);
2341 }
2342
2343 pci_unmap_single(qdev->pdev,
2344 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2345 pci_unmap_addr(&tx_cb->map[0], maplen),
2346 PCI_DMA_TODEVICE);
2347
2348 return NETDEV_TX_BUSY;
2349
3e71f6dd
RM		 2350}
2351
2352/*
2353 * The difference between 3022 and 3032 sends:
2354 * 3022 only supports a simple single segment transmission.
2355 * 3032 supports checksumming and scatter/gather lists (fragments).
2356 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2357 * in the IOCB plus a chain of outbound address lists (OAL) that
2358 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2359 * will used to point to an OAL when more ALP entries are required.
2360 * The IOCB is always the top of the chain followed by one or more
2361 * OALs (when necessary).
2362 */
2363static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2364{
2365 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2366 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2367 struct ql_tx_buf_cb *tx_cb;
2368 u32 tot_len = skb->len;
2369 struct ob_mac_iocb_req *mac_iocb_ptr;
2370
2371 if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
3e71f6dd
RM		 2372 return NETDEV_TX_BUSY;
2373 }
2374
2375 tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
e8f4df24
BL		 2376 if((tx_cb->seg_count = ql_get_seg_count(qdev,
2377 (skb_shinfo(skb)->nr_frags))) == -1) {
3e71f6dd
RM		 2378 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2379 return NETDEV_TX_OK;
2380 }
2381
2382 mac_iocb_ptr = tx_cb->queue_entry;
d8a759ff 2383 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
3e71f6dd
RM		 2384 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2385 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2386 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2387 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2388 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2389 tx_cb->skb = skb;
e8f4df24
BL		 2390 if (qdev->device_id == QL3032_DEVICE_ID &&
2391 skb->ip_summed == CHECKSUM_PARTIAL)
3e71f6dd
RM		 2392 ql_hw_csum_setup(skb, mac_iocb_ptr);
2393
2394 if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2395 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2396 return NETDEV_TX_BUSY;
2397 }
2398
bd36b0ac 2399 wmb();
5a4faa87
RM		 2400 qdev->req_producer_index++;
2401 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2402 qdev->req_producer_index = 0;
2403 wmb();
2404 ql_write_common_reg_l(qdev,
ee111d11 2405 &port_regs->CommonRegs.reqQProducerIndex,
5a4faa87
RM		 2406 qdev->req_producer_index);
2407
2408 ndev->trans_start = jiffies;
2409 if (netif_msg_tx_queued(qdev))
2410 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2411 ndev->name, qdev->req_producer_index, skb->len);
2412
bd36b0ac 2413 atomic_dec(&qdev->tx_count);
5a4faa87
RM		 2414 return NETDEV_TX_OK;
2415}
bd36b0ac 2416
5a4faa87
RM		 2417static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2418{
2419 qdev->req_q_size =
2420 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2421
2422 qdev->req_q_virt_addr =
2423 pci_alloc_consistent(qdev->pdev,
2424 (size_t) qdev->req_q_size,
2425 &qdev->req_q_phy_addr);
2426
2427 if ((qdev->req_q_virt_addr == NULL) ||
2428 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2429 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2430 qdev->ndev->name);
2431 return -ENOMEM;
2432 }
2433
2434 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2435
2436 qdev->rsp_q_virt_addr =
2437 pci_alloc_consistent(qdev->pdev,
2438 (size_t) qdev->rsp_q_size,
2439 &qdev->rsp_q_phy_addr);
2440
2441 if ((qdev->rsp_q_virt_addr == NULL) ||
2442 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2443 printk(KERN_ERR PFX
2444 "%s: rspQ allocation failed\n",
2445 qdev->ndev->name);
2446 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2447 qdev->req_q_virt_addr,
2448 qdev->req_q_phy_addr);
2449 return -ENOMEM;
2450 }
2451
2452 set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2453
2454 return 0;
2455}
2456
2457static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2458{
2459 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2460 printk(KERN_INFO PFX
2461 "%s: Already done.\n", qdev->ndev->name);
2462 return;
2463 }
2464
2465 pci_free_consistent(qdev->pdev,
2466 qdev->req_q_size,
2467 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2468
2469 qdev->req_q_virt_addr = NULL;
2470
2471 pci_free_consistent(qdev->pdev,
2472 qdev->rsp_q_size,
2473 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2474
2475 qdev->rsp_q_virt_addr = NULL;
2476
2477 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2478}
2479
2480static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2481{
2482 /* Create Large Buffer Queue */
2483 qdev->lrg_buf_q_size =
1357bfcf 2484 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
5a4faa87
RM		 2485 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2486 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2487 else
2488 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2489
1357bfcf
RM		 2490 qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2491 if (qdev->lrg_buf == NULL) {
2492 printk(KERN_ERR PFX
2493 "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2494 return -ENOMEM;
2495 }
2496
5a4faa87
RM		 2497 qdev->lrg_buf_q_alloc_virt_addr =
2498 pci_alloc_consistent(qdev->pdev,
2499 qdev->lrg_buf_q_alloc_size,
2500 &qdev->lrg_buf_q_alloc_phy_addr);
2501
2502 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2503 printk(KERN_ERR PFX
2504 "%s: lBufQ failed\n", qdev->ndev->name);
2505 return -ENOMEM;
2506 }
2507 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2508 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2509
2510 /* Create Small Buffer Queue */
2511 qdev->small_buf_q_size =
2512 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2513 if (qdev->small_buf_q_size < PAGE_SIZE)
2514 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2515 else
2516 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2517
2518 qdev->small_buf_q_alloc_virt_addr =
2519 pci_alloc_consistent(qdev->pdev,
2520 qdev->small_buf_q_alloc_size,
2521 &qdev->small_buf_q_alloc_phy_addr);
2522
2523 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2524 printk(KERN_ERR PFX
2525 "%s: Small Buffer Queue allocation failed.\n",
2526 qdev->ndev->name);
2527 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2528 qdev->lrg_buf_q_alloc_virt_addr,
2529 qdev->lrg_buf_q_alloc_phy_addr);
2530 return -ENOMEM;
2531 }
2532
2533 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2534 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2535 set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2536 return 0;
2537}
2538
2539static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2540{
2541 if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2542 printk(KERN_INFO PFX
2543 "%s: Already done.\n", qdev->ndev->name);
2544 return;
2545 }
1357bfcf 2546 if(qdev->lrg_buf) kfree(qdev->lrg_buf);
5a4faa87
RM		 2547 pci_free_consistent(qdev->pdev,
2548 qdev->lrg_buf_q_alloc_size,
2549 qdev->lrg_buf_q_alloc_virt_addr,
2550 qdev->lrg_buf_q_alloc_phy_addr);
2551
2552 qdev->lrg_buf_q_virt_addr = NULL;
2553
2554 pci_free_consistent(qdev->pdev,
2555 qdev->small_buf_q_alloc_size,
2556 qdev->small_buf_q_alloc_virt_addr,
2557 qdev->small_buf_q_alloc_phy_addr);
2558
2559 qdev->small_buf_q_virt_addr = NULL;
2560
2561 clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2562}
2563
2564static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2565{
2566 int i;
2567 struct bufq_addr_element *small_buf_q_entry;
2568
2569 /* Currently we allocate on one of memory and use it for smallbuffers */
2570 qdev->small_buf_total_size =
2571 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2572 QL_SMALL_BUFFER_SIZE);
2573
2574 qdev->small_buf_virt_addr =
2575 pci_alloc_consistent(qdev->pdev,
2576 qdev->small_buf_total_size,
2577 &qdev->small_buf_phy_addr);
2578
2579 if (qdev->small_buf_virt_addr == NULL) {
2580 printk(KERN_ERR PFX
2581 "%s: Failed to get small buffer memory.\n",
2582 qdev->ndev->name);
2583 return -ENOMEM;
2584 }
2585
2586 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2587 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2588
2589 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2590
5a4faa87
RM		 2591 /* Initialize the small buffer queue. */
2592 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2593 small_buf_q_entry->addr_high =
2594 cpu_to_le32(qdev->small_buf_phy_addr_high);
2595 small_buf_q_entry->addr_low =
2596 cpu_to_le32(qdev->small_buf_phy_addr_low +
2597 (i * QL_SMALL_BUFFER_SIZE));
2598 small_buf_q_entry++;
2599 }
2600 qdev->small_buf_index = 0;
2601 set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2602 return 0;
2603}
2604
2605static void ql_free_small_buffers(struct ql3_adapter *qdev)
2606{
2607 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2608 printk(KERN_INFO PFX
2609 "%s: Already done.\n", qdev->ndev->name);
2610 return;
2611 }
2612 if (qdev->small_buf_virt_addr != NULL) {
2613 pci_free_consistent(qdev->pdev,
2614 qdev->small_buf_total_size,
2615 qdev->small_buf_virt_addr,
2616 qdev->small_buf_phy_addr);
2617
2618 qdev->small_buf_virt_addr = NULL;
2619 }
2620}
2621
2622static void ql_free_large_buffers(struct ql3_adapter *qdev)
2623{
2624 int i = 0;
2625 struct ql_rcv_buf_cb *lrg_buf_cb;
2626
1357bfcf 2627 for (i = 0; i < qdev->num_large_buffers; i++) {
5a4faa87
RM		 2628 lrg_buf_cb = &qdev->lrg_buf[i];
2629 if (lrg_buf_cb->skb) {
2630 dev_kfree_skb(lrg_buf_cb->skb);
2631 pci_unmap_single(qdev->pdev,
2632 pci_unmap_addr(lrg_buf_cb, mapaddr),
2633 pci_unmap_len(lrg_buf_cb, maplen),
2634 PCI_DMA_FROMDEVICE);
2635 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2636 } else {
2637 break;
2638 }
2639 }
2640}
2641
2642static void ql_init_large_buffers(struct ql3_adapter *qdev)
2643{
2644 int i;
2645 struct ql_rcv_buf_cb *lrg_buf_cb;
2646 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2647
1357bfcf 2648 for (i = 0; i < qdev->num_large_buffers; i++) {
5a4faa87
RM		 2649 lrg_buf_cb = &qdev->lrg_buf[i];
2650 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2651 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2652 buf_addr_ele++;
2653 }
2654 qdev->lrg_buf_index = 0;
2655 qdev->lrg_buf_skb_check = 0;
2656}
2657
2658static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2659{
2660 int i;
2661 struct ql_rcv_buf_cb *lrg_buf_cb;
2662 struct sk_buff *skb;
0f8ab89e
BL		 2663 dma_addr_t map;
2664 int err;
5a4faa87 2665
1357bfcf 2666 for (i = 0; i < qdev->num_large_buffers; i++) {
cd238faa
BL		 2667 skb = netdev_alloc_skb(qdev->ndev,
2668 qdev->lrg_buffer_len);
5a4faa87
RM		 2669 if (unlikely(!skb)) {
2670 /* Better luck next round */
2671 printk(KERN_ERR PFX
2672 "%s: large buff alloc failed, "
2673 "for %d bytes at index %d.\n",
2674 qdev->ndev->name,
2675 qdev->lrg_buffer_len * 2, i);
2676 ql_free_large_buffers(qdev);
2677 return -ENOMEM;
2678 } else {
2679
2680 lrg_buf_cb = &qdev->lrg_buf[i];
2681 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2682 lrg_buf_cb->index = i;
2683 lrg_buf_cb->skb = skb;
2684 /*
2685 * We save some space to copy the ethhdr from first
2686 * buffer
2687 */
2688 skb_reserve(skb, QL_HEADER_SPACE);
2689 map = pci_map_single(qdev->pdev,
2690 skb->data,
2691 qdev->lrg_buffer_len -
2692 QL_HEADER_SPACE,
2693 PCI_DMA_FROMDEVICE);
0f8ab89e
BL		 2694
2695 err = pci_dma_mapping_error(map);
2696 if(err) {
2697 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2698 qdev->ndev->name, err);
2699 ql_free_large_buffers(qdev);
2700 return -ENOMEM;
2701 }
2702
5a4faa87
RM		 2703 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2704 pci_unmap_len_set(lrg_buf_cb, maplen,
2705 qdev->lrg_buffer_len -
2706 QL_HEADER_SPACE);
2707 lrg_buf_cb->buf_phy_addr_low =
2708 cpu_to_le32(LS_64BITS(map));
2709 lrg_buf_cb->buf_phy_addr_high =
2710 cpu_to_le32(MS_64BITS(map));
2711 }
2712 }
2713 return 0;
2714}
2715
bd36b0ac
RM		 2716static void ql_free_send_free_list(struct ql3_adapter *qdev)
2717{
2718 struct ql_tx_buf_cb *tx_cb;
2719 int i;
2720
2721 tx_cb = &qdev->tx_buf[0];
2722 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2723 if (tx_cb->oal) {
2724 kfree(tx_cb->oal);
2725 tx_cb->oal = NULL;
2726 }
2727 tx_cb++;
2728 }
2729}
2730
2731static int ql_create_send_free_list(struct ql3_adapter *qdev)
5a4faa87
RM		 2732{
2733 struct ql_tx_buf_cb *tx_cb;
2734 int i;
2735 struct ob_mac_iocb_req *req_q_curr =
2736 qdev->req_q_virt_addr;
2737
2738 /* Create free list of transmit buffers */
2739 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
bd36b0ac 2740
5a4faa87
RM		 2741 tx_cb = &qdev->tx_buf[i];
2742 tx_cb->skb = NULL;
2743 tx_cb->queue_entry = req_q_curr;
2744 req_q_curr++;
bd36b0ac
RM		 2745 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2746 if (tx_cb->oal == NULL)
2747 return -1;
5a4faa87 2748 }
bd36b0ac 2749 return 0;
5a4faa87
RM		 2750}
2751
2752static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2753{
1357bfcf
RM		 2754 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2755 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
5a4faa87 2756 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
1357bfcf 2757 }
5a4faa87 2758 else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
1357bfcf
RM		 2759 /*
2760 * Bigger buffers, so less of them.
2761 */
2762 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
5a4faa87
RM		 2763 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2764 } else {
2765 printk(KERN_ERR PFX
2766 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
2767 qdev->ndev->name);
2768 return -ENOMEM;
2769 }
1357bfcf 2770 qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
5a4faa87
RM		 2771 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2772 qdev->max_frame_size =
2773 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2774
2775 /*
2776 * First allocate a page of shared memory and use it for shadow
2777 * locations of Network Request Queue Consumer Address Register and
2778 * Network Completion Queue Producer Index Register
2779 */
2780 qdev->shadow_reg_virt_addr =
2781 pci_alloc_consistent(qdev->pdev,
2782 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2783
2784 if (qdev->shadow_reg_virt_addr != NULL) {
2785 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2786 qdev->req_consumer_index_phy_addr_high =
2787 MS_64BITS(qdev->shadow_reg_phy_addr);
2788 qdev->req_consumer_index_phy_addr_low =
2789 LS_64BITS(qdev->shadow_reg_phy_addr);
2790
2791 qdev->prsp_producer_index =
2792 (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2793 qdev->rsp_producer_index_phy_addr_high =
2794 qdev->req_consumer_index_phy_addr_high;
2795 qdev->rsp_producer_index_phy_addr_low =
2796 qdev->req_consumer_index_phy_addr_low + 8;
2797 } else {
2798 printk(KERN_ERR PFX
2799 "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
2800 return -ENOMEM;
2801 }
2802
2803 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2804 printk(KERN_ERR PFX
2805 "%s: ql_alloc_net_req_rsp_queues failed.\n",
2806 qdev->ndev->name);
2807 goto err_req_rsp;
2808 }
2809
2810 if (ql_alloc_buffer_queues(qdev) != 0) {
2811 printk(KERN_ERR PFX
2812 "%s: ql_alloc_buffer_queues failed.\n",
2813 qdev->ndev->name);
2814 goto err_buffer_queues;
2815 }
2816
2817 if (ql_alloc_small_buffers(qdev) != 0) {
2818 printk(KERN_ERR PFX
2819 "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
2820 goto err_small_buffers;
2821 }
2822
2823 if (ql_alloc_large_buffers(qdev) != 0) {
2824 printk(KERN_ERR PFX
2825 "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
2826 goto err_small_buffers;
2827 }
2828
2829 /* Initialize the large buffer queue. */
2830 ql_init_large_buffers(qdev);
bd36b0ac
RM		 2831 if (ql_create_send_free_list(qdev))
2832 goto err_free_list;
5a4faa87
RM		 2833
2834 qdev->rsp_current = qdev->rsp_q_virt_addr;
2835
2836 return 0;
bd36b0ac
RM		 2837err_free_list:
2838 ql_free_send_free_list(qdev);
5a4faa87
RM		 2839err_small_buffers:
2840 ql_free_buffer_queues(qdev);
2841err_buffer_queues:
2842 ql_free_net_req_rsp_queues(qdev);
2843err_req_rsp:
2844 pci_free_consistent(qdev->pdev,
2845 PAGE_SIZE,
2846 qdev->shadow_reg_virt_addr,
2847 qdev->shadow_reg_phy_addr);
2848
2849 return -ENOMEM;
2850}
2851
2852static void ql_free_mem_resources(struct ql3_adapter *qdev)
2853{
bd36b0ac 2854 ql_free_send_free_list(qdev);
5a4faa87
RM		 2855 ql_free_large_buffers(qdev);
2856 ql_free_small_buffers(qdev);
2857 ql_free_buffer_queues(qdev);
2858 ql_free_net_req_rsp_queues(qdev);
2859 if (qdev->shadow_reg_virt_addr != NULL) {
2860 pci_free_consistent(qdev->pdev,
2861 PAGE_SIZE,
2862 qdev->shadow_reg_virt_addr,
2863 qdev->shadow_reg_phy_addr);
2864 qdev->shadow_reg_virt_addr = NULL;
2865 }
2866}
2867
2868static int ql_init_misc_registers(struct ql3_adapter *qdev)
2869{
ee111d11
AV		 2870 struct ql3xxx_local_ram_registers __iomem *local_ram =
2871 (void __iomem *)qdev->mem_map_registers;
5a4faa87
RM		 2872
2873 if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2874 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2875 2) << 4))
2876 return -1;
2877
2878 ql_write_page2_reg(qdev,
2879 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2880
2881 ql_write_page2_reg(qdev,
2882 &local_ram->maxBufletCount,
2883 qdev->nvram_data.bufletCount);
2884
2885 ql_write_page2_reg(qdev,
2886 &local_ram->freeBufletThresholdLow,
2887 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2888 (qdev->nvram_data.tcpWindowThreshold0));
2889
2890 ql_write_page2_reg(qdev,
2891 &local_ram->freeBufletThresholdHigh,
2892 qdev->nvram_data.tcpWindowThreshold50);
2893
2894 ql_write_page2_reg(qdev,
2895 &local_ram->ipHashTableBase,
2896 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2897 qdev->nvram_data.ipHashTableBaseLo);
2898 ql_write_page2_reg(qdev,
2899 &local_ram->ipHashTableCount,
2900 qdev->nvram_data.ipHashTableSize);
2901 ql_write_page2_reg(qdev,
2902 &local_ram->tcpHashTableBase,
2903 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2904 qdev->nvram_data.tcpHashTableBaseLo);
2905 ql_write_page2_reg(qdev,
2906 &local_ram->tcpHashTableCount,
2907 qdev->nvram_data.tcpHashTableSize);
2908 ql_write_page2_reg(qdev,
2909 &local_ram->ncbBase,
2910 (qdev->nvram_data.ncbTableBaseHi << 16) |
2911 qdev->nvram_data.ncbTableBaseLo);
2912 ql_write_page2_reg(qdev,
2913 &local_ram->maxNcbCount,
2914 qdev->nvram_data.ncbTableSize);
2915 ql_write_page2_reg(qdev,
2916 &local_ram->drbBase,
2917 (qdev->nvram_data.drbTableBaseHi << 16) |
2918 qdev->nvram_data.drbTableBaseLo);
2919 ql_write_page2_reg(qdev,
2920 &local_ram->maxDrbCount,
2921 qdev->nvram_data.drbTableSize);
2922 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2923 return 0;
2924}
2925
2926static int ql_adapter_initialize(struct ql3_adapter *qdev)
2927{
2928 u32 value;
2929 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2930 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
ee111d11 2931 (void __iomem *)port_regs;
5a4faa87
RM		 2932 u32 delay = 10;
2933 int status = 0;
2934
2935 if(ql_mii_setup(qdev))
2936 return -1;
2937
2938 /* Bring out PHY out of reset */
2939 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2940 (ISP_SERIAL_PORT_IF_WE |
2941 (ISP_SERIAL_PORT_IF_WE << 16)));
2942
2943 qdev->port_link_state = LS_DOWN;
2944 netif_carrier_off(qdev->ndev);
2945
2946 /* V2 chip fix for ARS-39168. */
2947 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2948 (ISP_SERIAL_PORT_IF_SDE |
2949 (ISP_SERIAL_PORT_IF_SDE << 16)));
2950
2951 /* Request Queue Registers */
2952 *((u32 *) (qdev->preq_consumer_index)) = 0;
2953 atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
2954 qdev->req_producer_index = 0;
2955
2956 ql_write_page1_reg(qdev,
2957 &hmem_regs->reqConsumerIndexAddrHigh,
2958 qdev->req_consumer_index_phy_addr_high);
2959 ql_write_page1_reg(qdev,
2960 &hmem_regs->reqConsumerIndexAddrLow,
2961 qdev->req_consumer_index_phy_addr_low);
2962
2963 ql_write_page1_reg(qdev,
2964 &hmem_regs->reqBaseAddrHigh,
2965 MS_64BITS(qdev->req_q_phy_addr));
2966 ql_write_page1_reg(qdev,
2967 &hmem_regs->reqBaseAddrLow,
2968 LS_64BITS(qdev->req_q_phy_addr));
2969 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
2970
2971 /* Response Queue Registers */
2972 *((u16 *) (qdev->prsp_producer_index)) = 0;
2973 qdev->rsp_consumer_index = 0;
2974 qdev->rsp_current = qdev->rsp_q_virt_addr;
2975
2976 ql_write_page1_reg(qdev,
2977 &hmem_regs->rspProducerIndexAddrHigh,
2978 qdev->rsp_producer_index_phy_addr_high);
2979
2980 ql_write_page1_reg(qdev,
2981 &hmem_regs->rspProducerIndexAddrLow,
2982 qdev->rsp_producer_index_phy_addr_low);
2983
2984 ql_write_page1_reg(qdev,
2985 &hmem_regs->rspBaseAddrHigh,
2986 MS_64BITS(qdev->rsp_q_phy_addr));
2987
2988 ql_write_page1_reg(qdev,
2989 &hmem_regs->rspBaseAddrLow,
2990 LS_64BITS(qdev->rsp_q_phy_addr));
2991
2992 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
2993
2994 /* Large Buffer Queue */
2995 ql_write_page1_reg(qdev,
2996 &hmem_regs->rxLargeQBaseAddrHigh,
2997 MS_64BITS(qdev->lrg_buf_q_phy_addr));
2998
2999 ql_write_page1_reg(qdev,
3000 &hmem_regs->rxLargeQBaseAddrLow,
3001 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3002
1357bfcf 3003 ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
5a4faa87
RM		 3004
3005 ql_write_page1_reg(qdev,
3006 &hmem_regs->rxLargeBufferLength,
3007 qdev->lrg_buffer_len);
3008
3009 /* Small Buffer Queue */
3010 ql_write_page1_reg(qdev,
3011 &hmem_regs->rxSmallQBaseAddrHigh,
3012 MS_64BITS(qdev->small_buf_q_phy_addr));
3013
3014 ql_write_page1_reg(qdev,
3015 &hmem_regs->rxSmallQBaseAddrLow,
3016 LS_64BITS(qdev->small_buf_q_phy_addr));
3017
3018 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3019 ql_write_page1_reg(qdev,
3020 &hmem_regs->rxSmallBufferLength,
3021 QL_SMALL_BUFFER_SIZE);
3022
3023 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3024 qdev->small_buf_release_cnt = 8;
1357bfcf 3025 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
5a4faa87
RM		 3026 qdev->lrg_buf_release_cnt = 8;
3027 qdev->lrg_buf_next_free =
3028 (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3029 qdev->small_buf_index = 0;
3030 qdev->lrg_buf_index = 0;
3031 qdev->lrg_buf_free_count = 0;
3032 qdev->lrg_buf_free_head = NULL;
3033 qdev->lrg_buf_free_tail = NULL;
3034
3035 ql_write_common_reg(qdev,
ee111d11 3036 &port_regs->CommonRegs.
5a4faa87
RM		 3037 rxSmallQProducerIndex,
3038 qdev->small_buf_q_producer_index);
3039 ql_write_common_reg(qdev,
ee111d11 3040 &port_regs->CommonRegs.
5a4faa87
RM		 3041 rxLargeQProducerIndex,
3042 qdev->lrg_buf_q_producer_index);
3043
3044 /*
3045 * Find out if the chip has already been initialized. If it has, then
3046 * we skip some of the initialization.
3047 */
3048 clear_bit(QL_LINK_MASTER, &qdev->flags);
3049 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3050 if ((value & PORT_STATUS_IC) == 0) {
3051
3052 /* Chip has not been configured yet, so let it rip. */
3053 if(ql_init_misc_registers(qdev)) {
3054 status = -1;
3055 goto out;
3056 }
3057
3058 if (qdev->mac_index)
3059 ql_write_page0_reg(qdev,
3060 &port_regs->mac1MaxFrameLengthReg,
3061 qdev->max_frame_size);
3062 else
3063 ql_write_page0_reg(qdev,
3064 &port_regs->mac0MaxFrameLengthReg,
3065 qdev->max_frame_size);
3066
3067 value = qdev->nvram_data.tcpMaxWindowSize;
3068 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3069
3070 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3071
3072 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3073 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3074 * 2) << 13)) {
3075 status = -1;
3076 goto out;
3077 }
3078 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3079 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3080 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3081 16) | (INTERNAL_CHIP_SD |
3082 INTERNAL_CHIP_WE)));
3083 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3084 }
3085
3086
3087 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3088 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3089 2) << 7)) {
3090 status = -1;
3091 goto out;
3092 }
3093
3094 ql_init_scan_mode(qdev);
3095 ql_get_phy_owner(qdev);
3096
3097 /* Load the MAC Configuration */
3098
3099 /* Program lower 32 bits of the MAC address */
3100 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3101 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3102 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3103 ((qdev->ndev->dev_addr[2] << 24)
3104 | (qdev->ndev->dev_addr[3] << 16)
3105 | (qdev->ndev->dev_addr[4] << 8)
3106 | qdev->ndev->dev_addr[5]));
3107
3108 /* Program top 16 bits of the MAC address */
3109 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3110 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3111 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3112 ((qdev->ndev->dev_addr[0] << 8)
3113 | qdev->ndev->dev_addr[1]));
3114
3115 /* Enable Primary MAC */
3116 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3117 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3118 MAC_ADDR_INDIRECT_PTR_REG_PE));
3119
3120 /* Clear Primary and Secondary IP addresses */
3121 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3122 ((IP_ADDR_INDEX_REG_MASK << 16) |
3123 (qdev->mac_index << 2)));
3124 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3125
3126 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3127 ((IP_ADDR_INDEX_REG_MASK << 16) |
3128 ((qdev->mac_index << 2) + 1)));
3129 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3130
3131 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3132
3133 /* Indicate Configuration Complete */
3134 ql_write_page0_reg(qdev,
3135 &port_regs->portControl,
3136 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3137
3138 do {
3139 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3140 if (value & PORT_STATUS_IC)
3141 break;
3142 msleep(500);
3143 } while (--delay);
3144
3145 if (delay == 0) {
3146 printk(KERN_ERR PFX
3147 "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3148 status = -1;
3149 goto out;
3150 }
3151
3152 /* Enable Ethernet Function */
bd36b0ac
RM		 3153 if (qdev->device_id == QL3032_DEVICE_ID) {
3154 value =
3155 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3156 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4);
3157 ql_write_page0_reg(qdev, &port_regs->functionControl,
3158 ((value << 16) | value));
3159 } else {
3160 value =
3161 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3162 PORT_CONTROL_HH);
3163 ql_write_page0_reg(qdev, &port_regs->portControl,
3164 ((value << 16) | value));
3165 }
3166
5a4faa87
RM		 3167
3168out:
3169 return status;
3170}
3171
3172/*
3173 * Caller holds hw_lock.
3174 */
3175static int ql_adapter_reset(struct ql3_adapter *qdev)
3176{
3177 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3178 int status = 0;
3179 u16 value;
3180 int max_wait_time;
3181
3182 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3183 clear_bit(QL_RESET_DONE, &qdev->flags);
3184
3185 /*
3186 * Issue soft reset to chip.
3187 */
3188 printk(KERN_DEBUG PFX
3189 "%s: Issue soft reset to chip.\n",
3190 qdev->ndev->name);
3191 ql_write_common_reg(qdev,
ee111d11 3192 &port_regs->CommonRegs.ispControlStatus,
5a4faa87
RM		 3193 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3194
3195 /* Wait 3 seconds for reset to complete. */
3196 printk(KERN_DEBUG PFX
3197 "%s: Wait 10 milliseconds for reset to complete.\n",
3198 qdev->ndev->name);
3199
3200 /* Wait until the firmware tells us the Soft Reset is done */
3201 max_wait_time = 5;
3202 do {
3203 value =
3204 ql_read_common_reg(qdev,
3205 &port_regs->CommonRegs.ispControlStatus);
3206 if ((value & ISP_CONTROL_SR) == 0)
3207 break;
3208
3209 ssleep(1);
3210 } while ((--max_wait_time));
3211
3212 /*
3213 * Also, make sure that the Network Reset Interrupt bit has been
3214 * cleared after the soft reset has taken place.
3215 */
3216 value =
3217 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3218 if (value & ISP_CONTROL_RI) {
3219 printk(KERN_DEBUG PFX
3220 "ql_adapter_reset: clearing RI after reset.\n");
3221 ql_write_common_reg(qdev,
ee111d11 3222 &port_regs->CommonRegs.
5a4faa87
RM		 3223 ispControlStatus,
3224 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3225 }
3226
3227 if (max_wait_time == 0) {
3228 /* Issue Force Soft Reset */
3229 ql_write_common_reg(qdev,
ee111d11 3230 &port_regs->CommonRegs.
5a4faa87
RM		 3231 ispControlStatus,
3232 ((ISP_CONTROL_FSR << 16) |
3233 ISP_CONTROL_FSR));
3234 /*
3235 * Wait until the firmware tells us the Force Soft Reset is
3236 * done
3237 */
3238 max_wait_time = 5;
3239 do {
3240 value =
3241 ql_read_common_reg(qdev,
3242 &port_regs->CommonRegs.
3243 ispControlStatus);
3244 if ((value & ISP_CONTROL_FSR) == 0) {
3245 break;
3246 }
3247 ssleep(1);
3248 } while ((--max_wait_time));
3249 }
3250 if (max_wait_time == 0)
3251 status = 1;
3252
3253 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3254 set_bit(QL_RESET_DONE, &qdev->flags);
3255 return status;
3256}
3257
3258static void ql_set_mac_info(struct ql3_adapter *qdev)
3259{
3260 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3261 u32 value, port_status;
3262 u8 func_number;
3263
3264 /* Get the function number */
3265 value =
3266 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3267 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3268 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3269 switch (value & ISP_CONTROL_FN_MASK) {
3270 case ISP_CONTROL_FN0_NET:
3271 qdev->mac_index = 0;
3272 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3273 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3274 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3275 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3276 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3277 if (port_status & PORT_STATUS_SM0)
3278 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3279 else
3280 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3281 break;
3282
3283 case ISP_CONTROL_FN1_NET:
3284 qdev->mac_index = 1;
3285 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3286 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3287 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3288 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3289 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3290 if (port_status & PORT_STATUS_SM1)
3291 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3292 else
3293 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3294 break;
3295
3296 case ISP_CONTROL_FN0_SCSI:
3297 case ISP_CONTROL_FN1_SCSI:
3298 default:
3299 printk(KERN_DEBUG PFX
3300 "%s: Invalid function number, ispControlStatus = 0x%x\n",
3301 qdev->ndev->name,value);
3302 break;
3303 }
3304 qdev->numPorts = qdev->nvram_data.numPorts;
3305}
3306
3307static void ql_display_dev_info(struct net_device *ndev)
3308{
3309 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3310 struct pci_dev *pdev = qdev->pdev;
3311
3312 printk(KERN_INFO PFX
bd36b0ac
RM		 3313 "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3314 DRV_NAME, qdev->index, qdev->chip_rev_id,
3315 (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3316 qdev->pci_slot);
5a4faa87
RM		 3317 printk(KERN_INFO PFX
3318 "%s Interface.\n",
3319 test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3320
3321 /*
3322 * Print PCI bus width/type.
3323 */
3324 printk(KERN_INFO PFX
3325 "Bus interface is %s %s.\n",
3326 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3327 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3328
3329 printk(KERN_INFO PFX
3330 "mem IO base address adjusted = 0x%p\n",
3331 qdev->mem_map_registers);
3332 printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3333
3334 if (netif_msg_probe(qdev))
3335 printk(KERN_INFO PFX
3336 "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3337 ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3338 ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3339 ndev->dev_addr[5]);
3340}
3341
3342static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3343{
3344 struct net_device *ndev = qdev->ndev;
3345 int retval = 0;
3346
3347 netif_stop_queue(ndev);
3348 netif_carrier_off(ndev);
3349
3350 clear_bit(QL_ADAPTER_UP,&qdev->flags);
3351 clear_bit(QL_LINK_MASTER,&qdev->flags);
3352
3353 ql_disable_interrupts(qdev);
3354
3355 free_irq(qdev->pdev->irq, ndev);
3356
3357 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3358 printk(KERN_INFO PFX
3359 "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3360 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3361 pci_disable_msi(qdev->pdev);
3362 }
3363
3364 del_timer_sync(&qdev->adapter_timer);
3365
3366 netif_poll_disable(ndev);
3367
3368 if (do_reset) {
3369 int soft_reset;
3370 unsigned long hw_flags;
3371
3372 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3373 if (ql_wait_for_drvr_lock(qdev)) {
3374 if ((soft_reset = ql_adapter_reset(qdev))) {
3375 printk(KERN_ERR PFX
3376 "%s: ql_adapter_reset(%d) FAILED!\n",
3377 ndev->name, qdev->index);
3378 }
3379 printk(KERN_ERR PFX
3380 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3381 } else {
3382 printk(KERN_ERR PFX
3383 "%s: Could not acquire driver lock to do "
3384 "reset!\n", ndev->name);
3385 retval = -1;
3386 }
3387 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3388 }
3389 ql_free_mem_resources(qdev);
3390 return retval;
3391}
3392
3393static int ql_adapter_up(struct ql3_adapter *qdev)
3394{
3395 struct net_device *ndev = qdev->ndev;
3396 int err;
38515e90 3397 unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
5a4faa87
RM		 3398 unsigned long hw_flags;
3399
3400 if (ql_alloc_mem_resources(qdev)) {
3401 printk(KERN_ERR PFX
3402 "%s Unable to allocate buffers.\n", ndev->name);
3403 return -ENOMEM;
3404 }
3405
3406 if (qdev->msi) {
3407 if (pci_enable_msi(qdev->pdev)) {
3408 printk(KERN_ERR PFX
3409 "%s: User requested MSI, but MSI failed to "
3410 "initialize. Continuing without MSI.\n",
3411 qdev->ndev->name);
3412 qdev->msi = 0;
3413 } else {
3414 printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3415 set_bit(QL_MSI_ENABLED,&qdev->flags);
38515e90 3416 irq_flags &= ~IRQF_SHARED;
5a4faa87
RM		 3417 }
3418 }
3419
3420 if ((err = request_irq(qdev->pdev->irq,
3421 ql3xxx_isr,
3422 irq_flags, ndev->name, ndev))) {
3423 printk(KERN_ERR PFX
3424 "%s: Failed to reserve interrupt %d already in use.\n",
3425 ndev->name, qdev->pdev->irq);
3426 goto err_irq;
3427 }
3428
3429 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3430
3431 if ((err = ql_wait_for_drvr_lock(qdev))) {
3432 if ((err = ql_adapter_initialize(qdev))) {
3433 printk(KERN_ERR PFX
3434 "%s: Unable to initialize adapter.\n",
3435 ndev->name);
3436 goto err_init;
3437 }
3438 printk(KERN_ERR PFX
3439 "%s: Releaseing driver lock.\n",ndev->name);
3440 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3441 } else {
3442 printk(KERN_ERR PFX
3443 "%s: Could not aquire driver lock.\n",
3444 ndev->name);
3445 goto err_lock;
3446 }
3447
3448 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3449
3450 set_bit(QL_ADAPTER_UP,&qdev->flags);
3451
3452 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3453
3454 netif_poll_enable(ndev);
3455 ql_enable_interrupts(qdev);
3456 return 0;
3457
3458err_init:
3459 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3460err_lock:
04f10773 3461 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 3462 free_irq(qdev->pdev->irq, ndev);
3463err_irq:
3464 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3465 printk(KERN_INFO PFX
3466 "%s: calling pci_disable_msi().\n",
3467 qdev->ndev->name);
3468 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3469 pci_disable_msi(qdev->pdev);
3470 }
3471 return err;
3472}
3473
3474static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3475{
3476 if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3477 printk(KERN_ERR PFX
3478 "%s: Driver up/down cycle failed, "
3479 "closing device\n",qdev->ndev->name);
3480 dev_close(qdev->ndev);
3481 return -1;
3482 }
3483 return 0;
3484}
3485
3486static int ql3xxx_close(struct net_device *ndev)
3487{
3488 struct ql3_adapter *qdev = netdev_priv(ndev);
3489
3490 /*
3491 * Wait for device to recover from a reset.
3492 * (Rarely happens, but possible.)
3493 */
3494 while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3495 msleep(50);
3496
3497 ql_adapter_down(qdev,QL_DO_RESET);
3498 return 0;
3499}
3500
3501static int ql3xxx_open(struct net_device *ndev)
3502{
3503 struct ql3_adapter *qdev = netdev_priv(ndev);
3504 return (ql_adapter_up(qdev));
3505}
3506
3507static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3508{
3509 struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3510 return &qdev->stats;
3511}
3512
5a4faa87
RM		 3513static void ql3xxx_set_multicast_list(struct net_device *ndev)
3514{
3515 /*
3516 * We are manually parsing the list in the net_device structure.
3517 */
3518 return;
3519}
3520
3521static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3522{
3523 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3524 struct ql3xxx_port_registers __iomem *port_regs =
3525 qdev->mem_map_registers;
3526 struct sockaddr *addr = p;
3527 unsigned long hw_flags;
3528
3529 if (netif_running(ndev))
3530 return -EBUSY;
3531
3532 if (!is_valid_ether_addr(addr->sa_data))
3533 return -EADDRNOTAVAIL;
3534
3535 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3536
3537 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3538 /* Program lower 32 bits of the MAC address */
3539 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3540 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3541 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3542 ((ndev->dev_addr[2] << 24) | (ndev->
3543 dev_addr[3] << 16) |
3544 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3545
3546 /* Program top 16 bits of the MAC address */
3547 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3548 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3549 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3550 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3551 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3552
3553 return 0;
3554}
3555
3556static void ql3xxx_tx_timeout(struct net_device *ndev)
3557{
3558 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3559
3560 printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3561 /*
3562 * Stop the queues, we've got a problem.
3563 */
3564 netif_stop_queue(ndev);
3565
3566 /*
3567 * Wake up the worker to process this event.
3568 */
c4028958 3569 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
5a4faa87
RM		 3570}
3571
c4028958 3572static void ql_reset_work(struct work_struct *work)
5a4faa87 3573{
c4028958
DH		 3574 struct ql3_adapter *qdev =
3575 container_of(work, struct ql3_adapter, reset_work.work);
5a4faa87
RM		 3576 struct net_device *ndev = qdev->ndev;
3577 u32 value;
3578 struct ql_tx_buf_cb *tx_cb;
3579 int max_wait_time, i;
3580 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3581 unsigned long hw_flags;
3582
3583 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3584 clear_bit(QL_LINK_MASTER,&qdev->flags);
3585
3586 /*
3587 * Loop through the active list and return the skb.
3588 */
3589 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
bd36b0ac 3590 int j;
5a4faa87
RM		 3591 tx_cb = &qdev->tx_buf[i];
3592 if (tx_cb->skb) {
5a4faa87
RM		 3593 printk(KERN_DEBUG PFX
3594 "%s: Freeing lost SKB.\n",
3595 qdev->ndev->name);
3596 pci_unmap_single(qdev->pdev,
bd36b0ac
RM		 3597 pci_unmap_addr(&tx_cb->map[0], mapaddr),
3598 pci_unmap_len(&tx_cb->map[0], maplen),
3599 PCI_DMA_TODEVICE);
3600 for(j=1;j<tx_cb->seg_count;j++) {
3601 pci_unmap_page(qdev->pdev,
3602 pci_unmap_addr(&tx_cb->map[j],mapaddr),
3603 pci_unmap_len(&tx_cb->map[j],maplen),
3604 PCI_DMA_TODEVICE);
3605 }
5a4faa87
RM		 3606 dev_kfree_skb(tx_cb->skb);
3607 tx_cb->skb = NULL;
3608 }
3609 }
3610
3611 printk(KERN_ERR PFX
3612 "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3613 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3614 ql_write_common_reg(qdev,
3615 &port_regs->CommonRegs.
3616 ispControlStatus,
3617 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3618 /*
3619 * Wait the for Soft Reset to Complete.
3620 */
3621 max_wait_time = 10;
3622 do {
3623 value = ql_read_common_reg(qdev,
3624 &port_regs->CommonRegs.
3625
3626 ispControlStatus);
3627 if ((value & ISP_CONTROL_SR) == 0) {
3628 printk(KERN_DEBUG PFX
3629 "%s: reset completed.\n",
3630 qdev->ndev->name);
3631 break;
3632 }
3633
3634 if (value & ISP_CONTROL_RI) {
3635 printk(KERN_DEBUG PFX
3636 "%s: clearing NRI after reset.\n",
3637 qdev->ndev->name);
3638 ql_write_common_reg(qdev,
ee111d11 3639 &port_regs->
5a4faa87
RM		 3640 CommonRegs.
3641 ispControlStatus,
3642 ((ISP_CONTROL_RI <<
3643 16) | ISP_CONTROL_RI));
3644 }
3645
3646 ssleep(1);
3647 } while (--max_wait_time);
3648 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3649
3650 if (value & ISP_CONTROL_SR) {
3651
3652 /*
3653 * Set the reset flags and clear the board again.
3654 * Nothing else to do...
3655 */
3656 printk(KERN_ERR PFX
3657 "%s: Timed out waiting for reset to "
3658 "complete.\n", ndev->name);
3659 printk(KERN_ERR PFX
3660 "%s: Do a reset.\n", ndev->name);
3661 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3662 clear_bit(QL_RESET_START,&qdev->flags);
3663 ql_cycle_adapter(qdev,QL_DO_RESET);
3664 return;
3665 }
3666
3667 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3668 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3669 clear_bit(QL_RESET_START,&qdev->flags);
3670 ql_cycle_adapter(qdev,QL_NO_RESET);
3671 }
3672}
3673
c4028958 3674static void ql_tx_timeout_work(struct work_struct *work)
5a4faa87 3675{
c4028958
DH		 3676 struct ql3_adapter *qdev =
3677 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3678
3679 ql_cycle_adapter(qdev, QL_DO_RESET);
5a4faa87
RM		 3680}
3681
3682static void ql_get_board_info(struct ql3_adapter *qdev)
3683{
3684 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3685 u32 value;
3686
3687 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3688
3689 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3690 if (value & PORT_STATUS_64)
3691 qdev->pci_width = 64;
3692 else
3693 qdev->pci_width = 32;
3694 if (value & PORT_STATUS_X)
3695 qdev->pci_x = 1;
3696 else
3697 qdev->pci_x = 0;
3698 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3699}
3700
3701static void ql3xxx_timer(unsigned long ptr)
3702{
3703 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3704
3705 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3706 printk(KERN_DEBUG PFX
3707 "%s: Reset in progress.\n",
3708 qdev->ndev->name);
3709 goto end;
3710 }
3711
3712 ql_link_state_machine(qdev);
3713
3714 /* Restart timer on 2 second interval. */
3715end:
3716 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3717}
3718
3719static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3720 const struct pci_device_id *pci_entry)
3721{
3722 struct net_device *ndev = NULL;
3723 struct ql3_adapter *qdev = NULL;
3724 static int cards_found = 0;
3725 int pci_using_dac, err;
3726
3727 err = pci_enable_device(pdev);
3728 if (err) {
3729 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3730 pci_name(pdev));
3731 goto err_out;
3732 }
3733
3734 err = pci_request_regions(pdev, DRV_NAME);
3735 if (err) {
3736 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3737 pci_name(pdev));
3738 goto err_out_disable_pdev;
3739 }
3740
3741 pci_set_master(pdev);
3742
3743 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3744 pci_using_dac = 1;
3745 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3746 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3747 pci_using_dac = 0;
3748 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3749 }
3750
3751 if (err) {
3752 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3753 pci_name(pdev));
3754 goto err_out_free_regions;
3755 }
3756
3757 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
546faf07
BL		 3758 if (!ndev) {
3759 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3760 pci_name(pdev));
3761 err = -ENOMEM;
5a4faa87 3762 goto err_out_free_regions;
546faf07 3763 }
5a4faa87
RM		 3764
3765 SET_MODULE_OWNER(ndev);
3766 SET_NETDEV_DEV(ndev, &pdev->dev);
3767
5a4faa87
RM		 3768 pci_set_drvdata(pdev, ndev);
3769
3770 qdev = netdev_priv(ndev);
3771 qdev->index = cards_found;
3772 qdev->ndev = ndev;
3773 qdev->pdev = pdev;
bd36b0ac 3774 qdev->device_id = pci_entry->device;
5a4faa87
RM		 3775 qdev->port_link_state = LS_DOWN;
3776 if (msi)
3777 qdev->msi = 1;
3778
3779 qdev->msg_enable = netif_msg_init(debug, default_msg);
3780
bd36b0ac
RM		 3781 if (pci_using_dac)
3782 ndev->features |= NETIF_F_HIGHDMA;
3783 if (qdev->device_id == QL3032_DEVICE_ID)
3784 ndev->features |= (NETIF_F_HW_CSUM | NETIF_F_SG);
3785
5a4faa87
RM		 3786 qdev->mem_map_registers =
3787 ioremap_nocache(pci_resource_start(pdev, 1),
3788 pci_resource_len(qdev->pdev, 1));
3789 if (!qdev->mem_map_registers) {
3790 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3791 pci_name(pdev));
546faf07 3792 err = -EIO;
5a4faa87
RM		 3793 goto err_out_free_ndev;
3794 }
3795
3796 spin_lock_init(&qdev->adapter_lock);
3797 spin_lock_init(&qdev->hw_lock);
3798
3799 /* Set driver entry points */
3800 ndev->open = ql3xxx_open;
3801 ndev->hard_start_xmit = ql3xxx_send;
3802 ndev->stop = ql3xxx_close;
3803 ndev->get_stats = ql3xxx_get_stats;
5a4faa87
RM		 3804 ndev->set_multicast_list = ql3xxx_set_multicast_list;
3805 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3806 ndev->set_mac_address = ql3xxx_set_mac_address;
3807 ndev->tx_timeout = ql3xxx_tx_timeout;
3808 ndev->watchdog_timeo = 5 * HZ;
3809
3810 ndev->poll = &ql_poll;
3811 ndev->weight = 64;
3812
3813 ndev->irq = pdev->irq;
3814
3815 /* make sure the EEPROM is good */
3816 if (ql_get_nvram_params(qdev)) {
3817 printk(KERN_ALERT PFX
3818 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3819 qdev->index);
546faf07 3820 err = -EIO;
5a4faa87
RM		 3821 goto err_out_iounmap;
3822 }
3823
3824 ql_set_mac_info(qdev);
3825
3826 /* Validate and set parameters */
3827 if (qdev->mac_index) {
cb8bac12 3828 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
5a4faa87
RM		 3829 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
3830 ETH_ALEN);
3831 } else {
cb8bac12 3832 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
5a4faa87
RM		 3833 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
3834 ETH_ALEN);
3835 }
3836 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3837
3838 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3839
3840 /* Turn off support for multicasting */
3841 ndev->flags &= ~IFF_MULTICAST;
3842
3843 /* Record PCI bus information. */
3844 ql_get_board_info(qdev);
3845
3846 /*
3847 * Set the Maximum Memory Read Byte Count value. We do this to handle
3848 * jumbo frames.
3849 */
3850 if (qdev->pci_x) {
3851 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3852 }
3853
3854 err = register_netdev(ndev);
3855 if (err) {
3856 printk(KERN_ERR PFX "%s: cannot register net device\n",
3857 pci_name(pdev));
3858 goto err_out_iounmap;
3859 }
3860
3861 /* we're going to reset, so assume we have no link for now */
3862
3863 netif_carrier_off(ndev);
3864 netif_stop_queue(ndev);
3865
3866 qdev->workqueue = create_singlethread_workqueue(ndev->name);
c4028958
DH		 3867 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3868 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
5a4faa87
RM		 3869
3870 init_timer(&qdev->adapter_timer);
3871 qdev->adapter_timer.function = ql3xxx_timer;
3872 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3873 qdev->adapter_timer.data = (unsigned long)qdev;
3874
3875 if(!cards_found) {
3876 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
3877 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
3878 DRV_NAME, DRV_VERSION);
3879 }
3880 ql_display_dev_info(ndev);
3881
3882 cards_found++;
3883 return 0;
3884
3885err_out_iounmap:
3886 iounmap(qdev->mem_map_registers);
3887err_out_free_ndev:
3888 free_netdev(ndev);
3889err_out_free_regions:
3890 pci_release_regions(pdev);
3891err_out_disable_pdev:
3892 pci_disable_device(pdev);
3893 pci_set_drvdata(pdev, NULL);
3894err_out:
3895 return err;
3896}
3897
3898static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3899{
3900 struct net_device *ndev = pci_get_drvdata(pdev);
3901 struct ql3_adapter *qdev = netdev_priv(ndev);
3902
3903 unregister_netdev(ndev);
3904 qdev = netdev_priv(ndev);
3905
3906 ql_disable_interrupts(qdev);
3907
3908 if (qdev->workqueue) {
3909 cancel_delayed_work(&qdev->reset_work);
3910 cancel_delayed_work(&qdev->tx_timeout_work);
3911 destroy_workqueue(qdev->workqueue);
3912 qdev->workqueue = NULL;
3913 }
3914
855fc73b 3915 iounmap(qdev->mem_map_registers);
5a4faa87
RM		 3916 pci_release_regions(pdev);
3917 pci_set_drvdata(pdev, NULL);
3918 free_netdev(ndev);
3919}
3920
3921static struct pci_driver ql3xxx_driver = {
3922
3923 .name = DRV_NAME,
3924 .id_table = ql3xxx_pci_tbl,
3925 .probe = ql3xxx_probe,
3926 .remove = __devexit_p(ql3xxx_remove),
3927};
3928
3929static int __init ql3xxx_init_module(void)
3930{
3931 return pci_register_driver(&ql3xxx_driver);
3932}
3933
3934static void __exit ql3xxx_exit(void)
3935{
3936 pci_unregister_driver(&ql3xxx_driver);
3937}
3938
3939module_init(ql3xxx_init_module);
3940module_exit(ql3xxx_exit);
Linux 6.x block layer and io_uring tree(s)