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48e8c6f1 PG |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
813abcd9 | 3 | * Motorcomm 8511/8521/8531S PHY driver. |
48e8c6f1 PG |
4 | * |
5 | * Author: Peter Geis <pgwipeout@gmail.com> | |
70479a40 | 6 | * Author: Frank <Frank.Sae@motor-comm.com> |
48e8c6f1 PG |
7 | */ |
8 | ||
70479a40 | 9 | #include <linux/etherdevice.h> |
48e8c6f1 PG |
10 | #include <linux/kernel.h> |
11 | #include <linux/module.h> | |
12 | #include <linux/phy.h> | |
13 | ||
14 | #define PHY_ID_YT8511 0x0000010a | |
813abcd9 F |
15 | #define PHY_ID_YT8521 0x0000011A |
16 | #define PHY_ID_YT8531S 0x4F51E91A | |
70479a40 | 17 | |
813abcd9 | 18 | /* YT8521/YT8531S Register Overview |
70479a40 F |
19 | * UTP Register space | FIBER Register space |
20 | * ------------------------------------------------------------ | |
21 | * | UTP MII | FIBER MII | | |
22 | * | UTP MMD | | | |
23 | * | UTP Extended | FIBER Extended | | |
24 | * ------------------------------------------------------------ | |
25 | * | Common Extended | | |
26 | * ------------------------------------------------------------ | |
27 | */ | |
28 | ||
29 | /* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */ | |
30 | ||
31 | /* Specific Function Control Register */ | |
32 | #define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG 0x10 | |
33 | ||
34 | /* 2b00 Manual MDI configuration | |
35 | * 2b01 Manual MDIX configuration | |
36 | * 2b10 Reserved | |
37 | * 2b11 Enable automatic crossover for all modes *default* | |
38 | */ | |
39 | #define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK (BIT(6) | BIT(5)) | |
40 | #define YTPHY_SFCR_CROSSOVER_EN BIT(3) | |
41 | #define YTPHY_SFCR_SQE_TEST_EN BIT(2) | |
42 | #define YTPHY_SFCR_POLARITY_REVERSAL_EN BIT(1) | |
43 | #define YTPHY_SFCR_JABBER_DIS BIT(0) | |
44 | ||
45 | /* Specific Status Register */ | |
46 | #define YTPHY_SPECIFIC_STATUS_REG 0x11 | |
47 | #define YTPHY_SSR_SPEED_MODE_OFFSET 14 | |
48 | ||
49 | #define YTPHY_SSR_SPEED_MODE_MASK (BIT(15) | BIT(14)) | |
50 | #define YTPHY_SSR_SPEED_10M 0x0 | |
51 | #define YTPHY_SSR_SPEED_100M 0x1 | |
52 | #define YTPHY_SSR_SPEED_1000M 0x2 | |
53 | #define YTPHY_SSR_DUPLEX_OFFSET 13 | |
54 | #define YTPHY_SSR_DUPLEX BIT(13) | |
55 | #define YTPHY_SSR_PAGE_RECEIVED BIT(12) | |
56 | #define YTPHY_SSR_SPEED_DUPLEX_RESOLVED BIT(11) | |
57 | #define YTPHY_SSR_LINK BIT(10) | |
58 | #define YTPHY_SSR_MDIX_CROSSOVER BIT(6) | |
59 | #define YTPHY_SSR_DOWNGRADE BIT(5) | |
60 | #define YTPHY_SSR_TRANSMIT_PAUSE BIT(3) | |
61 | #define YTPHY_SSR_RECEIVE_PAUSE BIT(2) | |
62 | #define YTPHY_SSR_POLARITY BIT(1) | |
63 | #define YTPHY_SSR_JABBER BIT(0) | |
64 | ||
65 | /* Interrupt enable Register */ | |
66 | #define YTPHY_INTERRUPT_ENABLE_REG 0x12 | |
67 | #define YTPHY_IER_WOL BIT(6) | |
68 | ||
69 | /* Interrupt Status Register */ | |
70 | #define YTPHY_INTERRUPT_STATUS_REG 0x13 | |
71 | #define YTPHY_ISR_AUTONEG_ERR BIT(15) | |
72 | #define YTPHY_ISR_SPEED_CHANGED BIT(14) | |
73 | #define YTPHY_ISR_DUPLEX_CHANGED BIT(13) | |
74 | #define YTPHY_ISR_PAGE_RECEIVED BIT(12) | |
75 | #define YTPHY_ISR_LINK_FAILED BIT(11) | |
76 | #define YTPHY_ISR_LINK_SUCCESSED BIT(10) | |
77 | #define YTPHY_ISR_WOL BIT(6) | |
78 | #define YTPHY_ISR_WIRESPEED_DOWNGRADE BIT(5) | |
79 | #define YTPHY_ISR_SERDES_LINK_FAILED BIT(3) | |
80 | #define YTPHY_ISR_SERDES_LINK_SUCCESSED BIT(2) | |
81 | #define YTPHY_ISR_POLARITY_CHANGED BIT(1) | |
82 | #define YTPHY_ISR_JABBER_HAPPENED BIT(0) | |
83 | ||
84 | /* Speed Auto Downgrade Control Register */ | |
85 | #define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG 0x14 | |
86 | #define YTPHY_SADCR_SPEED_DOWNGRADE_EN BIT(5) | |
87 | ||
88 | /* If these bits are set to 3, the PHY attempts five times ( 3(set value) + | |
89 | * additional 2) before downgrading, default 0x3 | |
90 | */ | |
91 | #define YTPHY_SADCR_SPEED_RETRY_LIMIT (0x3 << 2) | |
92 | ||
93 | /* Rx Error Counter Register */ | |
94 | #define YTPHY_RX_ERROR_COUNTER_REG 0x15 | |
95 | ||
96 | /* Extended Register's Address Offset Register */ | |
97 | #define YTPHY_PAGE_SELECT 0x1E | |
98 | ||
99 | /* Extended Register's Data Register */ | |
100 | #define YTPHY_PAGE_DATA 0x1F | |
101 | ||
102 | /* FIBER Auto-Negotiation link partner ability */ | |
103 | #define YTPHY_FLPA_PAUSE (0x3 << 7) | |
104 | #define YTPHY_FLPA_ASYM_PAUSE (0x2 << 7) | |
48e8c6f1 PG |
105 | |
106 | #define YT8511_PAGE_SELECT 0x1e | |
107 | #define YT8511_PAGE 0x1f | |
108 | #define YT8511_EXT_CLK_GATE 0x0c | |
109 | #define YT8511_EXT_DELAY_DRIVE 0x0d | |
110 | #define YT8511_EXT_SLEEP_CTRL 0x27 | |
111 | ||
112 | /* 2b00 25m from pll | |
113 | * 2b01 25m from xtl *default* | |
114 | * 2b10 62.m from pll | |
115 | * 2b11 125m from pll | |
116 | */ | |
117 | #define YT8511_CLK_125M (BIT(2) | BIT(1)) | |
118 | #define YT8511_PLLON_SLP BIT(14) | |
119 | ||
120 | /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */ | |
121 | #define YT8511_DELAY_RX BIT(0) | |
122 | ||
123 | /* TX Gig-E Delay is bits 7:4, default 0x5 | |
124 | * TX Fast-E Delay is bits 15:12, default 0xf | |
125 | * Delay = 150ps * N - 250ps | |
126 | * On = 2000ps, off = 50ps | |
127 | */ | |
128 | #define YT8511_DELAY_GE_TX_EN (0xf << 4) | |
129 | #define YT8511_DELAY_GE_TX_DIS (0x2 << 4) | |
130 | #define YT8511_DELAY_FE_TX_EN (0xf << 12) | |
131 | #define YT8511_DELAY_FE_TX_DIS (0x2 << 12) | |
132 | ||
70479a40 F |
133 | /* Extended register is different from MMD Register and MII Register. |
134 | * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to | |
135 | * operate extended register. | |
136 | * Extended Register start | |
137 | */ | |
138 | ||
139 | /* Phy gmii clock gating Register */ | |
140 | #define YT8521_CLOCK_GATING_REG 0xC | |
141 | #define YT8521_CGR_RX_CLK_EN BIT(12) | |
142 | ||
143 | #define YT8521_EXTREG_SLEEP_CONTROL1_REG 0x27 | |
144 | #define YT8521_ESC1R_SLEEP_SW BIT(15) | |
145 | #define YT8521_ESC1R_PLLON_SLP BIT(14) | |
146 | ||
147 | /* Phy fiber Link timer cfg2 Register */ | |
148 | #define YT8521_LINK_TIMER_CFG2_REG 0xA5 | |
149 | #define YT8521_LTCR_EN_AUTOSEN BIT(15) | |
150 | ||
813abcd9 | 151 | /* 0xA000, 0xA001, 0xA003, 0xA006 ~ 0xA00A and 0xA012 are common ext registers |
70479a40 F |
152 | * of yt8521 phy. There is no need to switch reg space when operating these |
153 | * registers. | |
154 | */ | |
155 | ||
156 | #define YT8521_REG_SPACE_SELECT_REG 0xA000 | |
157 | #define YT8521_RSSR_SPACE_MASK BIT(1) | |
158 | #define YT8521_RSSR_FIBER_SPACE (0x1 << 1) | |
159 | #define YT8521_RSSR_UTP_SPACE (0x0 << 1) | |
160 | #define YT8521_RSSR_TO_BE_ARBITRATED (0xFF) | |
161 | ||
162 | #define YT8521_CHIP_CONFIG_REG 0xA001 | |
163 | #define YT8521_CCR_SW_RST BIT(15) | |
164 | ||
165 | #define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0)) | |
166 | #define YT8521_CCR_MODE_UTP_TO_RGMII 0 | |
167 | #define YT8521_CCR_MODE_FIBER_TO_RGMII 1 | |
168 | #define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII 2 | |
169 | #define YT8521_CCR_MODE_UTP_TO_SGMII 3 | |
170 | #define YT8521_CCR_MODE_SGPHY_TO_RGMAC 4 | |
171 | #define YT8521_CCR_MODE_SGMAC_TO_RGPHY 5 | |
172 | #define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO 6 | |
173 | #define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE 7 | |
174 | ||
175 | /* 3 phy polling modes,poll mode combines utp and fiber mode*/ | |
176 | #define YT8521_MODE_FIBER 0x1 | |
177 | #define YT8521_MODE_UTP 0x2 | |
178 | #define YT8521_MODE_POLL 0x3 | |
179 | ||
180 | #define YT8521_RGMII_CONFIG1_REG 0xA003 | |
181 | ||
182 | /* TX Gig-E Delay is bits 3:0, default 0x1 | |
183 | * TX Fast-E Delay is bits 7:4, default 0xf | |
184 | * RX Delay is bits 13:10, default 0x0 | |
185 | * Delay = 150ps * N | |
186 | * On = 2250ps, off = 0ps | |
187 | */ | |
188 | #define YT8521_RC1R_RX_DELAY_MASK (0xF << 10) | |
189 | #define YT8521_RC1R_RX_DELAY_EN (0xF << 10) | |
190 | #define YT8521_RC1R_RX_DELAY_DIS (0x0 << 10) | |
191 | #define YT8521_RC1R_FE_TX_DELAY_MASK (0xF << 4) | |
192 | #define YT8521_RC1R_FE_TX_DELAY_EN (0xF << 4) | |
193 | #define YT8521_RC1R_FE_TX_DELAY_DIS (0x0 << 4) | |
194 | #define YT8521_RC1R_GE_TX_DELAY_MASK (0xF << 0) | |
195 | #define YT8521_RC1R_GE_TX_DELAY_EN (0xF << 0) | |
196 | #define YT8521_RC1R_GE_TX_DELAY_DIS (0x0 << 0) | |
197 | ||
198 | #define YTPHY_MISC_CONFIG_REG 0xA006 | |
199 | #define YTPHY_MCR_FIBER_SPEED_MASK BIT(0) | |
200 | #define YTPHY_MCR_FIBER_1000BX (0x1 << 0) | |
201 | #define YTPHY_MCR_FIBER_100FX (0x0 << 0) | |
202 | ||
203 | /* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */ | |
204 | #define YTPHY_WOL_MACADDR2_REG 0xA007 | |
205 | #define YTPHY_WOL_MACADDR1_REG 0xA008 | |
206 | #define YTPHY_WOL_MACADDR0_REG 0xA009 | |
207 | ||
208 | #define YTPHY_WOL_CONFIG_REG 0xA00A | |
209 | #define YTPHY_WCR_INTR_SEL BIT(6) | |
210 | #define YTPHY_WCR_ENABLE BIT(3) | |
211 | ||
212 | /* 2b00 84ms | |
213 | * 2b01 168ms *default* | |
214 | * 2b10 336ms | |
215 | * 2b11 672ms | |
216 | */ | |
217 | #define YTPHY_WCR_PULSE_WIDTH_MASK (BIT(2) | BIT(1)) | |
218 | #define YTPHY_WCR_PULSE_WIDTH_672MS (BIT(2) | BIT(1)) | |
219 | ||
220 | /* 1b0 Interrupt and WOL events is level triggered and active LOW *default* | |
221 | * 1b1 Interrupt and WOL events is pulse triggered and active LOW | |
222 | */ | |
223 | #define YTPHY_WCR_TYPE_PULSE BIT(0) | |
224 | ||
813abcd9 F |
225 | #define YT8531S_SYNCE_CFG_REG 0xA012 |
226 | #define YT8531S_SCR_SYNCE_ENABLE BIT(6) | |
227 | ||
70479a40 F |
228 | /* Extended Register end */ |
229 | ||
230 | struct yt8521_priv { | |
231 | /* combo_advertising is used for case of YT8521 in combo mode, | |
232 | * this means that yt8521 may work in utp or fiber mode which depends | |
233 | * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED). | |
234 | */ | |
235 | __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising); | |
236 | ||
237 | /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/ | |
238 | u8 polling_mode; | |
239 | u8 strap_mode; /* 8 working modes */ | |
240 | /* current reg page of yt8521 phy: | |
241 | * YT8521_RSSR_UTP_SPACE | |
242 | * YT8521_RSSR_FIBER_SPACE | |
243 | * YT8521_RSSR_TO_BE_ARBITRATED | |
244 | */ | |
245 | u8 reg_page; | |
246 | }; | |
247 | ||
248 | /** | |
249 | * ytphy_read_ext() - read a PHY's extended register | |
250 | * @phydev: a pointer to a &struct phy_device | |
251 | * @regnum: register number to read | |
252 | * | |
253 | * NOTE:The caller must have taken the MDIO bus lock. | |
254 | * | |
255 | * returns the value of regnum reg or negative error code | |
256 | */ | |
257 | static int ytphy_read_ext(struct phy_device *phydev, u16 regnum) | |
258 | { | |
259 | int ret; | |
260 | ||
261 | ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); | |
262 | if (ret < 0) | |
263 | return ret; | |
264 | ||
265 | return __phy_read(phydev, YTPHY_PAGE_DATA); | |
266 | } | |
267 | ||
268 | /** | |
269 | * ytphy_read_ext_with_lock() - read a PHY's extended register | |
270 | * @phydev: a pointer to a &struct phy_device | |
271 | * @regnum: register number to read | |
272 | * | |
273 | * returns the value of regnum reg or negative error code | |
274 | */ | |
275 | static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum) | |
276 | { | |
277 | int ret; | |
278 | ||
279 | phy_lock_mdio_bus(phydev); | |
280 | ret = ytphy_read_ext(phydev, regnum); | |
281 | phy_unlock_mdio_bus(phydev); | |
282 | ||
283 | return ret; | |
284 | } | |
285 | ||
286 | /** | |
287 | * ytphy_write_ext() - write a PHY's extended register | |
288 | * @phydev: a pointer to a &struct phy_device | |
289 | * @regnum: register number to write | |
290 | * @val: value to write to @regnum | |
291 | * | |
292 | * NOTE:The caller must have taken the MDIO bus lock. | |
293 | * | |
294 | * returns 0 or negative error code | |
295 | */ | |
296 | static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val) | |
297 | { | |
298 | int ret; | |
299 | ||
300 | ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); | |
301 | if (ret < 0) | |
302 | return ret; | |
303 | ||
304 | return __phy_write(phydev, YTPHY_PAGE_DATA, val); | |
305 | } | |
306 | ||
307 | /** | |
308 | * ytphy_write_ext_with_lock() - write a PHY's extended register | |
309 | * @phydev: a pointer to a &struct phy_device | |
310 | * @regnum: register number to write | |
311 | * @val: value to write to @regnum | |
312 | * | |
313 | * returns 0 or negative error code | |
314 | */ | |
315 | static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum, | |
316 | u16 val) | |
317 | { | |
318 | int ret; | |
319 | ||
320 | phy_lock_mdio_bus(phydev); | |
321 | ret = ytphy_write_ext(phydev, regnum, val); | |
322 | phy_unlock_mdio_bus(phydev); | |
323 | ||
324 | return ret; | |
325 | } | |
326 | ||
327 | /** | |
328 | * ytphy_modify_ext() - bits modify a PHY's extended register | |
329 | * @phydev: a pointer to a &struct phy_device | |
330 | * @regnum: register number to write | |
331 | * @mask: bit mask of bits to clear | |
332 | * @set: bit mask of bits to set | |
333 | * | |
334 | * NOTE: Convenience function which allows a PHY's extended register to be | |
335 | * modified as new register value = (old register value & ~mask) | set. | |
336 | * The caller must have taken the MDIO bus lock. | |
337 | * | |
338 | * returns 0 or negative error code | |
339 | */ | |
340 | static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask, | |
341 | u16 set) | |
342 | { | |
343 | int ret; | |
344 | ||
345 | ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); | |
346 | if (ret < 0) | |
347 | return ret; | |
348 | ||
349 | return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set); | |
350 | } | |
351 | ||
352 | /** | |
353 | * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register | |
354 | * @phydev: a pointer to a &struct phy_device | |
355 | * @regnum: register number to write | |
356 | * @mask: bit mask of bits to clear | |
357 | * @set: bit mask of bits to set | |
358 | * | |
359 | * NOTE: Convenience function which allows a PHY's extended register to be | |
360 | * modified as new register value = (old register value & ~mask) | set. | |
361 | * | |
362 | * returns 0 or negative error code | |
363 | */ | |
364 | static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum, | |
365 | u16 mask, u16 set) | |
366 | { | |
367 | int ret; | |
368 | ||
369 | phy_lock_mdio_bus(phydev); | |
370 | ret = ytphy_modify_ext(phydev, regnum, mask, set); | |
371 | phy_unlock_mdio_bus(phydev); | |
372 | ||
373 | return ret; | |
374 | } | |
375 | ||
376 | /** | |
377 | * ytphy_get_wol() - report whether wake-on-lan is enabled | |
378 | * @phydev: a pointer to a &struct phy_device | |
379 | * @wol: a pointer to a &struct ethtool_wolinfo | |
380 | * | |
381 | * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg. | |
382 | */ | |
383 | static void ytphy_get_wol(struct phy_device *phydev, | |
384 | struct ethtool_wolinfo *wol) | |
385 | { | |
386 | int wol_config; | |
387 | ||
388 | wol->supported = WAKE_MAGIC; | |
389 | wol->wolopts = 0; | |
390 | ||
391 | wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); | |
392 | if (wol_config < 0) | |
393 | return; | |
394 | ||
395 | if (wol_config & YTPHY_WCR_ENABLE) | |
396 | wol->wolopts |= WAKE_MAGIC; | |
397 | } | |
398 | ||
399 | /** | |
400 | * ytphy_set_wol() - turn wake-on-lan on or off | |
401 | * @phydev: a pointer to a &struct phy_device | |
402 | * @wol: a pointer to a &struct ethtool_wolinfo | |
403 | * | |
404 | * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG | |
405 | * and YTPHY_WOL_MACADDR0_REG are common ext reg. The | |
406 | * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register. | |
407 | * | |
408 | * returns 0 or negative errno code | |
409 | */ | |
410 | static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) | |
411 | { | |
412 | struct net_device *p_attached_dev; | |
413 | const u16 mac_addr_reg[] = { | |
414 | YTPHY_WOL_MACADDR2_REG, | |
415 | YTPHY_WOL_MACADDR1_REG, | |
416 | YTPHY_WOL_MACADDR0_REG, | |
417 | }; | |
418 | const u8 *mac_addr; | |
419 | int old_page; | |
420 | int ret = 0; | |
421 | u16 mask; | |
422 | u16 val; | |
423 | u8 i; | |
424 | ||
425 | if (wol->wolopts & WAKE_MAGIC) { | |
426 | p_attached_dev = phydev->attached_dev; | |
427 | if (!p_attached_dev) | |
428 | return -ENODEV; | |
429 | ||
430 | mac_addr = (const u8 *)p_attached_dev->dev_addr; | |
431 | if (!is_valid_ether_addr(mac_addr)) | |
432 | return -EINVAL; | |
433 | ||
434 | /* lock mdio bus then switch to utp reg space */ | |
435 | old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); | |
436 | if (old_page < 0) | |
437 | goto err_restore_page; | |
438 | ||
439 | /* Store the device address for the magic packet */ | |
440 | for (i = 0; i < 3; i++) { | |
441 | ret = ytphy_write_ext(phydev, mac_addr_reg[i], | |
442 | ((mac_addr[i * 2] << 8)) | | |
443 | (mac_addr[i * 2 + 1])); | |
444 | if (ret < 0) | |
445 | goto err_restore_page; | |
446 | } | |
447 | ||
448 | /* Enable WOL feature */ | |
449 | mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; | |
450 | val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; | |
451 | val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; | |
452 | ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val); | |
453 | if (ret < 0) | |
454 | goto err_restore_page; | |
455 | ||
456 | /* Enable WOL interrupt */ | |
457 | ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, | |
458 | YTPHY_IER_WOL); | |
459 | if (ret < 0) | |
460 | goto err_restore_page; | |
461 | ||
462 | } else { | |
463 | old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); | |
464 | if (old_page < 0) | |
465 | goto err_restore_page; | |
466 | ||
467 | /* Disable WOL feature */ | |
468 | mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; | |
469 | ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0); | |
470 | ||
471 | /* Disable WOL interrupt */ | |
472 | ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, | |
473 | YTPHY_IER_WOL, 0); | |
474 | if (ret < 0) | |
475 | goto err_restore_page; | |
476 | } | |
477 | ||
478 | err_restore_page: | |
479 | return phy_restore_page(phydev, old_page, ret); | |
480 | } | |
481 | ||
48e8c6f1 PG |
482 | static int yt8511_read_page(struct phy_device *phydev) |
483 | { | |
484 | return __phy_read(phydev, YT8511_PAGE_SELECT); | |
485 | }; | |
486 | ||
487 | static int yt8511_write_page(struct phy_device *phydev, int page) | |
488 | { | |
489 | return __phy_write(phydev, YT8511_PAGE_SELECT, page); | |
490 | }; | |
491 | ||
492 | static int yt8511_config_init(struct phy_device *phydev) | |
493 | { | |
546d6bad | 494 | int oldpage, ret = 0; |
48e8c6f1 | 495 | unsigned int ge, fe; |
48e8c6f1 | 496 | |
48e8c6f1 PG |
497 | oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE); |
498 | if (oldpage < 0) | |
499 | goto err_restore_page; | |
500 | ||
48e8c6f1 PG |
501 | /* set rgmii delay mode */ |
502 | switch (phydev->interface) { | |
503 | case PHY_INTERFACE_MODE_RGMII: | |
504 | ge = YT8511_DELAY_GE_TX_DIS; | |
505 | fe = YT8511_DELAY_FE_TX_DIS; | |
506 | break; | |
507 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
508 | ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS; | |
509 | fe = YT8511_DELAY_FE_TX_DIS; | |
510 | break; | |
511 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
512 | ge = YT8511_DELAY_GE_TX_EN; | |
513 | fe = YT8511_DELAY_FE_TX_EN; | |
514 | break; | |
515 | case PHY_INTERFACE_MODE_RGMII_ID: | |
516 | ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN; | |
517 | fe = YT8511_DELAY_FE_TX_EN; | |
518 | break; | |
0cc8bddb PG |
519 | default: /* do not support other modes */ |
520 | ret = -EOPNOTSUPP; | |
521 | goto err_restore_page; | |
48e8c6f1 PG |
522 | } |
523 | ||
524 | ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge); | |
525 | if (ret < 0) | |
526 | goto err_restore_page; | |
527 | ||
0cc8bddb PG |
528 | /* set clock mode to 125mhz */ |
529 | ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M); | |
530 | if (ret < 0) | |
531 | goto err_restore_page; | |
532 | ||
48e8c6f1 PG |
533 | /* fast ethernet delay is in a separate page */ |
534 | ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE); | |
535 | if (ret < 0) | |
536 | goto err_restore_page; | |
537 | ||
538 | ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe); | |
539 | if (ret < 0) | |
540 | goto err_restore_page; | |
541 | ||
542 | /* leave pll enabled in sleep */ | |
543 | ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL); | |
544 | if (ret < 0) | |
545 | goto err_restore_page; | |
546 | ||
547 | ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP); | |
548 | if (ret < 0) | |
549 | goto err_restore_page; | |
550 | ||
551 | err_restore_page: | |
552 | return phy_restore_page(phydev, oldpage, ret); | |
553 | } | |
554 | ||
70479a40 F |
555 | /** |
556 | * yt8521_read_page() - read reg page | |
557 | * @phydev: a pointer to a &struct phy_device | |
558 | * | |
559 | * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/ | |
560 | * YT8521_RSSR_UTP_SPACE) or negative errno code | |
561 | */ | |
562 | static int yt8521_read_page(struct phy_device *phydev) | |
563 | { | |
564 | int old_page; | |
565 | ||
566 | old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG); | |
567 | if (old_page < 0) | |
568 | return old_page; | |
569 | ||
570 | if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) | |
571 | return YT8521_RSSR_FIBER_SPACE; | |
572 | ||
573 | return YT8521_RSSR_UTP_SPACE; | |
574 | }; | |
575 | ||
576 | /** | |
577 | * yt8521_write_page() - write reg page | |
578 | * @phydev: a pointer to a &struct phy_device | |
579 | * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write. | |
580 | * | |
581 | * returns 0 or negative errno code | |
582 | */ | |
583 | static int yt8521_write_page(struct phy_device *phydev, int page) | |
584 | { | |
585 | int mask = YT8521_RSSR_SPACE_MASK; | |
586 | int set; | |
587 | ||
588 | if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) | |
589 | set = YT8521_RSSR_FIBER_SPACE; | |
590 | else | |
591 | set = YT8521_RSSR_UTP_SPACE; | |
592 | ||
593 | return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set); | |
594 | }; | |
595 | ||
596 | /** | |
597 | * yt8521_probe() - read chip config then set suitable polling_mode | |
598 | * @phydev: a pointer to a &struct phy_device | |
599 | * | |
600 | * returns 0 or negative errno code | |
601 | */ | |
602 | static int yt8521_probe(struct phy_device *phydev) | |
603 | { | |
604 | struct device *dev = &phydev->mdio.dev; | |
605 | struct yt8521_priv *priv; | |
606 | int chip_config; | |
607 | int ret; | |
608 | ||
609 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
610 | if (!priv) | |
611 | return -ENOMEM; | |
612 | ||
613 | phydev->priv = priv; | |
614 | ||
615 | chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); | |
616 | if (chip_config < 0) | |
617 | return chip_config; | |
618 | ||
619 | priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK; | |
620 | switch (priv->strap_mode) { | |
621 | case YT8521_CCR_MODE_FIBER_TO_RGMII: | |
622 | case YT8521_CCR_MODE_SGPHY_TO_RGMAC: | |
623 | case YT8521_CCR_MODE_SGMAC_TO_RGPHY: | |
624 | priv->polling_mode = YT8521_MODE_FIBER; | |
625 | priv->reg_page = YT8521_RSSR_FIBER_SPACE; | |
626 | phydev->port = PORT_FIBRE; | |
627 | break; | |
628 | case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII: | |
629 | case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO: | |
630 | case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE: | |
631 | priv->polling_mode = YT8521_MODE_POLL; | |
632 | priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; | |
633 | phydev->port = PORT_NONE; | |
634 | break; | |
635 | case YT8521_CCR_MODE_UTP_TO_SGMII: | |
636 | case YT8521_CCR_MODE_UTP_TO_RGMII: | |
637 | priv->polling_mode = YT8521_MODE_UTP; | |
638 | priv->reg_page = YT8521_RSSR_UTP_SPACE; | |
639 | phydev->port = PORT_TP; | |
640 | break; | |
641 | } | |
642 | /* set default reg space */ | |
643 | if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { | |
644 | ret = ytphy_write_ext_with_lock(phydev, | |
645 | YT8521_REG_SPACE_SELECT_REG, | |
646 | priv->reg_page); | |
647 | if (ret < 0) | |
648 | return ret; | |
649 | } | |
650 | ||
651 | return 0; | |
652 | } | |
653 | ||
813abcd9 F |
654 | /** |
655 | * yt8531s_probe() - read chip config then set suitable polling_mode | |
656 | * @phydev: a pointer to a &struct phy_device | |
657 | * | |
658 | * returns 0 or negative errno code | |
659 | */ | |
660 | static int yt8531s_probe(struct phy_device *phydev) | |
661 | { | |
662 | int ret; | |
663 | ||
664 | /* Disable SyncE clock output by default */ | |
665 | ret = ytphy_modify_ext_with_lock(phydev, YT8531S_SYNCE_CFG_REG, | |
666 | YT8531S_SCR_SYNCE_ENABLE, 0); | |
667 | if (ret < 0) | |
668 | return ret; | |
669 | ||
670 | /* same as yt8521_probe */ | |
671 | return yt8521_probe(phydev); | |
672 | } | |
673 | ||
70479a40 F |
674 | /** |
675 | * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp | |
676 | * @phydev: a pointer to a &struct phy_device | |
677 | * | |
678 | * NOTE:The caller must have taken the MDIO bus lock. | |
679 | * | |
680 | * returns 0 or negative errno code | |
681 | */ | |
682 | static int ytphy_utp_read_lpa(struct phy_device *phydev) | |
683 | { | |
684 | int lpa, lpagb; | |
685 | ||
686 | if (phydev->autoneg == AUTONEG_ENABLE) { | |
687 | if (!phydev->autoneg_complete) { | |
688 | mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, | |
689 | 0); | |
690 | mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0); | |
691 | return 0; | |
692 | } | |
693 | ||
694 | if (phydev->is_gigabit_capable) { | |
695 | lpagb = __phy_read(phydev, MII_STAT1000); | |
696 | if (lpagb < 0) | |
697 | return lpagb; | |
698 | ||
699 | if (lpagb & LPA_1000MSFAIL) { | |
700 | int adv = __phy_read(phydev, MII_CTRL1000); | |
701 | ||
702 | if (adv < 0) | |
703 | return adv; | |
704 | ||
705 | if (adv & CTL1000_ENABLE_MASTER) | |
706 | phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); | |
707 | else | |
708 | phydev_err(phydev, "Master/Slave resolution failed\n"); | |
709 | return -ENOLINK; | |
710 | } | |
711 | ||
712 | mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, | |
713 | lpagb); | |
714 | } | |
715 | ||
716 | lpa = __phy_read(phydev, MII_LPA); | |
717 | if (lpa < 0) | |
718 | return lpa; | |
719 | ||
720 | mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa); | |
721 | } else { | |
722 | linkmode_zero(phydev->lp_advertising); | |
723 | } | |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
728 | /** | |
729 | * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber | |
730 | * mode, adjust speed and duplex. | |
731 | * @phydev: a pointer to a &struct phy_device | |
732 | * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG | |
733 | * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode) | |
734 | * | |
735 | * NOTE:The caller must have taken the MDIO bus lock. | |
736 | * | |
737 | * returns 0 | |
738 | */ | |
739 | static int yt8521_adjust_status(struct phy_device *phydev, int status, | |
740 | bool is_utp) | |
741 | { | |
742 | int speed_mode, duplex; | |
743 | int speed; | |
744 | int err; | |
745 | int lpa; | |
746 | ||
747 | if (is_utp) | |
748 | duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET; | |
749 | else | |
750 | duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */ | |
751 | ||
752 | speed_mode = (status & YTPHY_SSR_SPEED_MODE_MASK) >> | |
753 | YTPHY_SSR_SPEED_MODE_OFFSET; | |
754 | ||
755 | switch (speed_mode) { | |
756 | case YTPHY_SSR_SPEED_10M: | |
757 | if (is_utp) | |
758 | speed = SPEED_10; | |
759 | else | |
760 | /* for fiber, it will never run here, default to | |
761 | * SPEED_UNKNOWN | |
762 | */ | |
763 | speed = SPEED_UNKNOWN; | |
764 | break; | |
765 | case YTPHY_SSR_SPEED_100M: | |
766 | speed = SPEED_100; | |
767 | break; | |
768 | case YTPHY_SSR_SPEED_1000M: | |
769 | speed = SPEED_1000; | |
770 | break; | |
771 | default: | |
772 | speed = SPEED_UNKNOWN; | |
773 | break; | |
774 | } | |
775 | ||
776 | phydev->speed = speed; | |
777 | phydev->duplex = duplex; | |
778 | ||
779 | if (is_utp) { | |
780 | err = ytphy_utp_read_lpa(phydev); | |
781 | if (err < 0) | |
782 | return err; | |
783 | ||
784 | phy_resolve_aneg_pause(phydev); | |
785 | } else { | |
786 | lpa = __phy_read(phydev, MII_LPA); | |
787 | if (lpa < 0) | |
788 | return lpa; | |
789 | ||
790 | /* only support 1000baseX Full */ | |
791 | linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, | |
792 | phydev->lp_advertising, lpa & LPA_1000XFULL); | |
793 | ||
794 | if (!(lpa & YTPHY_FLPA_PAUSE)) { | |
795 | phydev->pause = 0; | |
796 | phydev->asym_pause = 0; | |
797 | } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) { | |
798 | phydev->pause = 1; | |
799 | phydev->asym_pause = 1; | |
800 | } else { | |
801 | phydev->pause = 1; | |
802 | phydev->asym_pause = 0; | |
803 | } | |
804 | } | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | /** | |
810 | * yt8521_read_status_paged() - determines the speed and duplex of one page | |
811 | * @phydev: a pointer to a &struct phy_device | |
812 | * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to | |
813 | * operate. | |
814 | * | |
815 | * returns 1 (utp or fiber link),0 (no link) or negative errno code | |
816 | */ | |
817 | static int yt8521_read_status_paged(struct phy_device *phydev, int page) | |
818 | { | |
819 | int fiber_latch_val; | |
820 | int fiber_curr_val; | |
821 | int old_page; | |
822 | int ret = 0; | |
823 | int status; | |
824 | int link; | |
825 | ||
826 | linkmode_zero(phydev->lp_advertising); | |
827 | phydev->duplex = DUPLEX_UNKNOWN; | |
828 | phydev->speed = SPEED_UNKNOWN; | |
829 | phydev->asym_pause = 0; | |
830 | phydev->pause = 0; | |
831 | ||
832 | /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber | |
833 | * respectively. but for utp/fiber combo mode, reg space should be | |
834 | * arbitrated based on media priority. by default, utp takes | |
835 | * priority. reg space should be properly set before read | |
836 | * YTPHY_SPECIFIC_STATUS_REG. | |
837 | */ | |
838 | ||
839 | page &= YT8521_RSSR_SPACE_MASK; | |
840 | old_page = phy_select_page(phydev, page); | |
841 | if (old_page < 0) | |
842 | goto err_restore_page; | |
843 | ||
844 | /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex | |
845 | * of the PHY is actually using. | |
846 | */ | |
847 | ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); | |
848 | if (ret < 0) | |
849 | goto err_restore_page; | |
850 | ||
851 | status = ret; | |
852 | link = !!(status & YTPHY_SSR_LINK); | |
853 | ||
854 | /* When PHY is in fiber mode, speed transferred from 1000Mbps to | |
855 | * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so | |
856 | * we need check MII_BMSR to identify such case. | |
857 | */ | |
858 | if (page == YT8521_RSSR_FIBER_SPACE) { | |
859 | ret = __phy_read(phydev, MII_BMSR); | |
860 | if (ret < 0) | |
861 | goto err_restore_page; | |
862 | ||
863 | fiber_latch_val = ret; | |
864 | ret = __phy_read(phydev, MII_BMSR); | |
865 | if (ret < 0) | |
866 | goto err_restore_page; | |
867 | ||
868 | fiber_curr_val = ret; | |
869 | if (link && fiber_latch_val != fiber_curr_val) { | |
870 | link = 0; | |
871 | phydev_info(phydev, | |
872 | "%s, fiber link down detect, latch = %04x, curr = %04x\n", | |
873 | __func__, fiber_latch_val, fiber_curr_val); | |
874 | } | |
875 | } else { | |
876 | /* Read autonegotiation status */ | |
877 | ret = __phy_read(phydev, MII_BMSR); | |
878 | if (ret < 0) | |
879 | goto err_restore_page; | |
880 | ||
881 | phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0; | |
882 | } | |
883 | ||
884 | if (link) { | |
885 | if (page == YT8521_RSSR_UTP_SPACE) | |
886 | yt8521_adjust_status(phydev, status, true); | |
887 | else | |
888 | yt8521_adjust_status(phydev, status, false); | |
889 | } | |
890 | return phy_restore_page(phydev, old_page, link); | |
891 | ||
892 | err_restore_page: | |
893 | return phy_restore_page(phydev, old_page, ret); | |
894 | } | |
895 | ||
896 | /** | |
897 | * yt8521_read_status() - determines the negotiated speed and duplex | |
898 | * @phydev: a pointer to a &struct phy_device | |
899 | * | |
900 | * returns 0 or negative errno code | |
901 | */ | |
902 | static int yt8521_read_status(struct phy_device *phydev) | |
903 | { | |
904 | struct yt8521_priv *priv = phydev->priv; | |
905 | int link_fiber = 0; | |
906 | int link_utp; | |
907 | int link; | |
908 | int ret; | |
909 | ||
910 | if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { | |
911 | link = yt8521_read_status_paged(phydev, priv->reg_page); | |
912 | if (link < 0) | |
913 | return link; | |
914 | } else { | |
915 | /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is | |
916 | * needed. by default, utp is higher priority. | |
917 | */ | |
918 | ||
919 | link_utp = yt8521_read_status_paged(phydev, | |
920 | YT8521_RSSR_UTP_SPACE); | |
921 | if (link_utp < 0) | |
922 | return link_utp; | |
923 | ||
924 | if (!link_utp) { | |
925 | link_fiber = yt8521_read_status_paged(phydev, | |
926 | YT8521_RSSR_FIBER_SPACE); | |
927 | if (link_fiber < 0) | |
928 | return link_fiber; | |
929 | } | |
930 | ||
931 | link = link_utp || link_fiber; | |
932 | } | |
933 | ||
934 | if (link) { | |
935 | if (phydev->link == 0) { | |
936 | /* arbitrate reg space based on linkup media type. */ | |
937 | if (priv->polling_mode == YT8521_MODE_POLL && | |
938 | priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { | |
939 | if (link_fiber) | |
940 | priv->reg_page = | |
941 | YT8521_RSSR_FIBER_SPACE; | |
942 | else | |
943 | priv->reg_page = YT8521_RSSR_UTP_SPACE; | |
944 | ||
945 | ret = ytphy_write_ext_with_lock(phydev, | |
946 | YT8521_REG_SPACE_SELECT_REG, | |
947 | priv->reg_page); | |
948 | if (ret < 0) | |
949 | return ret; | |
950 | ||
951 | phydev->port = link_fiber ? PORT_FIBRE : PORT_TP; | |
952 | ||
953 | phydev_info(phydev, "%s, link up, media: %s\n", | |
954 | __func__, | |
955 | (phydev->port == PORT_TP) ? | |
956 | "UTP" : "Fiber"); | |
957 | } | |
958 | } | |
959 | phydev->link = 1; | |
960 | } else { | |
961 | if (phydev->link == 1) { | |
962 | phydev_info(phydev, "%s, link down, media: %s\n", | |
963 | __func__, (phydev->port == PORT_TP) ? | |
964 | "UTP" : "Fiber"); | |
965 | ||
966 | /* When in YT8521_MODE_POLL mode, need prepare for next | |
967 | * arbitration. | |
968 | */ | |
969 | if (priv->polling_mode == YT8521_MODE_POLL) { | |
970 | priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; | |
971 | phydev->port = PORT_NONE; | |
972 | } | |
973 | } | |
974 | ||
975 | phydev->link = 0; | |
976 | } | |
977 | ||
978 | return 0; | |
979 | } | |
980 | ||
981 | /** | |
982 | * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page | |
983 | * @phydev: the phy_device struct | |
984 | * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate | |
985 | * @mask: bit mask of bits to clear | |
986 | * @set: bit mask of bits to set | |
987 | * | |
988 | * NOTE: Convenience function which allows a PHY's BMCR register to be | |
989 | * modified as new register value = (old register value & ~mask) | set. | |
990 | * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space | |
991 | * has MII_BMCR. poll mode combines utp and faber,so need do both. | |
992 | * If it is reset, it will wait for completion. | |
993 | * | |
994 | * returns 0 or negative errno code | |
995 | */ | |
996 | static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page, | |
997 | u16 mask, u16 set) | |
998 | { | |
999 | int max_cnt = 500; /* the max wait time of reset ~ 500 ms */ | |
1000 | int old_page; | |
1001 | int ret = 0; | |
1002 | ||
1003 | old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); | |
1004 | if (old_page < 0) | |
1005 | goto err_restore_page; | |
1006 | ||
1007 | ret = __phy_modify(phydev, MII_BMCR, mask, set); | |
1008 | if (ret < 0) | |
1009 | goto err_restore_page; | |
1010 | ||
1011 | /* If it is reset, need to wait for the reset to complete */ | |
1012 | if (set == BMCR_RESET) { | |
1013 | while (max_cnt--) { | |
1014 | usleep_range(1000, 1100); | |
1015 | ret = __phy_read(phydev, MII_BMCR); | |
1016 | if (ret < 0) | |
1017 | goto err_restore_page; | |
1018 | ||
1019 | if (!(ret & BMCR_RESET)) | |
1020 | return phy_restore_page(phydev, old_page, 0); | |
1021 | } | |
1022 | } | |
1023 | ||
1024 | err_restore_page: | |
1025 | return phy_restore_page(phydev, old_page, ret); | |
1026 | } | |
1027 | ||
1028 | /** | |
1029 | * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register | |
1030 | * @phydev: the phy_device struct | |
1031 | * @mask: bit mask of bits to clear | |
1032 | * @set: bit mask of bits to set | |
1033 | * | |
1034 | * NOTE: Convenience function which allows a PHY's BMCR register to be | |
1035 | * modified as new register value = (old register value & ~mask) | set. | |
1036 | * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space | |
1037 | * has MII_BMCR. poll mode combines utp and faber,so need do both. | |
1038 | * | |
1039 | * returns 0 or negative errno code | |
1040 | */ | |
1041 | static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask, | |
1042 | u16 set) | |
1043 | { | |
1044 | struct yt8521_priv *priv = phydev->priv; | |
1045 | int ret; | |
1046 | ||
1047 | if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { | |
1048 | ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask, | |
1049 | set); | |
1050 | if (ret < 0) | |
1051 | return ret; | |
1052 | } else { | |
1053 | ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE, | |
1054 | mask, set); | |
1055 | if (ret < 0) | |
1056 | return ret; | |
1057 | ||
1058 | ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE, | |
1059 | mask, set); | |
1060 | if (ret < 0) | |
1061 | return ret; | |
1062 | } | |
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | /** | |
1067 | * yt8521_soft_reset() - called to issue a PHY software reset | |
1068 | * @phydev: a pointer to a &struct phy_device | |
1069 | * | |
1070 | * returns 0 or negative errno code | |
1071 | */ | |
1072 | static int yt8521_soft_reset(struct phy_device *phydev) | |
1073 | { | |
1074 | return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET); | |
1075 | } | |
1076 | ||
1077 | /** | |
1078 | * yt8521_suspend() - suspend the hardware | |
1079 | * @phydev: a pointer to a &struct phy_device | |
1080 | * | |
1081 | * returns 0 or negative errno code | |
1082 | */ | |
1083 | static int yt8521_suspend(struct phy_device *phydev) | |
1084 | { | |
1085 | int wol_config; | |
1086 | ||
1087 | /* YTPHY_WOL_CONFIG_REG is common ext reg */ | |
1088 | wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); | |
1089 | if (wol_config < 0) | |
1090 | return wol_config; | |
1091 | ||
1092 | /* if wol enable, do nothing */ | |
1093 | if (wol_config & YTPHY_WCR_ENABLE) | |
1094 | return 0; | |
1095 | ||
1096 | return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN); | |
1097 | } | |
1098 | ||
1099 | /** | |
1100 | * yt8521_resume() - resume the hardware | |
1101 | * @phydev: a pointer to a &struct phy_device | |
1102 | * | |
1103 | * returns 0 or negative errno code | |
1104 | */ | |
1105 | static int yt8521_resume(struct phy_device *phydev) | |
1106 | { | |
1107 | int ret; | |
1108 | int wol_config; | |
1109 | ||
1110 | /* disable auto sleep */ | |
1111 | ret = ytphy_modify_ext_with_lock(phydev, | |
1112 | YT8521_EXTREG_SLEEP_CONTROL1_REG, | |
1113 | YT8521_ESC1R_SLEEP_SW, 0); | |
1114 | if (ret < 0) | |
1115 | return ret; | |
1116 | ||
1117 | wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); | |
1118 | if (wol_config < 0) | |
1119 | return wol_config; | |
1120 | ||
1121 | /* if wol enable, do nothing */ | |
1122 | if (wol_config & YTPHY_WCR_ENABLE) | |
1123 | return 0; | |
1124 | ||
1125 | return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0); | |
1126 | } | |
1127 | ||
1128 | /** | |
1129 | * yt8521_config_init() - called to initialize the PHY | |
1130 | * @phydev: a pointer to a &struct phy_device | |
1131 | * | |
1132 | * returns 0 or negative errno code | |
1133 | */ | |
1134 | static int yt8521_config_init(struct phy_device *phydev) | |
1135 | { | |
1136 | int old_page; | |
1137 | int ret = 0; | |
1138 | u16 val; | |
1139 | ||
1140 | old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); | |
1141 | if (old_page < 0) | |
1142 | goto err_restore_page; | |
1143 | ||
1144 | switch (phydev->interface) { | |
1145 | case PHY_INTERFACE_MODE_RGMII: | |
4e0243e7 | 1146 | val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS; |
70479a40 F |
1147 | val |= YT8521_RC1R_RX_DELAY_DIS; |
1148 | break; | |
1149 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
4e0243e7 | 1150 | val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS; |
70479a40 F |
1151 | val |= YT8521_RC1R_RX_DELAY_EN; |
1152 | break; | |
1153 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
4e0243e7 | 1154 | val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN; |
70479a40 F |
1155 | val |= YT8521_RC1R_RX_DELAY_DIS; |
1156 | break; | |
1157 | case PHY_INTERFACE_MODE_RGMII_ID: | |
4e0243e7 | 1158 | val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN; |
70479a40 F |
1159 | val |= YT8521_RC1R_RX_DELAY_EN; |
1160 | break; | |
1161 | case PHY_INTERFACE_MODE_SGMII: | |
1162 | break; | |
1163 | default: /* do not support other modes */ | |
1164 | ret = -EOPNOTSUPP; | |
1165 | goto err_restore_page; | |
1166 | } | |
1167 | ||
1168 | /* set rgmii delay mode */ | |
1169 | if (phydev->interface != PHY_INTERFACE_MODE_SGMII) { | |
1170 | ret = ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, | |
1171 | (YT8521_RC1R_RX_DELAY_MASK | | |
1172 | YT8521_RC1R_FE_TX_DELAY_MASK | | |
1173 | YT8521_RC1R_GE_TX_DELAY_MASK), | |
1174 | val); | |
1175 | if (ret < 0) | |
1176 | goto err_restore_page; | |
1177 | } | |
1178 | ||
1179 | /* disable auto sleep */ | |
1180 | ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG, | |
1181 | YT8521_ESC1R_SLEEP_SW, 0); | |
1182 | if (ret < 0) | |
1183 | goto err_restore_page; | |
1184 | ||
1185 | /* enable RXC clock when no wire plug */ | |
1186 | ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG, | |
1187 | YT8521_CGR_RX_CLK_EN, 0); | |
1188 | if (ret < 0) | |
1189 | goto err_restore_page; | |
1190 | ||
1191 | err_restore_page: | |
1192 | return phy_restore_page(phydev, old_page, ret); | |
1193 | } | |
1194 | ||
1195 | /** | |
1196 | * yt8521_prepare_fiber_features() - A small helper function that setup | |
1197 | * fiber's features. | |
1198 | * @phydev: a pointer to a &struct phy_device | |
1199 | * @dst: a pointer to store fiber's features | |
1200 | */ | |
1201 | static void yt8521_prepare_fiber_features(struct phy_device *phydev, | |
1202 | unsigned long *dst) | |
1203 | { | |
1204 | linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst); | |
1205 | linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst); | |
1206 | linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst); | |
1207 | linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst); | |
1208 | } | |
1209 | ||
1210 | /** | |
1211 | * yt8521_fiber_setup_forced - configures/forces speed from @phydev | |
1212 | * @phydev: target phy_device struct | |
1213 | * | |
1214 | * NOTE:The caller must have taken the MDIO bus lock. | |
1215 | * | |
1216 | * returns 0 or negative errno code | |
1217 | */ | |
1218 | static int yt8521_fiber_setup_forced(struct phy_device *phydev) | |
1219 | { | |
1220 | u16 val; | |
1221 | int ret; | |
1222 | ||
1223 | if (phydev->speed == SPEED_1000) | |
1224 | val = YTPHY_MCR_FIBER_1000BX; | |
1225 | else if (phydev->speed == SPEED_100) | |
1226 | val = YTPHY_MCR_FIBER_100FX; | |
1227 | else | |
1228 | return -EINVAL; | |
1229 | ||
1230 | ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); | |
1231 | if (ret < 0) | |
1232 | return ret; | |
1233 | ||
1234 | /* disable Fiber auto sensing */ | |
1235 | ret = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, | |
1236 | YT8521_LTCR_EN_AUTOSEN, 0); | |
1237 | if (ret < 0) | |
1238 | return ret; | |
1239 | ||
1240 | ret = ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG, | |
1241 | YTPHY_MCR_FIBER_SPEED_MASK, val); | |
1242 | if (ret < 0) | |
1243 | return ret; | |
1244 | ||
1245 | return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, | |
1246 | YT8521_CCR_SW_RST, 0); | |
1247 | } | |
1248 | ||
1249 | /** | |
1250 | * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation | |
1251 | * @phydev: target phy_device struct | |
1252 | * @restart: whether aneg restart is requested | |
1253 | * | |
1254 | * NOTE:The caller must have taken the MDIO bus lock. | |
1255 | * | |
1256 | * returns 0 or negative errno code | |
1257 | */ | |
1258 | static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart) | |
1259 | { | |
1260 | int ret; | |
1261 | ||
1262 | if (!restart) { | |
1263 | /* Advertisement hasn't changed, but maybe aneg was never on to | |
1264 | * begin with? Or maybe phy was isolated? | |
1265 | */ | |
1266 | ret = __phy_read(phydev, MII_BMCR); | |
1267 | if (ret < 0) | |
1268 | return ret; | |
1269 | ||
1270 | if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE)) | |
1271 | restart = true; | |
1272 | } | |
1273 | /* Enable and Restart Autonegotiation | |
1274 | * Don't isolate the PHY if we're negotiating | |
1275 | */ | |
1276 | if (restart) | |
1277 | return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, | |
1278 | BMCR_ANENABLE | BMCR_ANRESTART); | |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
1283 | /** | |
1284 | * yt8521_fiber_config_aneg - restart auto-negotiation or write | |
1285 | * YTPHY_MISC_CONFIG_REG. | |
1286 | * @phydev: target phy_device struct | |
1287 | * | |
1288 | * NOTE:The caller must have taken the MDIO bus lock. | |
1289 | * | |
1290 | * returns 0 or negative errno code | |
1291 | */ | |
1292 | static int yt8521_fiber_config_aneg(struct phy_device *phydev) | |
1293 | { | |
1294 | int err, changed = 0; | |
1295 | int bmcr; | |
1296 | u16 adv; | |
1297 | ||
1298 | if (phydev->autoneg != AUTONEG_ENABLE) | |
1299 | return yt8521_fiber_setup_forced(phydev); | |
1300 | ||
1301 | /* enable Fiber auto sensing */ | |
1302 | err = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, | |
1303 | 0, YT8521_LTCR_EN_AUTOSEN); | |
1304 | if (err < 0) | |
1305 | return err; | |
1306 | ||
1307 | err = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, | |
1308 | YT8521_CCR_SW_RST, 0); | |
1309 | if (err < 0) | |
1310 | return err; | |
1311 | ||
1312 | bmcr = __phy_read(phydev, MII_BMCR); | |
1313 | if (bmcr < 0) | |
1314 | return bmcr; | |
1315 | ||
1316 | /* When it is coming from fiber forced mode, add bmcr power down | |
1317 | * and power up to let aneg work fine. | |
1318 | */ | |
1319 | if (!(bmcr & BMCR_ANENABLE)) { | |
1320 | __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); | |
1321 | usleep_range(1000, 1100); | |
1322 | __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); | |
1323 | } | |
1324 | ||
1325 | adv = linkmode_adv_to_mii_adv_x(phydev->advertising, | |
1326 | ETHTOOL_LINK_MODE_1000baseX_Full_BIT); | |
1327 | ||
1328 | /* Setup fiber advertisement */ | |
1329 | err = __phy_modify_changed(phydev, MII_ADVERTISE, | |
1330 | ADVERTISE_1000XHALF | ADVERTISE_1000XFULL | | |
1331 | ADVERTISE_1000XPAUSE | | |
1332 | ADVERTISE_1000XPSE_ASYM, | |
1333 | adv); | |
1334 | if (err < 0) | |
1335 | return err; | |
1336 | ||
1337 | if (err > 0) | |
1338 | changed = 1; | |
1339 | ||
1340 | return ytphy_check_and_restart_aneg(phydev, changed); | |
1341 | } | |
1342 | ||
1343 | /** | |
1344 | * ytphy_setup_master_slave | |
1345 | * @phydev: target phy_device struct | |
1346 | * | |
1347 | * NOTE: The caller must have taken the MDIO bus lock. | |
1348 | * | |
1349 | * returns 0 or negative errno code | |
1350 | */ | |
1351 | static int ytphy_setup_master_slave(struct phy_device *phydev) | |
1352 | { | |
1353 | u16 ctl = 0; | |
1354 | ||
1355 | if (!phydev->is_gigabit_capable) | |
1356 | return 0; | |
1357 | ||
1358 | switch (phydev->master_slave_set) { | |
1359 | case MASTER_SLAVE_CFG_MASTER_PREFERRED: | |
1360 | ctl |= CTL1000_PREFER_MASTER; | |
1361 | break; | |
1362 | case MASTER_SLAVE_CFG_SLAVE_PREFERRED: | |
1363 | break; | |
1364 | case MASTER_SLAVE_CFG_MASTER_FORCE: | |
1365 | ctl |= CTL1000_AS_MASTER; | |
1366 | fallthrough; | |
1367 | case MASTER_SLAVE_CFG_SLAVE_FORCE: | |
1368 | ctl |= CTL1000_ENABLE_MASTER; | |
1369 | break; | |
1370 | case MASTER_SLAVE_CFG_UNKNOWN: | |
1371 | case MASTER_SLAVE_CFG_UNSUPPORTED: | |
1372 | return 0; | |
1373 | default: | |
1374 | phydev_warn(phydev, "Unsupported Master/Slave mode\n"); | |
1375 | return -EOPNOTSUPP; | |
1376 | } | |
1377 | ||
1378 | return __phy_modify_changed(phydev, MII_CTRL1000, | |
1379 | (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER | | |
1380 | CTL1000_PREFER_MASTER), ctl); | |
1381 | } | |
1382 | ||
1383 | /** | |
1384 | * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters | |
1385 | * @phydev: target phy_device struct | |
1386 | * | |
1387 | * NOTE: Writes MII_ADVERTISE with the appropriate values, | |
1388 | * after sanitizing the values to make sure we only advertise | |
1389 | * what is supported. Returns < 0 on error, 0 if the PHY's advertisement | |
1390 | * hasn't changed, and > 0 if it has changed. | |
1391 | * The caller must have taken the MDIO bus lock. | |
1392 | * | |
1393 | * returns 0 or negative errno code | |
1394 | */ | |
1395 | static int ytphy_utp_config_advert(struct phy_device *phydev) | |
1396 | { | |
1397 | int err, bmsr, changed = 0; | |
1398 | u32 adv; | |
1399 | ||
1400 | /* Only allow advertising what this PHY supports */ | |
1401 | linkmode_and(phydev->advertising, phydev->advertising, | |
1402 | phydev->supported); | |
1403 | ||
1404 | adv = linkmode_adv_to_mii_adv_t(phydev->advertising); | |
1405 | ||
1406 | /* Setup standard advertisement */ | |
1407 | err = __phy_modify_changed(phydev, MII_ADVERTISE, | |
1408 | ADVERTISE_ALL | ADVERTISE_100BASE4 | | |
1409 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, | |
1410 | adv); | |
1411 | if (err < 0) | |
1412 | return err; | |
1413 | if (err > 0) | |
1414 | changed = 1; | |
1415 | ||
1416 | bmsr = __phy_read(phydev, MII_BMSR); | |
1417 | if (bmsr < 0) | |
1418 | return bmsr; | |
1419 | ||
1420 | /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all | |
1421 | * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a | |
1422 | * logical 1. | |
1423 | */ | |
1424 | if (!(bmsr & BMSR_ESTATEN)) | |
1425 | return changed; | |
1426 | ||
1427 | adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); | |
1428 | ||
1429 | err = __phy_modify_changed(phydev, MII_CTRL1000, | |
1430 | ADVERTISE_1000FULL | ADVERTISE_1000HALF, | |
1431 | adv); | |
1432 | if (err < 0) | |
1433 | return err; | |
1434 | if (err > 0) | |
1435 | changed = 1; | |
1436 | ||
1437 | return changed; | |
1438 | } | |
1439 | ||
1440 | /** | |
1441 | * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR | |
1442 | * @phydev: target phy_device struct | |
1443 | * @changed: whether autoneg is requested | |
1444 | * | |
1445 | * NOTE: If auto-negotiation is enabled, we configure the | |
1446 | * advertising, and then restart auto-negotiation. If it is not | |
1447 | * enabled, then we write the BMCR. | |
1448 | * The caller must have taken the MDIO bus lock. | |
1449 | * | |
1450 | * returns 0 or negative errno code | |
1451 | */ | |
1452 | static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed) | |
1453 | { | |
1454 | int err; | |
1455 | u16 ctl; | |
1456 | ||
1457 | err = ytphy_setup_master_slave(phydev); | |
1458 | if (err < 0) | |
1459 | return err; | |
1460 | else if (err) | |
1461 | changed = true; | |
1462 | ||
1463 | if (phydev->autoneg != AUTONEG_ENABLE) { | |
1464 | /* configures/forces speed/duplex from @phydev */ | |
1465 | ||
1466 | ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex); | |
1467 | ||
1468 | return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK | | |
1469 | BMCR_ISOLATE | BMCR_PDOWN), ctl); | |
1470 | } | |
1471 | ||
1472 | err = ytphy_utp_config_advert(phydev); | |
1473 | if (err < 0) /* error */ | |
1474 | return err; | |
1475 | else if (err) | |
1476 | changed = true; | |
1477 | ||
1478 | return ytphy_check_and_restart_aneg(phydev, changed); | |
1479 | } | |
1480 | ||
1481 | /** | |
1482 | * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg | |
1483 | * of one page | |
1484 | * @phydev: a pointer to a &struct phy_device | |
1485 | * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to | |
1486 | * operate. | |
1487 | * | |
1488 | * returns 0 or negative errno code | |
1489 | */ | |
1490 | static int yt8521_config_aneg_paged(struct phy_device *phydev, int page) | |
1491 | { | |
1492 | __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported); | |
1493 | struct yt8521_priv *priv = phydev->priv; | |
1494 | int old_page; | |
1495 | int ret = 0; | |
1496 | ||
1497 | page &= YT8521_RSSR_SPACE_MASK; | |
1498 | ||
1499 | old_page = phy_select_page(phydev, page); | |
1500 | if (old_page < 0) | |
1501 | goto err_restore_page; | |
1502 | ||
1503 | /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, | |
1504 | * phydev->advertising should be updated. | |
1505 | */ | |
1506 | if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { | |
1507 | linkmode_zero(fiber_supported); | |
1508 | yt8521_prepare_fiber_features(phydev, fiber_supported); | |
1509 | ||
1510 | /* prepare fiber_supported, then setup advertising. */ | |
1511 | if (page == YT8521_RSSR_FIBER_SPACE) { | |
1512 | linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, | |
1513 | fiber_supported); | |
1514 | linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, | |
1515 | fiber_supported); | |
1516 | linkmode_and(phydev->advertising, | |
1517 | priv->combo_advertising, fiber_supported); | |
1518 | } else { | |
1519 | /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */ | |
1520 | linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, | |
1521 | fiber_supported); | |
1522 | linkmode_andnot(phydev->advertising, | |
1523 | priv->combo_advertising, | |
1524 | fiber_supported); | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | if (page == YT8521_RSSR_FIBER_SPACE) | |
1529 | ret = yt8521_fiber_config_aneg(phydev); | |
1530 | else | |
1531 | ret = ytphy_utp_config_aneg(phydev, false); | |
1532 | ||
1533 | err_restore_page: | |
1534 | return phy_restore_page(phydev, old_page, ret); | |
1535 | } | |
1536 | ||
1537 | /** | |
1538 | * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged | |
1539 | * @phydev: a pointer to a &struct phy_device | |
1540 | * | |
1541 | * returns 0 or negative errno code | |
1542 | */ | |
1543 | static int yt8521_config_aneg(struct phy_device *phydev) | |
1544 | { | |
1545 | struct yt8521_priv *priv = phydev->priv; | |
1546 | int ret; | |
1547 | ||
1548 | if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { | |
1549 | ret = yt8521_config_aneg_paged(phydev, priv->reg_page); | |
1550 | if (ret < 0) | |
1551 | return ret; | |
1552 | } else { | |
1553 | /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, | |
1554 | * phydev->advertising need to be saved at first run. | |
1555 | * Because it contains the advertising which supported by both | |
1556 | * mac and yt8521(utp and fiber). | |
1557 | */ | |
1558 | if (linkmode_empty(priv->combo_advertising)) { | |
1559 | linkmode_copy(priv->combo_advertising, | |
1560 | phydev->advertising); | |
1561 | } | |
1562 | ||
1563 | ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE); | |
1564 | if (ret < 0) | |
1565 | return ret; | |
1566 | ||
1567 | ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE); | |
1568 | if (ret < 0) | |
1569 | return ret; | |
1570 | ||
1571 | /* we don't known which will be link, so restore | |
1572 | * phydev->advertising as default value. | |
1573 | */ | |
1574 | linkmode_copy(phydev->advertising, priv->combo_advertising); | |
1575 | } | |
1576 | return 0; | |
1577 | } | |
1578 | ||
1579 | /** | |
1580 | * yt8521_aneg_done_paged() - determines the auto negotiation result of one | |
1581 | * page. | |
1582 | * @phydev: a pointer to a &struct phy_device | |
1583 | * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to | |
1584 | * operate. | |
1585 | * | |
1586 | * returns 0(no link)or 1(fiber or utp link) or negative errno code | |
1587 | */ | |
1588 | static int yt8521_aneg_done_paged(struct phy_device *phydev, int page) | |
1589 | { | |
1590 | int old_page; | |
1591 | int ret = 0; | |
1592 | int link; | |
1593 | ||
1594 | old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); | |
1595 | if (old_page < 0) | |
1596 | goto err_restore_page; | |
1597 | ||
1598 | ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); | |
1599 | if (ret < 0) | |
1600 | goto err_restore_page; | |
1601 | ||
1602 | link = !!(ret & YTPHY_SSR_LINK); | |
1603 | ret = link; | |
1604 | ||
1605 | err_restore_page: | |
1606 | return phy_restore_page(phydev, old_page, ret); | |
1607 | } | |
1608 | ||
1609 | /** | |
1610 | * yt8521_aneg_done() - determines the auto negotiation result | |
1611 | * @phydev: a pointer to a &struct phy_device | |
1612 | * | |
1613 | * returns 0(no link)or 1(fiber or utp link) or negative errno code | |
1614 | */ | |
1615 | static int yt8521_aneg_done(struct phy_device *phydev) | |
1616 | { | |
1617 | struct yt8521_priv *priv = phydev->priv; | |
1618 | int link_fiber = 0; | |
1619 | int link_utp; | |
1620 | int link; | |
1621 | ||
1622 | if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { | |
1623 | link = yt8521_aneg_done_paged(phydev, priv->reg_page); | |
1624 | } else { | |
1625 | link_utp = yt8521_aneg_done_paged(phydev, | |
1626 | YT8521_RSSR_UTP_SPACE); | |
1627 | if (link_utp < 0) | |
1628 | return link_utp; | |
1629 | ||
1630 | if (!link_utp) { | |
1631 | link_fiber = yt8521_aneg_done_paged(phydev, | |
1632 | YT8521_RSSR_FIBER_SPACE); | |
1633 | if (link_fiber < 0) | |
1634 | return link_fiber; | |
1635 | } | |
1636 | link = link_fiber || link_utp; | |
1637 | phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n", | |
1638 | __func__, link_fiber, link_utp); | |
1639 | } | |
1640 | ||
1641 | return link; | |
1642 | } | |
1643 | ||
1644 | /** | |
1645 | * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers | |
1646 | * @phydev: target phy_device struct | |
1647 | * | |
1648 | * NOTE: Reads the PHY's abilities and populates | |
1649 | * phydev->supported accordingly. | |
1650 | * The caller must have taken the MDIO bus lock. | |
1651 | * | |
1652 | * returns 0 or negative errno code | |
1653 | */ | |
1654 | static int ytphy_utp_read_abilities(struct phy_device *phydev) | |
1655 | { | |
1656 | int val; | |
1657 | ||
1658 | linkmode_set_bit_array(phy_basic_ports_array, | |
1659 | ARRAY_SIZE(phy_basic_ports_array), | |
1660 | phydev->supported); | |
1661 | ||
1662 | val = __phy_read(phydev, MII_BMSR); | |
1663 | if (val < 0) | |
1664 | return val; | |
1665 | ||
1666 | linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported, | |
1667 | val & BMSR_ANEGCAPABLE); | |
1668 | ||
1669 | linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported, | |
1670 | val & BMSR_100FULL); | |
1671 | linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported, | |
1672 | val & BMSR_100HALF); | |
1673 | linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported, | |
1674 | val & BMSR_10FULL); | |
1675 | linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported, | |
1676 | val & BMSR_10HALF); | |
1677 | ||
1678 | if (val & BMSR_ESTATEN) { | |
1679 | val = __phy_read(phydev, MII_ESTATUS); | |
1680 | if (val < 0) | |
1681 | return val; | |
1682 | ||
1683 | linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, | |
1684 | phydev->supported, val & ESTATUS_1000_TFULL); | |
1685 | linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, | |
1686 | phydev->supported, val & ESTATUS_1000_THALF); | |
1687 | linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, | |
1688 | phydev->supported, val & ESTATUS_1000_XFULL); | |
1689 | } | |
1690 | ||
1691 | return 0; | |
1692 | } | |
1693 | ||
1694 | /** | |
1695 | * yt8521_get_features_paged() - read supported link modes for one page | |
1696 | * @phydev: a pointer to a &struct phy_device | |
1697 | * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to | |
1698 | * operate. | |
1699 | * | |
1700 | * returns 0 or negative errno code | |
1701 | */ | |
1702 | static int yt8521_get_features_paged(struct phy_device *phydev, int page) | |
1703 | { | |
1704 | int old_page; | |
1705 | int ret = 0; | |
1706 | ||
1707 | page &= YT8521_RSSR_SPACE_MASK; | |
1708 | old_page = phy_select_page(phydev, page); | |
1709 | if (old_page < 0) | |
1710 | goto err_restore_page; | |
1711 | ||
1712 | if (page == YT8521_RSSR_FIBER_SPACE) { | |
1713 | linkmode_zero(phydev->supported); | |
1714 | yt8521_prepare_fiber_features(phydev, phydev->supported); | |
1715 | } else { | |
1716 | ret = ytphy_utp_read_abilities(phydev); | |
1717 | if (ret < 0) | |
1718 | goto err_restore_page; | |
1719 | } | |
1720 | ||
1721 | err_restore_page: | |
1722 | return phy_restore_page(phydev, old_page, ret); | |
1723 | } | |
1724 | ||
1725 | /** | |
1726 | * yt8521_get_features - switch reg space then call yt8521_get_features_paged | |
1727 | * @phydev: target phy_device struct | |
1728 | * | |
1729 | * returns 0 or negative errno code | |
1730 | */ | |
1731 | static int yt8521_get_features(struct phy_device *phydev) | |
1732 | { | |
1733 | struct yt8521_priv *priv = phydev->priv; | |
1734 | int ret; | |
1735 | ||
1736 | if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { | |
1737 | ret = yt8521_get_features_paged(phydev, priv->reg_page); | |
1738 | } else { | |
1739 | ret = yt8521_get_features_paged(phydev, | |
1740 | YT8521_RSSR_UTP_SPACE); | |
1741 | if (ret < 0) | |
1742 | return ret; | |
1743 | ||
1744 | /* add fiber's features to phydev->supported */ | |
1745 | yt8521_prepare_fiber_features(phydev, phydev->supported); | |
1746 | } | |
1747 | return ret; | |
1748 | } | |
1749 | ||
48e8c6f1 PG |
1750 | static struct phy_driver motorcomm_phy_drvs[] = { |
1751 | { | |
1752 | PHY_ID_MATCH_EXACT(PHY_ID_YT8511), | |
1753 | .name = "YT8511 Gigabit Ethernet", | |
1754 | .config_init = yt8511_config_init, | |
1755 | .suspend = genphy_suspend, | |
1756 | .resume = genphy_resume, | |
1757 | .read_page = yt8511_read_page, | |
1758 | .write_page = yt8511_write_page, | |
1759 | }, | |
70479a40 F |
1760 | { |
1761 | PHY_ID_MATCH_EXACT(PHY_ID_YT8521), | |
1762 | .name = "YT8521 Gigabit Ethernet", | |
1763 | .get_features = yt8521_get_features, | |
1764 | .probe = yt8521_probe, | |
1765 | .read_page = yt8521_read_page, | |
1766 | .write_page = yt8521_write_page, | |
1767 | .get_wol = ytphy_get_wol, | |
1768 | .set_wol = ytphy_set_wol, | |
1769 | .config_aneg = yt8521_config_aneg, | |
1770 | .aneg_done = yt8521_aneg_done, | |
1771 | .config_init = yt8521_config_init, | |
1772 | .read_status = yt8521_read_status, | |
1773 | .soft_reset = yt8521_soft_reset, | |
1774 | .suspend = yt8521_suspend, | |
1775 | .resume = yt8521_resume, | |
1776 | }, | |
813abcd9 F |
1777 | { |
1778 | PHY_ID_MATCH_EXACT(PHY_ID_YT8531S), | |
1779 | .name = "YT8531S Gigabit Ethernet", | |
1780 | .get_features = yt8521_get_features, | |
1781 | .probe = yt8531s_probe, | |
1782 | .read_page = yt8521_read_page, | |
1783 | .write_page = yt8521_write_page, | |
1784 | .get_wol = ytphy_get_wol, | |
1785 | .set_wol = ytphy_set_wol, | |
1786 | .config_aneg = yt8521_config_aneg, | |
1787 | .aneg_done = yt8521_aneg_done, | |
1788 | .config_init = yt8521_config_init, | |
1789 | .read_status = yt8521_read_status, | |
1790 | .soft_reset = yt8521_soft_reset, | |
1791 | .suspend = yt8521_suspend, | |
1792 | .resume = yt8521_resume, | |
1793 | }, | |
48e8c6f1 PG |
1794 | }; |
1795 | ||
1796 | module_phy_driver(motorcomm_phy_drvs); | |
1797 | ||
813abcd9 | 1798 | MODULE_DESCRIPTION("Motorcomm 8511/8521/8531S PHY driver"); |
48e8c6f1 | 1799 | MODULE_AUTHOR("Peter Geis"); |
70479a40 | 1800 | MODULE_AUTHOR("Frank"); |
48e8c6f1 PG |
1801 | MODULE_LICENSE("GPL"); |
1802 | ||
1803 | static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = { | |
1804 | { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) }, | |
70479a40 | 1805 | { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) }, |
813abcd9 | 1806 | { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) }, |
48e8c6f1 PG |
1807 | { /* sentinal */ } |
1808 | }; | |
1809 | ||
1810 | MODULE_DEVICE_TABLE(mdio, motorcomm_tbl); |