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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux
[linux-2.6-block.git] / drivers / net / phy / micrel.c
CommitLineData
d0507009
DC		 1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
7ab59dc1 8 * Copyright (c) 2010-2013 Micrel, Inc.
d0507009
DC		 9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
7ab59dc1
DC		 15 * Support : Micrel Phys:
16 * Giga phys: ksz9021, ksz9031
17 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
18 * ksz8021, ksz8031, ksz8051,
19 * ksz8081, ksz8091,
20 * ksz8061,
21 * Switch : ksz8873, ksz886x
d0507009
DC		 22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
d606ef3f 27#include <linux/micrel_phy.h>
954c3967 28#include <linux/of.h>
1fadee0c 29#include <linux/clk.h>
d0507009 30
212ea99a
MV		 31/* Operation Mode Strap Override */
32#define MII_KSZPHY_OMSO 0x16
33#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
34#define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
35#define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
36
51f932c4
CD		 37/* general Interrupt control/status reg in vendor specific block. */
38#define MII_KSZPHY_INTCS 0x1B
39#define KSZPHY_INTCS_JABBER (1 << 15)
40#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
41#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
42#define KSZPHY_INTCS_PARELLEL (1 << 12)
43#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
44#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
45#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
46#define KSZPHY_INTCS_LINK_UP (1 << 8)
47#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
48 KSZPHY_INTCS_LINK_DOWN)
49
50/* general PHY control reg in vendor specific block. */
51#define MII_KSZPHY_CTRL 0x1F
52/* bitmap of PHY register to set interrupt mode */
53#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
54#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
55#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
d606ef3f 56#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
51f932c4 57
954c3967
SC		 58/* Write/read to/from extended registers */
59#define MII_KSZPHY_EXTREG 0x0b
60#define KSZPHY_EXTREG_WRITE 0x8000
61
62#define MII_KSZPHY_EXTREG_WRITE 0x0c
63#define MII_KSZPHY_EXTREG_READ 0x0d
64
65/* Extended registers */
66#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
67#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
68#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
69
70#define PS_TO_REG 200
71
b6bb4dfc
HP		 72static int ksz_config_flags(struct phy_device *phydev)
73{
74 int regval;
75
1fadee0c 76 if (phydev->dev_flags & (MICREL_PHY_50MHZ_CLK | MICREL_PHY_25MHZ_CLK)) {
b6bb4dfc 77 regval = phy_read(phydev, MII_KSZPHY_CTRL);
1fadee0c
SH		 78 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK)
79 regval |= KSZ8051_RMII_50MHZ_CLK;
80 else
81 regval &= ~KSZ8051_RMII_50MHZ_CLK;
b6bb4dfc
HP		 82 return phy_write(phydev, MII_KSZPHY_CTRL, regval);
83 }
84 return 0;
85}
86
954c3967 87static int kszphy_extended_write(struct phy_device *phydev,
756b5089 88 u32 regnum, u16 val)
954c3967
SC		 89{
90 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
91 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
92}
93
94static int kszphy_extended_read(struct phy_device *phydev,
756b5089 95 u32 regnum)
954c3967
SC		 96{
97 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
98 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
99}
100
51f932c4
CD		 101static int kszphy_ack_interrupt(struct phy_device *phydev)
102{
103 /* bit[7..0] int status, which is a read and clear register. */
104 int rc;
105
106 rc = phy_read(phydev, MII_KSZPHY_INTCS);
107
108 return (rc < 0) ? rc : 0;
109}
110
111static int kszphy_set_interrupt(struct phy_device *phydev)
112{
113 int temp;
114 temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
115 KSZPHY_INTCS_ALL : 0;
116 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
117}
118
119static int kszphy_config_intr(struct phy_device *phydev)
120{
121 int temp, rc;
122
123 /* set the interrupt pin active low */
124 temp = phy_read(phydev, MII_KSZPHY_CTRL);
125 temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
126 phy_write(phydev, MII_KSZPHY_CTRL, temp);
127 rc = kszphy_set_interrupt(phydev);
128 return rc < 0 ? rc : 0;
129}
130
131static int ksz9021_config_intr(struct phy_device *phydev)
132{
133 int temp, rc;
134
135 /* set the interrupt pin active low */
136 temp = phy_read(phydev, MII_KSZPHY_CTRL);
137 temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
138 phy_write(phydev, MII_KSZPHY_CTRL, temp);
139 rc = kszphy_set_interrupt(phydev);
140 return rc < 0 ? rc : 0;
141}
142
143static int ks8737_config_intr(struct phy_device *phydev)
144{
145 int temp, rc;
146
147 /* set the interrupt pin active low */
148 temp = phy_read(phydev, MII_KSZPHY_CTRL);
149 temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
150 phy_write(phydev, MII_KSZPHY_CTRL, temp);
151 rc = kszphy_set_interrupt(phydev);
152 return rc < 0 ? rc : 0;
153}
d0507009 154
20d8435a
BD		 155static int kszphy_setup_led(struct phy_device *phydev,
156 unsigned int reg, unsigned int shift)
157{
158
159 struct device *dev = &phydev->dev;
160 struct device_node *of_node = dev->of_node;
161 int rc, temp;
162 u32 val;
163
164 if (!of_node && dev->parent->of_node)
165 of_node = dev->parent->of_node;
166
167 if (of_property_read_u32(of_node, "micrel,led-mode", &val))
168 return 0;
169
170 temp = phy_read(phydev, reg);
171 if (temp < 0)
172 return temp;
173
28bdc499 174 temp &= ~(3 << shift);
20d8435a
BD		 175 temp |= val << shift;
176 rc = phy_write(phydev, reg, temp);
177
178 return rc < 0 ? rc : 0;
179}
180
d0507009
DC		 181static int kszphy_config_init(struct phy_device *phydev)
182{
183 return 0;
184}
185
20d8435a
BD		 186static int kszphy_config_init_led8041(struct phy_device *phydev)
187{
188 /* single led control, register 0x1e bits 15..14 */
189 return kszphy_setup_led(phydev, 0x1e, 14);
190}
191
212ea99a
MV		 192static int ksz8021_config_init(struct phy_device *phydev)
193{
194 const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
20d8435a
BD		 195 int rc;
196
197 rc = kszphy_setup_led(phydev, 0x1f, 4);
198 if (rc)
199 dev_err(&phydev->dev, "failed to set led mode\n");
200
b6bb4dfc 201 rc = ksz_config_flags(phydev);
b838b4ac
BT		 202 if (rc < 0)
203 return rc;
204 rc = phy_write(phydev, MII_KSZPHY_OMSO, val);
b6bb4dfc 205 return rc < 0 ? rc : 0;
212ea99a
MV		 206}
207
d606ef3f
BS		 208static int ks8051_config_init(struct phy_device *phydev)
209{
b6bb4dfc 210 int rc;
d606ef3f 211
20d8435a
BD		 212 rc = kszphy_setup_led(phydev, 0x1f, 4);
213 if (rc)
214 dev_err(&phydev->dev, "failed to set led mode\n");
215
b6bb4dfc
HP		 216 rc = ksz_config_flags(phydev);
217 return rc < 0 ? rc : 0;
d606ef3f
BS		 218}
219
954c3967
SC		 220static int ksz9021_load_values_from_of(struct phy_device *phydev,
221 struct device_node *of_node, u16 reg,
222 char *field1, char *field2,
223 char *field3, char *field4)
224{
225 int val1 = -1;
226 int val2 = -2;
227 int val3 = -3;
228 int val4 = -4;
229 int newval;
230 int matches = 0;
231
232 if (!of_property_read_u32(of_node, field1, &val1))
233 matches++;
234
235 if (!of_property_read_u32(of_node, field2, &val2))
236 matches++;
237
238 if (!of_property_read_u32(of_node, field3, &val3))
239 matches++;
240
241 if (!of_property_read_u32(of_node, field4, &val4))
242 matches++;
243
244 if (!matches)
245 return 0;
246
247 if (matches < 4)
248 newval = kszphy_extended_read(phydev, reg);
249 else
250 newval = 0;
251
252 if (val1 != -1)
253 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
254
6a119745 255 if (val2 != -2)
954c3967
SC		 256 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
257
6a119745 258 if (val3 != -3)
954c3967
SC		 259 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
260
6a119745 261 if (val4 != -4)
954c3967
SC		 262 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
263
264 return kszphy_extended_write(phydev, reg, newval);
265}
266
267static int ksz9021_config_init(struct phy_device *phydev)
268{
269 struct device *dev = &phydev->dev;
270 struct device_node *of_node = dev->of_node;
271
272 if (!of_node && dev->parent->of_node)
273 of_node = dev->parent->of_node;
274
275 if (of_node) {
276 ksz9021_load_values_from_of(phydev, of_node,
277 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
278 "txen-skew-ps", "txc-skew-ps",
279 "rxdv-skew-ps", "rxc-skew-ps");
280 ksz9021_load_values_from_of(phydev, of_node,
281 MII_KSZPHY_RX_DATA_PAD_SKEW,
282 "rxd0-skew-ps", "rxd1-skew-ps",
283 "rxd2-skew-ps", "rxd3-skew-ps");
284 ksz9021_load_values_from_of(phydev, of_node,
285 MII_KSZPHY_TX_DATA_PAD_SKEW,
286 "txd0-skew-ps", "txd1-skew-ps",
287 "txd2-skew-ps", "txd3-skew-ps");
288 }
289 return 0;
290}
291
6e4b8273
HC		 292#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
293#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
294#define OP_DATA 1
295#define KSZ9031_PS_TO_REG 60
296
297/* Extended registers */
298#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
299#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
300#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
301#define MII_KSZ9031RN_CLK_PAD_SKEW 8
302
303static int ksz9031_extended_write(struct phy_device *phydev,
304 u8 mode, u32 dev_addr, u32 regnum, u16 val)
305{
306 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
307 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
308 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
309 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
310}
311
312static int ksz9031_extended_read(struct phy_device *phydev,
313 u8 mode, u32 dev_addr, u32 regnum)
314{
315 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
316 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
317 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
318 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
319}
320
321static int ksz9031_of_load_skew_values(struct phy_device *phydev,
322 struct device_node *of_node,
323 u16 reg, size_t field_sz,
324 char *field[], u8 numfields)
325{
326 int val[4] = {-1, -2, -3, -4};
327 int matches = 0;
328 u16 mask;
329 u16 maxval;
330 u16 newval;
331 int i;
332
333 for (i = 0; i < numfields; i++)
334 if (!of_property_read_u32(of_node, field[i], val + i))
335 matches++;
336
337 if (!matches)
338 return 0;
339
340 if (matches < numfields)
341 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
342 else
343 newval = 0;
344
345 maxval = (field_sz == 4) ? 0xf : 0x1f;
346 for (i = 0; i < numfields; i++)
347 if (val[i] != -(i + 1)) {
348 mask = 0xffff;
349 mask ^= maxval << (field_sz * i);
350 newval = (newval & mask) |
351 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
352 << (field_sz * i));
353 }
354
355 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
356}
357
358static int ksz9031_config_init(struct phy_device *phydev)
359{
360 struct device *dev = &phydev->dev;
361 struct device_node *of_node = dev->of_node;
362 char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
363 char *rx_data_skews[4] = {
364 "rxd0-skew-ps", "rxd1-skew-ps",
365 "rxd2-skew-ps", "rxd3-skew-ps"
366 };
367 char *tx_data_skews[4] = {
368 "txd0-skew-ps", "txd1-skew-ps",
369 "txd2-skew-ps", "txd3-skew-ps"
370 };
371 char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
372
373 if (!of_node && dev->parent->of_node)
374 of_node = dev->parent->of_node;
375
376 if (of_node) {
377 ksz9031_of_load_skew_values(phydev, of_node,
378 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
379 clk_skews, 2);
380
381 ksz9031_of_load_skew_values(phydev, of_node,
382 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
383 control_skews, 2);
384
385 ksz9031_of_load_skew_values(phydev, of_node,
386 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
387 rx_data_skews, 4);
388
389 ksz9031_of_load_skew_values(phydev, of_node,
390 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
391 tx_data_skews, 4);
392 }
393 return 0;
394}
395
93272e07
JCPV		 396#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
397#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
398#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
32d73b14 399static int ksz8873mll_read_status(struct phy_device *phydev)
93272e07
JCPV		 400{
401 int regval;
402
403 /* dummy read */
404 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
405
406 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
407
408 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
409 phydev->duplex = DUPLEX_HALF;
410 else
411 phydev->duplex = DUPLEX_FULL;
412
413 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
414 phydev->speed = SPEED_10;
415 else
416 phydev->speed = SPEED_100;
417
418 phydev->link = 1;
419 phydev->pause = phydev->asym_pause = 0;
420
421 return 0;
422}
423
424static int ksz8873mll_config_aneg(struct phy_device *phydev)
425{
426 return 0;
427}
428
19936942
VB		 429/* This routine returns -1 as an indication to the caller that the
430 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
431 * MMD extended PHY registers.
432 */
433static int
434ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
435 int regnum)
436{
437 return -1;
438}
439
440/* This routine does nothing since the Micrel ksz9021 does not support
441 * standard IEEE MMD extended PHY registers.
442 */
443static void
444ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
445 int regnum, u32 val)
446{
447}
448
1fadee0c
SH		 449static int ksz8021_probe(struct phy_device *phydev)
450{
451 struct clk *clk;
452
453 clk = devm_clk_get(&phydev->dev, "rmii-ref");
454 if (!IS_ERR(clk)) {
455 unsigned long rate = clk_get_rate(clk);
456
457 if (rate > 24500000 && rate < 25500000) {
458 phydev->dev_flags |= MICREL_PHY_25MHZ_CLK;
459 } else if (rate > 49500000 && rate < 50500000) {
460 phydev->dev_flags |= MICREL_PHY_50MHZ_CLK;
461 } else {
462 dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate);
463 return -EINVAL;
464 }
465 }
466
467 return 0;
468}
469
d5bf9071
CH		 470static struct phy_driver ksphy_driver[] = {
471{
51f932c4
CD		 472 .phy_id = PHY_ID_KS8737,
473 .phy_id_mask = 0x00fffff0,
474 .name = "Micrel KS8737",
475 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
476 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
477 .config_init = kszphy_config_init,
478 .config_aneg = genphy_config_aneg,
479 .read_status = genphy_read_status,
480 .ack_interrupt = kszphy_ack_interrupt,
481 .config_intr = ks8737_config_intr,
1a5465f5
PV		 482 .suspend = genphy_suspend,
483 .resume = genphy_resume,
51f932c4 484 .driver = { .owner = THIS_MODULE,},
212ea99a
MV		 485}, {
486 .phy_id = PHY_ID_KSZ8021,
487 .phy_id_mask = 0x00ffffff,
7ab59dc1 488 .name = "Micrel KSZ8021 or KSZ8031",
212ea99a
MV		 489 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
490 SUPPORTED_Asym_Pause),
491 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1fadee0c 492 .probe = ksz8021_probe,
212ea99a
MV		 493 .config_init = ksz8021_config_init,
494 .config_aneg = genphy_config_aneg,
495 .read_status = genphy_read_status,
496 .ack_interrupt = kszphy_ack_interrupt,
497 .config_intr = kszphy_config_intr,
1a5465f5
PV		 498 .suspend = genphy_suspend,
499 .resume = genphy_resume,
212ea99a 500 .driver = { .owner = THIS_MODULE,},
b818d1a7
HP		 501}, {
502 .phy_id = PHY_ID_KSZ8031,
503 .phy_id_mask = 0x00ffffff,
504 .name = "Micrel KSZ8031",
505 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
506 SUPPORTED_Asym_Pause),
507 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1fadee0c 508 .probe = ksz8021_probe,
b818d1a7
HP		 509 .config_init = ksz8021_config_init,
510 .config_aneg = genphy_config_aneg,
511 .read_status = genphy_read_status,
512 .ack_interrupt = kszphy_ack_interrupt,
513 .config_intr = kszphy_config_intr,
1a5465f5
PV		 514 .suspend = genphy_suspend,
515 .resume = genphy_resume,
b818d1a7 516 .driver = { .owner = THIS_MODULE,},
d5bf9071 517}, {
510d573f 518 .phy_id = PHY_ID_KSZ8041,
51f932c4 519 .phy_id_mask = 0x00fffff0,
510d573f 520 .name = "Micrel KSZ8041",
51f932c4
CD		 521 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
522 | SUPPORTED_Asym_Pause),
523 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 524 .config_init = kszphy_config_init_led8041,
51f932c4
CD		 525 .config_aneg = genphy_config_aneg,
526 .read_status = genphy_read_status,
527 .ack_interrupt = kszphy_ack_interrupt,
528 .config_intr = kszphy_config_intr,
1a5465f5
PV		 529 .suspend = genphy_suspend,
530 .resume = genphy_resume,
51f932c4 531 .driver = { .owner = THIS_MODULE,},
4bd7b512
SS		 532}, {
533 .phy_id = PHY_ID_KSZ8041RNLI,
534 .phy_id_mask = 0x00fffff0,
535 .name = "Micrel KSZ8041RNLI",
536 .features = PHY_BASIC_FEATURES |
537 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
538 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 539 .config_init = kszphy_config_init_led8041,
4bd7b512
SS		 540 .config_aneg = genphy_config_aneg,
541 .read_status = genphy_read_status,
542 .ack_interrupt = kszphy_ack_interrupt,
543 .config_intr = kszphy_config_intr,
544 .suspend = genphy_suspend,
545 .resume = genphy_resume,
546 .driver = { .owner = THIS_MODULE,},
d5bf9071 547}, {
510d573f 548 .phy_id = PHY_ID_KSZ8051,
d0507009 549 .phy_id_mask = 0x00fffff0,
510d573f 550 .name = "Micrel KSZ8051",
51f932c4
CD		 551 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
552 | SUPPORTED_Asym_Pause),
553 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
d606ef3f 554 .config_init = ks8051_config_init,
d0507009
DC		 555 .config_aneg = genphy_config_aneg,
556 .read_status = genphy_read_status,
51f932c4
CD		 557 .ack_interrupt = kszphy_ack_interrupt,
558 .config_intr = kszphy_config_intr,
1a5465f5
PV		 559 .suspend = genphy_suspend,
560 .resume = genphy_resume,
d0507009 561 .driver = { .owner = THIS_MODULE,},
d5bf9071 562}, {
510d573f
MV		 563 .phy_id = PHY_ID_KSZ8001,
564 .name = "Micrel KSZ8001 or KS8721",
48d7d0ad 565 .phy_id_mask = 0x00ffffff,
51f932c4
CD		 566 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
567 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 568 .config_init = kszphy_config_init_led8041,
d0507009
DC		 569 .config_aneg = genphy_config_aneg,
570 .read_status = genphy_read_status,
51f932c4
CD		 571 .ack_interrupt = kszphy_ack_interrupt,
572 .config_intr = kszphy_config_intr,
1a5465f5
PV		 573 .suspend = genphy_suspend,
574 .resume = genphy_resume,
d0507009 575 .driver = { .owner = THIS_MODULE,},
7ab59dc1
DC		 576}, {
577 .phy_id = PHY_ID_KSZ8081,
578 .name = "Micrel KSZ8081 or KSZ8091",
579 .phy_id_mask = 0x00fffff0,
580 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
581 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
582 .config_init = kszphy_config_init,
583 .config_aneg = genphy_config_aneg,
584 .read_status = genphy_read_status,
585 .ack_interrupt = kszphy_ack_interrupt,
586 .config_intr = kszphy_config_intr,
1a5465f5
PV		 587 .suspend = genphy_suspend,
588 .resume = genphy_resume,
7ab59dc1
DC		 589 .driver = { .owner = THIS_MODULE,},
590}, {
591 .phy_id = PHY_ID_KSZ8061,
592 .name = "Micrel KSZ8061",
593 .phy_id_mask = 0x00fffff0,
594 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
595 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
596 .config_init = kszphy_config_init,
597 .config_aneg = genphy_config_aneg,
598 .read_status = genphy_read_status,
599 .ack_interrupt = kszphy_ack_interrupt,
600 .config_intr = kszphy_config_intr,
1a5465f5
PV		 601 .suspend = genphy_suspend,
602 .resume = genphy_resume,
7ab59dc1 603 .driver = { .owner = THIS_MODULE,},
d5bf9071 604}, {
d0507009 605 .phy_id = PHY_ID_KSZ9021,
48d7d0ad 606 .phy_id_mask = 0x000ffffe,
d0507009 607 .name = "Micrel KSZ9021 Gigabit PHY",
32fcafbc 608 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
51f932c4 609 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
954c3967 610 .config_init = ksz9021_config_init,
d0507009
DC		 611 .config_aneg = genphy_config_aneg,
612 .read_status = genphy_read_status,
51f932c4
CD		 613 .ack_interrupt = kszphy_ack_interrupt,
614 .config_intr = ksz9021_config_intr,
1a5465f5
PV		 615 .suspend = genphy_suspend,
616 .resume = genphy_resume,
19936942
VB		 617 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
618 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
d0507009 619 .driver = { .owner = THIS_MODULE, },
7ab59dc1
DC		 620}, {
621 .phy_id = PHY_ID_KSZ9031,
622 .phy_id_mask = 0x00fffff0,
623 .name = "Micrel KSZ9031 Gigabit PHY",
95e8b103 624 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
7ab59dc1 625 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
6e4b8273 626 .config_init = ksz9031_config_init,
7ab59dc1
DC		 627 .config_aneg = genphy_config_aneg,
628 .read_status = genphy_read_status,
629 .ack_interrupt = kszphy_ack_interrupt,
630 .config_intr = ksz9021_config_intr,
1a5465f5
PV		 631 .suspend = genphy_suspend,
632 .resume = genphy_resume,
7ab59dc1 633 .driver = { .owner = THIS_MODULE, },
93272e07
JCPV		 634}, {
635 .phy_id = PHY_ID_KSZ8873MLL,
636 .phy_id_mask = 0x00fffff0,
637 .name = "Micrel KSZ8873MLL Switch",
638 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
639 .flags = PHY_HAS_MAGICANEG,
640 .config_init = kszphy_config_init,
641 .config_aneg = ksz8873mll_config_aneg,
642 .read_status = ksz8873mll_read_status,
1a5465f5
PV		 643 .suspend = genphy_suspend,
644 .resume = genphy_resume,
93272e07 645 .driver = { .owner = THIS_MODULE, },
7ab59dc1
DC		 646}, {
647 .phy_id = PHY_ID_KSZ886X,
648 .phy_id_mask = 0x00fffff0,
649 .name = "Micrel KSZ886X Switch",
650 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
651 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
652 .config_init = kszphy_config_init,
653 .config_aneg = genphy_config_aneg,
654 .read_status = genphy_read_status,
1a5465f5
PV		 655 .suspend = genphy_suspend,
656 .resume = genphy_resume,
7ab59dc1 657 .driver = { .owner = THIS_MODULE, },
d5bf9071 658} };
d0507009
DC		 659
660static int __init ksphy_init(void)
661{
d5bf9071
CH		 662 return phy_drivers_register(ksphy_driver,
663 ARRAY_SIZE(ksphy_driver));
d0507009
DC		 664}
665
666static void __exit ksphy_exit(void)
667{
d5bf9071
CH		 668 phy_drivers_unregister(ksphy_driver,
669 ARRAY_SIZE(ksphy_driver));
d0507009
DC		 670}
671
672module_init(ksphy_init);
673module_exit(ksphy_exit);
674
675MODULE_DESCRIPTION("Micrel PHY driver");
676MODULE_AUTHOR("David J. Choi");
677MODULE_LICENSE("GPL");
52a60ed2 678
cf93c945 679static struct mdio_device_id __maybe_unused micrel_tbl[] = {
48d7d0ad 680 { PHY_ID_KSZ9021, 0x000ffffe },
7ab59dc1 681 { PHY_ID_KSZ9031, 0x00fffff0 },
510d573f 682 { PHY_ID_KSZ8001, 0x00ffffff },
51f932c4 683 { PHY_ID_KS8737, 0x00fffff0 },
212ea99a 684 { PHY_ID_KSZ8021, 0x00ffffff },
b818d1a7 685 { PHY_ID_KSZ8031, 0x00ffffff },
510d573f
MV		 686 { PHY_ID_KSZ8041, 0x00fffff0 },
687 { PHY_ID_KSZ8051, 0x00fffff0 },
7ab59dc1
DC		 688 { PHY_ID_KSZ8061, 0x00fffff0 },
689 { PHY_ID_KSZ8081, 0x00fffff0 },
93272e07 690 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
7ab59dc1 691 { PHY_ID_KSZ886X, 0x00fffff0 },
52a60ed2
DM		 692 { }
693};
694
695MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Linux 6.x block layer and io_uring tree(s)