[linux-2.6-block.git] / drivers / net / phy / micrel.c

/*
 * drivers/net/phy/micrel.c
 *
 * Driver for Micrel PHYs
 *
 * Author: David J. Choi
 *
 * Copyright (c) 2010-2013 Micrel, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Support : Micrel Phys:
 *		Giga phys: ksz9021, ksz9031
 *		100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
 *			   ksz8021, ksz8031, ksz8051,
 *			   ksz8081, ksz8091,
 *			   ksz8061,
 *		Switch : ksz8873, ksz886x
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>
#include <linux/of.h>

/* Operation Mode Strap Override */
#define MII_KSZPHY_OMSO				0x16
#define KSZPHY_OMSO_B_CAST_OFF			(1 << 9)
#define KSZPHY_OMSO_RMII_OVERRIDE		(1 << 1)
#define KSZPHY_OMSO_MII_OVERRIDE		(1 << 0)

/* general Interrupt control/status reg in vendor specific block. */
#define MII_KSZPHY_INTCS			0x1B
#define	KSZPHY_INTCS_JABBER			(1 << 15)
#define	KSZPHY_INTCS_RECEIVE_ERR		(1 << 14)
#define	KSZPHY_INTCS_PAGE_RECEIVE		(1 << 13)
#define	KSZPHY_INTCS_PARELLEL			(1 << 12)
#define	KSZPHY_INTCS_LINK_PARTNER_ACK		(1 << 11)
#define	KSZPHY_INTCS_LINK_DOWN			(1 << 10)
#define	KSZPHY_INTCS_REMOTE_FAULT		(1 << 9)
#define	KSZPHY_INTCS_LINK_UP			(1 << 8)
#define	KSZPHY_INTCS_ALL			(KSZPHY_INTCS_LINK_UP |\
						KSZPHY_INTCS_LINK_DOWN)

/* general PHY control reg in vendor specific block. */
#define	MII_KSZPHY_CTRL			0x1F
/* bitmap of PHY register to set interrupt mode */
#define KSZPHY_CTRL_INT_ACTIVE_HIGH		(1 << 9)
#define KSZ9021_CTRL_INT_ACTIVE_HIGH		(1 << 14)
#define KS8737_CTRL_INT_ACTIVE_HIGH		(1 << 14)
#define KSZ8051_RMII_50MHZ_CLK			(1 << 7)

/* Write/read to/from extended registers */
#define MII_KSZPHY_EXTREG                       0x0b
#define KSZPHY_EXTREG_WRITE                     0x8000

#define MII_KSZPHY_EXTREG_WRITE                 0x0c
#define MII_KSZPHY_EXTREG_READ                  0x0d

/* Extended registers */
#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
#define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
#define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106

#define PS_TO_REG				200

static int ksz_config_flags(struct phy_device *phydev)
{
	int regval;

	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
		regval = phy_read(phydev, MII_KSZPHY_CTRL);
		regval |= KSZ8051_RMII_50MHZ_CLK;
		return phy_write(phydev, MII_KSZPHY_CTRL, regval);
	}
	return 0;
}

static int kszphy_extended_write(struct phy_device *phydev,
                                 u32 regnum, u16 val)
{
	phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
	return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
}

static int kszphy_extended_read(struct phy_device *phydev,
                                 u32 regnum)
{
	phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
	return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
}

static int kszphy_ack_interrupt(struct phy_device *phydev)
{
	/* bit[7..0] int status, which is a read and clear register. */
	int rc;

	rc = phy_read(phydev, MII_KSZPHY_INTCS);

	return (rc < 0) ? rc : 0;
}

static int kszphy_set_interrupt(struct phy_device *phydev)
{
	int temp;
	temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
		KSZPHY_INTCS_ALL : 0;
	return phy_write(phydev, MII_KSZPHY_INTCS, temp);
}

static int kszphy_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int ksz9021_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int ks8737_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int kszphy_config_init(struct phy_device *phydev)
{
	return 0;
}

static int ksz8021_config_init(struct phy_device *phydev)
{
	int rc;
	const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
	phy_write(phydev, MII_KSZPHY_OMSO, val);
	rc = ksz_config_flags(phydev);
	return rc < 0 ? rc : 0;
}

static int ks8051_config_init(struct phy_device *phydev)
{
	int rc;

	rc = ksz_config_flags(phydev);
	return rc < 0 ? rc : 0;
}

static int ksz9021_load_values_from_of(struct phy_device *phydev,
				       struct device_node *of_node, u16 reg,
				       char *field1, char *field2,
				       char *field3, char *field4)
{
	int val1 = -1;
	int val2 = -2;
	int val3 = -3;
	int val4 = -4;
	int newval;
	int matches = 0;

	if (!of_property_read_u32(of_node, field1, &val1))
		matches++;

	if (!of_property_read_u32(of_node, field2, &val2))
		matches++;

	if (!of_property_read_u32(of_node, field3, &val3))
		matches++;

	if (!of_property_read_u32(of_node, field4, &val4))
		matches++;

	if (!matches)
		return 0;

	if (matches < 4)
		newval = kszphy_extended_read(phydev, reg);
	else
		newval = 0;

	if (val1 != -1)
		newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);

	if (val2 != -1)
		newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);

	if (val3 != -1)
		newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);

	if (val4 != -1)
		newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);

	return kszphy_extended_write(phydev, reg, newval);
}

static int ksz9021_config_init(struct phy_device *phydev)
{
	struct device *dev = &phydev->dev;
	struct device_node *of_node = dev->of_node;

	if (!of_node && dev->parent->of_node)
		of_node = dev->parent->of_node;

	if (of_node) {
		ksz9021_load_values_from_of(phydev, of_node,
				    MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
				    "txen-skew-ps", "txc-skew-ps",
				    "rxdv-skew-ps", "rxc-skew-ps");
		ksz9021_load_values_from_of(phydev, of_node,
				    MII_KSZPHY_RX_DATA_PAD_SKEW,
				    "rxd0-skew-ps", "rxd1-skew-ps",
				    "rxd2-skew-ps", "rxd3-skew-ps");
		ksz9021_load_values_from_of(phydev, of_node,
				    MII_KSZPHY_TX_DATA_PAD_SKEW,
				    "txd0-skew-ps", "txd1-skew-ps",
				    "txd2-skew-ps", "txd3-skew-ps");
	}
	return 0;
}

#define KSZ8873MLL_GLOBAL_CONTROL_4	0x06
#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX	(1 << 6)
#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED	(1 << 4)
static int ksz8873mll_read_status(struct phy_device *phydev)
{
	int regval;

	/* dummy read */
	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
		phydev->duplex = DUPLEX_HALF;
	else
		phydev->duplex = DUPLEX_FULL;

	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
		phydev->speed = SPEED_10;
	else
		phydev->speed = SPEED_100;

	phydev->link = 1;
	phydev->pause = phydev->asym_pause = 0;

	return 0;
}

static int ksz8873mll_config_aneg(struct phy_device *phydev)
{
	return 0;
}

static struct phy_driver ksphy_driver[] = {
{
	.phy_id		= PHY_ID_KS8737,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KS8737",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ks8737_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8021,
	.phy_id_mask	= 0x00ffffff,
	.name		= "Micrel KSZ8021 or KSZ8031",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ksz8021_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8031,
	.phy_id_mask	= 0x00ffffff,
	.name		= "Micrel KSZ8031",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ksz8021_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8041,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8041",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8051,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8051",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ks8051_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8001,
	.name		= "Micrel KSZ8001 or KS8721",
	.phy_id_mask	= 0x00ffffff,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8081,
	.name		= "Micrel KSZ8081 or KSZ8091",
	.phy_id_mask	= 0x00fffff0,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8061,
	.name		= "Micrel KSZ8061",
	.phy_id_mask	= 0x00fffff0,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ9021,
	.phy_id_mask	= 0x000ffffe,
	.name		= "Micrel KSZ9021 Gigabit PHY",
	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ksz9021_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ksz9021_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ9031,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ9031 Gigabit PHY",
	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ksz9021_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ8873MLL,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8873MLL Switch",
	.features	= (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG,
	.config_init	= kszphy_config_init,
	.config_aneg	= ksz8873mll_config_aneg,
	.read_status	= ksz8873mll_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ886X,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ886X Switch",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE, },
} };

static int __init ksphy_init(void)
{
	return phy_drivers_register(ksphy_driver,
		ARRAY_SIZE(ksphy_driver));
}

static void __exit ksphy_exit(void)
{
	phy_drivers_unregister(ksphy_driver,
		ARRAY_SIZE(ksphy_driver));
}

module_init(ksphy_init);
module_exit(ksphy_exit);

MODULE_DESCRIPTION("Micrel PHY driver");
MODULE_AUTHOR("David J. Choi");
MODULE_LICENSE("GPL");

static struct mdio_device_id __maybe_unused micrel_tbl[] = {
	{ PHY_ID_KSZ9021, 0x000ffffe },
	{ PHY_ID_KSZ9031, 0x00fffff0 },
	{ PHY_ID_KSZ8001, 0x00ffffff },
	{ PHY_ID_KS8737, 0x00fffff0 },
	{ PHY_ID_KSZ8021, 0x00ffffff },
	{ PHY_ID_KSZ8031, 0x00ffffff },
	{ PHY_ID_KSZ8041, 0x00fffff0 },
	{ PHY_ID_KSZ8051, 0x00fffff0 },
	{ PHY_ID_KSZ8061, 0x00fffff0 },
	{ PHY_ID_KSZ8081, 0x00fffff0 },
	{ PHY_ID_KSZ8873MLL, 0x00fffff0 },
	{ PHY_ID_KSZ886X, 0x00fffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Commit	Line	Data
d0507009 DC	1	/*
	2	* drivers/net/phy/micrel.c
	3	*
	4	* Driver for Micrel PHYs
	5	*
	6	* Author: David J. Choi
	7	*
7ab59dc1	8	* Copyright (c) 2010-2013 Micrel, Inc.
d0507009 DC	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*
7ab59dc1 DC	15	* Support : Micrel Phys:
	16	* Giga phys: ksz9021, ksz9031
	17	* 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
	18	* ksz8021, ksz8031, ksz8051,
	19	* ksz8081, ksz8091,
	20	* ksz8061,
	21	* Switch : ksz8873, ksz886x
d0507009 DC	22	*/
	23
	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/phy.h>
d606ef3f	27	#include <linux/micrel_phy.h>
954c3967	28	#include <linux/of.h>
d0507009	29
212ea99a MV	30	/* Operation Mode Strap Override */
	31	#define MII_KSZPHY_OMSO 0x16
	32	#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
	33	#define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
	34	#define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
	35
51f932c4 CD	36	/* general Interrupt control/status reg in vendor specific block. */
	37	#define MII_KSZPHY_INTCS 0x1B
	38	#define KSZPHY_INTCS_JABBER (1 << 15)
	39	#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
	40	#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
	41	#define KSZPHY_INTCS_PARELLEL (1 << 12)
	42	#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
	43	#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
	44	#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
	45	#define KSZPHY_INTCS_LINK_UP (1 << 8)
	46	#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP \|\
	47	KSZPHY_INTCS_LINK_DOWN)
	48
	49	/* general PHY control reg in vendor specific block. */
	50	#define MII_KSZPHY_CTRL 0x1F
	51	/* bitmap of PHY register to set interrupt mode */
	52	#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
	53	#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
	54	#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
d606ef3f	55	#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
51f932c4	56
954c3967 SC	57	/* Write/read to/from extended registers */
	58	#define MII_KSZPHY_EXTREG 0x0b
	59	#define KSZPHY_EXTREG_WRITE 0x8000
	60
	61	#define MII_KSZPHY_EXTREG_WRITE 0x0c
	62	#define MII_KSZPHY_EXTREG_READ 0x0d
	63
	64	/* Extended registers */
	65	#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
	66	#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
	67	#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
	68
	69	#define PS_TO_REG 200
	70
b6bb4dfc HP	71	static int ksz_config_flags(struct phy_device *phydev)
	72	{
	73	int regval;
	74
	75	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
	76	regval = phy_read(phydev, MII_KSZPHY_CTRL);
	77	regval \|= KSZ8051_RMII_50MHZ_CLK;
	78	return phy_write(phydev, MII_KSZPHY_CTRL, regval);
	79	}
	80	return 0;
	81	}
	82
954c3967 SC	83	static int kszphy_extended_write(struct phy_device *phydev,
	84	u32 regnum, u16 val)
	85	{
	86	phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE \| regnum);
	87	return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
	88	}
	89
	90	static int kszphy_extended_read(struct phy_device *phydev,
	91	u32 regnum)
	92	{
	93	phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
	94	return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
	95	}
	96
51f932c4 CD	97	static int kszphy_ack_interrupt(struct phy_device *phydev)
	98	{
	99	/* bit[7..0] int status, which is a read and clear register. */
	100	int rc;
	101
	102	rc = phy_read(phydev, MII_KSZPHY_INTCS);
	103
	104	return (rc < 0) ? rc : 0;
	105	}
	106
	107	static int kszphy_set_interrupt(struct phy_device *phydev)
	108	{
	109	int temp;
	110	temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
	111	KSZPHY_INTCS_ALL : 0;
	112	return phy_write(phydev, MII_KSZPHY_INTCS, temp);
	113	}
	114
	115	static int kszphy_config_intr(struct phy_device *phydev)
	116	{
	117	int temp, rc;
	118
	119	/* set the interrupt pin active low */
	120	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	121	temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
	122	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	123	rc = kszphy_set_interrupt(phydev);
	124	return rc < 0 ? rc : 0;
	125	}
	126
	127	static int ksz9021_config_intr(struct phy_device *phydev)
	128	{
	129	int temp, rc;
	130
	131	/* set the interrupt pin active low */
	132	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	133	temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
	134	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	135	rc = kszphy_set_interrupt(phydev);
	136	return rc < 0 ? rc : 0;
	137	}
	138
	139	static int ks8737_config_intr(struct phy_device *phydev)
	140	{
	141	int temp, rc;
	142
	143	/* set the interrupt pin active low */
	144	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	145	temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
	146	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	147	rc = kszphy_set_interrupt(phydev);
	148	return rc < 0 ? rc : 0;
	149	}
d0507009 DC	150
	151	static int kszphy_config_init(struct phy_device *phydev)
	152	{
	153	return 0;
	154	}
	155
212ea99a MV	156	static int ksz8021_config_init(struct phy_device *phydev)
212ea99a MV	157	{
b6bb4dfc	158	int rc;
212ea99a MV	159	const u16 val = KSZPHY_OMSO_B_CAST_OFF \| KSZPHY_OMSO_RMII_OVERRIDE;
212ea99a MV	160	phy_write(phydev, MII_KSZPHY_OMSO, val);
b6bb4dfc HP	161	rc = ksz_config_flags(phydev);
b6bb4dfc HP	162	return rc < 0 ? rc : 0;
212ea99a MV	163	}
212ea99a MV	164
d606ef3f BS	165	static int ks8051_config_init(struct phy_device *phydev)
d606ef3f BS	166	{
b6bb4dfc	167	int rc;
d606ef3f	168
b6bb4dfc HP	169	rc = ksz_config_flags(phydev);
b6bb4dfc HP	170	return rc < 0 ? rc : 0;
d606ef3f BS	171	}
d606ef3f BS	172
954c3967 SC	173	static int ksz9021_load_values_from_of(struct phy_device *phydev,
	174	struct device_node *of_node, u16 reg,
	175	char field1, char field2,
	176	char field3, char field4)
	177	{
	178	int val1 = -1;
	179	int val2 = -2;
	180	int val3 = -3;
	181	int val4 = -4;
	182	int newval;
	183	int matches = 0;
	184
	185	if (!of_property_read_u32(of_node, field1, &val1))
	186	matches++;
	187
	188	if (!of_property_read_u32(of_node, field2, &val2))
	189	matches++;
	190
	191	if (!of_property_read_u32(of_node, field3, &val3))
	192	matches++;
	193
	194	if (!of_property_read_u32(of_node, field4, &val4))
	195	matches++;
	196
	197	if (!matches)
	198	return 0;
	199
	200	if (matches < 4)
	201	newval = kszphy_extended_read(phydev, reg);
	202	else
	203	newval = 0;
	204
	205	if (val1 != -1)
	206	newval = ((newval & 0xfff0) \| ((val1 / PS_TO_REG) & 0xf) << 0);
	207
	208	if (val2 != -1)
	209	newval = ((newval & 0xff0f) \| ((val2 / PS_TO_REG) & 0xf) << 4);
	210
	211	if (val3 != -1)
	212	newval = ((newval & 0xf0ff) \| ((val3 / PS_TO_REG) & 0xf) << 8);
	213
	214	if (val4 != -1)
	215	newval = ((newval & 0x0fff) \| ((val4 / PS_TO_REG) & 0xf) << 12);
	216
	217	return kszphy_extended_write(phydev, reg, newval);
	218	}
	219
	220	static int ksz9021_config_init(struct phy_device *phydev)
	221	{
	222	struct device *dev = &phydev->dev;
	223	struct device_node *of_node = dev->of_node;
	224
	225	if (!of_node && dev->parent->of_node)
	226	of_node = dev->parent->of_node;
	227
	228	if (of_node) {
	229	ksz9021_load_values_from_of(phydev, of_node,
	230	MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
	231	"txen-skew-ps", "txc-skew-ps",
	232	"rxdv-skew-ps", "rxc-skew-ps");
	233	ksz9021_load_values_from_of(phydev, of_node,
	234	MII_KSZPHY_RX_DATA_PAD_SKEW,
	235	"rxd0-skew-ps", "rxd1-skew-ps",
	236	"rxd2-skew-ps", "rxd3-skew-ps");
237	ksz9021_load_values_from_of(phydev, of_node,
238	MII_KSZPHY_TX_DATA_PAD_SKEW,
239	"txd0-skew-ps", "txd1-skew-ps",
240	"txd2-skew-ps", "txd3-skew-ps");
241	}
242	return 0;
243	}
244
93272e07 JCPV	245	#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
	246	#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
	247	#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
32d73b14	248	static int ksz8873mll_read_status(struct phy_device *phydev)
93272e07 JCPV	249	{
	250	int regval;
	251
	252	/* dummy read */
	253	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
	254
	255	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
	256
	257	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
	258	phydev->duplex = DUPLEX_HALF;
	259	else
	260	phydev->duplex = DUPLEX_FULL;
	261
	262	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
	263	phydev->speed = SPEED_10;
	264	else
	265	phydev->speed = SPEED_100;
	266
	267	phydev->link = 1;
	268	phydev->pause = phydev->asym_pause = 0;
	269
	270	return 0;
	271	}
	272
	273	static int ksz8873mll_config_aneg(struct phy_device *phydev)
	274	{
	275	return 0;
	276	}
	277
d5bf9071 CH	278	static struct phy_driver ksphy_driver[] = {
d5bf9071 CH	279	{
51f932c4 CD	280	.phy_id = PHY_ID_KS8737,
	281	.phy_id_mask = 0x00fffff0,
	282	.name = "Micrel KS8737",
	283	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	284	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	285	.config_init = kszphy_config_init,
	286	.config_aneg = genphy_config_aneg,
	287	.read_status = genphy_read_status,
	288	.ack_interrupt = kszphy_ack_interrupt,
	289	.config_intr = ks8737_config_intr,
1a5465f5 PV	290	.suspend = genphy_suspend,
1a5465f5 PV	291	.resume = genphy_resume,
51f932c4	292	.driver = { .owner = THIS_MODULE,},
212ea99a MV	293	}, {
	294	.phy_id = PHY_ID_KSZ8021,
	295	.phy_id_mask = 0x00ffffff,
7ab59dc1	296	.name = "Micrel KSZ8021 or KSZ8031",
212ea99a MV	297	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause \|
	298	SUPPORTED_Asym_Pause),
	299	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	300	.config_init = ksz8021_config_init,
	301	.config_aneg = genphy_config_aneg,
	302	.read_status = genphy_read_status,
	303	.ack_interrupt = kszphy_ack_interrupt,
	304	.config_intr = kszphy_config_intr,
1a5465f5 PV	305	.suspend = genphy_suspend,
1a5465f5 PV	306	.resume = genphy_resume,
212ea99a	307	.driver = { .owner = THIS_MODULE,},
b818d1a7 HP	308	}, {
	309	.phy_id = PHY_ID_KSZ8031,
	310	.phy_id_mask = 0x00ffffff,
	311	.name = "Micrel KSZ8031",
	312	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause \|
	313	SUPPORTED_Asym_Pause),
	314	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	315	.config_init = ksz8021_config_init,
	316	.config_aneg = genphy_config_aneg,
	317	.read_status = genphy_read_status,
	318	.ack_interrupt = kszphy_ack_interrupt,
	319	.config_intr = kszphy_config_intr,
1a5465f5 PV	320	.suspend = genphy_suspend,
1a5465f5 PV	321	.resume = genphy_resume,
b818d1a7	322	.driver = { .owner = THIS_MODULE,},
d5bf9071	323	}, {
510d573f	324	.phy_id = PHY_ID_KSZ8041,
51f932c4	325	.phy_id_mask = 0x00fffff0,
510d573f	326	.name = "Micrel KSZ8041",
51f932c4 CD	327	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause
	328	\| SUPPORTED_Asym_Pause),
	329	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	330	.config_init = kszphy_config_init,
	331	.config_aneg = genphy_config_aneg,
	332	.read_status = genphy_read_status,
	333	.ack_interrupt = kszphy_ack_interrupt,
	334	.config_intr = kszphy_config_intr,
1a5465f5 PV	335	.suspend = genphy_suspend,
1a5465f5 PV	336	.resume = genphy_resume,
51f932c4	337	.driver = { .owner = THIS_MODULE,},
d5bf9071	338	}, {
510d573f	339	.phy_id = PHY_ID_KSZ8051,
d0507009	340	.phy_id_mask = 0x00fffff0,
510d573f	341	.name = "Micrel KSZ8051",
51f932c4 CD	342	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause
	343	\| SUPPORTED_Asym_Pause),
	344	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
d606ef3f	345	.config_init = ks8051_config_init,
d0507009 DC	346	.config_aneg = genphy_config_aneg,
d0507009 DC	347	.read_status = genphy_read_status,
51f932c4 CD	348	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	349	.config_intr = kszphy_config_intr,
1a5465f5 PV	350	.suspend = genphy_suspend,
1a5465f5 PV	351	.resume = genphy_resume,
d0507009	352	.driver = { .owner = THIS_MODULE,},
d5bf9071	353	}, {
510d573f MV	354	.phy_id = PHY_ID_KSZ8001,
510d573f MV	355	.name = "Micrel KSZ8001 or KS8721",
48d7d0ad	356	.phy_id_mask = 0x00ffffff,
51f932c4 CD	357	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
51f932c4 CD	358	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
d0507009 DC	359	.config_init = kszphy_config_init,
	360	.config_aneg = genphy_config_aneg,
	361	.read_status = genphy_read_status,
51f932c4 CD	362	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	363	.config_intr = kszphy_config_intr,
1a5465f5 PV	364	.suspend = genphy_suspend,
1a5465f5 PV	365	.resume = genphy_resume,
d0507009	366	.driver = { .owner = THIS_MODULE,},
7ab59dc1 DC	367	}, {
	368	.phy_id = PHY_ID_KSZ8081,
	369	.name = "Micrel KSZ8081 or KSZ8091",
	370	.phy_id_mask = 0x00fffff0,
	371	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	372	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	373	.config_init = kszphy_config_init,
	374	.config_aneg = genphy_config_aneg,
	375	.read_status = genphy_read_status,
	376	.ack_interrupt = kszphy_ack_interrupt,
	377	.config_intr = kszphy_config_intr,
1a5465f5 PV	378	.suspend = genphy_suspend,
1a5465f5 PV	379	.resume = genphy_resume,
7ab59dc1 DC	380	.driver = { .owner = THIS_MODULE,},
	381	}, {
	382	.phy_id = PHY_ID_KSZ8061,
	383	.name = "Micrel KSZ8061",
	384	.phy_id_mask = 0x00fffff0,
	385	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	386	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	387	.config_init = kszphy_config_init,
	388	.config_aneg = genphy_config_aneg,
	389	.read_status = genphy_read_status,
	390	.ack_interrupt = kszphy_ack_interrupt,
	391	.config_intr = kszphy_config_intr,
1a5465f5 PV	392	.suspend = genphy_suspend,
1a5465f5 PV	393	.resume = genphy_resume,
7ab59dc1	394	.driver = { .owner = THIS_MODULE,},
d5bf9071	395	}, {
d0507009	396	.phy_id = PHY_ID_KSZ9021,
48d7d0ad	397	.phy_id_mask = 0x000ffffe,
d0507009	398	.name = "Micrel KSZ9021 Gigabit PHY",
32fcafbc	399	.features = (PHY_GBIT_FEATURES \| SUPPORTED_Pause),
51f932c4	400	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
954c3967	401	.config_init = ksz9021_config_init,
d0507009 DC	402	.config_aneg = genphy_config_aneg,
d0507009 DC	403	.read_status = genphy_read_status,
51f932c4 CD	404	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	405	.config_intr = ksz9021_config_intr,
1a5465f5 PV	406	.suspend = genphy_suspend,
1a5465f5 PV	407	.resume = genphy_resume,
d0507009	408	.driver = { .owner = THIS_MODULE, },
7ab59dc1 DC	409	}, {
	410	.phy_id = PHY_ID_KSZ9031,
	411	.phy_id_mask = 0x00fffff0,
	412	.name = "Micrel KSZ9031 Gigabit PHY",
	413	.features = (PHY_GBIT_FEATURES \| SUPPORTED_Pause
	414	\| SUPPORTED_Asym_Pause),
	415	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	416	.config_init = kszphy_config_init,
	417	.config_aneg = genphy_config_aneg,
	418	.read_status = genphy_read_status,
	419	.ack_interrupt = kszphy_ack_interrupt,
	420	.config_intr = ksz9021_config_intr,
1a5465f5 PV	421	.suspend = genphy_suspend,
1a5465f5 PV	422	.resume = genphy_resume,
7ab59dc1	423	.driver = { .owner = THIS_MODULE, },
93272e07 JCPV	424	}, {
	425	.phy_id = PHY_ID_KSZ8873MLL,
	426	.phy_id_mask = 0x00fffff0,
	427	.name = "Micrel KSZ8873MLL Switch",
	428	.features = (SUPPORTED_Pause \| SUPPORTED_Asym_Pause),
	429	.flags = PHY_HAS_MAGICANEG,
	430	.config_init = kszphy_config_init,
	431	.config_aneg = ksz8873mll_config_aneg,
	432	.read_status = ksz8873mll_read_status,
1a5465f5 PV	433	.suspend = genphy_suspend,
1a5465f5 PV	434	.resume = genphy_resume,
93272e07	435	.driver = { .owner = THIS_MODULE, },
7ab59dc1 DC	436	}, {
	437	.phy_id = PHY_ID_KSZ886X,
	438	.phy_id_mask = 0x00fffff0,
	439	.name = "Micrel KSZ886X Switch",
	440	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	441	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	442	.config_init = kszphy_config_init,
	443	.config_aneg = genphy_config_aneg,
	444	.read_status = genphy_read_status,
1a5465f5 PV	445	.suspend = genphy_suspend,
1a5465f5 PV	446	.resume = genphy_resume,
7ab59dc1	447	.driver = { .owner = THIS_MODULE, },
d5bf9071	448	} };
d0507009 DC	449
	450	static int __init ksphy_init(void)
	451	{
d5bf9071 CH	452	return phy_drivers_register(ksphy_driver,
d5bf9071 CH	453	ARRAY_SIZE(ksphy_driver));
d0507009 DC	454	}
	455
	456	static void __exit ksphy_exit(void)
	457	{
d5bf9071 CH	458	phy_drivers_unregister(ksphy_driver,
d5bf9071 CH	459	ARRAY_SIZE(ksphy_driver));
d0507009 DC	460	}
	461
	462	module_init(ksphy_init);
	463	module_exit(ksphy_exit);
	464
	465	MODULE_DESCRIPTION("Micrel PHY driver");
	466	MODULE_AUTHOR("David J. Choi");
	467	MODULE_LICENSE("GPL");
52a60ed2	468
cf93c945	469	static struct mdio_device_id __maybe_unused micrel_tbl[] = {
48d7d0ad	470	{ PHY_ID_KSZ9021, 0x000ffffe },
7ab59dc1	471	{ PHY_ID_KSZ9031, 0x00fffff0 },
510d573f	472	{ PHY_ID_KSZ8001, 0x00ffffff },
51f932c4	473	{ PHY_ID_KS8737, 0x00fffff0 },
212ea99a	474	{ PHY_ID_KSZ8021, 0x00ffffff },
b818d1a7	475	{ PHY_ID_KSZ8031, 0x00ffffff },
510d573f MV	476	{ PHY_ID_KSZ8041, 0x00fffff0 },
510d573f MV	477	{ PHY_ID_KSZ8051, 0x00fffff0 },
7ab59dc1 DC	478	{ PHY_ID_KSZ8061, 0x00fffff0 },
7ab59dc1 DC	479	{ PHY_ID_KSZ8081, 0x00fffff0 },
93272e07	480	{ PHY_ID_KSZ8873MLL, 0x00fffff0 },
7ab59dc1	481	{ PHY_ID_KSZ886X, 0x00fffff0 },
52a60ed2 DM	482	{ }
	483	};
	484
	485	MODULE_DEVICE_TABLE(mdio, micrel_tbl);