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e2ec4581 SW |
1 | /* |
2 | * Bitbanged MDIO support. | |
3 | * | |
4 | * Author: Scott Wood <scottwood@freescale.com> | |
5 | * Copyright (c) 2007 Freescale Semiconductor | |
6 | * | |
7 | * Based on CPM2 MDIO code which is: | |
8 | * | |
9 | * Copyright (c) 2003 Intracom S.A. | |
10 | * by Pantelis Antoniou <panto@intracom.gr> | |
11 | * | |
12 | * 2005 (c) MontaVista Software, Inc. | |
13 | * Vitaly Bordug <vbordug@ru.mvista.com> | |
14 | * | |
15 | * This file is licensed under the terms of the GNU General Public License | |
16 | * version 2. This program is licensed "as is" without any warranty of any | |
17 | * kind, whether express or implied. | |
18 | */ | |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/mdio-bitbang.h> | |
e2ec4581 SW |
22 | #include <linux/types.h> |
23 | #include <linux/delay.h> | |
24 | ||
25 | #define MDIO_READ 1 | |
26 | #define MDIO_WRITE 0 | |
27 | ||
28 | #define MDIO_SETUP_TIME 10 | |
29 | #define MDIO_HOLD_TIME 10 | |
30 | ||
31 | /* Minimum MDC period is 400 ns, plus some margin for error. MDIO_DELAY | |
32 | * is done twice per period. | |
33 | */ | |
34 | #define MDIO_DELAY 250 | |
35 | ||
36 | /* The PHY may take up to 300 ns to produce data, plus some margin | |
37 | * for error. | |
38 | */ | |
39 | #define MDIO_READ_DELAY 350 | |
40 | ||
41 | /* MDIO must already be configured as output. */ | |
42 | static void mdiobb_send_bit(struct mdiobb_ctrl *ctrl, int val) | |
43 | { | |
44 | const struct mdiobb_ops *ops = ctrl->ops; | |
45 | ||
46 | ops->set_mdio_data(ctrl, val); | |
47 | ndelay(MDIO_DELAY); | |
48 | ops->set_mdc(ctrl, 1); | |
49 | ndelay(MDIO_DELAY); | |
50 | ops->set_mdc(ctrl, 0); | |
51 | } | |
52 | ||
53 | /* MDIO must already be configured as input. */ | |
54 | static int mdiobb_get_bit(struct mdiobb_ctrl *ctrl) | |
55 | { | |
56 | const struct mdiobb_ops *ops = ctrl->ops; | |
57 | ||
58 | ndelay(MDIO_DELAY); | |
59 | ops->set_mdc(ctrl, 1); | |
60 | ndelay(MDIO_READ_DELAY); | |
61 | ops->set_mdc(ctrl, 0); | |
62 | ||
63 | return ops->get_mdio_data(ctrl); | |
64 | } | |
65 | ||
66 | /* MDIO must already be configured as output. */ | |
67 | static void mdiobb_send_num(struct mdiobb_ctrl *ctrl, u16 val, int bits) | |
68 | { | |
69 | int i; | |
70 | ||
71 | for (i = bits - 1; i >= 0; i--) | |
72 | mdiobb_send_bit(ctrl, (val >> i) & 1); | |
73 | } | |
74 | ||
75 | /* MDIO must already be configured as input. */ | |
76 | static u16 mdiobb_get_num(struct mdiobb_ctrl *ctrl, int bits) | |
77 | { | |
78 | int i; | |
79 | u16 ret = 0; | |
80 | ||
81 | for (i = bits - 1; i >= 0; i--) { | |
82 | ret <<= 1; | |
83 | ret |= mdiobb_get_bit(ctrl); | |
84 | } | |
85 | ||
86 | return ret; | |
87 | } | |
88 | ||
89 | /* Utility to send the preamble, address, and | |
90 | * register (common to read and write). | |
91 | */ | |
92 | static void mdiobb_cmd(struct mdiobb_ctrl *ctrl, int read, u8 phy, u8 reg) | |
93 | { | |
94 | const struct mdiobb_ops *ops = ctrl->ops; | |
95 | int i; | |
96 | ||
97 | ops->set_mdio_dir(ctrl, 1); | |
98 | ||
99 | /* | |
100 | * Send a 32 bit preamble ('1's) with an extra '1' bit for good | |
101 | * measure. The IEEE spec says this is a PHY optional | |
102 | * requirement. The AMD 79C874 requires one after power up and | |
103 | * one after a MII communications error. This means that we are | |
104 | * doing more preambles than we need, but it is safer and will be | |
105 | * much more robust. | |
106 | */ | |
107 | ||
108 | for (i = 0; i < 32; i++) | |
109 | mdiobb_send_bit(ctrl, 1); | |
110 | ||
111 | /* send the start bit (01) and the read opcode (10) or write (10) */ | |
112 | mdiobb_send_bit(ctrl, 0); | |
113 | mdiobb_send_bit(ctrl, 1); | |
114 | mdiobb_send_bit(ctrl, read); | |
115 | mdiobb_send_bit(ctrl, !read); | |
116 | ||
117 | mdiobb_send_num(ctrl, phy, 5); | |
118 | mdiobb_send_num(ctrl, reg, 5); | |
119 | } | |
120 | ||
121 | ||
122 | static int mdiobb_read(struct mii_bus *bus, int phy, int reg) | |
123 | { | |
124 | struct mdiobb_ctrl *ctrl = bus->priv; | |
125 | int ret, i; | |
126 | ||
127 | mdiobb_cmd(ctrl, MDIO_READ, phy, reg); | |
128 | ctrl->ops->set_mdio_dir(ctrl, 0); | |
129 | ||
130 | /* check the turnaround bit: the PHY should be driving it to zero */ | |
131 | if (mdiobb_get_bit(ctrl) != 0) { | |
132 | /* PHY didn't drive TA low -- flush any bits it | |
133 | * may be trying to send. | |
134 | */ | |
135 | for (i = 0; i < 32; i++) | |
136 | mdiobb_get_bit(ctrl); | |
137 | ||
138 | return 0xffff; | |
139 | } | |
140 | ||
141 | ret = mdiobb_get_num(ctrl, 16); | |
142 | mdiobb_get_bit(ctrl); | |
143 | return ret; | |
144 | } | |
145 | ||
146 | static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) | |
147 | { | |
148 | struct mdiobb_ctrl *ctrl = bus->priv; | |
149 | ||
150 | mdiobb_cmd(ctrl, MDIO_WRITE, phy, reg); | |
151 | ||
152 | /* send the turnaround (10) */ | |
153 | mdiobb_send_bit(ctrl, 1); | |
154 | mdiobb_send_bit(ctrl, 0); | |
155 | ||
156 | mdiobb_send_num(ctrl, val, 16); | |
157 | ||
158 | ctrl->ops->set_mdio_dir(ctrl, 0); | |
159 | mdiobb_get_bit(ctrl); | |
160 | return 0; | |
161 | } | |
162 | ||
163 | struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl) | |
164 | { | |
165 | struct mii_bus *bus; | |
166 | ||
298cf9be | 167 | bus = mdiobus_alloc(); |
e2ec4581 SW |
168 | if (!bus) |
169 | return NULL; | |
170 | ||
171 | __module_get(ctrl->ops->owner); | |
172 | ||
173 | bus->read = mdiobb_read; | |
174 | bus->write = mdiobb_write; | |
175 | bus->priv = ctrl; | |
176 | ||
177 | return bus; | |
178 | } | |
e9911c2c | 179 | EXPORT_SYMBOL(alloc_mdio_bitbang); |
e2ec4581 SW |
180 | |
181 | void free_mdio_bitbang(struct mii_bus *bus) | |
182 | { | |
183 | struct mdiobb_ctrl *ctrl = bus->priv; | |
184 | ||
185 | module_put(ctrl->ops->owner); | |
298cf9be | 186 | mdiobus_free(bus); |
e2ec4581 | 187 | } |
e9911c2c | 188 | EXPORT_SYMBOL(free_mdio_bitbang); |
5a46236d RD |
189 | |
190 | MODULE_LICENSE("GPL"); |