[linux-block.git] / drivers / net / phy / marvell10g.c

/*
 * Marvell 10G 88x3310 PHY driver
 *
 * Based upon the ID registers, this PHY appears to be a mixture of IPs
 * from two different companies.
 *
 * There appears to be several different data paths through the PHY which
 * are automatically managed by the PHY.  The following has been determined
 * via observation and experimentation for a setup using single-lane Serdes:
 *
 *       SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
 *  10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
 *  10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
 *
 * With XAUI, observation shows:
 *
 *        XAUI PHYXS -- <appropriate PCS as above>
 *
 * and no switching of the host interface mode occurs.
 *
 * If both the fiber and copper ports are connected, the first to gain
 * link takes priority and the other port is completely locked out.
 */
#include <linux/phy.h>
#include <linux/marvell_phy.h>

enum {
	MV_PCS_BASE_T		= 0x0000,
	MV_PCS_BASE_R		= 0x1000,
	MV_PCS_1000BASEX	= 0x2000,

	MV_PCS_PAIRSWAP		= 0x8182,
	MV_PCS_PAIRSWAP_MASK	= 0x0003,
	MV_PCS_PAIRSWAP_AB	= 0x0002,
	MV_PCS_PAIRSWAP_NONE	= 0x0003,

	/* These registers appear at 0x800X and 0xa00X - the 0xa00X control
	 * registers appear to set themselves to the 0x800X when AN is
	 * restarted, but status registers appear readable from either.
	 */
	MV_AN_CTRL1000		= 0x8000, /* 1000base-T control register */
	MV_AN_STAT1000		= 0x8001, /* 1000base-T status register */

	/* This register appears to reflect the copper status */
	MV_AN_RESULT		= 0xa016,
	MV_AN_RESULT_SPD_10	= BIT(12),
	MV_AN_RESULT_SPD_100	= BIT(13),
	MV_AN_RESULT_SPD_1000	= BIT(14),
	MV_AN_RESULT_SPD_10000	= BIT(15),
};

static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
			 u16 mask, u16 bits)
{
	int old, val, ret;

	old = phy_read_mmd(phydev, devad, reg);
	if (old < 0)
		return old;

	val = (old & ~mask) | (bits & mask);
	if (val == old)
		return 0;

	ret = phy_write_mmd(phydev, devad, reg, val);

	return ret < 0 ? ret : 1;
}

static int mv3310_probe(struct phy_device *phydev)
{
	u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;

	if (!phydev->is_c45 ||
	    (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
		return -ENODEV;

	return 0;
}

/*
 * Resetting the MV88X3310 causes it to become non-responsive.  Avoid
 * setting the reset bit(s).
 */
static int mv3310_soft_reset(struct phy_device *phydev)
{
	return 0;
}

static int mv3310_config_init(struct phy_device *phydev)
{
	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
	u32 mask;
	int val;

	/* Check that the PHY interface type is compatible */
	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
	    phydev->interface != PHY_INTERFACE_MODE_XAUI &&
	    phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
	    phydev->interface != PHY_INTERFACE_MODE_10GKR)
		return -ENODEV;

	__set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
	__set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);

	if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
		val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
		if (val < 0)
			return val;

		if (val & MDIO_AN_STAT1_ABLE)
			__set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
	}

	val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
	if (val < 0)
		return val;

	/* Ethtool does not support the WAN mode bits */
	if (val & (MDIO_PMA_STAT2_10GBSR | MDIO_PMA_STAT2_10GBLR |
		   MDIO_PMA_STAT2_10GBER | MDIO_PMA_STAT2_10GBLX4 |
		   MDIO_PMA_STAT2_10GBSW | MDIO_PMA_STAT2_10GBLW |
		   MDIO_PMA_STAT2_10GBEW))
		__set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
	if (val & MDIO_PMA_STAT2_10GBSR)
		__set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported);
	if (val & MDIO_PMA_STAT2_10GBLR)
		__set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported);
	if (val & MDIO_PMA_STAT2_10GBER)
		__set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported);

	if (val & MDIO_PMA_STAT2_EXTABLE) {
		val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
		if (val < 0)
			return val;

		if (val & (MDIO_PMA_EXTABLE_10GBT | MDIO_PMA_EXTABLE_1000BT |
			   MDIO_PMA_EXTABLE_100BTX | MDIO_PMA_EXTABLE_10BT))
			__set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
		if (val & MDIO_PMA_EXTABLE_10GBLRM)
			__set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
		if (val & (MDIO_PMA_EXTABLE_10GBKX4 | MDIO_PMA_EXTABLE_10GBKR |
			   MDIO_PMA_EXTABLE_1000BKX))
			__set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, supported);
		if (val & MDIO_PMA_EXTABLE_10GBLRM)
			__set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
				  supported);
		if (val & MDIO_PMA_EXTABLE_10GBT)
			__set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
				  supported);
		if (val & MDIO_PMA_EXTABLE_10GBKX4)
			__set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
				  supported);
		if (val & MDIO_PMA_EXTABLE_10GBKR)
			__set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
				  supported);
		if (val & MDIO_PMA_EXTABLE_1000BT)
			__set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
				  supported);
		if (val & MDIO_PMA_EXTABLE_1000BKX)
			__set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
				  supported);
		if (val & MDIO_PMA_EXTABLE_100BTX)
			__set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
				  supported);
		if (val & MDIO_PMA_EXTABLE_10BT)
			__set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
				  supported);
	}

	if (!ethtool_convert_link_mode_to_legacy_u32(&mask, supported))
		dev_warn(&phydev->mdio.dev,
			 "PHY supports (%*pb) more modes than phylib supports, some modes not supported.\n",
			 __ETHTOOL_LINK_MODE_MASK_NBITS, supported);

	phydev->supported &= mask;
	phydev->advertising &= phydev->supported;

	return 0;
}

static int mv3310_config_aneg(struct phy_device *phydev)
{
	bool changed = false;
	u32 advertising;
	int ret;

	/* We don't support manual MDI control */
	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;

	if (phydev->autoneg == AUTONEG_DISABLE) {
		ret = genphy_c45_pma_setup_forced(phydev);
		if (ret < 0)
			return ret;

		return genphy_c45_an_disable_aneg(phydev);
	}

	phydev->advertising &= phydev->supported;
	advertising = phydev->advertising;

	ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
			    ADVERTISE_ALL | ADVERTISE_100BASE4 |
			    ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
			    ethtool_adv_to_mii_adv_t(advertising));
	if (ret < 0)
		return ret;
	if (ret > 0)
		changed = true;

	ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
			    ADVERTISE_1000FULL | ADVERTISE_1000HALF,
			    ethtool_adv_to_mii_ctrl1000_t(advertising));
	if (ret < 0)
		return ret;
	if (ret > 0)
		changed = true;

	/* 10G control register */
	ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
			    MDIO_AN_10GBT_CTRL_ADV10G,
			    advertising & ADVERTISED_10000baseT_Full ?
				MDIO_AN_10GBT_CTRL_ADV10G : 0);
	if (ret < 0)
		return ret;
	if (ret > 0)
		changed = true;

	if (changed)
		ret = genphy_c45_restart_aneg(phydev);

	return ret;
}

static int mv3310_aneg_done(struct phy_device *phydev)
{
	int val;

	val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
	if (val < 0)
		return val;

	if (val & MDIO_STAT1_LSTATUS)
		return 1;

	return genphy_c45_aneg_done(phydev);
}

/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
static int mv3310_read_10gbr_status(struct phy_device *phydev)
{
	phydev->link = 1;
	phydev->speed = SPEED_10000;
	phydev->duplex = DUPLEX_FULL;

	if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
		phydev->interface = PHY_INTERFACE_MODE_10GKR;

	return 0;
}

static int mv3310_read_status(struct phy_device *phydev)
{
	u32 mmd_mask = phydev->c45_ids.devices_in_package;
	int val;

	/* The vendor devads do not report link status.  Avoid the PHYXS
	 * instance as there are three, and its status depends on the MAC
	 * being appropriately configured for the negotiated speed.
	 */
	mmd_mask &= ~(BIT(MDIO_MMD_VEND1) | BIT(MDIO_MMD_VEND2) |
		      BIT(MDIO_MMD_PHYXS));

	phydev->speed = SPEED_UNKNOWN;
	phydev->duplex = DUPLEX_UNKNOWN;
	phydev->lp_advertising = 0;
	phydev->link = 0;
	phydev->pause = 0;
	phydev->asym_pause = 0;
	phydev->mdix = 0;

	val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
	if (val < 0)
		return val;

	if (val & MDIO_STAT1_LSTATUS)
		return mv3310_read_10gbr_status(phydev);

	val = genphy_c45_read_link(phydev, mmd_mask);
	if (val < 0)
		return val;

	phydev->link = val > 0 ? 1 : 0;

	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
	if (val < 0)
		return val;

	if (val & MDIO_AN_STAT1_COMPLETE) {
		val = genphy_c45_read_lpa(phydev);
		if (val < 0)
			return val;

		/* Read the link partner's 1G advertisment */
		val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
		if (val < 0)
			return val;

		phydev->lp_advertising |= mii_stat1000_to_ethtool_lpa_t(val);

		if (phydev->autoneg == AUTONEG_ENABLE) {
			val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_RESULT);
			if (val < 0)
				return val;

			if (val & MV_AN_RESULT_SPD_10000)
				phydev->speed = SPEED_10000;
			else if (val & MV_AN_RESULT_SPD_1000)
				phydev->speed = SPEED_1000;
			else if (val & MV_AN_RESULT_SPD_100)
				phydev->speed = SPEED_100;
			else if (val & MV_AN_RESULT_SPD_10)
				phydev->speed = SPEED_10;

			phydev->duplex = DUPLEX_FULL;
		}
	}

	if (phydev->autoneg != AUTONEG_ENABLE) {
		val = genphy_c45_read_pma(phydev);
		if (val < 0)
			return val;
	}

	if (phydev->speed == SPEED_10000) {
		val = genphy_c45_read_mdix(phydev);
		if (val < 0)
			return val;
	} else {
		val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP);
		if (val < 0)
			return val;

		switch (val & MV_PCS_PAIRSWAP_MASK) {
		case MV_PCS_PAIRSWAP_AB:
			phydev->mdix = ETH_TP_MDI_X;
			break;
		case MV_PCS_PAIRSWAP_NONE:
			phydev->mdix = ETH_TP_MDI;
			break;
		default:
			phydev->mdix = ETH_TP_MDI_INVALID;
			break;
		}
	}

	if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
	     phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
		/* The PHY automatically switches its serdes interface (and
		 * active PHYXS instance) between Cisco SGMII and 10GBase-KR
		 * modes according to the speed.  Florian suggests setting
		 * phydev->interface to communicate this to the MAC. Only do
		 * this if we are already in either SGMII or 10GBase-KR mode.
		 */
		if (phydev->speed == SPEED_10000)
			phydev->interface = PHY_INTERFACE_MODE_10GKR;
		else if (phydev->speed >= SPEED_10 &&
			 phydev->speed < SPEED_10000)
			phydev->interface = PHY_INTERFACE_MODE_SGMII;
	}

	return 0;
}

static struct phy_driver mv3310_drivers[] = {
	{
		.phy_id		= 0x002b09aa,
		.phy_id_mask	= MARVELL_PHY_ID_MASK,
		.name		= "mv88x3310",
		.features	= SUPPORTED_10baseT_Full |
				  SUPPORTED_100baseT_Full |
				  SUPPORTED_1000baseT_Full |
				  SUPPORTED_Autoneg |
				  SUPPORTED_TP |
				  SUPPORTED_FIBRE |
				  SUPPORTED_10000baseT_Full |
				  SUPPORTED_Backplane,
		.probe		= mv3310_probe,
		.soft_reset	= mv3310_soft_reset,
		.config_init	= mv3310_config_init,
		.config_aneg	= mv3310_config_aneg,
		.aneg_done	= mv3310_aneg_done,
		.read_status	= mv3310_read_status,
	},
};

module_phy_driver(mv3310_drivers);

static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
	{ 0x002b09aa, MARVELL_PHY_ID_MASK },
	{ },
};
MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
MODULE_LICENSE("GPL");
Commit	Line	Data
20b2af32 RK	1	/*
	2	* Marvell 10G 88x3310 PHY driver
	3	*
	4	* Based upon the ID registers, this PHY appears to be a mixture of IPs
	5	* from two different companies.
	6	*
	7	* There appears to be several different data paths through the PHY which
	8	* are automatically managed by the PHY. The following has been determined
05ca1b32	9	* via observation and experimentation for a setup using single-lane Serdes:
20b2af32 RK	10	*
	11	* SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
	12	* 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
	13	* 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
	14	*
05ca1b32 RK	15	* With XAUI, observation shows:
	16	*
	17	* XAUI PHYXS -- <appropriate PCS as above>
	18	*
	19	* and no switching of the host interface mode occurs.
	20	*
20b2af32 RK	21	* If both the fiber and copper ports are connected, the first to gain
	22	* link takes priority and the other port is completely locked out.
	23	*/
	24	#include <linux/phy.h>
952b6b3b	25	#include <linux/marvell_phy.h>
20b2af32 RK	26
	27	enum {
	28	MV_PCS_BASE_T = 0x0000,
	29	MV_PCS_BASE_R = 0x1000,
	30	MV_PCS_1000BASEX = 0x2000,
	31
ea4efe25 RK	32	MV_PCS_PAIRSWAP = 0x8182,
	33	MV_PCS_PAIRSWAP_MASK = 0x0003,
	34	MV_PCS_PAIRSWAP_AB = 0x0002,
	35	MV_PCS_PAIRSWAP_NONE = 0x0003,
	36
20b2af32 RK	37	/* These registers appear at 0x800X and 0xa00X - the 0xa00X control
	38	* registers appear to set themselves to the 0x800X when AN is
	39	* restarted, but status registers appear readable from either.
	40	*/
	41	MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
	42	MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
	43
	44	/* This register appears to reflect the copper status */
	45	MV_AN_RESULT = 0xa016,
	46	MV_AN_RESULT_SPD_10 = BIT(12),
	47	MV_AN_RESULT_SPD_100 = BIT(13),
	48	MV_AN_RESULT_SPD_1000 = BIT(14),
	49	MV_AN_RESULT_SPD_10000 = BIT(15),
	50	};
	51
	52	static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
	53	u16 mask, u16 bits)
	54	{
	55	int old, val, ret;
	56
	57	old = phy_read_mmd(phydev, devad, reg);
	58	if (old < 0)
	59	return old;
	60
	61	val = (old & ~mask) \| (bits & mask);
	62	if (val == old)
	63	return 0;
	64
	65	ret = phy_write_mmd(phydev, devad, reg, val);
	66
	67	return ret < 0 ? ret : 1;
	68	}
	69
	70	static int mv3310_probe(struct phy_device *phydev)
	71	{
	72	u32 mmd_mask = MDIO_DEVS_PMAPMD \| MDIO_DEVS_AN;
	73
	74	if (!phydev->is_c45 \|\|
	75	(phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
	76	return -ENODEV;
	77
	78	return 0;
	79	}
	80
	81	/*
	82	* Resetting the MV88X3310 causes it to become non-responsive. Avoid
	83	* setting the reset bit(s).
	84	*/
	85	static int mv3310_soft_reset(struct phy_device *phydev)
	86	{
	87	return 0;
	88	}
	89
	90	static int mv3310_config_init(struct phy_device *phydev)
	91	{
	92	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
	93	u32 mask;
	94	int val;
	95
	96	/* Check that the PHY interface type is compatible */
	97	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
20b2af32 RK	98	phydev->interface != PHY_INTERFACE_MODE_XAUI &&
	99	phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
	100	phydev->interface != PHY_INTERFACE_MODE_10GKR)
	101	return -ENODEV;
	102
	103	__set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
	104	__set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
	105
	106	if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
	107	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
	108	if (val < 0)
	109	return val;
	110
	111	if (val & MDIO_AN_STAT1_ABLE)
	112	__set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
	113	}
	114
	115	val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
	116	if (val < 0)
	117	return val;
	118
	119	/* Ethtool does not support the WAN mode bits */
	120	if (val & (MDIO_PMA_STAT2_10GBSR \| MDIO_PMA_STAT2_10GBLR \|
	121	MDIO_PMA_STAT2_10GBER \| MDIO_PMA_STAT2_10GBLX4 \|
	122	MDIO_PMA_STAT2_10GBSW \| MDIO_PMA_STAT2_10GBLW \|
	123	MDIO_PMA_STAT2_10GBEW))
	124	__set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
	125	if (val & MDIO_PMA_STAT2_10GBSR)
	126	__set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported);
	127	if (val & MDIO_PMA_STAT2_10GBLR)
	128	__set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported);
	129	if (val & MDIO_PMA_STAT2_10GBER)
	130	__set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported);
	131
	132	if (val & MDIO_PMA_STAT2_EXTABLE) {
	133	val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
	134	if (val < 0)
	135	return val;
	136
	137	if (val & (MDIO_PMA_EXTABLE_10GBT \| MDIO_PMA_EXTABLE_1000BT \|
	138	MDIO_PMA_EXTABLE_100BTX \| MDIO_PMA_EXTABLE_10BT))
	139	__set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
	140	if (val & MDIO_PMA_EXTABLE_10GBLRM)
	141	__set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
	142	if (val & (MDIO_PMA_EXTABLE_10GBKX4 \| MDIO_PMA_EXTABLE_10GBKR \|
	143	MDIO_PMA_EXTABLE_1000BKX))
	144	__set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, supported);
	145	if (val & MDIO_PMA_EXTABLE_10GBLRM)
	146	__set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
	147	supported);
	148	if (val & MDIO_PMA_EXTABLE_10GBT)
	149	__set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
	150	supported);
	151	if (val & MDIO_PMA_EXTABLE_10GBKX4)
	152	__set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
	153	supported);
	154	if (val & MDIO_PMA_EXTABLE_10GBKR)
	155	__set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
	156	supported);
	157	if (val & MDIO_PMA_EXTABLE_1000BT)
	158	__set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
	159	supported);
	160	if (val & MDIO_PMA_EXTABLE_1000BKX)
	161	__set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
162	supported);
163	if (val & MDIO_PMA_EXTABLE_100BTX)
164	__set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
165	supported);
166	if (val & MDIO_PMA_EXTABLE_10BT)
167	__set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
168	supported);
169	}
170
171	if (!ethtool_convert_link_mode_to_legacy_u32(&mask, supported))
172	dev_warn(&phydev->mdio.dev,
173	"PHY supports (%*pb) more modes than phylib supports, some modes not supported.\n",
174	__ETHTOOL_LINK_MODE_MASK_NBITS, supported);
175
176	phydev->supported &= mask;
177	phydev->advertising &= phydev->supported;
178
179	return 0;
180	}
181
182	static int mv3310_config_aneg(struct phy_device *phydev)
183	{
184	bool changed = false;
185	u32 advertising;
186	int ret;
187
ea4efe25 RK	188	/* We don't support manual MDI control */
	189	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
	190
20b2af32 RK	191	if (phydev->autoneg == AUTONEG_DISABLE) {
	192	ret = genphy_c45_pma_setup_forced(phydev);
	193	if (ret < 0)
	194	return ret;
	195
	196	return genphy_c45_an_disable_aneg(phydev);
	197	}
	198
	199	phydev->advertising &= phydev->supported;
	200	advertising = phydev->advertising;
	201
	202	ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
	203	ADVERTISE_ALL \| ADVERTISE_100BASE4 \|
	204	ADVERTISE_PAUSE_CAP \| ADVERTISE_PAUSE_ASYM,
	205	ethtool_adv_to_mii_adv_t(advertising));
	206	if (ret < 0)
	207	return ret;
	208	if (ret > 0)
	209	changed = true;
	210
	211	ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
	212	ADVERTISE_1000FULL \| ADVERTISE_1000HALF,
	213	ethtool_adv_to_mii_ctrl1000_t(advertising));
	214	if (ret < 0)
	215	return ret;
	216	if (ret > 0)
	217	changed = true;
	218
	219	/* 10G control register */
	220	ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
	221	MDIO_AN_10GBT_CTRL_ADV10G,
	222	advertising & ADVERTISED_10000baseT_Full ?
	223	MDIO_AN_10GBT_CTRL_ADV10G : 0);
	224	if (ret < 0)
	225	return ret;
	226	if (ret > 0)
	227	changed = true;
	228
	229	if (changed)
	230	ret = genphy_c45_restart_aneg(phydev);
	231
	232	return ret;
	233	}
	234
	235	static int mv3310_aneg_done(struct phy_device *phydev)
	236	{
	237	int val;
	238
	239	val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
	240	if (val < 0)
	241	return val;
	242
	243	if (val & MDIO_STAT1_LSTATUS)
	244	return 1;
	245
	246	return genphy_c45_aneg_done(phydev);
	247	}
	248
	249	/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
	250	static int mv3310_read_10gbr_status(struct phy_device *phydev)
	251	{
	252	phydev->link = 1;
	253	phydev->speed = SPEED_10000;
	254	phydev->duplex = DUPLEX_FULL;
255
256	if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
257	phydev->interface = PHY_INTERFACE_MODE_10GKR;
258
259	return 0;
260	}
261
262	static int mv3310_read_status(struct phy_device *phydev)
263	{
264	u32 mmd_mask = phydev->c45_ids.devices_in_package;
265	int val;
266
267	/* The vendor devads do not report link status. Avoid the PHYXS
268	* instance as there are three, and its status depends on the MAC
269	* being appropriately configured for the negotiated speed.
270	*/
271	mmd_mask &= ~(BIT(MDIO_MMD_VEND1) \| BIT(MDIO_MMD_VEND2) \|
272	BIT(MDIO_MMD_PHYXS));
273
274	phydev->speed = SPEED_UNKNOWN;
275	phydev->duplex = DUPLEX_UNKNOWN;
276	phydev->lp_advertising = 0;
277	phydev->link = 0;
278	phydev->pause = 0;
279	phydev->asym_pause = 0;
ea4efe25	280	phydev->mdix = 0;
20b2af32 RK	281
	282	val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
	283	if (val < 0)
	284	return val;
	285
	286	if (val & MDIO_STAT1_LSTATUS)
	287	return mv3310_read_10gbr_status(phydev);
	288
	289	val = genphy_c45_read_link(phydev, mmd_mask);
	290	if (val < 0)
	291	return val;
	292
	293	phydev->link = val > 0 ? 1 : 0;
	294
	295	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
	296	if (val < 0)
	297	return val;
	298
	299	if (val & MDIO_AN_STAT1_COMPLETE) {
	300	val = genphy_c45_read_lpa(phydev);
	301	if (val < 0)
	302	return val;
	303
	304	/* Read the link partner's 1G advertisment */
	305	val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
	306	if (val < 0)
	307	return val;
	308
	309	phydev->lp_advertising \|= mii_stat1000_to_ethtool_lpa_t(val);
	310
	311	if (phydev->autoneg == AUTONEG_ENABLE) {
	312	val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_RESULT);
	313	if (val < 0)
	314	return val;
	315
	316	if (val & MV_AN_RESULT_SPD_10000)
	317	phydev->speed = SPEED_10000;
	318	else if (val & MV_AN_RESULT_SPD_1000)
	319	phydev->speed = SPEED_1000;
	320	else if (val & MV_AN_RESULT_SPD_100)
	321	phydev->speed = SPEED_100;
	322	else if (val & MV_AN_RESULT_SPD_10)
	323	phydev->speed = SPEED_10;
	324
	325	phydev->duplex = DUPLEX_FULL;
	326	}
	327	}
	328
	329	if (phydev->autoneg != AUTONEG_ENABLE) {
	330	val = genphy_c45_read_pma(phydev);
	331	if (val < 0)
	332	return val;
	333	}
	334
ea4efe25 RK	335	if (phydev->speed == SPEED_10000) {
	336	val = genphy_c45_read_mdix(phydev);
	337	if (val < 0)
	338	return val;
	339	} else {
	340	val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP);
	341	if (val < 0)
	342	return val;
	343
	344	switch (val & MV_PCS_PAIRSWAP_MASK) {
	345	case MV_PCS_PAIRSWAP_AB:
	346	phydev->mdix = ETH_TP_MDI_X;
	347	break;
	348	case MV_PCS_PAIRSWAP_NONE:
	349	phydev->mdix = ETH_TP_MDI;
	350	break;
	351	default:
	352	phydev->mdix = ETH_TP_MDI_INVALID;
	353	break;
	354	}
	355	}
	356
20b2af32 RK	357	if ((phydev->interface == PHY_INTERFACE_MODE_SGMII \|\|
	358	phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
	359	/* The PHY automatically switches its serdes interface (and
	360	* active PHYXS instance) between Cisco SGMII and 10GBase-KR
	361	* modes according to the speed. Florian suggests setting
	362	* phydev->interface to communicate this to the MAC. Only do
	363	* this if we are already in either SGMII or 10GBase-KR mode.
	364	*/
	365	if (phydev->speed == SPEED_10000)
	366	phydev->interface = PHY_INTERFACE_MODE_10GKR;
	367	else if (phydev->speed >= SPEED_10 &&
	368	phydev->speed < SPEED_10000)
	369	phydev->interface = PHY_INTERFACE_MODE_SGMII;
	370	}
	371
	372	return 0;
	373	}
	374
	375	static struct phy_driver mv3310_drivers[] = {
	376	{
	377	.phy_id = 0x002b09aa,
952b6b3b	378	.phy_id_mask = MARVELL_PHY_ID_MASK,
20b2af32 RK	379	.name = "mv88x3310",
	380	.features = SUPPORTED_10baseT_Full \|
	381	SUPPORTED_100baseT_Full \|
	382	SUPPORTED_1000baseT_Full \|
	383	SUPPORTED_Autoneg \|
	384	SUPPORTED_TP \|
	385	SUPPORTED_FIBRE \|
	386	SUPPORTED_10000baseT_Full \|
	387	SUPPORTED_Backplane,
	388	.probe = mv3310_probe,
	389	.soft_reset = mv3310_soft_reset,
	390	.config_init = mv3310_config_init,
	391	.config_aneg = mv3310_config_aneg,
	392	.aneg_done = mv3310_aneg_done,
	393	.read_status = mv3310_read_status,
	394	},
	395	};
	396
	397	module_phy_driver(mv3310_drivers);
	398
	399	static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
952b6b3b	400	{ 0x002b09aa, MARVELL_PHY_ID_MASK },
20b2af32 RK	401	{ },
	402	};
	403	MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
	404	MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
	405	MODULE_LICENSE("GPL");